internal.h 4.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _WCD938X_INTERNAL_H
  6. #define _WCD938X_INTERNAL_H
  7. #include <asoc/wcd-mbhc-v2.h>
  8. #include <asoc/wcd-irq.h>
  9. #include <asoc/wcd-clsh.h>
  10. #include "wcd938x-mbhc.h"
  11. #define WCD938X_MAX_MICBIAS 4
  12. /* Convert from vout ctl to micbias voltage in mV */
  13. #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
  14. #define MAX_PORT 8
  15. #define MAX_CH_PER_PORT 8
  16. #define TX_ADC_MAX 4
  17. enum {
  18. TX_HDR12 = 0,
  19. TX_HDR34,
  20. TX_HDR_MAX,
  21. };
  22. extern struct regmap_config wcd938x_regmap_config;
  23. struct codec_port_info {
  24. u32 slave_port_type;
  25. u32 master_port_type;
  26. u32 ch_mask;
  27. u32 num_ch;
  28. u32 ch_rate;
  29. };
  30. struct wcd938x_priv {
  31. struct device *dev;
  32. int variant;
  33. struct snd_soc_component *component;
  34. struct device_node *rst_np;
  35. struct regmap *regmap;
  36. struct swr_device *rx_swr_dev;
  37. struct swr_device *tx_swr_dev;
  38. s32 micb_ref[WCD938X_MAX_MICBIAS];
  39. s32 pullup_ref[WCD938X_MAX_MICBIAS];
  40. struct fw_info *fw_data;
  41. struct device_node *wcd_rst_np;
  42. struct mutex micb_lock;
  43. s32 dmic_0_1_clk_cnt;
  44. s32 dmic_2_3_clk_cnt;
  45. s32 dmic_4_5_clk_cnt;
  46. s32 dmic_6_7_clk_cnt;
  47. int hdr_en[TX_HDR_MAX];
  48. /* class h specific info */
  49. struct wcd_clsh_cdc_info clsh_info;
  50. /* mbhc module */
  51. struct wcd938x_mbhc *mbhc;
  52. u32 hph_mode;
  53. u32 tx_mode[TX_ADC_MAX];
  54. bool comp1_enable;
  55. bool comp2_enable;
  56. bool ldoh;
  57. struct irq_domain *virq;
  58. struct wcd_irq_info irq_info;
  59. u32 rx_clk_cnt;
  60. int num_irq_regs;
  61. /* to track the status */
  62. unsigned long status_mask;
  63. u8 num_tx_ports;
  64. u8 num_rx_ports;
  65. struct codec_port_info
  66. tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  67. struct codec_port_info
  68. rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  69. struct regulator_bulk_data *supplies;
  70. struct notifier_block nblock;
  71. /* wcd callback to bolero */
  72. void *handle;
  73. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  74. int (*register_notifier)(void *handle,
  75. struct notifier_block *nblock,
  76. bool enable);
  77. int (*wakeup)(void *handle, bool enable);
  78. u32 version;
  79. /* Entry for version info */
  80. struct snd_info_entry *entry;
  81. struct snd_info_entry *version_entry;
  82. struct snd_info_entry *variant_entry;
  83. int flyback_cur_det_disable;
  84. int ear_rx_path;
  85. };
  86. struct wcd938x_micbias_setting {
  87. u8 ldoh_v;
  88. u32 cfilt1_mv;
  89. u32 micb1_mv;
  90. u32 micb2_mv;
  91. u32 micb3_mv;
  92. u32 micb4_mv;
  93. u8 bias1_cfilt_sel;
  94. };
  95. struct wcd938x_pdata {
  96. struct device_node *rst_np;
  97. struct device_node *rx_slave;
  98. struct device_node *tx_slave;
  99. struct wcd938x_micbias_setting micbias;
  100. struct cdc_regulator *regulator;
  101. int num_supplies;
  102. };
  103. struct wcd_ctrl_platform_data {
  104. void *handle;
  105. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  106. int (*register_notifier)(void *handle,
  107. struct notifier_block *nblock,
  108. bool enable);
  109. };
  110. enum {
  111. WCD_RX1,
  112. WCD_RX2,
  113. WCD_RX3
  114. };
  115. enum {
  116. BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR = 1,
  117. BOLERO_WCD_EVT_PA_OFF_PRE_SSR,
  118. BOLERO_WCD_EVT_SSR_DOWN,
  119. BOLERO_WCD_EVT_SSR_UP,
  120. BOLERO_WCD_EVT_CLK_NOTIFY,
  121. };
  122. enum {
  123. WCD_BOLERO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
  124. WCD_BOLERO_EVT_IMPED_TRUE, /* for imped true */
  125. WCD_BOLERO_EVT_IMPED_FALSE, /* for imped false */
  126. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  127. };
  128. enum {
  129. /* INTR_CTRL_INT_MASK_0 */
  130. WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET = 0,
  131. WCD938X_IRQ_MBHC_BUTTON_PRESS_DET,
  132. WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
  133. WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
  134. WCD938X_IRQ_MBHC_SW_DET,
  135. WCD938X_IRQ_HPHR_OCP_INT,
  136. WCD938X_IRQ_HPHR_CNP_INT,
  137. WCD938X_IRQ_HPHL_OCP_INT,
  138. /* INTR_CTRL_INT_MASK_1 */
  139. WCD938X_IRQ_HPHL_CNP_INT,
  140. WCD938X_IRQ_EAR_CNP_INT,
  141. WCD938X_IRQ_EAR_SCD_INT,
  142. WCD938X_IRQ_AUX_CNP_INT,
  143. WCD938X_IRQ_AUX_SCD_INT,
  144. WCD938X_IRQ_HPHL_PDM_WD_INT,
  145. WCD938X_IRQ_HPHR_PDM_WD_INT,
  146. WCD938X_IRQ_AUX_PDM_WD_INT,
  147. /* INTR_CTRL_INT_MASK_2 */
  148. WCD938X_IRQ_LDORT_SCD_INT,
  149. WCD938X_IRQ_MBHC_MOISTURE_INT,
  150. WCD938X_IRQ_HPHL_SURGE_DET_INT,
  151. WCD938X_IRQ_HPHR_SURGE_DET_INT,
  152. WCD938X_NUM_IRQS,
  153. };
  154. extern struct wcd938x_mbhc *wcd938x_soc_get_mbhc(
  155. struct snd_soc_component *component);
  156. extern int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  157. int volt, int micb_num);
  158. extern int wcd938x_get_micb_vout_ctl_val(u32 micb_mv);
  159. extern int wcd938x_micbias_control(struct snd_soc_component *component,
  160. int micb_num, int req, bool is_dapm);
  161. #endif /* _WCD938X_INTERNAL_H */