tcl_gse_cmd.h 10 KB

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  1. /*
  2. * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _TCL_GSE_CMD_H_
  17. #define _TCL_GSE_CMD_H_
  18. #define NUM_OF_DWORDS_TCL_GSE_CMD 8
  19. struct tcl_gse_cmd {
  20. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  21. uint32_t control_buffer_addr_31_0 : 32;
  22. uint32_t control_buffer_addr_39_32 : 8,
  23. gse_ctrl : 4,
  24. gse_sel : 1,
  25. status_destination_ring_id : 1,
  26. swap : 1,
  27. index_search_en : 1,
  28. cache_set_num : 4,
  29. reserved_1a : 12;
  30. uint32_t tcl_cmd_type : 1,
  31. reserved_2a : 31;
  32. uint32_t cmd_meta_data_31_0 : 32;
  33. uint32_t cmd_meta_data_63_32 : 32;
  34. uint32_t reserved_5a : 32;
  35. uint32_t reserved_6a : 32;
  36. uint32_t reserved_7a : 20,
  37. ring_id : 8,
  38. looping_count : 4;
  39. #else
  40. uint32_t control_buffer_addr_31_0 : 32;
  41. uint32_t reserved_1a : 12,
  42. cache_set_num : 4,
  43. index_search_en : 1,
  44. swap : 1,
  45. status_destination_ring_id : 1,
  46. gse_sel : 1,
  47. gse_ctrl : 4,
  48. control_buffer_addr_39_32 : 8;
  49. uint32_t reserved_2a : 31,
  50. tcl_cmd_type : 1;
  51. uint32_t cmd_meta_data_31_0 : 32;
  52. uint32_t cmd_meta_data_63_32 : 32;
  53. uint32_t reserved_5a : 32;
  54. uint32_t reserved_6a : 32;
  55. uint32_t looping_count : 4,
  56. ring_id : 8,
  57. reserved_7a : 20;
  58. #endif
  59. };
  60. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
  61. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0
  62. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31
  63. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
  64. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
  65. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0
  66. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7
  67. #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
  68. #define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004
  69. #define TCL_GSE_CMD_GSE_CTRL_LSB 8
  70. #define TCL_GSE_CMD_GSE_CTRL_MSB 11
  71. #define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00
  72. #define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004
  73. #define TCL_GSE_CMD_GSE_SEL_LSB 12
  74. #define TCL_GSE_CMD_GSE_SEL_MSB 12
  75. #define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000
  76. #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
  77. #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13
  78. #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13
  79. #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000
  80. #define TCL_GSE_CMD_SWAP_OFFSET 0x00000004
  81. #define TCL_GSE_CMD_SWAP_LSB 14
  82. #define TCL_GSE_CMD_SWAP_MSB 14
  83. #define TCL_GSE_CMD_SWAP_MASK 0x00004000
  84. #define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004
  85. #define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15
  86. #define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15
  87. #define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000
  88. #define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004
  89. #define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16
  90. #define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19
  91. #define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000
  92. #define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004
  93. #define TCL_GSE_CMD_RESERVED_1A_LSB 20
  94. #define TCL_GSE_CMD_RESERVED_1A_MSB 31
  95. #define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000
  96. #define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008
  97. #define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0
  98. #define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0
  99. #define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001
  100. #define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008
  101. #define TCL_GSE_CMD_RESERVED_2A_LSB 1
  102. #define TCL_GSE_CMD_RESERVED_2A_MSB 31
  103. #define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe
  104. #define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c
  105. #define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0
  106. #define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31
  107. #define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff
  108. #define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010
  109. #define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0
  110. #define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31
  111. #define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff
  112. #define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014
  113. #define TCL_GSE_CMD_RESERVED_5A_LSB 0
  114. #define TCL_GSE_CMD_RESERVED_5A_MSB 31
  115. #define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff
  116. #define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018
  117. #define TCL_GSE_CMD_RESERVED_6A_LSB 0
  118. #define TCL_GSE_CMD_RESERVED_6A_MSB 31
  119. #define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff
  120. #define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c
  121. #define TCL_GSE_CMD_RESERVED_7A_LSB 0
  122. #define TCL_GSE_CMD_RESERVED_7A_MSB 19
  123. #define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff
  124. #define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c
  125. #define TCL_GSE_CMD_RING_ID_LSB 20
  126. #define TCL_GSE_CMD_RING_ID_MSB 27
  127. #define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000
  128. #define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c
  129. #define TCL_GSE_CMD_LOOPING_COUNT_LSB 28
  130. #define TCL_GSE_CMD_LOOPING_COUNT_MSB 31
  131. #define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000
  132. #endif