uniform_descriptor_header.h 5.2 KB

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  1. /*
  2. * Copyright (c) 2019, The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
  17. #define _UNIFORM_DESCRIPTOR_HEADER_H_
  18. #if !defined(__ASSEMBLER__)
  19. #endif
  20. // ################ START SUMMARY #################
  21. //
  22. // Dword Fields
  23. // 0 owner[3:0], buffer_type[7:4], reserved_0a[31:8]
  24. //
  25. // ################ END SUMMARY #################
  26. #define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
  27. struct uniform_descriptor_header {
  28. uint32_t owner : 4, //[3:0]
  29. buffer_type : 4, //[7:4]
  30. reserved_0a : 24; //[31:8]
  31. };
  32. /*
  33. owner
  34. Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  35. Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  36. The owner of this data structure:
  37. <enum 0 WBM_owned> Buffer Manager currently owns this
  38. data structure.
  39. <enum 1 SW_OR_FW_owned> Software of FW currently owns
  40. this data structure.
  41. <enum 2 TQM_owned> Transmit Queue Manager currently owns
  42. this data structure.
  43. <enum 3 RXDMA_owned> Receive DMA currently owns this
  44. data structure.
  45. <enum 4 REO_owned> Reorder currently owns this data
  46. structure.
  47. <enum 5 SWITCH_owned> SWITCH currently owns this data
  48. structure.
  49. <legal 0-5>
  50. buffer_type
  51. Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  52. Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  53. Field describing what contents format is of this
  54. descriptor
  55. <enum 0 Transmit_MSDU_Link_descriptor >
  56. <enum 1 Transmit_MPDU_Link_descriptor >
  57. <enum 2 Transmit_MPDU_Queue_head_descriptor>
  58. <enum 3 Transmit_MPDU_Queue_ext_descriptor>
  59. <enum 4 Transmit_flow_descriptor>
  60. <enum 5 Transmit_buffer > NOT TO BE USED:
  61. <enum 6 Receive_MSDU_Link_descriptor >
  62. <enum 7 Receive_MPDU_Link_descriptor >
  63. <enum 8 Receive_REO_queue_descriptor >
  64. <enum 9 Receive_REO_queue_ext_descriptor >
  65. <enum 10 Receive_buffer >
  66. <enum 11 Idle_link_list_entry>
  67. <legal 0-11>
  68. reserved_0a
  69. <legal 0>
  70. */
  71. /* Description UNIFORM_DESCRIPTOR_HEADER_0_OWNER
  72. Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  73. Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  74. The owner of this data structure:
  75. <enum 0 WBM_owned> Buffer Manager currently owns this
  76. data structure.
  77. <enum 1 SW_OR_FW_owned> Software of FW currently owns
  78. this data structure.
  79. <enum 2 TQM_owned> Transmit Queue Manager currently owns
  80. this data structure.
  81. <enum 3 RXDMA_owned> Receive DMA currently owns this
  82. data structure.
  83. <enum 4 REO_owned> Reorder currently owns this data
  84. structure.
  85. <enum 5 SWITCH_owned> SWITCH currently owns this data
  86. structure.
  87. <legal 0-5>
  88. */
  89. #define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000
  90. #define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0
  91. #define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f
  92. /* Description UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE
  93. Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  94. Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
  95. Field describing what contents format is of this
  96. descriptor
  97. <enum 0 Transmit_MSDU_Link_descriptor >
  98. <enum 1 Transmit_MPDU_Link_descriptor >
  99. <enum 2 Transmit_MPDU_Queue_head_descriptor>
  100. <enum 3 Transmit_MPDU_Queue_ext_descriptor>
  101. <enum 4 Transmit_flow_descriptor>
  102. <enum 5 Transmit_buffer > NOT TO BE USED:
  103. <enum 6 Receive_MSDU_Link_descriptor >
  104. <enum 7 Receive_MPDU_Link_descriptor >
  105. <enum 8 Receive_REO_queue_descriptor >
  106. <enum 9 Receive_REO_queue_ext_descriptor >
  107. <enum 10 Receive_buffer >
  108. <enum 11 Idle_link_list_entry>
  109. <legal 0-11>
  110. */
  111. #define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000
  112. #define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4
  113. #define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0
  114. /* Description UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A
  115. <legal 0>
  116. */
  117. #define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000
  118. #define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8
  119. #define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00
  120. #endif // _UNIFORM_DESCRIPTOR_HEADER_H_