rx_mpdu_end.h 21 KB

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  1. /*
  2. * Copyright (c) 2016 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. // $ATH_LICENSE_HW_HDR_C$
  19. //
  20. // DO NOT EDIT! This file is automatically generated
  21. // These definitions are tied to a particular hardware layout
  22. #ifndef _RX_MPDU_END_H_
  23. #define _RX_MPDU_END_H_
  24. #if !defined(__ASSEMBLER__)
  25. #endif
  26. // ################ START SUMMARY #################
  27. //
  28. // Dword Fields
  29. // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
  30. // 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29]
  31. //
  32. // ################ END SUMMARY #################
  33. #define NUM_OF_DWORDS_RX_MPDU_END 2
  34. struct rx_mpdu_end {
  35. uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0]
  36. sw_frame_group_id : 7, //[8:2]
  37. reserved_0 : 7, //[15:9]
  38. phy_ppdu_id : 16; //[31:16]
  39. uint32_t reserved_1a : 11, //[10:0]
  40. unsup_ktype_short_frame : 1, //[11]
  41. rx_in_tx_decrypt_byp : 1, //[12]
  42. overflow_err : 1, //[13]
  43. mpdu_length_err : 1, //[14]
  44. tkip_mic_err : 1, //[15]
  45. decrypt_err : 1, //[16]
  46. unencrypted_frame_err : 1, //[17]
  47. pn_fields_contain_valid_info : 1, //[18]
  48. fcs_err : 1, //[19]
  49. msdu_length_err : 1, //[20]
  50. rxdma0_destination_ring : 2, //[22:21]
  51. rxdma1_destination_ring : 2, //[24:23]
  52. decrypt_status_code : 3, //[27:25]
  53. rx_bitmap_not_updated : 1, //[28]
  54. reserved_1b : 3; //[31:29]
  55. };
  56. /*
  57. rxpcu_mpdu_filter_in_category
  58. Field indicates what the reason was that this MPDU frame
  59. was allowed to come into the receive path by RXPCU
  60. <enum 0 rxpcu_filter_pass> This MPDU passed the normal
  61. frame filter programming of rxpcu
  62. <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
  63. regular frame filter and would have been dropped, were it
  64. not for the frame fitting into the 'monitor_client'
  65. category.
  66. <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
  67. regular frame filter and also did not pass the
  68. rxpcu_monitor_client filter. It would have been dropped
  69. accept that it did pass the 'monitor_other' category.
  70. <legal 0-2>
  71. sw_frame_group_id
  72. SW processes frames based on certain classifications.
  73. This field indicates to what sw classification this MPDU is
  74. mapped.
  75. The classification is given in priority order
  76. <enum 0 sw_frame_group_NDP_frame>
  77. <enum 1 sw_frame_group_Multicast_data>
  78. <enum 2 sw_frame_group_Unicast_data>
  79. <enum 3 sw_frame_group_Null_data > This includes mpdus
  80. of type Data Null as well as QoS Data Null
  81. <enum 4 sw_frame_group_mgmt_0000 >
  82. <enum 5 sw_frame_group_mgmt_0001 >
  83. <enum 6 sw_frame_group_mgmt_0010 >
  84. <enum 7 sw_frame_group_mgmt_0011 >
  85. <enum 8 sw_frame_group_mgmt_0100 >
  86. <enum 9 sw_frame_group_mgmt_0101 >
  87. <enum 10 sw_frame_group_mgmt_0110 >
  88. <enum 11 sw_frame_group_mgmt_0111 >
  89. <enum 12 sw_frame_group_mgmt_1000 >
  90. <enum 13 sw_frame_group_mgmt_1001 >
  91. <enum 14 sw_frame_group_mgmt_1010 >
  92. <enum 15 sw_frame_group_mgmt_1011 >
  93. <enum 16 sw_frame_group_mgmt_1100 >
  94. <enum 17 sw_frame_group_mgmt_1101 >
  95. <enum 18 sw_frame_group_mgmt_1110 >
  96. <enum 19 sw_frame_group_mgmt_1111 >
  97. <enum 20 sw_frame_group_ctrl_0000 >
  98. <enum 21 sw_frame_group_ctrl_0001 >
  99. <enum 22 sw_frame_group_ctrl_0010 >
  100. <enum 23 sw_frame_group_ctrl_0011 >
  101. <enum 24 sw_frame_group_ctrl_0100 >
  102. <enum 25 sw_frame_group_ctrl_0101 >
  103. <enum 26 sw_frame_group_ctrl_0110 >
  104. <enum 27 sw_frame_group_ctrl_0111 >
  105. <enum 28 sw_frame_group_ctrl_1000 >
  106. <enum 29 sw_frame_group_ctrl_1001 >
  107. <enum 30 sw_frame_group_ctrl_1010 >
  108. <enum 31 sw_frame_group_ctrl_1011 >
  109. <enum 32 sw_frame_group_ctrl_1100 >
  110. <enum 33 sw_frame_group_ctrl_1101 >
  111. <enum 34 sw_frame_group_ctrl_1110 >
  112. <enum 35 sw_frame_group_ctrl_1111 >
  113. <enum 36 sw_frame_group_unsupported> This covers type 3
  114. and protocol version != 0
  115. <legal 0-37>
  116. reserved_0
  117. <legal 0>
  118. phy_ppdu_id
  119. A ppdu counter value that PHY increments for every PPDU
  120. received. The counter value wraps around
  121. <legal all>
  122. reserved_1a
  123. <legal 0>
  124. unsup_ktype_short_frame
  125. This bit will be '1' when WEP or TKIP or WAPI key type
  126. is received for 11ah short frame. Crypto will bypass the
  127. received packet without decryption to RxOLE after setting
  128. this bit.
  129. rx_in_tx_decrypt_byp
  130. Indicates that RX packet is not decrypted as Crypto is
  131. busy with TX packet processing.
  132. overflow_err
  133. RXPCU Receive FIFO ran out of space to receive the full
  134. MPDU. Therefor this MPDU is terminated early and is thus
  135. corrupted.
  136. This MPDU will not be ACKed.
  137. RXPCU might still be able to correctly receive the
  138. following MPDUs in the PPDU if enough fifo space became
  139. available in time
  140. mpdu_length_err
  141. Set by RXPCU if the expected MPDU length does not
  142. correspond with the actually received number of bytes in the
  143. MPDU.
  144. tkip_mic_err
  145. Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
  146. for this MPDU
  147. decrypt_err
  148. Set by RX CRYPTO when CRYPTO detected a decrypt error
  149. for this MPDU.
  150. unencrypted_frame_err
  151. Set by RX CRYPTO when CRYPTO detected an unencrypted
  152. frame while in the peer entry field
  153. 'All_frames_shall_be_encrypted' is set.
  154. pn_fields_contain_valid_info
  155. Set by RX CRYPTO to indicate that there is a valid PN
  156. field present in this MPDU
  157. fcs_err
  158. Set by RXPCU when there is an FCS error detected for
  159. this MPDU
  160. msdu_length_err
  161. Set by RXOLE when there is an msdu length error detected
  162. in at least 1 of the MSDUs embedded within the MPDU
  163. rxdma0_destination_ring
  164. The ring to which RXDMA0 shall push the frame, assuming
  165. no MPDU level errors are detected. In case of MPDU level
  166. errors, RXDMA0 might change the RXDMA0 destination
  167. <enum 0 rxdma_release_ring > RXDMA0 shall push the
  168. frame to the Release ring. Effectively this means the frame
  169. needs to be dropped.
  170. <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to
  171. the FW ring
  172. <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
  173. the SW ring
  174. <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame
  175. to the REO entrance ring
  176. <legal all>
  177. rxdma1_destination_ring
  178. The ring to which RXDMA1 shall push the frame, assuming
  179. no MPDU level errors are detected. In case of MPDU level
  180. errors, RXDMA1 might change the RXDMA destination
  181. <enum 0 rxdma_release_ring > RXDMA1 shall push the
  182. frame to the Release ring. Effectively this means the frame
  183. needs to be dropped.
  184. <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to
  185. the FW ring
  186. <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
  187. the SW ring
  188. <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame
  189. to the REO entrance ring
  190. <legal all>
  191. decrypt_status_code
  192. Field provides insight into the decryption performed
  193. <enum 0 decrypt_ok> Frame had protection enabled and
  194. decrypted properly
  195. <enum 1 decrypt_unprotected_frame > Frame is unprotected
  196. and hence bypassed
  197. <enum 2 decrypt_data_err > Frame has protection enabled
  198. and could not be properly decrypted due to MIC/ICV mismatch
  199. etc.
  200. <enum 3 decrypt_key_invalid > Frame has protection
  201. enabled but the key that was required to decrypt this frame
  202. was not valid
  203. <enum 4 decrypt_peer_entry_invalid > Frame has
  204. protection enabled but the key that was required to decrypt
  205. this frame was not valid
  206. <enum 5 decrypt_other > Reserved for other indications
  207. <legal 0 - 5>
  208. rx_bitmap_not_updated
  209. Frame is received, but RXPCU could not update the
  210. receive bitmap due to (temporary) fifo contraints.
  211. <legal all>
  212. reserved_1b
  213. <legal 0>
  214. */
  215. /* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
  216. Field indicates what the reason was that this MPDU frame
  217. was allowed to come into the receive path by RXPCU
  218. <enum 0 rxpcu_filter_pass> This MPDU passed the normal
  219. frame filter programming of rxpcu
  220. <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
  221. regular frame filter and would have been dropped, were it
  222. not for the frame fitting into the 'monitor_client'
  223. category.
  224. <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
  225. regular frame filter and also did not pass the
  226. rxpcu_monitor_client filter. It would have been dropped
  227. accept that it did pass the 'monitor_other' category.
  228. <legal 0-2>
  229. */
  230. #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
  231. #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
  232. #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
  233. /* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID
  234. SW processes frames based on certain classifications.
  235. This field indicates to what sw classification this MPDU is
  236. mapped.
  237. The classification is given in priority order
  238. <enum 0 sw_frame_group_NDP_frame>
  239. <enum 1 sw_frame_group_Multicast_data>
  240. <enum 2 sw_frame_group_Unicast_data>
  241. <enum 3 sw_frame_group_Null_data > This includes mpdus
  242. of type Data Null as well as QoS Data Null
  243. <enum 4 sw_frame_group_mgmt_0000 >
  244. <enum 5 sw_frame_group_mgmt_0001 >
  245. <enum 6 sw_frame_group_mgmt_0010 >
  246. <enum 7 sw_frame_group_mgmt_0011 >
  247. <enum 8 sw_frame_group_mgmt_0100 >
  248. <enum 9 sw_frame_group_mgmt_0101 >
  249. <enum 10 sw_frame_group_mgmt_0110 >
  250. <enum 11 sw_frame_group_mgmt_0111 >
  251. <enum 12 sw_frame_group_mgmt_1000 >
  252. <enum 13 sw_frame_group_mgmt_1001 >
  253. <enum 14 sw_frame_group_mgmt_1010 >
  254. <enum 15 sw_frame_group_mgmt_1011 >
  255. <enum 16 sw_frame_group_mgmt_1100 >
  256. <enum 17 sw_frame_group_mgmt_1101 >
  257. <enum 18 sw_frame_group_mgmt_1110 >
  258. <enum 19 sw_frame_group_mgmt_1111 >
  259. <enum 20 sw_frame_group_ctrl_0000 >
  260. <enum 21 sw_frame_group_ctrl_0001 >
  261. <enum 22 sw_frame_group_ctrl_0010 >
  262. <enum 23 sw_frame_group_ctrl_0011 >
  263. <enum 24 sw_frame_group_ctrl_0100 >
  264. <enum 25 sw_frame_group_ctrl_0101 >
  265. <enum 26 sw_frame_group_ctrl_0110 >
  266. <enum 27 sw_frame_group_ctrl_0111 >
  267. <enum 28 sw_frame_group_ctrl_1000 >
  268. <enum 29 sw_frame_group_ctrl_1001 >
  269. <enum 30 sw_frame_group_ctrl_1010 >
  270. <enum 31 sw_frame_group_ctrl_1011 >
  271. <enum 32 sw_frame_group_ctrl_1100 >
  272. <enum 33 sw_frame_group_ctrl_1101 >
  273. <enum 34 sw_frame_group_ctrl_1110 >
  274. <enum 35 sw_frame_group_ctrl_1111 >
  275. <enum 36 sw_frame_group_unsupported> This covers type 3
  276. and protocol version != 0
  277. <legal 0-37>
  278. */
  279. #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
  280. #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2
  281. #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
  282. /* Description RX_MPDU_END_0_RESERVED_0
  283. <legal 0>
  284. */
  285. #define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000
  286. #define RX_MPDU_END_0_RESERVED_0_LSB 9
  287. #define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00
  288. /* Description RX_MPDU_END_0_PHY_PPDU_ID
  289. A ppdu counter value that PHY increments for every PPDU
  290. received. The counter value wraps around
  291. <legal all>
  292. */
  293. #define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000
  294. #define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16
  295. #define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000
  296. /* Description RX_MPDU_END_1_RESERVED_1A
  297. <legal 0>
  298. */
  299. #define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004
  300. #define RX_MPDU_END_1_RESERVED_1A_LSB 0
  301. #define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff
  302. /* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME
  303. This bit will be '1' when WEP or TKIP or WAPI key type
  304. is received for 11ah short frame. Crypto will bypass the
  305. received packet without decryption to RxOLE after setting
  306. this bit.
  307. */
  308. #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004
  309. #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11
  310. #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800
  311. /* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP
  312. Indicates that RX packet is not decrypted as Crypto is
  313. busy with TX packet processing.
  314. */
  315. #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004
  316. #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12
  317. #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000
  318. /* Description RX_MPDU_END_1_OVERFLOW_ERR
  319. RXPCU Receive FIFO ran out of space to receive the full
  320. MPDU. Therefor this MPDU is terminated early and is thus
  321. corrupted.
  322. This MPDU will not be ACKed.
  323. RXPCU might still be able to correctly receive the
  324. following MPDUs in the PPDU if enough fifo space became
  325. available in time
  326. */
  327. #define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004
  328. #define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13
  329. #define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000
  330. /* Description RX_MPDU_END_1_MPDU_LENGTH_ERR
  331. Set by RXPCU if the expected MPDU length does not
  332. correspond with the actually received number of bytes in the
  333. MPDU.
  334. */
  335. #define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004
  336. #define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14
  337. #define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000
  338. /* Description RX_MPDU_END_1_TKIP_MIC_ERR
  339. Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
  340. for this MPDU
  341. */
  342. #define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004
  343. #define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15
  344. #define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000
  345. /* Description RX_MPDU_END_1_DECRYPT_ERR
  346. Set by RX CRYPTO when CRYPTO detected a decrypt error
  347. for this MPDU.
  348. */
  349. #define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004
  350. #define RX_MPDU_END_1_DECRYPT_ERR_LSB 16
  351. #define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000
  352. /* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR
  353. Set by RX CRYPTO when CRYPTO detected an unencrypted
  354. frame while in the peer entry field
  355. 'All_frames_shall_be_encrypted' is set.
  356. */
  357. #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004
  358. #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17
  359. #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000
  360. /* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO
  361. Set by RX CRYPTO to indicate that there is a valid PN
  362. field present in this MPDU
  363. */
  364. #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004
  365. #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18
  366. #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000
  367. /* Description RX_MPDU_END_1_FCS_ERR
  368. Set by RXPCU when there is an FCS error detected for
  369. this MPDU
  370. */
  371. #define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004
  372. #define RX_MPDU_END_1_FCS_ERR_LSB 19
  373. #define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000
  374. /* Description RX_MPDU_END_1_MSDU_LENGTH_ERR
  375. Set by RXOLE when there is an msdu length error detected
  376. in at least 1 of the MSDUs embedded within the MPDU
  377. */
  378. #define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004
  379. #define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20
  380. #define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000
  381. /* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING
  382. The ring to which RXDMA0 shall push the frame, assuming
  383. no MPDU level errors are detected. In case of MPDU level
  384. errors, RXDMA0 might change the RXDMA0 destination
  385. <enum 0 rxdma_release_ring > RXDMA0 shall push the
  386. frame to the Release ring. Effectively this means the frame
  387. needs to be dropped.
  388. <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to
  389. the FW ring
  390. <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
  391. the SW ring
  392. <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame
  393. to the REO entrance ring
  394. <legal all>
  395. */
  396. #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004
  397. #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21
  398. #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000
  399. /* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING
  400. The ring to which RXDMA1 shall push the frame, assuming
  401. no MPDU level errors are detected. In case of MPDU level
  402. errors, RXDMA1 might change the RXDMA destination
  403. <enum 0 rxdma_release_ring > RXDMA1 shall push the
  404. frame to the Release ring. Effectively this means the frame
  405. needs to be dropped.
  406. <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to
  407. the FW ring
  408. <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
  409. the SW ring
  410. <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame
  411. to the REO entrance ring
  412. <legal all>
  413. */
  414. #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004
  415. #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23
  416. #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000
  417. /* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE
  418. Field provides insight into the decryption performed
  419. <enum 0 decrypt_ok> Frame had protection enabled and
  420. decrypted properly
  421. <enum 1 decrypt_unprotected_frame > Frame is unprotected
  422. and hence bypassed
  423. <enum 2 decrypt_data_err > Frame has protection enabled
  424. and could not be properly decrypted due to MIC/ICV mismatch
  425. etc.
  426. <enum 3 decrypt_key_invalid > Frame has protection
  427. enabled but the key that was required to decrypt this frame
  428. was not valid
  429. <enum 4 decrypt_peer_entry_invalid > Frame has
  430. protection enabled but the key that was required to decrypt
  431. this frame was not valid
  432. <enum 5 decrypt_other > Reserved for other indications
  433. <legal 0 - 5>
  434. */
  435. #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004
  436. #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25
  437. #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000
  438. /* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED
  439. Frame is received, but RXPCU could not update the
  440. receive bitmap due to (temporary) fifo contraints.
  441. <legal all>
  442. */
  443. #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004
  444. #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28
  445. #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000
  446. /* Description RX_MPDU_END_1_RESERVED_1B
  447. <legal 0>
  448. */
  449. #define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004
  450. #define RX_MPDU_END_1_RESERVED_1B_LSB 29
  451. #define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000
  452. #endif // _RX_MPDU_END_H_