rx_mpdu_start.h 48 KB

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  1. /*
  2. * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  3. * SPDX-License-Identifier: ISC
  4. */
  5. #ifndef _RX_MPDU_START_H_
  6. #define _RX_MPDU_START_H_
  7. #if !defined(__ASSEMBLER__)
  8. #endif
  9. #include "rx_mpdu_info.h"
  10. #define NUM_OF_DWORDS_RX_MPDU_START 30
  11. #define NUM_OF_QWORDS_RX_MPDU_START 15
  12. struct rx_mpdu_start {
  13. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  14. struct rx_mpdu_info rx_mpdu_info_details;
  15. #else
  16. struct rx_mpdu_info rx_mpdu_info_details;
  17. #endif
  18. };
  19. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000
  20. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
  21. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
  22. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f
  23. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000
  24. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
  25. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6
  26. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060
  27. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000
  28. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
  29. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7
  30. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080
  31. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000
  32. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
  33. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8
  34. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100
  35. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000
  36. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
  37. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9
  38. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200
  39. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000
  40. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
  41. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10
  42. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400
  43. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000
  44. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
  45. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13
  46. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800
  47. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000
  48. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
  49. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
  50. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000
  51. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000
  52. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17
  53. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17
  54. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000
  55. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000
  56. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18
  57. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18
  58. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000
  59. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000
  60. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19
  61. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19
  62. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000
  63. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000
  64. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20
  65. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20
  66. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000
  67. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000
  68. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21
  69. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21
  70. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000
  71. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
  72. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22
  73. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31
  74. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ffc00000
  75. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000
  76. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32
  77. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63
  78. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000
  79. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008
  80. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
  81. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
  82. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff
  83. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008
  84. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8
  85. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 23
  86. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000ffff00
  87. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008
  88. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24
  89. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 24
  90. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0000000001000000
  91. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008
  92. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25
  93. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 25
  94. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0000000002000000
  95. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008
  96. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26
  97. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 31
  98. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0x00000000fc000000
  99. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000008
  100. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 32
  101. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 63
  102. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff00000000
  103. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010
  104. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0
  105. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 31
  106. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0x00000000ffffffff
  107. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000010
  108. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 32
  109. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 63
  110. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff00000000
  111. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018
  112. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0
  113. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 31
  114. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0x00000000ffffffff
  115. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000018
  116. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32
  117. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32
  118. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000
  119. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000018
  120. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33
  121. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33
  122. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000
  123. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000018
  124. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34
  125. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37
  126. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000
  127. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000018
  128. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38
  129. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39
  130. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000
  131. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000000000000018
  132. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 40
  133. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MSB 41
  134. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x0000030000000000
  135. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000018
  136. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42
  137. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42
  138. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000
  139. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000018
  140. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43
  141. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46
  142. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000
  143. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000018
  144. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47
  145. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50
  146. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000
  147. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000018
  148. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51
  149. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63
  150. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000
  151. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020
  152. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0
  153. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 31
  154. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0x00000000ffffffff
  155. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000020
  156. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32
  157. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33
  158. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000
  159. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000020
  160. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34
  161. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40
  162. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000
  163. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000020
  164. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41
  165. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41
  166. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000
  167. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000020
  168. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42
  169. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42
  170. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000
  171. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000020
  172. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43
  173. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43
  174. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000
  175. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000020
  176. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44
  177. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44
  178. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000
  179. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000020
  180. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45
  181. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45
  182. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000
  183. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_OFFSET 0x0000000000000020
  184. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_LSB 46
  185. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MSB 46
  186. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MASK 0x0000400000000000
  187. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x0000000000000020
  188. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 47
  189. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB 47
  190. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000800000000000
  191. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000020
  192. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48
  193. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63
  194. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000
  195. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028
  196. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0
  197. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15
  198. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff
  199. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028
  200. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16
  201. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31
  202. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000
  203. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000028
  204. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 32
  205. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 32
  206. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000100000000
  207. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000028
  208. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 33
  209. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 33
  210. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000200000000
  211. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000028
  212. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 34
  213. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 34
  214. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000400000000
  215. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000028
  216. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 35
  217. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 35
  218. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000800000000
  219. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000028
  220. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 36
  221. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 36
  222. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000001000000000
  223. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000028
  224. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 37
  225. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 37
  226. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000002000000000
  227. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000028
  228. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 38
  229. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 38
  230. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000004000000000
  231. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
  232. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 39
  233. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 39
  234. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000008000000000
  235. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000028
  236. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 40
  237. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 40
  238. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000010000000000
  239. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000028
  240. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 41
  241. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 41
  242. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000020000000000
  243. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000028
  244. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 42
  245. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 45
  246. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c0000000000
  247. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000028
  248. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 46
  249. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 46
  250. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000400000000000
  251. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000000000000028
  252. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 47
  253. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 47
  254. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x0000800000000000
  255. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000028
  256. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 48
  257. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 48
  258. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0001000000000000
  259. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000028
  260. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 49
  261. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 49
  262. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0002000000000000
  263. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000028
  264. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 50
  265. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 50
  266. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0004000000000000
  267. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000028
  268. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 51
  269. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 51
  270. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0008000000000000
  271. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000028
  272. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 52
  273. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 63
  274. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff0000000000000
  275. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030
  276. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0
  277. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7
  278. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff
  279. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030
  280. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8
  281. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8
  282. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100
  283. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030
  284. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9
  285. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9
  286. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200
  287. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030
  288. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10
  289. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11
  290. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00
  291. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030
  292. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12
  293. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12
  294. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000
  295. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030
  296. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13
  297. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13
  298. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000
  299. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030
  300. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14
  301. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14
  302. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000
  303. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030
  304. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15
  305. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15
  306. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000
  307. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030
  308. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16
  309. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27
  310. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000
  311. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030
  312. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28
  313. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28
  314. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000
  315. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030
  316. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29
  317. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29
  318. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000
  319. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030
  320. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30
  321. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30
  322. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000
  323. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030
  324. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31
  325. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31
  326. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000
  327. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030
  328. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32
  329. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45
  330. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000
  331. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030
  332. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46
  333. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46
  334. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000
  335. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030
  336. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47
  337. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47
  338. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000
  339. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030
  340. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48
  341. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48
  342. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000
  343. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030
  344. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49
  345. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49
  346. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000
  347. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030
  348. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50
  349. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50
  350. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000
  351. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030
  352. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51
  353. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51
  354. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000
  355. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030
  356. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52
  357. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52
  358. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000
  359. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030
  360. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53
  361. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53
  362. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000
  363. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030
  364. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54
  365. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54
  366. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000
  367. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030
  368. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55
  369. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55
  370. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000
  371. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030
  372. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56
  373. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56
  374. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000
  375. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030
  376. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57
  377. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57
  378. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000
  379. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030
  380. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58
  381. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58
  382. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000
  383. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030
  384. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59
  385. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59
  386. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000
  387. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030
  388. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60
  389. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60
  390. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000
  391. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030
  392. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61
  393. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61
  394. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000
  395. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030
  396. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62
  397. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62
  398. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000
  399. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030
  400. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63
  401. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63
  402. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000
  403. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038
  404. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0
  405. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15
  406. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff
  407. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038
  408. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16
  409. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31
  410. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000
  411. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038
  412. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32
  413. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63
  414. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000
  415. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040
  416. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0
  417. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15
  418. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff
  419. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040
  420. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16
  421. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31
  422. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000
  423. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040
  424. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32
  425. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63
  426. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000
  427. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048
  428. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0
  429. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31
  430. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff
  431. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048
  432. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32
  433. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47
  434. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000
  435. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048
  436. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48
  437. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63
  438. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000
  439. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050
  440. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0
  441. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31
  442. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff
  443. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050
  444. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32
  445. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47
  446. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000
  447. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050
  448. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48
  449. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63
  450. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000
  451. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058
  452. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0
  453. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31
  454. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff
  455. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058
  456. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32
  457. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39
  458. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000
  459. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058
  460. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40
  461. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48
  462. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000
  463. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058
  464. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49
  465. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49
  466. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000
  467. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058
  468. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50
  469. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61
  470. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000
  471. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000000000000058
  472. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 62
  473. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 62
  474. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x4000000000000000
  475. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000000000000058
  476. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 63
  477. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 63
  478. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x8000000000000000
  479. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000060
  480. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_LSB 0
  481. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MSB 31
  482. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff
  483. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000060
  484. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_LSB 32
  485. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MSB 47
  486. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000
  487. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000060
  488. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_LSB 48
  489. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MSB 63
  490. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000
  491. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000068
  492. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_LSB 0
  493. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MSB 31
  494. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff
  495. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068
  496. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32
  497. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32
  498. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000
  499. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068
  500. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 33
  501. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63
  502. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xfffffffe00000000
  503. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET 0x0000000000000070
  504. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB 0
  505. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB 31
  506. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK 0x00000000ffffffff
  507. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070
  508. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 32
  509. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63
  510. #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffffffff00000000
  511. #endif