reo_entrance_ring.h 18 KB

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  1. /*
  2. * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  3. * SPDX-License-Identifier: ISC
  4. */
  5. #ifndef _REO_ENTRANCE_RING_H_
  6. #define _REO_ENTRANCE_RING_H_
  7. #if !defined(__ASSEMBLER__)
  8. #endif
  9. #include "rx_mpdu_details.h"
  10. #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
  11. struct reo_entrance_ring {
  12. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  13. struct rx_mpdu_details reo_level_mpdu_frame_info;
  14. uint32_t rx_reo_queue_desc_addr_31_0 : 32;
  15. uint32_t rx_reo_queue_desc_addr_39_32 : 8,
  16. rounded_mpdu_byte_count : 14,
  17. reo_destination_indication : 5,
  18. frameless_bar : 1,
  19. reserved_5a : 4;
  20. uint32_t rxdma_push_reason : 2,
  21. rxdma_error_code : 5,
  22. mpdu_fragment_number : 4,
  23. sw_exception : 1,
  24. sw_exception_mpdu_delink : 1,
  25. sw_exception_destination_ring_valid : 1,
  26. sw_exception_destination_ring : 5,
  27. mpdu_sequence_number : 12,
  28. reserved_6a : 1;
  29. uint32_t phy_ppdu_id : 16,
  30. src_link_id : 3,
  31. reserved_7a : 1,
  32. ring_id : 8,
  33. looping_count : 4;
  34. #else
  35. struct rx_mpdu_details reo_level_mpdu_frame_info;
  36. uint32_t rx_reo_queue_desc_addr_31_0 : 32;
  37. uint32_t reserved_5a : 4,
  38. frameless_bar : 1,
  39. reo_destination_indication : 5,
  40. rounded_mpdu_byte_count : 14,
  41. rx_reo_queue_desc_addr_39_32 : 8;
  42. uint32_t reserved_6a : 1,
  43. mpdu_sequence_number : 12,
  44. sw_exception_destination_ring : 5,
  45. sw_exception_destination_ring_valid : 1,
  46. sw_exception_mpdu_delink : 1,
  47. sw_exception : 1,
  48. mpdu_fragment_number : 4,
  49. rxdma_error_code : 5,
  50. rxdma_push_reason : 2;
  51. uint32_t looping_count : 4,
  52. ring_id : 8,
  53. reserved_7a : 1,
  54. src_link_id : 3,
  55. phy_ppdu_id : 16;
  56. #endif
  57. };
  58. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
  59. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  60. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
  61. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  62. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
  63. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  64. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
  65. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  66. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
  67. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  68. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
  69. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
  70. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
  71. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
  72. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
  73. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
  74. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
  75. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
  76. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
  77. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
  78. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
  79. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
  80. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
  81. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
  82. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
  83. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
  84. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
  85. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
  86. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
  87. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
  88. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
  89. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
  90. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
  91. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
  92. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
  93. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
  94. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
  95. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
  96. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
  97. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
  98. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
  99. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
  100. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
  101. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
  102. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
  103. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
  104. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
  105. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
  106. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
  107. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
  108. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
  109. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
  110. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
  111. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
  112. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
  113. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
  114. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
  115. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
  116. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
  117. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
  118. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
  119. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
  120. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
  121. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
  122. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
  123. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
  124. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31
  125. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
  126. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
  127. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
  128. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
  129. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
  130. #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
  131. #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8
  132. #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21
  133. #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
  134. #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014
  135. #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22
  136. #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26
  137. #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000
  138. #define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014
  139. #define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27
  140. #define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27
  141. #define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000
  142. #define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014
  143. #define REO_ENTRANCE_RING_RESERVED_5A_LSB 28
  144. #define REO_ENTRANCE_RING_RESERVED_5A_MSB 31
  145. #define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000
  146. #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018
  147. #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0
  148. #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1
  149. #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003
  150. #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018
  151. #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2
  152. #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6
  153. #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c
  154. #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018
  155. #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7
  156. #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10
  157. #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780
  158. #define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018
  159. #define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11
  160. #define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11
  161. #define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800
  162. #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018
  163. #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12
  164. #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12
  165. #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000
  166. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018
  167. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13
  168. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13
  169. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
  170. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018
  171. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14
  172. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18
  173. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000
  174. #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018
  175. #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19
  176. #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30
  177. #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000
  178. #define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018
  179. #define REO_ENTRANCE_RING_RESERVED_6A_LSB 31
  180. #define REO_ENTRANCE_RING_RESERVED_6A_MSB 31
  181. #define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000
  182. #define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c
  183. #define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0
  184. #define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15
  185. #define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff
  186. #define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c
  187. #define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16
  188. #define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18
  189. #define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000
  190. #define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c
  191. #define REO_ENTRANCE_RING_RESERVED_7A_LSB 19
  192. #define REO_ENTRANCE_RING_RESERVED_7A_MSB 19
  193. #define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000
  194. #define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c
  195. #define REO_ENTRANCE_RING_RING_ID_LSB 20
  196. #define REO_ENTRANCE_RING_RING_ID_MSB 27
  197. #define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000
  198. #define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c
  199. #define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28
  200. #define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31
  201. #define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000
  202. #endif