rx_mpdu_end.h 23 KB

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  1. /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  2. *
  3. * Permission to use, copy, modify, and/or distribute this software for any
  4. * purpose with or without fee is hereby granted, provided that the above
  5. * copyright notice and this permission notice appear in all copies.
  6. *
  7. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  8. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  9. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  12. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  13. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14. */
  15. #ifndef _RX_MPDU_END_H_
  16. #define _RX_MPDU_END_H_
  17. #if !defined(__ASSEMBLER__)
  18. #endif
  19. #define NUM_OF_DWORDS_RX_MPDU_END 4
  20. #define NUM_OF_QWORDS_RX_MPDU_END 2
  21. struct rx_mpdu_end {
  22. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  23. uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0]
  24. sw_frame_group_id : 7, // [8:2]
  25. reserved_0 : 7, // [15:9]
  26. phy_ppdu_id : 16; // [31:16]
  27. uint32_t reserved_1a : 11, // [10:0]
  28. unsup_ktype_short_frame : 1, // [11:11]
  29. rx_in_tx_decrypt_byp : 1, // [12:12]
  30. overflow_err : 1, // [13:13]
  31. mpdu_length_err : 1, // [14:14]
  32. tkip_mic_err : 1, // [15:15]
  33. decrypt_err : 1, // [16:16]
  34. unencrypted_frame_err : 1, // [17:17]
  35. pn_fields_contain_valid_info : 1, // [18:18]
  36. fcs_err : 1, // [19:19]
  37. msdu_length_err : 1, // [20:20]
  38. rxdma0_destination_ring : 3, // [23:21]
  39. rxdma1_destination_ring : 3, // [26:24]
  40. decrypt_status_code : 3, // [29:27]
  41. rx_bitmap_not_updated : 1, // [30:30]
  42. reserved_1b : 1; // [31:31]
  43. uint32_t reserved_2a : 15, // [14:0]
  44. rxpcu_mgmt_sequence_nr_valid : 1, // [15:15]
  45. rxpcu_mgmt_sequence_nr : 16; // [31:16]
  46. uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0]
  47. #else
  48. uint32_t phy_ppdu_id : 16, // [31:16]
  49. reserved_0 : 7, // [15:9]
  50. sw_frame_group_id : 7, // [8:2]
  51. rxpcu_mpdu_filter_in_category : 2; // [1:0]
  52. uint32_t reserved_1b : 1, // [31:31]
  53. rx_bitmap_not_updated : 1, // [30:30]
  54. decrypt_status_code : 3, // [29:27]
  55. rxdma1_destination_ring : 3, // [26:24]
  56. rxdma0_destination_ring : 3, // [23:21]
  57. msdu_length_err : 1, // [20:20]
  58. fcs_err : 1, // [19:19]
  59. pn_fields_contain_valid_info : 1, // [18:18]
  60. unencrypted_frame_err : 1, // [17:17]
  61. decrypt_err : 1, // [16:16]
  62. tkip_mic_err : 1, // [15:15]
  63. mpdu_length_err : 1, // [14:14]
  64. overflow_err : 1, // [13:13]
  65. rx_in_tx_decrypt_byp : 1, // [12:12]
  66. unsup_ktype_short_frame : 1, // [11:11]
  67. reserved_1a : 11; // [10:0]
  68. uint32_t rxpcu_mgmt_sequence_nr : 16, // [31:16]
  69. rxpcu_mgmt_sequence_nr_valid : 1, // [15:15]
  70. reserved_2a : 15; // [14:0]
  71. uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0]
  72. #endif
  73. };
  74. /* Description RXPCU_MPDU_FILTER_IN_CATEGORY
  75. Field indicates what the reason was that this MPDU frame
  76. was allowed to come into the receive path by RXPCU
  77. <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame
  78. filter programming of rxpcu
  79. <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
  80. regular frame filter and would have been dropped, were
  81. it not for the frame fitting into the 'monitor_client' category.
  82. <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
  83. regular frame filter and also did not pass the rxpcu_monitor_client
  84. filter. It would have been dropped accept that it did pass
  85. the 'monitor_other' category.
  86. <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed
  87. the normal frame filter programming of RXPCU but additionally
  88. fit into the 'monitor_override_client' category.
  89. <legal 0-3>
  90. */
  91. #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000
  92. #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
  93. #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
  94. #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003
  95. /* Description SW_FRAME_GROUP_ID
  96. SW processes frames based on certain classifications. This
  97. field indicates to what sw classification this MPDU is
  98. mapped.
  99. The classification is given in priority order
  100. <enum 0 sw_frame_group_NDP_frame>
  101. <enum 1 sw_frame_group_Multicast_data>
  102. <enum 2 sw_frame_group_Unicast_data>
  103. <enum 3 sw_frame_group_Null_data > This includes mpdus of
  104. type Data Null.
  105. Hamilton v1 included QoS Data Null as well here.
  106. <enum 38 sw_frame_group_QoS_Null_data> This includes QoS
  107. Null frames except in UL MU or TB PPDUs.
  108. <enum 39 sw_frame_group_QoS_Null_data_TB> This includes
  109. QoS Null frames in UL MU or TB PPDUs.
  110. <enum 4 sw_frame_group_mgmt_0000 >
  111. <enum 5 sw_frame_group_mgmt_0001 >
  112. <enum 6 sw_frame_group_mgmt_0010 >
  113. <enum 7 sw_frame_group_mgmt_0011 >
  114. <enum 8 sw_frame_group_mgmt_0100 >
  115. <enum 9 sw_frame_group_mgmt_0101 >
  116. <enum 10 sw_frame_group_mgmt_0110 >
  117. <enum 11 sw_frame_group_mgmt_0111 >
  118. <enum 12 sw_frame_group_mgmt_1000 >
  119. <enum 13 sw_frame_group_mgmt_1001 >
  120. <enum 14 sw_frame_group_mgmt_1010 >
  121. <enum 15 sw_frame_group_mgmt_1011 >
  122. <enum 16 sw_frame_group_mgmt_1100 >
  123. <enum 17 sw_frame_group_mgmt_1101 >
  124. <enum 18 sw_frame_group_mgmt_1110 >
  125. <enum 19 sw_frame_group_mgmt_1111 >
  126. <enum 20 sw_frame_group_ctrl_0000 >
  127. <enum 21 sw_frame_group_ctrl_0001 >
  128. <enum 22 sw_frame_group_ctrl_0010 >
  129. <enum 23 sw_frame_group_ctrl_0011 >
  130. <enum 24 sw_frame_group_ctrl_0100 >
  131. <enum 25 sw_frame_group_ctrl_0101 >
  132. <enum 26 sw_frame_group_ctrl_0110 >
  133. <enum 27 sw_frame_group_ctrl_0111 >
  134. <enum 28 sw_frame_group_ctrl_1000 >
  135. <enum 29 sw_frame_group_ctrl_1001 >
  136. <enum 30 sw_frame_group_ctrl_1010 >
  137. <enum 31 sw_frame_group_ctrl_1011 >
  138. <enum 32 sw_frame_group_ctrl_1100 >
  139. <enum 33 sw_frame_group_ctrl_1101 >
  140. <enum 34 sw_frame_group_ctrl_1110 >
  141. <enum 35 sw_frame_group_ctrl_1111 >
  142. <enum 36 sw_frame_group_unsupported> This covers type 3
  143. and protocol version != 0
  144. <enum 37 sw_frame_group_phy_error> PHY reported an error
  145. <legal 0-39>
  146. */
  147. #define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000
  148. #define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2
  149. #define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8
  150. #define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc
  151. /* Description RESERVED_0
  152. <legal 0>
  153. */
  154. #define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000
  155. #define RX_MPDU_END_RESERVED_0_LSB 9
  156. #define RX_MPDU_END_RESERVED_0_MSB 15
  157. #define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00
  158. /* Description PHY_PPDU_ID
  159. A ppdu counter value that PHY increments for every PPDU
  160. received. The counter value wraps around
  161. <legal all>
  162. */
  163. #define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000
  164. #define RX_MPDU_END_PHY_PPDU_ID_LSB 16
  165. #define RX_MPDU_END_PHY_PPDU_ID_MSB 31
  166. #define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000
  167. /* Description RESERVED_1A
  168. <legal 0>
  169. */
  170. #define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000
  171. #define RX_MPDU_END_RESERVED_1A_LSB 32
  172. #define RX_MPDU_END_RESERVED_1A_MSB 42
  173. #define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000
  174. /* Description UNSUP_KTYPE_SHORT_FRAME
  175. This bit will be '1' when WEP or TKIP or WAPI key type is
  176. received for 11ah short frame. Crypto will bypass the
  177. received packet without decryption to RxOLE after setting
  178. this bit.
  179. */
  180. #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000
  181. #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43
  182. #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43
  183. #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000
  184. /* Description RX_IN_TX_DECRYPT_BYP
  185. Indicates that RX packet is not decrypted as Crypto is busy
  186. with TX packet processing.
  187. */
  188. #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000
  189. #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44
  190. #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44
  191. #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000
  192. /* Description OVERFLOW_ERR
  193. RXPCU Receive FIFO ran out of space to receive the full
  194. MPDU. Therefor this MPDU is terminated early and is thus
  195. corrupted.
  196. This MPDU will not be ACKed.
  197. RXPCU might still be able to correctly receive the following
  198. MPDUs in the PPDU if enough fifo space became available
  199. in time
  200. */
  201. #define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000
  202. #define RX_MPDU_END_OVERFLOW_ERR_LSB 45
  203. #define RX_MPDU_END_OVERFLOW_ERR_MSB 45
  204. #define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000
  205. /* Description MPDU_LENGTH_ERR
  206. Set by RXPCU if the expected MPDU length does not correspond
  207. with the actually received number of bytes in the MPDU.
  208. */
  209. #define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000
  210. #define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46
  211. #define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46
  212. #define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000
  213. /* Description TKIP_MIC_ERR
  214. Set by RX CRYPTO when CRYPTO detected a TKIP MIC error for
  215. this MPDU
  216. */
  217. #define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000
  218. #define RX_MPDU_END_TKIP_MIC_ERR_LSB 47
  219. #define RX_MPDU_END_TKIP_MIC_ERR_MSB 47
  220. #define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000
  221. /* Description DECRYPT_ERR
  222. Set by RX CRYPTO when CRYPTO detected a decrypt error for
  223. this MPDU or CRYPTO received an encrypted frame, but did
  224. not get a valid corresponding key id in the peer entry.
  225. */
  226. #define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000
  227. #define RX_MPDU_END_DECRYPT_ERR_LSB 48
  228. #define RX_MPDU_END_DECRYPT_ERR_MSB 48
  229. #define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000
  230. /* Description UNENCRYPTED_FRAME_ERR
  231. Set by RX CRYPTO when CRYPTO detected an unencrypted frame
  232. while in the peer entry field 'All_frames_shall_be_encrypted'
  233. is set.
  234. */
  235. #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000
  236. #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49
  237. #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49
  238. #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000
  239. /* Description PN_FIELDS_CONTAIN_VALID_INFO
  240. Set by RX CRYPTO to indicate that there is a valid PN field
  241. present in this MPDU
  242. */
  243. #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000
  244. #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50
  245. #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50
  246. #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000
  247. /* Description FCS_ERR
  248. Set by RXPCU when there is an FCS error detected for this
  249. MPDU
  250. NOTE that when this field is set, all other (error) field
  251. settings should be ignored as modules could have made wrong
  252. decisions based on the corrupted data.
  253. */
  254. #define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000
  255. #define RX_MPDU_END_FCS_ERR_LSB 51
  256. #define RX_MPDU_END_FCS_ERR_MSB 51
  257. #define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000
  258. /* Description MSDU_LENGTH_ERR
  259. Set by RXOLE when there is an msdu length error detected
  260. in at least 1 of the MSDUs embedded within the MPDU
  261. */
  262. #define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000
  263. #define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52
  264. #define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52
  265. #define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000
  266. /* Description RXDMA0_DESTINATION_RING
  267. The ring to which RXDMA0 shall push the frame, assuming
  268. no MPDU level errors are detected. In case of MPDU level
  269. errors, RXDMA0 might change the RXDMA0 destination
  270. <enum 0 rxdma_release_ring > RXDMA0 shall push the frame
  271. to the Release ring. Effectively this means the frame needs
  272. to be dropped.
  273. <enum 1 rxdma2fw_pmac0_ring > RXDMA0 shall push the frame
  274. to the FW ring for PMAC0.
  275. <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
  276. the SW ring
  277. <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame to
  278. the REO entrance ring
  279. <enum 4 rxdma2fw_pmac1_ring> RXDMA0 shall push the frame
  280. to the FW ring for PMAC1.
  281. <enum 5 rxdma2reo_remote0_ring> RXDMA0 shall push the frame
  282. to the first MLO REO entrance ring.
  283. <enum 6 rxdma2reo_remote1_ring> RXDMA0 shall push the frame
  284. to the second MLO REO entrance ring.
  285. <legal 0 - 6>
  286. */
  287. #define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000
  288. #define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53
  289. #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55
  290. #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000
  291. /* Description RXDMA1_DESTINATION_RING
  292. The ring to which RXDMA1 shall push the frame, assuming
  293. no MPDU level errors are detected. In case of MPDU level
  294. errors, RXDMA1 might change the RXDMA destination
  295. <enum 0 rxdma_release_ring > DO NOT USE.
  296. <enum 1 rxdma2fw_pmac0_ring > DO NOT USE.
  297. <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
  298. the SW ring
  299. <enum 3 rxdma2reo_ring > DO NOT USE.
  300. <enum 4 rxdma2fw_pmac1_ring> DO NOT USE.
  301. <enum 5 rxdma2reo_remote0_ring> DO NOT USE.
  302. <enum 6 rxdma2reo_remote1_ring> DO NOT USE.
  303. <legal 0 - 6>
  304. */
  305. #define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000
  306. #define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56
  307. #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58
  308. #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000
  309. /* Description DECRYPT_STATUS_CODE
  310. Field provides insight into the decryption performed
  311. <enum 0 decrypt_ok> Frame had protection enabled and decrypted
  312. properly
  313. <enum 1 decrypt_unprotected_frame > Frame is unprotected
  314. and hence bypassed
  315. <enum 2 decrypt_data_err > Frame has protection enabled
  316. and could not be properly decrypted due to MIC/ICV mismatch
  317. etc.
  318. <enum 3 decrypt_key_invalid > Frame has protection enabled
  319. but the key that was required to decrypt this frame was
  320. not valid
  321. <enum 4 decrypt_peer_entry_invalid > Frame has protection
  322. enabled but the key that was required to decrypt this frame
  323. was not valid
  324. <enum 5 decrypt_other > Reserved for other indications
  325. <legal 0 - 5>
  326. */
  327. #define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000
  328. #define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59
  329. #define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61
  330. #define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000
  331. /* Description RX_BITMAP_NOT_UPDATED
  332. Frame is received, but RXPCU could not update the receive
  333. bitmap due to (temporary) fifo contraints.
  334. <legal all>
  335. */
  336. #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000
  337. #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62
  338. #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62
  339. #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000
  340. /* Description RESERVED_1B
  341. <legal 0>
  342. */
  343. #define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000
  344. #define RX_MPDU_END_RESERVED_1B_LSB 63
  345. #define RX_MPDU_END_RESERVED_1B_MSB 63
  346. #define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000
  347. /* Description RESERVED_2A
  348. <legal 0>
  349. */
  350. #define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008
  351. #define RX_MPDU_END_RESERVED_2A_LSB 0
  352. #define RX_MPDU_END_RESERVED_2A_MSB 14
  353. #define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff
  354. /* Description RXPCU_MGMT_SEQUENCE_NR_VALID
  355. This field gets set by RXPCU when the received management
  356. frame is destined to this device, passes FCS and is categorized
  357. as one for which RXPCU should assign a rxpcu_mgmt_sequence_number.
  358. After assigning a number, the RXPCU will increment the sequence
  359. number for the next management frame that meets these criteria.
  360. <legal all>
  361. */
  362. #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008
  363. #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15
  364. #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15
  365. #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000
  366. /* Description RXPCU_MGMT_SEQUENCE_NR
  367. Field only valid when rxpcu_mgmt_sequence_nr_valid is set
  368. This RXPCU generated sequence number is assigned to this
  369. management frame. It is used by FW and host SW for management
  370. frame reordering across multiple bands/links.
  371. <legal all>
  372. */
  373. #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008
  374. #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16
  375. #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31
  376. #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000
  377. /* Description RXFRAME_ASSERT_MLO_TIMESTAMP
  378. 'mlo_global_timestamp' that indicates when for the PPDU
  379. that contained this MPDU, the 'rx_frame' signal got asserted.
  380. This field is always valid, irrespective of the frame being
  381. related to MLO reception or not. It is used by FW and host
  382. SW for management frame reordering purposes.
  383. <legal all>
  384. */
  385. #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008
  386. #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32
  387. #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63
  388. #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000
  389. #endif // RX_MPDU_END