sdm660-common.c 94 KB

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  1. /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/input.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/of_device.h>
  17. #include <sound/pcm_params.h>
  18. #include <dsp/q6afe-v2.h>
  19. #include <dsp/audio_notifier.h>
  20. #include "msm-pcm-routing-v2.h"
  21. #include "sdm660-common.h"
  22. #include "sdm660-internal.h"
  23. #include "sdm660-external.h"
  24. #include "codecs/msm-cdc-pinctrl.h"
  25. #include "codecs/sdm660_cdc/msm-analog-cdc.h"
  26. #include "codecs/wsa881x.h"
  27. #define DRV_NAME "sdm660-asoc-snd"
  28. #define MSM_INT_DIGITAL_CODEC "msm-dig-codec"
  29. #define PMIC_INT_ANALOG_CODEC "analog-codec"
  30. #define DEV_NAME_STR_LEN 32
  31. #define DEFAULT_MCLK_RATE 9600000
  32. struct dev_config {
  33. u32 sample_rate;
  34. u32 bit_format;
  35. u32 channels;
  36. };
  37. enum {
  38. DP_RX_IDX,
  39. EXT_DISP_RX_IDX_MAX,
  40. };
  41. bool codec_reg_done;
  42. /* TDM default config */
  43. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  44. { /* PRI TDM */
  45. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  46. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  47. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  48. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  49. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  50. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  51. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  52. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  53. },
  54. { /* SEC TDM */
  55. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  56. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  57. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  58. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  59. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  60. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  61. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  62. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  63. },
  64. { /* TERT TDM */
  65. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  66. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  67. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  68. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  69. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  70. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  71. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  72. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  73. },
  74. { /* QUAT TDM */
  75. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  76. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  77. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  78. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  79. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  80. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  81. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  82. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  83. },
  84. { /* QUIN TDM */
  85. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  86. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  87. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  88. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  89. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  90. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  91. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  92. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  93. }
  94. };
  95. /* TDM default config */
  96. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  97. { /* PRI TDM */
  98. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  99. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  100. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  101. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  102. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  103. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  104. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  105. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  106. },
  107. { /* SEC TDM */
  108. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  109. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  110. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  111. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  112. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  113. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  114. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  115. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  116. },
  117. { /* TERT TDM */
  118. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  119. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  120. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  121. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  122. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  123. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  124. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  125. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  126. },
  127. { /* QUAT TDM */
  128. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  129. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  130. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  131. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  132. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  133. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  134. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  135. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  136. },
  137. { /* QUIN TDM */
  138. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  139. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  140. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  141. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  142. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  143. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  144. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  145. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  146. }
  147. };
  148. /* Default configuration of external display BE */
  149. static struct dev_config ext_disp_rx_cfg[] = {
  150. [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  151. };
  152. static struct dev_config usb_rx_cfg = {
  153. .sample_rate = SAMPLING_RATE_48KHZ,
  154. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  155. .channels = 2,
  156. };
  157. static struct dev_config usb_tx_cfg = {
  158. .sample_rate = SAMPLING_RATE_48KHZ,
  159. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  160. .channels = 1,
  161. };
  162. enum {
  163. PRIM_AUX_PCM = 0,
  164. SEC_AUX_PCM,
  165. TERT_AUX_PCM,
  166. QUAT_AUX_PCM,
  167. QUIN_AUX_PCM,
  168. AUX_PCM_MAX,
  169. };
  170. enum {
  171. PCM_I2S_SEL_PRIM = 0,
  172. PCM_I2S_SEL_SEC,
  173. PCM_I2S_SEL_TERT,
  174. PCM_I2S_SEL_QUAT,
  175. PCM_I2S_SEL_QUIN,
  176. PCM_I2S_SEL_MAX,
  177. };
  178. struct mi2s_conf {
  179. struct mutex lock;
  180. u32 ref_cnt;
  181. u32 msm_is_mi2s_master;
  182. u32 msm_is_ext_mclk;
  183. };
  184. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  185. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  186. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  187. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  188. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  189. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  190. };
  191. struct msm_wsa881x_dev_info {
  192. struct device_node *of_node;
  193. u32 index;
  194. };
  195. static struct snd_soc_aux_dev *msm_aux_dev;
  196. static struct snd_soc_codec_conf *msm_codec_conf;
  197. static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active);
  198. static struct wcd_mbhc_config mbhc_cfg = {
  199. .read_fw_bin = false,
  200. .calibration = NULL,
  201. .detect_extn_cable = true,
  202. .mono_stero_detection = false,
  203. .swap_gnd_mic = NULL,
  204. .hs_ext_micbias = true,
  205. .key_code[0] = KEY_MEDIA,
  206. .key_code[1] = KEY_VOICECOMMAND,
  207. .key_code[2] = KEY_VOLUMEUP,
  208. .key_code[3] = KEY_VOLUMEDOWN,
  209. .key_code[4] = 0,
  210. .key_code[5] = 0,
  211. .key_code[6] = 0,
  212. .key_code[7] = 0,
  213. .linein_th = 5000,
  214. .moisture_en = false,
  215. .mbhc_micbias = 0,
  216. .anc_micbias = 0,
  217. .enable_anc_mic_detect = false,
  218. };
  219. static struct dev_config proxy_rx_cfg = {
  220. .sample_rate = SAMPLING_RATE_48KHZ,
  221. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  222. .channels = 2,
  223. };
  224. /* Default configuration of MI2S channels */
  225. static struct dev_config mi2s_rx_cfg[] = {
  226. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  227. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  228. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  229. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  230. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  231. };
  232. static struct dev_config mi2s_tx_cfg[] = {
  233. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  234. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  235. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  236. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  237. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  238. };
  239. static struct dev_config aux_pcm_rx_cfg[] = {
  240. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  241. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  242. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  243. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  244. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  245. };
  246. static struct dev_config aux_pcm_tx_cfg[] = {
  247. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  248. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  249. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  250. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  251. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  252. };
  253. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  254. "Six", "Seven", "Eight"};
  255. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  256. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_16",
  257. "KHZ_32", "KHZ_44P1", "KHZ_48",
  258. "KHZ_96", "KHZ_192"};
  259. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  260. "Five", "Six", "Seven",
  261. "Eight"};
  262. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  263. "S32_LE"};
  264. static char const *mi2s_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  265. "S32_LE"};
  266. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  267. "Five", "Six", "Seven", "Eight"};
  268. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  269. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  270. "KHZ_44P1", "KHZ_48", "KHZ_96",
  271. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  272. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  273. "Five", "Six", "Seven",
  274. "Eight"};
  275. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  276. "KHZ_16", "KHZ_22P05",
  277. "KHZ_32", "KHZ_44P1", "KHZ_48",
  278. "KHZ_96", "KHZ_192", "KHZ_384"};
  279. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE"};
  280. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  281. "KHZ_192"};
  282. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  283. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  284. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  285. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  286. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  287. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  288. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  289. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  290. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  291. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  292. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  293. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  294. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  295. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  296. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  297. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  298. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  299. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  300. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  301. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  302. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  303. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  304. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_format, mi2s_format_text);
  305. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_format, mi2s_format_text);
  306. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_format, mi2s_format_text);
  307. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_format, mi2s_format_text);
  308. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_format, mi2s_format_text);
  309. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_format, mi2s_format_text);
  310. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_format, mi2s_format_text);
  311. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_format, mi2s_format_text);
  312. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_format, mi2s_format_text);
  313. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_format, mi2s_format_text);
  314. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  315. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  316. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  317. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  318. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  319. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  320. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  321. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  322. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  323. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  324. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  325. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  326. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  327. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  328. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  329. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  330. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  331. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  332. ext_disp_sample_rate_text);
  333. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  334. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  335. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  336. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  337. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  338. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  339. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  340. {
  341. AFE_API_VERSION_I2S_CONFIG,
  342. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  343. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  344. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  345. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  346. 0,
  347. },
  348. {
  349. AFE_API_VERSION_I2S_CONFIG,
  350. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  351. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  352. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  353. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  354. 0,
  355. },
  356. {
  357. AFE_API_VERSION_I2S_CONFIG,
  358. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  359. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  360. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  361. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  362. 0,
  363. },
  364. {
  365. AFE_API_VERSION_I2S_CONFIG,
  366. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  367. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  368. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  369. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  370. 0,
  371. },
  372. {
  373. AFE_API_VERSION_I2S_CONFIG,
  374. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  375. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  376. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  377. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  378. 0,
  379. }
  380. };
  381. static struct afe_clk_set mi2s_mclk[MI2S_MAX] = {
  382. {
  383. AFE_API_VERSION_I2S_CONFIG,
  384. Q6AFE_LPASS_CLK_ID_MCLK_3,
  385. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  386. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  387. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  388. 0,
  389. },
  390. {
  391. AFE_API_VERSION_I2S_CONFIG,
  392. Q6AFE_LPASS_CLK_ID_MCLK_2,
  393. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  394. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  395. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  396. 0,
  397. },
  398. {
  399. AFE_API_VERSION_I2S_CONFIG,
  400. Q6AFE_LPASS_CLK_ID_MCLK_1,
  401. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  402. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  403. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  404. 0,
  405. },
  406. {
  407. AFE_API_VERSION_I2S_CONFIG,
  408. Q6AFE_LPASS_CLK_ID_MCLK_1,
  409. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  410. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  411. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  412. 0,
  413. },
  414. {
  415. AFE_API_VERSION_I2S_CONFIG,
  416. Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR,
  417. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  418. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  419. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  420. 0,
  421. }
  422. };
  423. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  424. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  425. struct snd_ctl_elem_value *ucontrol)
  426. {
  427. pr_debug("%s: proxy_rx channels = %d\n",
  428. __func__, proxy_rx_cfg.channels);
  429. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  430. return 0;
  431. }
  432. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  433. struct snd_ctl_elem_value *ucontrol)
  434. {
  435. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  436. pr_debug("%s: proxy_rx channels = %d\n",
  437. __func__, proxy_rx_cfg.channels);
  438. return 1;
  439. }
  440. static int tdm_get_sample_rate(int value)
  441. {
  442. int sample_rate = 0;
  443. switch (value) {
  444. case 0:
  445. sample_rate = SAMPLING_RATE_8KHZ;
  446. break;
  447. case 1:
  448. sample_rate = SAMPLING_RATE_16KHZ;
  449. break;
  450. case 2:
  451. sample_rate = SAMPLING_RATE_32KHZ;
  452. break;
  453. case 3:
  454. sample_rate = SAMPLING_RATE_44P1KHZ;
  455. break;
  456. case 4:
  457. sample_rate = SAMPLING_RATE_48KHZ;
  458. break;
  459. case 5:
  460. sample_rate = SAMPLING_RATE_96KHZ;
  461. break;
  462. case 6:
  463. sample_rate = SAMPLING_RATE_192KHZ;
  464. break;
  465. case 7:
  466. sample_rate = SAMPLING_RATE_352P8KHZ;
  467. break;
  468. case 8:
  469. sample_rate = SAMPLING_RATE_384KHZ;
  470. break;
  471. default:
  472. sample_rate = SAMPLING_RATE_48KHZ;
  473. break;
  474. }
  475. return sample_rate;
  476. }
  477. static int tdm_get_sample_rate_val(int sample_rate)
  478. {
  479. int sample_rate_val = 0;
  480. switch (sample_rate) {
  481. case SAMPLING_RATE_8KHZ:
  482. sample_rate_val = 0;
  483. break;
  484. case SAMPLING_RATE_16KHZ:
  485. sample_rate_val = 1;
  486. break;
  487. case SAMPLING_RATE_32KHZ:
  488. sample_rate_val = 2;
  489. break;
  490. case SAMPLING_RATE_44P1KHZ:
  491. sample_rate_val = 3;
  492. break;
  493. case SAMPLING_RATE_48KHZ:
  494. sample_rate_val = 4;
  495. break;
  496. case SAMPLING_RATE_96KHZ:
  497. sample_rate_val = 5;
  498. break;
  499. case SAMPLING_RATE_192KHZ:
  500. sample_rate_val = 6;
  501. break;
  502. case SAMPLING_RATE_352P8KHZ:
  503. sample_rate_val = 7;
  504. break;
  505. case SAMPLING_RATE_384KHZ:
  506. sample_rate_val = 8;
  507. break;
  508. default:
  509. sample_rate_val = 4;
  510. break;
  511. }
  512. return sample_rate_val;
  513. }
  514. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  515. struct tdm_port *port)
  516. {
  517. if (port) {
  518. if (strnstr(kcontrol->id.name, "PRI",
  519. sizeof(kcontrol->id.name))) {
  520. port->mode = TDM_PRI;
  521. } else if (strnstr(kcontrol->id.name, "SEC",
  522. sizeof(kcontrol->id.name))) {
  523. port->mode = TDM_SEC;
  524. } else if (strnstr(kcontrol->id.name, "TERT",
  525. sizeof(kcontrol->id.name))) {
  526. port->mode = TDM_TERT;
  527. } else if (strnstr(kcontrol->id.name, "QUAT",
  528. sizeof(kcontrol->id.name))) {
  529. port->mode = TDM_QUAT;
  530. } else if (strnstr(kcontrol->id.name, "QUIN",
  531. sizeof(kcontrol->id.name))) {
  532. port->mode = TDM_QUIN;
  533. } else {
  534. pr_err("%s: unsupported mode in: %s",
  535. __func__, kcontrol->id.name);
  536. return -EINVAL;
  537. }
  538. if (strnstr(kcontrol->id.name, "RX_0",
  539. sizeof(kcontrol->id.name)) ||
  540. strnstr(kcontrol->id.name, "TX_0",
  541. sizeof(kcontrol->id.name))) {
  542. port->channel = TDM_0;
  543. } else if (strnstr(kcontrol->id.name, "RX_1",
  544. sizeof(kcontrol->id.name)) ||
  545. strnstr(kcontrol->id.name, "TX_1",
  546. sizeof(kcontrol->id.name))) {
  547. port->channel = TDM_1;
  548. } else if (strnstr(kcontrol->id.name, "RX_2",
  549. sizeof(kcontrol->id.name)) ||
  550. strnstr(kcontrol->id.name, "TX_2",
  551. sizeof(kcontrol->id.name))) {
  552. port->channel = TDM_2;
  553. } else if (strnstr(kcontrol->id.name, "RX_3",
  554. sizeof(kcontrol->id.name)) ||
  555. strnstr(kcontrol->id.name, "TX_3",
  556. sizeof(kcontrol->id.name))) {
  557. port->channel = TDM_3;
  558. } else if (strnstr(kcontrol->id.name, "RX_4",
  559. sizeof(kcontrol->id.name)) ||
  560. strnstr(kcontrol->id.name, "TX_4",
  561. sizeof(kcontrol->id.name))) {
  562. port->channel = TDM_4;
  563. } else if (strnstr(kcontrol->id.name, "RX_5",
  564. sizeof(kcontrol->id.name)) ||
  565. strnstr(kcontrol->id.name, "TX_5",
  566. sizeof(kcontrol->id.name))) {
  567. port->channel = TDM_5;
  568. } else if (strnstr(kcontrol->id.name, "RX_6",
  569. sizeof(kcontrol->id.name)) ||
  570. strnstr(kcontrol->id.name, "TX_6",
  571. sizeof(kcontrol->id.name))) {
  572. port->channel = TDM_6;
  573. } else if (strnstr(kcontrol->id.name, "RX_7",
  574. sizeof(kcontrol->id.name)) ||
  575. strnstr(kcontrol->id.name, "TX_7",
  576. sizeof(kcontrol->id.name))) {
  577. port->channel = TDM_7;
  578. } else {
  579. pr_err("%s: unsupported channel in: %s",
  580. __func__, kcontrol->id.name);
  581. return -EINVAL;
  582. }
  583. } else
  584. return -EINVAL;
  585. return 0;
  586. }
  587. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  588. struct snd_ctl_elem_value *ucontrol)
  589. {
  590. struct tdm_port port;
  591. int ret = tdm_get_port_idx(kcontrol, &port);
  592. if (ret) {
  593. pr_err("%s: unsupported control: %s",
  594. __func__, kcontrol->id.name);
  595. } else {
  596. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  597. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  598. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  599. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  600. ucontrol->value.enumerated.item[0]);
  601. }
  602. return ret;
  603. }
  604. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  605. struct snd_ctl_elem_value *ucontrol)
  606. {
  607. struct tdm_port port;
  608. int ret = tdm_get_port_idx(kcontrol, &port);
  609. if (ret) {
  610. pr_err("%s: unsupported control: %s",
  611. __func__, kcontrol->id.name);
  612. } else {
  613. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  614. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  615. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  616. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  617. ucontrol->value.enumerated.item[0]);
  618. }
  619. return ret;
  620. }
  621. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  622. struct snd_ctl_elem_value *ucontrol)
  623. {
  624. struct tdm_port port;
  625. int ret = tdm_get_port_idx(kcontrol, &port);
  626. if (ret) {
  627. pr_err("%s: unsupported control: %s",
  628. __func__, kcontrol->id.name);
  629. } else {
  630. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  631. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  632. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  633. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  634. ucontrol->value.enumerated.item[0]);
  635. }
  636. return ret;
  637. }
  638. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  639. struct snd_ctl_elem_value *ucontrol)
  640. {
  641. struct tdm_port port;
  642. int ret = tdm_get_port_idx(kcontrol, &port);
  643. if (ret) {
  644. pr_err("%s: unsupported control: %s",
  645. __func__, kcontrol->id.name);
  646. } else {
  647. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  648. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  649. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  650. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  651. ucontrol->value.enumerated.item[0]);
  652. }
  653. return ret;
  654. }
  655. static int tdm_get_format(int value)
  656. {
  657. int format = 0;
  658. switch (value) {
  659. case 0:
  660. format = SNDRV_PCM_FORMAT_S16_LE;
  661. break;
  662. case 1:
  663. format = SNDRV_PCM_FORMAT_S24_LE;
  664. break;
  665. case 2:
  666. format = SNDRV_PCM_FORMAT_S32_LE;
  667. break;
  668. default:
  669. format = SNDRV_PCM_FORMAT_S16_LE;
  670. break;
  671. }
  672. return format;
  673. }
  674. static int tdm_get_format_val(int format)
  675. {
  676. int value = 0;
  677. switch (format) {
  678. case SNDRV_PCM_FORMAT_S16_LE:
  679. value = 0;
  680. break;
  681. case SNDRV_PCM_FORMAT_S24_LE:
  682. value = 1;
  683. break;
  684. case SNDRV_PCM_FORMAT_S32_LE:
  685. value = 2;
  686. break;
  687. default:
  688. value = 0;
  689. break;
  690. }
  691. return value;
  692. }
  693. static int mi2s_get_format(int value)
  694. {
  695. int format = 0;
  696. switch (value) {
  697. case 0:
  698. format = SNDRV_PCM_FORMAT_S16_LE;
  699. break;
  700. case 1:
  701. format = SNDRV_PCM_FORMAT_S24_LE;
  702. break;
  703. case 2:
  704. format = SNDRV_PCM_FORMAT_S24_3LE;
  705. break;
  706. case 3:
  707. format = SNDRV_PCM_FORMAT_S32_LE;
  708. break;
  709. default:
  710. format = SNDRV_PCM_FORMAT_S16_LE;
  711. break;
  712. }
  713. return format;
  714. }
  715. static int mi2s_get_format_value(int format)
  716. {
  717. int value = 0;
  718. switch (format) {
  719. case SNDRV_PCM_FORMAT_S16_LE:
  720. value = 0;
  721. break;
  722. case SNDRV_PCM_FORMAT_S24_LE:
  723. value = 1;
  724. break;
  725. case SNDRV_PCM_FORMAT_S24_3LE:
  726. value = 2;
  727. break;
  728. case SNDRV_PCM_FORMAT_S32_LE:
  729. value = 3;
  730. break;
  731. default:
  732. value = 0;
  733. break;
  734. }
  735. return value;
  736. }
  737. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  738. struct snd_ctl_elem_value *ucontrol)
  739. {
  740. struct tdm_port port;
  741. int ret = tdm_get_port_idx(kcontrol, &port);
  742. if (ret) {
  743. pr_err("%s: unsupported control: %s",
  744. __func__, kcontrol->id.name);
  745. } else {
  746. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  747. tdm_rx_cfg[port.mode][port.channel].bit_format);
  748. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  749. tdm_rx_cfg[port.mode][port.channel].bit_format,
  750. ucontrol->value.enumerated.item[0]);
  751. }
  752. return ret;
  753. }
  754. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  755. struct snd_ctl_elem_value *ucontrol)
  756. {
  757. struct tdm_port port;
  758. int ret = tdm_get_port_idx(kcontrol, &port);
  759. if (ret) {
  760. pr_err("%s: unsupported control: %s",
  761. __func__, kcontrol->id.name);
  762. } else {
  763. tdm_rx_cfg[port.mode][port.channel].bit_format =
  764. tdm_get_format(ucontrol->value.enumerated.item[0]);
  765. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  766. tdm_rx_cfg[port.mode][port.channel].bit_format,
  767. ucontrol->value.enumerated.item[0]);
  768. }
  769. return ret;
  770. }
  771. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  772. struct snd_ctl_elem_value *ucontrol)
  773. {
  774. struct tdm_port port;
  775. int ret = tdm_get_port_idx(kcontrol, &port);
  776. if (ret) {
  777. pr_err("%s: unsupported control: %s",
  778. __func__, kcontrol->id.name);
  779. } else {
  780. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  781. tdm_tx_cfg[port.mode][port.channel].bit_format);
  782. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  783. tdm_tx_cfg[port.mode][port.channel].bit_format,
  784. ucontrol->value.enumerated.item[0]);
  785. }
  786. return ret;
  787. }
  788. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  789. struct snd_ctl_elem_value *ucontrol)
  790. {
  791. struct tdm_port port;
  792. int ret = tdm_get_port_idx(kcontrol, &port);
  793. if (ret) {
  794. pr_err("%s: unsupported control: %s",
  795. __func__, kcontrol->id.name);
  796. } else {
  797. tdm_tx_cfg[port.mode][port.channel].bit_format =
  798. tdm_get_format(ucontrol->value.enumerated.item[0]);
  799. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  800. tdm_tx_cfg[port.mode][port.channel].bit_format,
  801. ucontrol->value.enumerated.item[0]);
  802. }
  803. return ret;
  804. }
  805. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  806. struct snd_ctl_elem_value *ucontrol)
  807. {
  808. struct tdm_port port;
  809. int ret = tdm_get_port_idx(kcontrol, &port);
  810. if (ret) {
  811. pr_err("%s: unsupported control: %s",
  812. __func__, kcontrol->id.name);
  813. } else {
  814. ucontrol->value.enumerated.item[0] =
  815. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  816. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  817. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  818. ucontrol->value.enumerated.item[0]);
  819. }
  820. return ret;
  821. }
  822. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  823. struct snd_ctl_elem_value *ucontrol)
  824. {
  825. struct tdm_port port;
  826. int ret = tdm_get_port_idx(kcontrol, &port);
  827. if (ret) {
  828. pr_err("%s: unsupported control: %s",
  829. __func__, kcontrol->id.name);
  830. } else {
  831. tdm_rx_cfg[port.mode][port.channel].channels =
  832. ucontrol->value.enumerated.item[0] + 1;
  833. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  834. tdm_rx_cfg[port.mode][port.channel].channels,
  835. ucontrol->value.enumerated.item[0] + 1);
  836. }
  837. return ret;
  838. }
  839. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  840. struct snd_ctl_elem_value *ucontrol)
  841. {
  842. struct tdm_port port;
  843. int ret = tdm_get_port_idx(kcontrol, &port);
  844. if (ret) {
  845. pr_err("%s: unsupported control: %s",
  846. __func__, kcontrol->id.name);
  847. } else {
  848. ucontrol->value.enumerated.item[0] =
  849. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  850. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  851. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  852. ucontrol->value.enumerated.item[0]);
  853. }
  854. return ret;
  855. }
  856. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  857. struct snd_ctl_elem_value *ucontrol)
  858. {
  859. struct tdm_port port;
  860. int ret = tdm_get_port_idx(kcontrol, &port);
  861. if (ret) {
  862. pr_err("%s: unsupported control: %s",
  863. __func__, kcontrol->id.name);
  864. } else {
  865. tdm_tx_cfg[port.mode][port.channel].channels =
  866. ucontrol->value.enumerated.item[0] + 1;
  867. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  868. tdm_tx_cfg[port.mode][port.channel].channels,
  869. ucontrol->value.enumerated.item[0] + 1);
  870. }
  871. return ret;
  872. }
  873. static int aux_pcm_get_sample_rate(int value)
  874. {
  875. int sample_rate;
  876. switch (value) {
  877. case 1:
  878. sample_rate = SAMPLING_RATE_16KHZ;
  879. break;
  880. case 0:
  881. default:
  882. sample_rate = SAMPLING_RATE_8KHZ;
  883. break;
  884. }
  885. return sample_rate;
  886. }
  887. static int aux_pcm_get_sample_rate_val(int sample_rate)
  888. {
  889. int sample_rate_val;
  890. switch (sample_rate) {
  891. case SAMPLING_RATE_16KHZ:
  892. sample_rate_val = 1;
  893. break;
  894. case SAMPLING_RATE_8KHZ:
  895. default:
  896. sample_rate_val = 0;
  897. break;
  898. }
  899. return sample_rate_val;
  900. }
  901. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  902. {
  903. int idx;
  904. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  905. sizeof("PRIM_AUX_PCM")))
  906. idx = PRIM_AUX_PCM;
  907. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  908. sizeof("SEC_AUX_PCM")))
  909. idx = SEC_AUX_PCM;
  910. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  911. sizeof("TERT_AUX_PCM")))
  912. idx = TERT_AUX_PCM;
  913. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  914. sizeof("QUAT_AUX_PCM")))
  915. idx = QUAT_AUX_PCM;
  916. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  917. sizeof("QUIN_AUX_PCM")))
  918. idx = QUIN_AUX_PCM;
  919. else {
  920. pr_err("%s: unsupported port: %s",
  921. __func__, kcontrol->id.name);
  922. idx = -EINVAL;
  923. }
  924. return idx;
  925. }
  926. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  927. struct snd_ctl_elem_value *ucontrol)
  928. {
  929. int idx = aux_pcm_get_port_idx(kcontrol);
  930. if (idx < 0)
  931. return idx;
  932. aux_pcm_rx_cfg[idx].sample_rate =
  933. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  934. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  935. idx, aux_pcm_rx_cfg[idx].sample_rate,
  936. ucontrol->value.enumerated.item[0]);
  937. return 0;
  938. }
  939. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  940. struct snd_ctl_elem_value *ucontrol)
  941. {
  942. int idx = aux_pcm_get_port_idx(kcontrol);
  943. if (idx < 0)
  944. return idx;
  945. ucontrol->value.enumerated.item[0] =
  946. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  947. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  948. idx, aux_pcm_rx_cfg[idx].sample_rate,
  949. ucontrol->value.enumerated.item[0]);
  950. return 0;
  951. }
  952. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  953. struct snd_ctl_elem_value *ucontrol)
  954. {
  955. int idx = aux_pcm_get_port_idx(kcontrol);
  956. if (idx < 0)
  957. return idx;
  958. aux_pcm_tx_cfg[idx].sample_rate =
  959. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  960. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  961. idx, aux_pcm_tx_cfg[idx].sample_rate,
  962. ucontrol->value.enumerated.item[0]);
  963. return 0;
  964. }
  965. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  966. struct snd_ctl_elem_value *ucontrol)
  967. {
  968. int idx = aux_pcm_get_port_idx(kcontrol);
  969. if (idx < 0)
  970. return idx;
  971. ucontrol->value.enumerated.item[0] =
  972. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  973. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  974. idx, aux_pcm_tx_cfg[idx].sample_rate,
  975. ucontrol->value.enumerated.item[0]);
  976. return 0;
  977. }
  978. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  979. {
  980. int idx;
  981. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  982. sizeof("PRIM_MI2S_RX")))
  983. idx = PRIM_MI2S;
  984. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  985. sizeof("SEC_MI2S_RX")))
  986. idx = SEC_MI2S;
  987. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  988. sizeof("TERT_MI2S_RX")))
  989. idx = TERT_MI2S;
  990. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  991. sizeof("QUAT_MI2S_RX")))
  992. idx = QUAT_MI2S;
  993. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  994. sizeof("QUIN_MI2S_RX")))
  995. idx = QUIN_MI2S;
  996. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  997. sizeof("PRIM_MI2S_TX")))
  998. idx = PRIM_MI2S;
  999. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1000. sizeof("SEC_MI2S_TX")))
  1001. idx = SEC_MI2S;
  1002. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1003. sizeof("TERT_MI2S_TX")))
  1004. idx = TERT_MI2S;
  1005. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1006. sizeof("QUAT_MI2S_TX")))
  1007. idx = QUAT_MI2S;
  1008. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  1009. sizeof("QUIN_MI2S_TX")))
  1010. idx = QUIN_MI2S;
  1011. else {
  1012. pr_err("%s: unsupported channel: %s",
  1013. __func__, kcontrol->id.name);
  1014. idx = -EINVAL;
  1015. }
  1016. return idx;
  1017. }
  1018. static int mi2s_get_sample_rate_val(int sample_rate)
  1019. {
  1020. int sample_rate_val;
  1021. switch (sample_rate) {
  1022. case SAMPLING_RATE_8KHZ:
  1023. sample_rate_val = 0;
  1024. break;
  1025. case SAMPLING_RATE_16KHZ:
  1026. sample_rate_val = 1;
  1027. break;
  1028. case SAMPLING_RATE_32KHZ:
  1029. sample_rate_val = 2;
  1030. break;
  1031. case SAMPLING_RATE_44P1KHZ:
  1032. sample_rate_val = 3;
  1033. break;
  1034. case SAMPLING_RATE_48KHZ:
  1035. sample_rate_val = 4;
  1036. break;
  1037. case SAMPLING_RATE_96KHZ:
  1038. sample_rate_val = 5;
  1039. break;
  1040. case SAMPLING_RATE_192KHZ:
  1041. sample_rate_val = 6;
  1042. break;
  1043. default:
  1044. sample_rate_val = 4;
  1045. break;
  1046. }
  1047. return sample_rate_val;
  1048. }
  1049. static int mi2s_get_sample_rate(int value)
  1050. {
  1051. int sample_rate;
  1052. switch (value) {
  1053. case 0:
  1054. sample_rate = SAMPLING_RATE_8KHZ;
  1055. break;
  1056. case 1:
  1057. sample_rate = SAMPLING_RATE_16KHZ;
  1058. break;
  1059. case 2:
  1060. sample_rate = SAMPLING_RATE_32KHZ;
  1061. break;
  1062. case 3:
  1063. sample_rate = SAMPLING_RATE_44P1KHZ;
  1064. break;
  1065. case 4:
  1066. sample_rate = SAMPLING_RATE_48KHZ;
  1067. break;
  1068. case 5:
  1069. sample_rate = SAMPLING_RATE_96KHZ;
  1070. break;
  1071. case 6:
  1072. sample_rate = SAMPLING_RATE_192KHZ;
  1073. break;
  1074. default:
  1075. sample_rate = SAMPLING_RATE_48KHZ;
  1076. break;
  1077. }
  1078. return sample_rate;
  1079. }
  1080. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1081. struct snd_ctl_elem_value *ucontrol)
  1082. {
  1083. int idx = mi2s_get_port_idx(kcontrol);
  1084. if (idx < 0)
  1085. return idx;
  1086. mi2s_rx_cfg[idx].sample_rate =
  1087. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1088. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1089. idx, mi2s_rx_cfg[idx].sample_rate,
  1090. ucontrol->value.enumerated.item[0]);
  1091. return 0;
  1092. }
  1093. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1094. struct snd_ctl_elem_value *ucontrol)
  1095. {
  1096. int idx = mi2s_get_port_idx(kcontrol);
  1097. if (idx < 0)
  1098. return idx;
  1099. ucontrol->value.enumerated.item[0] =
  1100. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1101. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1102. idx, mi2s_rx_cfg[idx].sample_rate,
  1103. ucontrol->value.enumerated.item[0]);
  1104. return 0;
  1105. }
  1106. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1107. struct snd_ctl_elem_value *ucontrol)
  1108. {
  1109. int idx = mi2s_get_port_idx(kcontrol);
  1110. if (idx < 0)
  1111. return idx;
  1112. mi2s_tx_cfg[idx].sample_rate =
  1113. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1114. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1115. idx, mi2s_tx_cfg[idx].sample_rate,
  1116. ucontrol->value.enumerated.item[0]);
  1117. return 0;
  1118. }
  1119. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1120. struct snd_ctl_elem_value *ucontrol)
  1121. {
  1122. int idx = mi2s_get_port_idx(kcontrol);
  1123. if (idx < 0)
  1124. return idx;
  1125. ucontrol->value.enumerated.item[0] =
  1126. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1127. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1128. idx, mi2s_tx_cfg[idx].sample_rate,
  1129. ucontrol->value.enumerated.item[0]);
  1130. return 0;
  1131. }
  1132. static int mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1133. struct snd_ctl_elem_value *ucontrol)
  1134. {
  1135. int idx = mi2s_get_port_idx(kcontrol);
  1136. if (idx < 0)
  1137. return idx;
  1138. mi2s_tx_cfg[idx].bit_format =
  1139. mi2s_get_format(ucontrol->value.enumerated.item[0]);
  1140. pr_debug("%s: idx[%d] _tx_format = %d, item = %d\n", __func__,
  1141. idx, mi2s_tx_cfg[idx].bit_format,
  1142. ucontrol->value.enumerated.item[0]);
  1143. return 0;
  1144. }
  1145. static int mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1146. struct snd_ctl_elem_value *ucontrol)
  1147. {
  1148. int idx = mi2s_get_port_idx(kcontrol);
  1149. if (idx < 0)
  1150. return idx;
  1151. ucontrol->value.enumerated.item[0] =
  1152. mi2s_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1153. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1154. idx, mi2s_tx_cfg[idx].bit_format,
  1155. ucontrol->value.enumerated.item[0]);
  1156. return 0;
  1157. }
  1158. static int mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1159. struct snd_ctl_elem_value *ucontrol)
  1160. {
  1161. int idx = mi2s_get_port_idx(kcontrol);
  1162. if (idx < 0)
  1163. return idx;
  1164. mi2s_rx_cfg[idx].bit_format =
  1165. mi2s_get_format(ucontrol->value.enumerated.item[0]);
  1166. pr_debug("%s: idx[%d] _rx_format = %d, item = %d\n", __func__,
  1167. idx, mi2s_rx_cfg[idx].bit_format,
  1168. ucontrol->value.enumerated.item[0]);
  1169. return 0;
  1170. }
  1171. static int mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1172. struct snd_ctl_elem_value *ucontrol)
  1173. {
  1174. int idx = mi2s_get_port_idx(kcontrol);
  1175. if (idx < 0)
  1176. return idx;
  1177. ucontrol->value.enumerated.item[0] =
  1178. mi2s_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1179. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1180. idx, mi2s_rx_cfg[idx].bit_format,
  1181. ucontrol->value.enumerated.item[0]);
  1182. return 0;
  1183. }
  1184. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1185. struct snd_ctl_elem_value *ucontrol)
  1186. {
  1187. int idx = mi2s_get_port_idx(kcontrol);
  1188. if (idx < 0)
  1189. return idx;
  1190. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1191. idx, mi2s_rx_cfg[idx].channels);
  1192. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1193. return 0;
  1194. }
  1195. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1196. struct snd_ctl_elem_value *ucontrol)
  1197. {
  1198. int idx = mi2s_get_port_idx(kcontrol);
  1199. if (idx < 0)
  1200. return idx;
  1201. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1202. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1203. idx, mi2s_rx_cfg[idx].channels);
  1204. return 1;
  1205. }
  1206. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  1207. struct snd_ctl_elem_value *ucontrol)
  1208. {
  1209. int idx = mi2s_get_port_idx(kcontrol);
  1210. if (idx < 0)
  1211. return idx;
  1212. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1213. idx, mi2s_tx_cfg[idx].channels);
  1214. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  1215. return 0;
  1216. }
  1217. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  1218. struct snd_ctl_elem_value *ucontrol)
  1219. {
  1220. int idx = mi2s_get_port_idx(kcontrol);
  1221. if (idx < 0)
  1222. return idx;
  1223. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1224. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1225. idx, mi2s_tx_cfg[idx].channels);
  1226. return 1;
  1227. }
  1228. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1229. struct snd_ctl_elem_value *ucontrol)
  1230. {
  1231. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1232. usb_rx_cfg.channels);
  1233. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1234. return 0;
  1235. }
  1236. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1237. struct snd_ctl_elem_value *ucontrol)
  1238. {
  1239. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1240. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1241. return 1;
  1242. }
  1243. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1244. struct snd_ctl_elem_value *ucontrol)
  1245. {
  1246. int sample_rate_val;
  1247. switch (usb_rx_cfg.sample_rate) {
  1248. case SAMPLING_RATE_384KHZ:
  1249. sample_rate_val = 9;
  1250. break;
  1251. case SAMPLING_RATE_192KHZ:
  1252. sample_rate_val = 8;
  1253. break;
  1254. case SAMPLING_RATE_96KHZ:
  1255. sample_rate_val = 7;
  1256. break;
  1257. case SAMPLING_RATE_48KHZ:
  1258. sample_rate_val = 6;
  1259. break;
  1260. case SAMPLING_RATE_44P1KHZ:
  1261. sample_rate_val = 5;
  1262. break;
  1263. case SAMPLING_RATE_32KHZ:
  1264. sample_rate_val = 4;
  1265. break;
  1266. case SAMPLING_RATE_22P05KHZ:
  1267. sample_rate_val = 3;
  1268. break;
  1269. case SAMPLING_RATE_16KHZ:
  1270. sample_rate_val = 2;
  1271. break;
  1272. case SAMPLING_RATE_11P025KHZ:
  1273. sample_rate_val = 1;
  1274. break;
  1275. case SAMPLING_RATE_8KHZ:
  1276. default:
  1277. sample_rate_val = 0;
  1278. break;
  1279. }
  1280. ucontrol->value.integer.value[0] = sample_rate_val;
  1281. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1282. usb_rx_cfg.sample_rate);
  1283. return 0;
  1284. }
  1285. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1286. struct snd_ctl_elem_value *ucontrol)
  1287. {
  1288. switch (ucontrol->value.integer.value[0]) {
  1289. case 9:
  1290. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1291. break;
  1292. case 8:
  1293. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1294. break;
  1295. case 7:
  1296. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1297. break;
  1298. case 6:
  1299. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1300. break;
  1301. case 5:
  1302. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1303. break;
  1304. case 4:
  1305. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1306. break;
  1307. case 3:
  1308. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1309. break;
  1310. case 2:
  1311. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1312. break;
  1313. case 1:
  1314. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1315. break;
  1316. case 0:
  1317. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1318. break;
  1319. default:
  1320. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1321. break;
  1322. }
  1323. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1324. __func__, ucontrol->value.integer.value[0],
  1325. usb_rx_cfg.sample_rate);
  1326. return 0;
  1327. }
  1328. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1329. struct snd_ctl_elem_value *ucontrol)
  1330. {
  1331. switch (usb_rx_cfg.bit_format) {
  1332. case SNDRV_PCM_FORMAT_S32_LE:
  1333. ucontrol->value.integer.value[0] = 3;
  1334. break;
  1335. case SNDRV_PCM_FORMAT_S24_3LE:
  1336. ucontrol->value.integer.value[0] = 2;
  1337. break;
  1338. case SNDRV_PCM_FORMAT_S24_LE:
  1339. ucontrol->value.integer.value[0] = 1;
  1340. break;
  1341. case SNDRV_PCM_FORMAT_S16_LE:
  1342. default:
  1343. ucontrol->value.integer.value[0] = 0;
  1344. break;
  1345. }
  1346. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1347. __func__, usb_rx_cfg.bit_format,
  1348. ucontrol->value.integer.value[0]);
  1349. return 0;
  1350. }
  1351. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1352. struct snd_ctl_elem_value *ucontrol)
  1353. {
  1354. int rc = 0;
  1355. switch (ucontrol->value.integer.value[0]) {
  1356. case 3:
  1357. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1358. break;
  1359. case 2:
  1360. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1361. break;
  1362. case 1:
  1363. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1364. break;
  1365. case 0:
  1366. default:
  1367. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1368. break;
  1369. }
  1370. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1371. __func__, usb_rx_cfg.bit_format,
  1372. ucontrol->value.integer.value[0]);
  1373. return rc;
  1374. }
  1375. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1376. struct snd_ctl_elem_value *ucontrol)
  1377. {
  1378. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1379. usb_tx_cfg.channels);
  1380. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1381. return 0;
  1382. }
  1383. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1384. struct snd_ctl_elem_value *ucontrol)
  1385. {
  1386. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1387. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1388. return 1;
  1389. }
  1390. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1391. struct snd_ctl_elem_value *ucontrol)
  1392. {
  1393. int sample_rate_val;
  1394. switch (usb_tx_cfg.sample_rate) {
  1395. case SAMPLING_RATE_384KHZ:
  1396. sample_rate_val = 9;
  1397. break;
  1398. case SAMPLING_RATE_192KHZ:
  1399. sample_rate_val = 8;
  1400. break;
  1401. case SAMPLING_RATE_96KHZ:
  1402. sample_rate_val = 7;
  1403. break;
  1404. case SAMPLING_RATE_48KHZ:
  1405. sample_rate_val = 6;
  1406. break;
  1407. case SAMPLING_RATE_44P1KHZ:
  1408. sample_rate_val = 5;
  1409. break;
  1410. case SAMPLING_RATE_32KHZ:
  1411. sample_rate_val = 4;
  1412. break;
  1413. case SAMPLING_RATE_22P05KHZ:
  1414. sample_rate_val = 3;
  1415. break;
  1416. case SAMPLING_RATE_16KHZ:
  1417. sample_rate_val = 2;
  1418. break;
  1419. case SAMPLING_RATE_11P025KHZ:
  1420. sample_rate_val = 1;
  1421. break;
  1422. case SAMPLING_RATE_8KHZ:
  1423. sample_rate_val = 0;
  1424. break;
  1425. default:
  1426. sample_rate_val = 6;
  1427. break;
  1428. }
  1429. ucontrol->value.integer.value[0] = sample_rate_val;
  1430. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1431. usb_tx_cfg.sample_rate);
  1432. return 0;
  1433. }
  1434. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1435. struct snd_ctl_elem_value *ucontrol)
  1436. {
  1437. switch (ucontrol->value.integer.value[0]) {
  1438. case 9:
  1439. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1440. break;
  1441. case 8:
  1442. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1443. break;
  1444. case 7:
  1445. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1446. break;
  1447. case 6:
  1448. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1449. break;
  1450. case 5:
  1451. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1452. break;
  1453. case 4:
  1454. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1455. break;
  1456. case 3:
  1457. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1458. break;
  1459. case 2:
  1460. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1461. break;
  1462. case 1:
  1463. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1464. break;
  1465. case 0:
  1466. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1467. break;
  1468. default:
  1469. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1470. break;
  1471. }
  1472. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1473. __func__, ucontrol->value.integer.value[0],
  1474. usb_tx_cfg.sample_rate);
  1475. return 0;
  1476. }
  1477. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1478. struct snd_ctl_elem_value *ucontrol)
  1479. {
  1480. switch (usb_tx_cfg.bit_format) {
  1481. case SNDRV_PCM_FORMAT_S32_LE:
  1482. ucontrol->value.integer.value[0] = 3;
  1483. break;
  1484. case SNDRV_PCM_FORMAT_S24_3LE:
  1485. ucontrol->value.integer.value[0] = 2;
  1486. break;
  1487. case SNDRV_PCM_FORMAT_S24_LE:
  1488. ucontrol->value.integer.value[0] = 1;
  1489. break;
  1490. case SNDRV_PCM_FORMAT_S16_LE:
  1491. default:
  1492. ucontrol->value.integer.value[0] = 0;
  1493. break;
  1494. }
  1495. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1496. __func__, usb_tx_cfg.bit_format,
  1497. ucontrol->value.integer.value[0]);
  1498. return 0;
  1499. }
  1500. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1501. struct snd_ctl_elem_value *ucontrol)
  1502. {
  1503. int rc = 0;
  1504. switch (ucontrol->value.integer.value[0]) {
  1505. case 3:
  1506. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1507. break;
  1508. case 2:
  1509. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1510. break;
  1511. case 1:
  1512. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1513. break;
  1514. case 0:
  1515. default:
  1516. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1517. break;
  1518. }
  1519. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1520. __func__, usb_tx_cfg.bit_format,
  1521. ucontrol->value.integer.value[0]);
  1522. return rc;
  1523. }
  1524. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1525. {
  1526. int idx;
  1527. if (strnstr(kcontrol->id.name, "Display Port RX",
  1528. sizeof("Display Port RX")))
  1529. idx = DP_RX_IDX;
  1530. else {
  1531. pr_err("%s: unsupported BE: %s",
  1532. __func__, kcontrol->id.name);
  1533. idx = -EINVAL;
  1534. }
  1535. return idx;
  1536. }
  1537. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1538. struct snd_ctl_elem_value *ucontrol)
  1539. {
  1540. int idx = ext_disp_get_port_idx(kcontrol);
  1541. if (idx < 0)
  1542. return idx;
  1543. switch (ext_disp_rx_cfg[idx].bit_format) {
  1544. case SNDRV_PCM_FORMAT_S24_LE:
  1545. ucontrol->value.integer.value[0] = 1;
  1546. break;
  1547. case SNDRV_PCM_FORMAT_S16_LE:
  1548. default:
  1549. ucontrol->value.integer.value[0] = 0;
  1550. break;
  1551. }
  1552. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1553. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1554. ucontrol->value.integer.value[0]);
  1555. return 0;
  1556. }
  1557. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1558. struct snd_ctl_elem_value *ucontrol)
  1559. {
  1560. int idx = ext_disp_get_port_idx(kcontrol);
  1561. if (idx < 0)
  1562. return idx;
  1563. switch (ucontrol->value.integer.value[0]) {
  1564. case 1:
  1565. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1566. break;
  1567. case 0:
  1568. default:
  1569. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1570. break;
  1571. }
  1572. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1573. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1574. ucontrol->value.integer.value[0]);
  1575. return 0;
  1576. }
  1577. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1578. struct snd_ctl_elem_value *ucontrol)
  1579. {
  1580. int idx = ext_disp_get_port_idx(kcontrol);
  1581. if (idx < 0)
  1582. return idx;
  1583. ucontrol->value.integer.value[0] =
  1584. ext_disp_rx_cfg[idx].channels - 2;
  1585. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1586. idx, ext_disp_rx_cfg[idx].channels);
  1587. return 0;
  1588. }
  1589. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1590. struct snd_ctl_elem_value *ucontrol)
  1591. {
  1592. int idx = ext_disp_get_port_idx(kcontrol);
  1593. if (idx < 0)
  1594. return idx;
  1595. ext_disp_rx_cfg[idx].channels =
  1596. ucontrol->value.integer.value[0] + 2;
  1597. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1598. idx, ext_disp_rx_cfg[idx].channels);
  1599. return 1;
  1600. }
  1601. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1602. struct snd_ctl_elem_value *ucontrol)
  1603. {
  1604. int sample_rate_val;
  1605. int idx = ext_disp_get_port_idx(kcontrol);
  1606. if (idx < 0)
  1607. return idx;
  1608. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1609. case SAMPLING_RATE_192KHZ:
  1610. sample_rate_val = 2;
  1611. break;
  1612. case SAMPLING_RATE_96KHZ:
  1613. sample_rate_val = 1;
  1614. break;
  1615. case SAMPLING_RATE_48KHZ:
  1616. default:
  1617. sample_rate_val = 0;
  1618. break;
  1619. }
  1620. ucontrol->value.integer.value[0] = sample_rate_val;
  1621. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1622. idx, ext_disp_rx_cfg[idx].sample_rate);
  1623. return 0;
  1624. }
  1625. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1626. struct snd_ctl_elem_value *ucontrol)
  1627. {
  1628. int idx = ext_disp_get_port_idx(kcontrol);
  1629. if (idx < 0)
  1630. return idx;
  1631. switch (ucontrol->value.integer.value[0]) {
  1632. case 2:
  1633. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1634. break;
  1635. case 1:
  1636. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1637. break;
  1638. case 0:
  1639. default:
  1640. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1641. break;
  1642. }
  1643. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1644. __func__, ucontrol->value.integer.value[0], idx,
  1645. ext_disp_rx_cfg[idx].sample_rate);
  1646. return 0;
  1647. }
  1648. const struct snd_kcontrol_new msm_common_snd_controls[] = {
  1649. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  1650. proxy_rx_ch_get, proxy_rx_ch_put),
  1651. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  1652. aux_pcm_rx_sample_rate_get,
  1653. aux_pcm_rx_sample_rate_put),
  1654. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  1655. aux_pcm_rx_sample_rate_get,
  1656. aux_pcm_rx_sample_rate_put),
  1657. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  1658. aux_pcm_rx_sample_rate_get,
  1659. aux_pcm_rx_sample_rate_put),
  1660. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  1661. aux_pcm_rx_sample_rate_get,
  1662. aux_pcm_rx_sample_rate_put),
  1663. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  1664. aux_pcm_rx_sample_rate_get,
  1665. aux_pcm_rx_sample_rate_put),
  1666. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  1667. aux_pcm_tx_sample_rate_get,
  1668. aux_pcm_tx_sample_rate_put),
  1669. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  1670. aux_pcm_tx_sample_rate_get,
  1671. aux_pcm_tx_sample_rate_put),
  1672. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  1673. aux_pcm_tx_sample_rate_get,
  1674. aux_pcm_tx_sample_rate_put),
  1675. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  1676. aux_pcm_tx_sample_rate_get,
  1677. aux_pcm_tx_sample_rate_put),
  1678. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  1679. aux_pcm_tx_sample_rate_get,
  1680. aux_pcm_tx_sample_rate_put),
  1681. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  1682. mi2s_rx_sample_rate_get,
  1683. mi2s_rx_sample_rate_put),
  1684. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  1685. mi2s_rx_sample_rate_get,
  1686. mi2s_rx_sample_rate_put),
  1687. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  1688. mi2s_rx_sample_rate_get,
  1689. mi2s_rx_sample_rate_put),
  1690. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  1691. mi2s_rx_sample_rate_get,
  1692. mi2s_rx_sample_rate_put),
  1693. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  1694. mi2s_rx_sample_rate_get,
  1695. mi2s_rx_sample_rate_put),
  1696. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  1697. mi2s_tx_sample_rate_get,
  1698. mi2s_tx_sample_rate_put),
  1699. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  1700. mi2s_tx_sample_rate_get,
  1701. mi2s_tx_sample_rate_put),
  1702. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  1703. mi2s_tx_sample_rate_get,
  1704. mi2s_tx_sample_rate_put),
  1705. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  1706. mi2s_tx_sample_rate_get,
  1707. mi2s_tx_sample_rate_put),
  1708. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  1709. mi2s_tx_sample_rate_get,
  1710. mi2s_tx_sample_rate_put),
  1711. SOC_ENUM_EXT("PRIM_MI2S_RX Format", prim_mi2s_rx_format,
  1712. mi2s_rx_format_get,
  1713. mi2s_rx_format_put),
  1714. SOC_ENUM_EXT("SEC_MI2S_RX Format", sec_mi2s_rx_format,
  1715. mi2s_rx_format_get,
  1716. mi2s_rx_format_put),
  1717. SOC_ENUM_EXT("TERT_MI2S_RX Format", tert_mi2s_rx_format,
  1718. mi2s_rx_format_get,
  1719. mi2s_rx_format_put),
  1720. SOC_ENUM_EXT("QUAT_MI2S_RX Format", quat_mi2s_rx_format,
  1721. mi2s_rx_format_get,
  1722. mi2s_rx_format_put),
  1723. SOC_ENUM_EXT("QUIN_MI2S_RX Format", quin_mi2s_rx_format,
  1724. mi2s_rx_format_get,
  1725. mi2s_rx_format_put),
  1726. SOC_ENUM_EXT("PRIM_MI2S_TX Format", prim_mi2s_tx_format,
  1727. mi2s_tx_format_get,
  1728. mi2s_tx_format_put),
  1729. SOC_ENUM_EXT("SEC_MI2S_TX Format", sec_mi2s_tx_format,
  1730. mi2s_tx_format_get,
  1731. mi2s_tx_format_put),
  1732. SOC_ENUM_EXT("TERT_MI2S_TX Format", tert_mi2s_tx_format,
  1733. mi2s_tx_format_get,
  1734. mi2s_tx_format_put),
  1735. SOC_ENUM_EXT("QUAT_MI2S_TX Format", quat_mi2s_tx_format,
  1736. mi2s_tx_format_get,
  1737. mi2s_tx_format_put),
  1738. SOC_ENUM_EXT("QUIN_MI2S_TX Format", quin_mi2s_tx_format,
  1739. mi2s_tx_format_get,
  1740. mi2s_tx_format_put),
  1741. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  1742. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1743. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  1744. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1745. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  1746. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1747. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  1748. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1749. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  1750. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1751. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  1752. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1753. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  1754. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1755. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  1756. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1757. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  1758. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1759. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  1760. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1761. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  1762. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  1763. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  1764. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  1765. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  1766. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  1767. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  1768. usb_audio_rx_format_get, usb_audio_rx_format_put),
  1769. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  1770. usb_audio_tx_format_get, usb_audio_tx_format_put),
  1771. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  1772. ext_disp_rx_format_get, ext_disp_rx_format_put),
  1773. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  1774. usb_audio_rx_sample_rate_get,
  1775. usb_audio_rx_sample_rate_put),
  1776. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  1777. usb_audio_tx_sample_rate_get,
  1778. usb_audio_tx_sample_rate_put),
  1779. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  1780. ext_disp_rx_sample_rate_get,
  1781. ext_disp_rx_sample_rate_put),
  1782. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1783. tdm_rx_sample_rate_get,
  1784. tdm_rx_sample_rate_put),
  1785. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1786. tdm_tx_sample_rate_get,
  1787. tdm_tx_sample_rate_put),
  1788. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  1789. tdm_rx_format_get,
  1790. tdm_rx_format_put),
  1791. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  1792. tdm_tx_format_get,
  1793. tdm_tx_format_put),
  1794. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  1795. tdm_rx_ch_get,
  1796. tdm_rx_ch_put),
  1797. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  1798. tdm_tx_ch_get,
  1799. tdm_tx_ch_put),
  1800. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1801. tdm_rx_sample_rate_get,
  1802. tdm_rx_sample_rate_put),
  1803. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1804. tdm_tx_sample_rate_get,
  1805. tdm_tx_sample_rate_put),
  1806. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  1807. tdm_rx_format_get,
  1808. tdm_rx_format_put),
  1809. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  1810. tdm_tx_format_get,
  1811. tdm_tx_format_put),
  1812. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  1813. tdm_rx_ch_get,
  1814. tdm_rx_ch_put),
  1815. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  1816. tdm_tx_ch_get,
  1817. tdm_tx_ch_put),
  1818. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1819. tdm_rx_sample_rate_get,
  1820. tdm_rx_sample_rate_put),
  1821. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1822. tdm_tx_sample_rate_get,
  1823. tdm_tx_sample_rate_put),
  1824. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  1825. tdm_rx_format_get,
  1826. tdm_rx_format_put),
  1827. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  1828. tdm_tx_format_get,
  1829. tdm_tx_format_put),
  1830. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  1831. tdm_rx_ch_get,
  1832. tdm_rx_ch_put),
  1833. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  1834. tdm_tx_ch_get,
  1835. tdm_tx_ch_put),
  1836. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1837. tdm_rx_sample_rate_get,
  1838. tdm_rx_sample_rate_put),
  1839. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1840. tdm_tx_sample_rate_get,
  1841. tdm_tx_sample_rate_put),
  1842. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  1843. tdm_rx_format_get,
  1844. tdm_rx_format_put),
  1845. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  1846. tdm_tx_format_get,
  1847. tdm_tx_format_put),
  1848. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  1849. tdm_rx_ch_get,
  1850. tdm_rx_ch_put),
  1851. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  1852. tdm_tx_ch_get,
  1853. tdm_tx_ch_put),
  1854. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1855. tdm_rx_sample_rate_get,
  1856. tdm_rx_sample_rate_put),
  1857. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1858. tdm_tx_sample_rate_get,
  1859. tdm_tx_sample_rate_put),
  1860. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  1861. tdm_rx_format_get,
  1862. tdm_rx_format_put),
  1863. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  1864. tdm_tx_format_get,
  1865. tdm_tx_format_put),
  1866. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  1867. tdm_rx_ch_get,
  1868. tdm_rx_ch_put),
  1869. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  1870. tdm_tx_ch_get,
  1871. tdm_tx_ch_put),
  1872. };
  1873. /**
  1874. * msm_common_snd_controls_size - to return controls size
  1875. *
  1876. * Return: returns size of common controls array
  1877. */
  1878. int msm_common_snd_controls_size(void)
  1879. {
  1880. return ARRAY_SIZE(msm_common_snd_controls);
  1881. }
  1882. EXPORT_SYMBOL(msm_common_snd_controls_size);
  1883. void msm_set_codec_reg_done(bool done)
  1884. {
  1885. codec_reg_done = done;
  1886. }
  1887. EXPORT_SYMBOL(msm_set_codec_reg_done);
  1888. static inline int param_is_mask(int p)
  1889. {
  1890. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  1891. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  1892. }
  1893. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  1894. int n)
  1895. {
  1896. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  1897. }
  1898. static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned int bit)
  1899. {
  1900. if (bit >= SNDRV_MASK_MAX)
  1901. return;
  1902. if (param_is_mask(n)) {
  1903. struct snd_mask *m = param_to_mask(p, n);
  1904. m->bits[0] = 0;
  1905. m->bits[1] = 0;
  1906. m->bits[bit >> 5] |= (1 << (bit & 31));
  1907. }
  1908. }
  1909. static int msm_ext_disp_get_idx_from_beid(int32_t id)
  1910. {
  1911. int idx;
  1912. switch (id) {
  1913. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  1914. idx = DP_RX_IDX;
  1915. break;
  1916. default:
  1917. pr_err("%s: Incorrect ext_disp id %d\n", __func__, id);
  1918. idx = -EINVAL;
  1919. break;
  1920. }
  1921. return idx;
  1922. }
  1923. /**
  1924. * msm_common_be_hw_params_fixup - updates settings of ALSA BE hw params.
  1925. *
  1926. * @rtd: runtime dailink instance
  1927. * @params: HW params of associated backend dailink.
  1928. *
  1929. * Returns 0.
  1930. */
  1931. int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  1932. struct snd_pcm_hw_params *params)
  1933. {
  1934. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  1935. struct snd_interval *rate = hw_param_interval(params,
  1936. SNDRV_PCM_HW_PARAM_RATE);
  1937. struct snd_interval *channels = hw_param_interval(params,
  1938. SNDRV_PCM_HW_PARAM_CHANNELS);
  1939. int rc = 0;
  1940. int idx;
  1941. pr_debug("%s: format = %d, rate = %d\n",
  1942. __func__, params_format(params), params_rate(params));
  1943. switch (dai_link->id) {
  1944. case MSM_BACKEND_DAI_USB_RX:
  1945. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1946. usb_rx_cfg.bit_format);
  1947. rate->min = rate->max = usb_rx_cfg.sample_rate;
  1948. channels->min = channels->max = usb_rx_cfg.channels;
  1949. break;
  1950. case MSM_BACKEND_DAI_USB_TX:
  1951. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1952. usb_tx_cfg.bit_format);
  1953. rate->min = rate->max = usb_tx_cfg.sample_rate;
  1954. channels->min = channels->max = usb_tx_cfg.channels;
  1955. break;
  1956. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  1957. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  1958. if (idx < 0) {
  1959. pr_err("%s: Incorrect ext disp idx %d\n",
  1960. __func__, idx);
  1961. rc = idx;
  1962. break;
  1963. }
  1964. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1965. ext_disp_rx_cfg[idx].bit_format);
  1966. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  1967. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  1968. break;
  1969. case MSM_BACKEND_DAI_AFE_PCM_RX:
  1970. channels->min = channels->max = proxy_rx_cfg.channels;
  1971. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  1972. break;
  1973. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  1974. channels->min = channels->max =
  1975. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  1976. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1977. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  1978. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  1979. break;
  1980. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  1981. channels->min = channels->max =
  1982. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  1983. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1984. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  1985. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  1986. break;
  1987. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  1988. channels->min = channels->max =
  1989. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  1990. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1991. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  1992. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  1993. break;
  1994. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  1995. channels->min = channels->max =
  1996. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  1997. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1998. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  1999. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  2000. break;
  2001. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  2002. channels->min = channels->max =
  2003. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  2004. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2005. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  2006. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  2007. break;
  2008. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  2009. channels->min = channels->max =
  2010. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  2011. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2012. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  2013. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  2014. break;
  2015. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  2016. channels->min = channels->max =
  2017. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  2018. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2019. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  2020. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2021. break;
  2022. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  2023. channels->min = channels->max =
  2024. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  2025. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2026. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  2027. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2028. break;
  2029. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  2030. channels->min = channels->max =
  2031. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  2032. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2033. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  2034. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  2035. break;
  2036. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  2037. channels->min = channels->max =
  2038. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  2039. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2040. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  2041. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  2042. break;
  2043. case MSM_BACKEND_DAI_AUXPCM_RX:
  2044. rate->min = rate->max =
  2045. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  2046. channels->min = channels->max =
  2047. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  2048. break;
  2049. case MSM_BACKEND_DAI_AUXPCM_TX:
  2050. rate->min = rate->max =
  2051. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  2052. channels->min = channels->max =
  2053. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  2054. break;
  2055. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  2056. rate->min = rate->max =
  2057. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  2058. channels->min = channels->max =
  2059. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  2060. break;
  2061. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  2062. rate->min = rate->max =
  2063. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  2064. channels->min = channels->max =
  2065. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  2066. break;
  2067. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  2068. rate->min = rate->max =
  2069. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  2070. channels->min = channels->max =
  2071. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  2072. break;
  2073. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  2074. rate->min = rate->max =
  2075. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  2076. channels->min = channels->max =
  2077. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  2078. break;
  2079. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  2080. rate->min = rate->max =
  2081. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  2082. channels->min = channels->max =
  2083. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  2084. break;
  2085. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  2086. rate->min = rate->max =
  2087. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  2088. channels->min = channels->max =
  2089. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  2090. break;
  2091. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  2092. rate->min = rate->max =
  2093. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  2094. channels->min = channels->max =
  2095. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  2096. break;
  2097. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  2098. rate->min = rate->max =
  2099. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  2100. channels->min = channels->max =
  2101. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  2102. break;
  2103. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2104. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  2105. channels->min = channels->max =
  2106. mi2s_rx_cfg[PRIM_MI2S].channels;
  2107. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2108. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  2109. break;
  2110. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2111. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  2112. channels->min = channels->max =
  2113. mi2s_tx_cfg[PRIM_MI2S].channels;
  2114. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2115. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  2116. break;
  2117. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2118. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  2119. channels->min = channels->max =
  2120. mi2s_rx_cfg[SEC_MI2S].channels;
  2121. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2122. mi2s_rx_cfg[SEC_MI2S].bit_format);
  2123. break;
  2124. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2125. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  2126. channels->min = channels->max =
  2127. mi2s_tx_cfg[SEC_MI2S].channels;
  2128. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2129. mi2s_tx_cfg[SEC_MI2S].bit_format);
  2130. break;
  2131. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2132. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  2133. channels->min = channels->max =
  2134. mi2s_rx_cfg[TERT_MI2S].channels;
  2135. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2136. mi2s_rx_cfg[TERT_MI2S].bit_format);
  2137. break;
  2138. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2139. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  2140. channels->min = channels->max =
  2141. mi2s_tx_cfg[TERT_MI2S].channels;
  2142. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2143. mi2s_tx_cfg[TERT_MI2S].bit_format);
  2144. break;
  2145. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2146. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  2147. channels->min = channels->max =
  2148. mi2s_rx_cfg[QUAT_MI2S].channels;
  2149. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2150. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  2151. break;
  2152. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2153. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  2154. channels->min = channels->max =
  2155. mi2s_tx_cfg[QUAT_MI2S].channels;
  2156. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2157. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  2158. break;
  2159. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2160. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  2161. channels->min = channels->max =
  2162. mi2s_rx_cfg[QUIN_MI2S].channels;
  2163. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2164. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  2165. break;
  2166. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2167. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  2168. channels->min = channels->max =
  2169. mi2s_tx_cfg[QUIN_MI2S].channels;
  2170. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2171. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  2172. break;
  2173. default:
  2174. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  2175. break;
  2176. }
  2177. return rc;
  2178. }
  2179. EXPORT_SYMBOL(msm_common_be_hw_params_fixup);
  2180. /**
  2181. * msm_aux_pcm_snd_startup - startup ops of auxpcm.
  2182. *
  2183. * @substream: PCM stream pointer of associated backend dailink
  2184. *
  2185. * Returns 0 on success or -EINVAL on error.
  2186. */
  2187. int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream)
  2188. {
  2189. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2190. dev_dbg(rtd->card->dev,
  2191. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2192. __func__, substream->name, substream->stream,
  2193. rtd->cpu_dai->name, rtd->cpu_dai->id);
  2194. return 0;
  2195. }
  2196. EXPORT_SYMBOL(msm_aux_pcm_snd_startup);
  2197. /**
  2198. * msm_aux_pcm_snd_shutdown - shutdown ops of auxpcm.
  2199. *
  2200. * @substream: PCM stream pointer of associated backend dailink
  2201. */
  2202. void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream)
  2203. {
  2204. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2205. dev_dbg(rtd->card->dev,
  2206. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2207. __func__,
  2208. substream->name, substream->stream,
  2209. rtd->cpu_dai->name, rtd->cpu_dai->id);
  2210. }
  2211. EXPORT_SYMBOL(msm_aux_pcm_snd_shutdown);
  2212. static int msm_get_port_id(int id)
  2213. {
  2214. int afe_port_id;
  2215. switch (id) {
  2216. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2217. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2218. break;
  2219. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2220. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2221. break;
  2222. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2223. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2224. break;
  2225. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2226. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2227. break;
  2228. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2229. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2230. break;
  2231. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2232. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2233. break;
  2234. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2235. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2236. break;
  2237. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2238. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2239. break;
  2240. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2241. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2242. break;
  2243. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2244. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2245. break;
  2246. default:
  2247. pr_err("%s: Invalid id: %d\n", __func__, id);
  2248. afe_port_id = -EINVAL;
  2249. }
  2250. return afe_port_id;
  2251. }
  2252. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2253. {
  2254. u32 bit_per_sample;
  2255. switch (bit_format) {
  2256. case SNDRV_PCM_FORMAT_S32_LE:
  2257. case SNDRV_PCM_FORMAT_S24_3LE:
  2258. case SNDRV_PCM_FORMAT_S24_LE:
  2259. bit_per_sample = 32;
  2260. break;
  2261. case SNDRV_PCM_FORMAT_S16_LE:
  2262. default:
  2263. bit_per_sample = 16;
  2264. break;
  2265. }
  2266. return bit_per_sample;
  2267. }
  2268. static void update_mi2s_clk_val(int dai_id, int stream)
  2269. {
  2270. u32 bit_per_sample;
  2271. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2272. bit_per_sample =
  2273. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2274. mi2s_clk[dai_id].clk_freq_in_hz =
  2275. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2276. } else {
  2277. bit_per_sample =
  2278. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2279. mi2s_clk[dai_id].clk_freq_in_hz =
  2280. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2281. }
  2282. }
  2283. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2284. {
  2285. int ret = 0;
  2286. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2287. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2288. int port_id = 0;
  2289. int index = cpu_dai->id;
  2290. port_id = msm_get_port_id(rtd->dai_link->id);
  2291. if (port_id < 0) {
  2292. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2293. ret = port_id;
  2294. goto done;
  2295. }
  2296. if (enable) {
  2297. update_mi2s_clk_val(index, substream->stream);
  2298. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2299. mi2s_clk[index].clk_freq_in_hz);
  2300. }
  2301. mi2s_clk[index].enable = enable;
  2302. ret = afe_set_lpass_clock_v2(port_id,
  2303. &mi2s_clk[index]);
  2304. if (ret < 0) {
  2305. dev_err(rtd->card->dev,
  2306. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2307. __func__, port_id, ret);
  2308. goto done;
  2309. }
  2310. done:
  2311. return ret;
  2312. }
  2313. /**
  2314. * msm_mi2s_snd_startup - startup ops of mi2s.
  2315. *
  2316. * @substream: PCM stream pointer of associated backend dailink
  2317. *
  2318. * Returns 0 on success or -EINVAL on error.
  2319. */
  2320. int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  2321. {
  2322. int ret = 0;
  2323. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2324. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2325. int port_id = msm_get_port_id(rtd->dai_link->id);
  2326. int index = cpu_dai->id;
  2327. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  2328. struct msm_asoc_mach_data *pdata =
  2329. snd_soc_card_get_drvdata(rtd->card);
  2330. dev_dbg(rtd->card->dev,
  2331. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2332. __func__, substream->name, substream->stream,
  2333. cpu_dai->name, cpu_dai->id);
  2334. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  2335. ret = -EINVAL;
  2336. dev_err(rtd->card->dev,
  2337. "%s: CPU DAI id (%d) out of range\n",
  2338. __func__, cpu_dai->id);
  2339. goto done;
  2340. }
  2341. /*
  2342. * Muxtex protection in case the same MI2S
  2343. * interface using for both TX and RX so
  2344. * that the same clock won't be enable twice.
  2345. */
  2346. mutex_lock(&mi2s_intf_conf[index].lock);
  2347. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  2348. /* Check if msm needs to provide the clock to the interface */
  2349. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  2350. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  2351. fmt = SND_SOC_DAIFMT_CBM_CFM;
  2352. }
  2353. ret = msm_mi2s_set_sclk(substream, true);
  2354. if (ret < 0) {
  2355. dev_err(rtd->card->dev,
  2356. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  2357. __func__, ret);
  2358. goto clean_up;
  2359. }
  2360. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  2361. if (ret < 0) {
  2362. dev_err(rtd->card->dev,
  2363. "%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  2364. __func__, index, ret);
  2365. goto clk_off;
  2366. }
  2367. if (mi2s_intf_conf[index].msm_is_ext_mclk) {
  2368. mi2s_mclk[index].enable = 1;
  2369. pr_debug("%s: Enabling mclk, clk_freq_in_hz = %u\n",
  2370. __func__, mi2s_mclk[index].clk_freq_in_hz);
  2371. ret = afe_set_lpass_clock_v2(port_id,
  2372. &mi2s_mclk[index]);
  2373. if (ret < 0) {
  2374. pr_err("%s: afe lpass mclk failed, err:%d\n",
  2375. __func__, ret);
  2376. goto clk_off;
  2377. }
  2378. }
  2379. if (pdata->mi2s_gpio_p[index])
  2380. msm_cdc_pinctrl_select_active_state(
  2381. pdata->mi2s_gpio_p[index]);
  2382. }
  2383. mutex_unlock(&mi2s_intf_conf[index].lock);
  2384. return 0;
  2385. clk_off:
  2386. if (ret < 0)
  2387. msm_mi2s_set_sclk(substream, false);
  2388. clean_up:
  2389. if (ret < 0)
  2390. mi2s_intf_conf[index].ref_cnt--;
  2391. mutex_unlock(&mi2s_intf_conf[index].lock);
  2392. done:
  2393. return ret;
  2394. }
  2395. EXPORT_SYMBOL(msm_mi2s_snd_startup);
  2396. /**
  2397. * msm_mi2s_snd_shutdown - shutdown ops of mi2s.
  2398. *
  2399. * @substream: PCM stream pointer of associated backend dailink
  2400. */
  2401. void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  2402. {
  2403. int ret;
  2404. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2405. int port_id = msm_get_port_id(rtd->dai_link->id);
  2406. int index = rtd->cpu_dai->id;
  2407. struct msm_asoc_mach_data *pdata =
  2408. snd_soc_card_get_drvdata(rtd->card);
  2409. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  2410. substream->name, substream->stream);
  2411. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  2412. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  2413. return;
  2414. }
  2415. mutex_lock(&mi2s_intf_conf[index].lock);
  2416. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  2417. if (pdata->mi2s_gpio_p[index])
  2418. msm_cdc_pinctrl_select_sleep_state(
  2419. pdata->mi2s_gpio_p[index]);
  2420. ret = msm_mi2s_set_sclk(substream, false);
  2421. if (ret < 0) {
  2422. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  2423. __func__, index, ret);
  2424. mi2s_intf_conf[index].ref_cnt++;
  2425. }
  2426. if (mi2s_intf_conf[index].msm_is_ext_mclk) {
  2427. mi2s_mclk[index].enable = 0;
  2428. pr_debug("%s: Disabling mclk, clk_freq_in_hz = %u\n",
  2429. __func__, mi2s_mclk[index].clk_freq_in_hz);
  2430. ret = afe_set_lpass_clock_v2(port_id,
  2431. &mi2s_mclk[index]);
  2432. if (ret < 0) {
  2433. pr_err("%s: mclk disable failed for MCLK (%d); ret=%d\n",
  2434. __func__, index, ret);
  2435. }
  2436. }
  2437. }
  2438. mutex_unlock(&mi2s_intf_conf[index].lock);
  2439. }
  2440. EXPORT_SYMBOL(msm_mi2s_snd_shutdown);
  2441. /* Validate whether US EU switch is present or not */
  2442. static int msm_prepare_us_euro(struct snd_soc_card *card)
  2443. {
  2444. struct msm_asoc_mach_data *pdata =
  2445. snd_soc_card_get_drvdata(card);
  2446. int ret = 0;
  2447. if (pdata->us_euro_gpio >= 0) {
  2448. dev_dbg(card->dev, "%s: us_euro gpio request %d", __func__,
  2449. pdata->us_euro_gpio);
  2450. ret = gpio_request(pdata->us_euro_gpio, "TASHA_CODEC_US_EURO");
  2451. if (ret) {
  2452. dev_err(card->dev,
  2453. "%s: Failed to request codec US/EURO gpio %d error %d\n",
  2454. __func__, pdata->us_euro_gpio, ret);
  2455. }
  2456. }
  2457. return ret;
  2458. }
  2459. static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active)
  2460. {
  2461. struct snd_soc_card *card = codec->component.card;
  2462. struct msm_asoc_mach_data *pdata =
  2463. snd_soc_card_get_drvdata(card);
  2464. int value = 0;
  2465. if (pdata->us_euro_gpio_p) {
  2466. value = msm_cdc_pinctrl_get_state(pdata->us_euro_gpio_p);
  2467. if (value)
  2468. msm_cdc_pinctrl_select_sleep_state(
  2469. pdata->us_euro_gpio_p);
  2470. else
  2471. msm_cdc_pinctrl_select_active_state(
  2472. pdata->us_euro_gpio_p);
  2473. } else if (pdata->us_euro_gpio >= 0) {
  2474. value = gpio_get_value_cansleep(pdata->us_euro_gpio);
  2475. gpio_set_value_cansleep(pdata->us_euro_gpio, !value);
  2476. }
  2477. pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value);
  2478. return true;
  2479. }
  2480. static int msm_populate_dai_link_component_of_node(
  2481. struct msm_asoc_mach_data *pdata,
  2482. struct snd_soc_card *card)
  2483. {
  2484. int i, index, ret = 0;
  2485. struct device *cdev = card->dev;
  2486. struct snd_soc_dai_link *dai_link = card->dai_link;
  2487. struct device_node *phandle;
  2488. if (!cdev) {
  2489. pr_err("%s: Sound card device memory NULL\n", __func__);
  2490. return -ENODEV;
  2491. }
  2492. for (i = 0; i < card->num_links; i++) {
  2493. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  2494. continue;
  2495. /* populate platform_of_node for snd card dai links */
  2496. if (dai_link[i].platform_name &&
  2497. !dai_link[i].platform_of_node) {
  2498. index = of_property_match_string(cdev->of_node,
  2499. "asoc-platform-names",
  2500. dai_link[i].platform_name);
  2501. if (index < 0) {
  2502. pr_err("%s: No match found for platform name: %s\n",
  2503. __func__, dai_link[i].platform_name);
  2504. ret = index;
  2505. goto cpu_dai;
  2506. }
  2507. phandle = of_parse_phandle(cdev->of_node,
  2508. "asoc-platform",
  2509. index);
  2510. if (!phandle) {
  2511. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  2512. __func__, dai_link[i].platform_name,
  2513. index);
  2514. ret = -ENODEV;
  2515. goto err;
  2516. }
  2517. dai_link[i].platform_of_node = phandle;
  2518. dai_link[i].platform_name = NULL;
  2519. }
  2520. cpu_dai:
  2521. /* populate cpu_of_node for snd card dai links */
  2522. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  2523. index = of_property_match_string(cdev->of_node,
  2524. "asoc-cpu-names",
  2525. dai_link[i].cpu_dai_name);
  2526. if (index < 0)
  2527. goto codec_dai;
  2528. phandle = of_parse_phandle(cdev->of_node, "asoc-cpu",
  2529. index);
  2530. if (!phandle) {
  2531. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  2532. __func__, dai_link[i].cpu_dai_name);
  2533. ret = -ENODEV;
  2534. goto err;
  2535. }
  2536. dai_link[i].cpu_of_node = phandle;
  2537. dai_link[i].cpu_dai_name = NULL;
  2538. }
  2539. codec_dai:
  2540. /* populate codec_of_node for snd card dai links */
  2541. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  2542. index = of_property_match_string(cdev->of_node,
  2543. "asoc-codec-names",
  2544. dai_link[i].codec_name);
  2545. if (index < 0)
  2546. continue;
  2547. phandle = of_parse_phandle(cdev->of_node, "asoc-codec",
  2548. index);
  2549. if (!phandle) {
  2550. pr_err("%s: retrieving phandle for codec dai %s failed\n",
  2551. __func__, dai_link[i].codec_name);
  2552. ret = -ENODEV;
  2553. goto err;
  2554. }
  2555. dai_link[i].codec_of_node = phandle;
  2556. dai_link[i].codec_name = NULL;
  2557. }
  2558. if (pdata->snd_card_val == INT_SND_CARD) {
  2559. if ((dai_link[i].id ==
  2560. MSM_BACKEND_DAI_INT0_MI2S_RX) ||
  2561. (dai_link[i].id ==
  2562. MSM_BACKEND_DAI_INT1_MI2S_RX) ||
  2563. (dai_link[i].id ==
  2564. MSM_BACKEND_DAI_INT2_MI2S_TX) ||
  2565. (dai_link[i].id ==
  2566. MSM_BACKEND_DAI_INT3_MI2S_TX)) {
  2567. index = of_property_match_string(cdev->of_node,
  2568. "asoc-codec-names",
  2569. MSM_INT_DIGITAL_CODEC);
  2570. phandle = of_parse_phandle(cdev->of_node,
  2571. "asoc-codec",
  2572. index);
  2573. dai_link[i].codecs[DIG_CDC].of_node = phandle;
  2574. index = of_property_match_string(cdev->of_node,
  2575. "asoc-codec-names",
  2576. PMIC_INT_ANALOG_CODEC);
  2577. phandle = of_parse_phandle(cdev->of_node,
  2578. "asoc-codec",
  2579. index);
  2580. dai_link[i].codecs[ANA_CDC].of_node = phandle;
  2581. }
  2582. }
  2583. }
  2584. err:
  2585. return ret;
  2586. }
  2587. static int msm_wsa881x_init(struct snd_soc_component *component)
  2588. {
  2589. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106};
  2590. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107};
  2591. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  2592. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  2593. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  2594. struct msm_asoc_mach_data *pdata;
  2595. struct snd_soc_dapm_context *dapm =
  2596. snd_soc_codec_get_dapm(codec);
  2597. if (!codec) {
  2598. pr_err("%s codec is NULL\n", __func__);
  2599. return -EINVAL;
  2600. }
  2601. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  2602. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  2603. __func__, codec->component.name);
  2604. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  2605. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  2606. &ch_rate[0]);
  2607. if (dapm->component) {
  2608. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  2609. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  2610. }
  2611. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  2612. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  2613. __func__, codec->component.name);
  2614. wsa881x_set_channel_map(codec, &spkright_ports[0],
  2615. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  2616. &ch_rate[0]);
  2617. if (dapm->component) {
  2618. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  2619. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  2620. }
  2621. } else {
  2622. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  2623. codec->component.name);
  2624. return -EINVAL;
  2625. }
  2626. pdata = snd_soc_card_get_drvdata(component->card);
  2627. if (pdata && pdata->codec_root)
  2628. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  2629. codec);
  2630. return 0;
  2631. }
  2632. static int msm_init_wsa_dev(struct platform_device *pdev,
  2633. struct snd_soc_card *card)
  2634. {
  2635. struct device_node *wsa_of_node;
  2636. u32 wsa_max_devs;
  2637. u32 wsa_dev_cnt;
  2638. char *dev_name_str = NULL;
  2639. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  2640. const char *wsa_auxdev_name_prefix[1];
  2641. int found = 0;
  2642. int i;
  2643. int ret;
  2644. /* Get maximum WSA device count for this platform */
  2645. ret = of_property_read_u32(pdev->dev.of_node,
  2646. "qcom,wsa-max-devs", &wsa_max_devs);
  2647. if (ret) {
  2648. dev_dbg(&pdev->dev,
  2649. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  2650. __func__, pdev->dev.of_node->full_name, ret);
  2651. goto err_dt;
  2652. }
  2653. if (wsa_max_devs == 0) {
  2654. dev_warn(&pdev->dev,
  2655. "%s: Max WSA devices is 0 for this target?\n",
  2656. __func__);
  2657. goto err_dt;
  2658. }
  2659. /* Get count of WSA device phandles for this platform */
  2660. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  2661. "qcom,wsa-devs", NULL);
  2662. if (wsa_dev_cnt == -ENOENT) {
  2663. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  2664. __func__);
  2665. goto err_dt;
  2666. } else if (wsa_dev_cnt <= 0) {
  2667. dev_err(&pdev->dev,
  2668. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  2669. __func__, wsa_dev_cnt);
  2670. ret = -EINVAL;
  2671. goto err_dt;
  2672. }
  2673. /*
  2674. * Expect total phandles count to be NOT less than maximum possible
  2675. * WSA count. However, if it is less, then assign same value to
  2676. * max count as well.
  2677. */
  2678. if (wsa_dev_cnt < wsa_max_devs) {
  2679. dev_dbg(&pdev->dev,
  2680. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  2681. __func__, wsa_max_devs, wsa_dev_cnt);
  2682. wsa_max_devs = wsa_dev_cnt;
  2683. }
  2684. /* Make sure prefix string passed for each WSA device */
  2685. ret = of_property_count_strings(pdev->dev.of_node,
  2686. "qcom,wsa-aux-dev-prefix");
  2687. if (ret != wsa_dev_cnt) {
  2688. dev_err(&pdev->dev,
  2689. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  2690. __func__, wsa_dev_cnt, ret);
  2691. ret = -EINVAL;
  2692. goto err_dt;
  2693. }
  2694. /*
  2695. * Alloc mem to store phandle and index info of WSA device, if already
  2696. * registered with ALSA core
  2697. */
  2698. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  2699. sizeof(struct msm_wsa881x_dev_info),
  2700. GFP_KERNEL);
  2701. if (!wsa881x_dev_info) {
  2702. ret = -ENOMEM;
  2703. goto err_mem;
  2704. }
  2705. /*
  2706. * search and check whether all WSA devices are already
  2707. * registered with ALSA core or not. If found a node, store
  2708. * the node and the index in a local array of struct for later
  2709. * use.
  2710. */
  2711. for (i = 0; i < wsa_dev_cnt; i++) {
  2712. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  2713. "qcom,wsa-devs", i);
  2714. if (unlikely(!wsa_of_node)) {
  2715. /* we should not be here */
  2716. dev_err(&pdev->dev,
  2717. "%s: wsa dev node is not present\n",
  2718. __func__);
  2719. ret = -EINVAL;
  2720. goto err_dev_node;
  2721. }
  2722. if (soc_find_component(wsa_of_node, NULL)) {
  2723. /* WSA device registered with ALSA core */
  2724. wsa881x_dev_info[found].of_node = wsa_of_node;
  2725. wsa881x_dev_info[found].index = i;
  2726. found++;
  2727. if (found == wsa_max_devs)
  2728. break;
  2729. }
  2730. }
  2731. if (found < wsa_max_devs) {
  2732. dev_dbg(&pdev->dev,
  2733. "%s: failed to find %d components. Found only %d\n",
  2734. __func__, wsa_max_devs, found);
  2735. return -EPROBE_DEFER;
  2736. }
  2737. dev_info(&pdev->dev,
  2738. "%s: found %d wsa881x devices registered with ALSA core\n",
  2739. __func__, found);
  2740. card->num_aux_devs = wsa_max_devs;
  2741. card->num_configs = wsa_max_devs;
  2742. /* Alloc array of AUX devs struct */
  2743. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  2744. sizeof(struct snd_soc_aux_dev),
  2745. GFP_KERNEL);
  2746. if (!msm_aux_dev) {
  2747. ret = -ENOMEM;
  2748. goto err_auxdev_mem;
  2749. }
  2750. /* Alloc array of codec conf struct */
  2751. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  2752. sizeof(struct snd_soc_codec_conf),
  2753. GFP_KERNEL);
  2754. if (!msm_codec_conf) {
  2755. ret = -ENOMEM;
  2756. goto err_codec_conf;
  2757. }
  2758. for (i = 0; i < card->num_aux_devs; i++) {
  2759. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  2760. GFP_KERNEL);
  2761. if (!dev_name_str) {
  2762. ret = -ENOMEM;
  2763. goto err_dev_str;
  2764. }
  2765. ret = of_property_read_string_index(pdev->dev.of_node,
  2766. "qcom,wsa-aux-dev-prefix",
  2767. wsa881x_dev_info[i].index,
  2768. wsa_auxdev_name_prefix);
  2769. if (ret) {
  2770. dev_err(&pdev->dev,
  2771. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  2772. __func__, ret);
  2773. ret = -EINVAL;
  2774. goto err_dt_prop;
  2775. }
  2776. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  2777. msm_aux_dev[i].name = dev_name_str;
  2778. msm_aux_dev[i].codec_name = NULL;
  2779. msm_aux_dev[i].codec_of_node =
  2780. wsa881x_dev_info[i].of_node;
  2781. msm_aux_dev[i].init = msm_wsa881x_init;
  2782. msm_codec_conf[i].dev_name = NULL;
  2783. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  2784. msm_codec_conf[i].of_node = wsa881x_dev_info[i].of_node;
  2785. }
  2786. card->codec_conf = msm_codec_conf;
  2787. card->aux_dev = msm_aux_dev;
  2788. return 0;
  2789. err_dt_prop:
  2790. devm_kfree(&pdev->dev, dev_name_str);
  2791. err_dev_str:
  2792. devm_kfree(&pdev->dev, msm_codec_conf);
  2793. err_codec_conf:
  2794. devm_kfree(&pdev->dev, msm_aux_dev);
  2795. err_auxdev_mem:
  2796. err_dev_node:
  2797. devm_kfree(&pdev->dev, wsa881x_dev_info);
  2798. err_mem:
  2799. err_dt:
  2800. return ret;
  2801. }
  2802. static void i2s_auxpcm_init(struct platform_device *pdev)
  2803. {
  2804. int count;
  2805. u32 mi2s_master_slave[MI2S_MAX];
  2806. u32 mi2s_ext_mclk[MI2S_MAX];
  2807. int ret;
  2808. for (count = 0; count < MI2S_MAX; count++) {
  2809. mutex_init(&mi2s_intf_conf[count].lock);
  2810. mi2s_intf_conf[count].ref_cnt = 0;
  2811. }
  2812. ret = of_property_read_u32_array(pdev->dev.of_node,
  2813. "qcom,msm-mi2s-master",
  2814. mi2s_master_slave, MI2S_MAX);
  2815. if (ret) {
  2816. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  2817. __func__);
  2818. } else {
  2819. for (count = 0; count < MI2S_MAX; count++) {
  2820. mi2s_intf_conf[count].msm_is_mi2s_master =
  2821. mi2s_master_slave[count];
  2822. }
  2823. }
  2824. ret = of_property_read_u32_array(pdev->dev.of_node,
  2825. "qcom,msm-mi2s-ext-mclk",
  2826. mi2s_ext_mclk, MI2S_MAX);
  2827. if (ret) {
  2828. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-ext-mclk in DT node\n",
  2829. __func__);
  2830. } else {
  2831. for (count = 0; count < MI2S_MAX; count++)
  2832. mi2s_intf_conf[count].msm_is_ext_mclk =
  2833. mi2s_ext_mclk[count];
  2834. }
  2835. }
  2836. static const struct of_device_id sdm660_asoc_machine_of_match[] = {
  2837. { .compatible = "qcom,sdm660-asoc-snd",
  2838. .data = "internal_codec"},
  2839. { .compatible = "qcom,sdm660-asoc-snd-tasha",
  2840. .data = "tasha_codec"},
  2841. { .compatible = "qcom,sdm660-asoc-snd-tavil",
  2842. .data = "tavil_codec"},
  2843. { .compatible = "qcom,sdm670-asoc-snd",
  2844. .data = "internal_codec"},
  2845. { .compatible = "qcom,sdm670-asoc-snd-tasha",
  2846. .data = "tasha_codec"},
  2847. { .compatible = "qcom,sdm670-asoc-snd-tavil",
  2848. .data = "tavil_codec"},
  2849. {},
  2850. };
  2851. static int msm_asoc_machine_probe(struct platform_device *pdev)
  2852. {
  2853. struct snd_soc_card *card = NULL;
  2854. struct msm_asoc_mach_data *pdata = NULL;
  2855. const char *mclk = "qcom,msm-mclk-freq";
  2856. int ret = -EINVAL, id;
  2857. const struct of_device_id *match;
  2858. pdata = devm_kzalloc(&pdev->dev,
  2859. sizeof(struct msm_asoc_mach_data),
  2860. GFP_KERNEL);
  2861. if (!pdata)
  2862. return -ENOMEM;
  2863. msm_set_codec_reg_done(false);
  2864. match = of_match_node(sdm660_asoc_machine_of_match,
  2865. pdev->dev.of_node);
  2866. if (!match)
  2867. goto err;
  2868. ret = of_property_read_u32(pdev->dev.of_node, mclk, &id);
  2869. if (ret) {
  2870. dev_err(&pdev->dev,
  2871. "%s: missing %s in dt node\n", __func__, mclk);
  2872. id = DEFAULT_MCLK_RATE;
  2873. }
  2874. pdata->mclk_freq = id;
  2875. if (!strcmp(match->data, "tasha_codec") ||
  2876. !strcmp(match->data, "tavil_codec")) {
  2877. if (!strcmp(match->data, "tasha_codec"))
  2878. pdata->snd_card_val = EXT_SND_CARD_TASHA;
  2879. else
  2880. pdata->snd_card_val = EXT_SND_CARD_TAVIL;
  2881. ret = msm_ext_cdc_init(pdev, pdata, &card, &mbhc_cfg);
  2882. if (ret)
  2883. goto err;
  2884. } else if (!strcmp(match->data, "internal_codec")) {
  2885. pdata->snd_card_val = INT_SND_CARD;
  2886. ret = msm_int_cdc_init(pdev, pdata, &card, &mbhc_cfg);
  2887. if (ret)
  2888. goto err;
  2889. } else {
  2890. dev_err(&pdev->dev,
  2891. "%s: Not a matching DT sound node\n", __func__);
  2892. goto err;
  2893. }
  2894. if (!card)
  2895. goto err;
  2896. if (pdata->snd_card_val == INT_SND_CARD) {
  2897. /*reading the gpio configurations from dtsi file*/
  2898. pdata->pdm_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2899. "qcom,cdc-pdm-gpios", 0);
  2900. pdata->comp_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2901. "qcom,cdc-comp-gpios", 0);
  2902. pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2903. "qcom,cdc-dmic-gpios", 0);
  2904. pdata->ext_spk_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2905. "qcom,cdc-ext-spk-gpios", 0);
  2906. }
  2907. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2908. "qcom,pri-mi2s-gpios", 0);
  2909. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2910. "qcom,sec-mi2s-gpios", 0);
  2911. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2912. "qcom,tert-mi2s-gpios", 0);
  2913. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2914. "qcom,quat-mi2s-gpios", 0);
  2915. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2916. "qcom,quin-mi2s-gpios", 0);
  2917. /*
  2918. * Parse US-Euro gpio info from DT. Report no error if us-euro
  2919. * entry is not found in DT file as some targets do not support
  2920. * US-Euro detection
  2921. */
  2922. pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node,
  2923. "qcom,us-euro-gpios", 0);
  2924. if (!gpio_is_valid(pdata->us_euro_gpio))
  2925. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2926. "qcom,us-euro-gpios", 0);
  2927. if (!gpio_is_valid(pdata->us_euro_gpio) && (!pdata->us_euro_gpio_p)) {
  2928. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  2929. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  2930. } else {
  2931. dev_dbg(&pdev->dev, "%s detected",
  2932. "qcom,us-euro-gpios");
  2933. mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  2934. }
  2935. ret = msm_prepare_us_euro(card);
  2936. if (ret)
  2937. dev_dbg(&pdev->dev, "msm_prepare_us_euro failed (%d)\n",
  2938. ret);
  2939. i2s_auxpcm_init(pdev);
  2940. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  2941. if (ret)
  2942. goto err;
  2943. ret = msm_populate_dai_link_component_of_node(pdata, card);
  2944. if (ret) {
  2945. ret = -EPROBE_DEFER;
  2946. goto err;
  2947. }
  2948. if (!of_property_read_bool(pdev->dev.of_node, "qcom,wsa-disable")) {
  2949. ret = msm_init_wsa_dev(pdev, card);
  2950. if (ret)
  2951. goto err;
  2952. }
  2953. ret = devm_snd_soc_register_card(&pdev->dev, card);
  2954. if (ret == -EPROBE_DEFER) {
  2955. if (codec_reg_done) {
  2956. /*
  2957. * return failure as EINVAL since other codec
  2958. * registered sound card successfully.
  2959. * This avoids any further probe calls.
  2960. */
  2961. ret = -EINVAL;
  2962. }
  2963. goto err;
  2964. } else if (ret) {
  2965. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  2966. ret);
  2967. goto err;
  2968. }
  2969. if (pdata->snd_card_val != INT_SND_CARD)
  2970. msm_ext_register_audio_notifier(pdev);
  2971. return 0;
  2972. err:
  2973. if (pdata->us_euro_gpio > 0) {
  2974. dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n",
  2975. __func__, pdata->us_euro_gpio);
  2976. pdata->us_euro_gpio = 0;
  2977. }
  2978. if (pdata->hph_en1_gpio > 0) {
  2979. dev_dbg(&pdev->dev, "%s free hph_en1_gpio %d\n",
  2980. __func__, pdata->hph_en1_gpio);
  2981. gpio_free(pdata->hph_en1_gpio);
  2982. pdata->hph_en1_gpio = 0;
  2983. }
  2984. if (pdata->hph_en0_gpio > 0) {
  2985. dev_dbg(&pdev->dev, "%s free hph_en0_gpio %d\n",
  2986. __func__, pdata->hph_en0_gpio);
  2987. gpio_free(pdata->hph_en0_gpio);
  2988. pdata->hph_en0_gpio = 0;
  2989. }
  2990. devm_kfree(&pdev->dev, pdata);
  2991. return ret;
  2992. }
  2993. static int msm_asoc_machine_remove(struct platform_device *pdev)
  2994. {
  2995. struct snd_soc_card *card = platform_get_drvdata(pdev);
  2996. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  2997. if (pdata->snd_card_val == INT_SND_CARD)
  2998. mutex_destroy(&pdata->cdc_int_mclk0_mutex);
  2999. gpio_free(pdata->us_euro_gpio);
  3000. gpio_free(pdata->hph_en1_gpio);
  3001. gpio_free(pdata->hph_en0_gpio);
  3002. if (pdata->snd_card_val != INT_SND_CARD)
  3003. audio_notifier_deregister("sdm660");
  3004. snd_soc_unregister_card(card);
  3005. return 0;
  3006. }
  3007. static struct platform_driver sdm660_asoc_machine_driver = {
  3008. .driver = {
  3009. .name = DRV_NAME,
  3010. .owner = THIS_MODULE,
  3011. .pm = &snd_soc_pm_ops,
  3012. .of_match_table = sdm660_asoc_machine_of_match,
  3013. },
  3014. .probe = msm_asoc_machine_probe,
  3015. .remove = msm_asoc_machine_remove,
  3016. };
  3017. module_platform_driver(sdm660_asoc_machine_driver);
  3018. MODULE_DESCRIPTION("ALSA SoC msm");
  3019. MODULE_LICENSE("GPL v2");
  3020. MODULE_ALIAS("platform:" DRV_NAME);
  3021. MODULE_DEVICE_TABLE(of, sdm660_asoc_machine_of_match);