dp_main.c 160 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include <ol_cfg.h>
  52. #include "dp_ipa.h"
  53. #define DP_INTR_POLL_TIMER_MS 10
  54. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  55. #define DP_MCS_LENGTH (6*MAX_MCS)
  56. #define DP_NSS_LENGTH (6*SS_COUNT)
  57. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  58. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  59. #define DP_MAX_MCS_STRING_LEN 30
  60. #define DP_CURR_FW_STATS_AVAIL 19
  61. #define DP_HTT_DBG_EXT_STATS_MAX 256
  62. #ifdef IPA_OFFLOAD
  63. /* Exclude IPA rings from the interrupt context */
  64. #define TX_RING_MASK_VAL 0x7
  65. #define RX_RING_MASK_VAL 0x7
  66. #else
  67. #define TX_RING_MASK_VAL 0xF
  68. #define RX_RING_MASK_VAL 0xF
  69. #endif
  70. bool rx_hash = 1;
  71. qdf_declare_param(rx_hash, bool);
  72. #define STR_MAXLEN 64
  73. /**
  74. * default_dscp_tid_map - Default DSCP-TID mapping
  75. *
  76. * DSCP TID AC
  77. * 000000 0 WME_AC_BE
  78. * 001000 1 WME_AC_BK
  79. * 010000 1 WME_AC_BK
  80. * 011000 0 WME_AC_BE
  81. * 100000 5 WME_AC_VI
  82. * 101000 5 WME_AC_VI
  83. * 110000 6 WME_AC_VO
  84. * 111000 6 WME_AC_VO
  85. */
  86. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  87. 0, 0, 0, 0, 0, 0, 0, 0,
  88. 1, 1, 1, 1, 1, 1, 1, 1,
  89. 1, 1, 1, 1, 1, 1, 1, 1,
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 5, 5, 5, 5, 5, 5, 5, 5,
  92. 5, 5, 5, 5, 5, 5, 5, 5,
  93. 6, 6, 6, 6, 6, 6, 6, 6,
  94. 6, 6, 6, 6, 6, 6, 6, 6,
  95. };
  96. /*
  97. * struct dp_rate_debug
  98. *
  99. * @mcs_type: print string for a given mcs
  100. * @valid: valid mcs rate?
  101. */
  102. struct dp_rate_debug {
  103. char mcs_type[DP_MAX_MCS_STRING_LEN];
  104. uint8_t valid;
  105. };
  106. #define MCS_VALID 1
  107. #define MCS_INVALID 0
  108. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  109. {
  110. {"CCK 11 Mbps Long ", MCS_VALID},
  111. {"CCK 5.5 Mbps Long ", MCS_VALID},
  112. {"CCK 2 Mbps Long ", MCS_VALID},
  113. {"CCK 1 Mbps Long ", MCS_VALID},
  114. {"CCK 11 Mbps Short ", MCS_VALID},
  115. {"CCK 5.5 Mbps Short", MCS_VALID},
  116. {"CCK 2 Mbps Short ", MCS_VALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_INVALID},
  119. {"INVALID ", MCS_INVALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_INVALID},
  122. {"INVALID ", MCS_VALID},
  123. },
  124. {
  125. {"OFDM 48 Mbps", MCS_VALID},
  126. {"OFDM 24 Mbps", MCS_VALID},
  127. {"OFDM 12 Mbps", MCS_VALID},
  128. {"OFDM 6 Mbps ", MCS_VALID},
  129. {"OFDM 54 Mbps", MCS_VALID},
  130. {"OFDM 36 Mbps", MCS_VALID},
  131. {"OFDM 18 Mbps", MCS_VALID},
  132. {"OFDM 9 Mbps ", MCS_VALID},
  133. {"INVALID ", MCS_INVALID},
  134. {"INVALID ", MCS_INVALID},
  135. {"INVALID ", MCS_INVALID},
  136. {"INVALID ", MCS_INVALID},
  137. {"INVALID ", MCS_VALID},
  138. },
  139. {
  140. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  141. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  142. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  143. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  144. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  145. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  146. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  147. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  148. {"INVALID ", MCS_INVALID},
  149. {"INVALID ", MCS_INVALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_INVALID},
  152. {"INVALID ", MCS_VALID},
  153. },
  154. {
  155. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  156. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  157. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  158. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  159. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  160. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  161. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  162. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  163. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  164. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  165. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  166. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  167. {"INVALID ", MCS_VALID},
  168. },
  169. {
  170. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  171. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  172. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  173. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  174. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  175. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  176. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  177. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  178. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  179. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  180. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  181. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  182. {"INVALID ", MCS_VALID},
  183. }
  184. };
  185. /**
  186. * @brief Cpu ring map types
  187. */
  188. enum dp_cpu_ring_map_types {
  189. DP_DEFAULT_MAP,
  190. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  191. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  192. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  193. DP_CPU_RING_MAP_MAX
  194. };
  195. /**
  196. * @brief Cpu to tx ring map
  197. */
  198. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  199. {0x0, 0x1, 0x2, 0x0},
  200. {0x1, 0x2, 0x1, 0x2},
  201. {0x0, 0x2, 0x0, 0x2},
  202. {0x2, 0x2, 0x2, 0x2}
  203. };
  204. /**
  205. * @brief Select the type of statistics
  206. */
  207. enum dp_stats_type {
  208. STATS_FW = 0,
  209. STATS_HOST = 1,
  210. STATS_TYPE_MAX = 2,
  211. };
  212. /**
  213. * @brief General Firmware statistics options
  214. *
  215. */
  216. enum dp_fw_stats {
  217. TXRX_FW_STATS_INVALID = -1,
  218. };
  219. /**
  220. * dp_stats_mapping_table - Firmware and Host statistics
  221. * currently supported
  222. */
  223. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  224. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  235. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  242. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  243. /* Last ENUM for HTT FW STATS */
  244. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  245. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  247. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  248. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  250. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  251. {TXRX_FW_STATS_INVALID, TXRX_SRNG_PTR_STATS},
  252. };
  253. /**
  254. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  255. * @ring_num: ring num of the ring being queried
  256. * @grp_mask: the grp_mask array for the ring type in question.
  257. *
  258. * The grp_mask array is indexed by group number and the bit fields correspond
  259. * to ring numbers. We are finding which interrupt group a ring belongs to.
  260. *
  261. * Return: the index in the grp_mask array with the ring number.
  262. * -QDF_STATUS_E_NOENT if no entry is found
  263. */
  264. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  265. {
  266. int ext_group_num;
  267. int mask = 1 << ring_num;
  268. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  269. ext_group_num++) {
  270. if (mask & grp_mask[ext_group_num])
  271. return ext_group_num;
  272. }
  273. return -QDF_STATUS_E_NOENT;
  274. }
  275. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  276. enum hal_ring_type ring_type,
  277. int ring_num)
  278. {
  279. int *grp_mask;
  280. switch (ring_type) {
  281. case WBM2SW_RELEASE:
  282. /* dp_tx_comp_handler - soc->tx_comp_ring */
  283. if (ring_num < 3)
  284. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  285. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  286. else if (ring_num == 3) {
  287. /* sw treats this as a separate ring type */
  288. grp_mask = &soc->wlan_cfg_ctx->
  289. int_rx_wbm_rel_ring_mask[0];
  290. ring_num = 0;
  291. } else {
  292. qdf_assert(0);
  293. return -QDF_STATUS_E_NOENT;
  294. }
  295. break;
  296. case REO_EXCEPTION:
  297. /* dp_rx_err_process - &soc->reo_exception_ring */
  298. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  299. break;
  300. case REO_DST:
  301. /* dp_rx_process - soc->reo_dest_ring */
  302. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  303. break;
  304. case REO_STATUS:
  305. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  306. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  307. break;
  308. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  309. case RXDMA_MONITOR_STATUS:
  310. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  311. case RXDMA_MONITOR_DST:
  312. /* dp_mon_process */
  313. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  314. break;
  315. case RXDMA_DST:
  316. /* dp_rxdma_err_process */
  317. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  318. break;
  319. case RXDMA_MONITOR_BUF:
  320. case RXDMA_BUF:
  321. /* TODO: support low_thresh interrupt */
  322. return -QDF_STATUS_E_NOENT;
  323. break;
  324. case TCL_DATA:
  325. case TCL_CMD:
  326. case REO_CMD:
  327. case SW2WBM_RELEASE:
  328. case WBM_IDLE_LINK:
  329. /* normally empty SW_TO_HW rings */
  330. return -QDF_STATUS_E_NOENT;
  331. break;
  332. case TCL_STATUS:
  333. case REO_REINJECT:
  334. /* misc unused rings */
  335. return -QDF_STATUS_E_NOENT;
  336. break;
  337. case CE_SRC:
  338. case CE_DST:
  339. case CE_DST_STATUS:
  340. /* CE_rings - currently handled by hif */
  341. default:
  342. return -QDF_STATUS_E_NOENT;
  343. break;
  344. }
  345. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  346. }
  347. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  348. *ring_params, int ring_type, int ring_num)
  349. {
  350. int msi_group_number;
  351. int msi_data_count;
  352. int ret;
  353. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  354. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  355. &msi_data_count, &msi_data_start,
  356. &msi_irq_start);
  357. if (ret)
  358. return;
  359. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  360. ring_num);
  361. if (msi_group_number < 0) {
  362. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  363. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  364. ring_type, ring_num);
  365. ring_params->msi_addr = 0;
  366. ring_params->msi_data = 0;
  367. return;
  368. }
  369. if (msi_group_number > msi_data_count) {
  370. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  371. FL("2 msi_groups will share an msi; msi_group_num %d"),
  372. msi_group_number);
  373. QDF_ASSERT(0);
  374. }
  375. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  376. ring_params->msi_addr = addr_low;
  377. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  378. ring_params->msi_data = (msi_group_number % msi_data_count)
  379. + msi_data_start;
  380. ring_params->flags |= HAL_SRNG_MSI_INTR;
  381. }
  382. /**
  383. * dp_print_ast_stats() - Dump AST table contents
  384. * @soc: Datapath soc handle
  385. *
  386. * return void
  387. */
  388. #ifdef FEATURE_WDS
  389. static void dp_print_ast_stats(struct dp_soc *soc)
  390. {
  391. uint8_t i;
  392. uint8_t num_entries = 0;
  393. struct dp_vdev *vdev;
  394. struct dp_pdev *pdev;
  395. struct dp_peer *peer;
  396. struct dp_ast_entry *ase, *tmp_ase;
  397. DP_PRINT_STATS("AST Stats:");
  398. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  399. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  400. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  401. DP_PRINT_STATS("AST Table:");
  402. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  403. pdev = soc->pdev_list[i];
  404. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  405. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  406. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  407. DP_PRINT_STATS("%6d mac_addr = %pM"
  408. " peer_mac_addr = %pM"
  409. " type = %d"
  410. " next_hop = %d"
  411. " is_active = %d"
  412. " is_bss = %d",
  413. ++num_entries,
  414. ase->mac_addr.raw,
  415. ase->peer->mac_addr.raw,
  416. ase->type,
  417. ase->next_hop,
  418. ase->is_active,
  419. ase->is_bss);
  420. }
  421. }
  422. }
  423. }
  424. }
  425. #else
  426. static void dp_print_ast_stats(struct dp_soc *soc)
  427. {
  428. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  429. return;
  430. }
  431. #endif
  432. /*
  433. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  434. */
  435. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  436. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  437. {
  438. void *hal_soc = soc->hal_soc;
  439. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  440. /* TODO: See if we should get align size from hal */
  441. uint32_t ring_base_align = 8;
  442. struct hal_srng_params ring_params;
  443. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  444. /* TODO: Currently hal layer takes care of endianness related settings.
  445. * See if these settings need to passed from DP layer
  446. */
  447. ring_params.flags = 0;
  448. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  449. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  450. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  451. srng->hal_srng = NULL;
  452. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  453. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  454. soc->osdev, soc->osdev->dev, srng->alloc_size,
  455. &(srng->base_paddr_unaligned));
  456. if (!srng->base_vaddr_unaligned) {
  457. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  458. FL("alloc failed - ring_type: %d, ring_num %d"),
  459. ring_type, ring_num);
  460. return QDF_STATUS_E_NOMEM;
  461. }
  462. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  463. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  464. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  465. ((unsigned long)(ring_params.ring_base_vaddr) -
  466. (unsigned long)srng->base_vaddr_unaligned);
  467. ring_params.num_entries = num_entries;
  468. if (soc->intr_mode == DP_INTR_MSI) {
  469. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  470. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  471. FL("Using MSI for ring_type: %d, ring_num %d"),
  472. ring_type, ring_num);
  473. } else {
  474. ring_params.msi_data = 0;
  475. ring_params.msi_addr = 0;
  476. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  477. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  478. ring_type, ring_num);
  479. }
  480. /*
  481. * Setup interrupt timer and batch counter thresholds for
  482. * interrupt mitigation based on ring type
  483. */
  484. if (ring_type == REO_DST) {
  485. ring_params.intr_timer_thres_us =
  486. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  487. ring_params.intr_batch_cntr_thres_entries =
  488. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  489. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  490. ring_params.intr_timer_thres_us =
  491. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  492. ring_params.intr_batch_cntr_thres_entries =
  493. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  494. } else {
  495. ring_params.intr_timer_thres_us =
  496. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  497. ring_params.intr_batch_cntr_thres_entries =
  498. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  499. }
  500. /* Enable low threshold interrupts for rx buffer rings (regular and
  501. * monitor buffer rings.
  502. * TODO: See if this is required for any other ring
  503. */
  504. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  505. /* TODO: Setting low threshold to 1/8th of ring size
  506. * see if this needs to be configurable
  507. */
  508. ring_params.low_threshold = num_entries >> 3;
  509. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  510. ring_params.intr_timer_thres_us = 0x1000;
  511. }
  512. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  513. mac_id, &ring_params);
  514. return 0;
  515. }
  516. /**
  517. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  518. * Any buffers allocated and attached to ring entries are expected to be freed
  519. * before calling this function.
  520. */
  521. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  522. int ring_type, int ring_num)
  523. {
  524. if (!srng->hal_srng) {
  525. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  526. FL("Ring type: %d, num:%d not setup"),
  527. ring_type, ring_num);
  528. return;
  529. }
  530. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  531. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  532. srng->alloc_size,
  533. srng->base_vaddr_unaligned,
  534. srng->base_paddr_unaligned, 0);
  535. srng->hal_srng = NULL;
  536. }
  537. #ifdef IPA_OFFLOAD
  538. /**
  539. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  540. * @soc: data path instance
  541. * @pdev: core txrx pdev context
  542. *
  543. * Free allocated TX buffers with WBM SRNG
  544. *
  545. * Return: none
  546. */
  547. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  548. {
  549. int idx;
  550. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  551. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  552. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  553. }
  554. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  555. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  556. }
  557. /**
  558. * dp_rx_ipa_uc_detach - free autonomy RX resources
  559. * @soc: data path instance
  560. * @pdev: core txrx pdev context
  561. *
  562. * This function will detach DP RX into main device context
  563. * will free DP Rx resources.
  564. *
  565. * Return: none
  566. */
  567. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  568. {
  569. }
  570. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  571. {
  572. /* TX resource detach */
  573. dp_tx_ipa_uc_detach(soc, pdev);
  574. /* RX resource detach */
  575. dp_rx_ipa_uc_detach(soc, pdev);
  576. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  577. return QDF_STATUS_SUCCESS; /* success */
  578. }
  579. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  580. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  581. /**
  582. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  583. * @soc: data path instance
  584. * @pdev: Physical device handle
  585. *
  586. * Allocate TX buffer from non-cacheable memory
  587. * Attache allocated TX buffers with WBM SRNG
  588. *
  589. * Return: int
  590. */
  591. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  592. {
  593. uint32_t tx_buffer_count;
  594. uint32_t ring_base_align = 8;
  595. void *buffer_vaddr_unaligned;
  596. void *buffer_vaddr;
  597. qdf_dma_addr_t buffer_paddr_unaligned;
  598. qdf_dma_addr_t buffer_paddr;
  599. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  600. uint32_t paddr_lo;
  601. uint32_t paddr_hi;
  602. void *ring_entry;
  603. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  604. int retval = QDF_STATUS_SUCCESS;
  605. /*
  606. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  607. * unsigned int uc_tx_buf_sz =
  608. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  609. */
  610. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  611. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  612. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  613. "requested %d buffers to be posted to wbm ring",
  614. ring_size);
  615. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  616. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  617. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  618. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  619. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  620. return -ENOMEM;
  621. }
  622. hal_srng_access_start(soc->hal_soc, wbm_srng);
  623. /* Allocate TX buffers as many as possible */
  624. for (tx_buffer_count = 0;
  625. tx_buffer_count < ring_size; tx_buffer_count++) {
  626. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  627. if (!ring_entry) {
  628. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  629. "Failed to get WBM ring entry\n");
  630. goto fail;
  631. }
  632. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  633. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  634. if (!buffer_vaddr_unaligned) {
  635. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  636. "IPA WDI TX buffer alloc fail %d allocated\n",
  637. tx_buffer_count);
  638. break;
  639. }
  640. buffer_vaddr = buffer_vaddr_unaligned +
  641. ((unsigned long)buffer_vaddr_unaligned %
  642. ring_base_align);
  643. buffer_paddr = buffer_paddr_unaligned +
  644. ((unsigned long)(buffer_vaddr) -
  645. (unsigned long)buffer_vaddr_unaligned);
  646. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  647. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  648. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  649. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  650. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  651. buffer_vaddr;
  652. }
  653. hal_srng_access_end(soc->hal_soc, wbm_srng);
  654. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  655. return retval;
  656. fail:
  657. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  658. return retval;
  659. }
  660. /**
  661. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  662. * @soc: data path instance
  663. * @pdev: core txrx pdev context
  664. *
  665. * This function will attach a DP RX instance into the main
  666. * device (SOC) context.
  667. *
  668. * Return: QDF_STATUS_SUCCESS: success
  669. * QDF_STATUS_E_RESOURCES: Error return
  670. */
  671. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  672. {
  673. return QDF_STATUS_SUCCESS;
  674. }
  675. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  676. {
  677. int error;
  678. /* TX resource attach */
  679. error = dp_tx_ipa_uc_attach(soc, pdev);
  680. if (error) {
  681. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  682. "DP IPA UC TX attach fail code %d\n", error);
  683. return error;
  684. }
  685. /* RX resource attach */
  686. error = dp_rx_ipa_uc_attach(soc, pdev);
  687. if (error) {
  688. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  689. "DP IPA UC RX attach fail code %d\n", error);
  690. dp_tx_ipa_uc_detach(soc, pdev);
  691. return error;
  692. }
  693. return QDF_STATUS_SUCCESS; /* success */
  694. }
  695. #else
  696. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  697. {
  698. return QDF_STATUS_SUCCESS;
  699. }
  700. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  701. {
  702. return QDF_STATUS_SUCCESS;
  703. }
  704. #endif
  705. /* TODO: Need this interface from HIF */
  706. void *hif_get_hal_handle(void *hif_handle);
  707. /*
  708. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  709. * @dp_ctx: DP SOC handle
  710. * @budget: Number of frames/descriptors that can be processed in one shot
  711. *
  712. * Return: remaining budget/quota for the soc device
  713. */
  714. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  715. {
  716. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  717. struct dp_soc *soc = int_ctx->soc;
  718. int ring = 0;
  719. uint32_t work_done = 0;
  720. int budget = dp_budget;
  721. uint8_t tx_mask = int_ctx->tx_ring_mask;
  722. uint8_t rx_mask = int_ctx->rx_ring_mask;
  723. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  724. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  725. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  726. uint32_t remaining_quota = dp_budget;
  727. /* Process Tx completion interrupts first to return back buffers */
  728. while (tx_mask) {
  729. if (tx_mask & 0x1) {
  730. work_done = dp_tx_comp_handler(soc,
  731. soc->tx_comp_ring[ring].hal_srng,
  732. remaining_quota);
  733. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  734. "tx mask 0x%x ring %d, budget %d, work_done %d",
  735. tx_mask, ring, budget, work_done);
  736. budget -= work_done;
  737. if (budget <= 0)
  738. goto budget_done;
  739. remaining_quota = budget;
  740. }
  741. tx_mask = tx_mask >> 1;
  742. ring++;
  743. }
  744. /* Process REO Exception ring interrupt */
  745. if (rx_err_mask) {
  746. work_done = dp_rx_err_process(soc,
  747. soc->reo_exception_ring.hal_srng,
  748. remaining_quota);
  749. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  750. "REO Exception Ring: work_done %d budget %d",
  751. work_done, budget);
  752. budget -= work_done;
  753. if (budget <= 0) {
  754. goto budget_done;
  755. }
  756. remaining_quota = budget;
  757. }
  758. /* Process Rx WBM release ring interrupt */
  759. if (rx_wbm_rel_mask) {
  760. work_done = dp_rx_wbm_err_process(soc,
  761. soc->rx_rel_ring.hal_srng, remaining_quota);
  762. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  763. "WBM Release Ring: work_done %d budget %d",
  764. work_done, budget);
  765. budget -= work_done;
  766. if (budget <= 0) {
  767. goto budget_done;
  768. }
  769. remaining_quota = budget;
  770. }
  771. /* Process Rx interrupts */
  772. if (rx_mask) {
  773. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  774. if (rx_mask & (1 << ring)) {
  775. work_done = dp_rx_process(int_ctx,
  776. soc->reo_dest_ring[ring].hal_srng,
  777. remaining_quota);
  778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  779. "rx mask 0x%x ring %d, work_done %d budget %d",
  780. rx_mask, ring, work_done, budget);
  781. budget -= work_done;
  782. if (budget <= 0)
  783. goto budget_done;
  784. remaining_quota = budget;
  785. }
  786. }
  787. }
  788. if (reo_status_mask)
  789. dp_reo_status_ring_handler(soc);
  790. /* Process LMAC interrupts */
  791. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  792. if (soc->pdev_list[ring] == NULL)
  793. continue;
  794. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  795. work_done = dp_mon_process(soc, ring, remaining_quota);
  796. budget -= work_done;
  797. remaining_quota = budget;
  798. }
  799. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  800. work_done = dp_rxdma_err_process(soc, ring,
  801. remaining_quota);
  802. budget -= work_done;
  803. }
  804. }
  805. qdf_lro_flush(int_ctx->lro_ctx);
  806. budget_done:
  807. return dp_budget - budget;
  808. }
  809. #ifdef DP_INTR_POLL_BASED
  810. /* dp_interrupt_timer()- timer poll for interrupts
  811. *
  812. * @arg: SoC Handle
  813. *
  814. * Return:
  815. *
  816. */
  817. static void dp_interrupt_timer(void *arg)
  818. {
  819. struct dp_soc *soc = (struct dp_soc *) arg;
  820. int i;
  821. if (qdf_atomic_read(&soc->cmn_init_done)) {
  822. for (i = 0;
  823. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  824. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  825. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  826. }
  827. }
  828. /*
  829. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  830. * @txrx_soc: DP SOC handle
  831. *
  832. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  833. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  834. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  835. *
  836. * Return: 0 for success. nonzero for failure.
  837. */
  838. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  839. {
  840. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  841. int i;
  842. soc->intr_mode = DP_INTR_POLL;
  843. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  844. soc->intr_ctx[i].dp_intr_id = i;
  845. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  846. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  847. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  848. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  849. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  850. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  851. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  852. soc->intr_ctx[i].soc = soc;
  853. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  854. }
  855. qdf_timer_init(soc->osdev, &soc->int_timer,
  856. dp_interrupt_timer, (void *)soc,
  857. QDF_TIMER_TYPE_WAKE_APPS);
  858. return QDF_STATUS_SUCCESS;
  859. }
  860. #ifdef CONFIG_MCL
  861. extern int con_mode_monitor;
  862. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  863. /*
  864. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  865. * @txrx_soc: DP SOC handle
  866. *
  867. * Call the appropriate attach function based on the mode of operation.
  868. * This is a WAR for enabling monitor mode.
  869. *
  870. * Return: 0 for success. nonzero for failure.
  871. */
  872. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  873. {
  874. if (con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  875. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  876. FL("Attach interrupts in Poll mode"));
  877. return dp_soc_interrupt_attach_poll(txrx_soc);
  878. } else {
  879. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  880. FL("Attach interrupts in MSI mode"));
  881. return dp_soc_interrupt_attach(txrx_soc);
  882. }
  883. }
  884. #else
  885. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  886. {
  887. return dp_soc_interrupt_attach_poll(txrx_soc);
  888. }
  889. #endif
  890. #endif
  891. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  892. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  893. {
  894. int j;
  895. int num_irq = 0;
  896. int tx_mask =
  897. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  898. int rx_mask =
  899. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  900. int rx_mon_mask =
  901. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  902. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  903. soc->wlan_cfg_ctx, intr_ctx_num);
  904. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  905. soc->wlan_cfg_ctx, intr_ctx_num);
  906. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  907. soc->wlan_cfg_ctx, intr_ctx_num);
  908. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  909. soc->wlan_cfg_ctx, intr_ctx_num);
  910. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  911. if (tx_mask & (1 << j)) {
  912. irq_id_map[num_irq++] =
  913. (wbm2host_tx_completions_ring1 - j);
  914. }
  915. if (rx_mask & (1 << j)) {
  916. irq_id_map[num_irq++] =
  917. (reo2host_destination_ring1 - j);
  918. }
  919. if (rxdma2host_ring_mask & (1 << j)) {
  920. irq_id_map[num_irq++] =
  921. rxdma2host_destination_ring_mac1 -
  922. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  923. }
  924. if (rx_mon_mask & (1 << j)) {
  925. irq_id_map[num_irq++] =
  926. ppdu_end_interrupts_mac1 -
  927. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  928. }
  929. if (rx_wbm_rel_ring_mask & (1 << j))
  930. irq_id_map[num_irq++] = wbm2host_rx_release;
  931. if (rx_err_ring_mask & (1 << j))
  932. irq_id_map[num_irq++] = reo2host_exception;
  933. if (reo_status_ring_mask & (1 << j))
  934. irq_id_map[num_irq++] = reo2host_status;
  935. }
  936. *num_irq_r = num_irq;
  937. }
  938. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  939. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  940. int msi_vector_count, int msi_vector_start)
  941. {
  942. int tx_mask = wlan_cfg_get_tx_ring_mask(
  943. soc->wlan_cfg_ctx, intr_ctx_num);
  944. int rx_mask = wlan_cfg_get_rx_ring_mask(
  945. soc->wlan_cfg_ctx, intr_ctx_num);
  946. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  947. soc->wlan_cfg_ctx, intr_ctx_num);
  948. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  949. soc->wlan_cfg_ctx, intr_ctx_num);
  950. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  951. soc->wlan_cfg_ctx, intr_ctx_num);
  952. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  953. soc->wlan_cfg_ctx, intr_ctx_num);
  954. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  955. soc->wlan_cfg_ctx, intr_ctx_num);
  956. unsigned int vector =
  957. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  958. int num_irq = 0;
  959. soc->intr_mode = DP_INTR_MSI;
  960. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  961. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask)
  962. irq_id_map[num_irq++] =
  963. pld_get_msi_irq(soc->osdev->dev, vector);
  964. *num_irq_r = num_irq;
  965. }
  966. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  967. int *irq_id_map, int *num_irq)
  968. {
  969. int msi_vector_count, ret;
  970. uint32_t msi_base_data, msi_vector_start;
  971. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  972. &msi_vector_count,
  973. &msi_base_data,
  974. &msi_vector_start);
  975. if (ret)
  976. return dp_soc_interrupt_map_calculate_integrated(soc,
  977. intr_ctx_num, irq_id_map, num_irq);
  978. else
  979. dp_soc_interrupt_map_calculate_msi(soc,
  980. intr_ctx_num, irq_id_map, num_irq,
  981. msi_vector_count, msi_vector_start);
  982. }
  983. /*
  984. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  985. * @txrx_soc: DP SOC handle
  986. *
  987. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  988. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  989. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  990. *
  991. * Return: 0 for success. nonzero for failure.
  992. */
  993. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  994. {
  995. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  996. int i = 0;
  997. int num_irq = 0;
  998. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  999. int ret = 0;
  1000. /* Map of IRQ ids registered with one interrupt context */
  1001. int irq_id_map[HIF_MAX_GRP_IRQ];
  1002. int tx_mask =
  1003. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1004. int rx_mask =
  1005. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1006. int rx_mon_mask =
  1007. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1008. int rx_err_ring_mask =
  1009. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1010. int rx_wbm_rel_ring_mask =
  1011. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1012. int reo_status_ring_mask =
  1013. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1014. int rxdma2host_ring_mask =
  1015. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1016. soc->intr_ctx[i].dp_intr_id = i;
  1017. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1018. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1019. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1020. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1021. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1022. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1023. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1024. soc->intr_ctx[i].soc = soc;
  1025. num_irq = 0;
  1026. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1027. &num_irq);
  1028. ret = hif_register_ext_group(soc->hif_handle,
  1029. num_irq, irq_id_map, dp_service_srngs,
  1030. &soc->intr_ctx[i], "dp_intr",
  1031. HIF_EXEC_NAPI_TYPE, 2);
  1032. if (ret) {
  1033. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1034. FL("failed, ret = %d"), ret);
  1035. return QDF_STATUS_E_FAILURE;
  1036. }
  1037. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1038. }
  1039. hif_configure_ext_group_interrupts(soc->hif_handle);
  1040. return QDF_STATUS_SUCCESS;
  1041. }
  1042. /*
  1043. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  1044. * @txrx_soc: DP SOC handle
  1045. *
  1046. * Return: void
  1047. */
  1048. static void dp_soc_interrupt_detach(void *txrx_soc)
  1049. {
  1050. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1051. int i;
  1052. if (soc->intr_mode == DP_INTR_POLL) {
  1053. qdf_timer_stop(&soc->int_timer);
  1054. qdf_timer_free(&soc->int_timer);
  1055. } else {
  1056. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1057. }
  1058. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1059. soc->intr_ctx[i].tx_ring_mask = 0;
  1060. soc->intr_ctx[i].rx_ring_mask = 0;
  1061. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1062. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1063. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1064. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1065. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  1066. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1067. }
  1068. }
  1069. #define AVG_MAX_MPDUS_PER_TID 128
  1070. #define AVG_TIDS_PER_CLIENT 2
  1071. #define AVG_FLOWS_PER_TID 2
  1072. #define AVG_MSDUS_PER_FLOW 128
  1073. #define AVG_MSDUS_PER_MPDU 4
  1074. /*
  1075. * Allocate and setup link descriptor pool that will be used by HW for
  1076. * various link and queue descriptors and managed by WBM
  1077. */
  1078. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1079. {
  1080. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1081. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1082. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1083. uint32_t num_mpdus_per_link_desc =
  1084. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1085. uint32_t num_msdus_per_link_desc =
  1086. hal_num_msdus_per_link_desc(soc->hal_soc);
  1087. uint32_t num_mpdu_links_per_queue_desc =
  1088. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1089. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1090. uint32_t total_link_descs, total_mem_size;
  1091. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1092. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1093. uint32_t num_link_desc_banks;
  1094. uint32_t last_bank_size = 0;
  1095. uint32_t entry_size, num_entries;
  1096. int i;
  1097. uint32_t desc_id = 0;
  1098. /* Only Tx queue descriptors are allocated from common link descriptor
  1099. * pool Rx queue descriptors are not included in this because (REO queue
  1100. * extension descriptors) they are expected to be allocated contiguously
  1101. * with REO queue descriptors
  1102. */
  1103. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1104. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1105. num_mpdu_queue_descs = num_mpdu_link_descs /
  1106. num_mpdu_links_per_queue_desc;
  1107. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1108. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1109. num_msdus_per_link_desc;
  1110. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1111. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1112. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1113. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1114. /* Round up to power of 2 */
  1115. total_link_descs = 1;
  1116. while (total_link_descs < num_entries)
  1117. total_link_descs <<= 1;
  1118. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1119. FL("total_link_descs: %u, link_desc_size: %d"),
  1120. total_link_descs, link_desc_size);
  1121. total_mem_size = total_link_descs * link_desc_size;
  1122. total_mem_size += link_desc_align;
  1123. if (total_mem_size <= max_alloc_size) {
  1124. num_link_desc_banks = 0;
  1125. last_bank_size = total_mem_size;
  1126. } else {
  1127. num_link_desc_banks = (total_mem_size) /
  1128. (max_alloc_size - link_desc_align);
  1129. last_bank_size = total_mem_size %
  1130. (max_alloc_size - link_desc_align);
  1131. }
  1132. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1133. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1134. total_mem_size, num_link_desc_banks);
  1135. for (i = 0; i < num_link_desc_banks; i++) {
  1136. soc->link_desc_banks[i].base_vaddr_unaligned =
  1137. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1138. max_alloc_size,
  1139. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1140. soc->link_desc_banks[i].size = max_alloc_size;
  1141. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1142. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1143. ((unsigned long)(
  1144. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1145. link_desc_align));
  1146. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1147. soc->link_desc_banks[i].base_paddr_unaligned) +
  1148. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1149. (unsigned long)(
  1150. soc->link_desc_banks[i].base_vaddr_unaligned));
  1151. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1152. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1153. FL("Link descriptor memory alloc failed"));
  1154. goto fail;
  1155. }
  1156. }
  1157. if (last_bank_size) {
  1158. /* Allocate last bank in case total memory required is not exact
  1159. * multiple of max_alloc_size
  1160. */
  1161. soc->link_desc_banks[i].base_vaddr_unaligned =
  1162. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1163. last_bank_size,
  1164. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1165. soc->link_desc_banks[i].size = last_bank_size;
  1166. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1167. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1168. ((unsigned long)(
  1169. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1170. link_desc_align));
  1171. soc->link_desc_banks[i].base_paddr =
  1172. (unsigned long)(
  1173. soc->link_desc_banks[i].base_paddr_unaligned) +
  1174. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1175. (unsigned long)(
  1176. soc->link_desc_banks[i].base_vaddr_unaligned));
  1177. }
  1178. /* Allocate and setup link descriptor idle list for HW internal use */
  1179. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1180. total_mem_size = entry_size * total_link_descs;
  1181. if (total_mem_size <= max_alloc_size) {
  1182. void *desc;
  1183. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1184. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1185. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1186. FL("Link desc idle ring setup failed"));
  1187. goto fail;
  1188. }
  1189. hal_srng_access_start_unlocked(soc->hal_soc,
  1190. soc->wbm_idle_link_ring.hal_srng);
  1191. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1192. soc->link_desc_banks[i].base_paddr; i++) {
  1193. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1194. ((unsigned long)(
  1195. soc->link_desc_banks[i].base_vaddr) -
  1196. (unsigned long)(
  1197. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1198. / link_desc_size;
  1199. unsigned long paddr = (unsigned long)(
  1200. soc->link_desc_banks[i].base_paddr);
  1201. while (num_entries && (desc = hal_srng_src_get_next(
  1202. soc->hal_soc,
  1203. soc->wbm_idle_link_ring.hal_srng))) {
  1204. hal_set_link_desc_addr(desc,
  1205. LINK_DESC_COOKIE(desc_id, i), paddr);
  1206. num_entries--;
  1207. desc_id++;
  1208. paddr += link_desc_size;
  1209. }
  1210. }
  1211. hal_srng_access_end_unlocked(soc->hal_soc,
  1212. soc->wbm_idle_link_ring.hal_srng);
  1213. } else {
  1214. uint32_t num_scatter_bufs;
  1215. uint32_t num_entries_per_buf;
  1216. uint32_t rem_entries;
  1217. uint8_t *scatter_buf_ptr;
  1218. uint16_t scatter_buf_num;
  1219. soc->wbm_idle_scatter_buf_size =
  1220. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1221. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1222. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1223. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1224. soc->hal_soc, total_mem_size,
  1225. soc->wbm_idle_scatter_buf_size);
  1226. for (i = 0; i < num_scatter_bufs; i++) {
  1227. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1228. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1229. soc->wbm_idle_scatter_buf_size,
  1230. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1231. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1232. QDF_TRACE(QDF_MODULE_ID_DP,
  1233. QDF_TRACE_LEVEL_ERROR,
  1234. FL("Scatter list memory alloc failed"));
  1235. goto fail;
  1236. }
  1237. }
  1238. /* Populate idle list scatter buffers with link descriptor
  1239. * pointers
  1240. */
  1241. scatter_buf_num = 0;
  1242. scatter_buf_ptr = (uint8_t *)(
  1243. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1244. rem_entries = num_entries_per_buf;
  1245. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1246. soc->link_desc_banks[i].base_paddr; i++) {
  1247. uint32_t num_link_descs =
  1248. (soc->link_desc_banks[i].size -
  1249. ((unsigned long)(
  1250. soc->link_desc_banks[i].base_vaddr) -
  1251. (unsigned long)(
  1252. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1253. / link_desc_size;
  1254. unsigned long paddr = (unsigned long)(
  1255. soc->link_desc_banks[i].base_paddr);
  1256. while (num_link_descs) {
  1257. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1258. LINK_DESC_COOKIE(desc_id, i), paddr);
  1259. num_link_descs--;
  1260. desc_id++;
  1261. paddr += link_desc_size;
  1262. rem_entries--;
  1263. if (rem_entries) {
  1264. scatter_buf_ptr += entry_size;
  1265. } else {
  1266. rem_entries = num_entries_per_buf;
  1267. scatter_buf_num++;
  1268. if (scatter_buf_num >= num_scatter_bufs)
  1269. break;
  1270. scatter_buf_ptr = (uint8_t *)(
  1271. soc->wbm_idle_scatter_buf_base_vaddr[
  1272. scatter_buf_num]);
  1273. }
  1274. }
  1275. }
  1276. /* Setup link descriptor idle list in HW */
  1277. hal_setup_link_idle_list(soc->hal_soc,
  1278. soc->wbm_idle_scatter_buf_base_paddr,
  1279. soc->wbm_idle_scatter_buf_base_vaddr,
  1280. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1281. (uint32_t)(scatter_buf_ptr -
  1282. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1283. scatter_buf_num-1])), total_link_descs);
  1284. }
  1285. return 0;
  1286. fail:
  1287. if (soc->wbm_idle_link_ring.hal_srng) {
  1288. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1289. WBM_IDLE_LINK, 0);
  1290. }
  1291. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1292. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1293. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1294. soc->wbm_idle_scatter_buf_size,
  1295. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1296. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1297. }
  1298. }
  1299. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1300. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1301. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1302. soc->link_desc_banks[i].size,
  1303. soc->link_desc_banks[i].base_vaddr_unaligned,
  1304. soc->link_desc_banks[i].base_paddr_unaligned,
  1305. 0);
  1306. }
  1307. }
  1308. return QDF_STATUS_E_FAILURE;
  1309. }
  1310. /*
  1311. * Free link descriptor pool that was setup HW
  1312. */
  1313. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1314. {
  1315. int i;
  1316. if (soc->wbm_idle_link_ring.hal_srng) {
  1317. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1318. WBM_IDLE_LINK, 0);
  1319. }
  1320. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1321. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1322. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1323. soc->wbm_idle_scatter_buf_size,
  1324. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1325. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1326. }
  1327. }
  1328. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1329. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1330. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1331. soc->link_desc_banks[i].size,
  1332. soc->link_desc_banks[i].base_vaddr_unaligned,
  1333. soc->link_desc_banks[i].base_paddr_unaligned,
  1334. 0);
  1335. }
  1336. }
  1337. }
  1338. /* TODO: Following should be configurable */
  1339. #define WBM_RELEASE_RING_SIZE 64
  1340. #define TCL_CMD_RING_SIZE 32
  1341. #define TCL_STATUS_RING_SIZE 32
  1342. #if defined(QCA_WIFI_QCA6290)
  1343. #define REO_DST_RING_SIZE 1024
  1344. #else
  1345. #define REO_DST_RING_SIZE 2048
  1346. #endif
  1347. #define REO_REINJECT_RING_SIZE 32
  1348. #define RX_RELEASE_RING_SIZE 1024
  1349. #define REO_EXCEPTION_RING_SIZE 128
  1350. #define REO_CMD_RING_SIZE 32
  1351. #define REO_STATUS_RING_SIZE 32
  1352. #define RXDMA_BUF_RING_SIZE 1024
  1353. #define RXDMA_REFILL_RING_SIZE 2048
  1354. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1355. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1356. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1357. #define RXDMA_MONITOR_DESC_RING_SIZE 2048
  1358. #define RXDMA_ERR_DST_RING_SIZE 1024
  1359. /*
  1360. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1361. * @soc: Datapath SOC handle
  1362. *
  1363. * This is a timer function used to age out stale WDS nodes from
  1364. * AST table
  1365. */
  1366. #ifdef FEATURE_WDS
  1367. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1368. {
  1369. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1370. struct dp_pdev *pdev;
  1371. struct dp_vdev *vdev;
  1372. struct dp_peer *peer;
  1373. struct dp_ast_entry *ase, *temp_ase;
  1374. int i;
  1375. qdf_spin_lock_bh(&soc->ast_lock);
  1376. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1377. pdev = soc->pdev_list[i];
  1378. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1379. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1380. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1381. /*
  1382. * Do not expire static ast entries
  1383. */
  1384. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1385. continue;
  1386. if (ase->is_active) {
  1387. ase->is_active = FALSE;
  1388. continue;
  1389. }
  1390. DP_STATS_INC(soc, ast.aged_out, 1);
  1391. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1392. pdev->osif_pdev,
  1393. ase->mac_addr.raw);
  1394. dp_peer_del_ast(soc, ase);
  1395. }
  1396. }
  1397. }
  1398. }
  1399. qdf_spin_unlock_bh(&soc->ast_lock);
  1400. if (qdf_atomic_read(&soc->cmn_init_done))
  1401. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1402. }
  1403. /*
  1404. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1405. * @soc: Datapath SOC handle
  1406. *
  1407. * Return: None
  1408. */
  1409. static void dp_soc_wds_attach(struct dp_soc *soc)
  1410. {
  1411. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1412. dp_wds_aging_timer_fn, (void *)soc,
  1413. QDF_TIMER_TYPE_WAKE_APPS);
  1414. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1415. }
  1416. /*
  1417. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1418. * @txrx_soc: DP SOC handle
  1419. *
  1420. * Return: None
  1421. */
  1422. static void dp_soc_wds_detach(struct dp_soc *soc)
  1423. {
  1424. qdf_timer_stop(&soc->wds_aging_timer);
  1425. qdf_timer_free(&soc->wds_aging_timer);
  1426. }
  1427. #else
  1428. static void dp_soc_wds_attach(struct dp_soc *soc)
  1429. {
  1430. }
  1431. static void dp_soc_wds_detach(struct dp_soc *soc)
  1432. {
  1433. }
  1434. #endif
  1435. /*
  1436. * dp_soc_reset_ring_map() - Reset cpu ring map
  1437. * @soc: Datapath soc handler
  1438. *
  1439. * This api resets the default cpu ring map
  1440. */
  1441. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1442. {
  1443. uint8_t i;
  1444. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1445. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1446. if (nss_config == 1) {
  1447. /*
  1448. * Setting Tx ring map for one nss offloaded radio
  1449. */
  1450. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1451. } else if (nss_config == 2) {
  1452. /*
  1453. * Setting Tx ring for two nss offloaded radios
  1454. */
  1455. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1456. } else {
  1457. /*
  1458. * Setting Tx ring map for all nss offloaded radios
  1459. */
  1460. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1461. }
  1462. }
  1463. }
  1464. /*
  1465. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  1466. * @dp_soc - DP soc handle
  1467. * @ring_type - ring type
  1468. * @ring_num - ring_num
  1469. *
  1470. * return 0 or 1
  1471. */
  1472. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc, enum hal_ring_type ring_type, int ring_num)
  1473. {
  1474. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1475. uint8_t status = 0;
  1476. switch (ring_type) {
  1477. case WBM2SW_RELEASE:
  1478. case REO_DST:
  1479. status = ((nss_config) & (1 << ring_num));
  1480. break;
  1481. default:
  1482. break;
  1483. }
  1484. return status;
  1485. }
  1486. /*
  1487. * dp_soc_reset_intr_mask() - reset interrupt mask
  1488. * @dp_soc - DP Soc handle
  1489. *
  1490. * Return: Return void
  1491. */
  1492. static void dp_soc_reset_intr_mask(struct dp_soc *soc)
  1493. {
  1494. uint8_t j;
  1495. int *grp_mask = NULL;
  1496. int group_number, mask, num_ring;
  1497. /* number of tx ring */
  1498. num_ring = wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1499. /*
  1500. * group mask for tx completion ring.
  1501. */
  1502. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  1503. /* loop and reset the mask for only offloaded ring */
  1504. for (j = 0; j < num_ring; j++) {
  1505. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j)) {
  1506. continue;
  1507. }
  1508. /*
  1509. * Group number corresponding to tx offloaded ring.
  1510. */
  1511. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1512. if (group_number < 0) {
  1513. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1514. FL("ring not part of an group; ring_type: %d,ring_num %d"),
  1515. WBM2SW_RELEASE, j);
  1516. return;
  1517. }
  1518. /* reset the tx mask for offloaded ring */
  1519. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1520. mask &= (~(1 << j));
  1521. /*
  1522. * reset the interrupt mask for offloaded ring.
  1523. */
  1524. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1525. }
  1526. /* number of rx rings */
  1527. num_ring = wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1528. /*
  1529. * group mask for reo destination ring.
  1530. */
  1531. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  1532. /* loop and reset the mask for only offloaded ring */
  1533. for (j = 0; j < num_ring; j++) {
  1534. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j)) {
  1535. continue;
  1536. }
  1537. /*
  1538. * Group number corresponding to rx offloaded ring.
  1539. */
  1540. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1541. if (group_number < 0) {
  1542. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1543. FL("ring not part of an group; ring_type: %d,ring_num %d"),
  1544. REO_DST, j);
  1545. return;
  1546. }
  1547. /* set the interrupt mask for offloaded ring */
  1548. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1549. mask &= (~(1 << j));
  1550. /*
  1551. * set the interrupt mask to zero for rx offloaded radio.
  1552. */
  1553. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1554. }
  1555. }
  1556. #ifdef IPA_OFFLOAD
  1557. /**
  1558. * dp_reo_remap_config() - configure reo remap register value based
  1559. * nss configuration.
  1560. * based on offload_radio value below remap configuration
  1561. * get applied.
  1562. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1563. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1564. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1565. * 3 - both Radios handled by NSS (remap not required)
  1566. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1567. *
  1568. * @remap1: output parameter indicates reo remap 1 register value
  1569. * @remap2: output parameter indicates reo remap 2 register value
  1570. * Return: bool type, true if remap is configured else false.
  1571. */
  1572. static bool dp_reo_remap_config(struct dp_soc *soc,
  1573. uint32_t *remap1,
  1574. uint32_t *remap2)
  1575. {
  1576. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1577. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1578. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1579. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1580. return true;
  1581. }
  1582. #else
  1583. static bool dp_reo_remap_config(struct dp_soc *soc,
  1584. uint32_t *remap1,
  1585. uint32_t *remap2)
  1586. {
  1587. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1588. switch (offload_radio) {
  1589. case 0:
  1590. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1591. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1592. (0x3 << 18) | (0x4 << 21)) << 8;
  1593. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1594. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1595. (0x3 << 18) | (0x4 << 21)) << 8;
  1596. break;
  1597. case 1:
  1598. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1599. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1600. (0x2 << 18) | (0x3 << 21)) << 8;
  1601. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1602. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1603. (0x4 << 18) | (0x2 << 21)) << 8;
  1604. break;
  1605. case 2:
  1606. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1607. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1608. (0x1 << 18) | (0x3 << 21)) << 8;
  1609. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1610. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1611. (0x4 << 18) | (0x1 << 21)) << 8;
  1612. break;
  1613. case 3:
  1614. /* return false if both radios are offloaded to NSS */
  1615. return false;
  1616. }
  1617. return true;
  1618. }
  1619. #endif
  1620. /*
  1621. * dp_soc_cmn_setup() - Common SoC level initializion
  1622. * @soc: Datapath SOC handle
  1623. *
  1624. * This is an internal function used to setup common SOC data structures,
  1625. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1626. */
  1627. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1628. {
  1629. int i;
  1630. struct hal_reo_params reo_params;
  1631. int tx_ring_size;
  1632. int tx_comp_ring_size;
  1633. if (qdf_atomic_read(&soc->cmn_init_done))
  1634. return 0;
  1635. if (dp_peer_find_attach(soc))
  1636. goto fail0;
  1637. if (dp_hw_link_desc_pool_setup(soc))
  1638. goto fail1;
  1639. /* Setup SRNG rings */
  1640. /* Common rings */
  1641. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1642. WBM_RELEASE_RING_SIZE)) {
  1643. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1644. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1645. goto fail1;
  1646. }
  1647. soc->num_tcl_data_rings = 0;
  1648. /* Tx data rings */
  1649. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1650. soc->num_tcl_data_rings =
  1651. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1652. tx_comp_ring_size =
  1653. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1654. tx_ring_size =
  1655. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1656. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1657. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1658. TCL_DATA, i, 0, tx_ring_size)) {
  1659. QDF_TRACE(QDF_MODULE_ID_DP,
  1660. QDF_TRACE_LEVEL_ERROR,
  1661. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1662. goto fail1;
  1663. }
  1664. /*
  1665. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1666. * count
  1667. */
  1668. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1669. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1670. QDF_TRACE(QDF_MODULE_ID_DP,
  1671. QDF_TRACE_LEVEL_ERROR,
  1672. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1673. goto fail1;
  1674. }
  1675. }
  1676. } else {
  1677. /* This will be incremented during per pdev ring setup */
  1678. soc->num_tcl_data_rings = 0;
  1679. }
  1680. if (dp_tx_soc_attach(soc)) {
  1681. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1682. FL("dp_tx_soc_attach failed"));
  1683. goto fail1;
  1684. }
  1685. /* TCL command and status rings */
  1686. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1687. TCL_CMD_RING_SIZE)) {
  1688. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1689. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1690. goto fail1;
  1691. }
  1692. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1693. TCL_STATUS_RING_SIZE)) {
  1694. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1695. FL("dp_srng_setup failed for tcl_status_ring"));
  1696. goto fail1;
  1697. }
  1698. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1699. * descriptors
  1700. */
  1701. /* Rx data rings */
  1702. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1703. soc->num_reo_dest_rings =
  1704. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1705. QDF_TRACE(QDF_MODULE_ID_DP,
  1706. QDF_TRACE_LEVEL_ERROR,
  1707. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1708. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1709. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1710. i, 0, REO_DST_RING_SIZE)) {
  1711. QDF_TRACE(QDF_MODULE_ID_DP,
  1712. QDF_TRACE_LEVEL_ERROR,
  1713. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1714. goto fail1;
  1715. }
  1716. }
  1717. } else {
  1718. /* This will be incremented during per pdev ring setup */
  1719. soc->num_reo_dest_rings = 0;
  1720. }
  1721. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1722. /* REO reinjection ring */
  1723. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1724. REO_REINJECT_RING_SIZE)) {
  1725. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1726. FL("dp_srng_setup failed for reo_reinject_ring"));
  1727. goto fail1;
  1728. }
  1729. /* Rx release ring */
  1730. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1731. RX_RELEASE_RING_SIZE)) {
  1732. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1733. FL("dp_srng_setup failed for rx_rel_ring"));
  1734. goto fail1;
  1735. }
  1736. /* Rx exception ring */
  1737. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1738. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1740. FL("dp_srng_setup failed for reo_exception_ring"));
  1741. goto fail1;
  1742. }
  1743. /* REO command and status rings */
  1744. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1745. REO_CMD_RING_SIZE)) {
  1746. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1747. FL("dp_srng_setup failed for reo_cmd_ring"));
  1748. goto fail1;
  1749. }
  1750. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1751. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1752. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1753. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1754. REO_STATUS_RING_SIZE)) {
  1755. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1756. FL("dp_srng_setup failed for reo_status_ring"));
  1757. goto fail1;
  1758. }
  1759. qdf_spinlock_create(&soc->ast_lock);
  1760. dp_soc_wds_attach(soc);
  1761. /* Reset the cpu ring map if radio is NSS offloaded */
  1762. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1763. dp_soc_reset_cpu_ring_map(soc);
  1764. dp_soc_reset_intr_mask(soc);
  1765. }
  1766. /* Setup HW REO */
  1767. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1768. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1769. /*
  1770. * Reo ring remap is not required if both radios
  1771. * are offloaded to NSS
  1772. */
  1773. if (!dp_reo_remap_config(soc,
  1774. &reo_params.remap1,
  1775. &reo_params.remap2))
  1776. goto out;
  1777. reo_params.rx_hash_enabled = true;
  1778. }
  1779. out:
  1780. hal_reo_setup(soc->hal_soc, &reo_params);
  1781. qdf_atomic_set(&soc->cmn_init_done, 1);
  1782. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1783. return 0;
  1784. fail1:
  1785. /*
  1786. * Cleanup will be done as part of soc_detach, which will
  1787. * be called on pdev attach failure
  1788. */
  1789. fail0:
  1790. return QDF_STATUS_E_FAILURE;
  1791. }
  1792. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1793. static void dp_lro_hash_setup(struct dp_soc *soc)
  1794. {
  1795. struct cdp_lro_hash_config lro_hash;
  1796. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1797. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1798. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1799. FL("LRO disabled RX hash disabled"));
  1800. return;
  1801. }
  1802. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1803. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1804. lro_hash.lro_enable = 1;
  1805. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1806. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1807. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1808. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1809. }
  1810. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW, FL("enabled"));
  1811. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1812. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1813. LRO_IPV4_SEED_ARR_SZ));
  1814. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1815. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1816. LRO_IPV6_SEED_ARR_SZ));
  1817. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  1818. "lro_hash: lro_enable: 0x%x tcp_flag 0x%x tcp_flag_mask 0x%x",
  1819. lro_hash.lro_enable, lro_hash.tcp_flag,
  1820. lro_hash.tcp_flag_mask);
  1821. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1822. QDF_TRACE_LEVEL_ERROR,
  1823. (void *)lro_hash.toeplitz_hash_ipv4,
  1824. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1825. LRO_IPV4_SEED_ARR_SZ));
  1826. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1827. QDF_TRACE_LEVEL_ERROR,
  1828. (void *)lro_hash.toeplitz_hash_ipv6,
  1829. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1830. LRO_IPV6_SEED_ARR_SZ));
  1831. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1832. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1833. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1834. (soc->osif_soc, &lro_hash);
  1835. }
  1836. /*
  1837. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1838. * @soc: data path SoC handle
  1839. * @pdev: Physical device handle
  1840. *
  1841. * Return: 0 - success, > 0 - failure
  1842. */
  1843. #ifdef QCA_HOST2FW_RXBUF_RING
  1844. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1845. struct dp_pdev *pdev)
  1846. {
  1847. int max_mac_rings =
  1848. wlan_cfg_get_num_mac_rings
  1849. (pdev->wlan_cfg_ctx);
  1850. int i;
  1851. for (i = 0; i < max_mac_rings; i++) {
  1852. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1853. "%s: pdev_id %d mac_id %d\n",
  1854. __func__, pdev->pdev_id, i);
  1855. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1856. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1857. QDF_TRACE(QDF_MODULE_ID_DP,
  1858. QDF_TRACE_LEVEL_ERROR,
  1859. FL("failed rx mac ring setup"));
  1860. return QDF_STATUS_E_FAILURE;
  1861. }
  1862. }
  1863. return QDF_STATUS_SUCCESS;
  1864. }
  1865. #else
  1866. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1867. struct dp_pdev *pdev)
  1868. {
  1869. return QDF_STATUS_SUCCESS;
  1870. }
  1871. #endif
  1872. /**
  1873. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1874. * @pdev - DP_PDEV handle
  1875. *
  1876. * Return: void
  1877. */
  1878. static inline void
  1879. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1880. {
  1881. uint8_t map_id;
  1882. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1883. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1884. sizeof(default_dscp_tid_map));
  1885. }
  1886. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1887. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1888. pdev->dscp_tid_map[map_id],
  1889. map_id);
  1890. }
  1891. }
  1892. /*
  1893. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1894. * @soc: data path SoC handle
  1895. *
  1896. * Return: none
  1897. */
  1898. #ifdef IPA_OFFLOAD
  1899. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1900. struct dp_pdev *pdev)
  1901. {
  1902. void *hal_srng;
  1903. struct hal_srng_params srng_params;
  1904. qdf_dma_addr_t hp_addr, tp_addr;
  1905. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1906. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1907. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1908. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1909. srng_params.ring_base_paddr;
  1910. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1911. srng_params.ring_base_vaddr;
  1912. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1913. srng_params.num_entries * srng_params.entry_size;
  1914. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1915. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1916. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1917. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1918. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1919. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1920. srng_params.ring_base_paddr;
  1921. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1922. srng_params.ring_base_vaddr;
  1923. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1924. srng_params.num_entries * srng_params.entry_size;
  1925. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1926. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1927. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1928. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1929. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1930. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1931. srng_params.ring_base_paddr;
  1932. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1933. srng_params.ring_base_vaddr;
  1934. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1935. srng_params.num_entries * srng_params.entry_size;
  1936. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1937. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1938. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1939. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1940. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1941. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1942. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1943. __func__);
  1944. return -EFAULT;
  1945. }
  1946. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1947. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1948. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1949. srng_params.ring_base_paddr;
  1950. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1951. srng_params.ring_base_vaddr;
  1952. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1953. srng_params.num_entries * srng_params.entry_size;
  1954. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1955. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1956. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1957. "%s: ring_base_paddr:%pK, ring_base_vaddr:%pK"
  1958. "_entries:%d, hp_addr:%pK\n",
  1959. __func__,
  1960. (void *)srng_params.ring_base_paddr,
  1961. (void *)srng_params.ring_base_vaddr,
  1962. srng_params.num_entries,
  1963. (void *)hp_addr);
  1964. return 0;
  1965. }
  1966. #else
  1967. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1968. struct dp_pdev *pdev)
  1969. {
  1970. return 0;
  1971. }
  1972. #endif
  1973. /*
  1974. * dp_pdev_attach_wifi3() - attach txrx pdev
  1975. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1976. * @txrx_soc: Datapath SOC handle
  1977. * @htc_handle: HTC handle for host-target interface
  1978. * @qdf_osdev: QDF OS device
  1979. * @pdev_id: PDEV ID
  1980. *
  1981. * Return: DP PDEV handle on success, NULL on failure
  1982. */
  1983. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1984. struct cdp_cfg *ctrl_pdev,
  1985. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1986. {
  1987. int tx_ring_size;
  1988. int tx_comp_ring_size;
  1989. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1990. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1991. if (!pdev) {
  1992. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1993. FL("DP PDEV memory allocation failed"));
  1994. goto fail0;
  1995. }
  1996. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1997. if (!pdev->wlan_cfg_ctx) {
  1998. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1999. FL("pdev cfg_attach failed"));
  2000. qdf_mem_free(pdev);
  2001. goto fail0;
  2002. }
  2003. /*
  2004. * set nss pdev config based on soc config
  2005. */
  2006. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  2007. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  2008. pdev->soc = soc;
  2009. pdev->osif_pdev = ctrl_pdev;
  2010. pdev->pdev_id = pdev_id;
  2011. soc->pdev_list[pdev_id] = pdev;
  2012. soc->pdev_count++;
  2013. TAILQ_INIT(&pdev->vdev_list);
  2014. pdev->vdev_count = 0;
  2015. qdf_spinlock_create(&pdev->tx_mutex);
  2016. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  2017. TAILQ_INIT(&pdev->neighbour_peers_list);
  2018. if (dp_soc_cmn_setup(soc)) {
  2019. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2020. FL("dp_soc_cmn_setup failed"));
  2021. goto fail1;
  2022. }
  2023. /* Setup per PDEV TCL rings if configured */
  2024. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2025. tx_ring_size =
  2026. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2027. tx_comp_ring_size =
  2028. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  2029. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  2030. pdev_id, pdev_id, tx_ring_size)) {
  2031. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2032. FL("dp_srng_setup failed for tcl_data_ring"));
  2033. goto fail1;
  2034. }
  2035. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  2036. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  2037. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2038. FL("dp_srng_setup failed for tx_comp_ring"));
  2039. goto fail1;
  2040. }
  2041. soc->num_tcl_data_rings++;
  2042. }
  2043. /* Tx specific init */
  2044. if (dp_tx_pdev_attach(pdev)) {
  2045. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2046. FL("dp_tx_pdev_attach failed"));
  2047. goto fail1;
  2048. }
  2049. /* Setup per PDEV REO rings if configured */
  2050. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2051. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  2052. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  2053. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2054. FL("dp_srng_setup failed for reo_dest_ringn"));
  2055. goto fail1;
  2056. }
  2057. soc->num_reo_dest_rings++;
  2058. }
  2059. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  2060. RXDMA_REFILL_RING_SIZE)) {
  2061. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2062. FL("dp_srng_setup failed rx refill ring"));
  2063. goto fail1;
  2064. }
  2065. if (dp_rxdma_ring_setup(soc, pdev)) {
  2066. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2067. FL("RXDMA ring config failed"));
  2068. goto fail1;
  2069. }
  2070. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  2071. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  2072. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2073. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  2074. goto fail1;
  2075. }
  2076. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  2077. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  2078. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2079. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2080. goto fail1;
  2081. }
  2082. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  2083. RXDMA_MONITOR_STATUS, 0, pdev_id,
  2084. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  2085. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2086. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  2087. goto fail1;
  2088. }
  2089. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  2090. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  2091. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2092. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  2093. goto fail1;
  2094. }
  2095. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  2096. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  2097. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2098. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2099. goto fail1;
  2100. }
  2101. if (dp_ipa_ring_resource_setup(soc, pdev))
  2102. goto fail1;
  2103. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  2104. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2105. "%s: dp_ipa_uc_attach failed\n", __func__);
  2106. goto fail1;
  2107. }
  2108. /* Rx specific init */
  2109. if (dp_rx_pdev_attach(pdev)) {
  2110. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2111. FL("dp_rx_pdev_attach failed "));
  2112. goto fail0;
  2113. }
  2114. DP_STATS_INIT(pdev);
  2115. #ifndef CONFIG_WIN
  2116. /* MCL */
  2117. dp_local_peer_id_pool_init(pdev);
  2118. #endif
  2119. dp_dscp_tid_map_setup(pdev);
  2120. /* Rx monitor mode specific init */
  2121. if (dp_rx_pdev_mon_attach(pdev)) {
  2122. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2123. "dp_rx_pdev_attach failed\n");
  2124. goto fail1;
  2125. }
  2126. if (dp_wdi_event_attach(pdev)) {
  2127. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2128. "dp_wdi_evet_attach failed\n");
  2129. goto fail1;
  2130. }
  2131. /* set the reo destination during initialization */
  2132. pdev->reo_dest = pdev->pdev_id + 1;
  2133. return (struct cdp_pdev *)pdev;
  2134. fail1:
  2135. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2136. fail0:
  2137. return NULL;
  2138. }
  2139. /*
  2140. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2141. * @soc: data path SoC handle
  2142. * @pdev: Physical device handle
  2143. *
  2144. * Return: void
  2145. */
  2146. #ifdef QCA_HOST2FW_RXBUF_RING
  2147. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2148. struct dp_pdev *pdev)
  2149. {
  2150. int max_mac_rings =
  2151. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2152. int i;
  2153. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2154. max_mac_rings : MAX_RX_MAC_RINGS;
  2155. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2156. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2157. RXDMA_BUF, 1);
  2158. }
  2159. #else
  2160. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2161. struct dp_pdev *pdev)
  2162. {
  2163. }
  2164. #endif
  2165. /*
  2166. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2167. * @pdev: device object
  2168. *
  2169. * Return: void
  2170. */
  2171. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2172. {
  2173. struct dp_neighbour_peer *peer = NULL;
  2174. struct dp_neighbour_peer *temp_peer = NULL;
  2175. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2176. neighbour_peer_list_elem, temp_peer) {
  2177. /* delete this peer from the list */
  2178. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2179. peer, neighbour_peer_list_elem);
  2180. qdf_mem_free(peer);
  2181. }
  2182. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2183. }
  2184. /*
  2185. * dp_pdev_detach_wifi3() - detach txrx pdev
  2186. * @txrx_pdev: Datapath PDEV handle
  2187. * @force: Force detach
  2188. *
  2189. */
  2190. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2191. {
  2192. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2193. struct dp_soc *soc = pdev->soc;
  2194. dp_wdi_event_detach(pdev);
  2195. dp_tx_pdev_detach(pdev);
  2196. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2197. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2198. TCL_DATA, pdev->pdev_id);
  2199. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2200. WBM2SW_RELEASE, pdev->pdev_id);
  2201. }
  2202. dp_rx_pdev_detach(pdev);
  2203. dp_rx_pdev_mon_detach(pdev);
  2204. dp_neighbour_peers_detach(pdev);
  2205. qdf_spinlock_destroy(&pdev->tx_mutex);
  2206. dp_ipa_uc_detach(soc, pdev);
  2207. /* Cleanup per PDEV REO rings if configured */
  2208. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2209. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2210. REO_DST, pdev->pdev_id);
  2211. }
  2212. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2213. dp_rxdma_ring_cleanup(soc, pdev);
  2214. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2215. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2216. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2217. RXDMA_MONITOR_STATUS, 0);
  2218. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2219. RXDMA_MONITOR_DESC, 0);
  2220. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2221. soc->pdev_list[pdev->pdev_id] = NULL;
  2222. soc->pdev_count--;
  2223. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2224. qdf_mem_free(pdev);
  2225. }
  2226. /*
  2227. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2228. * @soc: DP SOC handle
  2229. */
  2230. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2231. {
  2232. struct reo_desc_list_node *desc;
  2233. struct dp_rx_tid *rx_tid;
  2234. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2235. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2236. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2237. rx_tid = &desc->rx_tid;
  2238. qdf_mem_unmap_nbytes_single(soc->osdev,
  2239. rx_tid->hw_qdesc_paddr,
  2240. QDF_DMA_BIDIRECTIONAL,
  2241. rx_tid->hw_qdesc_alloc_size);
  2242. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2243. qdf_mem_free(desc);
  2244. }
  2245. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2246. qdf_list_destroy(&soc->reo_desc_freelist);
  2247. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2248. }
  2249. /*
  2250. * dp_soc_detach_wifi3() - Detach txrx SOC
  2251. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2252. */
  2253. static void dp_soc_detach_wifi3(void *txrx_soc)
  2254. {
  2255. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2256. int i;
  2257. qdf_atomic_set(&soc->cmn_init_done, 0);
  2258. qdf_flush_work(&soc->htt_stats.work);
  2259. qdf_disable_work(&soc->htt_stats.work);
  2260. /* Free pending htt stats messages */
  2261. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2262. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2263. if (soc->pdev_list[i])
  2264. dp_pdev_detach_wifi3(
  2265. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2266. }
  2267. dp_peer_find_detach(soc);
  2268. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2269. * SW descriptors
  2270. */
  2271. /* Free the ring memories */
  2272. /* Common rings */
  2273. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2274. dp_tx_soc_detach(soc);
  2275. /* Tx data rings */
  2276. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2277. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2278. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2279. TCL_DATA, i);
  2280. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2281. WBM2SW_RELEASE, i);
  2282. }
  2283. }
  2284. /* TCL command and status rings */
  2285. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2286. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2287. /* Rx data rings */
  2288. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2289. soc->num_reo_dest_rings =
  2290. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2291. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2292. /* TODO: Get number of rings and ring sizes
  2293. * from wlan_cfg
  2294. */
  2295. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2296. REO_DST, i);
  2297. }
  2298. }
  2299. /* REO reinjection ring */
  2300. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2301. /* Rx release ring */
  2302. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2303. /* Rx exception ring */
  2304. /* TODO: Better to store ring_type and ring_num in
  2305. * dp_srng during setup
  2306. */
  2307. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2308. /* REO command and status rings */
  2309. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2310. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2311. dp_hw_link_desc_pool_cleanup(soc);
  2312. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2313. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2314. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2315. htt_soc_detach(soc->htt_handle);
  2316. dp_reo_cmdlist_destroy(soc);
  2317. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2318. dp_reo_desc_freelist_destroy(soc);
  2319. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2320. dp_soc_wds_detach(soc);
  2321. qdf_spinlock_destroy(&soc->ast_lock);
  2322. qdf_mem_free(soc);
  2323. }
  2324. /*
  2325. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2326. * @soc: data path SoC handle
  2327. * @pdev: physical device handle
  2328. *
  2329. * Return: void
  2330. */
  2331. #ifdef IPA_OFFLOAD
  2332. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2333. struct dp_pdev *pdev)
  2334. {
  2335. htt_srng_setup(soc->htt_handle, 0,
  2336. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2337. }
  2338. #else
  2339. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2340. struct dp_pdev *pdev)
  2341. {
  2342. }
  2343. #endif
  2344. /*
  2345. * dp_rxdma_ring_config() - configure the RX DMA rings
  2346. *
  2347. * This function is used to configure the MAC rings.
  2348. * On MCL host provides buffers in Host2FW ring
  2349. * FW refills (copies) buffers to the ring and updates
  2350. * ring_idx in register
  2351. *
  2352. * @soc: data path SoC handle
  2353. *
  2354. * Return: void
  2355. */
  2356. #ifdef QCA_HOST2FW_RXBUF_RING
  2357. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2358. {
  2359. int i;
  2360. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2361. struct dp_pdev *pdev = soc->pdev_list[i];
  2362. if (pdev) {
  2363. int mac_id = 0;
  2364. int j;
  2365. bool dbs_enable = 0;
  2366. int max_mac_rings =
  2367. wlan_cfg_get_num_mac_rings
  2368. (pdev->wlan_cfg_ctx);
  2369. htt_srng_setup(soc->htt_handle, 0,
  2370. pdev->rx_refill_buf_ring.hal_srng,
  2371. RXDMA_BUF);
  2372. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2373. if (soc->cdp_soc.ol_ops->
  2374. is_hw_dbs_2x2_capable) {
  2375. dbs_enable = soc->cdp_soc.ol_ops->
  2376. is_hw_dbs_2x2_capable(soc->psoc);
  2377. }
  2378. if (dbs_enable) {
  2379. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2380. QDF_TRACE_LEVEL_ERROR,
  2381. FL("DBS enabled max_mac_rings %d\n"),
  2382. max_mac_rings);
  2383. } else {
  2384. max_mac_rings = 1;
  2385. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2386. QDF_TRACE_LEVEL_ERROR,
  2387. FL("DBS disabled, max_mac_rings %d\n"),
  2388. max_mac_rings);
  2389. }
  2390. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2391. FL("pdev_id %d max_mac_rings %d\n"),
  2392. pdev->pdev_id, max_mac_rings);
  2393. for (j = 0; j < max_mac_rings; j++) {
  2394. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2395. QDF_TRACE_LEVEL_ERROR,
  2396. FL("mac_id %d\n"), mac_id);
  2397. htt_srng_setup(soc->htt_handle, mac_id,
  2398. pdev->rx_mac_buf_ring[j]
  2399. .hal_srng,
  2400. RXDMA_BUF);
  2401. mac_id++;
  2402. }
  2403. /* Configure monitor mode rings */
  2404. htt_srng_setup(soc->htt_handle, i,
  2405. pdev->rxdma_mon_buf_ring.hal_srng,
  2406. RXDMA_MONITOR_BUF);
  2407. htt_srng_setup(soc->htt_handle, i,
  2408. pdev->rxdma_mon_dst_ring.hal_srng,
  2409. RXDMA_MONITOR_DST);
  2410. htt_srng_setup(soc->htt_handle, i,
  2411. pdev->rxdma_mon_status_ring.hal_srng,
  2412. RXDMA_MONITOR_STATUS);
  2413. htt_srng_setup(soc->htt_handle, i,
  2414. pdev->rxdma_mon_desc_ring.hal_srng,
  2415. RXDMA_MONITOR_DESC);
  2416. htt_srng_setup(soc->htt_handle, i,
  2417. pdev->rxdma_err_dst_ring.hal_srng,
  2418. RXDMA_DST);
  2419. }
  2420. }
  2421. }
  2422. #else
  2423. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2424. {
  2425. int i;
  2426. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2427. struct dp_pdev *pdev = soc->pdev_list[i];
  2428. if (pdev) {
  2429. htt_srng_setup(soc->htt_handle, i,
  2430. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2431. htt_srng_setup(soc->htt_handle, i,
  2432. pdev->rxdma_mon_buf_ring.hal_srng,
  2433. RXDMA_MONITOR_BUF);
  2434. htt_srng_setup(soc->htt_handle, i,
  2435. pdev->rxdma_mon_dst_ring.hal_srng,
  2436. RXDMA_MONITOR_DST);
  2437. htt_srng_setup(soc->htt_handle, i,
  2438. pdev->rxdma_mon_status_ring.hal_srng,
  2439. RXDMA_MONITOR_STATUS);
  2440. htt_srng_setup(soc->htt_handle, i,
  2441. pdev->rxdma_mon_desc_ring.hal_srng,
  2442. RXDMA_MONITOR_DESC);
  2443. htt_srng_setup(soc->htt_handle, i,
  2444. pdev->rxdma_err_dst_ring.hal_srng,
  2445. RXDMA_DST);
  2446. }
  2447. }
  2448. }
  2449. #endif
  2450. /*
  2451. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2452. * @txrx_soc: Datapath SOC handle
  2453. */
  2454. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2455. {
  2456. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2457. htt_soc_attach_target(soc->htt_handle);
  2458. dp_rxdma_ring_config(soc);
  2459. DP_STATS_INIT(soc);
  2460. /* initialize work queue for stats processing */
  2461. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2462. return 0;
  2463. }
  2464. /*
  2465. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2466. * @txrx_soc: Datapath SOC handle
  2467. */
  2468. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2469. {
  2470. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2471. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2472. }
  2473. /*
  2474. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2475. * @txrx_soc: Datapath SOC handle
  2476. * @nss_cfg: nss config
  2477. */
  2478. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2479. {
  2480. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2481. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2482. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2483. FL("nss-wifi<0> nss config is enabled"));
  2484. }
  2485. /*
  2486. * dp_vdev_attach_wifi3() - attach txrx vdev
  2487. * @txrx_pdev: Datapath PDEV handle
  2488. * @vdev_mac_addr: MAC address of the virtual interface
  2489. * @vdev_id: VDEV Id
  2490. * @wlan_op_mode: VDEV operating mode
  2491. *
  2492. * Return: DP VDEV handle on success, NULL on failure
  2493. */
  2494. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2495. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2496. {
  2497. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2498. struct dp_soc *soc = pdev->soc;
  2499. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2500. int tx_ring_size;
  2501. if (!vdev) {
  2502. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2503. FL("DP VDEV memory allocation failed"));
  2504. goto fail0;
  2505. }
  2506. vdev->pdev = pdev;
  2507. vdev->vdev_id = vdev_id;
  2508. vdev->opmode = op_mode;
  2509. vdev->osdev = soc->osdev;
  2510. vdev->osif_rx = NULL;
  2511. vdev->osif_rsim_rx_decap = NULL;
  2512. vdev->osif_get_key = NULL;
  2513. vdev->osif_rx_mon = NULL;
  2514. vdev->osif_tx_free_ext = NULL;
  2515. vdev->osif_vdev = NULL;
  2516. vdev->delete.pending = 0;
  2517. vdev->safemode = 0;
  2518. vdev->drop_unenc = 1;
  2519. #ifdef notyet
  2520. vdev->filters_num = 0;
  2521. #endif
  2522. qdf_mem_copy(
  2523. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2524. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2525. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2526. vdev->dscp_tid_map_id = 0;
  2527. vdev->mcast_enhancement_en = 0;
  2528. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2529. /* TODO: Initialize default HTT meta data that will be used in
  2530. * TCL descriptors for packets transmitted from this VDEV
  2531. */
  2532. TAILQ_INIT(&vdev->peer_list);
  2533. /* add this vdev into the pdev's list */
  2534. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2535. pdev->vdev_count++;
  2536. dp_tx_vdev_attach(vdev);
  2537. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2538. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2539. goto fail1;
  2540. if ((soc->intr_mode == DP_INTR_POLL) &&
  2541. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2542. if (pdev->vdev_count == 1)
  2543. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2544. }
  2545. dp_lro_hash_setup(soc);
  2546. /* LRO */
  2547. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2548. wlan_op_mode_sta == vdev->opmode)
  2549. vdev->lro_enable = true;
  2550. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2551. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2552. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2553. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2554. DP_STATS_INIT(vdev);
  2555. return (struct cdp_vdev *)vdev;
  2556. fail1:
  2557. dp_tx_vdev_detach(vdev);
  2558. qdf_mem_free(vdev);
  2559. fail0:
  2560. return NULL;
  2561. }
  2562. /**
  2563. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2564. * @vdev: Datapath VDEV handle
  2565. * @osif_vdev: OSIF vdev handle
  2566. * @txrx_ops: Tx and Rx operations
  2567. *
  2568. * Return: DP VDEV handle on success, NULL on failure
  2569. */
  2570. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2571. void *osif_vdev,
  2572. struct ol_txrx_ops *txrx_ops)
  2573. {
  2574. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2575. vdev->osif_vdev = osif_vdev;
  2576. vdev->osif_rx = txrx_ops->rx.rx;
  2577. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2578. vdev->osif_get_key = txrx_ops->get_key;
  2579. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2580. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2581. #ifdef notyet
  2582. #if ATH_SUPPORT_WAPI
  2583. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2584. #endif
  2585. #endif
  2586. #ifdef UMAC_SUPPORT_PROXY_ARP
  2587. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2588. #endif
  2589. vdev->me_convert = txrx_ops->me_convert;
  2590. /* TODO: Enable the following once Tx code is integrated */
  2591. txrx_ops->tx.tx = dp_tx_send;
  2592. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  2593. "DP Vdev Register success");
  2594. }
  2595. /*
  2596. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2597. * @txrx_vdev: Datapath VDEV handle
  2598. * @callback: Callback OL_IF on completion of detach
  2599. * @cb_context: Callback context
  2600. *
  2601. */
  2602. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2603. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2604. {
  2605. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2606. struct dp_pdev *pdev = vdev->pdev;
  2607. struct dp_soc *soc = pdev->soc;
  2608. /* preconditions */
  2609. qdf_assert(vdev);
  2610. /* remove the vdev from its parent pdev's list */
  2611. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2612. /*
  2613. * Use peer_ref_mutex while accessing peer_list, in case
  2614. * a peer is in the process of being removed from the list.
  2615. */
  2616. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2617. /* check that the vdev has no peers allocated */
  2618. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2619. /* debug print - will be removed later */
  2620. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2621. FL("not deleting vdev object %pK (%pM)"
  2622. "until deletion finishes for all its peers"),
  2623. vdev, vdev->mac_addr.raw);
  2624. /* indicate that the vdev needs to be deleted */
  2625. vdev->delete.pending = 1;
  2626. vdev->delete.callback = callback;
  2627. vdev->delete.context = cb_context;
  2628. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2629. return;
  2630. }
  2631. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2632. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2633. vdev->vdev_id);
  2634. dp_tx_vdev_detach(vdev);
  2635. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2636. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  2637. qdf_mem_free(vdev);
  2638. if (callback)
  2639. callback(cb_context);
  2640. }
  2641. /*
  2642. * dp_peer_create_wifi3() - attach txrx peer
  2643. * @txrx_vdev: Datapath VDEV handle
  2644. * @peer_mac_addr: Peer MAC address
  2645. *
  2646. * Return: DP peeer handle on success, NULL on failure
  2647. */
  2648. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2649. uint8_t *peer_mac_addr)
  2650. {
  2651. struct dp_peer *peer;
  2652. int i;
  2653. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2654. struct dp_pdev *pdev;
  2655. struct dp_soc *soc;
  2656. /* preconditions */
  2657. qdf_assert(vdev);
  2658. qdf_assert(peer_mac_addr);
  2659. pdev = vdev->pdev;
  2660. soc = pdev->soc;
  2661. #ifdef notyet
  2662. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2663. soc->mempool_ol_ath_peer);
  2664. #else
  2665. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2666. #endif
  2667. if (!peer)
  2668. return NULL; /* failure */
  2669. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2670. TAILQ_INIT(&peer->ast_entry_list);
  2671. /* store provided params */
  2672. peer->vdev = vdev;
  2673. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2674. qdf_spinlock_create(&peer->peer_info_lock);
  2675. qdf_mem_copy(
  2676. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2677. /* TODO: See of rx_opt_proc is really required */
  2678. peer->rx_opt_proc = soc->rx_opt_proc;
  2679. /* initialize the peer_id */
  2680. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2681. peer->peer_ids[i] = HTT_INVALID_PEER;
  2682. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2683. qdf_atomic_init(&peer->ref_cnt);
  2684. /* keep one reference for attach */
  2685. qdf_atomic_inc(&peer->ref_cnt);
  2686. /* add this peer into the vdev's list */
  2687. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2688. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2689. /* TODO: See if hash based search is required */
  2690. dp_peer_find_hash_add(soc, peer);
  2691. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2692. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  2693. vdev, peer, peer->mac_addr.raw,
  2694. qdf_atomic_read(&peer->ref_cnt));
  2695. /*
  2696. * For every peer MAp message search and set if bss_peer
  2697. */
  2698. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2699. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2700. "vdev bss_peer!!!!");
  2701. peer->bss_peer = 1;
  2702. vdev->vap_bss_peer = peer;
  2703. }
  2704. #ifndef CONFIG_WIN
  2705. dp_local_peer_id_alloc(pdev, peer);
  2706. #endif
  2707. DP_STATS_INIT(peer);
  2708. return (void *)peer;
  2709. }
  2710. /*
  2711. * dp_peer_setup_wifi3() - initialize the peer
  2712. * @vdev_hdl: virtual device object
  2713. * @peer: Peer object
  2714. *
  2715. * Return: void
  2716. */
  2717. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2718. {
  2719. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2720. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2721. struct dp_pdev *pdev;
  2722. struct dp_soc *soc;
  2723. bool hash_based = 0;
  2724. enum cdp_host_reo_dest_ring reo_dest;
  2725. /* preconditions */
  2726. qdf_assert(vdev);
  2727. qdf_assert(peer);
  2728. pdev = vdev->pdev;
  2729. soc = pdev->soc;
  2730. dp_peer_rx_init(pdev, peer);
  2731. peer->last_assoc_rcvd = 0;
  2732. peer->last_disassoc_rcvd = 0;
  2733. peer->last_deauth_rcvd = 0;
  2734. /*
  2735. * hash based steering is disabled for Radios which are offloaded
  2736. * to NSS
  2737. */
  2738. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2739. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2740. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2741. FL("hash based steering for pdev: %d is %d\n"),
  2742. pdev->pdev_id, hash_based);
  2743. /*
  2744. * Below line of code will ensure the proper reo_dest ring is choosen
  2745. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  2746. */
  2747. reo_dest = pdev->reo_dest;
  2748. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2749. /* TODO: Check the destination ring number to be passed to FW */
  2750. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2751. pdev->osif_pdev, peer->mac_addr.raw,
  2752. peer->vdev->vdev_id, hash_based, reo_dest);
  2753. }
  2754. return;
  2755. }
  2756. /*
  2757. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2758. * @vdev_handle: virtual device object
  2759. * @htt_pkt_type: type of pkt
  2760. *
  2761. * Return: void
  2762. */
  2763. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2764. enum htt_cmn_pkt_type val)
  2765. {
  2766. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2767. vdev->tx_encap_type = val;
  2768. }
  2769. /*
  2770. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2771. * @vdev_handle: virtual device object
  2772. * @htt_pkt_type: type of pkt
  2773. *
  2774. * Return: void
  2775. */
  2776. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2777. enum htt_cmn_pkt_type val)
  2778. {
  2779. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2780. vdev->rx_decap_type = val;
  2781. }
  2782. /*
  2783. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2784. * @pdev_handle: physical device object
  2785. * @val: reo destination ring index (1 - 4)
  2786. *
  2787. * Return: void
  2788. */
  2789. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2790. enum cdp_host_reo_dest_ring val)
  2791. {
  2792. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2793. if (pdev)
  2794. pdev->reo_dest = val;
  2795. }
  2796. /*
  2797. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2798. * @pdev_handle: physical device object
  2799. *
  2800. * Return: reo destination ring index
  2801. */
  2802. static enum cdp_host_reo_dest_ring
  2803. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2804. {
  2805. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2806. if (pdev)
  2807. return pdev->reo_dest;
  2808. else
  2809. return cdp_host_reo_dest_ring_unknown;
  2810. }
  2811. #ifdef QCA_SUPPORT_SON
  2812. static void dp_son_peer_authorize(struct dp_peer *peer)
  2813. {
  2814. struct dp_soc *soc;
  2815. soc = peer->vdev->pdev->soc;
  2816. peer->peer_bs_inact_flag = 0;
  2817. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2818. return;
  2819. }
  2820. #else
  2821. static void dp_son_peer_authorize(struct dp_peer *peer)
  2822. {
  2823. return;
  2824. }
  2825. #endif
  2826. /*
  2827. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2828. * @pdev_handle: device object
  2829. * @val: value to be set
  2830. *
  2831. * Return: void
  2832. */
  2833. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2834. uint32_t val)
  2835. {
  2836. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2837. /* Enable/Disable smart mesh filtering. This flag will be checked
  2838. * during rx processing to check if packets are from NAC clients.
  2839. */
  2840. pdev->filter_neighbour_peers = val;
  2841. return 0;
  2842. }
  2843. /*
  2844. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2845. * address for smart mesh filtering
  2846. * @pdev_handle: device object
  2847. * @cmd: Add/Del command
  2848. * @macaddr: nac client mac address
  2849. *
  2850. * Return: void
  2851. */
  2852. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2853. uint32_t cmd, uint8_t *macaddr)
  2854. {
  2855. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2856. struct dp_neighbour_peer *peer = NULL;
  2857. if (!macaddr)
  2858. goto fail0;
  2859. /* Store address of NAC (neighbour peer) which will be checked
  2860. * against TA of received packets.
  2861. */
  2862. if (cmd == DP_NAC_PARAM_ADD) {
  2863. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2864. sizeof(*peer));
  2865. if (!peer) {
  2866. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2867. FL("DP neighbour peer node memory allocation failed"));
  2868. goto fail0;
  2869. }
  2870. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2871. macaddr, DP_MAC_ADDR_LEN);
  2872. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2873. /* add this neighbour peer into the list */
  2874. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2875. neighbour_peer_list_elem);
  2876. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2877. return 1;
  2878. } else if (cmd == DP_NAC_PARAM_DEL) {
  2879. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2880. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2881. neighbour_peer_list_elem) {
  2882. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2883. macaddr, DP_MAC_ADDR_LEN)) {
  2884. /* delete this peer from the list */
  2885. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2886. peer, neighbour_peer_list_elem);
  2887. qdf_mem_free(peer);
  2888. break;
  2889. }
  2890. }
  2891. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2892. return 1;
  2893. }
  2894. fail0:
  2895. return 0;
  2896. }
  2897. /*
  2898. * dp_get_sec_type() - Get the security type
  2899. * @peer: Datapath peer handle
  2900. * @sec_idx: Security id (mcast, ucast)
  2901. *
  2902. * return sec_type: Security type
  2903. */
  2904. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2905. {
  2906. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2907. return dpeer->security[sec_idx].sec_type;
  2908. }
  2909. /*
  2910. * dp_peer_authorize() - authorize txrx peer
  2911. * @peer_handle: Datapath peer handle
  2912. * @authorize
  2913. *
  2914. */
  2915. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2916. {
  2917. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2918. struct dp_soc *soc;
  2919. if (peer != NULL) {
  2920. soc = peer->vdev->pdev->soc;
  2921. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2922. dp_son_peer_authorize(peer);
  2923. peer->authorize = authorize ? 1 : 0;
  2924. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2925. }
  2926. }
  2927. /*
  2928. * dp_peer_unref_delete() - unref and delete peer
  2929. * @peer_handle: Datapath peer handle
  2930. *
  2931. */
  2932. void dp_peer_unref_delete(void *peer_handle)
  2933. {
  2934. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2935. struct dp_vdev *vdev = peer->vdev;
  2936. struct dp_pdev *pdev = vdev->pdev;
  2937. struct dp_soc *soc = pdev->soc;
  2938. struct dp_peer *tmppeer;
  2939. int found = 0;
  2940. uint16_t peer_id;
  2941. /*
  2942. * Hold the lock all the way from checking if the peer ref count
  2943. * is zero until the peer references are removed from the hash
  2944. * table and vdev list (if the peer ref count is zero).
  2945. * This protects against a new HL tx operation starting to use the
  2946. * peer object just after this function concludes it's done being used.
  2947. * Furthermore, the lock needs to be held while checking whether the
  2948. * vdev's list of peers is empty, to make sure that list is not modified
  2949. * concurrently with the empty check.
  2950. */
  2951. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2952. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2953. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  2954. peer, qdf_atomic_read(&peer->ref_cnt));
  2955. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2956. peer_id = peer->peer_ids[0];
  2957. /*
  2958. * Make sure that the reference to the peer in
  2959. * peer object map is removed
  2960. */
  2961. if (peer_id != HTT_INVALID_PEER)
  2962. soc->peer_id_to_obj_map[peer_id] = NULL;
  2963. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2964. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  2965. /* remove the reference to the peer from the hash table */
  2966. dp_peer_find_hash_remove(soc, peer);
  2967. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2968. if (tmppeer == peer) {
  2969. found = 1;
  2970. break;
  2971. }
  2972. }
  2973. if (found) {
  2974. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2975. peer_list_elem);
  2976. } else {
  2977. /*Ignoring the remove operation as peer not found*/
  2978. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2979. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  2980. peer, vdev, &peer->vdev->peer_list);
  2981. }
  2982. /* cleanup the peer data */
  2983. dp_peer_cleanup(vdev, peer);
  2984. /* check whether the parent vdev has no peers left */
  2985. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2986. /*
  2987. * Now that there are no references to the peer, we can
  2988. * release the peer reference lock.
  2989. */
  2990. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2991. /*
  2992. * Check if the parent vdev was waiting for its peers
  2993. * to be deleted, in order for it to be deleted too.
  2994. */
  2995. if (vdev->delete.pending) {
  2996. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2997. vdev->delete.callback;
  2998. void *vdev_delete_context =
  2999. vdev->delete.context;
  3000. QDF_TRACE(QDF_MODULE_ID_DP,
  3001. QDF_TRACE_LEVEL_INFO_HIGH,
  3002. FL("deleting vdev object %pK (%pM)"
  3003. " - its last peer is done"),
  3004. vdev, vdev->mac_addr.raw);
  3005. /* all peers are gone, go ahead and delete it */
  3006. qdf_mem_free(vdev);
  3007. if (vdev_delete_cb)
  3008. vdev_delete_cb(vdev_delete_context);
  3009. }
  3010. } else {
  3011. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3012. }
  3013. #ifdef notyet
  3014. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  3015. #else
  3016. qdf_mem_free(peer);
  3017. #endif
  3018. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  3019. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  3020. vdev->vdev_id, peer->mac_addr.raw);
  3021. }
  3022. } else {
  3023. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3024. }
  3025. }
  3026. /*
  3027. * dp_peer_detach_wifi3() – Detach txrx peer
  3028. * @peer_handle: Datapath peer handle
  3029. *
  3030. */
  3031. static void dp_peer_delete_wifi3(void *peer_handle)
  3032. {
  3033. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3034. /* redirect the peer's rx delivery function to point to a
  3035. * discard func
  3036. */
  3037. peer->rx_opt_proc = dp_rx_discard;
  3038. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  3039. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  3040. #ifndef CONFIG_WIN
  3041. dp_local_peer_id_free(peer->vdev->pdev, peer);
  3042. #endif
  3043. qdf_spinlock_destroy(&peer->peer_info_lock);
  3044. /*
  3045. * Remove the reference added during peer_attach.
  3046. * The peer will still be left allocated until the
  3047. * PEER_UNMAP message arrives to remove the other
  3048. * reference, added by the PEER_MAP message.
  3049. */
  3050. dp_peer_unref_delete(peer_handle);
  3051. }
  3052. /*
  3053. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  3054. * @peer_handle: Datapath peer handle
  3055. *
  3056. */
  3057. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  3058. {
  3059. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3060. return vdev->mac_addr.raw;
  3061. }
  3062. /*
  3063. * dp_vdev_set_wds() - Enable per packet stats
  3064. * @vdev_handle: DP VDEV handle
  3065. * @val: value
  3066. *
  3067. * Return: none
  3068. */
  3069. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  3070. {
  3071. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3072. vdev->wds_enabled = val;
  3073. return 0;
  3074. }
  3075. /*
  3076. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  3077. * @peer_handle: Datapath peer handle
  3078. *
  3079. */
  3080. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  3081. uint8_t vdev_id)
  3082. {
  3083. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  3084. struct dp_vdev *vdev = NULL;
  3085. if (qdf_unlikely(!pdev))
  3086. return NULL;
  3087. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3088. if (vdev->vdev_id == vdev_id)
  3089. break;
  3090. }
  3091. return (struct cdp_vdev *)vdev;
  3092. }
  3093. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  3094. {
  3095. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3096. return vdev->opmode;
  3097. }
  3098. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  3099. {
  3100. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3101. struct dp_pdev *pdev = vdev->pdev;
  3102. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  3103. }
  3104. /**
  3105. * dp_reset_monitor_mode() - Disable monitor mode
  3106. * @pdev_handle: Datapath PDEV handle
  3107. *
  3108. * Return: 0 on success, not 0 on failure
  3109. */
  3110. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  3111. {
  3112. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3113. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3114. struct dp_soc *soc;
  3115. uint8_t pdev_id;
  3116. pdev_id = pdev->pdev_id;
  3117. soc = pdev->soc;
  3118. pdev->monitor_vdev = NULL;
  3119. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  3120. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3121. pdev->rxdma_mon_buf_ring.hal_srng,
  3122. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3123. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3124. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3125. RX_BUFFER_SIZE, &htt_tlv_filter);
  3126. return 0;
  3127. }
  3128. /**
  3129. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3130. * @vdev_handle: Datapath VDEV handle
  3131. * @smart_monitor: Flag to denote if its smart monitor mode
  3132. *
  3133. * Return: 0 on success, not 0 on failure
  3134. */
  3135. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3136. uint8_t smart_monitor)
  3137. {
  3138. /* Many monitor VAPs can exists in a system but only one can be up at
  3139. * anytime
  3140. */
  3141. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3142. struct dp_pdev *pdev;
  3143. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3144. struct dp_soc *soc;
  3145. uint8_t pdev_id;
  3146. qdf_assert(vdev);
  3147. pdev = vdev->pdev;
  3148. pdev_id = pdev->pdev_id;
  3149. soc = pdev->soc;
  3150. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3151. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  3152. pdev, pdev_id, soc, vdev);
  3153. /*Check if current pdev's monitor_vdev exists */
  3154. if (pdev->monitor_vdev) {
  3155. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3156. "vdev=%pK\n", vdev);
  3157. qdf_assert(vdev);
  3158. }
  3159. pdev->monitor_vdev = vdev;
  3160. /* If smart monitor mode, do not configure monitor ring */
  3161. if (smart_monitor)
  3162. return QDF_STATUS_SUCCESS;
  3163. htt_tlv_filter.mpdu_start = 1;
  3164. htt_tlv_filter.msdu_start = 1;
  3165. htt_tlv_filter.packet = 1;
  3166. htt_tlv_filter.msdu_end = 1;
  3167. htt_tlv_filter.mpdu_end = 1;
  3168. htt_tlv_filter.packet_header = 1;
  3169. htt_tlv_filter.attention = 1;
  3170. htt_tlv_filter.ppdu_start = 0;
  3171. htt_tlv_filter.ppdu_end = 0;
  3172. htt_tlv_filter.ppdu_end_user_stats = 0;
  3173. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3174. htt_tlv_filter.ppdu_end_status_done = 0;
  3175. htt_tlv_filter.header_per_msdu = 1;
  3176. htt_tlv_filter.enable_fp = 1;
  3177. htt_tlv_filter.enable_md = 0;
  3178. htt_tlv_filter.enable_mo = 1;
  3179. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3180. pdev->rxdma_mon_buf_ring.hal_srng,
  3181. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3182. htt_tlv_filter.mpdu_start = 1;
  3183. htt_tlv_filter.msdu_start = 1;
  3184. htt_tlv_filter.packet = 0;
  3185. htt_tlv_filter.msdu_end = 1;
  3186. htt_tlv_filter.mpdu_end = 1;
  3187. htt_tlv_filter.packet_header = 1;
  3188. htt_tlv_filter.attention = 1;
  3189. htt_tlv_filter.ppdu_start = 1;
  3190. htt_tlv_filter.ppdu_end = 1;
  3191. htt_tlv_filter.ppdu_end_user_stats = 1;
  3192. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3193. htt_tlv_filter.ppdu_end_status_done = 1;
  3194. htt_tlv_filter.header_per_msdu = 0;
  3195. htt_tlv_filter.enable_fp = 1;
  3196. htt_tlv_filter.enable_md = 0;
  3197. htt_tlv_filter.enable_mo = 1;
  3198. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3199. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3200. RX_BUFFER_SIZE, &htt_tlv_filter);
  3201. return QDF_STATUS_SUCCESS;
  3202. }
  3203. #ifdef MESH_MODE_SUPPORT
  3204. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3205. {
  3206. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3207. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3208. FL("val %d"), val);
  3209. vdev->mesh_vdev = val;
  3210. }
  3211. /*
  3212. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3213. * @vdev_hdl: virtual device object
  3214. * @val: value to be set
  3215. *
  3216. * Return: void
  3217. */
  3218. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3219. {
  3220. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3221. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3222. FL("val %d"), val);
  3223. vdev->mesh_rx_filter = val;
  3224. }
  3225. #endif
  3226. /*
  3227. * dp_aggregate_pdev_ctrl_frames_stats()- function to agreegate peer stats
  3228. * Current scope is bar recieved count
  3229. *
  3230. * @pdev_handle: DP_PDEV handle
  3231. *
  3232. * Return: void
  3233. */
  3234. #define STATS_PROC_TIMEOUT (HZ/10)
  3235. static void
  3236. dp_aggregate_pdev_ctrl_frames_stats(struct dp_pdev *pdev)
  3237. {
  3238. struct dp_vdev *vdev;
  3239. struct dp_peer *peer;
  3240. uint32_t waitcnt;
  3241. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3242. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3243. if (!peer) {
  3244. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3245. FL("DP Invalid Peer refernce"));
  3246. return;
  3247. }
  3248. waitcnt = 0;
  3249. dp_peer_rxtid_stats(peer, dp_rx_bar_stats_cb, pdev);
  3250. while (!(qdf_atomic_read(&(pdev->stats.cmd_complete)))
  3251. && waitcnt < 10) {
  3252. schedule_timeout_interruptible(
  3253. STATS_PROC_TIMEOUT);
  3254. waitcnt++;
  3255. }
  3256. qdf_atomic_set(&(pdev->stats.cmd_complete), 0);
  3257. }
  3258. }
  3259. }
  3260. /**
  3261. * dp_rx_bar_stats_cb(): BAR received stats callback
  3262. * @soc: SOC handle
  3263. * @cb_ctxt: Call back context
  3264. * @reo_status: Reo status
  3265. *
  3266. * return: void
  3267. */
  3268. void dp_rx_bar_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3269. union hal_reo_status *reo_status)
  3270. {
  3271. struct dp_pdev *pdev = (struct dp_pdev *)cb_ctxt;
  3272. struct hal_reo_queue_status *queue_status = &(reo_status->queue_status);
  3273. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3274. DP_TRACE_STATS(FATAL, "REO stats failure %d \n",
  3275. queue_status->header.status);
  3276. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3277. return;
  3278. }
  3279. pdev->stats.rx.bar_recv_cnt += queue_status->bar_rcvd_cnt;
  3280. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3281. }
  3282. /**
  3283. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3284. * @vdev: DP VDEV handle
  3285. *
  3286. * return: void
  3287. */
  3288. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3289. {
  3290. struct dp_peer *peer = NULL;
  3291. struct dp_soc *soc = vdev->pdev->soc;
  3292. int i;
  3293. uint8_t pream_type;
  3294. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3295. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3296. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3297. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3298. for (i = 0; i < MAX_MCS; i++) {
  3299. DP_STATS_AGGR(vdev, peer,
  3300. tx.pkt_type[pream_type].mcs_count[i]);
  3301. DP_STATS_AGGR(vdev, peer,
  3302. rx.pkt_type[pream_type].mcs_count[i]);
  3303. }
  3304. }
  3305. for (i = 0; i < MAX_BW; i++) {
  3306. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3307. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3308. }
  3309. for (i = 0; i < SS_COUNT; i++)
  3310. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3311. for (i = 0; i < WME_AC_MAX; i++) {
  3312. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3313. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3314. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3315. }
  3316. for (i = 0; i < MAX_GI; i++) {
  3317. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3318. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3319. }
  3320. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3321. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3322. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3323. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3324. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3325. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3326. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3327. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3328. DP_STATS_AGGR(vdev, peer, tx.retries);
  3329. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3330. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3331. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3332. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3333. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3334. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3335. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3336. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3337. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3338. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3339. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3340. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3341. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3342. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3343. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3344. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3345. peer->stats.rx.multicast.num;
  3346. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3347. peer->stats.rx.multicast.bytes;
  3348. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3349. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3350. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3351. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3352. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3353. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3354. vdev->stats.tx.last_ack_rssi =
  3355. peer->stats.tx.last_ack_rssi;
  3356. }
  3357. if (soc->cdp_soc.ol_ops->update_dp_stats)
  3358. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3359. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3360. }
  3361. /**
  3362. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3363. * @pdev: DP PDEV handle
  3364. *
  3365. * return: void
  3366. */
  3367. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3368. {
  3369. struct dp_vdev *vdev = NULL;
  3370. uint8_t i;
  3371. uint8_t pream_type;
  3372. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3373. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3374. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3375. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3376. dp_aggregate_vdev_stats(vdev);
  3377. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3378. for (i = 0; i < MAX_MCS; i++) {
  3379. DP_STATS_AGGR(pdev, vdev,
  3380. tx.pkt_type[pream_type].mcs_count[i]);
  3381. DP_STATS_AGGR(pdev, vdev,
  3382. rx.pkt_type[pream_type].mcs_count[i]);
  3383. }
  3384. }
  3385. for (i = 0; i < MAX_BW; i++) {
  3386. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3387. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3388. }
  3389. for (i = 0; i < SS_COUNT; i++)
  3390. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3391. for (i = 0; i < WME_AC_MAX; i++) {
  3392. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3393. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3394. DP_STATS_AGGR(pdev, vdev,
  3395. tx.excess_retries_ac[i]);
  3396. }
  3397. for (i = 0; i < MAX_GI; i++) {
  3398. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3399. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3400. }
  3401. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3402. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3403. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3404. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3405. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3406. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3407. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3408. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3409. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3410. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3411. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3412. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3413. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3414. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3415. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3416. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3417. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3418. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3419. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3420. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3421. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3422. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3423. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3424. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3425. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3426. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3427. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3428. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3429. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3430. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3431. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3432. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3433. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3434. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3435. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3436. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3437. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3438. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3439. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3440. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3441. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3442. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3443. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3444. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3445. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3446. DP_STATS_AGGR(pdev, vdev,
  3447. tx_i.mcast_en.dropped_map_error);
  3448. DP_STATS_AGGR(pdev, vdev,
  3449. tx_i.mcast_en.dropped_self_mac);
  3450. DP_STATS_AGGR(pdev, vdev,
  3451. tx_i.mcast_en.dropped_send_fail);
  3452. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3453. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3454. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3455. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3456. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3457. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3458. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3459. pdev->stats.tx_i.dropped.dma_error +
  3460. pdev->stats.tx_i.dropped.ring_full +
  3461. pdev->stats.tx_i.dropped.enqueue_fail +
  3462. pdev->stats.tx_i.dropped.desc_na +
  3463. pdev->stats.tx_i.dropped.res_full;
  3464. pdev->stats.tx.last_ack_rssi =
  3465. vdev->stats.tx.last_ack_rssi;
  3466. pdev->stats.tx_i.tso.num_seg =
  3467. vdev->stats.tx_i.tso.num_seg;
  3468. }
  3469. }
  3470. /**
  3471. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3472. * @pdev: DP_PDEV Handle
  3473. *
  3474. * Return:void
  3475. */
  3476. static inline void
  3477. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3478. {
  3479. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3480. DP_PRINT_STATS("Received From Stack:");
  3481. DP_PRINT_STATS(" Packets = %d",
  3482. pdev->stats.tx_i.rcvd.num);
  3483. DP_PRINT_STATS(" Bytes = %d",
  3484. pdev->stats.tx_i.rcvd.bytes);
  3485. DP_PRINT_STATS("Processed:");
  3486. DP_PRINT_STATS(" Packets = %d",
  3487. pdev->stats.tx_i.processed.num);
  3488. DP_PRINT_STATS(" Bytes = %d",
  3489. pdev->stats.tx_i.processed.bytes);
  3490. DP_PRINT_STATS("Completions:");
  3491. DP_PRINT_STATS(" Packets = %d",
  3492. pdev->stats.tx.comp_pkt.num);
  3493. DP_PRINT_STATS(" Bytes = %d",
  3494. pdev->stats.tx.comp_pkt.bytes);
  3495. DP_PRINT_STATS("Dropped:");
  3496. DP_PRINT_STATS(" Total = %d",
  3497. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3498. DP_PRINT_STATS(" Dma_map_error = %d",
  3499. pdev->stats.tx_i.dropped.dma_error);
  3500. DP_PRINT_STATS(" Ring Full = %d",
  3501. pdev->stats.tx_i.dropped.ring_full);
  3502. DP_PRINT_STATS(" Descriptor Not available = %d",
  3503. pdev->stats.tx_i.dropped.desc_na);
  3504. DP_PRINT_STATS(" HW enqueue failed= %d",
  3505. pdev->stats.tx_i.dropped.enqueue_fail);
  3506. DP_PRINT_STATS(" Resources Full = %d",
  3507. pdev->stats.tx_i.dropped.res_full);
  3508. DP_PRINT_STATS(" FW removed = %d",
  3509. pdev->stats.tx.dropped.fw_rem);
  3510. DP_PRINT_STATS(" FW removed transmitted = %d",
  3511. pdev->stats.tx.dropped.fw_rem_tx);
  3512. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3513. pdev->stats.tx.dropped.fw_rem_notx);
  3514. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3515. pdev->stats.tx.dropped.age_out);
  3516. DP_PRINT_STATS("Scatter Gather:");
  3517. DP_PRINT_STATS(" Packets = %d",
  3518. pdev->stats.tx_i.sg.sg_pkt.num);
  3519. DP_PRINT_STATS(" Bytes = %d",
  3520. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3521. DP_PRINT_STATS(" Dropped By Host = %d",
  3522. pdev->stats.tx_i.sg.dropped_host);
  3523. DP_PRINT_STATS(" Dropped By Target = %d",
  3524. pdev->stats.tx_i.sg.dropped_target);
  3525. DP_PRINT_STATS("TSO:");
  3526. DP_PRINT_STATS(" Number of Segments = %d",
  3527. pdev->stats.tx_i.tso.num_seg);
  3528. DP_PRINT_STATS(" Packets = %d",
  3529. pdev->stats.tx_i.tso.tso_pkt.num);
  3530. DP_PRINT_STATS(" Bytes = %d",
  3531. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3532. DP_PRINT_STATS(" Dropped By Host = %d",
  3533. pdev->stats.tx_i.tso.dropped_host);
  3534. DP_PRINT_STATS("Mcast Enhancement:");
  3535. DP_PRINT_STATS(" Packets = %d",
  3536. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3537. DP_PRINT_STATS(" Bytes = %d",
  3538. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3539. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3540. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3541. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3542. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3543. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3544. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3545. DP_PRINT_STATS(" Unicast sent = %d",
  3546. pdev->stats.tx_i.mcast_en.ucast);
  3547. DP_PRINT_STATS("Raw:");
  3548. DP_PRINT_STATS(" Packets = %d",
  3549. pdev->stats.tx_i.raw.raw_pkt.num);
  3550. DP_PRINT_STATS(" Bytes = %d",
  3551. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3552. DP_PRINT_STATS(" DMA map error = %d",
  3553. pdev->stats.tx_i.raw.dma_map_error);
  3554. DP_PRINT_STATS("Reinjected:");
  3555. DP_PRINT_STATS(" Packets = %d",
  3556. pdev->stats.tx_i.reinject_pkts.num);
  3557. DP_PRINT_STATS("Bytes = %d\n",
  3558. pdev->stats.tx_i.reinject_pkts.bytes);
  3559. DP_PRINT_STATS("Inspected:");
  3560. DP_PRINT_STATS(" Packets = %d",
  3561. pdev->stats.tx_i.inspect_pkts.num);
  3562. DP_PRINT_STATS(" Bytes = %d",
  3563. pdev->stats.tx_i.inspect_pkts.bytes);
  3564. }
  3565. /**
  3566. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3567. * @pdev: DP_PDEV Handle
  3568. *
  3569. * Return: void
  3570. */
  3571. static inline void
  3572. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3573. {
  3574. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3575. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3576. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3577. pdev->stats.rx.rcvd_reo[0].num,
  3578. pdev->stats.rx.rcvd_reo[1].num,
  3579. pdev->stats.rx.rcvd_reo[2].num,
  3580. pdev->stats.rx.rcvd_reo[3].num);
  3581. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3582. pdev->stats.rx.rcvd_reo[0].bytes,
  3583. pdev->stats.rx.rcvd_reo[1].bytes,
  3584. pdev->stats.rx.rcvd_reo[2].bytes,
  3585. pdev->stats.rx.rcvd_reo[3].bytes);
  3586. DP_PRINT_STATS("Replenished:");
  3587. DP_PRINT_STATS(" Packets = %d",
  3588. pdev->stats.replenish.pkts.num);
  3589. DP_PRINT_STATS(" Bytes = %d",
  3590. pdev->stats.replenish.pkts.bytes);
  3591. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3592. pdev->stats.buf_freelist);
  3593. DP_PRINT_STATS("Dropped:");
  3594. DP_PRINT_STATS(" msdu_not_done = %d",
  3595. pdev->stats.dropped.msdu_not_done);
  3596. DP_PRINT_STATS("Sent To Stack:");
  3597. DP_PRINT_STATS(" Packets = %d",
  3598. pdev->stats.rx.to_stack.num);
  3599. DP_PRINT_STATS(" Bytes = %d",
  3600. pdev->stats.rx.to_stack.bytes);
  3601. DP_PRINT_STATS("Multicast/Broadcast:");
  3602. DP_PRINT_STATS(" Packets = %d",
  3603. pdev->stats.rx.multicast.num);
  3604. DP_PRINT_STATS(" Bytes = %d",
  3605. pdev->stats.rx.multicast.bytes);
  3606. DP_PRINT_STATS("Errors:");
  3607. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3608. pdev->stats.replenish.rxdma_err);
  3609. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3610. pdev->stats.err.desc_alloc_fail);
  3611. /* Get bar_recv_cnt */
  3612. dp_aggregate_pdev_ctrl_frames_stats(pdev);
  3613. DP_PRINT_STATS("BAR Received Count: = %d",
  3614. pdev->stats.rx.bar_recv_cnt);
  3615. }
  3616. /**
  3617. * dp_print_soc_tx_stats(): Print SOC level stats
  3618. * @soc DP_SOC Handle
  3619. *
  3620. * Return: void
  3621. */
  3622. static inline void
  3623. dp_print_soc_tx_stats(struct dp_soc *soc)
  3624. {
  3625. DP_PRINT_STATS("SOC Tx Stats:\n");
  3626. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3627. soc->stats.tx.desc_in_use);
  3628. DP_PRINT_STATS("Invalid peer:");
  3629. DP_PRINT_STATS(" Packets = %d",
  3630. soc->stats.tx.tx_invalid_peer.num);
  3631. DP_PRINT_STATS(" Bytes = %d",
  3632. soc->stats.tx.tx_invalid_peer.bytes);
  3633. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3634. soc->stats.tx.tcl_ring_full[0],
  3635. soc->stats.tx.tcl_ring_full[1],
  3636. soc->stats.tx.tcl_ring_full[2]);
  3637. }
  3638. /**
  3639. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3640. * @soc: DP_SOC Handle
  3641. *
  3642. * Return:void
  3643. */
  3644. static inline void
  3645. dp_print_soc_rx_stats(struct dp_soc *soc)
  3646. {
  3647. uint32_t i;
  3648. char reo_error[DP_REO_ERR_LENGTH];
  3649. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3650. uint8_t index = 0;
  3651. DP_PRINT_STATS("SOC Rx Stats:\n");
  3652. DP_PRINT_STATS("Errors:\n");
  3653. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3654. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3655. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3656. DP_PRINT_STATS("Invalid RBM = %d",
  3657. soc->stats.rx.err.invalid_rbm);
  3658. DP_PRINT_STATS("Invalid Vdev = %d",
  3659. soc->stats.rx.err.invalid_vdev);
  3660. DP_PRINT_STATS("Invalid Pdev = %d",
  3661. soc->stats.rx.err.invalid_pdev);
  3662. DP_PRINT_STATS("Invalid Peer = %d",
  3663. soc->stats.rx.err.rx_invalid_peer.num);
  3664. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3665. soc->stats.rx.err.hal_ring_access_fail);
  3666. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3667. index += qdf_snprint(&rxdma_error[index],
  3668. DP_RXDMA_ERR_LENGTH - index,
  3669. " %d", soc->stats.rx.err.rxdma_error[i]);
  3670. }
  3671. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3672. rxdma_error);
  3673. index = 0;
  3674. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3675. index += qdf_snprint(&reo_error[index],
  3676. DP_REO_ERR_LENGTH - index,
  3677. " %d", soc->stats.rx.err.reo_error[i]);
  3678. }
  3679. DP_PRINT_STATS("REO Error(0-14):%s",
  3680. reo_error);
  3681. }
  3682. /**
  3683. * dp_print_ring_stat_from_hal(): Print hal level ring stats
  3684. * @soc: DP_SOC handle
  3685. * @srng: DP_SRNG handle
  3686. * @ring_name: SRNG name
  3687. *
  3688. * Return: void
  3689. */
  3690. static inline void
  3691. dp_print_ring_stat_from_hal(struct dp_soc *soc, struct dp_srng *srng,
  3692. char *ring_name)
  3693. {
  3694. uint32_t tailp;
  3695. uint32_t headp;
  3696. if (srng->hal_srng != NULL) {
  3697. hal_api_get_tphp(soc->hal_soc, srng->hal_srng, &tailp, &headp);
  3698. DP_PRINT_STATS("%s : Head pointer = %d Tail Pointer = %d\n",
  3699. ring_name, headp, tailp);
  3700. }
  3701. }
  3702. /**
  3703. * dp_print_ring_stats(): Print tail and head pointer
  3704. * @pdev: DP_PDEV handle
  3705. *
  3706. * Return:void
  3707. */
  3708. static inline void
  3709. dp_print_ring_stats(struct dp_pdev *pdev)
  3710. {
  3711. uint32_t i;
  3712. char ring_name[STR_MAXLEN + 1];
  3713. dp_print_ring_stat_from_hal(pdev->soc,
  3714. &pdev->soc->reo_exception_ring,
  3715. "Reo Exception Ring");
  3716. dp_print_ring_stat_from_hal(pdev->soc,
  3717. &pdev->soc->reo_reinject_ring,
  3718. "Reo Inject Ring");
  3719. dp_print_ring_stat_from_hal(pdev->soc,
  3720. &pdev->soc->reo_cmd_ring,
  3721. "Reo Command Ring");
  3722. dp_print_ring_stat_from_hal(pdev->soc,
  3723. &pdev->soc->reo_status_ring,
  3724. "Reo Status Ring");
  3725. dp_print_ring_stat_from_hal(pdev->soc,
  3726. &pdev->soc->rx_rel_ring,
  3727. "Rx Release ring");
  3728. dp_print_ring_stat_from_hal(pdev->soc,
  3729. &pdev->soc->tcl_cmd_ring,
  3730. "Tcl command Ring");
  3731. dp_print_ring_stat_from_hal(pdev->soc,
  3732. &pdev->soc->tcl_status_ring,
  3733. "Tcl Status Ring");
  3734. dp_print_ring_stat_from_hal(pdev->soc,
  3735. &pdev->soc->wbm_desc_rel_ring,
  3736. "Wbm Desc Rel Ring");
  3737. for (i = 0; i < MAX_REO_DEST_RINGS; i++) {
  3738. snprintf(ring_name, STR_MAXLEN, "Reo Dest Ring %d", i);
  3739. dp_print_ring_stat_from_hal(pdev->soc,
  3740. &pdev->soc->reo_dest_ring[i],
  3741. ring_name);
  3742. }
  3743. for (i = 0; i < pdev->soc->num_tcl_data_rings; i++) {
  3744. snprintf(ring_name, STR_MAXLEN, "Tcl Data Ring %d", i);
  3745. dp_print_ring_stat_from_hal(pdev->soc,
  3746. &pdev->soc->tcl_data_ring[i],
  3747. ring_name);
  3748. }
  3749. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3750. snprintf(ring_name, STR_MAXLEN, "Tx Comp Ring %d", i);
  3751. dp_print_ring_stat_from_hal(pdev->soc,
  3752. &pdev->soc->tx_comp_ring[i],
  3753. ring_name);
  3754. }
  3755. dp_print_ring_stat_from_hal(pdev->soc,
  3756. &pdev->rx_refill_buf_ring,
  3757. "Rx Refill Buf Ring");
  3758. #ifdef IPA_OFFLOAD
  3759. dp_print_ring_stat_from_hal(pdev->soc,
  3760. &pdev->ipa_rx_refill_buf_ring,
  3761. "IPA Rx Refill Buf Ring");
  3762. #endif
  3763. dp_print_ring_stat_from_hal(pdev->soc,
  3764. &pdev->rxdma_mon_buf_ring,
  3765. "Rxdma Mon Buf Ring");
  3766. dp_print_ring_stat_from_hal(pdev->soc,
  3767. &pdev->rxdma_mon_dst_ring,
  3768. "Rxdma Mon Dst Ring");
  3769. dp_print_ring_stat_from_hal(pdev->soc,
  3770. &pdev->rxdma_mon_status_ring,
  3771. "Rxdma Mon Status Ring");
  3772. dp_print_ring_stat_from_hal(pdev->soc,
  3773. &pdev->rxdma_mon_desc_ring,
  3774. "Rxdma mon desc Ring");
  3775. dp_print_ring_stat_from_hal(pdev->soc,
  3776. &pdev->rxdma_err_dst_ring,
  3777. "Rxdma err dst ring");
  3778. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3779. snprintf(ring_name, STR_MAXLEN, "Rx mac buf ring %d", i);
  3780. dp_print_ring_stat_from_hal(pdev->soc,
  3781. &pdev->rx_mac_buf_ring[i],
  3782. ring_name);
  3783. }
  3784. }
  3785. /**
  3786. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3787. * @vdev: DP_VDEV handle
  3788. *
  3789. * Return:void
  3790. */
  3791. static inline void
  3792. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3793. {
  3794. struct dp_peer *peer = NULL;
  3795. DP_STATS_CLR(vdev->pdev);
  3796. DP_STATS_CLR(vdev->pdev->soc);
  3797. DP_STATS_CLR(vdev);
  3798. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3799. if (!peer)
  3800. return;
  3801. DP_STATS_CLR(peer);
  3802. }
  3803. }
  3804. /**
  3805. * dp_print_rx_rates(): Print Rx rate stats
  3806. * @vdev: DP_VDEV handle
  3807. *
  3808. * Return:void
  3809. */
  3810. static inline void
  3811. dp_print_rx_rates(struct dp_vdev *vdev)
  3812. {
  3813. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3814. uint8_t i, mcs, pkt_type;
  3815. uint8_t index = 0;
  3816. char nss[DP_NSS_LENGTH];
  3817. DP_PRINT_STATS("Rx Rate Info:\n");
  3818. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3819. index = 0;
  3820. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3821. if (!dp_rate_string[pkt_type][mcs].valid)
  3822. continue;
  3823. DP_PRINT_STATS(" %s = %d",
  3824. dp_rate_string[pkt_type][mcs].mcs_type,
  3825. pdev->stats.rx.pkt_type[pkt_type].
  3826. mcs_count[mcs]);
  3827. }
  3828. DP_PRINT_STATS("\n");
  3829. }
  3830. index = 0;
  3831. for (i = 0; i < SS_COUNT; i++) {
  3832. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3833. " %d", pdev->stats.rx.nss[i]);
  3834. }
  3835. DP_PRINT_STATS("NSS(0-7) = %s",
  3836. nss);
  3837. DP_PRINT_STATS("SGI ="
  3838. " 0.8us %d,"
  3839. " 0.4us %d,"
  3840. " 1.6us %d,"
  3841. " 3.2us %d,",
  3842. pdev->stats.rx.sgi_count[0],
  3843. pdev->stats.rx.sgi_count[1],
  3844. pdev->stats.rx.sgi_count[2],
  3845. pdev->stats.rx.sgi_count[3]);
  3846. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3847. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3848. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3849. DP_PRINT_STATS("Reception Type ="
  3850. " SU: %d,"
  3851. " MU_MIMO:%d,"
  3852. " MU_OFDMA:%d,"
  3853. " MU_OFDMA_MIMO:%d\n",
  3854. pdev->stats.rx.reception_type[0],
  3855. pdev->stats.rx.reception_type[1],
  3856. pdev->stats.rx.reception_type[2],
  3857. pdev->stats.rx.reception_type[3]);
  3858. DP_PRINT_STATS("Aggregation:\n");
  3859. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3860. pdev->stats.rx.ampdu_cnt);
  3861. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3862. pdev->stats.rx.non_ampdu_cnt);
  3863. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3864. pdev->stats.rx.amsdu_cnt);
  3865. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3866. pdev->stats.rx.non_amsdu_cnt);
  3867. }
  3868. /**
  3869. * dp_print_tx_rates(): Print tx rates
  3870. * @vdev: DP_VDEV handle
  3871. *
  3872. * Return:void
  3873. */
  3874. static inline void
  3875. dp_print_tx_rates(struct dp_vdev *vdev)
  3876. {
  3877. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3878. uint8_t mcs, pkt_type;
  3879. uint32_t index;
  3880. DP_PRINT_STATS("Tx Rate Info:\n");
  3881. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3882. index = 0;
  3883. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3884. if (!dp_rate_string[pkt_type][mcs].valid)
  3885. continue;
  3886. DP_PRINT_STATS(" %s = %d",
  3887. dp_rate_string[pkt_type][mcs].mcs_type,
  3888. pdev->stats.tx.pkt_type[pkt_type].
  3889. mcs_count[mcs]);
  3890. }
  3891. DP_PRINT_STATS("\n");
  3892. }
  3893. DP_PRINT_STATS("SGI ="
  3894. " 0.8us %d"
  3895. " 0.4us %d"
  3896. " 1.6us %d"
  3897. " 3.2us %d",
  3898. pdev->stats.tx.sgi_count[0],
  3899. pdev->stats.tx.sgi_count[1],
  3900. pdev->stats.tx.sgi_count[2],
  3901. pdev->stats.tx.sgi_count[3]);
  3902. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3903. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3904. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3905. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3906. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3907. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3908. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3909. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3910. DP_PRINT_STATS("Aggregation:\n");
  3911. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3912. pdev->stats.tx.amsdu_cnt);
  3913. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3914. pdev->stats.tx.non_amsdu_cnt);
  3915. }
  3916. /**
  3917. * dp_print_peer_stats():print peer stats
  3918. * @peer: DP_PEER handle
  3919. *
  3920. * return void
  3921. */
  3922. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3923. {
  3924. uint8_t i, mcs, pkt_type;
  3925. uint32_t index;
  3926. char nss[DP_NSS_LENGTH];
  3927. DP_PRINT_STATS("Node Tx Stats:\n");
  3928. DP_PRINT_STATS("Total Packet Completions = %d",
  3929. peer->stats.tx.comp_pkt.num);
  3930. DP_PRINT_STATS("Total Bytes Completions = %d",
  3931. peer->stats.tx.comp_pkt.bytes);
  3932. DP_PRINT_STATS("Success Packets = %d",
  3933. peer->stats.tx.tx_success.num);
  3934. DP_PRINT_STATS("Success Bytes = %d",
  3935. peer->stats.tx.tx_success.bytes);
  3936. DP_PRINT_STATS("Packets Failed = %d",
  3937. peer->stats.tx.tx_failed);
  3938. DP_PRINT_STATS("Packets In OFDMA = %d",
  3939. peer->stats.tx.ofdma);
  3940. DP_PRINT_STATS("Packets In STBC = %d",
  3941. peer->stats.tx.stbc);
  3942. DP_PRINT_STATS("Packets In LDPC = %d",
  3943. peer->stats.tx.ldpc);
  3944. DP_PRINT_STATS("Packet Retries = %d",
  3945. peer->stats.tx.retries);
  3946. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3947. peer->stats.tx.amsdu_cnt);
  3948. DP_PRINT_STATS("Last Packet RSSI = %d",
  3949. peer->stats.tx.last_ack_rssi);
  3950. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3951. peer->stats.tx.dropped.fw_rem);
  3952. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3953. peer->stats.tx.dropped.fw_rem_tx);
  3954. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3955. peer->stats.tx.dropped.fw_rem_notx);
  3956. DP_PRINT_STATS("Dropped : Age Out = %d",
  3957. peer->stats.tx.dropped.age_out);
  3958. DP_PRINT_STATS("Rate Info:");
  3959. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3960. index = 0;
  3961. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3962. if (!dp_rate_string[pkt_type][mcs].valid)
  3963. continue;
  3964. DP_PRINT_STATS(" %s = %d",
  3965. dp_rate_string[pkt_type][mcs].mcs_type,
  3966. peer->stats.tx.pkt_type[pkt_type].
  3967. mcs_count[mcs]);
  3968. }
  3969. DP_PRINT_STATS("\n");
  3970. }
  3971. DP_PRINT_STATS("SGI = "
  3972. " 0.8us %d"
  3973. " 0.4us %d"
  3974. " 1.6us %d"
  3975. " 3.2us %d",
  3976. peer->stats.tx.sgi_count[0],
  3977. peer->stats.tx.sgi_count[1],
  3978. peer->stats.tx.sgi_count[2],
  3979. peer->stats.tx.sgi_count[3]);
  3980. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3981. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3982. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3983. DP_PRINT_STATS("Aggregation:");
  3984. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3985. peer->stats.tx.amsdu_cnt);
  3986. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3987. peer->stats.tx.non_amsdu_cnt);
  3988. DP_PRINT_STATS("Node Rx Stats:");
  3989. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3990. peer->stats.rx.to_stack.num);
  3991. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3992. peer->stats.rx.to_stack.bytes);
  3993. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3994. DP_PRINT_STATS("Packets Received = %d",
  3995. peer->stats.rx.rcvd_reo[i].num);
  3996. DP_PRINT_STATS("Bytes Received = %d",
  3997. peer->stats.rx.rcvd_reo[i].bytes);
  3998. }
  3999. DP_PRINT_STATS("Multicast Packets Received = %d",
  4000. peer->stats.rx.multicast.num);
  4001. DP_PRINT_STATS("Multicast Bytes Received = %d",
  4002. peer->stats.rx.multicast.bytes);
  4003. DP_PRINT_STATS("WDS Packets Received = %d",
  4004. peer->stats.rx.wds.num);
  4005. DP_PRINT_STATS("WDS Bytes Received = %d",
  4006. peer->stats.rx.wds.bytes);
  4007. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  4008. peer->stats.rx.intra_bss.pkts.num);
  4009. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  4010. peer->stats.rx.intra_bss.pkts.bytes);
  4011. DP_PRINT_STATS("Raw Packets Received = %d",
  4012. peer->stats.rx.raw.num);
  4013. DP_PRINT_STATS("Raw Bytes Received = %d",
  4014. peer->stats.rx.raw.bytes);
  4015. DP_PRINT_STATS("Errors: MIC Errors = %d",
  4016. peer->stats.rx.err.mic_err);
  4017. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  4018. peer->stats.rx.err.decrypt_err);
  4019. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  4020. peer->stats.rx.non_ampdu_cnt);
  4021. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  4022. peer->stats.rx.ampdu_cnt);
  4023. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  4024. peer->stats.rx.non_amsdu_cnt);
  4025. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  4026. peer->stats.rx.amsdu_cnt);
  4027. DP_PRINT_STATS("SGI ="
  4028. " 0.8us %d"
  4029. " 0.4us %d"
  4030. " 1.6us %d"
  4031. " 3.2us %d",
  4032. peer->stats.rx.sgi_count[0],
  4033. peer->stats.rx.sgi_count[1],
  4034. peer->stats.rx.sgi_count[2],
  4035. peer->stats.rx.sgi_count[3]);
  4036. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  4037. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  4038. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  4039. DP_PRINT_STATS("Reception Type ="
  4040. " SU %d,"
  4041. " MU_MIMO %d,"
  4042. " MU_OFDMA %d,"
  4043. " MU_OFDMA_MIMO %d",
  4044. peer->stats.rx.reception_type[0],
  4045. peer->stats.rx.reception_type[1],
  4046. peer->stats.rx.reception_type[2],
  4047. peer->stats.rx.reception_type[3]);
  4048. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  4049. index = 0;
  4050. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  4051. if (!dp_rate_string[pkt_type][mcs].valid)
  4052. continue;
  4053. DP_PRINT_STATS(" %s = %d",
  4054. dp_rate_string[pkt_type][mcs].mcs_type,
  4055. peer->stats.rx.pkt_type[pkt_type].
  4056. mcs_count[mcs]);
  4057. }
  4058. DP_PRINT_STATS("\n");
  4059. }
  4060. index = 0;
  4061. for (i = 0; i < SS_COUNT; i++) {
  4062. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  4063. " %d", peer->stats.rx.nss[i]);
  4064. }
  4065. DP_PRINT_STATS("NSS(0-7) = %s",
  4066. nss);
  4067. DP_PRINT_STATS("Aggregation:");
  4068. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  4069. peer->stats.rx.ampdu_cnt);
  4070. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  4071. peer->stats.rx.non_ampdu_cnt);
  4072. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  4073. peer->stats.rx.amsdu_cnt);
  4074. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  4075. peer->stats.rx.non_amsdu_cnt);
  4076. }
  4077. /**
  4078. * dp_print_host_stats()- Function to print the stats aggregated at host
  4079. * @vdev_handle: DP_VDEV handle
  4080. * @type: host stats type
  4081. *
  4082. * Available Stat types
  4083. * TXRX_CLEAR_STATS : Clear the stats
  4084. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  4085. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  4086. * TXRX_TX_HOST_STATS: Print Tx Stats
  4087. * TXRX_RX_HOST_STATS: Print Rx Stats
  4088. * TXRX_AST_STATS: Print AST Stats
  4089. * TXRX_SRNG_PTR_STATS: Print SRNG ring pointer stats
  4090. *
  4091. * Return: 0 on success, print error message in case of failure
  4092. */
  4093. static int
  4094. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  4095. {
  4096. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4097. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  4098. dp_aggregate_pdev_stats(pdev);
  4099. switch (type) {
  4100. case TXRX_CLEAR_STATS:
  4101. dp_txrx_host_stats_clr(vdev);
  4102. break;
  4103. case TXRX_RX_RATE_STATS:
  4104. dp_print_rx_rates(vdev);
  4105. break;
  4106. case TXRX_TX_RATE_STATS:
  4107. dp_print_tx_rates(vdev);
  4108. break;
  4109. case TXRX_TX_HOST_STATS:
  4110. dp_print_pdev_tx_stats(pdev);
  4111. dp_print_soc_tx_stats(pdev->soc);
  4112. break;
  4113. case TXRX_RX_HOST_STATS:
  4114. dp_print_pdev_rx_stats(pdev);
  4115. dp_print_soc_rx_stats(pdev->soc);
  4116. break;
  4117. case TXRX_AST_STATS:
  4118. dp_print_ast_stats(pdev->soc);
  4119. break;
  4120. case TXRX_SRNG_PTR_STATS:
  4121. dp_print_ring_stats(pdev);
  4122. break;
  4123. default:
  4124. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  4125. break;
  4126. }
  4127. return 0;
  4128. }
  4129. /*
  4130. * dp_get_host_peer_stats()- function to print peer stats
  4131. * @pdev_handle: DP_PDEV handle
  4132. * @mac_addr: mac address of the peer
  4133. *
  4134. * Return: void
  4135. */
  4136. static void
  4137. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  4138. {
  4139. struct dp_peer *peer;
  4140. uint8_t local_id;
  4141. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  4142. &local_id);
  4143. if (!peer) {
  4144. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  4145. "%s: Invalid peer\n", __func__);
  4146. return;
  4147. }
  4148. dp_print_peer_stats(peer);
  4149. dp_peer_rxtid_stats(peer, dp_rx_tid_stats_cb, NULL);
  4150. return;
  4151. }
  4152. /*
  4153. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  4154. * @pdev: DP_PDEV handle
  4155. *
  4156. * Return: void
  4157. */
  4158. static void
  4159. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  4160. {
  4161. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4162. htt_tlv_filter.mpdu_start = 0;
  4163. htt_tlv_filter.msdu_start = 0;
  4164. htt_tlv_filter.packet = 0;
  4165. htt_tlv_filter.msdu_end = 0;
  4166. htt_tlv_filter.mpdu_end = 0;
  4167. htt_tlv_filter.packet_header = 1;
  4168. htt_tlv_filter.attention = 1;
  4169. htt_tlv_filter.ppdu_start = 1;
  4170. htt_tlv_filter.ppdu_end = 1;
  4171. htt_tlv_filter.ppdu_end_user_stats = 1;
  4172. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4173. htt_tlv_filter.ppdu_end_status_done = 1;
  4174. htt_tlv_filter.enable_fp = 1;
  4175. htt_tlv_filter.enable_md = 0;
  4176. htt_tlv_filter.enable_mo = 0;
  4177. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  4178. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  4179. RX_BUFFER_SIZE, &htt_tlv_filter);
  4180. }
  4181. /*
  4182. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  4183. * @pdev_handle: DP_PDEV handle
  4184. *
  4185. * Return: void
  4186. */
  4187. static void
  4188. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4189. {
  4190. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4191. pdev->enhanced_stats_en = 1;
  4192. dp_ppdu_ring_cfg(pdev);
  4193. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4194. }
  4195. /*
  4196. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  4197. * @pdev_handle: DP_PDEV handle
  4198. *
  4199. * Return: void
  4200. */
  4201. static void
  4202. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4203. {
  4204. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4205. pdev->enhanced_stats_en = 0;
  4206. }
  4207. /*
  4208. * dp_get_fw_peer_stats()- function to print peer stats
  4209. * @pdev_handle: DP_PDEV handle
  4210. * @mac_addr: mac address of the peer
  4211. * @cap: Type of htt stats requested
  4212. *
  4213. * Currently Supporting only MAC ID based requests Only
  4214. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  4215. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  4216. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  4217. *
  4218. * Return: void
  4219. */
  4220. static void
  4221. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  4222. uint32_t cap)
  4223. {
  4224. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4225. uint32_t config_param0 = 0;
  4226. uint32_t config_param1 = 0;
  4227. uint32_t config_param2 = 0;
  4228. uint32_t config_param3 = 0;
  4229. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  4230. config_param0 |= (1 << (cap + 1));
  4231. config_param1 = 0x8f;
  4232. config_param2 |= (mac_addr[0] & 0x000000ff);
  4233. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  4234. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  4235. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  4236. config_param3 |= (mac_addr[4] & 0x000000ff);
  4237. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  4238. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  4239. config_param0, config_param1, config_param2,
  4240. config_param3);
  4241. }
  4242. /*
  4243. * dp_set_vdev_param: function to set parameters in vdev
  4244. * @param: parameter type to be set
  4245. * @val: value of parameter to be set
  4246. *
  4247. * return: void
  4248. */
  4249. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  4250. enum cdp_vdev_param_type param, uint32_t val)
  4251. {
  4252. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4253. switch (param) {
  4254. case CDP_ENABLE_WDS:
  4255. vdev->wds_enabled = val;
  4256. break;
  4257. case CDP_ENABLE_NAWDS:
  4258. vdev->nawds_enabled = val;
  4259. break;
  4260. case CDP_ENABLE_MCAST_EN:
  4261. vdev->mcast_enhancement_en = val;
  4262. break;
  4263. case CDP_ENABLE_PROXYSTA:
  4264. vdev->proxysta_vdev = val;
  4265. break;
  4266. case CDP_UPDATE_TDLS_FLAGS:
  4267. vdev->tdls_link_connected = val;
  4268. break;
  4269. case CDP_CFG_WDS_AGING_TIMER:
  4270. if (val == 0)
  4271. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4272. else if (val != vdev->wds_aging_timer_val)
  4273. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4274. vdev->wds_aging_timer_val = val;
  4275. break;
  4276. case CDP_ENABLE_AP_BRIDGE:
  4277. if (wlan_op_mode_sta != vdev->opmode)
  4278. vdev->ap_bridge_enabled = val;
  4279. else
  4280. vdev->ap_bridge_enabled = false;
  4281. break;
  4282. default:
  4283. break;
  4284. }
  4285. dp_tx_vdev_update_search_flags(vdev);
  4286. }
  4287. /**
  4288. * dp_peer_set_nawds: set nawds bit in peer
  4289. * @peer_handle: pointer to peer
  4290. * @value: enable/disable nawds
  4291. *
  4292. * return: void
  4293. */
  4294. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4295. {
  4296. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4297. peer->nawds_enabled = value;
  4298. }
  4299. /*
  4300. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4301. * @vdev_handle: DP_VDEV handle
  4302. * @map_id:ID of map that needs to be updated
  4303. *
  4304. * Return: void
  4305. */
  4306. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4307. uint8_t map_id)
  4308. {
  4309. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4310. vdev->dscp_tid_map_id = map_id;
  4311. return;
  4312. }
  4313. /**
  4314. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4315. * @pdev: DP_PDEV handle
  4316. * @map_id: ID of map that needs to be updated
  4317. * @tos: index value in map
  4318. * @tid: tid value passed by the user
  4319. *
  4320. * Return: void
  4321. */
  4322. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4323. uint8_t map_id, uint8_t tos, uint8_t tid)
  4324. {
  4325. uint8_t dscp;
  4326. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4327. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4328. pdev->dscp_tid_map[map_id][dscp] = tid;
  4329. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4330. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4331. map_id, dscp);
  4332. return;
  4333. }
  4334. /**
  4335. * dp_fw_stats_process(): Process TxRX FW stats request
  4336. * @vdev_handle: DP VDEV handle
  4337. * @val: value passed by user
  4338. *
  4339. * return: int
  4340. */
  4341. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4342. {
  4343. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4344. struct dp_pdev *pdev = NULL;
  4345. if (!vdev) {
  4346. DP_TRACE(NONE, "VDEV not found");
  4347. return 1;
  4348. }
  4349. pdev = vdev->pdev;
  4350. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4351. }
  4352. /*
  4353. * dp_txrx_stats() - function to map to firmware and host stats
  4354. * @vdev: virtual handle
  4355. * @stats: type of statistics requested
  4356. *
  4357. * Return: integer
  4358. */
  4359. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4360. {
  4361. int host_stats;
  4362. int fw_stats;
  4363. if (stats >= CDP_TXRX_MAX_STATS)
  4364. return 0;
  4365. /*
  4366. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4367. * has to be updated if new FW HTT stats added
  4368. */
  4369. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4370. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4371. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4372. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4373. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4374. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4375. stats, fw_stats, host_stats);
  4376. if (fw_stats != TXRX_FW_STATS_INVALID)
  4377. return dp_fw_stats_process(vdev, fw_stats);
  4378. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4379. (host_stats <= TXRX_HOST_STATS_MAX))
  4380. return dp_print_host_stats(vdev, host_stats);
  4381. else
  4382. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4383. "Wrong Input for TxRx Stats");
  4384. return 0;
  4385. }
  4386. /*
  4387. * dp_print_napi_stats(): NAPI stats
  4388. * @soc - soc handle
  4389. */
  4390. static void dp_print_napi_stats(struct dp_soc *soc)
  4391. {
  4392. hif_print_napi_stats(soc->hif_handle);
  4393. }
  4394. /*
  4395. * dp_print_per_ring_stats(): Packet count per ring
  4396. * @soc - soc handle
  4397. */
  4398. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4399. {
  4400. uint8_t core, ring;
  4401. uint64_t total_packets;
  4402. DP_TRACE(FATAL, "Reo packets per ring:");
  4403. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4404. total_packets = 0;
  4405. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4406. for (core = 0; core < NR_CPUS; core++) {
  4407. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4408. core, soc->stats.rx.ring_packets[core][ring]);
  4409. total_packets += soc->stats.rx.ring_packets[core][ring];
  4410. }
  4411. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4412. ring, total_packets);
  4413. }
  4414. }
  4415. /*
  4416. * dp_txrx_path_stats() - Function to display dump stats
  4417. * @soc - soc handle
  4418. *
  4419. * return: none
  4420. */
  4421. static void dp_txrx_path_stats(struct dp_soc *soc)
  4422. {
  4423. uint8_t error_code;
  4424. uint8_t loop_pdev;
  4425. struct dp_pdev *pdev;
  4426. uint8_t i;
  4427. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4428. pdev = soc->pdev_list[loop_pdev];
  4429. dp_aggregate_pdev_stats(pdev);
  4430. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4431. "Tx path Statistics:");
  4432. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4433. pdev->stats.tx_i.rcvd.num,
  4434. pdev->stats.tx_i.rcvd.bytes);
  4435. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4436. pdev->stats.tx_i.processed.num,
  4437. pdev->stats.tx_i.processed.bytes);
  4438. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4439. pdev->stats.tx.tx_success.num,
  4440. pdev->stats.tx.tx_success.bytes);
  4441. DP_TRACE(FATAL, "Dropped in host:");
  4442. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4443. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4444. DP_TRACE(FATAL, "Descriptor not available: %u",
  4445. pdev->stats.tx_i.dropped.desc_na);
  4446. DP_TRACE(FATAL, "Ring full: %u",
  4447. pdev->stats.tx_i.dropped.ring_full);
  4448. DP_TRACE(FATAL, "Enqueue fail: %u",
  4449. pdev->stats.tx_i.dropped.enqueue_fail);
  4450. DP_TRACE(FATAL, "DMA Error: %u",
  4451. pdev->stats.tx_i.dropped.dma_error);
  4452. DP_TRACE(FATAL, "Dropped in hardware:");
  4453. DP_TRACE(FATAL, "total packets dropped: %u",
  4454. pdev->stats.tx.tx_failed);
  4455. DP_TRACE(FATAL, "mpdu age out: %u",
  4456. pdev->stats.tx.dropped.age_out);
  4457. DP_TRACE(FATAL, "firmware removed: %u",
  4458. pdev->stats.tx.dropped.fw_rem);
  4459. DP_TRACE(FATAL, "firmware removed tx: %u",
  4460. pdev->stats.tx.dropped.fw_rem_tx);
  4461. DP_TRACE(FATAL, "firmware removed notx %u",
  4462. pdev->stats.tx.dropped.fw_rem_notx);
  4463. DP_TRACE(FATAL, "peer_invalid: %u",
  4464. pdev->soc->stats.tx.tx_invalid_peer.num);
  4465. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4466. DP_TRACE(FATAL, "Single Packet: %u",
  4467. pdev->stats.tx_comp_histogram.pkts_1);
  4468. DP_TRACE(FATAL, "2-20 Packets: %u",
  4469. pdev->stats.tx_comp_histogram.pkts_2_20);
  4470. DP_TRACE(FATAL, "21-40 Packets: %u",
  4471. pdev->stats.tx_comp_histogram.pkts_21_40);
  4472. DP_TRACE(FATAL, "41-60 Packets: %u",
  4473. pdev->stats.tx_comp_histogram.pkts_41_60);
  4474. DP_TRACE(FATAL, "61-80 Packets: %u",
  4475. pdev->stats.tx_comp_histogram.pkts_61_80);
  4476. DP_TRACE(FATAL, "81-100 Packets: %u",
  4477. pdev->stats.tx_comp_histogram.pkts_81_100);
  4478. DP_TRACE(FATAL, "101-200 Packets: %u",
  4479. pdev->stats.tx_comp_histogram.pkts_101_200);
  4480. DP_TRACE(FATAL, " 201+ Packets: %u",
  4481. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4482. DP_TRACE(FATAL, "Rx path statistics");
  4483. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4484. pdev->stats.rx.to_stack.num,
  4485. pdev->stats.rx.to_stack.bytes);
  4486. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4487. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4488. i, pdev->stats.rx.rcvd_reo[i].num,
  4489. pdev->stats.rx.rcvd_reo[i].bytes);
  4490. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4491. pdev->stats.rx.intra_bss.pkts.num,
  4492. pdev->stats.rx.intra_bss.pkts.bytes);
  4493. DP_TRACE(FATAL, "intra-bss fails %u msdus ( %u bytes),",
  4494. pdev->stats.rx.intra_bss.fail.num,
  4495. pdev->stats.rx.intra_bss.fail.bytes);
  4496. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4497. pdev->stats.rx.raw.num,
  4498. pdev->stats.rx.raw.bytes);
  4499. DP_TRACE(FATAL, "dropped: error %u msdus",
  4500. pdev->stats.rx.err.mic_err);
  4501. DP_TRACE(FATAL, "peer invalid %u",
  4502. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4503. DP_TRACE(FATAL, "Reo Statistics");
  4504. DP_TRACE(FATAL, "rbm error: %u msdus",
  4505. pdev->soc->stats.rx.err.invalid_rbm);
  4506. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4507. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4508. DP_TRACE(FATAL, "Reo errors");
  4509. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4510. error_code++) {
  4511. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4512. error_code,
  4513. pdev->soc->stats.rx.err.reo_error[error_code]);
  4514. }
  4515. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4516. error_code++) {
  4517. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4518. error_code,
  4519. pdev->soc->stats.rx.err
  4520. .rxdma_error[error_code]);
  4521. }
  4522. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4523. DP_TRACE(FATAL, "Single Packet: %u",
  4524. pdev->stats.rx_ind_histogram.pkts_1);
  4525. DP_TRACE(FATAL, "2-20 Packets: %u",
  4526. pdev->stats.rx_ind_histogram.pkts_2_20);
  4527. DP_TRACE(FATAL, "21-40 Packets: %u",
  4528. pdev->stats.rx_ind_histogram.pkts_21_40);
  4529. DP_TRACE(FATAL, "41-60 Packets: %u",
  4530. pdev->stats.rx_ind_histogram.pkts_41_60);
  4531. DP_TRACE(FATAL, "61-80 Packets: %u",
  4532. pdev->stats.rx_ind_histogram.pkts_61_80);
  4533. DP_TRACE(FATAL, "81-100 Packets: %u",
  4534. pdev->stats.rx_ind_histogram.pkts_81_100);
  4535. DP_TRACE(FATAL, "101-200 Packets: %u",
  4536. pdev->stats.rx_ind_histogram.pkts_101_200);
  4537. DP_TRACE(FATAL, " 201+ Packets: %u",
  4538. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4539. }
  4540. }
  4541. /*
  4542. * dp_txrx_dump_stats() - Dump statistics
  4543. * @value - Statistics option
  4544. */
  4545. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4546. {
  4547. struct dp_soc *soc =
  4548. (struct dp_soc *)psoc;
  4549. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4550. if (!soc) {
  4551. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4552. "%s: soc is NULL", __func__);
  4553. return QDF_STATUS_E_INVAL;
  4554. }
  4555. switch (value) {
  4556. case CDP_TXRX_PATH_STATS:
  4557. dp_txrx_path_stats(soc);
  4558. break;
  4559. case CDP_RX_RING_STATS:
  4560. dp_print_per_ring_stats(soc);
  4561. break;
  4562. case CDP_TXRX_TSO_STATS:
  4563. /* TODO: NOT IMPLEMENTED */
  4564. break;
  4565. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4566. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4567. break;
  4568. case CDP_DP_NAPI_STATS:
  4569. dp_print_napi_stats(soc);
  4570. break;
  4571. case CDP_TXRX_DESC_STATS:
  4572. /* TODO: NOT IMPLEMENTED */
  4573. break;
  4574. default:
  4575. status = QDF_STATUS_E_INVAL;
  4576. break;
  4577. }
  4578. return status;
  4579. }
  4580. static struct cdp_wds_ops dp_ops_wds = {
  4581. .vdev_set_wds = dp_vdev_set_wds,
  4582. };
  4583. /*
  4584. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4585. * @soc - datapath soc handle
  4586. * @peer - datapath peer handle
  4587. *
  4588. * Delete the AST entries belonging to a peer
  4589. */
  4590. #ifdef FEATURE_WDS
  4591. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4592. struct dp_peer *peer)
  4593. {
  4594. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4595. qdf_spin_lock_bh(&soc->ast_lock);
  4596. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4597. if (ast_entry->next_hop) {
  4598. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4599. peer->vdev->pdev->osif_pdev,
  4600. ast_entry->mac_addr.raw);
  4601. }
  4602. dp_peer_del_ast(soc, ast_entry);
  4603. }
  4604. qdf_spin_unlock_bh(&soc->ast_lock);
  4605. }
  4606. #else
  4607. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4608. struct dp_peer *peer)
  4609. {
  4610. }
  4611. #endif
  4612. /*
  4613. * dp_txrx_data_tx_cb_set(): set the callback for non standard tx
  4614. * @vdev_handle - datapath vdev handle
  4615. * @callback - callback function
  4616. * @ctxt: callback context
  4617. *
  4618. */
  4619. static void
  4620. dp_txrx_data_tx_cb_set(struct cdp_vdev *vdev_handle,
  4621. ol_txrx_data_tx_cb callback, void *ctxt)
  4622. {
  4623. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4624. vdev->tx_non_std_data_callback.func = callback;
  4625. vdev->tx_non_std_data_callback.ctxt = ctxt;
  4626. }
  4627. #ifdef CONFIG_WIN
  4628. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4629. {
  4630. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4631. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4632. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4633. dp_peer_delete_ast_entries(soc, peer);
  4634. }
  4635. #endif
  4636. static struct cdp_cmn_ops dp_ops_cmn = {
  4637. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4638. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4639. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4640. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4641. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4642. .txrx_peer_create = dp_peer_create_wifi3,
  4643. .txrx_peer_setup = dp_peer_setup_wifi3,
  4644. #ifdef CONFIG_WIN
  4645. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4646. #else
  4647. .txrx_peer_teardown = NULL,
  4648. #endif
  4649. .txrx_peer_delete = dp_peer_delete_wifi3,
  4650. .txrx_vdev_register = dp_vdev_register_wifi3,
  4651. .txrx_soc_detach = dp_soc_detach_wifi3,
  4652. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4653. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4654. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4655. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4656. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4657. .delba_process = dp_delba_process_wifi3,
  4658. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4659. .flush_cache_rx_queue = NULL,
  4660. /* TODO: get API's for dscp-tid need to be added*/
  4661. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4662. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4663. .txrx_stats = dp_txrx_stats,
  4664. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4665. .display_stats = dp_txrx_dump_stats,
  4666. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4667. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4668. #ifdef DP_INTR_POLL_BASED
  4669. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4670. #else
  4671. .txrx_intr_attach = dp_soc_interrupt_attach,
  4672. #endif
  4673. .txrx_intr_detach = dp_soc_interrupt_detach,
  4674. .set_pn_check = dp_set_pn_check_wifi3,
  4675. /* TODO: Add other functions */
  4676. .txrx_data_tx_cb_set = dp_txrx_data_tx_cb_set
  4677. };
  4678. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4679. .txrx_peer_authorize = dp_peer_authorize,
  4680. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4681. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4682. #ifdef MESH_MODE_SUPPORT
  4683. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4684. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4685. #endif
  4686. .txrx_set_vdev_param = dp_set_vdev_param,
  4687. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4688. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4689. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4690. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4691. .txrx_update_filter_neighbour_peers =
  4692. dp_update_filter_neighbour_peers,
  4693. .txrx_get_sec_type = dp_get_sec_type,
  4694. /* TODO: Add other functions */
  4695. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4696. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4697. };
  4698. static struct cdp_me_ops dp_ops_me = {
  4699. #ifdef ATH_SUPPORT_IQUE
  4700. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4701. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4702. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4703. #endif
  4704. };
  4705. static struct cdp_mon_ops dp_ops_mon = {
  4706. .txrx_monitor_set_filter_ucast_data = NULL,
  4707. .txrx_monitor_set_filter_mcast_data = NULL,
  4708. .txrx_monitor_set_filter_non_data = NULL,
  4709. .txrx_monitor_get_filter_ucast_data = NULL,
  4710. .txrx_monitor_get_filter_mcast_data = NULL,
  4711. .txrx_monitor_get_filter_non_data = NULL,
  4712. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  4713. };
  4714. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4715. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4716. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4717. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4718. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4719. /* TODO */
  4720. };
  4721. static struct cdp_raw_ops dp_ops_raw = {
  4722. /* TODO */
  4723. };
  4724. #ifdef CONFIG_WIN
  4725. static struct cdp_pflow_ops dp_ops_pflow = {
  4726. /* TODO */
  4727. };
  4728. #endif /* CONFIG_WIN */
  4729. #ifdef FEATURE_RUNTIME_PM
  4730. /**
  4731. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  4732. * @opaque_pdev: DP pdev context
  4733. *
  4734. * DP is ready to runtime suspend if there are no pending TX packets.
  4735. *
  4736. * Return: QDF_STATUS
  4737. */
  4738. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  4739. {
  4740. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4741. struct dp_soc *soc = pdev->soc;
  4742. /* Call DP TX flow control API to check if there is any
  4743. pending packets */
  4744. if (soc->intr_mode == DP_INTR_POLL)
  4745. qdf_timer_stop(&soc->int_timer);
  4746. return QDF_STATUS_SUCCESS;
  4747. }
  4748. /**
  4749. * dp_runtime_resume() - ensure DP is ready to runtime resume
  4750. * @opaque_pdev: DP pdev context
  4751. *
  4752. * Resume DP for runtime PM.
  4753. *
  4754. * Return: QDF_STATUS
  4755. */
  4756. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  4757. {
  4758. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4759. struct dp_soc *soc = pdev->soc;
  4760. void *hal_srng;
  4761. int i;
  4762. if (soc->intr_mode == DP_INTR_POLL)
  4763. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4764. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  4765. hal_srng = soc->tcl_data_ring[i].hal_srng;
  4766. if (hal_srng) {
  4767. /* We actually only need to acquire the lock */
  4768. hal_srng_access_start(soc->hal_soc, hal_srng);
  4769. /* Update SRC ring head pointer for HW to send
  4770. all pending packets */
  4771. hal_srng_access_end(soc->hal_soc, hal_srng);
  4772. }
  4773. }
  4774. return QDF_STATUS_SUCCESS;
  4775. }
  4776. #endif /* FEATURE_RUNTIME_PM */
  4777. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4778. {
  4779. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4780. struct dp_soc *soc = pdev->soc;
  4781. if (soc->intr_mode == DP_INTR_POLL)
  4782. qdf_timer_stop(&soc->int_timer);
  4783. return QDF_STATUS_SUCCESS;
  4784. }
  4785. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4786. {
  4787. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4788. struct dp_soc *soc = pdev->soc;
  4789. if (soc->intr_mode == DP_INTR_POLL)
  4790. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4791. return QDF_STATUS_SUCCESS;
  4792. }
  4793. #ifndef CONFIG_WIN
  4794. static struct cdp_misc_ops dp_ops_misc = {
  4795. .tx_non_std = dp_tx_non_std,
  4796. .get_opmode = dp_get_opmode,
  4797. #ifdef FEATURE_RUNTIME_PM
  4798. .runtime_suspend = dp_runtime_suspend,
  4799. .runtime_resume = dp_runtime_resume,
  4800. #endif /* FEATURE_RUNTIME_PM */
  4801. };
  4802. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4803. /* WIFI 3.0 DP implement as required. */
  4804. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4805. .register_pause_cb = dp_txrx_register_pause_cb,
  4806. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4807. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4808. };
  4809. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4810. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4811. };
  4812. #ifdef IPA_OFFLOAD
  4813. static struct cdp_ipa_ops dp_ops_ipa = {
  4814. .ipa_get_resource = dp_ipa_get_resource,
  4815. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4816. .ipa_op_response = dp_ipa_op_response,
  4817. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4818. .ipa_get_stat = dp_ipa_get_stat,
  4819. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4820. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4821. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4822. .ipa_setup = dp_ipa_setup,
  4823. .ipa_cleanup = dp_ipa_cleanup,
  4824. .ipa_setup_iface = dp_ipa_setup_iface,
  4825. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4826. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4827. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4828. .ipa_set_perf_level = dp_ipa_set_perf_level
  4829. };
  4830. #endif
  4831. static struct cdp_bus_ops dp_ops_bus = {
  4832. .bus_suspend = dp_bus_suspend,
  4833. .bus_resume = dp_bus_resume
  4834. };
  4835. static struct cdp_ocb_ops dp_ops_ocb = {
  4836. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4837. };
  4838. static struct cdp_throttle_ops dp_ops_throttle = {
  4839. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4840. };
  4841. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4842. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4843. };
  4844. static struct cdp_cfg_ops dp_ops_cfg = {
  4845. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4846. };
  4847. static struct cdp_peer_ops dp_ops_peer = {
  4848. .register_peer = dp_register_peer,
  4849. .clear_peer = dp_clear_peer,
  4850. .find_peer_by_addr = dp_find_peer_by_addr,
  4851. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4852. .local_peer_id = dp_local_peer_id,
  4853. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4854. .peer_state_update = dp_peer_state_update,
  4855. .get_vdevid = dp_get_vdevid,
  4856. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4857. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4858. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4859. .get_peer_state = dp_get_peer_state,
  4860. .last_assoc_received = dp_get_last_assoc_received,
  4861. .last_disassoc_received = dp_get_last_disassoc_received,
  4862. .last_deauth_received = dp_get_last_deauth_received,
  4863. };
  4864. #endif
  4865. static struct cdp_ops dp_txrx_ops = {
  4866. .cmn_drv_ops = &dp_ops_cmn,
  4867. .ctrl_ops = &dp_ops_ctrl,
  4868. .me_ops = &dp_ops_me,
  4869. .mon_ops = &dp_ops_mon,
  4870. .host_stats_ops = &dp_ops_host_stats,
  4871. .wds_ops = &dp_ops_wds,
  4872. .raw_ops = &dp_ops_raw,
  4873. #ifdef CONFIG_WIN
  4874. .pflow_ops = &dp_ops_pflow,
  4875. #endif /* CONFIG_WIN */
  4876. #ifndef CONFIG_WIN
  4877. .misc_ops = &dp_ops_misc,
  4878. .cfg_ops = &dp_ops_cfg,
  4879. .flowctl_ops = &dp_ops_flowctl,
  4880. .l_flowctl_ops = &dp_ops_l_flowctl,
  4881. #ifdef IPA_OFFLOAD
  4882. .ipa_ops = &dp_ops_ipa,
  4883. #endif
  4884. .bus_ops = &dp_ops_bus,
  4885. .ocb_ops = &dp_ops_ocb,
  4886. .peer_ops = &dp_ops_peer,
  4887. .throttle_ops = &dp_ops_throttle,
  4888. .mob_stats_ops = &dp_ops_mob_stats,
  4889. #endif
  4890. };
  4891. /*
  4892. * dp_soc_set_txrx_ring_map()
  4893. * @dp_soc: DP handler for soc
  4894. *
  4895. * Return: Void
  4896. */
  4897. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4898. {
  4899. uint32_t i;
  4900. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4901. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4902. }
  4903. }
  4904. /*
  4905. * dp_soc_attach_wifi3() - Attach txrx SOC
  4906. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4907. * @htc_handle: Opaque HTC handle
  4908. * @hif_handle: Opaque HIF handle
  4909. * @qdf_osdev: QDF device
  4910. *
  4911. * Return: DP SOC handle on success, NULL on failure
  4912. */
  4913. /*
  4914. * Local prototype added to temporarily address warning caused by
  4915. * -Wmissing-prototypes. A more correct solution, namely to expose
  4916. * a prototype in an appropriate header file, will come later.
  4917. */
  4918. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4919. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4920. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4921. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4922. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4923. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4924. {
  4925. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4926. if (!soc) {
  4927. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4928. FL("DP SOC memory allocation failed"));
  4929. goto fail0;
  4930. }
  4931. soc->cdp_soc.ops = &dp_txrx_ops;
  4932. soc->cdp_soc.ol_ops = ol_ops;
  4933. soc->osif_soc = osif_soc;
  4934. soc->osdev = qdf_osdev;
  4935. soc->hif_handle = hif_handle;
  4936. soc->psoc = psoc;
  4937. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4938. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4939. soc->hal_soc, qdf_osdev);
  4940. if (!soc->htt_handle) {
  4941. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4942. FL("HTT attach failed"));
  4943. goto fail1;
  4944. }
  4945. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4946. if (!soc->wlan_cfg_ctx) {
  4947. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4948. FL("wlan_cfg_soc_attach failed"));
  4949. goto fail2;
  4950. }
  4951. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  4952. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4953. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4954. CDP_CFG_MAX_PEER_ID);
  4955. if (ret != -EINVAL) {
  4956. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4957. }
  4958. }
  4959. qdf_spinlock_create(&soc->peer_ref_mutex);
  4960. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4961. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4962. /* fill the tx/rx cpu ring map*/
  4963. dp_soc_set_txrx_ring_map(soc);
  4964. qdf_spinlock_create(&soc->htt_stats.lock);
  4965. /* initialize work queue for stats processing */
  4966. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4967. return (void *)soc;
  4968. fail2:
  4969. htt_soc_detach(soc->htt_handle);
  4970. fail1:
  4971. qdf_mem_free(soc);
  4972. fail0:
  4973. return NULL;
  4974. }
  4975. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4976. /*
  4977. * dp_set_pktlog_wifi3() - attach txrx vdev
  4978. * @pdev: Datapath PDEV handle
  4979. * @event: which event's notifications are being subscribed to
  4980. * @enable: WDI event subscribe or not. (True or False)
  4981. *
  4982. * Return: Success, NULL on failure
  4983. */
  4984. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4985. bool enable)
  4986. {
  4987. struct dp_soc *soc = pdev->soc;
  4988. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4989. if (enable) {
  4990. switch (event) {
  4991. case WDI_EVENT_RX_DESC:
  4992. if (pdev->monitor_vdev) {
  4993. /* Nothing needs to be done if monitor mode is
  4994. * enabled
  4995. */
  4996. return 0;
  4997. }
  4998. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4999. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  5000. htt_tlv_filter.mpdu_start = 1;
  5001. htt_tlv_filter.msdu_start = 1;
  5002. htt_tlv_filter.msdu_end = 1;
  5003. htt_tlv_filter.mpdu_end = 1;
  5004. htt_tlv_filter.packet_header = 1;
  5005. htt_tlv_filter.attention = 1;
  5006. htt_tlv_filter.ppdu_start = 1;
  5007. htt_tlv_filter.ppdu_end = 1;
  5008. htt_tlv_filter.ppdu_end_user_stats = 1;
  5009. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  5010. htt_tlv_filter.ppdu_end_status_done = 1;
  5011. htt_tlv_filter.enable_fp = 1;
  5012. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5013. pdev->pdev_id,
  5014. pdev->rxdma_mon_status_ring.hal_srng,
  5015. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  5016. &htt_tlv_filter);
  5017. }
  5018. break;
  5019. case WDI_EVENT_LITE_RX:
  5020. if (pdev->monitor_vdev) {
  5021. /* Nothing needs to be done if monitor mode is
  5022. * enabled
  5023. */
  5024. return 0;
  5025. }
  5026. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  5027. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  5028. htt_tlv_filter.ppdu_start = 1;
  5029. htt_tlv_filter.ppdu_end = 1;
  5030. htt_tlv_filter.ppdu_end_user_stats = 1;
  5031. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  5032. htt_tlv_filter.ppdu_end_status_done = 1;
  5033. htt_tlv_filter.enable_fp = 1;
  5034. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5035. pdev->pdev_id,
  5036. pdev->rxdma_mon_status_ring.hal_srng,
  5037. RXDMA_MONITOR_STATUS,
  5038. RX_BUFFER_SIZE_PKTLOG_LITE,
  5039. &htt_tlv_filter);
  5040. }
  5041. break;
  5042. case WDI_EVENT_LITE_T2H:
  5043. if (pdev->monitor_vdev) {
  5044. /* Nothing needs to be done if monitor mode is
  5045. * enabled
  5046. */
  5047. return 0;
  5048. }
  5049. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  5050. * passing value 0xffff. Once these macros will define in htt
  5051. * header file will use proper macros
  5052. */
  5053. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  5054. break;
  5055. default:
  5056. /* Nothing needs to be done for other pktlog types */
  5057. break;
  5058. }
  5059. } else {
  5060. switch (event) {
  5061. case WDI_EVENT_RX_DESC:
  5062. case WDI_EVENT_LITE_RX:
  5063. if (pdev->monitor_vdev) {
  5064. /* Nothing needs to be done if monitor mode is
  5065. * enabled
  5066. */
  5067. return 0;
  5068. }
  5069. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  5070. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  5071. /* htt_tlv_filter is initialized to 0 */
  5072. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5073. pdev->pdev_id,
  5074. pdev->rxdma_mon_status_ring.hal_srng,
  5075. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  5076. &htt_tlv_filter);
  5077. }
  5078. break;
  5079. case WDI_EVENT_LITE_T2H:
  5080. if (pdev->monitor_vdev) {
  5081. /* Nothing needs to be done if monitor mode is
  5082. * enabled
  5083. */
  5084. return 0;
  5085. }
  5086. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  5087. * passing value 0. Once these macros will define in htt
  5088. * header file will use proper macros
  5089. */
  5090. dp_h2t_cfg_stats_msg_send(pdev, 0);
  5091. break;
  5092. default:
  5093. /* Nothing needs to be done for other pktlog types */
  5094. break;
  5095. }
  5096. }
  5097. return 0;
  5098. }
  5099. #endif