dp_be_rx.c 36 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_types.h"
  22. #include "dp_rx.h"
  23. #include "dp_be_rx.h"
  24. #include "dp_peer.h"
  25. #include "hal_rx.h"
  26. #include "hal_be_rx.h"
  27. #include "hal_api.h"
  28. #include "hal_be_api.h"
  29. #include "qdf_nbuf.h"
  30. #ifdef MESH_MODE_SUPPORT
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "dp_internal.h"
  34. #include "dp_ipa.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #include "dp_hist.h"
  39. #include "dp_rx_buffer_pool.h"
  40. #ifndef AST_OFFLOAD_ENABLE
  41. static void
  42. dp_rx_wds_learn(struct dp_soc *soc,
  43. struct dp_vdev *vdev,
  44. uint8_t *rx_tlv_hdr,
  45. struct dp_peer *peer,
  46. qdf_nbuf_t nbuf,
  47. struct hal_rx_msdu_metadata msdu_metadata)
  48. {
  49. /* WDS Source Port Learning */
  50. if (qdf_likely(vdev->wds_enabled))
  51. dp_rx_wds_srcport_learn(soc,
  52. rx_tlv_hdr,
  53. peer,
  54. nbuf,
  55. msdu_metadata);
  56. }
  57. #else
  58. #ifdef QCA_SUPPORT_WDS_EXTENDED
  59. /**
  60. * dp_wds_ext_peer_learn_be() - function to send event to control
  61. * path on receiving 1st 4-address frame from backhaul.
  62. * @soc: DP soc
  63. * @ta_peer: WDS repeater peer
  64. * @rx_tlv_hdr : start address of rx tlvs
  65. *
  66. * Return: void
  67. */
  68. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  69. struct dp_peer *ta_peer,
  70. uint8_t *rx_tlv_hdr)
  71. {
  72. uint8_t wds_ext_src_mac[QDF_MAC_ADDR_SIZE];
  73. /* instead of checking addr4 is valid or not in per packet path
  74. * check for init bit, which will be set on reception of
  75. * first addr4 valid packet.
  76. */
  77. if (!ta_peer->vdev->wds_ext_enabled ||
  78. qdf_atomic_test_bit(WDS_EXT_PEER_INIT_BIT, &ta_peer->wds_ext.init))
  79. return;
  80. if (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc, rx_tlv_hdr)) {
  81. qdf_atomic_test_and_set_bit(WDS_EXT_PEER_INIT_BIT,
  82. &ta_peer->wds_ext.init);
  83. qdf_mem_copy(wds_ext_src_mac, &ta_peer->mac_addr.raw[0],
  84. QDF_MAC_ADDR_SIZE);
  85. soc->cdp_soc.ol_ops->rx_wds_ext_peer_learn(
  86. soc->ctrl_psoc,
  87. ta_peer->peer_id,
  88. ta_peer->vdev->vdev_id,
  89. wds_ext_src_mac);
  90. }
  91. }
  92. #else
  93. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  94. struct dp_peer *ta_peer,
  95. uint8_t *rx_tlv_hdr)
  96. {
  97. }
  98. #endif
  99. static void
  100. dp_rx_wds_learn(struct dp_soc *soc,
  101. struct dp_vdev *vdev,
  102. uint8_t *rx_tlv_hdr,
  103. struct dp_peer *ta_peer,
  104. qdf_nbuf_t nbuf,
  105. struct hal_rx_msdu_metadata msdu_metadata)
  106. {
  107. dp_wds_ext_peer_learn_be(soc, ta_peer, rx_tlv_hdr);
  108. }
  109. #endif
  110. /**
  111. * dp_rx_process_be() - Brain of the Rx processing functionality
  112. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  113. * @int_ctx: per interrupt context
  114. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  115. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  116. * @quota: No. of units (packets) that can be serviced in one shot.
  117. *
  118. * This function implements the core of Rx functionality. This is
  119. * expected to handle only non-error frames.
  120. *
  121. * Return: uint32_t: No. of elements processed
  122. */
  123. uint32_t dp_rx_process_be(struct dp_intr *int_ctx,
  124. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  125. uint32_t quota)
  126. {
  127. hal_ring_desc_t ring_desc;
  128. hal_soc_handle_t hal_soc;
  129. struct dp_rx_desc *rx_desc = NULL;
  130. qdf_nbuf_t nbuf, next;
  131. bool near_full;
  132. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT];
  133. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT];
  134. uint32_t num_pending;
  135. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  136. uint16_t msdu_len = 0;
  137. uint16_t peer_id;
  138. uint8_t vdev_id;
  139. struct dp_peer *peer;
  140. struct dp_vdev *vdev;
  141. uint32_t pkt_len = 0;
  142. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  143. struct hal_rx_msdu_desc_info msdu_desc_info;
  144. enum hal_reo_error_status error;
  145. uint32_t peer_mdata;
  146. uint8_t *rx_tlv_hdr;
  147. uint32_t rx_bufs_reaped[MAX_PDEV_CNT];
  148. uint8_t mac_id = 0;
  149. struct dp_pdev *rx_pdev;
  150. struct dp_srng *dp_rxdma_srng;
  151. struct rx_desc_pool *rx_desc_pool;
  152. struct dp_soc *soc = int_ctx->soc;
  153. uint8_t core_id = 0;
  154. struct cdp_tid_rx_stats *tid_stats;
  155. qdf_nbuf_t nbuf_head;
  156. qdf_nbuf_t nbuf_tail;
  157. qdf_nbuf_t deliver_list_head;
  158. qdf_nbuf_t deliver_list_tail;
  159. uint32_t num_rx_bufs_reaped = 0;
  160. uint32_t intr_id;
  161. struct hif_opaque_softc *scn;
  162. int32_t tid = 0;
  163. bool is_prev_msdu_last = true;
  164. uint32_t num_entries_avail = 0;
  165. uint32_t rx_ol_pkt_cnt = 0;
  166. uint32_t num_entries = 0;
  167. struct hal_rx_msdu_metadata msdu_metadata;
  168. QDF_STATUS status;
  169. qdf_nbuf_t ebuf_head;
  170. qdf_nbuf_t ebuf_tail;
  171. uint8_t pkt_capture_offload = 0;
  172. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  173. int max_reap_limit, ring_near_full;
  174. DP_HIST_INIT();
  175. qdf_assert_always(soc && hal_ring_hdl);
  176. hal_soc = soc->hal_soc;
  177. qdf_assert_always(hal_soc);
  178. scn = soc->hif_handle;
  179. hif_pm_runtime_mark_dp_rx_busy(scn);
  180. intr_id = int_ctx->dp_intr_id;
  181. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  182. more_data:
  183. /* reset local variables here to be re-used in the function */
  184. nbuf_head = NULL;
  185. nbuf_tail = NULL;
  186. deliver_list_head = NULL;
  187. deliver_list_tail = NULL;
  188. peer = NULL;
  189. vdev = NULL;
  190. num_rx_bufs_reaped = 0;
  191. ebuf_head = NULL;
  192. ebuf_tail = NULL;
  193. ring_near_full = 0;
  194. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  195. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  196. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  197. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  198. qdf_mem_zero(head, sizeof(head));
  199. qdf_mem_zero(tail, sizeof(tail));
  200. ring_near_full = _dp_srng_test_and_update_nf_params(soc, rx_ring,
  201. &max_reap_limit);
  202. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  203. /*
  204. * Need API to convert from hal_ring pointer to
  205. * Ring Type / Ring Id combo
  206. */
  207. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  208. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  209. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  210. goto done;
  211. }
  212. /*
  213. * start reaping the buffers from reo ring and queue
  214. * them in per vdev queue.
  215. * Process the received pkts in a different per vdev loop.
  216. */
  217. while (qdf_likely(quota &&
  218. (ring_desc = hal_srng_dst_peek(hal_soc,
  219. hal_ring_hdl)))) {
  220. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  221. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  222. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  223. soc, hal_ring_hdl, error);
  224. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  225. 1);
  226. /* Don't know how to deal with this -- assert */
  227. qdf_assert(0);
  228. }
  229. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  230. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  231. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  232. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  233. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  234. break;
  235. }
  236. rx_desc = (struct dp_rx_desc *)
  237. hal_rx_get_reo_desc_va(ring_desc);
  238. dp_rx_desc_sw_cc_check(soc, rx_buf_cookie, &rx_desc);
  239. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  240. ring_desc, rx_desc);
  241. if (QDF_IS_STATUS_ERROR(status)) {
  242. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  243. qdf_assert_always(!rx_desc->unmapped);
  244. dp_ipa_reo_ctx_buf_mapping_lock(
  245. soc,
  246. reo_ring_num);
  247. dp_ipa_handle_rx_buf_smmu_mapping(
  248. soc,
  249. rx_desc->nbuf,
  250. RX_DATA_BUFFER_SIZE,
  251. false);
  252. qdf_nbuf_unmap_nbytes_single(
  253. soc->osdev,
  254. rx_desc->nbuf,
  255. QDF_DMA_FROM_DEVICE,
  256. RX_DATA_BUFFER_SIZE);
  257. rx_desc->unmapped = 1;
  258. dp_ipa_reo_ctx_buf_mapping_unlock(
  259. soc,
  260. reo_ring_num);
  261. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  262. rx_desc->pool_id);
  263. dp_rx_add_to_free_desc_list(
  264. &head[rx_desc->pool_id],
  265. &tail[rx_desc->pool_id],
  266. rx_desc);
  267. }
  268. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  269. continue;
  270. }
  271. /*
  272. * this is a unlikely scenario where the host is reaping
  273. * a descriptor which it already reaped just a while ago
  274. * but is yet to replenish it back to HW.
  275. * In this case host will dump the last 128 descriptors
  276. * including the software descriptor rx_desc and assert.
  277. */
  278. if (qdf_unlikely(!rx_desc->in_use)) {
  279. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  280. dp_info_rl("Reaping rx_desc not in use!");
  281. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  282. ring_desc, rx_desc);
  283. /* ignore duplicate RX desc and continue to process */
  284. /* Pop out the descriptor */
  285. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  286. continue;
  287. }
  288. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  289. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  290. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  291. dp_info_rl("Nbuf sanity check failure!");
  292. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  293. ring_desc, rx_desc);
  294. rx_desc->in_err_state = 1;
  295. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  296. continue;
  297. }
  298. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  299. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  300. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  301. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  302. ring_desc, rx_desc);
  303. }
  304. /* Get MPDU DESC info */
  305. hal_rx_mpdu_desc_info_get_be(ring_desc, &mpdu_desc_info);
  306. /* Get MSDU DESC info */
  307. hal_rx_msdu_desc_info_get_be(ring_desc, &msdu_desc_info);
  308. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  309. HAL_MSDU_F_MSDU_CONTINUATION)) {
  310. /* previous msdu has end bit set, so current one is
  311. * the new MPDU
  312. */
  313. if (is_prev_msdu_last) {
  314. /* Get number of entries available in HW ring */
  315. num_entries_avail =
  316. hal_srng_dst_num_valid(hal_soc,
  317. hal_ring_hdl, 1);
  318. /* For new MPDU check if we can read complete
  319. * MPDU by comparing the number of buffers
  320. * available and number of buffers needed to
  321. * reap this MPDU
  322. */
  323. if ((msdu_desc_info.msdu_len /
  324. (RX_DATA_BUFFER_SIZE -
  325. soc->rx_pkt_tlv_size) + 1) >
  326. num_entries_avail) {
  327. DP_STATS_INC(soc,
  328. rx.msdu_scatter_wait_break,
  329. 1);
  330. dp_rx_cookie_reset_invalid_bit(
  331. ring_desc);
  332. break;
  333. }
  334. is_prev_msdu_last = false;
  335. }
  336. }
  337. core_id = smp_processor_id();
  338. DP_STATS_INC(soc, rx.ring_packets[core_id][reo_ring_num], 1);
  339. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  340. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  341. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  342. HAL_MPDU_F_RAW_AMPDU))
  343. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  344. if (!is_prev_msdu_last &&
  345. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  346. is_prev_msdu_last = true;
  347. /* Pop out the descriptor*/
  348. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  349. rx_bufs_reaped[rx_desc->pool_id]++;
  350. peer_mdata = mpdu_desc_info.peer_meta_data;
  351. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  352. dp_rx_peer_metadata_peer_id_get_be(soc, peer_mdata);
  353. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  354. dp_rx_peer_metadata_vdev_id_get_be(soc, peer_mdata);
  355. /* to indicate whether this msdu is rx offload */
  356. pkt_capture_offload =
  357. DP_PEER_METADATA_OFFLOAD_GET_BE(peer_mdata);
  358. /*
  359. * save msdu flags first, last and continuation msdu in
  360. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  361. * length to nbuf->cb. This ensures the info required for
  362. * per pkt processing is always in the same cache line.
  363. * This helps in improving throughput for smaller pkt
  364. * sizes.
  365. */
  366. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  367. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  368. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  369. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  370. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  371. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  372. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  373. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  374. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  375. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  376. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  377. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  378. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_INTRA_BSS)
  379. qdf_nbuf_set_intra_bss(rx_desc->nbuf, 1);
  380. if (qdf_likely(mpdu_desc_info.mpdu_flags &
  381. HAL_MPDU_F_QOS_CONTROL_VALID))
  382. qdf_nbuf_set_tid_val(rx_desc->nbuf, mpdu_desc_info.tid);
  383. /* set sw exception */
  384. qdf_nbuf_set_rx_reo_dest_ind_or_sw_excpt(
  385. rx_desc->nbuf,
  386. hal_rx_sw_exception_get_be(ring_desc));
  387. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  388. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  389. /*
  390. * move unmap after scattered msdu waiting break logic
  391. * in case double skb unmap happened.
  392. */
  393. rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
  394. dp_ipa_reo_ctx_buf_mapping_lock(soc, reo_ring_num);
  395. dp_ipa_handle_rx_buf_smmu_mapping(soc, rx_desc->nbuf,
  396. rx_desc_pool->buf_size,
  397. false);
  398. qdf_nbuf_unmap_nbytes_single(soc->osdev, rx_desc->nbuf,
  399. QDF_DMA_FROM_DEVICE,
  400. rx_desc_pool->buf_size);
  401. rx_desc->unmapped = 1;
  402. dp_ipa_reo_ctx_buf_mapping_unlock(soc, reo_ring_num);
  403. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  404. ebuf_tail, rx_desc);
  405. /*
  406. * if continuation bit is set then we have MSDU spread
  407. * across multiple buffers, let us not decrement quota
  408. * till we reap all buffers of that MSDU.
  409. */
  410. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(rx_desc->nbuf)))
  411. quota -= 1;
  412. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  413. &tail[rx_desc->pool_id], rx_desc);
  414. num_rx_bufs_reaped++;
  415. /*
  416. * only if complete msdu is received for scatter case,
  417. * then allow break.
  418. */
  419. if (is_prev_msdu_last &&
  420. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  421. max_reap_limit))
  422. break;
  423. }
  424. done:
  425. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  426. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  427. /*
  428. * continue with next mac_id if no pkts were reaped
  429. * from that pool
  430. */
  431. if (!rx_bufs_reaped[mac_id])
  432. continue;
  433. dp_rxdma_srng = &soc->rx_refill_buf_ring[mac_id];
  434. rx_desc_pool = &soc->rx_desc_buf[mac_id];
  435. dp_rx_buffers_replenish(soc, mac_id, dp_rxdma_srng,
  436. rx_desc_pool, rx_bufs_reaped[mac_id],
  437. &head[mac_id], &tail[mac_id]);
  438. }
  439. dp_verbose_debug("replenished %u\n", rx_bufs_reaped[0]);
  440. /* Peer can be NULL is case of LFR */
  441. if (qdf_likely(peer))
  442. vdev = NULL;
  443. /*
  444. * BIG loop where each nbuf is dequeued from global queue,
  445. * processed and queued back on a per vdev basis. These nbufs
  446. * are sent to stack as and when we run out of nbufs
  447. * or a new nbuf dequeued from global queue has a different
  448. * vdev when compared to previous nbuf.
  449. */
  450. nbuf = nbuf_head;
  451. while (nbuf) {
  452. next = nbuf->next;
  453. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  454. nbuf = next;
  455. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  456. continue;
  457. }
  458. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  459. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  460. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  461. if (dp_rx_is_list_ready(deliver_list_head, vdev, peer,
  462. peer_id, vdev_id)) {
  463. dp_rx_deliver_to_stack(soc, vdev, peer,
  464. deliver_list_head,
  465. deliver_list_tail);
  466. deliver_list_head = NULL;
  467. deliver_list_tail = NULL;
  468. }
  469. /* Get TID from struct cb->tid_val, save to tid */
  470. if (qdf_nbuf_is_rx_chfrag_start(nbuf))
  471. tid = qdf_nbuf_get_tid_val(nbuf);
  472. if (qdf_unlikely(!peer)) {
  473. peer = dp_peer_get_ref_by_id(soc, peer_id,
  474. DP_MOD_ID_RX);
  475. } else if (peer && peer->peer_id != peer_id) {
  476. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  477. peer = dp_peer_get_ref_by_id(soc, peer_id,
  478. DP_MOD_ID_RX);
  479. }
  480. if (peer) {
  481. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  482. qdf_dp_trace_set_track(nbuf, QDF_RX);
  483. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  484. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  485. QDF_NBUF_RX_PKT_DATA_TRACK;
  486. }
  487. rx_bufs_used++;
  488. if (qdf_likely(peer)) {
  489. vdev = peer->vdev;
  490. } else {
  491. nbuf->next = NULL;
  492. dp_rx_deliver_to_pkt_capture_no_peer(
  493. soc, nbuf, pkt_capture_offload);
  494. if (!pkt_capture_offload)
  495. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  496. nbuf = next;
  497. continue;
  498. }
  499. if (qdf_unlikely(!vdev)) {
  500. qdf_nbuf_free(nbuf);
  501. nbuf = next;
  502. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  503. continue;
  504. }
  505. /* when hlos tid override is enabled, save tid in
  506. * skb->priority
  507. */
  508. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  509. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  510. qdf_nbuf_set_priority(nbuf, tid);
  511. rx_pdev = vdev->pdev;
  512. DP_RX_TID_SAVE(nbuf, tid);
  513. if (qdf_unlikely(rx_pdev->delay_stats_flag) ||
  514. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  515. soc->wlan_cfg_ctx)))
  516. qdf_nbuf_set_timestamp(nbuf);
  517. tid_stats =
  518. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  519. /*
  520. * Check if DMA completed -- msdu_done is the last bit
  521. * to be written
  522. */
  523. if (qdf_unlikely(!qdf_nbuf_is_rx_chfrag_cont(nbuf) &&
  524. !hal_rx_attn_msdu_done_get(hal_soc,
  525. rx_tlv_hdr))) {
  526. dp_err("MSDU DONE failure");
  527. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  528. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  529. QDF_TRACE_LEVEL_INFO);
  530. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  531. qdf_nbuf_free(nbuf);
  532. qdf_assert(0);
  533. nbuf = next;
  534. continue;
  535. }
  536. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  537. /*
  538. * First IF condition:
  539. * 802.11 Fragmented pkts are reinjected to REO
  540. * HW block as SG pkts and for these pkts we only
  541. * need to pull the RX TLVS header length.
  542. * Second IF condition:
  543. * The below condition happens when an MSDU is spread
  544. * across multiple buffers. This can happen in two cases
  545. * 1. The nbuf size is smaller then the received msdu.
  546. * ex: we have set the nbuf size to 2048 during
  547. * nbuf_alloc. but we received an msdu which is
  548. * 2304 bytes in size then this msdu is spread
  549. * across 2 nbufs.
  550. *
  551. * 2. AMSDUs when RAW mode is enabled.
  552. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  553. * across 1st nbuf and 2nd nbuf and last MSDU is
  554. * spread across 2nd nbuf and 3rd nbuf.
  555. *
  556. * for these scenarios let us create a skb frag_list and
  557. * append these buffers till the last MSDU of the AMSDU
  558. * Third condition:
  559. * This is the most likely case, we receive 802.3 pkts
  560. * decapsulated by HW, here we need to set the pkt length.
  561. */
  562. hal_rx_msdu_metadata_get(hal_soc, rx_tlv_hdr, &msdu_metadata);
  563. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  564. bool is_mcbc, is_sa_vld, is_da_vld;
  565. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  566. rx_tlv_hdr);
  567. is_sa_vld =
  568. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  569. rx_tlv_hdr);
  570. is_da_vld =
  571. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  572. rx_tlv_hdr);
  573. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  574. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  575. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  576. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  577. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  578. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  579. nbuf = dp_rx_sg_create(soc, nbuf);
  580. next = nbuf->next;
  581. if (qdf_nbuf_is_raw_frame(nbuf)) {
  582. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  583. DP_STATS_INC_PKT(peer, rx.raw, 1, msdu_len);
  584. } else {
  585. qdf_nbuf_free(nbuf);
  586. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  587. dp_info_rl("scatter msdu len %d, dropped",
  588. msdu_len);
  589. nbuf = next;
  590. continue;
  591. }
  592. } else {
  593. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  594. pkt_len = msdu_len +
  595. msdu_metadata.l3_hdr_pad +
  596. soc->rx_pkt_tlv_size;
  597. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  598. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  599. }
  600. /*
  601. * process frame for mulitpass phrase processing
  602. */
  603. if (qdf_unlikely(vdev->multipass_en)) {
  604. if (dp_rx_multipass_process(peer, nbuf, tid) == false) {
  605. DP_STATS_INC(peer, rx.multipass_rx_pkt_drop, 1);
  606. qdf_nbuf_free(nbuf);
  607. nbuf = next;
  608. continue;
  609. }
  610. }
  611. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, peer)) {
  612. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  613. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  614. /* Drop & free packet */
  615. qdf_nbuf_free(nbuf);
  616. /* Statistics */
  617. nbuf = next;
  618. continue;
  619. }
  620. if (qdf_unlikely(peer && (peer->nawds_enabled) &&
  621. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  622. (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc,
  623. rx_tlv_hdr) ==
  624. false))) {
  625. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  626. DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
  627. qdf_nbuf_free(nbuf);
  628. nbuf = next;
  629. continue;
  630. }
  631. /*
  632. * Drop non-EAPOL frames from unauthorized peer.
  633. */
  634. if (qdf_likely(peer) && qdf_unlikely(!peer->authorize) &&
  635. !qdf_nbuf_is_raw_frame(nbuf)) {
  636. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  637. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  638. if (!is_eapol) {
  639. DP_STATS_INC(soc,
  640. rx.err.peer_unauth_rx_pkt_drop,
  641. 1);
  642. qdf_nbuf_free(nbuf);
  643. nbuf = next;
  644. continue;
  645. }
  646. }
  647. if (soc->process_rx_status)
  648. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  649. /* Update the protocol tag in SKB based on CCE metadata */
  650. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  651. reo_ring_num, false, true);
  652. /* Update the flow tag in SKB based on FSE metadata */
  653. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  654. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, peer,
  655. reo_ring_num, tid_stats);
  656. if (qdf_unlikely(vdev->mesh_vdev)) {
  657. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  658. == QDF_STATUS_SUCCESS) {
  659. dp_rx_info("%pK: mesh pkt filtered", soc);
  660. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  661. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  662. 1);
  663. qdf_nbuf_free(nbuf);
  664. nbuf = next;
  665. continue;
  666. }
  667. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
  668. }
  669. if (qdf_likely(vdev->rx_decap_type ==
  670. htt_cmn_pkt_type_ethernet) &&
  671. qdf_likely(!vdev->mesh_vdev)) {
  672. dp_rx_wds_learn(soc, vdev,
  673. rx_tlv_hdr,
  674. peer,
  675. nbuf,
  676. msdu_metadata);
  677. /* Intrabss-fwd */
  678. if (dp_rx_check_ap_bridge(vdev))
  679. if (dp_rx_intrabss_fwd_be(soc, peer, rx_tlv_hdr,
  680. nbuf,
  681. msdu_metadata)) {
  682. nbuf = next;
  683. tid_stats->intrabss_cnt++;
  684. continue; /* Get next desc */
  685. }
  686. }
  687. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  688. dp_rx_update_stats(soc, nbuf);
  689. DP_RX_LIST_APPEND(deliver_list_head,
  690. deliver_list_tail,
  691. nbuf);
  692. DP_STATS_INC_PKT(peer, rx.to_stack, 1,
  693. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  694. if (qdf_unlikely(peer->in_twt))
  695. DP_STATS_INC_PKT(peer, rx.to_stack_twt, 1,
  696. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  697. tid_stats->delivered_to_stack++;
  698. nbuf = next;
  699. }
  700. if (qdf_likely(deliver_list_head)) {
  701. if (qdf_likely(peer)) {
  702. dp_rx_deliver_to_pkt_capture(soc, vdev->pdev, peer_id,
  703. pkt_capture_offload,
  704. deliver_list_head);
  705. if (!pkt_capture_offload)
  706. dp_rx_deliver_to_stack(soc, vdev, peer,
  707. deliver_list_head,
  708. deliver_list_tail);
  709. } else {
  710. nbuf = deliver_list_head;
  711. while (nbuf) {
  712. next = nbuf->next;
  713. nbuf->next = NULL;
  714. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  715. nbuf = next;
  716. }
  717. }
  718. }
  719. if (qdf_likely(peer))
  720. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  721. /*
  722. * If we are processing in near-full condition, there are 3 scenario
  723. * 1) Ring entries has reached critical state
  724. * 2) Ring entries are still near high threshold
  725. * 3) Ring entries are below the safe level
  726. *
  727. * One more loop will move the state to normal processing and yield
  728. */
  729. if (ring_near_full && quota)
  730. goto more_data;
  731. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  732. if (quota) {
  733. num_pending =
  734. dp_rx_srng_get_num_pending(hal_soc,
  735. hal_ring_hdl,
  736. num_entries,
  737. &near_full);
  738. if (num_pending) {
  739. DP_STATS_INC(soc, rx.hp_oos2, 1);
  740. if (!hif_exec_should_yield(scn, intr_id))
  741. goto more_data;
  742. if (qdf_unlikely(near_full)) {
  743. DP_STATS_INC(soc, rx.near_full, 1);
  744. goto more_data;
  745. }
  746. }
  747. }
  748. if (vdev && vdev->osif_fisa_flush)
  749. vdev->osif_fisa_flush(soc, reo_ring_num);
  750. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  751. vdev->osif_gro_flush(vdev->osif_vdev,
  752. reo_ring_num);
  753. }
  754. }
  755. /* Update histogram statistics by looping through pdev's */
  756. DP_RX_HIST_STATS_PER_PDEV();
  757. return rx_bufs_used; /* Assume no scale factor for now */
  758. }
  759. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  760. /**
  761. * dp_rx_desc_pool_init_be_cc() - initial RX desc pool for cookie conversion
  762. * @soc: Handle to DP Soc structure
  763. * @rx_desc_pool: Rx descriptor pool handler
  764. * @pool_id: Rx descriptor pool ID
  765. *
  766. * Return: QDF_STATUS_SUCCESS - succeeded, others - failed
  767. */
  768. static QDF_STATUS
  769. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  770. struct rx_desc_pool *rx_desc_pool,
  771. uint32_t pool_id)
  772. {
  773. struct dp_soc_be *be_soc;
  774. union dp_rx_desc_list_elem_t *rx_desc_elem;
  775. struct dp_spt_page_desc *page_desc;
  776. struct dp_spt_page_desc_list *page_desc_list;
  777. be_soc = dp_get_be_soc_from_dp_soc(soc);
  778. page_desc_list = &be_soc->rx_spt_page_desc[pool_id];
  779. /* allocate SPT pages from page desc pool */
  780. page_desc_list->num_spt_pages =
  781. dp_cc_spt_page_desc_alloc(be_soc,
  782. &page_desc_list->spt_page_list_head,
  783. &page_desc_list->spt_page_list_tail,
  784. rx_desc_pool->pool_size);
  785. if (!page_desc_list->num_spt_pages) {
  786. dp_err("fail to allocate cookie conversion spt pages");
  787. return QDF_STATUS_E_FAILURE;
  788. }
  789. /* put each RX Desc VA to SPT pages and get corresponding ID */
  790. page_desc = page_desc_list->spt_page_list_head;
  791. rx_desc_elem = rx_desc_pool->freelist;
  792. while (rx_desc_elem) {
  793. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  794. page_desc->avail_entry_index,
  795. &rx_desc_elem->rx_desc);
  796. rx_desc_elem->rx_desc.cookie =
  797. dp_cc_desc_id_generate(page_desc->ppt_index,
  798. page_desc->avail_entry_index);
  799. rx_desc_elem->rx_desc.pool_id = pool_id;
  800. rx_desc_elem->rx_desc.in_use = 0;
  801. rx_desc_elem = rx_desc_elem->next;
  802. page_desc->avail_entry_index++;
  803. if (page_desc->avail_entry_index >=
  804. DP_CC_SPT_PAGE_MAX_ENTRIES)
  805. page_desc = page_desc->next;
  806. }
  807. return QDF_STATUS_SUCCESS;
  808. }
  809. #else
  810. static QDF_STATUS
  811. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  812. struct rx_desc_pool *rx_desc_pool,
  813. uint32_t pool_id)
  814. {
  815. struct dp_soc_be *be_soc;
  816. struct dp_spt_page_desc *page_desc;
  817. struct dp_spt_page_desc_list *page_desc_list;
  818. int i;
  819. be_soc = dp_get_be_soc_from_dp_soc(soc);
  820. page_desc_list = &be_soc->rx_spt_page_desc[pool_id];
  821. /* allocate SPT pages from page desc pool */
  822. page_desc_list->num_spt_pages =
  823. dp_cc_spt_page_desc_alloc(
  824. be_soc,
  825. &page_desc_list->spt_page_list_head,
  826. &page_desc_list->spt_page_list_tail,
  827. rx_desc_pool->pool_size);
  828. if (!page_desc_list->num_spt_pages) {
  829. dp_err("fail to allocate cookie conversion spt pages");
  830. return QDF_STATUS_E_FAILURE;
  831. }
  832. /* put each RX Desc VA to SPT pages and get corresponding ID */
  833. page_desc = page_desc_list->spt_page_list_head;
  834. for (i = 0; i <= rx_desc_pool->pool_size - 1; i++) {
  835. if (i == rx_desc_pool->pool_size - 1)
  836. rx_desc_pool->array[i].next = NULL;
  837. else
  838. rx_desc_pool->array[i].next =
  839. &rx_desc_pool->array[i + 1];
  840. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  841. page_desc->avail_entry_index,
  842. &rx_desc_pool->array[i].rx_desc);
  843. rx_desc_pool->array[i].rx_desc.cookie =
  844. dp_cc_desc_id_generate(page_desc->ppt_index,
  845. page_desc->avail_entry_index);
  846. rx_desc_pool->array[i].rx_desc.pool_id = pool_id;
  847. rx_desc_pool->array[i].rx_desc.in_use = 0;
  848. page_desc->avail_entry_index++;
  849. if (page_desc->avail_entry_index >=
  850. DP_CC_SPT_PAGE_MAX_ENTRIES)
  851. page_desc = page_desc->next;
  852. }
  853. return QDF_STATUS_SUCCESS;
  854. }
  855. #endif
  856. static void
  857. dp_rx_desc_pool_deinit_be_cc(struct dp_soc *soc,
  858. struct rx_desc_pool *rx_desc_pool,
  859. uint32_t pool_id)
  860. {
  861. struct dp_soc_be *be_soc;
  862. struct dp_spt_page_desc *page_desc;
  863. struct dp_spt_page_desc_list *page_desc_list;
  864. be_soc = dp_get_be_soc_from_dp_soc(soc);
  865. page_desc_list = &be_soc->rx_spt_page_desc[pool_id];
  866. if (!page_desc_list->num_spt_pages) {
  867. dp_warn("page_desc_list is empty for pool_id %d", pool_id);
  868. return;
  869. }
  870. /* cleanup for each page */
  871. page_desc = page_desc_list->spt_page_list_head;
  872. while (page_desc) {
  873. page_desc->avail_entry_index = 0;
  874. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  875. page_desc = page_desc->next;
  876. }
  877. /* free pages desc back to pool */
  878. dp_cc_spt_page_desc_free(be_soc,
  879. &page_desc_list->spt_page_list_head,
  880. &page_desc_list->spt_page_list_tail,
  881. page_desc_list->num_spt_pages);
  882. page_desc_list->num_spt_pages = 0;
  883. }
  884. QDF_STATUS dp_rx_desc_pool_init_be(struct dp_soc *soc,
  885. struct rx_desc_pool *rx_desc_pool,
  886. uint32_t pool_id)
  887. {
  888. QDF_STATUS status = QDF_STATUS_SUCCESS;
  889. /* Only regular RX buffer desc pool use HW cookie conversion */
  890. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE) {
  891. dp_info("rx_desc_buf pool init");
  892. status = dp_rx_desc_pool_init_be_cc(soc,
  893. rx_desc_pool,
  894. pool_id);
  895. } else {
  896. dp_info("non_rx_desc_buf_pool init");
  897. status = dp_rx_desc_pool_init_generic(soc, rx_desc_pool, pool_id);
  898. }
  899. return status;
  900. }
  901. void dp_rx_desc_pool_deinit_be(struct dp_soc *soc,
  902. struct rx_desc_pool *rx_desc_pool,
  903. uint32_t pool_id)
  904. {
  905. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE)
  906. dp_rx_desc_pool_deinit_be_cc(soc, rx_desc_pool, pool_id);
  907. }
  908. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  909. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  910. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  911. void *ring_desc,
  912. struct dp_rx_desc **r_rx_desc)
  913. {
  914. if (hal_rx_wbm_get_cookie_convert_done(ring_desc)) {
  915. /* HW cookie conversion done */
  916. *r_rx_desc = (struct dp_rx_desc *)
  917. hal_rx_wbm_get_desc_va(ring_desc);
  918. } else {
  919. /* SW do cookie conversion */
  920. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  921. *r_rx_desc = (struct dp_rx_desc *)
  922. dp_cc_desc_find(soc, cookie);
  923. }
  924. return QDF_STATUS_SUCCESS;
  925. }
  926. #else
  927. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  928. void *ring_desc,
  929. struct dp_rx_desc **r_rx_desc)
  930. {
  931. *r_rx_desc = (struct dp_rx_desc *)
  932. hal_rx_wbm_get_desc_va(ring_desc);
  933. return QDF_STATUS_SUCCESS;
  934. }
  935. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  936. #else
  937. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  938. void *ring_desc,
  939. struct dp_rx_desc **r_rx_desc)
  940. {
  941. /* SW do cookie conversion */
  942. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  943. *r_rx_desc = (struct dp_rx_desc *)
  944. dp_cc_desc_find(soc, cookie);
  945. return QDF_STATUS_SUCCESS;
  946. }
  947. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  948. struct dp_rx_desc *dp_rx_desc_cookie_2_va_be(struct dp_soc *soc,
  949. uint32_t cookie)
  950. {
  951. return (struct dp_rx_desc *)dp_cc_desc_find(soc, cookie);
  952. }
  953. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  954. uint32_t dp_rx_nf_process(struct dp_intr *int_ctx,
  955. hal_ring_handle_t hal_ring_hdl,
  956. uint8_t reo_ring_num,
  957. uint32_t quota)
  958. {
  959. struct dp_soc *soc = int_ctx->soc;
  960. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  961. uint32_t work_done = 0;
  962. if (dp_srng_get_near_full_level(soc, rx_ring) <
  963. DP_SRNG_THRESH_NEAR_FULL)
  964. return 0;
  965. qdf_atomic_set(&rx_ring->near_full, 1);
  966. work_done++;
  967. return work_done;
  968. }
  969. #endif
  970. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  971. #ifdef WLAN_FEATURE_11BE_MLO
  972. /**
  973. * dp_rx_intrabss_fwd_mlo_allow() - check if MLO forwarding is allowed
  974. * @ta_peer: transmitter peer handle
  975. * @da_peer: destination peer handle
  976. *
  977. * Return: true - MLO forwarding case, false: not
  978. */
  979. static inline bool
  980. dp_rx_intrabss_fwd_mlo_allow(struct dp_peer *ta_peer,
  981. struct dp_peer *da_peer)
  982. {
  983. /* one of TA/DA peer should belong to MLO connection peer,
  984. * only MLD peer type is as expected
  985. */
  986. if (!IS_MLO_DP_MLD_PEER(ta_peer) &&
  987. !IS_MLO_DP_MLD_PEER(da_peer))
  988. return false;
  989. /* TA peer and DA peer's vdev should be partner MLO vdevs */
  990. if (dp_peer_find_mac_addr_cmp(&ta_peer->vdev->mld_mac_addr,
  991. &da_peer->vdev->mld_mac_addr))
  992. return false;
  993. return true;
  994. }
  995. #else
  996. static inline bool
  997. dp_rx_intrabss_fwd_mlo_allow(struct dp_peer *ta_peer,
  998. struct dp_peer *da_peer)
  999. {
  1000. return false;
  1001. }
  1002. #endif
  1003. #ifdef INTRA_BSS_FWD_OFFLOAD
  1004. /**
  1005. * dp_rx_intrabss_ucast_check_be() - Check if intrabss is allowed
  1006. for unicast frame
  1007. * @soc: SOC hanlde
  1008. * @nbuf: RX packet buffer
  1009. * @ta_peer: transmitter DP peer handle
  1010. * @msdu_metadata: MSDU meta data info
  1011. * @p_tx_vdev_id: get vdev id for Intra-BSS TX
  1012. *
  1013. * Return: true - intrabss allowed
  1014. false - not allow
  1015. */
  1016. static bool
  1017. dp_rx_intrabss_ucast_check_be(struct dp_soc *soc, qdf_nbuf_t nbuf,
  1018. struct dp_peer *ta_peer,
  1019. struct hal_rx_msdu_metadata *msdu_metadata,
  1020. uint8_t *p_tx_vdev_id)
  1021. {
  1022. uint16_t da_peer_id;
  1023. struct dp_peer *da_peer;
  1024. if (!qdf_nbuf_is_intra_bss(nbuf))
  1025. return false;
  1026. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1027. soc,
  1028. msdu_metadata->da_idx);
  1029. da_peer = dp_peer_get_ref_by_id(soc, da_peer_id, DP_MOD_ID_RX);
  1030. if (!da_peer)
  1031. return false;
  1032. *p_tx_vdev_id = da_peer->vdev->vdev_id;
  1033. dp_peer_unref_delete(da_peer, DP_MOD_ID_RX);
  1034. return true;
  1035. }
  1036. #else
  1037. static bool
  1038. dp_rx_intrabss_ucast_check_be(struct dp_soc *soc, qdf_nbuf_t nbuf,
  1039. struct dp_peer *ta_peer,
  1040. struct hal_rx_msdu_metadata *msdu_metadata,
  1041. uint8_t *p_tx_vdev_id)
  1042. {
  1043. uint16_t da_peer_id;
  1044. struct dp_peer *da_peer;
  1045. bool ret = false;
  1046. if (!(qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf)))
  1047. return false;
  1048. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1049. soc,
  1050. msdu_metadata->da_idx);
  1051. da_peer = dp_peer_get_ref_by_id(soc, da_peer_id,
  1052. DP_MOD_ID_RX);
  1053. if (!da_peer)
  1054. return false;
  1055. *p_tx_vdev_id = da_peer->vdev->vdev_id;
  1056. /* If the source or destination peer in the isolation
  1057. * list then dont forward instead push to bridge stack.
  1058. */
  1059. if (dp_get_peer_isolation(ta_peer) ||
  1060. dp_get_peer_isolation(da_peer))
  1061. goto rel_da_peer;
  1062. if (da_peer->bss_peer || da_peer == ta_peer)
  1063. goto rel_da_peer;
  1064. /* Same vdev, support Inra-BSS */
  1065. if (da_peer->vdev == ta_peer->vdev) {
  1066. ret = true;
  1067. goto rel_da_peer;
  1068. }
  1069. /* MLO specific Intra-BSS check */
  1070. if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
  1071. ret = true;
  1072. goto rel_da_peer;
  1073. }
  1074. rel_da_peer:
  1075. dp_peer_unref_delete(da_peer, DP_MOD_ID_RX);
  1076. return ret;
  1077. }
  1078. #endif
  1079. /*
  1080. * dp_rx_intrabss_fwd_be() - API for intrabss fwd. For EAPOL
  1081. * pkt with DA not equal to vdev mac addr, fwd is not allowed.
  1082. * @soc: core txrx main context
  1083. * @ta_peer: source peer entry
  1084. * @rx_tlv_hdr: start address of rx tlvs
  1085. * @nbuf: nbuf that has to be intrabss forwarded
  1086. * @msdu_metadata: msdu metadata
  1087. *
  1088. * Return: true if it is forwarded else false
  1089. */
  1090. bool dp_rx_intrabss_fwd_be(struct dp_soc *soc, struct dp_peer *ta_peer,
  1091. uint8_t *rx_tlv_hdr, qdf_nbuf_t nbuf,
  1092. struct hal_rx_msdu_metadata msdu_metadata)
  1093. {
  1094. uint8_t tx_vdev_id;
  1095. uint8_t tid = qdf_nbuf_get_tid_val(nbuf);
  1096. uint8_t ring_id = QDF_NBUF_CB_RX_CTX_ID(nbuf);
  1097. struct cdp_tid_rx_stats *tid_stats = &ta_peer->vdev->pdev->stats.
  1098. tid_stats.tid_rx_stats[ring_id][tid];
  1099. /* if it is a broadcast pkt (eg: ARP) and it is not its own
  1100. * source, then clone the pkt and send the cloned pkt for
  1101. * intra BSS forwarding and original pkt up the network stack
  1102. * Note: how do we handle multicast pkts. do we forward
  1103. * all multicast pkts as is or let a higher layer module
  1104. * like igmpsnoop decide whether to forward or not with
  1105. * Mcast enhancement.
  1106. */
  1107. if (qdf_nbuf_is_da_mcbc(nbuf) && !ta_peer->bss_peer)
  1108. return dp_rx_intrabss_mcbc_fwd(soc, ta_peer, rx_tlv_hdr,
  1109. nbuf, tid_stats);
  1110. if (dp_rx_intrabss_ucast_check_be(soc, nbuf, ta_peer,
  1111. &msdu_metadata, &tx_vdev_id))
  1112. return dp_rx_intrabss_ucast_fwd(soc, ta_peer, tx_vdev_id,
  1113. rx_tlv_hdr, nbuf, tid_stats);
  1114. return false;
  1115. }
  1116. #endif