dp_tx.c 143 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  44. #include <dp_swlm.h>
  45. #endif
  46. /* Flag to skip CCE classify when mesh or tid override enabled */
  47. #define DP_TX_SKIP_CCE_CLASSIFY \
  48. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  49. /* TODO Add support in TSO */
  50. #define DP_DESC_NUM_FRAG(x) 0
  51. /* disable TQM_BYPASS */
  52. #define TQM_BYPASS_WAR 0
  53. /* invalid peer id for reinject*/
  54. #define DP_INVALID_PEER 0XFFFE
  55. /*mapping between hal encrypt type and cdp_sec_type*/
  56. #define MAX_CDP_SEC_TYPE 12
  57. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  58. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  59. HAL_TX_ENCRYPT_TYPE_WEP_128,
  60. HAL_TX_ENCRYPT_TYPE_WEP_104,
  61. HAL_TX_ENCRYPT_TYPE_WEP_40,
  62. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  63. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_WAPI,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  70. #ifdef QCA_TX_LIMIT_CHECK
  71. /**
  72. * dp_tx_limit_check - Check if allocated tx descriptors reached
  73. * soc max limit and pdev max limit
  74. * @vdev: DP vdev handle
  75. *
  76. * Return: true if allocated tx descriptors reached max configured value, else
  77. * false
  78. */
  79. static inline bool
  80. dp_tx_limit_check(struct dp_vdev *vdev)
  81. {
  82. struct dp_pdev *pdev = vdev->pdev;
  83. struct dp_soc *soc = pdev->soc;
  84. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  85. soc->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  93. pdev->num_tx_allowed) {
  94. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  95. "%s: queued packets are more than max tx, drop the frame",
  96. __func__);
  97. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  98. return true;
  99. }
  100. return false;
  101. }
  102. /**
  103. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  104. * reached soc max limit
  105. * @vdev: DP vdev handle
  106. *
  107. * Return: true if allocated tx descriptors reached max configured value, else
  108. * false
  109. */
  110. static inline bool
  111. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  112. {
  113. struct dp_pdev *pdev = vdev->pdev;
  114. struct dp_soc *soc = pdev->soc;
  115. if (qdf_atomic_read(&soc->num_tx_exception) >=
  116. soc->num_msdu_exception_desc) {
  117. dp_info("exc packets are more than max drop the exc pkt");
  118. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  119. return true;
  120. }
  121. return false;
  122. }
  123. /**
  124. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  125. * @vdev: DP pdev handle
  126. *
  127. * Return: void
  128. */
  129. static inline void
  130. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  131. {
  132. struct dp_soc *soc = pdev->soc;
  133. qdf_atomic_inc(&pdev->num_tx_outstanding);
  134. qdf_atomic_inc(&soc->num_tx_outstanding);
  135. }
  136. /**
  137. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  138. * @vdev: DP pdev handle
  139. *
  140. * Return: void
  141. */
  142. static inline void
  143. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  144. {
  145. struct dp_soc *soc = pdev->soc;
  146. qdf_atomic_dec(&pdev->num_tx_outstanding);
  147. qdf_atomic_dec(&soc->num_tx_outstanding);
  148. }
  149. #else //QCA_TX_LIMIT_CHECK
  150. static inline bool
  151. dp_tx_limit_check(struct dp_vdev *vdev)
  152. {
  153. return false;
  154. }
  155. static inline bool
  156. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  157. {
  158. return false;
  159. }
  160. static inline void
  161. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  162. {
  163. qdf_atomic_inc(&pdev->num_tx_outstanding);
  164. }
  165. static inline void
  166. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  167. {
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. }
  170. #endif //QCA_TX_LIMIT_CHECK
  171. #if defined(FEATURE_TSO)
  172. /**
  173. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  174. *
  175. * @soc - core txrx main context
  176. * @seg_desc - tso segment descriptor
  177. * @num_seg_desc - tso number segment descriptor
  178. */
  179. static void dp_tx_tso_unmap_segment(
  180. struct dp_soc *soc,
  181. struct qdf_tso_seg_elem_t *seg_desc,
  182. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  183. {
  184. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  185. if (qdf_unlikely(!seg_desc)) {
  186. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  187. __func__, __LINE__);
  188. qdf_assert(0);
  189. } else if (qdf_unlikely(!num_seg_desc)) {
  190. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  191. __func__, __LINE__);
  192. qdf_assert(0);
  193. } else {
  194. bool is_last_seg;
  195. /* no tso segment left to do dma unmap */
  196. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  197. return;
  198. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  199. true : false;
  200. qdf_nbuf_unmap_tso_segment(soc->osdev,
  201. seg_desc, is_last_seg);
  202. num_seg_desc->num_seg.tso_cmn_num_seg--;
  203. }
  204. }
  205. /**
  206. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  207. * back to the freelist
  208. *
  209. * @soc - soc device handle
  210. * @tx_desc - Tx software descriptor
  211. */
  212. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  213. struct dp_tx_desc_s *tx_desc)
  214. {
  215. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  216. if (qdf_unlikely(!tx_desc->tso_desc)) {
  217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  218. "%s %d TSO desc is NULL!",
  219. __func__, __LINE__);
  220. qdf_assert(0);
  221. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  222. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  223. "%s %d TSO num desc is NULL!",
  224. __func__, __LINE__);
  225. qdf_assert(0);
  226. } else {
  227. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  228. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  229. /* Add the tso num segment into the free list */
  230. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  231. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  232. tx_desc->tso_num_desc);
  233. tx_desc->tso_num_desc = NULL;
  234. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  235. }
  236. /* Add the tso segment into the free list*/
  237. dp_tx_tso_desc_free(soc,
  238. tx_desc->pool_id, tx_desc->tso_desc);
  239. tx_desc->tso_desc = NULL;
  240. }
  241. }
  242. #else
  243. static void dp_tx_tso_unmap_segment(
  244. struct dp_soc *soc,
  245. struct qdf_tso_seg_elem_t *seg_desc,
  246. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  247. {
  248. }
  249. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  250. struct dp_tx_desc_s *tx_desc)
  251. {
  252. }
  253. #endif
  254. /**
  255. * dp_tx_desc_release() - Release Tx Descriptor
  256. * @tx_desc : Tx Descriptor
  257. * @desc_pool_id: Descriptor Pool ID
  258. *
  259. * Deallocate all resources attached to Tx descriptor and free the Tx
  260. * descriptor.
  261. *
  262. * Return:
  263. */
  264. static void
  265. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  266. {
  267. struct dp_pdev *pdev = tx_desc->pdev;
  268. struct dp_soc *soc;
  269. uint8_t comp_status = 0;
  270. qdf_assert(pdev);
  271. soc = pdev->soc;
  272. dp_tx_outstanding_dec(pdev);
  273. if (tx_desc->frm_type == dp_tx_frm_tso)
  274. dp_tx_tso_desc_release(soc, tx_desc);
  275. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  276. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  277. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  278. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  279. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  280. qdf_atomic_dec(&soc->num_tx_exception);
  281. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  282. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  283. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  284. soc->hal_soc);
  285. else
  286. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  287. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  288. "Tx Completion Release desc %d status %d outstanding %d",
  289. tx_desc->id, comp_status,
  290. qdf_atomic_read(&pdev->num_tx_outstanding));
  291. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  292. return;
  293. }
  294. /**
  295. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  296. * @vdev: DP vdev Handle
  297. * @nbuf: skb
  298. * @msdu_info: msdu_info required to create HTT metadata
  299. *
  300. * Prepares and fills HTT metadata in the frame pre-header for special frames
  301. * that should be transmitted using varying transmit parameters.
  302. * There are 2 VDEV modes that currently needs this special metadata -
  303. * 1) Mesh Mode
  304. * 2) DSRC Mode
  305. *
  306. * Return: HTT metadata size
  307. *
  308. */
  309. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  310. struct dp_tx_msdu_info_s *msdu_info)
  311. {
  312. uint32_t *meta_data = msdu_info->meta_data;
  313. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  314. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  315. uint8_t htt_desc_size;
  316. /* Size rounded of multiple of 8 bytes */
  317. uint8_t htt_desc_size_aligned;
  318. uint8_t *hdr = NULL;
  319. /*
  320. * Metadata - HTT MSDU Extension header
  321. */
  322. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  323. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  324. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  325. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  326. meta_data[0])) {
  327. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  328. htt_desc_size_aligned)) {
  329. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  330. htt_desc_size_aligned);
  331. if (!nbuf) {
  332. /*
  333. * qdf_nbuf_realloc_headroom won't do skb_clone
  334. * as skb_realloc_headroom does. so, no free is
  335. * needed here.
  336. */
  337. DP_STATS_INC(vdev,
  338. tx_i.dropped.headroom_insufficient,
  339. 1);
  340. qdf_print(" %s[%d] skb_realloc_headroom failed",
  341. __func__, __LINE__);
  342. return 0;
  343. }
  344. }
  345. /* Fill and add HTT metaheader */
  346. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  347. if (!hdr) {
  348. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  349. "Error in filling HTT metadata");
  350. return 0;
  351. }
  352. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  353. } else if (vdev->opmode == wlan_op_mode_ocb) {
  354. /* Todo - Add support for DSRC */
  355. }
  356. return htt_desc_size_aligned;
  357. }
  358. /**
  359. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  360. * @tso_seg: TSO segment to process
  361. * @ext_desc: Pointer to MSDU extension descriptor
  362. *
  363. * Return: void
  364. */
  365. #if defined(FEATURE_TSO)
  366. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  367. void *ext_desc)
  368. {
  369. uint8_t num_frag;
  370. uint32_t tso_flags;
  371. /*
  372. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  373. * tcp_flag_mask
  374. *
  375. * Checksum enable flags are set in TCL descriptor and not in Extension
  376. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  377. */
  378. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  379. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  380. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  381. tso_seg->tso_flags.ip_len);
  382. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  383. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  384. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  385. uint32_t lo = 0;
  386. uint32_t hi = 0;
  387. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  388. (tso_seg->tso_frags[num_frag].length));
  389. qdf_dmaaddr_to_32s(
  390. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  391. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  392. tso_seg->tso_frags[num_frag].length);
  393. }
  394. return;
  395. }
  396. #else
  397. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  398. void *ext_desc)
  399. {
  400. return;
  401. }
  402. #endif
  403. #if defined(FEATURE_TSO)
  404. /**
  405. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  406. * allocated and free them
  407. *
  408. * @soc: soc handle
  409. * @free_seg: list of tso segments
  410. * @msdu_info: msdu descriptor
  411. *
  412. * Return - void
  413. */
  414. static void dp_tx_free_tso_seg_list(
  415. struct dp_soc *soc,
  416. struct qdf_tso_seg_elem_t *free_seg,
  417. struct dp_tx_msdu_info_s *msdu_info)
  418. {
  419. struct qdf_tso_seg_elem_t *next_seg;
  420. while (free_seg) {
  421. next_seg = free_seg->next;
  422. dp_tx_tso_desc_free(soc,
  423. msdu_info->tx_queue.desc_pool_id,
  424. free_seg);
  425. free_seg = next_seg;
  426. }
  427. }
  428. /**
  429. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  430. * allocated and free them
  431. *
  432. * @soc: soc handle
  433. * @free_num_seg: list of tso number segments
  434. * @msdu_info: msdu descriptor
  435. * Return - void
  436. */
  437. static void dp_tx_free_tso_num_seg_list(
  438. struct dp_soc *soc,
  439. struct qdf_tso_num_seg_elem_t *free_num_seg,
  440. struct dp_tx_msdu_info_s *msdu_info)
  441. {
  442. struct qdf_tso_num_seg_elem_t *next_num_seg;
  443. while (free_num_seg) {
  444. next_num_seg = free_num_seg->next;
  445. dp_tso_num_seg_free(soc,
  446. msdu_info->tx_queue.desc_pool_id,
  447. free_num_seg);
  448. free_num_seg = next_num_seg;
  449. }
  450. }
  451. /**
  452. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  453. * do dma unmap for each segment
  454. *
  455. * @soc: soc handle
  456. * @free_seg: list of tso segments
  457. * @num_seg_desc: tso number segment descriptor
  458. *
  459. * Return - void
  460. */
  461. static void dp_tx_unmap_tso_seg_list(
  462. struct dp_soc *soc,
  463. struct qdf_tso_seg_elem_t *free_seg,
  464. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  465. {
  466. struct qdf_tso_seg_elem_t *next_seg;
  467. if (qdf_unlikely(!num_seg_desc)) {
  468. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  469. return;
  470. }
  471. while (free_seg) {
  472. next_seg = free_seg->next;
  473. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  474. free_seg = next_seg;
  475. }
  476. }
  477. #ifdef FEATURE_TSO_STATS
  478. /**
  479. * dp_tso_get_stats_idx: Retrieve the tso packet id
  480. * @pdev - pdev handle
  481. *
  482. * Return: id
  483. */
  484. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  485. {
  486. uint32_t stats_idx;
  487. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  488. % CDP_MAX_TSO_PACKETS);
  489. return stats_idx;
  490. }
  491. #else
  492. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  493. {
  494. return 0;
  495. }
  496. #endif /* FEATURE_TSO_STATS */
  497. /**
  498. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  499. * free the tso segments descriptor and
  500. * tso num segments descriptor
  501. *
  502. * @soc: soc handle
  503. * @msdu_info: msdu descriptor
  504. * @tso_seg_unmap: flag to show if dma unmap is necessary
  505. *
  506. * Return - void
  507. */
  508. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  509. struct dp_tx_msdu_info_s *msdu_info,
  510. bool tso_seg_unmap)
  511. {
  512. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  513. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  514. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  515. tso_info->tso_num_seg_list;
  516. /* do dma unmap for each segment */
  517. if (tso_seg_unmap)
  518. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  519. /* free all tso number segment descriptor though looks only have 1 */
  520. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  521. /* free all tso segment descriptor */
  522. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  523. }
  524. /**
  525. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  526. * @vdev: virtual device handle
  527. * @msdu: network buffer
  528. * @msdu_info: meta data associated with the msdu
  529. *
  530. * Return: QDF_STATUS_SUCCESS success
  531. */
  532. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  533. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  534. {
  535. struct qdf_tso_seg_elem_t *tso_seg;
  536. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  537. struct dp_soc *soc = vdev->pdev->soc;
  538. struct dp_pdev *pdev = vdev->pdev;
  539. struct qdf_tso_info_t *tso_info;
  540. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  541. tso_info = &msdu_info->u.tso_info;
  542. tso_info->curr_seg = NULL;
  543. tso_info->tso_seg_list = NULL;
  544. tso_info->num_segs = num_seg;
  545. msdu_info->frm_type = dp_tx_frm_tso;
  546. tso_info->tso_num_seg_list = NULL;
  547. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  548. while (num_seg) {
  549. tso_seg = dp_tx_tso_desc_alloc(
  550. soc, msdu_info->tx_queue.desc_pool_id);
  551. if (tso_seg) {
  552. tso_seg->next = tso_info->tso_seg_list;
  553. tso_info->tso_seg_list = tso_seg;
  554. num_seg--;
  555. } else {
  556. dp_err_rl("Failed to alloc tso seg desc");
  557. DP_STATS_INC_PKT(vdev->pdev,
  558. tso_stats.tso_no_mem_dropped, 1,
  559. qdf_nbuf_len(msdu));
  560. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  561. return QDF_STATUS_E_NOMEM;
  562. }
  563. }
  564. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  565. tso_num_seg = dp_tso_num_seg_alloc(soc,
  566. msdu_info->tx_queue.desc_pool_id);
  567. if (tso_num_seg) {
  568. tso_num_seg->next = tso_info->tso_num_seg_list;
  569. tso_info->tso_num_seg_list = tso_num_seg;
  570. } else {
  571. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  572. __func__);
  573. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  574. return QDF_STATUS_E_NOMEM;
  575. }
  576. msdu_info->num_seg =
  577. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  578. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  579. msdu_info->num_seg);
  580. if (!(msdu_info->num_seg)) {
  581. /*
  582. * Free allocated TSO seg desc and number seg desc,
  583. * do unmap for segments if dma map has done.
  584. */
  585. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  586. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  587. return QDF_STATUS_E_INVAL;
  588. }
  589. tso_info->curr_seg = tso_info->tso_seg_list;
  590. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  591. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  592. msdu, msdu_info->num_seg);
  593. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  594. tso_info->msdu_stats_idx);
  595. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  596. return QDF_STATUS_SUCCESS;
  597. }
  598. #else
  599. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  600. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  601. {
  602. return QDF_STATUS_E_NOMEM;
  603. }
  604. #endif
  605. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  606. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  607. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  608. /**
  609. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  610. * @vdev: DP Vdev handle
  611. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  612. * @desc_pool_id: Descriptor Pool ID
  613. *
  614. * Return:
  615. */
  616. static
  617. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  618. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  619. {
  620. uint8_t i;
  621. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  622. struct dp_tx_seg_info_s *seg_info;
  623. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  624. struct dp_soc *soc = vdev->pdev->soc;
  625. /* Allocate an extension descriptor */
  626. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  627. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  628. if (!msdu_ext_desc) {
  629. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  630. return NULL;
  631. }
  632. if (msdu_info->exception_fw &&
  633. qdf_unlikely(vdev->mesh_vdev)) {
  634. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  635. &msdu_info->meta_data[0],
  636. sizeof(struct htt_tx_msdu_desc_ext2_t));
  637. qdf_atomic_inc(&soc->num_tx_exception);
  638. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  639. }
  640. switch (msdu_info->frm_type) {
  641. case dp_tx_frm_sg:
  642. case dp_tx_frm_me:
  643. case dp_tx_frm_raw:
  644. seg_info = msdu_info->u.sg_info.curr_seg;
  645. /* Update the buffer pointers in MSDU Extension Descriptor */
  646. for (i = 0; i < seg_info->frag_cnt; i++) {
  647. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  648. seg_info->frags[i].paddr_lo,
  649. seg_info->frags[i].paddr_hi,
  650. seg_info->frags[i].len);
  651. }
  652. break;
  653. case dp_tx_frm_tso:
  654. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  655. &cached_ext_desc[0]);
  656. break;
  657. default:
  658. break;
  659. }
  660. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  661. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  662. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  663. msdu_ext_desc->vaddr);
  664. return msdu_ext_desc;
  665. }
  666. /**
  667. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  668. *
  669. * @skb: skb to be traced
  670. * @msdu_id: msdu_id of the packet
  671. * @vdev_id: vdev_id of the packet
  672. *
  673. * Return: None
  674. */
  675. #ifdef DP_DISABLE_TX_PKT_TRACE
  676. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  677. uint8_t vdev_id)
  678. {
  679. }
  680. #else
  681. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  682. uint8_t vdev_id)
  683. {
  684. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  685. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  686. DPTRACE(qdf_dp_trace_ptr(skb,
  687. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  688. QDF_TRACE_DEFAULT_PDEV_ID,
  689. qdf_nbuf_data_addr(skb),
  690. sizeof(qdf_nbuf_data(skb)),
  691. msdu_id, vdev_id));
  692. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  693. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  694. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  695. msdu_id, QDF_TX));
  696. }
  697. #endif
  698. #ifdef QCA_SUPPORT_WDS_EXTENDED
  699. /**
  700. * dp_is_tx_extended() - Configure AST override from peer ast entry
  701. *
  702. * @vdev: DP vdev handle
  703. * @tx_exc_metadata: Handle that holds exception path metadata
  704. *
  705. * Return: if this packet needs to exception to FW or not
  706. * (false: exception to wlan FW, true: do not exception)
  707. */
  708. static inline bool
  709. dp_is_tx_extended(struct dp_vdev *vdev, struct cdp_tx_exception_metadata
  710. *tx_exc_metadata)
  711. {
  712. if (qdf_likely(!vdev->wds_ext_enabled))
  713. return false;
  714. if (tx_exc_metadata && !tx_exc_metadata->is_wds_extended)
  715. return false;
  716. return true;
  717. }
  718. /**
  719. * dp_tx_wds_ext() - Configure AST override from peer ast entry
  720. *
  721. * @soc: DP soc handle
  722. * @vdev: DP vdev handle
  723. * @peer_id: peer_id of the peer for which packet is destined
  724. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  725. *
  726. * Return: None
  727. */
  728. static inline void
  729. dp_tx_wds_ext(struct dp_soc *soc, struct dp_vdev *vdev, uint16_t peer_id,
  730. struct dp_tx_msdu_info_s *msdu_info)
  731. {
  732. struct dp_peer *peer = NULL;
  733. msdu_info->search_type = vdev->search_type;
  734. msdu_info->ast_idx = vdev->bss_ast_idx;
  735. msdu_info->ast_hash = vdev->bss_ast_hash;
  736. if (qdf_likely(!vdev->wds_ext_enabled))
  737. return;
  738. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_TX);
  739. if (qdf_unlikely(!peer))
  740. return;
  741. msdu_info->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  742. msdu_info->ast_idx = peer->self_ast_entry->ast_idx;
  743. msdu_info->ast_hash = peer->self_ast_entry->ast_hash_value;
  744. dp_peer_unref_delete(peer, DP_MOD_ID_TX);
  745. msdu_info->exception_fw = 0;
  746. }
  747. #else
  748. static inline bool
  749. dp_is_tx_extended(struct dp_vdev *vdev, struct cdp_tx_exception_metadata
  750. *tx_exc_metadata)
  751. {
  752. return false;
  753. }
  754. static inline void
  755. dp_tx_wds_ext(struct dp_soc *soc, struct dp_vdev *vdev, uint16_t peer_id,
  756. struct dp_tx_msdu_info_s *msdu_info)
  757. {
  758. msdu_info->search_type = vdev->search_type;
  759. msdu_info->ast_idx = vdev->bss_ast_idx;
  760. msdu_info->ast_hash = vdev->bss_ast_hash;
  761. }
  762. #endif
  763. /**
  764. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  765. * @vdev: DP vdev handle
  766. * @nbuf: skb
  767. * @desc_pool_id: Descriptor pool ID
  768. * @meta_data: Metadata to the fw
  769. * @tx_exc_metadata: Handle that holds exception path metadata
  770. * Allocate and prepare Tx descriptor with msdu information.
  771. *
  772. * Return: Pointer to Tx Descriptor on success,
  773. * NULL on failure
  774. */
  775. static
  776. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  777. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  778. struct dp_tx_msdu_info_s *msdu_info,
  779. struct cdp_tx_exception_metadata *tx_exc_metadata)
  780. {
  781. uint8_t align_pad;
  782. uint8_t is_exception = 0;
  783. uint8_t htt_hdr_size;
  784. struct dp_tx_desc_s *tx_desc;
  785. struct dp_pdev *pdev = vdev->pdev;
  786. struct dp_soc *soc = pdev->soc;
  787. if (dp_tx_limit_check(vdev))
  788. return NULL;
  789. /* Allocate software Tx descriptor */
  790. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  791. if (qdf_unlikely(!tx_desc)) {
  792. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  793. return NULL;
  794. }
  795. dp_tx_outstanding_inc(pdev);
  796. /* Initialize the SW tx descriptor */
  797. tx_desc->nbuf = nbuf;
  798. tx_desc->frm_type = dp_tx_frm_std;
  799. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  800. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  801. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  802. tx_desc->vdev_id = vdev->vdev_id;
  803. tx_desc->pdev = pdev;
  804. tx_desc->msdu_ext_desc = NULL;
  805. tx_desc->pkt_offset = 0;
  806. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  807. if (qdf_unlikely(vdev->multipass_en)) {
  808. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  809. goto failure;
  810. }
  811. if (qdf_unlikely(dp_is_tx_extended(vdev, tx_exc_metadata)))
  812. return tx_desc;
  813. /*
  814. * For special modes (vdev_type == ocb or mesh), data frames should be
  815. * transmitted using varying transmit parameters (tx spec) which include
  816. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  817. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  818. * These frames are sent as exception packets to firmware.
  819. *
  820. * HW requirement is that metadata should always point to a
  821. * 8-byte aligned address. So we add alignment pad to start of buffer.
  822. * HTT Metadata should be ensured to be multiple of 8-bytes,
  823. * to get 8-byte aligned start address along with align_pad added
  824. *
  825. * |-----------------------------|
  826. * | |
  827. * |-----------------------------| <-----Buffer Pointer Address given
  828. * | | ^ in HW descriptor (aligned)
  829. * | HTT Metadata | |
  830. * | | |
  831. * | | | Packet Offset given in descriptor
  832. * | | |
  833. * |-----------------------------| |
  834. * | Alignment Pad | v
  835. * |-----------------------------| <----- Actual buffer start address
  836. * | SKB Data | (Unaligned)
  837. * | |
  838. * | |
  839. * | |
  840. * | |
  841. * | |
  842. * |-----------------------------|
  843. */
  844. if (qdf_unlikely((msdu_info->exception_fw)) ||
  845. (vdev->opmode == wlan_op_mode_ocb) ||
  846. (tx_exc_metadata &&
  847. tx_exc_metadata->is_tx_sniffer)) {
  848. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  849. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  850. DP_STATS_INC(vdev,
  851. tx_i.dropped.headroom_insufficient, 1);
  852. goto failure;
  853. }
  854. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  855. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  856. "qdf_nbuf_push_head failed");
  857. goto failure;
  858. }
  859. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  860. msdu_info);
  861. if (htt_hdr_size == 0)
  862. goto failure;
  863. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  864. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  865. is_exception = 1;
  866. }
  867. #if !TQM_BYPASS_WAR
  868. if (is_exception || tx_exc_metadata)
  869. #endif
  870. {
  871. /* Temporary WAR due to TQM VP issues */
  872. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  873. qdf_atomic_inc(&soc->num_tx_exception);
  874. }
  875. return tx_desc;
  876. failure:
  877. dp_tx_desc_release(tx_desc, desc_pool_id);
  878. return NULL;
  879. }
  880. /**
  881. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  882. * @vdev: DP vdev handle
  883. * @nbuf: skb
  884. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  885. * @desc_pool_id : Descriptor Pool ID
  886. *
  887. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  888. * information. For frames wth fragments, allocate and prepare
  889. * an MSDU extension descriptor
  890. *
  891. * Return: Pointer to Tx Descriptor on success,
  892. * NULL on failure
  893. */
  894. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  895. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  896. uint8_t desc_pool_id)
  897. {
  898. struct dp_tx_desc_s *tx_desc;
  899. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  900. struct dp_pdev *pdev = vdev->pdev;
  901. struct dp_soc *soc = pdev->soc;
  902. if (dp_tx_limit_check(vdev))
  903. return NULL;
  904. /* Allocate software Tx descriptor */
  905. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  906. if (!tx_desc) {
  907. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  908. return NULL;
  909. }
  910. dp_tx_outstanding_inc(pdev);
  911. /* Initialize the SW tx descriptor */
  912. tx_desc->nbuf = nbuf;
  913. tx_desc->frm_type = msdu_info->frm_type;
  914. tx_desc->tx_encap_type = vdev->tx_encap_type;
  915. tx_desc->vdev_id = vdev->vdev_id;
  916. tx_desc->pdev = pdev;
  917. tx_desc->pkt_offset = 0;
  918. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  919. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  920. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  921. /* Handle scattered frames - TSO/SG/ME */
  922. /* Allocate and prepare an extension descriptor for scattered frames */
  923. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  924. if (!msdu_ext_desc) {
  925. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  926. "%s Tx Extension Descriptor Alloc Fail",
  927. __func__);
  928. goto failure;
  929. }
  930. #if TQM_BYPASS_WAR
  931. /* Temporary WAR due to TQM VP issues */
  932. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  933. qdf_atomic_inc(&soc->num_tx_exception);
  934. #endif
  935. if (qdf_unlikely(msdu_info->exception_fw))
  936. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  937. tx_desc->msdu_ext_desc = msdu_ext_desc;
  938. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  939. return tx_desc;
  940. failure:
  941. dp_tx_desc_release(tx_desc, desc_pool_id);
  942. return NULL;
  943. }
  944. /**
  945. * dp_tx_prepare_raw() - Prepare RAW packet TX
  946. * @vdev: DP vdev handle
  947. * @nbuf: buffer pointer
  948. * @seg_info: Pointer to Segment info Descriptor to be prepared
  949. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  950. * descriptor
  951. *
  952. * Return:
  953. */
  954. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  955. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  956. {
  957. qdf_nbuf_t curr_nbuf = NULL;
  958. uint16_t total_len = 0;
  959. qdf_dma_addr_t paddr;
  960. int32_t i;
  961. int32_t mapped_buf_num = 0;
  962. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  963. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  964. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  965. /* Continue only if frames are of DATA type */
  966. if (!DP_FRAME_IS_DATA(qos_wh)) {
  967. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  968. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  969. "Pkt. recd is of not data type");
  970. goto error;
  971. }
  972. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  973. if (vdev->raw_mode_war &&
  974. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  975. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  976. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  977. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  978. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  979. /*
  980. * Number of nbuf's must not exceed the size of the frags
  981. * array in seg_info.
  982. */
  983. if (i >= DP_TX_MAX_NUM_FRAGS) {
  984. dp_err_rl("nbuf cnt exceeds the max number of segs");
  985. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  986. goto error;
  987. }
  988. if (QDF_STATUS_SUCCESS !=
  989. qdf_nbuf_map_nbytes_single(vdev->osdev,
  990. curr_nbuf,
  991. QDF_DMA_TO_DEVICE,
  992. curr_nbuf->len)) {
  993. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  994. "%s dma map error ", __func__);
  995. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  996. goto error;
  997. }
  998. /* Update the count of mapped nbuf's */
  999. mapped_buf_num++;
  1000. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1001. seg_info->frags[i].paddr_lo = paddr;
  1002. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1003. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1004. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1005. total_len += qdf_nbuf_len(curr_nbuf);
  1006. }
  1007. seg_info->frag_cnt = i;
  1008. seg_info->total_len = total_len;
  1009. seg_info->next = NULL;
  1010. sg_info->curr_seg = seg_info;
  1011. msdu_info->frm_type = dp_tx_frm_raw;
  1012. msdu_info->num_seg = 1;
  1013. return nbuf;
  1014. error:
  1015. i = 0;
  1016. while (nbuf) {
  1017. curr_nbuf = nbuf;
  1018. if (i < mapped_buf_num) {
  1019. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1020. QDF_DMA_TO_DEVICE,
  1021. curr_nbuf->len);
  1022. i++;
  1023. }
  1024. nbuf = qdf_nbuf_next(nbuf);
  1025. qdf_nbuf_free(curr_nbuf);
  1026. }
  1027. return NULL;
  1028. }
  1029. /**
  1030. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1031. * @soc: DP soc handle
  1032. * @nbuf: Buffer pointer
  1033. *
  1034. * unmap the chain of nbufs that belong to this RAW frame.
  1035. *
  1036. * Return: None
  1037. */
  1038. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1039. qdf_nbuf_t nbuf)
  1040. {
  1041. qdf_nbuf_t cur_nbuf = nbuf;
  1042. do {
  1043. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1044. QDF_DMA_TO_DEVICE,
  1045. cur_nbuf->len);
  1046. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1047. } while (cur_nbuf);
  1048. }
  1049. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1050. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  1051. { \
  1052. qdf_nbuf_t nbuf_local; \
  1053. struct dp_vdev *vdev_local = vdev_hdl; \
  1054. do { \
  1055. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  1056. break; \
  1057. nbuf_local = nbuf; \
  1058. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  1059. htt_cmn_pkt_type_raw)) \
  1060. break; \
  1061. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  1062. break; \
  1063. else if (qdf_nbuf_is_tso((nbuf_local))) \
  1064. break; \
  1065. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  1066. (nbuf_local), \
  1067. NULL, 1, 0); \
  1068. } while (0); \
  1069. }
  1070. #else
  1071. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  1072. #endif
  1073. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1074. /**
  1075. * dp_tx_update_stats() - Update soc level tx stats
  1076. * @soc: DP soc handle
  1077. * @nbuf: packet being transmitted
  1078. *
  1079. * Returns: none
  1080. */
  1081. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1082. qdf_nbuf_t nbuf)
  1083. {
  1084. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1085. }
  1086. /**
  1087. * dp_tx_attempt_coalescing() - Check and attempt TCL register write coalescing
  1088. * @soc: Datapath soc handle
  1089. * @tx_desc: tx packet descriptor
  1090. * @tid: TID for pkt transmission
  1091. *
  1092. * Returns: 1, if coalescing is to be done
  1093. * 0, if coalescing is not to be done
  1094. */
  1095. static inline int
  1096. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1097. struct dp_tx_desc_s *tx_desc,
  1098. uint8_t tid)
  1099. {
  1100. struct dp_swlm *swlm = &soc->swlm;
  1101. union swlm_data swlm_query_data;
  1102. struct dp_swlm_tcl_data tcl_data;
  1103. QDF_STATUS status;
  1104. int ret;
  1105. if (qdf_unlikely(!swlm->is_enabled))
  1106. return 0;
  1107. tcl_data.nbuf = tx_desc->nbuf;
  1108. tcl_data.tid = tid;
  1109. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1110. swlm_query_data.tcl_data = &tcl_data;
  1111. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1112. if (QDF_IS_STATUS_ERROR(status)) {
  1113. dp_swlm_tcl_reset_session_data(soc);
  1114. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1115. return 0;
  1116. }
  1117. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1118. if (ret) {
  1119. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1120. } else {
  1121. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1122. }
  1123. return ret;
  1124. }
  1125. /**
  1126. * dp_tx_ring_access_end() - HAL ring access end for data transmission
  1127. * @soc: Datapath soc handle
  1128. * @hal_ring_hdl: HAL ring handle
  1129. * @coalesce: Coalesce the current write or not
  1130. *
  1131. * Returns: none
  1132. */
  1133. static inline void
  1134. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1135. int coalesce)
  1136. {
  1137. if (coalesce)
  1138. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1139. else
  1140. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1141. }
  1142. #else
  1143. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1144. qdf_nbuf_t nbuf)
  1145. {
  1146. }
  1147. static inline int
  1148. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1149. struct dp_tx_desc_s *tx_desc,
  1150. uint8_t tid)
  1151. {
  1152. return 0;
  1153. }
  1154. static inline void
  1155. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1156. int coalesce)
  1157. {
  1158. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1159. }
  1160. #endif
  1161. /**
  1162. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1163. * @soc: DP Soc Handle
  1164. * @vdev: DP vdev handle
  1165. * @tx_desc: Tx Descriptor Handle
  1166. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1167. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1168. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1169. * @tx_exc_metadata: Handle that holds exception path meta data
  1170. *
  1171. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1172. * from software Tx descriptor
  1173. *
  1174. * Return: QDF_STATUS_SUCCESS: success
  1175. * QDF_STATUS_E_RESOURCES: Error return
  1176. */
  1177. static QDF_STATUS
  1178. dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1179. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1180. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1181. struct dp_tx_msdu_info_s *msdu_info)
  1182. {
  1183. uint8_t type;
  1184. void *hal_tx_desc;
  1185. uint32_t *hal_tx_desc_cached;
  1186. int coalesce = 0;
  1187. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1188. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  1189. uint8_t tid = msdu_info->tid;
  1190. /*
  1191. * Setting it initialization statically here to avoid
  1192. * a memset call jump with qdf_mem_set call
  1193. */
  1194. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1195. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1196. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1197. tx_exc_metadata->sec_type : vdev->sec_type);
  1198. /* Return Buffer Manager ID */
  1199. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1200. hal_ring_handle_t hal_ring_hdl = NULL;
  1201. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1202. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1203. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1204. return QDF_STATUS_E_RESOURCES;
  1205. }
  1206. hal_tx_desc_cached = (void *) cached_desc;
  1207. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1208. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1209. tx_desc->dma_addr = tx_desc->msdu_ext_desc->paddr;
  1210. if (tx_desc->msdu_ext_desc->flags &
  1211. DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1212. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1213. else
  1214. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1215. } else {
  1216. tx_desc->length = qdf_nbuf_len(tx_desc->nbuf) -
  1217. tx_desc->pkt_offset;
  1218. type = HAL_TX_BUF_TYPE_BUFFER;
  1219. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1220. }
  1221. qdf_assert_always(tx_desc->dma_addr);
  1222. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1223. tx_desc->dma_addr, bm_id, tx_desc->id,
  1224. type);
  1225. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1226. vdev->lmac_id);
  1227. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1228. msdu_info->search_type);
  1229. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1230. msdu_info->ast_idx);
  1231. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1232. vdev->dscp_tid_map_id);
  1233. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1234. sec_type_map[sec_type]);
  1235. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1236. (msdu_info->ast_hash & 0xF));
  1237. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1238. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1239. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1240. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1241. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1242. vdev->hal_desc_addr_search_flags);
  1243. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1244. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1245. /* verify checksum offload configuration*/
  1246. if (vdev->csum_enabled &&
  1247. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1248. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1249. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1250. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1251. }
  1252. if (tid != HTT_TX_EXT_TID_INVALID)
  1253. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1254. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1255. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1256. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1257. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1258. soc->wlan_cfg_ctx)))
  1259. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1260. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1261. tx_desc->length, type, (uint64_t)tx_desc->dma_addr,
  1262. tx_desc->pkt_offset, tx_desc->id);
  1263. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1264. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1265. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1266. "%s %d : HAL RING Access Failed -- %pK",
  1267. __func__, __LINE__, hal_ring_hdl);
  1268. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1269. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1270. return status;
  1271. }
  1272. /* Sync cached descriptor with HW */
  1273. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1274. if (qdf_unlikely(!hal_tx_desc)) {
  1275. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1276. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1277. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1278. goto ring_access_fail;
  1279. }
  1280. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1281. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1282. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1283. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
  1284. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1285. dp_tx_update_stats(soc, tx_desc->nbuf);
  1286. status = QDF_STATUS_SUCCESS;
  1287. ring_access_fail:
  1288. if (hif_pm_runtime_get(soc->hif_handle,
  1289. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1290. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1291. hif_pm_runtime_put(soc->hif_handle,
  1292. RTPM_ID_DW_TX_HW_ENQUEUE);
  1293. } else {
  1294. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1295. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1296. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1297. }
  1298. return status;
  1299. }
  1300. /**
  1301. * dp_cce_classify() - Classify the frame based on CCE rules
  1302. * @vdev: DP vdev handle
  1303. * @nbuf: skb
  1304. *
  1305. * Classify frames based on CCE rules
  1306. * Return: bool( true if classified,
  1307. * else false)
  1308. */
  1309. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1310. {
  1311. qdf_ether_header_t *eh = NULL;
  1312. uint16_t ether_type;
  1313. qdf_llc_t *llcHdr;
  1314. qdf_nbuf_t nbuf_clone = NULL;
  1315. qdf_dot3_qosframe_t *qos_wh = NULL;
  1316. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1317. /*
  1318. * In case of mesh packets or hlos tid override enabled,
  1319. * don't do any classification
  1320. */
  1321. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1322. & DP_TX_SKIP_CCE_CLASSIFY))
  1323. return false;
  1324. }
  1325. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1326. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1327. ether_type = eh->ether_type;
  1328. llcHdr = (qdf_llc_t *)(nbuf->data +
  1329. sizeof(qdf_ether_header_t));
  1330. } else {
  1331. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1332. /* For encrypted packets don't do any classification */
  1333. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1334. return false;
  1335. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1336. if (qdf_unlikely(
  1337. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1338. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1339. ether_type = *(uint16_t *)(nbuf->data
  1340. + QDF_IEEE80211_4ADDR_HDR_LEN
  1341. + sizeof(qdf_llc_t)
  1342. - sizeof(ether_type));
  1343. llcHdr = (qdf_llc_t *)(nbuf->data +
  1344. QDF_IEEE80211_4ADDR_HDR_LEN);
  1345. } else {
  1346. ether_type = *(uint16_t *)(nbuf->data
  1347. + QDF_IEEE80211_3ADDR_HDR_LEN
  1348. + sizeof(qdf_llc_t)
  1349. - sizeof(ether_type));
  1350. llcHdr = (qdf_llc_t *)(nbuf->data +
  1351. QDF_IEEE80211_3ADDR_HDR_LEN);
  1352. }
  1353. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1354. && (ether_type ==
  1355. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1356. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1357. return true;
  1358. }
  1359. }
  1360. return false;
  1361. }
  1362. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1363. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1364. sizeof(*llcHdr));
  1365. nbuf_clone = qdf_nbuf_clone(nbuf);
  1366. if (qdf_unlikely(nbuf_clone)) {
  1367. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1368. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1369. qdf_nbuf_pull_head(nbuf_clone,
  1370. sizeof(qdf_net_vlanhdr_t));
  1371. }
  1372. }
  1373. } else {
  1374. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1375. nbuf_clone = qdf_nbuf_clone(nbuf);
  1376. if (qdf_unlikely(nbuf_clone)) {
  1377. qdf_nbuf_pull_head(nbuf_clone,
  1378. sizeof(qdf_net_vlanhdr_t));
  1379. }
  1380. }
  1381. }
  1382. if (qdf_unlikely(nbuf_clone))
  1383. nbuf = nbuf_clone;
  1384. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1385. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1386. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1387. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1388. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1389. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1390. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1391. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1392. if (qdf_unlikely(nbuf_clone))
  1393. qdf_nbuf_free(nbuf_clone);
  1394. return true;
  1395. }
  1396. if (qdf_unlikely(nbuf_clone))
  1397. qdf_nbuf_free(nbuf_clone);
  1398. return false;
  1399. }
  1400. /**
  1401. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1402. * @vdev: DP vdev handle
  1403. * @nbuf: skb
  1404. *
  1405. * Extract the DSCP or PCP information from frame and map into TID value.
  1406. *
  1407. * Return: void
  1408. */
  1409. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1410. struct dp_tx_msdu_info_s *msdu_info)
  1411. {
  1412. uint8_t tos = 0, dscp_tid_override = 0;
  1413. uint8_t *hdr_ptr, *L3datap;
  1414. uint8_t is_mcast = 0;
  1415. qdf_ether_header_t *eh = NULL;
  1416. qdf_ethervlan_header_t *evh = NULL;
  1417. uint16_t ether_type;
  1418. qdf_llc_t *llcHdr;
  1419. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1420. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1421. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1422. eh = (qdf_ether_header_t *)nbuf->data;
  1423. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1424. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1425. } else {
  1426. qdf_dot3_qosframe_t *qos_wh =
  1427. (qdf_dot3_qosframe_t *) nbuf->data;
  1428. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1429. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1430. return;
  1431. }
  1432. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1433. ether_type = eh->ether_type;
  1434. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1435. /*
  1436. * Check if packet is dot3 or eth2 type.
  1437. */
  1438. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1439. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1440. sizeof(*llcHdr));
  1441. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1442. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1443. sizeof(*llcHdr);
  1444. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1445. + sizeof(*llcHdr) +
  1446. sizeof(qdf_net_vlanhdr_t));
  1447. } else {
  1448. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1449. sizeof(*llcHdr);
  1450. }
  1451. } else {
  1452. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1453. evh = (qdf_ethervlan_header_t *) eh;
  1454. ether_type = evh->ether_type;
  1455. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1456. }
  1457. }
  1458. /*
  1459. * Find priority from IP TOS DSCP field
  1460. */
  1461. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1462. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1463. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1464. /* Only for unicast frames */
  1465. if (!is_mcast) {
  1466. /* send it on VO queue */
  1467. msdu_info->tid = DP_VO_TID;
  1468. }
  1469. } else {
  1470. /*
  1471. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1472. * from TOS byte.
  1473. */
  1474. tos = ip->ip_tos;
  1475. dscp_tid_override = 1;
  1476. }
  1477. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1478. /* TODO
  1479. * use flowlabel
  1480. *igmpmld cases to be handled in phase 2
  1481. */
  1482. unsigned long ver_pri_flowlabel;
  1483. unsigned long pri;
  1484. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1485. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1486. DP_IPV6_PRIORITY_SHIFT;
  1487. tos = pri;
  1488. dscp_tid_override = 1;
  1489. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1490. msdu_info->tid = DP_VO_TID;
  1491. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1492. /* Only for unicast frames */
  1493. if (!is_mcast) {
  1494. /* send ucast arp on VO queue */
  1495. msdu_info->tid = DP_VO_TID;
  1496. }
  1497. }
  1498. /*
  1499. * Assign all MCAST packets to BE
  1500. */
  1501. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1502. if (is_mcast) {
  1503. tos = 0;
  1504. dscp_tid_override = 1;
  1505. }
  1506. }
  1507. if (dscp_tid_override == 1) {
  1508. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1509. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1510. }
  1511. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1512. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1513. return;
  1514. }
  1515. /**
  1516. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1517. * @vdev: DP vdev handle
  1518. * @nbuf: skb
  1519. *
  1520. * Software based TID classification is required when more than 2 DSCP-TID
  1521. * mapping tables are needed.
  1522. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1523. *
  1524. * Return: void
  1525. */
  1526. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1527. struct dp_tx_msdu_info_s *msdu_info)
  1528. {
  1529. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1530. /*
  1531. * skip_sw_tid_classification flag will set in below cases-
  1532. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1533. * 2. hlos_tid_override enabled for vdev
  1534. * 3. mesh mode enabled for vdev
  1535. */
  1536. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1537. /* Update tid in msdu_info from skb priority */
  1538. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1539. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1540. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1541. return;
  1542. }
  1543. return;
  1544. }
  1545. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1546. }
  1547. #ifdef FEATURE_WLAN_TDLS
  1548. /**
  1549. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1550. * @soc: datapath SOC
  1551. * @vdev: datapath vdev
  1552. * @tx_desc: TX descriptor
  1553. *
  1554. * Return: None
  1555. */
  1556. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1557. struct dp_vdev *vdev,
  1558. struct dp_tx_desc_s *tx_desc)
  1559. {
  1560. if (vdev) {
  1561. if (vdev->is_tdls_frame) {
  1562. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1563. vdev->is_tdls_frame = false;
  1564. }
  1565. }
  1566. }
  1567. /**
  1568. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1569. * @soc: dp_soc handle
  1570. * @tx_desc: TX descriptor
  1571. * @vdev: datapath vdev handle
  1572. *
  1573. * Return: None
  1574. */
  1575. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1576. struct dp_tx_desc_s *tx_desc)
  1577. {
  1578. struct hal_tx_completion_status ts = {0};
  1579. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1580. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1581. DP_MOD_ID_TDLS);
  1582. if (qdf_unlikely(!vdev)) {
  1583. dp_err_rl("vdev is null!");
  1584. goto error;
  1585. }
  1586. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1587. if (vdev->tx_non_std_data_callback.func) {
  1588. qdf_nbuf_set_next(nbuf, NULL);
  1589. vdev->tx_non_std_data_callback.func(
  1590. vdev->tx_non_std_data_callback.ctxt,
  1591. nbuf, ts.status);
  1592. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1593. return;
  1594. } else {
  1595. dp_err_rl("callback func is null");
  1596. }
  1597. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1598. error:
  1599. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1600. qdf_nbuf_free(nbuf);
  1601. }
  1602. /**
  1603. * dp_tx_msdu_single_map() - do nbuf map
  1604. * @vdev: DP vdev handle
  1605. * @tx_desc: DP TX descriptor pointer
  1606. * @nbuf: skb pointer
  1607. *
  1608. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1609. * operation done in other component.
  1610. *
  1611. * Return: QDF_STATUS
  1612. */
  1613. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1614. struct dp_tx_desc_s *tx_desc,
  1615. qdf_nbuf_t nbuf)
  1616. {
  1617. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1618. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1619. nbuf,
  1620. QDF_DMA_TO_DEVICE,
  1621. nbuf->len);
  1622. else
  1623. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1624. QDF_DMA_TO_DEVICE);
  1625. }
  1626. #else
  1627. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1628. struct dp_vdev *vdev,
  1629. struct dp_tx_desc_s *tx_desc)
  1630. {
  1631. }
  1632. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1633. struct dp_tx_desc_s *tx_desc)
  1634. {
  1635. }
  1636. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1637. struct dp_tx_desc_s *tx_desc,
  1638. qdf_nbuf_t nbuf)
  1639. {
  1640. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1641. nbuf,
  1642. QDF_DMA_TO_DEVICE,
  1643. nbuf->len);
  1644. }
  1645. #endif
  1646. #ifdef MESH_MODE_SUPPORT
  1647. /**
  1648. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1649. * @soc: datapath SOC
  1650. * @vdev: datapath vdev
  1651. * @tx_desc: TX descriptor
  1652. *
  1653. * Return: None
  1654. */
  1655. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1656. struct dp_vdev *vdev,
  1657. struct dp_tx_desc_s *tx_desc)
  1658. {
  1659. if (qdf_unlikely(vdev->mesh_vdev))
  1660. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1661. }
  1662. /**
  1663. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1664. * @soc: dp_soc handle
  1665. * @tx_desc: TX descriptor
  1666. * @vdev: datapath vdev handle
  1667. *
  1668. * Return: None
  1669. */
  1670. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1671. struct dp_tx_desc_s *tx_desc)
  1672. {
  1673. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1674. struct dp_vdev *vdev = NULL;
  1675. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1676. qdf_nbuf_free(nbuf);
  1677. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1678. } else {
  1679. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1680. DP_MOD_ID_MESH);
  1681. if (vdev && vdev->osif_tx_free_ext)
  1682. vdev->osif_tx_free_ext((nbuf));
  1683. else
  1684. qdf_nbuf_free(nbuf);
  1685. if (vdev)
  1686. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1687. }
  1688. }
  1689. #else
  1690. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1691. struct dp_vdev *vdev,
  1692. struct dp_tx_desc_s *tx_desc)
  1693. {
  1694. }
  1695. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1696. struct dp_tx_desc_s *tx_desc)
  1697. {
  1698. }
  1699. #endif
  1700. /**
  1701. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1702. * @vdev: DP vdev handle
  1703. * @nbuf: skb
  1704. *
  1705. * Return: 1 if frame needs to be dropped else 0
  1706. */
  1707. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1708. {
  1709. struct dp_pdev *pdev = NULL;
  1710. struct dp_ast_entry *src_ast_entry = NULL;
  1711. struct dp_ast_entry *dst_ast_entry = NULL;
  1712. struct dp_soc *soc = NULL;
  1713. qdf_assert(vdev);
  1714. pdev = vdev->pdev;
  1715. qdf_assert(pdev);
  1716. soc = pdev->soc;
  1717. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1718. (soc, dstmac, vdev->pdev->pdev_id);
  1719. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1720. (soc, srcmac, vdev->pdev->pdev_id);
  1721. if (dst_ast_entry && src_ast_entry) {
  1722. if (dst_ast_entry->peer_id ==
  1723. src_ast_entry->peer_id)
  1724. return 1;
  1725. }
  1726. return 0;
  1727. }
  1728. /**
  1729. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1730. * @vdev: DP vdev handle
  1731. * @nbuf: skb
  1732. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1733. * @meta_data: Metadata to the fw
  1734. * @tx_q: Tx queue to be used for this Tx frame
  1735. * @peer_id: peer_id of the peer in case of NAWDS frames
  1736. * @tx_exc_metadata: Handle that holds exception path metadata
  1737. *
  1738. * Return: NULL on success,
  1739. * nbuf when it fails to send
  1740. */
  1741. qdf_nbuf_t
  1742. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1743. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1744. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1745. {
  1746. struct dp_pdev *pdev = vdev->pdev;
  1747. struct dp_soc *soc = pdev->soc;
  1748. struct dp_tx_desc_s *tx_desc;
  1749. QDF_STATUS status;
  1750. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1751. uint16_t htt_tcl_metadata = 0;
  1752. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1753. uint8_t tid = msdu_info->tid;
  1754. struct cdp_tid_tx_stats *tid_stats = NULL;
  1755. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1756. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1757. msdu_info, tx_exc_metadata);
  1758. if (!tx_desc) {
  1759. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1760. vdev, tx_q->desc_pool_id);
  1761. drop_code = TX_DESC_ERR;
  1762. goto fail_return;
  1763. }
  1764. if (qdf_unlikely(soc->cce_disable)) {
  1765. if (dp_cce_classify(vdev, nbuf) == true) {
  1766. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1767. tid = DP_VO_TID;
  1768. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1769. }
  1770. }
  1771. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1772. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1773. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1774. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1775. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1776. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1777. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1778. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1779. peer_id);
  1780. } else
  1781. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1782. if (msdu_info->exception_fw)
  1783. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1784. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1785. !pdev->enhanced_stats_en);
  1786. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1787. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1788. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1789. /* Handle failure */
  1790. dp_err("qdf_nbuf_map failed");
  1791. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1792. drop_code = TX_DMA_MAP_ERR;
  1793. goto release_desc;
  1794. }
  1795. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1796. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1797. tx_exc_metadata, msdu_info);
  1798. if (status != QDF_STATUS_SUCCESS) {
  1799. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1800. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1801. __func__, tx_desc, tx_q->ring_id);
  1802. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1803. QDF_DMA_TO_DEVICE,
  1804. nbuf->len);
  1805. drop_code = TX_HW_ENQUEUE;
  1806. goto release_desc;
  1807. }
  1808. return NULL;
  1809. release_desc:
  1810. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1811. fail_return:
  1812. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1813. tid_stats = &pdev->stats.tid_stats.
  1814. tid_tx_stats[tx_q->ring_id][tid];
  1815. tid_stats->swdrop_cnt[drop_code]++;
  1816. return nbuf;
  1817. }
  1818. /**
  1819. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1820. * @soc: Soc handle
  1821. * @desc: software Tx descriptor to be processed
  1822. *
  1823. * Return: none
  1824. */
  1825. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1826. struct dp_tx_desc_s *desc)
  1827. {
  1828. qdf_nbuf_t nbuf = desc->nbuf;
  1829. /* nbuf already freed in vdev detach path */
  1830. if (!nbuf)
  1831. return;
  1832. /* If it is TDLS mgmt, don't unmap or free the frame */
  1833. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1834. return dp_non_std_tx_comp_free_buff(soc, desc);
  1835. /* 0 : MSDU buffer, 1 : MLE */
  1836. if (desc->msdu_ext_desc) {
  1837. /* TSO free */
  1838. if (hal_tx_ext_desc_get_tso_enable(
  1839. desc->msdu_ext_desc->vaddr)) {
  1840. /* unmap eash TSO seg before free the nbuf */
  1841. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1842. desc->tso_num_desc);
  1843. qdf_nbuf_free(nbuf);
  1844. return;
  1845. }
  1846. }
  1847. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  1848. QDF_DMA_TO_DEVICE, nbuf->len);
  1849. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1850. return dp_mesh_tx_comp_free_buff(soc, desc);
  1851. qdf_nbuf_free(nbuf);
  1852. }
  1853. /**
  1854. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1855. * @vdev: DP vdev handle
  1856. * @nbuf: skb
  1857. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1858. *
  1859. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1860. *
  1861. * Return: NULL on success,
  1862. * nbuf when it fails to send
  1863. */
  1864. #if QDF_LOCK_STATS
  1865. noinline
  1866. #else
  1867. #endif
  1868. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1869. struct dp_tx_msdu_info_s *msdu_info)
  1870. {
  1871. uint32_t i;
  1872. struct dp_pdev *pdev = vdev->pdev;
  1873. struct dp_soc *soc = pdev->soc;
  1874. struct dp_tx_desc_s *tx_desc;
  1875. bool is_cce_classified = false;
  1876. QDF_STATUS status;
  1877. uint16_t htt_tcl_metadata = 0;
  1878. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1879. struct cdp_tid_tx_stats *tid_stats = NULL;
  1880. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1881. if (qdf_unlikely(soc->cce_disable)) {
  1882. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1883. if (is_cce_classified) {
  1884. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1885. msdu_info->tid = DP_VO_TID;
  1886. }
  1887. }
  1888. if (msdu_info->frm_type == dp_tx_frm_me)
  1889. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1890. i = 0;
  1891. /* Print statement to track i and num_seg */
  1892. /*
  1893. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1894. * descriptors using information in msdu_info
  1895. */
  1896. while (i < msdu_info->num_seg) {
  1897. /*
  1898. * Setup Tx descriptor for an MSDU, and MSDU extension
  1899. * descriptor
  1900. */
  1901. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1902. tx_q->desc_pool_id);
  1903. if (!tx_desc) {
  1904. if (msdu_info->frm_type == dp_tx_frm_me) {
  1905. prep_desc_fail++;
  1906. dp_tx_me_free_buf(pdev,
  1907. (void *)(msdu_info->u.sg_info
  1908. .curr_seg->frags[0].vaddr));
  1909. if (prep_desc_fail == msdu_info->num_seg) {
  1910. /*
  1911. * Unmap is needed only if descriptor
  1912. * preparation failed for all segments.
  1913. */
  1914. qdf_nbuf_unmap(soc->osdev,
  1915. msdu_info->u.sg_info.
  1916. curr_seg->nbuf,
  1917. QDF_DMA_TO_DEVICE);
  1918. }
  1919. /*
  1920. * Free the nbuf for the current segment
  1921. * and make it point to the next in the list.
  1922. * For me, there are as many segments as there
  1923. * are no of clients.
  1924. */
  1925. qdf_nbuf_free(msdu_info->u.sg_info
  1926. .curr_seg->nbuf);
  1927. if (msdu_info->u.sg_info.curr_seg->next) {
  1928. msdu_info->u.sg_info.curr_seg =
  1929. msdu_info->u.sg_info
  1930. .curr_seg->next;
  1931. nbuf = msdu_info->u.sg_info
  1932. .curr_seg->nbuf;
  1933. }
  1934. i++;
  1935. continue;
  1936. }
  1937. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1938. dp_tx_tso_unmap_segment(soc,
  1939. msdu_info->u.tso_info.
  1940. curr_seg,
  1941. msdu_info->u.tso_info.
  1942. tso_num_seg_list);
  1943. if (msdu_info->u.tso_info.curr_seg->next) {
  1944. msdu_info->u.tso_info.curr_seg =
  1945. msdu_info->u.tso_info.curr_seg->next;
  1946. i++;
  1947. continue;
  1948. }
  1949. }
  1950. goto done;
  1951. }
  1952. if (msdu_info->frm_type == dp_tx_frm_me) {
  1953. tx_desc->me_buffer =
  1954. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1955. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1956. }
  1957. if (is_cce_classified)
  1958. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1959. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1960. if (msdu_info->exception_fw) {
  1961. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1962. }
  1963. /*
  1964. * For frames with multiple segments (TSO, ME), jump to next
  1965. * segment.
  1966. */
  1967. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1968. if (msdu_info->u.tso_info.curr_seg->next) {
  1969. msdu_info->u.tso_info.curr_seg =
  1970. msdu_info->u.tso_info.curr_seg->next;
  1971. /*
  1972. * If this is a jumbo nbuf, then increment the
  1973. * number of nbuf users for each additional
  1974. * segment of the msdu. This will ensure that
  1975. * the skb is freed only after receiving tx
  1976. * completion for all segments of an nbuf
  1977. */
  1978. qdf_nbuf_inc_users(nbuf);
  1979. /* Check with MCL if this is needed */
  1980. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  1981. */
  1982. }
  1983. }
  1984. /*
  1985. * Enqueue the Tx MSDU descriptor to HW for transmit
  1986. */
  1987. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1988. NULL, msdu_info);
  1989. if (status != QDF_STATUS_SUCCESS) {
  1990. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1991. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1992. __func__, tx_desc, tx_q->ring_id);
  1993. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1994. tid_stats = &pdev->stats.tid_stats.
  1995. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1996. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1997. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1998. if (msdu_info->frm_type == dp_tx_frm_me) {
  1999. hw_enq_fail++;
  2000. if (hw_enq_fail == msdu_info->num_seg) {
  2001. /*
  2002. * Unmap is needed only if enqueue
  2003. * failed for all segments.
  2004. */
  2005. qdf_nbuf_unmap(soc->osdev,
  2006. msdu_info->u.sg_info.
  2007. curr_seg->nbuf,
  2008. QDF_DMA_TO_DEVICE);
  2009. }
  2010. /*
  2011. * Free the nbuf for the current segment
  2012. * and make it point to the next in the list.
  2013. * For me, there are as many segments as there
  2014. * are no of clients.
  2015. */
  2016. qdf_nbuf_free(msdu_info->u.sg_info
  2017. .curr_seg->nbuf);
  2018. if (msdu_info->u.sg_info.curr_seg->next) {
  2019. msdu_info->u.sg_info.curr_seg =
  2020. msdu_info->u.sg_info
  2021. .curr_seg->next;
  2022. nbuf = msdu_info->u.sg_info
  2023. .curr_seg->nbuf;
  2024. }
  2025. i++;
  2026. continue;
  2027. }
  2028. /*
  2029. * For TSO frames, the nbuf users increment done for
  2030. * the current segment has to be reverted, since the
  2031. * hw enqueue for this segment failed
  2032. */
  2033. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2034. msdu_info->u.tso_info.curr_seg) {
  2035. /*
  2036. * unmap and free current,
  2037. * retransmit remaining segments
  2038. */
  2039. dp_tx_comp_free_buf(soc, tx_desc);
  2040. i++;
  2041. continue;
  2042. }
  2043. goto done;
  2044. }
  2045. /*
  2046. * TODO
  2047. * if tso_info structure can be modified to have curr_seg
  2048. * as first element, following 2 blocks of code (for TSO and SG)
  2049. * can be combined into 1
  2050. */
  2051. /*
  2052. * For Multicast-Unicast converted packets,
  2053. * each converted frame (for a client) is represented as
  2054. * 1 segment
  2055. */
  2056. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2057. (msdu_info->frm_type == dp_tx_frm_me)) {
  2058. if (msdu_info->u.sg_info.curr_seg->next) {
  2059. msdu_info->u.sg_info.curr_seg =
  2060. msdu_info->u.sg_info.curr_seg->next;
  2061. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2062. }
  2063. }
  2064. i++;
  2065. }
  2066. nbuf = NULL;
  2067. done:
  2068. return nbuf;
  2069. }
  2070. /**
  2071. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2072. * for SG frames
  2073. * @vdev: DP vdev handle
  2074. * @nbuf: skb
  2075. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2076. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2077. *
  2078. * Return: NULL on success,
  2079. * nbuf when it fails to send
  2080. */
  2081. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2082. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2083. {
  2084. uint32_t cur_frag, nr_frags, i;
  2085. qdf_dma_addr_t paddr;
  2086. struct dp_tx_sg_info_s *sg_info;
  2087. sg_info = &msdu_info->u.sg_info;
  2088. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2089. if (QDF_STATUS_SUCCESS !=
  2090. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2091. QDF_DMA_TO_DEVICE,
  2092. qdf_nbuf_headlen(nbuf))) {
  2093. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2094. "dma map error");
  2095. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2096. qdf_nbuf_free(nbuf);
  2097. return NULL;
  2098. }
  2099. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2100. seg_info->frags[0].paddr_lo = paddr;
  2101. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2102. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2103. seg_info->frags[0].vaddr = (void *) nbuf;
  2104. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2105. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2106. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2108. "frag dma map error");
  2109. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2110. goto map_err;
  2111. }
  2112. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2113. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2114. seg_info->frags[cur_frag + 1].paddr_hi =
  2115. ((uint64_t) paddr) >> 32;
  2116. seg_info->frags[cur_frag + 1].len =
  2117. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2118. }
  2119. seg_info->frag_cnt = (cur_frag + 1);
  2120. seg_info->total_len = qdf_nbuf_len(nbuf);
  2121. seg_info->next = NULL;
  2122. sg_info->curr_seg = seg_info;
  2123. msdu_info->frm_type = dp_tx_frm_sg;
  2124. msdu_info->num_seg = 1;
  2125. return nbuf;
  2126. map_err:
  2127. /* restore paddr into nbuf before calling unmap */
  2128. qdf_nbuf_mapped_paddr_set(nbuf,
  2129. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2130. ((uint64_t)
  2131. seg_info->frags[0].paddr_hi) << 32));
  2132. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2133. QDF_DMA_TO_DEVICE,
  2134. seg_info->frags[0].len);
  2135. for (i = 1; i <= cur_frag; i++) {
  2136. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2137. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2138. seg_info->frags[i].paddr_hi) << 32),
  2139. seg_info->frags[i].len,
  2140. QDF_DMA_TO_DEVICE);
  2141. }
  2142. qdf_nbuf_free(nbuf);
  2143. return NULL;
  2144. }
  2145. /**
  2146. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2147. * @vdev: DP vdev handle
  2148. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2149. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2150. *
  2151. * Return: NULL on failure,
  2152. * nbuf when extracted successfully
  2153. */
  2154. static
  2155. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2156. struct dp_tx_msdu_info_s *msdu_info,
  2157. uint16_t ppdu_cookie)
  2158. {
  2159. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2160. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2161. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2162. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2163. (msdu_info->meta_data[5], 1);
  2164. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2165. (msdu_info->meta_data[5], 1);
  2166. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2167. (msdu_info->meta_data[6], ppdu_cookie);
  2168. msdu_info->exception_fw = 1;
  2169. msdu_info->is_tx_sniffer = 1;
  2170. }
  2171. #ifdef MESH_MODE_SUPPORT
  2172. /**
  2173. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2174. and prepare msdu_info for mesh frames.
  2175. * @vdev: DP vdev handle
  2176. * @nbuf: skb
  2177. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2178. *
  2179. * Return: NULL on failure,
  2180. * nbuf when extracted successfully
  2181. */
  2182. static
  2183. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2184. struct dp_tx_msdu_info_s *msdu_info)
  2185. {
  2186. struct meta_hdr_s *mhdr;
  2187. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2188. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2189. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2190. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2191. msdu_info->exception_fw = 0;
  2192. goto remove_meta_hdr;
  2193. }
  2194. msdu_info->exception_fw = 1;
  2195. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2196. meta_data->host_tx_desc_pool = 1;
  2197. meta_data->update_peer_cache = 1;
  2198. meta_data->learning_frame = 1;
  2199. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2200. meta_data->power = mhdr->power;
  2201. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2202. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2203. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2204. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2205. meta_data->dyn_bw = 1;
  2206. meta_data->valid_pwr = 1;
  2207. meta_data->valid_mcs_mask = 1;
  2208. meta_data->valid_nss_mask = 1;
  2209. meta_data->valid_preamble_type = 1;
  2210. meta_data->valid_retries = 1;
  2211. meta_data->valid_bw_info = 1;
  2212. }
  2213. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2214. meta_data->encrypt_type = 0;
  2215. meta_data->valid_encrypt_type = 1;
  2216. meta_data->learning_frame = 0;
  2217. }
  2218. meta_data->valid_key_flags = 1;
  2219. meta_data->key_flags = (mhdr->keyix & 0x3);
  2220. remove_meta_hdr:
  2221. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2222. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2223. "qdf_nbuf_pull_head failed");
  2224. qdf_nbuf_free(nbuf);
  2225. return NULL;
  2226. }
  2227. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2228. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2229. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  2230. " tid %d to_fw %d",
  2231. __func__, msdu_info->meta_data[0],
  2232. msdu_info->meta_data[1],
  2233. msdu_info->meta_data[2],
  2234. msdu_info->meta_data[3],
  2235. msdu_info->meta_data[4],
  2236. msdu_info->meta_data[5],
  2237. msdu_info->tid, msdu_info->exception_fw);
  2238. return nbuf;
  2239. }
  2240. #else
  2241. static
  2242. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2243. struct dp_tx_msdu_info_s *msdu_info)
  2244. {
  2245. return nbuf;
  2246. }
  2247. #endif
  2248. /**
  2249. * dp_check_exc_metadata() - Checks if parameters are valid
  2250. * @tx_exc - holds all exception path parameters
  2251. *
  2252. * Returns true when all the parameters are valid else false
  2253. *
  2254. */
  2255. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2256. {
  2257. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  2258. HTT_INVALID_TID);
  2259. bool invalid_encap_type =
  2260. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2261. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2262. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2263. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2264. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2265. tx_exc->ppdu_cookie == 0);
  2266. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2267. invalid_cookie) {
  2268. return false;
  2269. }
  2270. return true;
  2271. }
  2272. #ifdef ATH_SUPPORT_IQUE
  2273. /**
  2274. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2275. * @vdev: vdev handle
  2276. * @nbuf: skb
  2277. *
  2278. * Return: true on success,
  2279. * false on failure
  2280. */
  2281. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2282. {
  2283. qdf_ether_header_t *eh;
  2284. /* Mcast to Ucast Conversion*/
  2285. if (qdf_likely(!vdev->mcast_enhancement_en))
  2286. return true;
  2287. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2288. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2289. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2290. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2291. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2292. qdf_nbuf_len(nbuf));
  2293. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2294. QDF_STATUS_SUCCESS) {
  2295. return false;
  2296. }
  2297. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2298. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2299. QDF_STATUS_SUCCESS) {
  2300. return false;
  2301. }
  2302. }
  2303. }
  2304. return true;
  2305. }
  2306. #else
  2307. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2308. {
  2309. return true;
  2310. }
  2311. #endif
  2312. /**
  2313. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2314. * @nbuf: qdf_nbuf_t
  2315. * @vdev: struct dp_vdev *
  2316. *
  2317. * Allow packet for processing only if it is for peer client which is
  2318. * connected with same vap. Drop packet if client is connected to
  2319. * different vap.
  2320. *
  2321. * Return: QDF_STATUS
  2322. */
  2323. static inline QDF_STATUS
  2324. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2325. {
  2326. struct dp_ast_entry *dst_ast_entry = NULL;
  2327. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2328. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2329. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2330. return QDF_STATUS_SUCCESS;
  2331. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2332. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2333. eh->ether_dhost,
  2334. vdev->vdev_id);
  2335. /* If there is no ast entry, return failure */
  2336. if (qdf_unlikely(!dst_ast_entry)) {
  2337. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2338. return QDF_STATUS_E_FAILURE;
  2339. }
  2340. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2341. return QDF_STATUS_SUCCESS;
  2342. }
  2343. /**
  2344. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2345. * @soc: DP soc handle
  2346. * @vdev_id: id of DP vdev handle
  2347. * @nbuf: skb
  2348. * @tx_exc_metadata: Handle that holds exception path meta data
  2349. *
  2350. * Entry point for Core Tx layer (DP_TX) invoked from
  2351. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2352. *
  2353. * Return: NULL on success,
  2354. * nbuf when it fails to send
  2355. */
  2356. qdf_nbuf_t
  2357. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2358. qdf_nbuf_t nbuf,
  2359. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2360. {
  2361. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2362. qdf_ether_header_t *eh = NULL;
  2363. struct dp_tx_msdu_info_s msdu_info;
  2364. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2365. DP_MOD_ID_TX_EXCEPTION);
  2366. if (qdf_unlikely(!vdev))
  2367. goto fail;
  2368. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2369. if (!tx_exc_metadata)
  2370. goto fail;
  2371. msdu_info.tid = tx_exc_metadata->tid;
  2372. dp_tx_wds_ext(soc, vdev, tx_exc_metadata->peer_id, &msdu_info);
  2373. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2374. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2375. QDF_MAC_ADDR_REF(nbuf->data));
  2376. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2377. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2378. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2379. "Invalid parameters in exception path");
  2380. goto fail;
  2381. }
  2382. /* Basic sanity checks for unsupported packets */
  2383. /* MESH mode */
  2384. if (qdf_unlikely(vdev->mesh_vdev)) {
  2385. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2386. "Mesh mode is not supported in exception path");
  2387. goto fail;
  2388. }
  2389. /*
  2390. * Classify the frame and call corresponding
  2391. * "prepare" function which extracts the segment (TSO)
  2392. * and fragmentation information (for TSO , SG, ME, or Raw)
  2393. * into MSDU_INFO structure which is later used to fill
  2394. * SW and HW descriptors.
  2395. */
  2396. if (qdf_nbuf_is_tso(nbuf)) {
  2397. dp_verbose_debug("TSO frame %pK", vdev);
  2398. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2399. qdf_nbuf_len(nbuf));
  2400. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2401. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2402. qdf_nbuf_len(nbuf));
  2403. return nbuf;
  2404. }
  2405. goto send_multiple;
  2406. }
  2407. /* SG */
  2408. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2409. struct dp_tx_seg_info_s seg_info = {0};
  2410. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2411. if (!nbuf)
  2412. return NULL;
  2413. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2414. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2415. qdf_nbuf_len(nbuf));
  2416. goto send_multiple;
  2417. }
  2418. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2419. return NULL;
  2420. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2421. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2422. qdf_nbuf_len(nbuf));
  2423. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2424. tx_exc_metadata->ppdu_cookie);
  2425. }
  2426. /*
  2427. * Get HW Queue to use for this frame.
  2428. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2429. * dedicated for data and 1 for command.
  2430. * "queue_id" maps to one hardware ring.
  2431. * With each ring, we also associate a unique Tx descriptor pool
  2432. * to minimize lock contention for these resources.
  2433. */
  2434. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2435. /*
  2436. * Check exception descriptors
  2437. */
  2438. if (dp_tx_exception_limit_check(vdev))
  2439. goto fail;
  2440. /* Single linear frame */
  2441. /*
  2442. * If nbuf is a simple linear frame, use send_single function to
  2443. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2444. * SRNG. There is no need to setup a MSDU extension descriptor.
  2445. */
  2446. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2447. tx_exc_metadata->peer_id, tx_exc_metadata);
  2448. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2449. return nbuf;
  2450. send_multiple:
  2451. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2452. fail:
  2453. if (vdev)
  2454. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2455. dp_verbose_debug("pkt send failed");
  2456. return nbuf;
  2457. }
  2458. /**
  2459. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2460. * in exception path in special case to avoid regular exception path chk.
  2461. * @soc: DP soc handle
  2462. * @vdev_id: id of DP vdev handle
  2463. * @nbuf: skb
  2464. * @tx_exc_metadata: Handle that holds exception path meta data
  2465. *
  2466. * Entry point for Core Tx layer (DP_TX) invoked from
  2467. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2468. *
  2469. * Return: NULL on success,
  2470. * nbuf when it fails to send
  2471. */
  2472. qdf_nbuf_t
  2473. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2474. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2475. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2476. {
  2477. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2478. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2479. DP_MOD_ID_TX_EXCEPTION);
  2480. if (qdf_unlikely(!vdev))
  2481. goto fail;
  2482. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2483. == QDF_STATUS_E_FAILURE)) {
  2484. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2485. goto fail;
  2486. }
  2487. /* Unref count as it will agin be taken inside dp_tx_exception */
  2488. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2489. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2490. fail:
  2491. if (vdev)
  2492. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2493. dp_verbose_debug("pkt send failed");
  2494. return nbuf;
  2495. }
  2496. /**
  2497. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2498. * @soc: DP soc handle
  2499. * @vdev_id: DP vdev handle
  2500. * @nbuf: skb
  2501. *
  2502. * Entry point for Core Tx layer (DP_TX) invoked from
  2503. * hard_start_xmit in OSIF/HDD
  2504. *
  2505. * Return: NULL on success,
  2506. * nbuf when it fails to send
  2507. */
  2508. #ifdef MESH_MODE_SUPPORT
  2509. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2510. qdf_nbuf_t nbuf)
  2511. {
  2512. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2513. struct meta_hdr_s *mhdr;
  2514. qdf_nbuf_t nbuf_mesh = NULL;
  2515. qdf_nbuf_t nbuf_clone = NULL;
  2516. struct dp_vdev *vdev;
  2517. uint8_t no_enc_frame = 0;
  2518. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2519. if (!nbuf_mesh) {
  2520. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2521. "qdf_nbuf_unshare failed");
  2522. return nbuf;
  2523. }
  2524. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2525. if (!vdev) {
  2526. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2527. "vdev is NULL for vdev_id %d", vdev_id);
  2528. return nbuf;
  2529. }
  2530. nbuf = nbuf_mesh;
  2531. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2532. if ((vdev->sec_type != cdp_sec_type_none) &&
  2533. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2534. no_enc_frame = 1;
  2535. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2536. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2537. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2538. !no_enc_frame) {
  2539. nbuf_clone = qdf_nbuf_clone(nbuf);
  2540. if (!nbuf_clone) {
  2541. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2542. "qdf_nbuf_clone failed");
  2543. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2544. return nbuf;
  2545. }
  2546. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2547. }
  2548. if (nbuf_clone) {
  2549. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2550. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2551. } else {
  2552. qdf_nbuf_free(nbuf_clone);
  2553. }
  2554. }
  2555. if (no_enc_frame)
  2556. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2557. else
  2558. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2559. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2560. if ((!nbuf) && no_enc_frame) {
  2561. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2562. }
  2563. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2564. return nbuf;
  2565. }
  2566. #else
  2567. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2568. qdf_nbuf_t nbuf)
  2569. {
  2570. return dp_tx_send(soc, vdev_id, nbuf);
  2571. }
  2572. #endif
  2573. /**
  2574. * dp_tx_nawds_handler() - NAWDS handler
  2575. *
  2576. * @soc: DP soc handle
  2577. * @vdev_id: id of DP vdev handle
  2578. * @msdu_info: msdu_info required to create HTT metadata
  2579. * @nbuf: skb
  2580. *
  2581. * This API transfers the multicast frames with the peer id
  2582. * on NAWDS enabled peer.
  2583. * Return: none
  2584. */
  2585. static inline
  2586. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2587. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2588. {
  2589. struct dp_peer *peer = NULL;
  2590. qdf_nbuf_t nbuf_clone = NULL;
  2591. uint16_t peer_id = DP_INVALID_PEER;
  2592. uint16_t sa_peer_id = DP_INVALID_PEER;
  2593. struct dp_ast_entry *ast_entry = NULL;
  2594. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2595. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2596. qdf_spin_lock_bh(&soc->ast_lock);
  2597. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2598. (soc,
  2599. (uint8_t *)(eh->ether_shost),
  2600. vdev->pdev->pdev_id);
  2601. if (ast_entry)
  2602. sa_peer_id = ast_entry->peer_id;
  2603. qdf_spin_unlock_bh(&soc->ast_lock);
  2604. }
  2605. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2606. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2607. if (!peer->bss_peer && peer->nawds_enabled) {
  2608. peer_id = peer->peer_id;
  2609. /* Multicast packets needs to be
  2610. * dropped in case of intra bss forwarding
  2611. */
  2612. if (sa_peer_id == peer->peer_id) {
  2613. QDF_TRACE(QDF_MODULE_ID_DP,
  2614. QDF_TRACE_LEVEL_DEBUG,
  2615. " %s: multicast packet", __func__);
  2616. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2617. continue;
  2618. }
  2619. nbuf_clone = qdf_nbuf_clone(nbuf);
  2620. if (!nbuf_clone) {
  2621. QDF_TRACE(QDF_MODULE_ID_DP,
  2622. QDF_TRACE_LEVEL_ERROR,
  2623. FL("nbuf clone failed"));
  2624. break;
  2625. }
  2626. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2627. msdu_info, peer_id,
  2628. NULL);
  2629. if (nbuf_clone) {
  2630. QDF_TRACE(QDF_MODULE_ID_DP,
  2631. QDF_TRACE_LEVEL_DEBUG,
  2632. FL("pkt send failed"));
  2633. qdf_nbuf_free(nbuf_clone);
  2634. } else {
  2635. if (peer_id != DP_INVALID_PEER)
  2636. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2637. 1, qdf_nbuf_len(nbuf));
  2638. }
  2639. }
  2640. }
  2641. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2642. }
  2643. /**
  2644. * dp_tx_send() - Transmit a frame on a given VAP
  2645. * @soc: DP soc handle
  2646. * @vdev_id: id of DP vdev handle
  2647. * @nbuf: skb
  2648. *
  2649. * Entry point for Core Tx layer (DP_TX) invoked from
  2650. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2651. * cases
  2652. *
  2653. * Return: NULL on success,
  2654. * nbuf when it fails to send
  2655. */
  2656. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2657. qdf_nbuf_t nbuf)
  2658. {
  2659. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2660. uint16_t peer_id = HTT_INVALID_PEER;
  2661. /*
  2662. * doing a memzero is causing additional function call overhead
  2663. * so doing static stack clearing
  2664. */
  2665. struct dp_tx_msdu_info_s msdu_info = {0};
  2666. struct dp_vdev *vdev = NULL;
  2667. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2668. return nbuf;
  2669. /*
  2670. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2671. * this in per packet path.
  2672. *
  2673. * As in this path vdev memory is already protected with netdev
  2674. * tx lock
  2675. */
  2676. vdev = soc->vdev_id_map[vdev_id];
  2677. if (qdf_unlikely(!vdev))
  2678. return nbuf;
  2679. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2680. QDF_MAC_ADDR_REF(nbuf->data));
  2681. /*
  2682. * Set Default Host TID value to invalid TID
  2683. * (TID override disabled)
  2684. */
  2685. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2686. dp_tx_wds_ext(soc, vdev, peer_id, &msdu_info);
  2687. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2688. if (qdf_unlikely(vdev->mesh_vdev)) {
  2689. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2690. &msdu_info);
  2691. if (!nbuf_mesh) {
  2692. dp_verbose_debug("Extracting mesh metadata failed");
  2693. return nbuf;
  2694. }
  2695. nbuf = nbuf_mesh;
  2696. }
  2697. /*
  2698. * Get HW Queue to use for this frame.
  2699. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2700. * dedicated for data and 1 for command.
  2701. * "queue_id" maps to one hardware ring.
  2702. * With each ring, we also associate a unique Tx descriptor pool
  2703. * to minimize lock contention for these resources.
  2704. */
  2705. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2706. /*
  2707. * TCL H/W supports 2 DSCP-TID mapping tables.
  2708. * Table 1 - Default DSCP-TID mapping table
  2709. * Table 2 - 1 DSCP-TID override table
  2710. *
  2711. * If we need a different DSCP-TID mapping for this vap,
  2712. * call tid_classify to extract DSCP/ToS from frame and
  2713. * map to a TID and store in msdu_info. This is later used
  2714. * to fill in TCL Input descriptor (per-packet TID override).
  2715. */
  2716. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2717. /*
  2718. * Classify the frame and call corresponding
  2719. * "prepare" function which extracts the segment (TSO)
  2720. * and fragmentation information (for TSO , SG, ME, or Raw)
  2721. * into MSDU_INFO structure which is later used to fill
  2722. * SW and HW descriptors.
  2723. */
  2724. if (qdf_nbuf_is_tso(nbuf)) {
  2725. dp_verbose_debug("TSO frame %pK", vdev);
  2726. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2727. qdf_nbuf_len(nbuf));
  2728. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2729. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2730. qdf_nbuf_len(nbuf));
  2731. return nbuf;
  2732. }
  2733. goto send_multiple;
  2734. }
  2735. /* SG */
  2736. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2737. struct dp_tx_seg_info_s seg_info = {0};
  2738. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2739. if (!nbuf)
  2740. return NULL;
  2741. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2742. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2743. qdf_nbuf_len(nbuf));
  2744. goto send_multiple;
  2745. }
  2746. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2747. return NULL;
  2748. /* RAW */
  2749. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2750. struct dp_tx_seg_info_s seg_info = {0};
  2751. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2752. if (!nbuf)
  2753. return NULL;
  2754. dp_verbose_debug("Raw frame %pK", vdev);
  2755. goto send_multiple;
  2756. }
  2757. if (qdf_unlikely(vdev->nawds_enabled)) {
  2758. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2759. qdf_nbuf_data(nbuf);
  2760. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2761. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2762. peer_id = DP_INVALID_PEER;
  2763. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2764. 1, qdf_nbuf_len(nbuf));
  2765. }
  2766. /* Single linear frame */
  2767. /*
  2768. * If nbuf is a simple linear frame, use send_single function to
  2769. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2770. * SRNG. There is no need to setup a MSDU extension descriptor.
  2771. */
  2772. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2773. return nbuf;
  2774. send_multiple:
  2775. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2776. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2777. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2778. return nbuf;
  2779. }
  2780. /**
  2781. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2782. * case to vaoid check in perpkt path.
  2783. * @soc: DP soc handle
  2784. * @vdev_id: id of DP vdev handle
  2785. * @nbuf: skb
  2786. *
  2787. * Entry point for Core Tx layer (DP_TX) invoked from
  2788. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2789. * with special condition to avoid per pkt check in dp_tx_send
  2790. *
  2791. * Return: NULL on success,
  2792. * nbuf when it fails to send
  2793. */
  2794. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2795. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2796. {
  2797. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2798. struct dp_vdev *vdev = NULL;
  2799. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2800. return nbuf;
  2801. /*
  2802. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2803. * this in per packet path.
  2804. *
  2805. * As in this path vdev memory is already protected with netdev
  2806. * tx lock
  2807. */
  2808. vdev = soc->vdev_id_map[vdev_id];
  2809. if (qdf_unlikely(!vdev))
  2810. return nbuf;
  2811. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2812. == QDF_STATUS_E_FAILURE)) {
  2813. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2814. return nbuf;
  2815. }
  2816. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2817. }
  2818. /**
  2819. * dp_tx_reinject_handler() - Tx Reinject Handler
  2820. * @soc: datapath soc handle
  2821. * @vdev: datapath vdev handle
  2822. * @tx_desc: software descriptor head pointer
  2823. * @status : Tx completion status from HTT descriptor
  2824. *
  2825. * This function reinjects frames back to Target.
  2826. * Todo - Host queue needs to be added
  2827. *
  2828. * Return: none
  2829. */
  2830. static
  2831. void dp_tx_reinject_handler(struct dp_soc *soc,
  2832. struct dp_vdev *vdev,
  2833. struct dp_tx_desc_s *tx_desc,
  2834. uint8_t *status)
  2835. {
  2836. struct dp_peer *peer = NULL;
  2837. uint32_t peer_id = HTT_INVALID_PEER;
  2838. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2839. qdf_nbuf_t nbuf_copy = NULL;
  2840. struct dp_tx_msdu_info_s msdu_info;
  2841. #ifdef WDS_VENDOR_EXTENSION
  2842. int is_mcast = 0, is_ucast = 0;
  2843. int num_peers_3addr = 0;
  2844. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2845. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2846. #endif
  2847. qdf_assert(vdev);
  2848. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2849. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2850. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2851. "%s Tx reinject path", __func__);
  2852. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2853. qdf_nbuf_len(tx_desc->nbuf));
  2854. #ifdef WDS_VENDOR_EXTENSION
  2855. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2856. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2857. } else {
  2858. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2859. }
  2860. is_ucast = !is_mcast;
  2861. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2862. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2863. if (peer->bss_peer)
  2864. continue;
  2865. /* Detect wds peers that use 3-addr framing for mcast.
  2866. * if there are any, the bss_peer is used to send the
  2867. * the mcast frame using 3-addr format. all wds enabled
  2868. * peers that use 4-addr framing for mcast frames will
  2869. * be duplicated and sent as 4-addr frames below.
  2870. */
  2871. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2872. num_peers_3addr = 1;
  2873. break;
  2874. }
  2875. }
  2876. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2877. #endif
  2878. if (qdf_unlikely(vdev->mesh_vdev)) {
  2879. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2880. } else {
  2881. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2882. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2883. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2884. #ifdef WDS_VENDOR_EXTENSION
  2885. /*
  2886. * . if 3-addr STA, then send on BSS Peer
  2887. * . if Peer WDS enabled and accept 4-addr mcast,
  2888. * send mcast on that peer only
  2889. * . if Peer WDS enabled and accept 4-addr ucast,
  2890. * send ucast on that peer only
  2891. */
  2892. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2893. (peer->wds_enabled &&
  2894. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2895. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2896. #else
  2897. ((peer->bss_peer &&
  2898. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2899. #endif
  2900. peer_id = DP_INVALID_PEER;
  2901. nbuf_copy = qdf_nbuf_copy(nbuf);
  2902. if (!nbuf_copy) {
  2903. QDF_TRACE(QDF_MODULE_ID_DP,
  2904. QDF_TRACE_LEVEL_DEBUG,
  2905. FL("nbuf copy failed"));
  2906. break;
  2907. }
  2908. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2909. nbuf_copy,
  2910. &msdu_info,
  2911. peer_id,
  2912. NULL);
  2913. if (nbuf_copy) {
  2914. QDF_TRACE(QDF_MODULE_ID_DP,
  2915. QDF_TRACE_LEVEL_DEBUG,
  2916. FL("pkt send failed"));
  2917. qdf_nbuf_free(nbuf_copy);
  2918. }
  2919. }
  2920. }
  2921. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2922. }
  2923. qdf_nbuf_free(nbuf);
  2924. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2925. }
  2926. /**
  2927. * dp_tx_inspect_handler() - Tx Inspect Handler
  2928. * @soc: datapath soc handle
  2929. * @vdev: datapath vdev handle
  2930. * @tx_desc: software descriptor head pointer
  2931. * @status : Tx completion status from HTT descriptor
  2932. *
  2933. * Handles Tx frames sent back to Host for inspection
  2934. * (ProxyARP)
  2935. *
  2936. * Return: none
  2937. */
  2938. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2939. struct dp_vdev *vdev,
  2940. struct dp_tx_desc_s *tx_desc,
  2941. uint8_t *status)
  2942. {
  2943. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2944. "%s Tx inspect path",
  2945. __func__);
  2946. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2947. qdf_nbuf_len(tx_desc->nbuf));
  2948. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2949. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2950. }
  2951. #ifdef FEATURE_PERPKT_INFO
  2952. /**
  2953. * dp_get_completion_indication_for_stack() - send completion to stack
  2954. * @soc : dp_soc handle
  2955. * @pdev: dp_pdev handle
  2956. * @peer: dp peer handle
  2957. * @ts: transmit completion status structure
  2958. * @netbuf: Buffer pointer for free
  2959. *
  2960. * This function is used for indication whether buffer needs to be
  2961. * sent to stack for freeing or not
  2962. */
  2963. QDF_STATUS
  2964. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2965. struct dp_pdev *pdev,
  2966. struct dp_peer *peer,
  2967. struct hal_tx_completion_status *ts,
  2968. qdf_nbuf_t netbuf,
  2969. uint64_t time_latency)
  2970. {
  2971. struct tx_capture_hdr *ppdu_hdr;
  2972. uint16_t peer_id = ts->peer_id;
  2973. uint32_t ppdu_id = ts->ppdu_id;
  2974. uint8_t first_msdu = ts->first_msdu;
  2975. uint8_t last_msdu = ts->last_msdu;
  2976. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2977. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2978. !pdev->latency_capture_enable))
  2979. return QDF_STATUS_E_NOSUPPORT;
  2980. if (!peer) {
  2981. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2982. FL("Peer Invalid"));
  2983. return QDF_STATUS_E_INVAL;
  2984. }
  2985. if (pdev->mcopy_mode) {
  2986. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2987. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2988. * for each MPDU
  2989. */
  2990. if (pdev->mcopy_mode == M_COPY) {
  2991. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2992. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2993. return QDF_STATUS_E_INVAL;
  2994. }
  2995. }
  2996. if (!first_msdu)
  2997. return QDF_STATUS_E_INVAL;
  2998. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2999. pdev->m_copy_id.tx_peer_id = peer_id;
  3000. }
  3001. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  3002. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  3003. if (!netbuf) {
  3004. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3005. FL("No headroom"));
  3006. return QDF_STATUS_E_NOMEM;
  3007. }
  3008. }
  3009. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  3010. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3011. FL("No headroom"));
  3012. return QDF_STATUS_E_NOMEM;
  3013. }
  3014. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  3015. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  3016. QDF_MAC_ADDR_SIZE);
  3017. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  3018. QDF_MAC_ADDR_SIZE);
  3019. ppdu_hdr->ppdu_id = ppdu_id;
  3020. ppdu_hdr->peer_id = peer_id;
  3021. ppdu_hdr->first_msdu = first_msdu;
  3022. ppdu_hdr->last_msdu = last_msdu;
  3023. if (qdf_unlikely(pdev->latency_capture_enable)) {
  3024. ppdu_hdr->tsf = ts->tsf;
  3025. ppdu_hdr->time_latency = time_latency;
  3026. }
  3027. return QDF_STATUS_SUCCESS;
  3028. }
  3029. /**
  3030. * dp_send_completion_to_stack() - send completion to stack
  3031. * @soc : dp_soc handle
  3032. * @pdev: dp_pdev handle
  3033. * @peer_id: peer_id of the peer for which completion came
  3034. * @ppdu_id: ppdu_id
  3035. * @netbuf: Buffer pointer for free
  3036. *
  3037. * This function is used to send completion to stack
  3038. * to free buffer
  3039. */
  3040. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  3041. uint16_t peer_id, uint32_t ppdu_id,
  3042. qdf_nbuf_t netbuf)
  3043. {
  3044. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  3045. netbuf, peer_id,
  3046. WDI_NO_VAL, pdev->pdev_id);
  3047. }
  3048. #else
  3049. static QDF_STATUS
  3050. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  3051. struct dp_pdev *pdev,
  3052. struct dp_peer *peer,
  3053. struct hal_tx_completion_status *ts,
  3054. qdf_nbuf_t netbuf,
  3055. uint64_t time_latency)
  3056. {
  3057. return QDF_STATUS_E_NOSUPPORT;
  3058. }
  3059. static void
  3060. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  3061. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  3062. {
  3063. }
  3064. #endif
  3065. #ifdef MESH_MODE_SUPPORT
  3066. /**
  3067. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3068. * in mesh meta header
  3069. * @tx_desc: software descriptor head pointer
  3070. * @ts: pointer to tx completion stats
  3071. * Return: none
  3072. */
  3073. static
  3074. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3075. struct hal_tx_completion_status *ts)
  3076. {
  3077. struct meta_hdr_s *mhdr;
  3078. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3079. if (!tx_desc->msdu_ext_desc) {
  3080. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3081. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3082. "netbuf %pK offset %d",
  3083. netbuf, tx_desc->pkt_offset);
  3084. return;
  3085. }
  3086. }
  3087. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  3088. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3089. "netbuf %pK offset %lu", netbuf,
  3090. sizeof(struct meta_hdr_s));
  3091. return;
  3092. }
  3093. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  3094. mhdr->rssi = ts->ack_frame_rssi;
  3095. mhdr->band = tx_desc->pdev->operating_channel.band;
  3096. mhdr->channel = tx_desc->pdev->operating_channel.num;
  3097. }
  3098. #else
  3099. static
  3100. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3101. struct hal_tx_completion_status *ts)
  3102. {
  3103. }
  3104. #endif
  3105. #ifdef QCA_PEER_EXT_STATS
  3106. /*
  3107. * dp_tx_compute_tid_delay() - Compute per TID delay
  3108. * @stats: Per TID delay stats
  3109. * @tx_desc: Software Tx descriptor
  3110. *
  3111. * Compute the software enqueue and hw enqueue delays and
  3112. * update the respective histograms
  3113. *
  3114. * Return: void
  3115. */
  3116. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3117. struct dp_tx_desc_s *tx_desc)
  3118. {
  3119. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3120. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3121. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3122. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3123. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3124. timestamp_hw_enqueue = tx_desc->timestamp;
  3125. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3126. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3127. timestamp_hw_enqueue);
  3128. /*
  3129. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3130. */
  3131. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3132. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3133. }
  3134. /*
  3135. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3136. * @peer: DP peer context
  3137. * @tx_desc: Tx software descriptor
  3138. * @tid: Transmission ID
  3139. * @ring_id: Rx CPU context ID/CPU_ID
  3140. *
  3141. * Update the peer extended stats. These are enhanced other
  3142. * delay stats per msdu level.
  3143. *
  3144. * Return: void
  3145. */
  3146. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3147. struct dp_tx_desc_s *tx_desc,
  3148. uint8_t tid, uint8_t ring_id)
  3149. {
  3150. struct dp_pdev *pdev = peer->vdev->pdev;
  3151. struct dp_soc *soc = NULL;
  3152. struct cdp_peer_ext_stats *pext_stats = NULL;
  3153. soc = pdev->soc;
  3154. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3155. return;
  3156. pext_stats = peer->pext_stats;
  3157. qdf_assert(pext_stats);
  3158. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3159. /*
  3160. * For non-TID packets use the TID 9
  3161. */
  3162. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3163. tid = CDP_MAX_DATA_TIDS - 1;
  3164. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3165. tx_desc);
  3166. }
  3167. #else
  3168. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3169. struct dp_tx_desc_s *tx_desc,
  3170. uint8_t tid, uint8_t ring_id)
  3171. {
  3172. }
  3173. #endif
  3174. /**
  3175. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3176. * to pass in correct fields
  3177. *
  3178. * @vdev: pdev handle
  3179. * @tx_desc: tx descriptor
  3180. * @tid: tid value
  3181. * @ring_id: TCL or WBM ring number for transmit path
  3182. * Return: none
  3183. */
  3184. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3185. struct dp_tx_desc_s *tx_desc,
  3186. uint8_t tid, uint8_t ring_id)
  3187. {
  3188. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3189. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3190. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3191. return;
  3192. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3193. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3194. timestamp_hw_enqueue = tx_desc->timestamp;
  3195. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3196. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3197. timestamp_hw_enqueue);
  3198. interframe_delay = (uint32_t)(timestamp_ingress -
  3199. vdev->prev_tx_enq_tstamp);
  3200. /*
  3201. * Delay in software enqueue
  3202. */
  3203. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3204. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3205. /*
  3206. * Delay between packet enqueued to HW and Tx completion
  3207. */
  3208. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3209. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3210. /*
  3211. * Update interframe delay stats calculated at hardstart receive point.
  3212. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3213. * interframe delay will not be calculate correctly for 1st frame.
  3214. * On the other side, this will help in avoiding extra per packet check
  3215. * of !vdev->prev_tx_enq_tstamp.
  3216. */
  3217. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3218. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3219. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3220. }
  3221. #ifdef DISABLE_DP_STATS
  3222. static
  3223. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3224. {
  3225. }
  3226. #else
  3227. static
  3228. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3229. {
  3230. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3231. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3232. if (subtype != QDF_PROTO_INVALID)
  3233. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3234. }
  3235. #endif
  3236. /**
  3237. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3238. * per wbm ring
  3239. *
  3240. * @tx_desc: software descriptor head pointer
  3241. * @ts: Tx completion status
  3242. * @peer: peer handle
  3243. * @ring_id: ring number
  3244. *
  3245. * Return: None
  3246. */
  3247. static inline void
  3248. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3249. struct hal_tx_completion_status *ts,
  3250. struct dp_peer *peer, uint8_t ring_id)
  3251. {
  3252. struct dp_pdev *pdev = peer->vdev->pdev;
  3253. struct dp_soc *soc = NULL;
  3254. uint8_t mcs, pkt_type;
  3255. uint8_t tid = ts->tid;
  3256. uint32_t length;
  3257. struct cdp_tid_tx_stats *tid_stats;
  3258. if (!pdev)
  3259. return;
  3260. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3261. tid = CDP_MAX_DATA_TIDS - 1;
  3262. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3263. soc = pdev->soc;
  3264. mcs = ts->mcs;
  3265. pkt_type = ts->pkt_type;
  3266. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3267. dp_err("Release source is not from TQM");
  3268. return;
  3269. }
  3270. length = qdf_nbuf_len(tx_desc->nbuf);
  3271. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3272. if (qdf_unlikely(pdev->delay_stats_flag))
  3273. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3274. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3275. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3276. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3277. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3278. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3279. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3280. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3281. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3282. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3283. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3284. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3285. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3286. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3287. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3288. /*
  3289. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3290. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3291. * are no completions for failed cases. Hence updating tx_failed from
  3292. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3293. * then this has to be removed
  3294. */
  3295. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3296. peer->stats.tx.dropped.fw_rem_notx +
  3297. peer->stats.tx.dropped.fw_rem_tx +
  3298. peer->stats.tx.dropped.age_out +
  3299. peer->stats.tx.dropped.fw_reason1 +
  3300. peer->stats.tx.dropped.fw_reason2 +
  3301. peer->stats.tx.dropped.fw_reason3;
  3302. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3303. tid_stats->tqm_status_cnt[ts->status]++;
  3304. }
  3305. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3306. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3307. return;
  3308. }
  3309. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3310. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3311. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3312. /*
  3313. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3314. * Return from here if HTT PPDU events are enabled.
  3315. */
  3316. if (!(soc->process_tx_status))
  3317. return;
  3318. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3319. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3320. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3321. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3322. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3323. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3324. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3325. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3326. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3327. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3328. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3329. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3330. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3331. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3332. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3333. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3334. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3335. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3336. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3337. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3338. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3339. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3340. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3341. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3342. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3343. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3344. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3345. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3346. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3347. &peer->stats, ts->peer_id,
  3348. UPDATE_PEER_STATS, pdev->pdev_id);
  3349. #endif
  3350. }
  3351. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3352. /**
  3353. * dp_tx_flow_pool_lock() - take flow pool lock
  3354. * @soc: core txrx main context
  3355. * @tx_desc: tx desc
  3356. *
  3357. * Return: None
  3358. */
  3359. static inline
  3360. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3361. struct dp_tx_desc_s *tx_desc)
  3362. {
  3363. struct dp_tx_desc_pool_s *pool;
  3364. uint8_t desc_pool_id;
  3365. desc_pool_id = tx_desc->pool_id;
  3366. pool = &soc->tx_desc[desc_pool_id];
  3367. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3368. }
  3369. /**
  3370. * dp_tx_flow_pool_unlock() - release flow pool lock
  3371. * @soc: core txrx main context
  3372. * @tx_desc: tx desc
  3373. *
  3374. * Return: None
  3375. */
  3376. static inline
  3377. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3378. struct dp_tx_desc_s *tx_desc)
  3379. {
  3380. struct dp_tx_desc_pool_s *pool;
  3381. uint8_t desc_pool_id;
  3382. desc_pool_id = tx_desc->pool_id;
  3383. pool = &soc->tx_desc[desc_pool_id];
  3384. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3385. }
  3386. #else
  3387. static inline
  3388. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3389. {
  3390. }
  3391. static inline
  3392. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3393. {
  3394. }
  3395. #endif
  3396. /**
  3397. * dp_tx_notify_completion() - Notify tx completion for this desc
  3398. * @soc: core txrx main context
  3399. * @vdev: datapath vdev handle
  3400. * @tx_desc: tx desc
  3401. * @netbuf: buffer
  3402. * @status: tx status
  3403. *
  3404. * Return: none
  3405. */
  3406. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3407. struct dp_vdev *vdev,
  3408. struct dp_tx_desc_s *tx_desc,
  3409. qdf_nbuf_t netbuf,
  3410. uint8_t status)
  3411. {
  3412. void *osif_dev;
  3413. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3414. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3415. qdf_assert(tx_desc);
  3416. dp_tx_flow_pool_lock(soc, tx_desc);
  3417. if (!vdev ||
  3418. !vdev->osif_vdev) {
  3419. dp_tx_flow_pool_unlock(soc, tx_desc);
  3420. return;
  3421. }
  3422. osif_dev = vdev->osif_vdev;
  3423. tx_compl_cbk = vdev->tx_comp;
  3424. dp_tx_flow_pool_unlock(soc, tx_desc);
  3425. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3426. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3427. if (tx_compl_cbk)
  3428. tx_compl_cbk(netbuf, osif_dev, flag);
  3429. }
  3430. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3431. * @pdev: pdev handle
  3432. * @tid: tid value
  3433. * @txdesc_ts: timestamp from txdesc
  3434. * @ppdu_id: ppdu id
  3435. *
  3436. * Return: none
  3437. */
  3438. #ifdef FEATURE_PERPKT_INFO
  3439. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3440. struct dp_peer *peer,
  3441. uint8_t tid,
  3442. uint64_t txdesc_ts,
  3443. uint32_t ppdu_id)
  3444. {
  3445. uint64_t delta_ms;
  3446. struct cdp_tx_sojourn_stats *sojourn_stats;
  3447. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3448. return;
  3449. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3450. tid >= CDP_DATA_TID_MAX))
  3451. return;
  3452. if (qdf_unlikely(!pdev->sojourn_buf))
  3453. return;
  3454. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3455. qdf_nbuf_data(pdev->sojourn_buf);
  3456. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3457. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3458. txdesc_ts;
  3459. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3460. delta_ms);
  3461. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3462. sojourn_stats->num_msdus[tid] = 1;
  3463. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3464. peer->avg_sojourn_msdu[tid].internal;
  3465. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3466. pdev->sojourn_buf, HTT_INVALID_PEER,
  3467. WDI_NO_VAL, pdev->pdev_id);
  3468. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3469. sojourn_stats->num_msdus[tid] = 0;
  3470. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3471. }
  3472. #else
  3473. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3474. struct dp_peer *peer,
  3475. uint8_t tid,
  3476. uint64_t txdesc_ts,
  3477. uint32_t ppdu_id)
  3478. {
  3479. }
  3480. #endif
  3481. /**
  3482. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3483. * @soc: DP Soc handle
  3484. * @tx_desc: software Tx descriptor
  3485. * @ts : Tx completion status from HAL/HTT descriptor
  3486. *
  3487. * Return: none
  3488. */
  3489. static inline void
  3490. dp_tx_comp_process_desc(struct dp_soc *soc,
  3491. struct dp_tx_desc_s *desc,
  3492. struct hal_tx_completion_status *ts,
  3493. struct dp_peer *peer)
  3494. {
  3495. uint64_t time_latency = 0;
  3496. /*
  3497. * m_copy/tx_capture modes are not supported for
  3498. * scatter gather packets
  3499. */
  3500. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3501. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3502. desc->timestamp);
  3503. }
  3504. if (!(desc->msdu_ext_desc)) {
  3505. if (QDF_STATUS_SUCCESS ==
  3506. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3507. return;
  3508. }
  3509. if (QDF_STATUS_SUCCESS ==
  3510. dp_get_completion_indication_for_stack(soc,
  3511. desc->pdev,
  3512. peer, ts,
  3513. desc->nbuf,
  3514. time_latency)) {
  3515. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3516. QDF_DMA_TO_DEVICE,
  3517. desc->nbuf->len);
  3518. dp_send_completion_to_stack(soc,
  3519. desc->pdev,
  3520. ts->peer_id,
  3521. ts->ppdu_id,
  3522. desc->nbuf);
  3523. return;
  3524. }
  3525. }
  3526. dp_tx_comp_free_buf(soc, desc);
  3527. }
  3528. #ifdef DISABLE_DP_STATS
  3529. /**
  3530. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3531. * @soc: core txrx main context
  3532. * @tx_desc: tx desc
  3533. * @status: tx status
  3534. *
  3535. * Return: none
  3536. */
  3537. static inline
  3538. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3539. struct dp_vdev *vdev,
  3540. struct dp_tx_desc_s *tx_desc,
  3541. uint8_t status)
  3542. {
  3543. }
  3544. #else
  3545. static inline
  3546. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3547. struct dp_vdev *vdev,
  3548. struct dp_tx_desc_s *tx_desc,
  3549. uint8_t status)
  3550. {
  3551. void *osif_dev;
  3552. ol_txrx_stats_rx_fp stats_cbk;
  3553. uint8_t pkt_type;
  3554. qdf_assert(tx_desc);
  3555. if (!vdev ||
  3556. !vdev->osif_vdev ||
  3557. !vdev->stats_cb)
  3558. return;
  3559. osif_dev = vdev->osif_vdev;
  3560. stats_cbk = vdev->stats_cb;
  3561. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3562. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3563. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3564. &pkt_type);
  3565. }
  3566. #endif
  3567. /**
  3568. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3569. * @soc: DP soc handle
  3570. * @tx_desc: software descriptor head pointer
  3571. * @ts: Tx completion status
  3572. * @peer: peer handle
  3573. * @ring_id: ring number
  3574. *
  3575. * Return: none
  3576. */
  3577. static inline
  3578. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3579. struct dp_tx_desc_s *tx_desc,
  3580. struct hal_tx_completion_status *ts,
  3581. struct dp_peer *peer, uint8_t ring_id)
  3582. {
  3583. uint32_t length;
  3584. qdf_ether_header_t *eh;
  3585. struct dp_vdev *vdev = NULL;
  3586. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3587. uint8_t dp_status;
  3588. if (!nbuf) {
  3589. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3590. goto out;
  3591. }
  3592. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3593. length = qdf_nbuf_len(nbuf);
  3594. dp_status = qdf_dp_get_status_from_htt(ts->status);
  3595. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3596. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3597. QDF_TRACE_DEFAULT_PDEV_ID,
  3598. qdf_nbuf_data_addr(nbuf),
  3599. sizeof(qdf_nbuf_data(nbuf)),
  3600. tx_desc->id,
  3601. dp_status));
  3602. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3603. "-------------------- \n"
  3604. "Tx Completion Stats: \n"
  3605. "-------------------- \n"
  3606. "ack_frame_rssi = %d \n"
  3607. "first_msdu = %d \n"
  3608. "last_msdu = %d \n"
  3609. "msdu_part_of_amsdu = %d \n"
  3610. "rate_stats valid = %d \n"
  3611. "bw = %d \n"
  3612. "pkt_type = %d \n"
  3613. "stbc = %d \n"
  3614. "ldpc = %d \n"
  3615. "sgi = %d \n"
  3616. "mcs = %d \n"
  3617. "ofdma = %d \n"
  3618. "tones_in_ru = %d \n"
  3619. "tsf = %d \n"
  3620. "ppdu_id = %d \n"
  3621. "transmit_cnt = %d \n"
  3622. "tid = %d \n"
  3623. "peer_id = %d\n",
  3624. ts->ack_frame_rssi, ts->first_msdu,
  3625. ts->last_msdu, ts->msdu_part_of_amsdu,
  3626. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3627. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3628. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3629. ts->transmit_cnt, ts->tid, ts->peer_id);
  3630. /* Update SoC level stats */
  3631. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3632. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3633. if (!peer) {
  3634. dp_err_rl("peer is null or deletion in progress");
  3635. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3636. goto out;
  3637. }
  3638. vdev = peer->vdev;
  3639. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3640. /* Update per-packet stats for mesh mode */
  3641. if (qdf_unlikely(vdev->mesh_vdev) &&
  3642. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3643. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3644. /* Update peer level stats */
  3645. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3646. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3647. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3648. if ((peer->vdev->tx_encap_type ==
  3649. htt_cmn_pkt_type_ethernet) &&
  3650. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3651. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3652. }
  3653. }
  3654. } else {
  3655. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3656. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3657. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3658. if (qdf_unlikely(peer->in_twt)) {
  3659. DP_STATS_INC_PKT(peer,
  3660. tx.tx_success_twt,
  3661. 1, length);
  3662. }
  3663. }
  3664. }
  3665. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3666. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3667. #ifdef QCA_SUPPORT_RDK_STATS
  3668. if (soc->rdkstats_enabled)
  3669. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3670. tx_desc->timestamp,
  3671. ts->ppdu_id);
  3672. #endif
  3673. out:
  3674. return;
  3675. }
  3676. /**
  3677. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3678. * @soc: core txrx main context
  3679. * @comp_head: software descriptor head pointer
  3680. * @ring_id: ring number
  3681. *
  3682. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3683. * and release the software descriptors after processing is complete
  3684. *
  3685. * Return: none
  3686. */
  3687. static void
  3688. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3689. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3690. {
  3691. struct dp_tx_desc_s *desc;
  3692. struct dp_tx_desc_s *next;
  3693. struct hal_tx_completion_status ts;
  3694. struct dp_peer *peer = NULL;
  3695. uint16_t peer_id = DP_INVALID_PEER;
  3696. qdf_nbuf_t netbuf;
  3697. desc = comp_head;
  3698. while (desc) {
  3699. if (peer_id != desc->peer_id) {
  3700. if (peer)
  3701. dp_peer_unref_delete(peer,
  3702. DP_MOD_ID_TX_COMP);
  3703. peer_id = desc->peer_id;
  3704. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3705. DP_MOD_ID_TX_COMP);
  3706. }
  3707. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3708. struct dp_pdev *pdev = desc->pdev;
  3709. if (qdf_likely(peer)) {
  3710. /*
  3711. * Increment peer statistics
  3712. * Minimal statistics update done here
  3713. */
  3714. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3715. desc->length);
  3716. if (desc->tx_status !=
  3717. HAL_TX_TQM_RR_FRAME_ACKED)
  3718. DP_STATS_INC(peer, tx.tx_failed, 1);
  3719. }
  3720. qdf_assert(pdev);
  3721. dp_tx_outstanding_dec(pdev);
  3722. /*
  3723. * Calling a QDF WRAPPER here is creating signifcant
  3724. * performance impact so avoided the wrapper call here
  3725. */
  3726. next = desc->next;
  3727. qdf_mem_unmap_nbytes_single(soc->osdev,
  3728. desc->dma_addr,
  3729. QDF_DMA_TO_DEVICE,
  3730. desc->length);
  3731. qdf_nbuf_free(desc->nbuf);
  3732. dp_tx_desc_free(soc, desc, desc->pool_id);
  3733. desc = next;
  3734. continue;
  3735. }
  3736. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3737. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3738. netbuf = desc->nbuf;
  3739. /* check tx complete notification */
  3740. if (peer &&
  3741. QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3742. dp_tx_notify_completion(soc, peer->vdev, desc,
  3743. netbuf, ts.status);
  3744. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3745. next = desc->next;
  3746. dp_tx_desc_release(desc, desc->pool_id);
  3747. desc = next;
  3748. }
  3749. if (peer)
  3750. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3751. }
  3752. /**
  3753. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3754. * @tx_desc: software descriptor head pointer
  3755. * @status : Tx completion status from HTT descriptor
  3756. * @ring_id: ring number
  3757. *
  3758. * This function will process HTT Tx indication messages from Target
  3759. *
  3760. * Return: none
  3761. */
  3762. static
  3763. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3764. uint8_t ring_id)
  3765. {
  3766. uint8_t tx_status;
  3767. struct dp_pdev *pdev;
  3768. struct dp_vdev *vdev;
  3769. struct dp_soc *soc;
  3770. struct hal_tx_completion_status ts = {0};
  3771. uint32_t *htt_desc = (uint32_t *)status;
  3772. struct dp_peer *peer;
  3773. struct cdp_tid_tx_stats *tid_stats = NULL;
  3774. struct htt_soc *htt_handle;
  3775. /*
  3776. * If the descriptor is already freed in vdev_detach,
  3777. * continue to next descriptor
  3778. */
  3779. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3780. QDF_TRACE(QDF_MODULE_ID_DP,
  3781. QDF_TRACE_LEVEL_INFO,
  3782. "Descriptor freed in vdev_detach %d",
  3783. tx_desc->id);
  3784. return;
  3785. }
  3786. pdev = tx_desc->pdev;
  3787. soc = pdev->soc;
  3788. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3789. QDF_TRACE(QDF_MODULE_ID_DP,
  3790. QDF_TRACE_LEVEL_INFO,
  3791. "pdev in down state %d",
  3792. tx_desc->id);
  3793. dp_tx_comp_free_buf(soc, tx_desc);
  3794. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3795. return;
  3796. }
  3797. qdf_assert(tx_desc->pdev);
  3798. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  3799. DP_MOD_ID_HTT_COMP);
  3800. if (!vdev)
  3801. return;
  3802. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3803. htt_handle = (struct htt_soc *)soc->htt_handle;
  3804. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3805. switch (tx_status) {
  3806. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3807. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3808. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3809. {
  3810. uint8_t tid;
  3811. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3812. ts.peer_id =
  3813. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3814. htt_desc[2]);
  3815. ts.tid =
  3816. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3817. htt_desc[2]);
  3818. } else {
  3819. ts.peer_id = HTT_INVALID_PEER;
  3820. ts.tid = HTT_INVALID_TID;
  3821. }
  3822. ts.ppdu_id =
  3823. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3824. htt_desc[1]);
  3825. ts.ack_frame_rssi =
  3826. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3827. htt_desc[1]);
  3828. ts.tsf = htt_desc[3];
  3829. ts.first_msdu = 1;
  3830. ts.last_msdu = 1;
  3831. tid = ts.tid;
  3832. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3833. tid = CDP_MAX_DATA_TIDS - 1;
  3834. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3835. if (qdf_unlikely(pdev->delay_stats_flag))
  3836. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3837. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3838. tid_stats->htt_status_cnt[tx_status]++;
  3839. }
  3840. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3841. DP_MOD_ID_HTT_COMP);
  3842. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3843. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3844. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3845. if (qdf_likely(peer))
  3846. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3847. break;
  3848. }
  3849. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3850. {
  3851. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3852. break;
  3853. }
  3854. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3855. {
  3856. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3857. break;
  3858. }
  3859. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3860. {
  3861. dp_tx_mec_handler(vdev, status);
  3862. break;
  3863. }
  3864. default:
  3865. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3866. "%s Invalid HTT tx_status %d\n",
  3867. __func__, tx_status);
  3868. break;
  3869. }
  3870. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3871. }
  3872. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3873. static inline
  3874. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3875. {
  3876. bool limit_hit = false;
  3877. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3878. limit_hit =
  3879. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3880. if (limit_hit)
  3881. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3882. return limit_hit;
  3883. }
  3884. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3885. {
  3886. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3887. }
  3888. #else
  3889. static inline
  3890. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3891. {
  3892. return false;
  3893. }
  3894. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3895. {
  3896. return false;
  3897. }
  3898. #endif
  3899. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3900. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3901. uint32_t quota)
  3902. {
  3903. void *tx_comp_hal_desc;
  3904. uint8_t buffer_src;
  3905. uint8_t pool_id;
  3906. uint32_t tx_desc_id;
  3907. struct dp_tx_desc_s *tx_desc = NULL;
  3908. struct dp_tx_desc_s *head_desc = NULL;
  3909. struct dp_tx_desc_s *tail_desc = NULL;
  3910. uint32_t num_processed = 0;
  3911. uint32_t count;
  3912. uint32_t num_avail_for_reap = 0;
  3913. bool force_break = false;
  3914. DP_HIST_INIT();
  3915. more_data:
  3916. /* Re-initialize local variables to be re-used */
  3917. head_desc = NULL;
  3918. tail_desc = NULL;
  3919. count = 0;
  3920. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3921. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3922. return 0;
  3923. }
  3924. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3925. if (num_avail_for_reap >= quota)
  3926. num_avail_for_reap = quota;
  3927. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3928. /* Find head descriptor from completion ring */
  3929. while (qdf_likely(num_avail_for_reap)) {
  3930. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3931. if (qdf_unlikely(!tx_comp_hal_desc))
  3932. break;
  3933. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3934. /* If this buffer was not released by TQM or FW, then it is not
  3935. * Tx completion indication, assert */
  3936. if (qdf_unlikely(buffer_src !=
  3937. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3938. (qdf_unlikely(buffer_src !=
  3939. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3940. uint8_t wbm_internal_error;
  3941. dp_err_rl(
  3942. "Tx comp release_src != TQM | FW but from %d",
  3943. buffer_src);
  3944. hal_dump_comp_desc(tx_comp_hal_desc);
  3945. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3946. /* When WBM sees NULL buffer_addr_info in any of
  3947. * ingress rings it sends an error indication,
  3948. * with wbm_internal_error=1, to a specific ring.
  3949. * The WBM2SW ring used to indicate these errors is
  3950. * fixed in HW, and that ring is being used as Tx
  3951. * completion ring. These errors are not related to
  3952. * Tx completions, and should just be ignored
  3953. */
  3954. wbm_internal_error = hal_get_wbm_internal_error(
  3955. soc->hal_soc,
  3956. tx_comp_hal_desc);
  3957. if (wbm_internal_error) {
  3958. dp_err_rl("Tx comp wbm_internal_error!!");
  3959. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3960. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3961. buffer_src)
  3962. dp_handle_wbm_internal_error(
  3963. soc,
  3964. tx_comp_hal_desc,
  3965. hal_tx_comp_get_buffer_type(
  3966. tx_comp_hal_desc));
  3967. } else {
  3968. dp_err_rl("Tx comp wbm_internal_error false");
  3969. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3970. }
  3971. continue;
  3972. }
  3973. /* Get descriptor id */
  3974. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3975. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3976. DP_TX_DESC_ID_POOL_OS;
  3977. /* Find Tx descriptor */
  3978. tx_desc = dp_tx_desc_find(soc, pool_id,
  3979. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3980. DP_TX_DESC_ID_PAGE_OS,
  3981. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3982. DP_TX_DESC_ID_OFFSET_OS);
  3983. /*
  3984. * If the release source is FW, process the HTT status
  3985. */
  3986. if (qdf_unlikely(buffer_src ==
  3987. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3988. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3989. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3990. htt_tx_status);
  3991. dp_tx_process_htt_completion(tx_desc,
  3992. htt_tx_status, ring_id);
  3993. } else {
  3994. tx_desc->peer_id =
  3995. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3996. tx_desc->tx_status =
  3997. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3998. /*
  3999. * If the fast completion mode is enabled extended
  4000. * metadata from descriptor is not copied
  4001. */
  4002. if (qdf_likely(tx_desc->flags &
  4003. DP_TX_DESC_FLAG_SIMPLE))
  4004. goto add_to_pool;
  4005. /*
  4006. * If the descriptor is already freed in vdev_detach,
  4007. * continue to next descriptor
  4008. */
  4009. if (qdf_unlikely
  4010. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4011. !tx_desc->flags)) {
  4012. QDF_TRACE(QDF_MODULE_ID_DP,
  4013. QDF_TRACE_LEVEL_INFO,
  4014. "Descriptor freed in vdev_detach %d",
  4015. tx_desc_id);
  4016. continue;
  4017. }
  4018. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4019. QDF_TRACE(QDF_MODULE_ID_DP,
  4020. QDF_TRACE_LEVEL_INFO,
  4021. "pdev in down state %d",
  4022. tx_desc_id);
  4023. dp_tx_comp_free_buf(soc, tx_desc);
  4024. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4025. goto next_desc;
  4026. }
  4027. /* Pool id is not matching. Error */
  4028. if (tx_desc->pool_id != pool_id) {
  4029. QDF_TRACE(QDF_MODULE_ID_DP,
  4030. QDF_TRACE_LEVEL_FATAL,
  4031. "Tx Comp pool id %d not matched %d",
  4032. pool_id, tx_desc->pool_id);
  4033. qdf_assert_always(0);
  4034. }
  4035. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4036. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4037. QDF_TRACE(QDF_MODULE_ID_DP,
  4038. QDF_TRACE_LEVEL_FATAL,
  4039. "Txdesc invalid, flgs = %x,id = %d",
  4040. tx_desc->flags, tx_desc_id);
  4041. qdf_assert_always(0);
  4042. }
  4043. /* Collect hw completion contents */
  4044. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4045. &tx_desc->comp, 1);
  4046. add_to_pool:
  4047. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4048. /* First ring descriptor on the cycle */
  4049. if (!head_desc) {
  4050. head_desc = tx_desc;
  4051. tail_desc = tx_desc;
  4052. }
  4053. tail_desc->next = tx_desc;
  4054. tx_desc->next = NULL;
  4055. tail_desc = tx_desc;
  4056. }
  4057. next_desc:
  4058. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4059. /*
  4060. * Processed packet count is more than given quota
  4061. * stop to processing
  4062. */
  4063. count++;
  4064. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  4065. break;
  4066. }
  4067. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4068. /* Process the reaped descriptors */
  4069. if (head_desc)
  4070. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4071. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4072. if (num_processed >= quota)
  4073. force_break = true;
  4074. if (!force_break &&
  4075. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4076. hal_ring_hdl)) {
  4077. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4078. if (!hif_exec_should_yield(soc->hif_handle,
  4079. int_ctx->dp_intr_id))
  4080. goto more_data;
  4081. }
  4082. }
  4083. DP_TX_HIST_STATS_PER_PDEV();
  4084. return num_processed;
  4085. }
  4086. #ifdef FEATURE_WLAN_TDLS
  4087. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4088. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4089. {
  4090. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4091. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4092. DP_MOD_ID_TDLS);
  4093. if (!vdev) {
  4094. dp_err("vdev handle for id %d is NULL", vdev_id);
  4095. return NULL;
  4096. }
  4097. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4098. vdev->is_tdls_frame = true;
  4099. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4100. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4101. }
  4102. #endif
  4103. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  4104. {
  4105. struct wlan_cfg_dp_soc_ctxt *cfg;
  4106. struct dp_soc *soc;
  4107. soc = vdev->pdev->soc;
  4108. if (!soc)
  4109. return;
  4110. cfg = soc->wlan_cfg_ctx;
  4111. if (!cfg)
  4112. return;
  4113. if (vdev->opmode == wlan_op_mode_ndi)
  4114. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  4115. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  4116. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  4117. (vdev->subtype == wlan_op_subtype_p2p_go))
  4118. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  4119. else
  4120. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  4121. }
  4122. /**
  4123. * dp_tx_vdev_attach() - attach vdev to dp tx
  4124. * @vdev: virtual device instance
  4125. *
  4126. * Return: QDF_STATUS_SUCCESS: success
  4127. * QDF_STATUS_E_RESOURCES: Error return
  4128. */
  4129. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4130. {
  4131. int pdev_id;
  4132. /*
  4133. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4134. */
  4135. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4136. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4137. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4138. vdev->vdev_id);
  4139. pdev_id =
  4140. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4141. vdev->pdev->pdev_id);
  4142. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4143. /*
  4144. * Set HTT Extension Valid bit to 0 by default
  4145. */
  4146. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4147. dp_tx_vdev_update_search_flags(vdev);
  4148. dp_tx_vdev_update_feature_flags(vdev);
  4149. return QDF_STATUS_SUCCESS;
  4150. }
  4151. #ifndef FEATURE_WDS
  4152. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4153. {
  4154. return false;
  4155. }
  4156. #endif
  4157. /**
  4158. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4159. * @vdev: virtual device instance
  4160. *
  4161. * Return: void
  4162. *
  4163. */
  4164. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4165. {
  4166. struct dp_soc *soc = vdev->pdev->soc;
  4167. /*
  4168. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4169. * for TDLS link
  4170. *
  4171. * Enable AddrY (SA based search) only for non-WDS STA and
  4172. * ProxySTA VAP (in HKv1) modes.
  4173. *
  4174. * In all other VAP modes, only DA based search should be
  4175. * enabled
  4176. */
  4177. if (vdev->opmode == wlan_op_mode_sta &&
  4178. vdev->tdls_link_connected)
  4179. vdev->hal_desc_addr_search_flags =
  4180. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4181. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4182. !dp_tx_da_search_override(vdev))
  4183. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4184. else
  4185. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4186. /* Set search type only when peer map v2 messaging is enabled
  4187. * as we will have the search index (AST hash) only when v2 is
  4188. * enabled
  4189. */
  4190. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  4191. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  4192. else
  4193. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4194. }
  4195. static inline bool
  4196. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4197. struct dp_vdev *vdev,
  4198. struct dp_tx_desc_s *tx_desc)
  4199. {
  4200. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4201. return false;
  4202. /*
  4203. * if vdev is given, then only check whether desc
  4204. * vdev match. if vdev is NULL, then check whether
  4205. * desc pdev match.
  4206. */
  4207. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4208. (tx_desc->pdev == pdev);
  4209. }
  4210. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4211. /**
  4212. * dp_tx_desc_flush() - release resources associated
  4213. * to TX Desc
  4214. *
  4215. * @dp_pdev: Handle to DP pdev structure
  4216. * @vdev: virtual device instance
  4217. * NULL: no specific Vdev is required and check all allcated TX desc
  4218. * on this pdev.
  4219. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4220. *
  4221. * @force_free:
  4222. * true: flush the TX desc.
  4223. * false: only reset the Vdev in each allocated TX desc
  4224. * that associated to current Vdev.
  4225. *
  4226. * This function will go through the TX desc pool to flush
  4227. * the outstanding TX data or reset Vdev to NULL in associated TX
  4228. * Desc.
  4229. */
  4230. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4231. bool force_free)
  4232. {
  4233. uint8_t i;
  4234. uint32_t j;
  4235. uint32_t num_desc, page_id, offset;
  4236. uint16_t num_desc_per_page;
  4237. struct dp_soc *soc = pdev->soc;
  4238. struct dp_tx_desc_s *tx_desc = NULL;
  4239. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4240. if (!vdev && !force_free) {
  4241. dp_err("Reset TX desc vdev, Vdev param is required!");
  4242. return;
  4243. }
  4244. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4245. tx_desc_pool = &soc->tx_desc[i];
  4246. if (!(tx_desc_pool->pool_size) ||
  4247. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4248. !(tx_desc_pool->desc_pages.cacheable_pages))
  4249. continue;
  4250. /*
  4251. * Add flow pool lock protection in case pool is freed
  4252. * due to all tx_desc is recycled when handle TX completion.
  4253. * this is not necessary when do force flush as:
  4254. * a. double lock will happen if dp_tx_desc_release is
  4255. * also trying to acquire it.
  4256. * b. dp interrupt has been disabled before do force TX desc
  4257. * flush in dp_pdev_deinit().
  4258. */
  4259. if (!force_free)
  4260. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4261. num_desc = tx_desc_pool->pool_size;
  4262. num_desc_per_page =
  4263. tx_desc_pool->desc_pages.num_element_per_page;
  4264. for (j = 0; j < num_desc; j++) {
  4265. page_id = j / num_desc_per_page;
  4266. offset = j % num_desc_per_page;
  4267. if (qdf_unlikely(!(tx_desc_pool->
  4268. desc_pages.cacheable_pages)))
  4269. break;
  4270. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4271. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4272. /*
  4273. * Free TX desc if force free is
  4274. * required, otherwise only reset vdev
  4275. * in this TX desc.
  4276. */
  4277. if (force_free) {
  4278. dp_tx_comp_free_buf(soc, tx_desc);
  4279. dp_tx_desc_release(tx_desc, i);
  4280. } else {
  4281. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4282. }
  4283. }
  4284. }
  4285. if (!force_free)
  4286. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4287. }
  4288. }
  4289. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4290. /**
  4291. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4292. *
  4293. * @soc: Handle to DP soc structure
  4294. * @tx_desc: pointer of one TX desc
  4295. * @desc_pool_id: TX Desc pool id
  4296. */
  4297. static inline void
  4298. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4299. uint8_t desc_pool_id)
  4300. {
  4301. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4302. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4303. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4304. }
  4305. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4306. bool force_free)
  4307. {
  4308. uint8_t i, num_pool;
  4309. uint32_t j;
  4310. uint32_t num_desc, page_id, offset;
  4311. uint16_t num_desc_per_page;
  4312. struct dp_soc *soc = pdev->soc;
  4313. struct dp_tx_desc_s *tx_desc = NULL;
  4314. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4315. if (!vdev && !force_free) {
  4316. dp_err("Reset TX desc vdev, Vdev param is required!");
  4317. return;
  4318. }
  4319. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4320. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4321. for (i = 0; i < num_pool; i++) {
  4322. tx_desc_pool = &soc->tx_desc[i];
  4323. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4324. continue;
  4325. num_desc_per_page =
  4326. tx_desc_pool->desc_pages.num_element_per_page;
  4327. for (j = 0; j < num_desc; j++) {
  4328. page_id = j / num_desc_per_page;
  4329. offset = j % num_desc_per_page;
  4330. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4331. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4332. if (force_free) {
  4333. dp_tx_comp_free_buf(soc, tx_desc);
  4334. dp_tx_desc_release(tx_desc, i);
  4335. } else {
  4336. dp_tx_desc_reset_vdev(soc, tx_desc,
  4337. i);
  4338. }
  4339. }
  4340. }
  4341. }
  4342. }
  4343. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4344. /**
  4345. * dp_tx_vdev_detach() - detach vdev from dp tx
  4346. * @vdev: virtual device instance
  4347. *
  4348. * Return: QDF_STATUS_SUCCESS: success
  4349. * QDF_STATUS_E_RESOURCES: Error return
  4350. */
  4351. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4352. {
  4353. struct dp_pdev *pdev = vdev->pdev;
  4354. /* Reset TX desc associated to this Vdev as NULL */
  4355. dp_tx_desc_flush(pdev, vdev, false);
  4356. dp_tx_vdev_multipass_deinit(vdev);
  4357. return QDF_STATUS_SUCCESS;
  4358. }
  4359. /**
  4360. * dp_tx_pdev_attach() - attach pdev to dp tx
  4361. * @pdev: physical device instance
  4362. *
  4363. * Return: QDF_STATUS_SUCCESS: success
  4364. * QDF_STATUS_E_RESOURCES: Error return
  4365. */
  4366. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  4367. {
  4368. struct dp_soc *soc = pdev->soc;
  4369. /* Initialize Flow control counters */
  4370. qdf_atomic_init(&pdev->num_tx_outstanding);
  4371. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  4372. /* Initialize descriptors in TCL Ring */
  4373. hal_tx_init_data_ring(soc->hal_soc,
  4374. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  4375. }
  4376. return QDF_STATUS_SUCCESS;
  4377. }
  4378. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4379. /* Pools will be allocated dynamically */
  4380. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4381. int num_desc)
  4382. {
  4383. uint8_t i;
  4384. for (i = 0; i < num_pool; i++) {
  4385. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4386. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4387. }
  4388. return QDF_STATUS_SUCCESS;
  4389. }
  4390. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4391. int num_desc)
  4392. {
  4393. return QDF_STATUS_SUCCESS;
  4394. }
  4395. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4396. {
  4397. }
  4398. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4399. {
  4400. uint8_t i;
  4401. for (i = 0; i < num_pool; i++)
  4402. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4403. }
  4404. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4405. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4406. int num_desc)
  4407. {
  4408. uint8_t i, count;
  4409. /* Allocate software Tx descriptor pools */
  4410. for (i = 0; i < num_pool; i++) {
  4411. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4412. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4413. FL("Tx Desc Pool alloc %d failed %pK"),
  4414. i, soc);
  4415. goto fail;
  4416. }
  4417. }
  4418. return QDF_STATUS_SUCCESS;
  4419. fail:
  4420. for (count = 0; count < i; count++)
  4421. dp_tx_desc_pool_free(soc, count);
  4422. return QDF_STATUS_E_NOMEM;
  4423. }
  4424. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4425. int num_desc)
  4426. {
  4427. uint8_t i;
  4428. for (i = 0; i < num_pool; i++) {
  4429. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4430. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4431. FL("Tx Desc Pool init %d failed %pK"),
  4432. i, soc);
  4433. return QDF_STATUS_E_NOMEM;
  4434. }
  4435. }
  4436. return QDF_STATUS_SUCCESS;
  4437. }
  4438. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4439. {
  4440. uint8_t i;
  4441. for (i = 0; i < num_pool; i++)
  4442. dp_tx_desc_pool_deinit(soc, i);
  4443. }
  4444. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4445. {
  4446. uint8_t i;
  4447. for (i = 0; i < num_pool; i++)
  4448. dp_tx_desc_pool_free(soc, i);
  4449. }
  4450. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4451. /**
  4452. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4453. * @soc: core txrx main context
  4454. * @num_pool: number of pools
  4455. *
  4456. */
  4457. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4458. {
  4459. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4460. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4461. }
  4462. /**
  4463. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4464. * @soc: core txrx main context
  4465. * @num_pool: number of pools
  4466. *
  4467. */
  4468. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4469. {
  4470. dp_tx_tso_desc_pool_free(soc, num_pool);
  4471. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4472. }
  4473. /**
  4474. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4475. * @soc: core txrx main context
  4476. *
  4477. * This function frees all tx related descriptors as below
  4478. * 1. Regular TX descriptors (static pools)
  4479. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4480. * 3. TSO descriptors
  4481. *
  4482. */
  4483. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4484. {
  4485. uint8_t num_pool;
  4486. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4487. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4488. dp_tx_ext_desc_pool_free(soc, num_pool);
  4489. dp_tx_delete_static_pools(soc, num_pool);
  4490. }
  4491. /**
  4492. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4493. * @soc: core txrx main context
  4494. *
  4495. * This function de-initializes all tx related descriptors as below
  4496. * 1. Regular TX descriptors (static pools)
  4497. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4498. * 3. TSO descriptors
  4499. *
  4500. */
  4501. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4502. {
  4503. uint8_t num_pool;
  4504. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4505. dp_tx_flow_control_deinit(soc);
  4506. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4507. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4508. dp_tx_deinit_static_pools(soc, num_pool);
  4509. }
  4510. /**
  4511. * dp_tso_attach() - TSO attach handler
  4512. * @txrx_soc: Opaque Dp handle
  4513. *
  4514. * Reserve TSO descriptor buffers
  4515. *
  4516. * Return: QDF_STATUS_E_FAILURE on failure or
  4517. * QDF_STATUS_SUCCESS on success
  4518. */
  4519. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4520. uint8_t num_pool,
  4521. uint16_t num_desc)
  4522. {
  4523. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4524. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4525. return QDF_STATUS_E_FAILURE;
  4526. }
  4527. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4528. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4529. num_pool, soc);
  4530. return QDF_STATUS_E_FAILURE;
  4531. }
  4532. return QDF_STATUS_SUCCESS;
  4533. }
  4534. /**
  4535. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4536. * @soc: DP soc handle
  4537. * @num_pool: Number of pools
  4538. * @num_desc: Number of descriptors
  4539. *
  4540. * Initialize TSO descriptor pools
  4541. *
  4542. * Return: QDF_STATUS_E_FAILURE on failure or
  4543. * QDF_STATUS_SUCCESS on success
  4544. */
  4545. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4546. uint8_t num_pool,
  4547. uint16_t num_desc)
  4548. {
  4549. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4550. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4551. return QDF_STATUS_E_FAILURE;
  4552. }
  4553. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4554. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4555. num_pool, soc);
  4556. return QDF_STATUS_E_FAILURE;
  4557. }
  4558. return QDF_STATUS_SUCCESS;
  4559. }
  4560. /**
  4561. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4562. * @soc: core txrx main context
  4563. *
  4564. * This function allocates memory for following descriptor pools
  4565. * 1. regular sw tx descriptor pools (static pools)
  4566. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4567. * 3. TSO descriptor pools
  4568. *
  4569. * Return: QDF_STATUS_SUCCESS: success
  4570. * QDF_STATUS_E_RESOURCES: Error return
  4571. */
  4572. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4573. {
  4574. uint8_t num_pool;
  4575. uint32_t num_desc;
  4576. uint32_t num_ext_desc;
  4577. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4578. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4579. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4581. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4582. __func__, num_pool, num_desc);
  4583. if ((num_pool > MAX_TXDESC_POOLS) ||
  4584. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4585. goto fail1;
  4586. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4587. goto fail1;
  4588. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4589. goto fail2;
  4590. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4591. return QDF_STATUS_SUCCESS;
  4592. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4593. goto fail3;
  4594. return QDF_STATUS_SUCCESS;
  4595. fail3:
  4596. dp_tx_ext_desc_pool_free(soc, num_pool);
  4597. fail2:
  4598. dp_tx_delete_static_pools(soc, num_pool);
  4599. fail1:
  4600. return QDF_STATUS_E_RESOURCES;
  4601. }
  4602. /**
  4603. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4604. * @soc: core txrx main context
  4605. *
  4606. * This function initializes the following TX descriptor pools
  4607. * 1. regular sw tx descriptor pools (static pools)
  4608. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4609. * 3. TSO descriptor pools
  4610. *
  4611. * Return: QDF_STATUS_SUCCESS: success
  4612. * QDF_STATUS_E_RESOURCES: Error return
  4613. */
  4614. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4615. {
  4616. uint8_t num_pool;
  4617. uint32_t num_desc;
  4618. uint32_t num_ext_desc;
  4619. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4620. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4621. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4622. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4623. goto fail1;
  4624. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4625. goto fail2;
  4626. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4627. return QDF_STATUS_SUCCESS;
  4628. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4629. goto fail3;
  4630. dp_tx_flow_control_init(soc);
  4631. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4632. return QDF_STATUS_SUCCESS;
  4633. fail3:
  4634. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4635. fail2:
  4636. dp_tx_deinit_static_pools(soc, num_pool);
  4637. fail1:
  4638. return QDF_STATUS_E_RESOURCES;
  4639. }
  4640. /**
  4641. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4642. * @txrx_soc: dp soc handle
  4643. *
  4644. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4645. * QDF_STATUS_E_FAILURE
  4646. */
  4647. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4648. {
  4649. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4650. uint8_t num_pool;
  4651. uint32_t num_desc;
  4652. uint32_t num_ext_desc;
  4653. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4654. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4655. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4656. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4657. return QDF_STATUS_E_FAILURE;
  4658. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4659. return QDF_STATUS_E_FAILURE;
  4660. return QDF_STATUS_SUCCESS;
  4661. }
  4662. /**
  4663. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4664. * @txrx_soc: dp soc handle
  4665. *
  4666. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4667. */
  4668. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4669. {
  4670. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4671. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4672. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4673. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4674. return QDF_STATUS_SUCCESS;
  4675. }