hif.h 48 KB

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  1. /*
  2. * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HIF_H_
  19. #define _HIF_H_
  20. #ifdef __cplusplus
  21. extern "C" {
  22. #endif /* __cplusplus */
  23. /* Header files */
  24. #include <qdf_status.h>
  25. #include "qdf_nbuf.h"
  26. #include "qdf_lro.h"
  27. #include "ol_if_athvar.h"
  28. #include <linux/platform_device.h>
  29. #ifdef HIF_PCI
  30. #include <linux/pci.h>
  31. #endif /* HIF_PCI */
  32. #ifdef HIF_USB
  33. #include <linux/usb.h>
  34. #endif /* HIF_USB */
  35. #ifdef IPA_OFFLOAD
  36. #include <linux/ipa.h>
  37. #endif
  38. #include "cfg_ucfg_api.h"
  39. #include "qdf_dev.h"
  40. #define ENABLE_MBOX_DUMMY_SPACE_FEATURE 1
  41. typedef void __iomem *A_target_id_t;
  42. typedef void *hif_handle_t;
  43. #define HIF_TYPE_AR6002 2
  44. #define HIF_TYPE_AR6003 3
  45. #define HIF_TYPE_AR6004 5
  46. #define HIF_TYPE_AR9888 6
  47. #define HIF_TYPE_AR6320 7
  48. #define HIF_TYPE_AR6320V2 8
  49. /* For attaching Peregrine 2.0 board host_reg_tbl only */
  50. #define HIF_TYPE_AR9888V2 9
  51. #define HIF_TYPE_ADRASTEA 10
  52. #define HIF_TYPE_AR900B 11
  53. #define HIF_TYPE_QCA9984 12
  54. #define HIF_TYPE_IPQ4019 13
  55. #define HIF_TYPE_QCA9888 14
  56. #define HIF_TYPE_QCA8074 15
  57. #define HIF_TYPE_QCA6290 16
  58. #define HIF_TYPE_QCN7605 17
  59. #define HIF_TYPE_QCA6390 18
  60. #define HIF_TYPE_QCA8074V2 19
  61. #define HIF_TYPE_QCA6018 20
  62. #define HIF_TYPE_QCN9000 21
  63. #define HIF_TYPE_QCA6490 22
  64. #define HIF_TYPE_QCA6750 23
  65. #define HIF_TYPE_QCA5018 24
  66. #define DMA_COHERENT_MASK_DEFAULT 37
  67. #ifdef IPA_OFFLOAD
  68. #define DMA_COHERENT_MASK_BELOW_IPA_VER_3 32
  69. #endif
  70. /* enum hif_ic_irq - enum defining integrated chip irq numbers
  71. * defining irq nubers that can be used by external modules like datapath
  72. */
  73. enum hif_ic_irq {
  74. host2wbm_desc_feed = 16,
  75. host2reo_re_injection,
  76. host2reo_command,
  77. host2rxdma_monitor_ring3,
  78. host2rxdma_monitor_ring2,
  79. host2rxdma_monitor_ring1,
  80. reo2host_exception,
  81. wbm2host_rx_release,
  82. reo2host_status,
  83. reo2host_destination_ring4,
  84. reo2host_destination_ring3,
  85. reo2host_destination_ring2,
  86. reo2host_destination_ring1,
  87. rxdma2host_monitor_destination_mac3,
  88. rxdma2host_monitor_destination_mac2,
  89. rxdma2host_monitor_destination_mac1,
  90. ppdu_end_interrupts_mac3,
  91. ppdu_end_interrupts_mac2,
  92. ppdu_end_interrupts_mac1,
  93. rxdma2host_monitor_status_ring_mac3,
  94. rxdma2host_monitor_status_ring_mac2,
  95. rxdma2host_monitor_status_ring_mac1,
  96. host2rxdma_host_buf_ring_mac3,
  97. host2rxdma_host_buf_ring_mac2,
  98. host2rxdma_host_buf_ring_mac1,
  99. rxdma2host_destination_ring_mac3,
  100. rxdma2host_destination_ring_mac2,
  101. rxdma2host_destination_ring_mac1,
  102. host2tcl_input_ring4,
  103. host2tcl_input_ring3,
  104. host2tcl_input_ring2,
  105. host2tcl_input_ring1,
  106. wbm2host_tx_completions_ring3,
  107. wbm2host_tx_completions_ring2,
  108. wbm2host_tx_completions_ring1,
  109. tcl2host_status_ring,
  110. };
  111. struct CE_state;
  112. #define CE_COUNT_MAX 12
  113. #define HIF_MAX_GRP_IRQ 16
  114. #ifndef HIF_MAX_GROUP
  115. #define HIF_MAX_GROUP 7
  116. #endif
  117. #ifndef NAPI_YIELD_BUDGET_BASED
  118. #ifndef QCA_NAPI_DEF_SCALE_BIN_SHIFT
  119. #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 4
  120. #endif
  121. #else /* NAPI_YIELD_BUDGET_BASED */
  122. #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 2
  123. #endif /* NAPI_YIELD_BUDGET_BASED */
  124. #define QCA_NAPI_BUDGET 64
  125. #define QCA_NAPI_DEF_SCALE \
  126. (1 << QCA_NAPI_DEF_SCALE_BIN_SHIFT)
  127. #define HIF_NAPI_MAX_RECEIVES (QCA_NAPI_BUDGET * QCA_NAPI_DEF_SCALE)
  128. /* NOTE: "napi->scale" can be changed,
  129. * but this does not change the number of buckets
  130. */
  131. #define QCA_NAPI_NUM_BUCKETS 4
  132. /**
  133. * qca_napi_stat - stats structure for execution contexts
  134. * @napi_schedules - number of times the schedule function is called
  135. * @napi_polls - number of times the execution context runs
  136. * @napi_completes - number of times that the generating interrupt is reenabled
  137. * @napi_workdone - cumulative of all work done reported by handler
  138. * @cpu_corrected - incremented when execution context runs on a different core
  139. * than the one that its irq is affined to.
  140. * @napi_budget_uses - histogram of work done per execution run
  141. * @time_limit_reache - count of yields due to time limit threshholds
  142. * @rxpkt_thresh_reached - count of yields due to a work limit
  143. * @poll_time_buckets - histogram of poll times for the napi
  144. *
  145. */
  146. struct qca_napi_stat {
  147. uint32_t napi_schedules;
  148. uint32_t napi_polls;
  149. uint32_t napi_completes;
  150. uint32_t napi_workdone;
  151. uint32_t cpu_corrected;
  152. uint32_t napi_budget_uses[QCA_NAPI_NUM_BUCKETS];
  153. uint32_t time_limit_reached;
  154. uint32_t rxpkt_thresh_reached;
  155. unsigned long long napi_max_poll_time;
  156. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  157. uint32_t poll_time_buckets[QCA_NAPI_NUM_BUCKETS];
  158. #endif
  159. };
  160. /**
  161. * per NAPI instance data structure
  162. * This data structure holds stuff per NAPI instance.
  163. * Note that, in the current implementation, though scale is
  164. * an instance variable, it is set to the same value for all
  165. * instances.
  166. */
  167. struct qca_napi_info {
  168. struct net_device netdev; /* dummy net_dev */
  169. void *hif_ctx;
  170. struct napi_struct napi;
  171. uint8_t scale; /* currently same on all instances */
  172. uint8_t id;
  173. uint8_t cpu;
  174. int irq;
  175. cpumask_t cpumask;
  176. struct qca_napi_stat stats[NR_CPUS];
  177. #ifdef RECEIVE_OFFLOAD
  178. /* will only be present for data rx CE's */
  179. void (*offld_flush_cb)(void *);
  180. struct napi_struct rx_thread_napi;
  181. struct net_device rx_thread_netdev;
  182. #endif /* RECEIVE_OFFLOAD */
  183. qdf_lro_ctx_t lro_ctx;
  184. };
  185. enum qca_napi_tput_state {
  186. QCA_NAPI_TPUT_UNINITIALIZED,
  187. QCA_NAPI_TPUT_LO,
  188. QCA_NAPI_TPUT_HI
  189. };
  190. enum qca_napi_cpu_state {
  191. QCA_NAPI_CPU_UNINITIALIZED,
  192. QCA_NAPI_CPU_DOWN,
  193. QCA_NAPI_CPU_UP };
  194. /**
  195. * struct qca_napi_cpu - an entry of the napi cpu table
  196. * @core_id: physical core id of the core
  197. * @cluster_id: cluster this core belongs to
  198. * @core_mask: mask to match all core of this cluster
  199. * @thread_mask: mask for this core within the cluster
  200. * @max_freq: maximum clock this core can be clocked at
  201. * same for all cpus of the same core.
  202. * @napis: bitmap of napi instances on this core
  203. * @execs: bitmap of execution contexts on this core
  204. * cluster_nxt: chain to link cores within the same cluster
  205. *
  206. * This structure represents a single entry in the napi cpu
  207. * table. The table is part of struct qca_napi_data.
  208. * This table is initialized by the init function, called while
  209. * the first napi instance is being created, updated by hotplug
  210. * notifier and when cpu affinity decisions are made (by throughput
  211. * detection), and deleted when the last napi instance is removed.
  212. */
  213. struct qca_napi_cpu {
  214. enum qca_napi_cpu_state state;
  215. int core_id;
  216. int cluster_id;
  217. cpumask_t core_mask;
  218. cpumask_t thread_mask;
  219. unsigned int max_freq;
  220. uint32_t napis;
  221. uint32_t execs;
  222. int cluster_nxt; /* index, not pointer */
  223. };
  224. /**
  225. * struct qca_napi_data - collection of napi data for a single hif context
  226. * @hif_softc: pointer to the hif context
  227. * @lock: spinlock used in the event state machine
  228. * @state: state variable used in the napi stat machine
  229. * @ce_map: bit map indicating which ce's have napis running
  230. * @exec_map: bit map of instanciated exec contexts
  231. * @user_cpu_affin_map: CPU affinity map from INI config.
  232. * @napi_cpu: cpu info for irq affinty
  233. * @lilcl_head:
  234. * @bigcl_head:
  235. * @napi_mode: irq affinity & clock voting mode
  236. * @cpuhp_handler: CPU hotplug event registration handle
  237. */
  238. struct qca_napi_data {
  239. struct hif_softc *hif_softc;
  240. qdf_spinlock_t lock;
  241. uint32_t state;
  242. /* bitmap of created/registered NAPI instances, indexed by pipe_id,
  243. * not used by clients (clients use an id returned by create)
  244. */
  245. uint32_t ce_map;
  246. uint32_t exec_map;
  247. uint32_t user_cpu_affin_mask;
  248. struct qca_napi_info *napis[CE_COUNT_MAX];
  249. struct qca_napi_cpu napi_cpu[NR_CPUS];
  250. int lilcl_head, bigcl_head;
  251. enum qca_napi_tput_state napi_mode;
  252. struct qdf_cpuhp_handler *cpuhp_handler;
  253. uint8_t flags;
  254. };
  255. /**
  256. * struct hif_config_info - Place Holder for HIF configuration
  257. * @enable_self_recovery: Self Recovery
  258. * @enable_runtime_pm: Enable Runtime PM
  259. * @runtime_pm_delay: Runtime PM Delay
  260. * @rx_softirq_max_yield_duration_ns: Max Yield time duration for RX Softirq
  261. *
  262. * Structure for holding HIF ini parameters.
  263. */
  264. struct hif_config_info {
  265. bool enable_self_recovery;
  266. #ifdef FEATURE_RUNTIME_PM
  267. uint8_t enable_runtime_pm;
  268. u_int32_t runtime_pm_delay;
  269. #endif
  270. uint64_t rx_softirq_max_yield_duration_ns;
  271. };
  272. /**
  273. * struct hif_target_info - Target Information
  274. * @target_version: Target Version
  275. * @target_type: Target Type
  276. * @target_revision: Target Revision
  277. * @soc_version: SOC Version
  278. * @hw_name: pointer to hardware name
  279. *
  280. * Structure to hold target information.
  281. */
  282. struct hif_target_info {
  283. uint32_t target_version;
  284. uint32_t target_type;
  285. uint32_t target_revision;
  286. uint32_t soc_version;
  287. char *hw_name;
  288. };
  289. struct hif_opaque_softc {
  290. };
  291. /**
  292. * enum hif_event_type - Type of DP events to be recorded
  293. * @HIF_EVENT_IRQ_TRIGGER: IRQ trigger event
  294. * @HIF_EVENT_TIMER_ENTRY: Monitor Timer entry event
  295. * @HIF_EVENT_TIMER_EXIT: Monitor Timer exit event
  296. * @HIF_EVENT_BH_SCHED: NAPI POLL scheduled event
  297. * @HIF_EVENT_SRNG_ACCESS_START: hal ring access start event
  298. * @HIF_EVENT_SRNG_ACCESS_END: hal ring access end event
  299. */
  300. enum hif_event_type {
  301. HIF_EVENT_IRQ_TRIGGER,
  302. HIF_EVENT_TIMER_ENTRY,
  303. HIF_EVENT_TIMER_EXIT,
  304. HIF_EVENT_BH_SCHED,
  305. HIF_EVENT_SRNG_ACCESS_START,
  306. HIF_EVENT_SRNG_ACCESS_END,
  307. };
  308. #ifdef WLAN_FEATURE_DP_EVENT_HISTORY
  309. /* HIF_EVENT_HIST_MAX should always be power of 2 */
  310. #define HIF_EVENT_HIST_MAX 512
  311. #define HIF_NUM_INT_CONTEXTS HIF_MAX_GROUP
  312. #define HIF_EVENT_HIST_DISABLE_MASK 0
  313. /**
  314. * struct hif_event_record - an entry of the DP event history
  315. * @hal_ring_id: ring id for which event is recorded
  316. * @hp: head pointer of the ring (may not be applicable for all events)
  317. * @tp: tail pointer of the ring (may not be applicable for all events)
  318. * @cpu_id: cpu id on which the event occurred
  319. * @timestamp: timestamp when event occurred
  320. * @type: type of the event
  321. *
  322. * This structure represents the information stored for every datapath
  323. * event which is logged in the history.
  324. */
  325. struct hif_event_record {
  326. uint8_t hal_ring_id;
  327. uint32_t hp;
  328. uint32_t tp;
  329. int cpu_id;
  330. uint64_t timestamp;
  331. enum hif_event_type type;
  332. };
  333. /**
  334. * struct hif_event_history - history for one interrupt group
  335. * @index: index to store new event
  336. * @event: event entry
  337. *
  338. * This structure represents the datapath history for one
  339. * interrupt group.
  340. */
  341. struct hif_event_history {
  342. qdf_atomic_t index;
  343. struct hif_event_record event[HIF_EVENT_HIST_MAX];
  344. };
  345. /**
  346. * hif_hist_record_event() - Record one datapath event in history
  347. * @hif_ctx: HIF opaque context
  348. * @event: DP event entry
  349. * @intr_grp_id: interrupt group ID registered with hif
  350. *
  351. * Return: None
  352. */
  353. void hif_hist_record_event(struct hif_opaque_softc *hif_ctx,
  354. struct hif_event_record *event,
  355. uint8_t intr_grp_id);
  356. /**
  357. * hif_event_history_init() - Initialize SRNG event history buffers
  358. * @hif_ctx: HIF opaque context
  359. * @id: context group ID for which history is recorded
  360. *
  361. * Returns: None
  362. */
  363. void hif_event_history_init(struct hif_opaque_softc *hif_ctx, uint8_t id);
  364. /**
  365. * hif_event_history_deinit() - De-initialize SRNG event history buffers
  366. * @hif_ctx: HIF opaque context
  367. * @id: context group ID for which history is recorded
  368. *
  369. * Returns: None
  370. */
  371. void hif_event_history_deinit(struct hif_opaque_softc *hif_ctx, uint8_t id);
  372. /**
  373. * hif_record_event() - Wrapper function to form and record DP event
  374. * @hif_ctx: HIF opaque context
  375. * @intr_grp_id: interrupt group ID registered with hif
  376. * @hal_ring_id: ring id for which event is recorded
  377. * @hp: head pointer index of the srng
  378. * @tp: tail pointer index of the srng
  379. * @type: type of the event to be logged in history
  380. *
  381. * Return: None
  382. */
  383. static inline void hif_record_event(struct hif_opaque_softc *hif_ctx,
  384. uint8_t intr_grp_id,
  385. uint8_t hal_ring_id,
  386. uint32_t hp,
  387. uint32_t tp,
  388. enum hif_event_type type)
  389. {
  390. struct hif_event_record event;
  391. event.hal_ring_id = hal_ring_id;
  392. event.hp = hp;
  393. event.tp = tp;
  394. event.type = type;
  395. return hif_hist_record_event(hif_ctx, &event,
  396. intr_grp_id);
  397. }
  398. #else
  399. static inline void hif_record_event(struct hif_opaque_softc *hif_ctx,
  400. uint8_t intr_grp_id,
  401. uint8_t hal_ring_id,
  402. uint32_t hp,
  403. uint32_t tp,
  404. enum hif_event_type type)
  405. {
  406. }
  407. static inline void hif_event_history_init(struct hif_opaque_softc *hif_ctx,
  408. uint8_t id)
  409. {
  410. }
  411. static inline void hif_event_history_deinit(struct hif_opaque_softc *hif_ctx,
  412. uint8_t id)
  413. {
  414. }
  415. #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */
  416. /**
  417. * enum HIF_DEVICE_POWER_CHANGE_TYPE: Device Power change type
  418. *
  419. * @HIF_DEVICE_POWER_UP: HIF layer should power up interface and/or module
  420. * @HIF_DEVICE_POWER_DOWN: HIF layer should initiate bus-specific measures to
  421. * minimize power
  422. * @HIF_DEVICE_POWER_CUT: HIF layer should initiate bus-specific AND/OR
  423. * platform-specific measures to completely power-off
  424. * the module and associated hardware (i.e. cut power
  425. * supplies)
  426. */
  427. enum HIF_DEVICE_POWER_CHANGE_TYPE {
  428. HIF_DEVICE_POWER_UP,
  429. HIF_DEVICE_POWER_DOWN,
  430. HIF_DEVICE_POWER_CUT
  431. };
  432. /**
  433. * enum hif_enable_type: what triggered the enabling of hif
  434. *
  435. * @HIF_ENABLE_TYPE_PROBE: probe triggered enable
  436. * @HIF_ENABLE_TYPE_REINIT: reinit triggered enable
  437. */
  438. enum hif_enable_type {
  439. HIF_ENABLE_TYPE_PROBE,
  440. HIF_ENABLE_TYPE_REINIT,
  441. HIF_ENABLE_TYPE_MAX
  442. };
  443. /**
  444. * enum hif_disable_type: what triggered the disabling of hif
  445. *
  446. * @HIF_DISABLE_TYPE_PROBE_ERROR: probe error triggered disable
  447. * @HIF_DISABLE_TYPE_REINIT_ERROR: reinit error triggered disable
  448. * @HIF_DISABLE_TYPE_REMOVE: remove triggered disable
  449. * @HIF_DISABLE_TYPE_SHUTDOWN: shutdown triggered disable
  450. */
  451. enum hif_disable_type {
  452. HIF_DISABLE_TYPE_PROBE_ERROR,
  453. HIF_DISABLE_TYPE_REINIT_ERROR,
  454. HIF_DISABLE_TYPE_REMOVE,
  455. HIF_DISABLE_TYPE_SHUTDOWN,
  456. HIF_DISABLE_TYPE_MAX
  457. };
  458. /**
  459. * enum hif_device_config_opcode: configure mode
  460. *
  461. * @HIF_DEVICE_POWER_STATE: device power state
  462. * @HIF_DEVICE_GET_BLOCK_SIZE: get block size
  463. * @HIF_DEVICE_GET_ADDR: get block address
  464. * @HIF_DEVICE_GET_PENDING_EVENTS_FUNC: get pending events functions
  465. * @HIF_DEVICE_GET_IRQ_PROC_MODE: get irq proc mode
  466. * @HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC: receive event function
  467. * @HIF_DEVICE_POWER_STATE_CHANGE: change power state
  468. * @HIF_DEVICE_GET_IRQ_YIELD_PARAMS: get yield params
  469. * @HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT: configure scatter request
  470. * @HIF_DEVICE_GET_OS_DEVICE: get OS device
  471. * @HIF_DEVICE_DEBUG_BUS_STATE: debug bus state
  472. * @HIF_BMI_DONE: bmi done
  473. * @HIF_DEVICE_SET_TARGET_TYPE: set target type
  474. * @HIF_DEVICE_SET_HTC_CONTEXT: set htc context
  475. * @HIF_DEVICE_GET_HTC_CONTEXT: get htc context
  476. */
  477. enum hif_device_config_opcode {
  478. HIF_DEVICE_POWER_STATE = 0,
  479. HIF_DEVICE_GET_BLOCK_SIZE,
  480. HIF_DEVICE_GET_FIFO_ADDR,
  481. HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
  482. HIF_DEVICE_GET_IRQ_PROC_MODE,
  483. HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
  484. HIF_DEVICE_POWER_STATE_CHANGE,
  485. HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
  486. HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
  487. HIF_DEVICE_GET_OS_DEVICE,
  488. HIF_DEVICE_DEBUG_BUS_STATE,
  489. HIF_BMI_DONE,
  490. HIF_DEVICE_SET_TARGET_TYPE,
  491. HIF_DEVICE_SET_HTC_CONTEXT,
  492. HIF_DEVICE_GET_HTC_CONTEXT,
  493. };
  494. #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
  495. struct HID_ACCESS_LOG {
  496. uint32_t seqnum;
  497. bool is_write;
  498. void *addr;
  499. uint32_t value;
  500. };
  501. #endif
  502. void hif_reg_write(struct hif_opaque_softc *hif_ctx, uint32_t offset,
  503. uint32_t value);
  504. uint32_t hif_reg_read(struct hif_opaque_softc *hif_ctx, uint32_t offset);
  505. #define HIF_MAX_DEVICES 1
  506. /**
  507. * struct htc_callbacks - Structure for HTC Callbacks methods
  508. * @context: context to pass to the dsrhandler
  509. * note : rwCompletionHandler is provided the context
  510. * passed to hif_read_write
  511. * @rwCompletionHandler: Read / write completion handler
  512. * @dsrHandler: DSR Handler
  513. */
  514. struct htc_callbacks {
  515. void *context;
  516. QDF_STATUS(*rw_compl_handler)(void *rw_ctx, QDF_STATUS status);
  517. QDF_STATUS(*dsr_handler)(void *context);
  518. };
  519. /**
  520. * struct hif_driver_state_callbacks - Callbacks for HIF to query Driver state
  521. * @context: Private data context
  522. * @set_recovery_in_progress: To Set Driver state for recovery in progress
  523. * @is_recovery_in_progress: Query if driver state is recovery in progress
  524. * @is_load_unload_in_progress: Query if driver state Load/Unload in Progress
  525. * @is_driver_unloading: Query if driver is unloading.
  526. * @get_bandwidth_level: Query current bandwidth level for the driver
  527. * This Structure provides callback pointer for HIF to query hdd for driver
  528. * states.
  529. */
  530. struct hif_driver_state_callbacks {
  531. void *context;
  532. void (*set_recovery_in_progress)(void *context, uint8_t val);
  533. bool (*is_recovery_in_progress)(void *context);
  534. bool (*is_load_unload_in_progress)(void *context);
  535. bool (*is_driver_unloading)(void *context);
  536. bool (*is_target_ready)(void *context);
  537. int (*get_bandwidth_level)(void *context);
  538. };
  539. /* This API detaches the HTC layer from the HIF device */
  540. void hif_detach_htc(struct hif_opaque_softc *hif_ctx);
  541. /****************************************************************/
  542. /* BMI and Diag window abstraction */
  543. /****************************************************************/
  544. #define HIF_BMI_EXCHANGE_NO_TIMEOUT ((uint32_t)(0))
  545. #define DIAG_TRANSFER_LIMIT 2048U /* maximum number of bytes that can be
  546. * handled atomically by
  547. * DiagRead/DiagWrite
  548. */
  549. #ifdef WLAN_FEATURE_BMI
  550. /*
  551. * API to handle HIF-specific BMI message exchanges, this API is synchronous
  552. * and only allowed to be called from a context that can block (sleep)
  553. */
  554. QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *hif_ctx,
  555. qdf_dma_addr_t cmd, qdf_dma_addr_t rsp,
  556. uint8_t *pSendMessage, uint32_t Length,
  557. uint8_t *pResponseMessage,
  558. uint32_t *pResponseLength, uint32_t TimeoutMS);
  559. void hif_register_bmi_callbacks(struct hif_opaque_softc *hif_ctx);
  560. bool hif_needs_bmi(struct hif_opaque_softc *hif_ctx);
  561. #else /* WLAN_FEATURE_BMI */
  562. static inline void
  563. hif_register_bmi_callbacks(struct hif_opaque_softc *hif_ctx)
  564. {
  565. }
  566. static inline bool
  567. hif_needs_bmi(struct hif_opaque_softc *hif_ctx)
  568. {
  569. return false;
  570. }
  571. #endif /* WLAN_FEATURE_BMI */
  572. /*
  573. * APIs to handle HIF specific diagnostic read accesses. These APIs are
  574. * synchronous and only allowed to be called from a context that
  575. * can block (sleep). They are not high performance APIs.
  576. *
  577. * hif_diag_read_access reads a 4 Byte aligned/length value from a
  578. * Target register or memory word.
  579. *
  580. * hif_diag_read_mem reads an arbitrary length of arbitrarily aligned memory.
  581. */
  582. QDF_STATUS hif_diag_read_access(struct hif_opaque_softc *hif_ctx,
  583. uint32_t address, uint32_t *data);
  584. QDF_STATUS hif_diag_read_mem(struct hif_opaque_softc *hif_ctx, uint32_t address,
  585. uint8_t *data, int nbytes);
  586. void hif_dump_target_memory(struct hif_opaque_softc *hif_ctx,
  587. void *ramdump_base, uint32_t address, uint32_t size);
  588. /*
  589. * APIs to handle HIF specific diagnostic write accesses. These APIs are
  590. * synchronous and only allowed to be called from a context that
  591. * can block (sleep).
  592. * They are not high performance APIs.
  593. *
  594. * hif_diag_write_access writes a 4 Byte aligned/length value to a
  595. * Target register or memory word.
  596. *
  597. * hif_diag_write_mem writes an arbitrary length of arbitrarily aligned memory.
  598. */
  599. QDF_STATUS hif_diag_write_access(struct hif_opaque_softc *hif_ctx,
  600. uint32_t address, uint32_t data);
  601. QDF_STATUS hif_diag_write_mem(struct hif_opaque_softc *hif_ctx,
  602. uint32_t address, uint8_t *data, int nbytes);
  603. typedef void (*fastpath_msg_handler)(void *, qdf_nbuf_t *, uint32_t);
  604. void hif_enable_polled_mode(struct hif_opaque_softc *hif_ctx);
  605. bool hif_is_polled_mode_enabled(struct hif_opaque_softc *hif_ctx);
  606. /*
  607. * Set the FASTPATH_mode_on flag in sc, for use by data path
  608. */
  609. #ifdef WLAN_FEATURE_FASTPATH
  610. void hif_enable_fastpath(struct hif_opaque_softc *hif_ctx);
  611. bool hif_is_fastpath_mode_enabled(struct hif_opaque_softc *hif_ctx);
  612. void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret);
  613. int hif_ce_fastpath_cb_register(struct hif_opaque_softc *hif_ctx,
  614. fastpath_msg_handler handler, void *context);
  615. #else
  616. static inline int hif_ce_fastpath_cb_register(struct hif_opaque_softc *hif_ctx,
  617. fastpath_msg_handler handler,
  618. void *context)
  619. {
  620. return QDF_STATUS_E_FAILURE;
  621. }
  622. static inline void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret)
  623. {
  624. return NULL;
  625. }
  626. #endif
  627. /*
  628. * Enable/disable CDC max performance workaround
  629. * For max-performace set this to 0
  630. * To allow SoC to enter sleep set this to 1
  631. */
  632. #define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0
  633. void hif_ipa_get_ce_resource(struct hif_opaque_softc *hif_ctx,
  634. qdf_shared_mem_t **ce_sr,
  635. uint32_t *ce_sr_ring_size,
  636. qdf_dma_addr_t *ce_reg_paddr);
  637. /**
  638. * @brief List of callbacks - filled in by HTC.
  639. */
  640. struct hif_msg_callbacks {
  641. void *Context;
  642. /**< context meaningful to HTC */
  643. QDF_STATUS (*txCompletionHandler)(void *Context, qdf_nbuf_t wbuf,
  644. uint32_t transferID,
  645. uint32_t toeplitz_hash_result);
  646. QDF_STATUS (*rxCompletionHandler)(void *Context, qdf_nbuf_t wbuf,
  647. uint8_t pipeID);
  648. void (*txResourceAvailHandler)(void *context, uint8_t pipe);
  649. void (*fwEventHandler)(void *context, QDF_STATUS status);
  650. void (*update_bundle_stats)(void *context, uint8_t no_of_pkt_in_bundle);
  651. };
  652. enum hif_target_status {
  653. TARGET_STATUS_CONNECTED = 0, /* target connected */
  654. TARGET_STATUS_RESET, /* target got reset */
  655. TARGET_STATUS_EJECT, /* target got ejected */
  656. TARGET_STATUS_SUSPEND /*target got suspend */
  657. };
  658. /**
  659. * enum hif_attribute_flags: configure hif
  660. *
  661. * @HIF_LOWDESC_CE_CFG: Configure HIF with Low descriptor CE
  662. * @HIF_LOWDESC_CE_NO_PKTLOG_CFG: Configure HIF with Low descriptor
  663. * + No pktlog CE
  664. */
  665. enum hif_attribute_flags {
  666. HIF_LOWDESC_CE_CFG = 1,
  667. HIF_LOWDESC_CE_NO_PKTLOG_CFG
  668. };
  669. #define HIF_DATA_ATTR_SET_TX_CLASSIFY(attr, v) \
  670. (attr |= (v & 0x01) << 5)
  671. #define HIF_DATA_ATTR_SET_ENCAPSULATION_TYPE(attr, v) \
  672. (attr |= (v & 0x03) << 6)
  673. #define HIF_DATA_ATTR_SET_ADDR_X_SEARCH_DISABLE(attr, v) \
  674. (attr |= (v & 0x01) << 13)
  675. #define HIF_DATA_ATTR_SET_ADDR_Y_SEARCH_DISABLE(attr, v) \
  676. (attr |= (v & 0x01) << 14)
  677. #define HIF_DATA_ATTR_SET_TOEPLITZ_HASH_ENABLE(attr, v) \
  678. (attr |= (v & 0x01) << 15)
  679. #define HIF_DATA_ATTR_SET_PACKET_OR_RESULT_OFFSET(attr, v) \
  680. (attr |= (v & 0x0FFF) << 16)
  681. #define HIF_DATA_ATTR_SET_ENABLE_11H(attr, v) \
  682. (attr |= (v & 0x01) << 30)
  683. struct hif_ul_pipe_info {
  684. unsigned int nentries;
  685. unsigned int nentries_mask;
  686. unsigned int sw_index;
  687. unsigned int write_index; /* cached copy */
  688. unsigned int hw_index; /* cached copy */
  689. void *base_addr_owner_space; /* Host address space */
  690. qdf_dma_addr_t base_addr_CE_space; /* CE address space */
  691. };
  692. struct hif_dl_pipe_info {
  693. unsigned int nentries;
  694. unsigned int nentries_mask;
  695. unsigned int sw_index;
  696. unsigned int write_index; /* cached copy */
  697. unsigned int hw_index; /* cached copy */
  698. void *base_addr_owner_space; /* Host address space */
  699. qdf_dma_addr_t base_addr_CE_space; /* CE address space */
  700. };
  701. struct hif_pipe_addl_info {
  702. uint32_t pci_mem;
  703. uint32_t ctrl_addr;
  704. struct hif_ul_pipe_info ul_pipe;
  705. struct hif_dl_pipe_info dl_pipe;
  706. };
  707. #ifdef CONFIG_SLUB_DEBUG_ON
  708. #define MSG_FLUSH_NUM 16
  709. #else /* PERF build */
  710. #define MSG_FLUSH_NUM 32
  711. #endif /* SLUB_DEBUG_ON */
  712. struct hif_bus_id;
  713. void hif_claim_device(struct hif_opaque_softc *hif_ctx);
  714. QDF_STATUS hif_get_config_item(struct hif_opaque_softc *hif_ctx,
  715. int opcode, void *config, uint32_t config_len);
  716. void hif_set_mailbox_swap(struct hif_opaque_softc *hif_ctx);
  717. void hif_mask_interrupt_call(struct hif_opaque_softc *hif_ctx);
  718. void hif_post_init(struct hif_opaque_softc *hif_ctx, void *hHTC,
  719. struct hif_msg_callbacks *callbacks);
  720. QDF_STATUS hif_start(struct hif_opaque_softc *hif_ctx);
  721. void hif_stop(struct hif_opaque_softc *hif_ctx);
  722. void hif_flush_surprise_remove(struct hif_opaque_softc *hif_ctx);
  723. void hif_dump(struct hif_opaque_softc *hif_ctx, uint8_t CmdId, bool start);
  724. void hif_trigger_dump(struct hif_opaque_softc *hif_ctx,
  725. uint8_t cmd_id, bool start);
  726. QDF_STATUS hif_send_head(struct hif_opaque_softc *hif_ctx, uint8_t PipeID,
  727. uint32_t transferID, uint32_t nbytes,
  728. qdf_nbuf_t wbuf, uint32_t data_attr);
  729. void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t PipeID,
  730. int force);
  731. void hif_shut_down_device(struct hif_opaque_softc *hif_ctx);
  732. void hif_get_default_pipe(struct hif_opaque_softc *hif_ctx, uint8_t *ULPipe,
  733. uint8_t *DLPipe);
  734. int hif_map_service_to_pipe(struct hif_opaque_softc *hif_ctx, uint16_t svc_id,
  735. uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled,
  736. int *dl_is_polled);
  737. uint16_t
  738. hif_get_free_queue_number(struct hif_opaque_softc *hif_ctx, uint8_t PipeID);
  739. void *hif_get_targetdef(struct hif_opaque_softc *hif_ctx);
  740. uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset);
  741. void hif_set_target_sleep(struct hif_opaque_softc *hif_ctx, bool sleep_ok,
  742. bool wait_for_it);
  743. int hif_check_fw_reg(struct hif_opaque_softc *hif_ctx);
  744. #ifndef HIF_PCI
  745. static inline int hif_check_soc_status(struct hif_opaque_softc *hif_ctx)
  746. {
  747. return 0;
  748. }
  749. #else
  750. int hif_check_soc_status(struct hif_opaque_softc *hif_ctx);
  751. #endif
  752. void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version,
  753. u32 *revision, const char **target_name);
  754. #ifdef RECEIVE_OFFLOAD
  755. /**
  756. * hif_offld_flush_cb_register() - Register the offld flush callback
  757. * @scn: HIF opaque context
  758. * @offld_flush_handler: Flush callback is either ol_flush, incase of rx_thread
  759. * Or GRO/LRO flush when RxThread is not enabled. Called
  760. * with corresponding context for flush.
  761. * Return: None
  762. */
  763. void hif_offld_flush_cb_register(struct hif_opaque_softc *scn,
  764. void (offld_flush_handler)(void *ol_ctx));
  765. /**
  766. * hif_offld_flush_cb_deregister() - deRegister the offld flush callback
  767. * @scn: HIF opaque context
  768. *
  769. * Return: None
  770. */
  771. void hif_offld_flush_cb_deregister(struct hif_opaque_softc *scn);
  772. #endif
  773. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  774. /**
  775. * hif_exec_should_yield() - Check if hif napi context should yield
  776. * @hif_ctx - HIF opaque context
  777. * @grp_id - grp_id of the napi for which check needs to be done
  778. *
  779. * The function uses grp_id to look for NAPI and checks if NAPI needs to
  780. * yield. HIF_EXT_GROUP_MAX_YIELD_DURATION_NS is the duration used for
  781. * yield decision.
  782. *
  783. * Return: true if NAPI needs to yield, else false
  784. */
  785. bool hif_exec_should_yield(struct hif_opaque_softc *hif_ctx, uint grp_id);
  786. #else
  787. static inline bool hif_exec_should_yield(struct hif_opaque_softc *hif_ctx,
  788. uint grp_id)
  789. {
  790. return false;
  791. }
  792. #endif
  793. void hif_disable_isr(struct hif_opaque_softc *hif_ctx);
  794. void hif_reset_soc(struct hif_opaque_softc *hif_ctx);
  795. void hif_save_htc_htt_config_endpoint(struct hif_opaque_softc *hif_ctx,
  796. int htc_htt_tx_endpoint);
  797. /**
  798. * hif_open() - Create hif handle
  799. * @qdf_ctx: qdf context
  800. * @mode: Driver Mode
  801. * @bus_type: Bus Type
  802. * @cbk: CDS Callbacks
  803. * @psoc: psoc object manager
  804. *
  805. * API to open HIF Context
  806. *
  807. * Return: HIF Opaque Pointer
  808. */
  809. struct hif_opaque_softc *hif_open(qdf_device_t qdf_ctx,
  810. uint32_t mode,
  811. enum qdf_bus_type bus_type,
  812. struct hif_driver_state_callbacks *cbk,
  813. struct wlan_objmgr_psoc *psoc);
  814. void hif_close(struct hif_opaque_softc *hif_ctx);
  815. QDF_STATUS hif_enable(struct hif_opaque_softc *hif_ctx, struct device *dev,
  816. void *bdev, const struct hif_bus_id *bid,
  817. enum qdf_bus_type bus_type,
  818. enum hif_enable_type type);
  819. void hif_disable(struct hif_opaque_softc *hif_ctx, enum hif_disable_type type);
  820. #ifdef CE_TASKLET_DEBUG_ENABLE
  821. void hif_enable_ce_latency_stats(struct hif_opaque_softc *hif_ctx,
  822. uint8_t value);
  823. #endif
  824. void hif_display_stats(struct hif_opaque_softc *hif_ctx);
  825. void hif_clear_stats(struct hif_opaque_softc *hif_ctx);
  826. /**
  827. * enum wlan_rtpm_dbgid - runtime pm put/get debug id
  828. * @RTPM_ID_RESVERD: Reserved
  829. * @RTPM_ID_WMI: WMI sending msg, expect put happen at
  830. * tx completion from CE level directly.
  831. * @RTPM_ID_HTC: pkt sending by HTT_DATA_MSG_SVC, expect
  832. * put from fw response or just in
  833. * htc_issue_packets
  834. * @RTPM_ID_QOS_NOTIFY: pm qos notifer
  835. * @RTPM_ID_DP_TX_DESC_ALLOC_FREE: tx desc alloc/free
  836. * @RTPM_ID_CE_SEND_FAST: operation in ce_send_fast, not include
  837. * the pkt put happens outside this function
  838. * @RTPM_ID_SUSPEND_RESUME: suspend/resume in hdd
  839. * @RTPM_ID_DW_TX_HW_ENQUEUE: operation in functin dp_tx_hw_enqueue
  840. * @RTPM_ID_HAL_REO_CMD: HAL_REO_CMD operation
  841. * @RTPM_ID_DP_PRINT_RING_STATS: operation in dp_print_ring_stats
  842. */
  843. /* New value added to the enum must also be reflected in function
  844. * rtpm_string_from_dbgid()
  845. */
  846. typedef enum {
  847. RTPM_ID_RESVERD = 0,
  848. RTPM_ID_WMI = 1,
  849. RTPM_ID_HTC = 2,
  850. RTPM_ID_QOS_NOTIFY = 3,
  851. RTPM_ID_DP_TX_DESC_ALLOC_FREE = 4,
  852. RTPM_ID_CE_SEND_FAST = 5,
  853. RTPM_ID_SUSPEND_RESUME = 6,
  854. RTPM_ID_DW_TX_HW_ENQUEUE = 7,
  855. RTPM_ID_HAL_REO_CMD = 8,
  856. RTPM_ID_DP_PRINT_RING_STATS = 9,
  857. RTPM_ID_MAX,
  858. } wlan_rtpm_dbgid;
  859. /**
  860. * rtpm_string_from_dbgid() - Convert dbgid to respective string
  861. * @id - debug id
  862. *
  863. * Debug support function to convert dbgid to string.
  864. * Please note to add new string in the array at index equal to
  865. * its enum value in wlan_rtpm_dbgid.
  866. */
  867. static inline char *rtpm_string_from_dbgid(wlan_rtpm_dbgid id)
  868. {
  869. static const char *strings[] = { "RTPM_ID_RESVERD",
  870. "RTPM_ID_WMI",
  871. "RTPM_ID_HTC",
  872. "RTPM_ID_QOS_NOTIFY",
  873. "RTPM_ID_DP_TX_DESC_ALLOC_FREE",
  874. "RTPM_ID_CE_SEND_FAST",
  875. "RTPM_ID_SUSPEND_RESUME",
  876. "RTPM_ID_DW_TX_HW_ENQUEUE",
  877. "RTPM_ID_HAL_REO_CMD",
  878. "RTPM_ID_DP_PRINT_RING_STATS",
  879. "RTPM_ID_MAX"};
  880. return (char *)strings[id];
  881. }
  882. #ifdef FEATURE_RUNTIME_PM
  883. struct hif_pm_runtime_lock;
  884. void hif_fastpath_resume(struct hif_opaque_softc *hif_ctx);
  885. int hif_pm_runtime_get_sync(struct hif_opaque_softc *hif_ctx,
  886. wlan_rtpm_dbgid rtpm_dbgid);
  887. int hif_pm_runtime_put_sync_suspend(struct hif_opaque_softc *hif_ctx,
  888. wlan_rtpm_dbgid rtpm_dbgid);
  889. int hif_pm_runtime_request_resume(struct hif_opaque_softc *hif_ctx);
  890. int hif_pm_runtime_get(struct hif_opaque_softc *hif_ctx,
  891. wlan_rtpm_dbgid rtpm_dbgid);
  892. void hif_pm_runtime_get_noresume(struct hif_opaque_softc *hif_ctx,
  893. wlan_rtpm_dbgid rtpm_dbgid);
  894. int hif_pm_runtime_put(struct hif_opaque_softc *hif_ctx,
  895. wlan_rtpm_dbgid rtpm_dbgid);
  896. int hif_pm_runtime_put_noidle(struct hif_opaque_softc *hif_ctx,
  897. wlan_rtpm_dbgid rtpm_dbgid);
  898. void hif_pm_runtime_mark_last_busy(struct hif_opaque_softc *hif_ctx);
  899. int hif_runtime_lock_init(qdf_runtime_lock_t *lock, const char *name);
  900. void hif_runtime_lock_deinit(struct hif_opaque_softc *hif_ctx,
  901. struct hif_pm_runtime_lock *lock);
  902. int hif_pm_runtime_prevent_suspend(struct hif_opaque_softc *ol_sc,
  903. struct hif_pm_runtime_lock *lock);
  904. int hif_pm_runtime_allow_suspend(struct hif_opaque_softc *ol_sc,
  905. struct hif_pm_runtime_lock *lock);
  906. int hif_pm_runtime_prevent_suspend_timeout(struct hif_opaque_softc *ol_sc,
  907. struct hif_pm_runtime_lock *lock, unsigned int delay);
  908. bool hif_pm_runtime_is_suspended(struct hif_opaque_softc *hif_ctx);
  909. int hif_pm_runtime_get_monitor_wake_intr(struct hif_opaque_softc *hif_ctx);
  910. void hif_pm_runtime_set_monitor_wake_intr(struct hif_opaque_softc *hif_ctx,
  911. int val);
  912. void hif_pm_runtime_check_and_request_resume(struct hif_opaque_softc *hif_ctx);
  913. void hif_pm_runtime_mark_dp_rx_busy(struct hif_opaque_softc *hif_ctx);
  914. int hif_pm_runtime_is_dp_rx_busy(struct hif_opaque_softc *hif_ctx);
  915. qdf_time_t hif_pm_runtime_get_dp_rx_busy_mark(struct hif_opaque_softc *hif_ctx);
  916. int hif_pm_runtime_sync_resume(struct hif_opaque_softc *hif_ctx);
  917. #else
  918. struct hif_pm_runtime_lock {
  919. const char *name;
  920. };
  921. static inline void hif_fastpath_resume(struct hif_opaque_softc *hif_ctx) {}
  922. static inline int
  923. hif_pm_runtime_get_sync(struct hif_opaque_softc *hif_ctx,
  924. wlan_rtpm_dbgid rtpm_dbgid)
  925. { return 0; }
  926. static inline int
  927. hif_pm_runtime_put_sync_suspend(struct hif_opaque_softc *hif_ctx,
  928. wlan_rtpm_dbgid rtpm_dbgid)
  929. { return 0; }
  930. static inline int
  931. hif_pm_runtime_request_resume(struct hif_opaque_softc *hif_ctx)
  932. { return 0; }
  933. static inline void
  934. hif_pm_runtime_get_noresume(struct hif_opaque_softc *hif_ctx,
  935. wlan_rtpm_dbgid rtpm_dbgid)
  936. {}
  937. static inline int
  938. hif_pm_runtime_get(struct hif_opaque_softc *hif_ctx, wlan_rtpm_dbgid rtpm_dbgid)
  939. { return 0; }
  940. static inline int
  941. hif_pm_runtime_put(struct hif_opaque_softc *hif_ctx, wlan_rtpm_dbgid rtpm_dbgid)
  942. { return 0; }
  943. static inline int
  944. hif_pm_runtime_put_noidle(struct hif_opaque_softc *hif_ctx,
  945. wlan_rtpm_dbgid rtpm_dbgid)
  946. { return 0; }
  947. static inline void
  948. hif_pm_runtime_mark_last_busy(struct hif_opaque_softc *hif_ctx) {};
  949. static inline int hif_runtime_lock_init(qdf_runtime_lock_t *lock,
  950. const char *name)
  951. { return 0; }
  952. static inline void
  953. hif_runtime_lock_deinit(struct hif_opaque_softc *hif_ctx,
  954. struct hif_pm_runtime_lock *lock) {}
  955. static inline int hif_pm_runtime_prevent_suspend(struct hif_opaque_softc *ol_sc,
  956. struct hif_pm_runtime_lock *lock)
  957. { return 0; }
  958. static inline int hif_pm_runtime_allow_suspend(struct hif_opaque_softc *ol_sc,
  959. struct hif_pm_runtime_lock *lock)
  960. { return 0; }
  961. static inline int
  962. hif_pm_runtime_prevent_suspend_timeout(struct hif_opaque_softc *ol_sc,
  963. struct hif_pm_runtime_lock *lock, unsigned int delay)
  964. { return 0; }
  965. static inline bool hif_pm_runtime_is_suspended(struct hif_opaque_softc *hif_ctx)
  966. { return false; }
  967. static inline int
  968. hif_pm_runtime_get_monitor_wake_intr(struct hif_opaque_softc *hif_ctx)
  969. { return 0; }
  970. static inline void
  971. hif_pm_runtime_set_monitor_wake_intr(struct hif_opaque_softc *hif_ctx, int val)
  972. { return; }
  973. static inline void
  974. hif_pm_runtime_check_and_request_resume(struct hif_opaque_softc *hif_ctx)
  975. { return; }
  976. static inline void
  977. hif_pm_runtime_mark_dp_rx_busy(struct hif_opaque_softc *hif_ctx) {};
  978. static inline int
  979. hif_pm_runtime_is_dp_rx_busy(struct hif_opaque_softc *hif_ctx)
  980. { return 0; }
  981. static inline qdf_time_t
  982. hif_pm_runtime_get_dp_rx_busy_mark(struct hif_opaque_softc *hif_ctx)
  983. { return 0; }
  984. static inline int hif_pm_runtime_sync_resume(struct hif_opaque_softc *hif_ctx)
  985. { return 0; }
  986. #endif
  987. void hif_enable_power_management(struct hif_opaque_softc *hif_ctx,
  988. bool is_packet_log_enabled);
  989. void hif_disable_power_management(struct hif_opaque_softc *hif_ctx);
  990. void hif_vote_link_down(struct hif_opaque_softc *hif_ctx);
  991. void hif_vote_link_up(struct hif_opaque_softc *hif_ctx);
  992. bool hif_can_suspend_link(struct hif_opaque_softc *hif_ctx);
  993. #ifdef IPA_OFFLOAD
  994. /**
  995. * hif_get_ipa_hw_type() - get IPA hw type
  996. *
  997. * This API return the IPA hw type.
  998. *
  999. * Return: IPA hw type
  1000. */
  1001. static inline
  1002. enum ipa_hw_type hif_get_ipa_hw_type(void)
  1003. {
  1004. return ipa_get_hw_type();
  1005. }
  1006. /**
  1007. * hif_get_ipa_present() - get IPA hw status
  1008. *
  1009. * This API return the IPA hw status.
  1010. *
  1011. * Return: true if IPA is present or false otherwise
  1012. */
  1013. static inline
  1014. bool hif_get_ipa_present(void)
  1015. {
  1016. if (ipa_uc_reg_rdyCB(NULL) != -EPERM)
  1017. return true;
  1018. else
  1019. return false;
  1020. }
  1021. #endif
  1022. int hif_bus_resume(struct hif_opaque_softc *hif_ctx);
  1023. /**
  1024. * hif_bus_ealry_suspend() - stop non wmi tx traffic
  1025. * @context: hif context
  1026. */
  1027. int hif_bus_early_suspend(struct hif_opaque_softc *hif_ctx);
  1028. /**
  1029. * hif_bus_late_resume() - resume non wmi traffic
  1030. * @context: hif context
  1031. */
  1032. int hif_bus_late_resume(struct hif_opaque_softc *hif_ctx);
  1033. int hif_bus_suspend(struct hif_opaque_softc *hif_ctx);
  1034. int hif_bus_resume_noirq(struct hif_opaque_softc *hif_ctx);
  1035. int hif_bus_suspend_noirq(struct hif_opaque_softc *hif_ctx);
  1036. /**
  1037. * hif_apps_irqs_enable() - Enables all irqs from the APPS side
  1038. * @hif_ctx: an opaque HIF handle to use
  1039. *
  1040. * As opposed to the standard hif_irq_enable, this function always applies to
  1041. * the APPS side kernel interrupt handling.
  1042. *
  1043. * Return: errno
  1044. */
  1045. int hif_apps_irqs_enable(struct hif_opaque_softc *hif_ctx);
  1046. /**
  1047. * hif_apps_irqs_disable() - Disables all irqs from the APPS side
  1048. * @hif_ctx: an opaque HIF handle to use
  1049. *
  1050. * As opposed to the standard hif_irq_disable, this function always applies to
  1051. * the APPS side kernel interrupt handling.
  1052. *
  1053. * Return: errno
  1054. */
  1055. int hif_apps_irqs_disable(struct hif_opaque_softc *hif_ctx);
  1056. /**
  1057. * hif_apps_wake_irq_enable() - Enables the wake irq from the APPS side
  1058. * @hif_ctx: an opaque HIF handle to use
  1059. *
  1060. * As opposed to the standard hif_irq_enable, this function always applies to
  1061. * the APPS side kernel interrupt handling.
  1062. *
  1063. * Return: errno
  1064. */
  1065. int hif_apps_wake_irq_enable(struct hif_opaque_softc *hif_ctx);
  1066. /**
  1067. * hif_apps_wake_irq_disable() - Disables the wake irq from the APPS side
  1068. * @hif_ctx: an opaque HIF handle to use
  1069. *
  1070. * As opposed to the standard hif_irq_disable, this function always applies to
  1071. * the APPS side kernel interrupt handling.
  1072. *
  1073. * Return: errno
  1074. */
  1075. int hif_apps_wake_irq_disable(struct hif_opaque_softc *hif_ctx);
  1076. /**
  1077. * hif_apps_enable_irq_wake() - Enables the irq wake from the APPS side
  1078. * @hif_ctx: an opaque HIF handle to use
  1079. *
  1080. * This function always applies to the APPS side kernel interrupt handling
  1081. * to wake the system from suspend.
  1082. *
  1083. * Return: errno
  1084. */
  1085. int hif_apps_enable_irq_wake(struct hif_opaque_softc *hif_ctx);
  1086. /**
  1087. * hif_apps_disable_irq_wake() - Disables the wake irq from the APPS side
  1088. * @hif_ctx: an opaque HIF handle to use
  1089. *
  1090. * This function always applies to the APPS side kernel interrupt handling
  1091. * to disable the wake irq.
  1092. *
  1093. * Return: errno
  1094. */
  1095. int hif_apps_disable_irq_wake(struct hif_opaque_softc *hif_ctx);
  1096. #ifdef FEATURE_RUNTIME_PM
  1097. int hif_pre_runtime_suspend(struct hif_opaque_softc *hif_ctx);
  1098. void hif_pre_runtime_resume(struct hif_opaque_softc *hif_ctx);
  1099. int hif_runtime_suspend(struct hif_opaque_softc *hif_ctx);
  1100. int hif_runtime_resume(struct hif_opaque_softc *hif_ctx);
  1101. void hif_process_runtime_suspend_success(struct hif_opaque_softc *hif_ctx);
  1102. void hif_process_runtime_suspend_failure(struct hif_opaque_softc *hif_ctx);
  1103. void hif_process_runtime_resume_success(struct hif_opaque_softc *hif_ctx);
  1104. #endif
  1105. int hif_get_irq_num(struct hif_opaque_softc *scn, int *irq, uint32_t size);
  1106. int hif_dump_registers(struct hif_opaque_softc *scn);
  1107. int ol_copy_ramdump(struct hif_opaque_softc *scn);
  1108. void hif_crash_shutdown(struct hif_opaque_softc *hif_ctx);
  1109. void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version,
  1110. u32 *revision, const char **target_name);
  1111. enum qdf_bus_type hif_get_bus_type(struct hif_opaque_softc *hif_hdl);
  1112. struct hif_target_info *hif_get_target_info_handle(struct hif_opaque_softc *
  1113. scn);
  1114. struct hif_config_info *hif_get_ini_handle(struct hif_opaque_softc *hif_ctx);
  1115. struct ramdump_info *hif_get_ramdump_ctx(struct hif_opaque_softc *hif_ctx);
  1116. enum hif_target_status hif_get_target_status(struct hif_opaque_softc *hif_ctx);
  1117. void hif_set_target_status(struct hif_opaque_softc *hif_ctx, enum
  1118. hif_target_status);
  1119. void hif_init_ini_config(struct hif_opaque_softc *hif_ctx,
  1120. struct hif_config_info *cfg);
  1121. void hif_update_tx_ring(struct hif_opaque_softc *osc, u_int32_t num_htt_cmpls);
  1122. qdf_nbuf_t hif_batch_send(struct hif_opaque_softc *osc, qdf_nbuf_t msdu,
  1123. uint32_t transfer_id, u_int32_t len, uint32_t sendhead);
  1124. QDF_STATUS hif_send_single(struct hif_opaque_softc *osc, qdf_nbuf_t msdu,
  1125. uint32_t transfer_id, u_int32_t len);
  1126. int hif_send_fast(struct hif_opaque_softc *osc, qdf_nbuf_t nbuf,
  1127. uint32_t transfer_id, uint32_t download_len);
  1128. void hif_pkt_dl_len_set(void *hif_sc, unsigned int pkt_download_len);
  1129. void hif_ce_war_disable(void);
  1130. void hif_ce_war_enable(void);
  1131. void hif_disable_interrupt(struct hif_opaque_softc *osc, uint32_t pipe_num);
  1132. #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT
  1133. struct hif_pipe_addl_info *hif_get_addl_pipe_info(struct hif_opaque_softc *osc,
  1134. struct hif_pipe_addl_info *hif_info, uint32_t pipe_number);
  1135. uint32_t hif_set_nss_wifiol_mode(struct hif_opaque_softc *osc,
  1136. uint32_t pipe_num);
  1137. int32_t hif_get_nss_wifiol_bypass_nw_process(struct hif_opaque_softc *osc);
  1138. #endif /* QCA_NSS_WIFI_OFFLOAD_SUPPORT */
  1139. void hif_set_bundle_mode(struct hif_opaque_softc *hif_ctx, bool enabled,
  1140. int rx_bundle_cnt);
  1141. int hif_bus_reset_resume(struct hif_opaque_softc *hif_ctx);
  1142. void hif_set_attribute(struct hif_opaque_softc *osc, uint8_t hif_attrib);
  1143. void *hif_get_lro_info(int ctx_id, struct hif_opaque_softc *hif_hdl);
  1144. enum hif_exec_type {
  1145. HIF_EXEC_NAPI_TYPE,
  1146. HIF_EXEC_TASKLET_TYPE,
  1147. };
  1148. typedef uint32_t (*ext_intr_handler)(void *, uint32_t);
  1149. /**
  1150. * hif_get_int_ctx_irq_num() - retrieve an irq num for an interrupt context id
  1151. * @softc: hif opaque context owning the exec context
  1152. * @id: the id of the interrupt context
  1153. *
  1154. * Return: IRQ number of the first (zero'th) IRQ within the interrupt context ID
  1155. * 'id' registered with the OS
  1156. */
  1157. int32_t hif_get_int_ctx_irq_num(struct hif_opaque_softc *softc,
  1158. uint8_t id);
  1159. uint32_t hif_configure_ext_group_interrupts(struct hif_opaque_softc *hif_ctx);
  1160. uint32_t hif_register_ext_group(struct hif_opaque_softc *hif_ctx,
  1161. uint32_t numirq, uint32_t irq[], ext_intr_handler handler,
  1162. void *cb_ctx, const char *context_name,
  1163. enum hif_exec_type type, uint32_t scale);
  1164. void hif_deregister_exec_group(struct hif_opaque_softc *hif_ctx,
  1165. const char *context_name);
  1166. void hif_update_pipe_callback(struct hif_opaque_softc *osc,
  1167. u_int8_t pipeid,
  1168. struct hif_msg_callbacks *callbacks);
  1169. /**
  1170. * hif_print_napi_stats() - Display HIF NAPI stats
  1171. * @hif_ctx - HIF opaque context
  1172. *
  1173. * Return: None
  1174. */
  1175. void hif_print_napi_stats(struct hif_opaque_softc *hif_ctx);
  1176. /* hif_clear_napi_stats() - function clears the stats of the
  1177. * latency when called.
  1178. * @hif_ctx - the HIF context to assign the callback to
  1179. *
  1180. * Return: None
  1181. */
  1182. void hif_clear_napi_stats(struct hif_opaque_softc *hif_ctx);
  1183. #ifdef __cplusplus
  1184. }
  1185. #endif
  1186. #ifdef FORCE_WAKE
  1187. /**
  1188. * hif_force_wake_request() - Function to wake from power collapse
  1189. * @handle: HIF opaque handle
  1190. *
  1191. * Description: API to check if the device is awake or not before
  1192. * read/write to BAR + 4K registers. If device is awake return
  1193. * success otherwise write '1' to
  1194. * PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG which will interrupt
  1195. * the device and does wakeup the PCI and MHI within 50ms
  1196. * and then the device writes a value to
  1197. * PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG to complete the
  1198. * handshake process to let the host know the device is awake.
  1199. *
  1200. * Return: zero - success/non-zero - failure
  1201. */
  1202. int hif_force_wake_request(struct hif_opaque_softc *handle);
  1203. /**
  1204. * hif_force_wake_release() - API to release/reset the SOC wake register
  1205. * from interrupting the device.
  1206. * @handle: HIF opaque handle
  1207. *
  1208. * Description: API to set the
  1209. * PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG to '0'
  1210. * to release the interrupt line.
  1211. *
  1212. * Return: zero - success/non-zero - failure
  1213. */
  1214. int hif_force_wake_release(struct hif_opaque_softc *handle);
  1215. #else
  1216. static inline
  1217. int hif_force_wake_request(struct hif_opaque_softc *handle)
  1218. {
  1219. return 0;
  1220. }
  1221. static inline
  1222. int hif_force_wake_release(struct hif_opaque_softc *handle)
  1223. {
  1224. return 0;
  1225. }
  1226. #endif /* FORCE_WAKE */
  1227. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  1228. /**
  1229. * hif_prevent_link_low_power_states() - Prevent from going to low power states
  1230. * @hif - HIF opaque context
  1231. *
  1232. * Return: 0 on success. Error code on failure.
  1233. */
  1234. int hif_prevent_link_low_power_states(struct hif_opaque_softc *hif);
  1235. /**
  1236. * hif_allow_link_low_power_states() - Allow link to go to low power states
  1237. * @hif - HIF opaque context
  1238. *
  1239. * Return: None
  1240. */
  1241. void hif_allow_link_low_power_states(struct hif_opaque_softc *hif);
  1242. #else
  1243. static inline
  1244. int hif_prevent_link_low_power_states(struct hif_opaque_softc *hif)
  1245. {
  1246. return 0;
  1247. }
  1248. static inline
  1249. void hif_allow_link_low_power_states(struct hif_opaque_softc *hif)
  1250. {
  1251. }
  1252. #endif
  1253. void *hif_get_dev_ba(struct hif_opaque_softc *hif_handle);
  1254. void *hif_get_dev_ba_ce(struct hif_opaque_softc *hif_handle);
  1255. /**
  1256. * hif_set_initial_wakeup_cb() - set the initial wakeup event handler function
  1257. * @hif_ctx - the HIF context to assign the callback to
  1258. * @callback - the callback to assign
  1259. * @priv - the private data to pass to the callback when invoked
  1260. *
  1261. * Return: None
  1262. */
  1263. void hif_set_initial_wakeup_cb(struct hif_opaque_softc *hif_ctx,
  1264. void (*callback)(void *),
  1265. void *priv);
  1266. /*
  1267. * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked
  1268. * for defined here
  1269. */
  1270. #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)
  1271. ssize_t hif_dump_desc_trace_buf(struct device *dev,
  1272. struct device_attribute *attr, char *buf);
  1273. ssize_t hif_input_desc_trace_buf_index(struct hif_softc *scn,
  1274. const char *buf, size_t size);
  1275. ssize_t hif_ce_en_desc_hist(struct hif_softc *scn,
  1276. const char *buf, size_t size);
  1277. ssize_t hif_disp_ce_enable_desc_data_hist(struct hif_softc *scn, char *buf);
  1278. ssize_t hif_dump_desc_event(struct hif_softc *scn, char *buf);
  1279. #endif/*#if defined(HIF_CONFIG_SLUB_DEBUG_ON)||defined(HIF_CE_DEBUG_DATA_BUF)*/
  1280. /**
  1281. * hif_set_ce_service_max_yield_time() - sets CE service max yield time
  1282. * @hif: hif context
  1283. * @ce_service_max_yield_time: CE service max yield time to set
  1284. *
  1285. * This API storess CE service max yield time in hif context based
  1286. * on ini value.
  1287. *
  1288. * Return: void
  1289. */
  1290. void hif_set_ce_service_max_yield_time(struct hif_opaque_softc *hif,
  1291. uint32_t ce_service_max_yield_time);
  1292. /**
  1293. * hif_get_ce_service_max_yield_time() - get CE service max yield time
  1294. * @hif: hif context
  1295. *
  1296. * This API returns CE service max yield time.
  1297. *
  1298. * Return: CE service max yield time
  1299. */
  1300. unsigned long long
  1301. hif_get_ce_service_max_yield_time(struct hif_opaque_softc *hif);
  1302. /**
  1303. * hif_set_ce_service_max_rx_ind_flush() - sets CE service max rx ind flush
  1304. * @hif: hif context
  1305. * @ce_service_max_rx_ind_flush: CE service max rx ind flush to set
  1306. *
  1307. * This API stores CE service max rx ind flush in hif context based
  1308. * on ini value.
  1309. *
  1310. * Return: void
  1311. */
  1312. void hif_set_ce_service_max_rx_ind_flush(struct hif_opaque_softc *hif,
  1313. uint8_t ce_service_max_rx_ind_flush);
  1314. #ifdef OL_ATH_SMART_LOGGING
  1315. /*
  1316. * hif_log_ce_dump() - Copy all the CE DEST ring to buf
  1317. * @scn : HIF handler
  1318. * @buf_cur: Current pointer in ring buffer
  1319. * @buf_init:Start of the ring buffer
  1320. * @buf_sz: Size of the ring buffer
  1321. * @ce: Copy Engine id
  1322. * @skb_sz: Max size of the SKB buffer to be copied
  1323. *
  1324. * Calls the respective function to dump all the CE SRC/DEST ring descriptors
  1325. * and buffers pointed by them in to the given buf
  1326. *
  1327. * Return: Current pointer in ring buffer
  1328. */
  1329. uint8_t *hif_log_dump_ce(struct hif_softc *scn, uint8_t *buf_cur,
  1330. uint8_t *buf_init, uint32_t buf_sz,
  1331. uint32_t ce, uint32_t skb_sz);
  1332. #endif /* OL_ATH_SMART_LOGGING */
  1333. /*
  1334. * hif_softc_to_hif_opaque_softc - API to convert hif_softc handle
  1335. * to hif_opaque_softc handle
  1336. * @hif_handle - hif_softc type
  1337. *
  1338. * Return: hif_opaque_softc type
  1339. */
  1340. static inline struct hif_opaque_softc *
  1341. hif_softc_to_hif_opaque_softc(struct hif_softc *hif_handle)
  1342. {
  1343. return (struct hif_opaque_softc *)hif_handle;
  1344. }
  1345. #ifdef FORCE_WAKE
  1346. /**
  1347. * hif_srng_init_phase(): Indicate srng initialization phase
  1348. * to avoid force wake as UMAC power collapse is not yet
  1349. * enabled
  1350. * @hif_ctx: hif opaque handle
  1351. * @init_phase: initialization phase
  1352. *
  1353. * Return: None
  1354. */
  1355. void hif_srng_init_phase(struct hif_opaque_softc *hif_ctx,
  1356. bool init_phase);
  1357. #else
  1358. static inline
  1359. void hif_srng_init_phase(struct hif_opaque_softc *hif_ctx,
  1360. bool init_phase)
  1361. {
  1362. }
  1363. #endif /* FORCE_WAKE */
  1364. #ifdef HIF_CE_LOG_INFO
  1365. /**
  1366. * hif_log_ce_info() - API to log ce info
  1367. * @scn: hif handle
  1368. * @data: hang event data buffer
  1369. * @offset: offset at which data needs to be written
  1370. *
  1371. * Return: None
  1372. */
  1373. void hif_log_ce_info(struct hif_softc *scn, uint8_t *data,
  1374. unsigned int *offset);
  1375. #else
  1376. static inline
  1377. void hif_log_ce_info(struct hif_softc *scn, uint8_t *data,
  1378. unsigned int *offset)
  1379. {
  1380. }
  1381. #endif
  1382. #ifdef HIF_CPU_PERF_AFFINE_MASK
  1383. /**
  1384. * hif_config_irq_set_perf_affinity_hint() - API to set affinity
  1385. * @hif_ctx: hif opaque handle
  1386. *
  1387. * This function is used to move the WLAN IRQs to perf cores in
  1388. * case of defconfig builds.
  1389. *
  1390. * Return: None
  1391. */
  1392. void hif_config_irq_set_perf_affinity_hint(
  1393. struct hif_opaque_softc *hif_ctx);
  1394. #else
  1395. static inline void hif_config_irq_set_perf_affinity_hint(
  1396. struct hif_opaque_softc *hif_ctx)
  1397. {
  1398. }
  1399. #endif
  1400. #endif /* _HIF_H_ */