4083155141
Support HW cookie conversion for BE platform. Change-Id: I39058fbf256266557f5e734ba376db4db0731b24 CRs-Fixed: 2929533
372 行
11 KiB
C
372 行
11 KiB
C
/*
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* Copyright (c) 2021 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __DP_BE_H
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#define __DP_BE_H
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#include <dp_types.h>
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#include <hal_be_tx.h>
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/* maximum number of entries in one page of secondary page table */
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#define DP_CC_SPT_PAGE_MAX_ENTRIES 512
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/* maximum number of entries in primary page table */
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#define DP_CC_PPT_MAX_ENTRIES 1024
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/* cookie conversion required CMEM offset from CMEM pool */
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#define DP_CC_MEM_OFFSET_IN_CMEM 0
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/* cookie conversion primary page table size 4K */
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#define DP_CC_PPT_MEM_SIZE 4096
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/* FST required CMEM offset from CMEM pool */
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#define DP_FST_MEM_OFFSET_IN_CMEM \
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(DP_CC_MEM_OFFSET_IN_CMEM + DP_CC_PPT_MEM_SIZE)
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/* lower 9 bits in Desc ID for offset in page of SPT */
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#define DP_CC_DESC_ID_SPT_VA_OS_SHIFT 0
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#define DP_CC_DESC_ID_SPT_VA_OS_MASK 0x1FF
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#define DP_CC_DESC_ID_SPT_VA_OS_LSB 0
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#define DP_CC_DESC_ID_SPT_VA_OS_MSB 8
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/* for 4k unaligned case */
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#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_SHIFT 9
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#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_MASK 0xFFE00
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#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_LSB 9
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#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_MSB 19
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#define DP_CC_PPT_ENTRY_SIZE_4K_UNALIGNED 8
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/* for 4k aligned case */
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#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_SHIFT 10
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#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_MASK 0xFFC00
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#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_LSB 10
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#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_MSB 19
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#define DP_CC_DESC_ID_PPT_PAGE_HIGH_32BIT_4K_ALIGNED_SHIFT 9
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#define DP_CC_DESC_ID_PPT_PAGE_HIGH_32BIT_4K_ALIGNED_MASK 0x200
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#define DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED 4
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/* 4K aligned case, number of bits HW append for one PPT entry value */
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#define DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED 12
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/**
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* struct dp_spt_page_desc - secondary page table page descriptors
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* @next: pointer to next linked SPT page Desc
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* @page_v_addr: page virtual address
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* @page_p_addr: page physical address
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* @ppt_index: entry index in primary page table where this page physical
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address stored
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* @avail_entry_index: index for available entry that store TX/RX Desc VA
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*/
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struct dp_spt_page_desc {
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struct dp_spt_page_desc *next;
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uint8_t *page_v_addr;
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qdf_dma_addr_t page_p_addr;
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uint16_t ppt_index;
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uint16_t avail_entry_index;
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};
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/**
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* struct dp_hw_cookie_conversion_t - main context for HW cookie conversion
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* @cmem_base: CMEM base address for primary page table setup
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* @total_page_num: total DDR page allocated
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* @free_page_num: available DDR page number for TX/RX Desc ID initialization
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* @page_desc_freelist: available page Desc list
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* @page_desc_base: page Desc buffer base address.
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* @page_pool: DDR pages pool
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* @cc_lock: locks for page acquiring/free
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*/
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struct dp_hw_cookie_conversion_t {
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uint32_t cmem_base;
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uint32_t total_page_num;
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uint32_t free_page_num;
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struct dp_spt_page_desc *page_desc_freelist;
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struct dp_spt_page_desc *page_desc_base;
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struct qdf_mem_multi_page_t page_pool;
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qdf_spinlock_t cc_lock;
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};
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/**
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* struct dp_spt_page_desc_list - containor of SPT page desc list info
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* @spt_page_list_head: head of SPT page descriptor list
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* @spt_page_list_tail: tail of SPT page descriptor list
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* @num_spt_pages: number of SPT page descriptor allocated
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*/
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struct dp_spt_page_desc_list {
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struct dp_spt_page_desc *spt_page_list_head;
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struct dp_spt_page_desc *spt_page_list_tail;
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uint16_t num_spt_pages;
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};
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#define DP_CC_SPT_PAGE_UPDATE_VA(_page_base_va, _index, _desc_va) \
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{ ((uint64_t *)(_page_base_va))[_index] = (uint64_t)(_desc_va); }
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/**
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* struct dp_tx_bank_profile - DP wrapper for TCL banks
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* @is_configured: flag indicating if this bank is configured
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* @ref_count: ref count indicating number of users of the bank
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* @bank_config: HAL TX bank configuration
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*/
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struct dp_tx_bank_profile {
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uint8_t is_configured;
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qdf_atomic_t ref_count;
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union hal_tx_bank_config bank_config;
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};
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/**
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* struct dp_soc_be - Extended DP soc for BE targets
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* @soc: dp soc structure
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* @num_bank_profiles: num TX bank profiles
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* @bank_profiles: bank profiles for various TX banks
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* @hw_cc_ctx: core context of HW cookie conversion
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* @tx_spt_page_desc: spt page desc allocated for TX desc pool
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* @rx_spt_page_desc: spt page desc allocated for RX desc pool
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*/
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struct dp_soc_be {
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struct dp_soc soc;
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uint8_t num_bank_profiles;
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qdf_mutex_t tx_bank_lock;
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struct dp_tx_bank_profile *bank_profiles;
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struct dp_hw_cookie_conversion_t hw_cc_ctx;
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struct dp_spt_page_desc_list tx_spt_page_desc[MAX_TXDESC_POOLS];
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struct dp_spt_page_desc_list rx_spt_page_desc[MAX_RXDESC_POOLS];
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};
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/**
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* struct dp_pdev_be - Extended DP pdev for BE targets
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* @pdev: dp pdev structure
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*/
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struct dp_pdev_be {
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struct dp_pdev pdev;
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};
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/**
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* struct dp_vdev_be - Extended DP vdev for BE targets
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* @vdev: dp vdev structure
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* @bank_id: bank_id to be used for TX
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* @vdev_id_check_en: flag if HW vdev_id check is enabled for vdev
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*/
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struct dp_vdev_be {
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struct dp_vdev vdev;
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int8_t bank_id;
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uint8_t vdev_id_check_en;
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};
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/**
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* struct dp_peer_be - Extended DP peer for BE targets
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* @dp_peer: dp peer structure
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*/
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struct dp_peer_be {
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struct dp_peer peer;
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};
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/**
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* dp_get_soc_context_size_be() - get context size for target specific DP soc
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*
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* Return: value in bytes for BE specific soc structure
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*/
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qdf_size_t dp_get_soc_context_size_be(void);
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/**
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* dp_initialize_arch_ops_be() - initialize BE specific arch ops
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* @arch_ops: arch ops pointer
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*
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* Return: none
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*/
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void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops);
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/**
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* dp_get_context_size_be() - get BE specific size for peer/vdev/pdev/soc
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* @arch_ops: arch ops pointer
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*
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* Return: size in bytes for the context_type
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*/
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qdf_size_t dp_get_context_size_be(enum dp_context_type context_type);
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/**
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* dp_get_be_soc_from_dp_soc() - get dp_soc_be from dp_soc
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* @soc: dp_soc pointer
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*
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* Return: dp_soc_be pointer
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*/
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static inline struct dp_soc_be *dp_get_be_soc_from_dp_soc(struct dp_soc *soc)
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{
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return (struct dp_soc_be *)soc;
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}
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/**
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* dp_get_be_pdev_from_dp_pdev() - get dp_pdev_be from dp_pdev
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* @pdev: dp_pdev pointer
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*
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* Return: dp_pdev_be pointer
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*/
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static inline
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struct dp_pdev_be *dp_get_be_pdev_from_dp_pdev(struct dp_pdev *pdev)
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{
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return (struct dp_pdev_be *)pdev;
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}
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/**
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* dp_get_be_vdev_from_dp_vdev() - get dp_vdev_be from dp_vdev
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* @vdev: dp_vdev pointer
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*
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* Return: dp_vdev_be pointer
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*/
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static inline
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struct dp_vdev_be *dp_get_be_vdev_from_dp_vdev(struct dp_vdev *vdev)
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{
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return (struct dp_vdev_be *)vdev;
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}
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/**
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* dp_get_be_peer_from_dp_peer() - get dp_peer_be from dp_peer
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* @peer: dp_peer pointer
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*
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* Return: dp_peer_be pointer
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*/
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static inline
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struct dp_peer_be *dp_get_be_peer_from_dp_peer(struct dp_peer *peer)
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{
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return (struct dp_peer_be *)peer;
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}
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/**
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* dp_cc_spt_page_desc_alloc() - allocate SPT DDR page descriptor from pool
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* @be_soc: beryllium soc handler
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* @list_head: pointer to page desc head
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* @list_tail: pointer to page desc tail
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* @desc_num: number of TX/RX Descs required for SPT pages
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*
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* Return: number of SPT page Desc allocated
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*/
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uint16_t dp_cc_spt_page_desc_alloc(struct dp_soc_be *be_soc,
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struct dp_spt_page_desc **list_head,
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struct dp_spt_page_desc **list_tail,
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uint16_t desc_num);
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/**
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* dp_cc_spt_page_desc_free() - free SPT DDR page descriptor to pool
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* @be_soc: beryllium soc handler
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* @list_head: pointer to page desc head
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* @list_tail: pointer to page desc tail
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* @page_nums: number of page desc freed back to pool
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*/
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void dp_cc_spt_page_desc_free(struct dp_soc_be *be_soc,
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struct dp_spt_page_desc **list_head,
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struct dp_spt_page_desc **list_tail,
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uint16_t page_nums);
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/**
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* dp_cc_desc_id_generate() - generate SW cookie ID according to
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DDR page 4K aligned or not
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* @ppt_index: offset index in primary page table
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* @spt_index: offset index in sceondary DDR page
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* @page_4k_align: DDR page address 4K aligned or not
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*
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* for 4K aligned DDR page, ppt_index offset is using 4 bytes entry,
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* while HW use 8 bytes offset index, need 10th bit to indicate it's
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* in high 32bits or low 32bits.
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* for 4k un-aligned DDR page, ppt_index offset is using 8bytes entry,
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* it's match with HW assuming.
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*
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* Return: cookie ID
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*/
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static inline uint32_t dp_cc_desc_id_generate(uint16_t ppt_index,
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uint16_t spt_index,
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bool page_4k_align)
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{
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uint32_t id = 0;
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if (qdf_likely(page_4k_align))
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id =
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((ppt_index / 2) <<
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DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_SHIFT) |
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((ppt_index % 2) <<
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DP_CC_DESC_ID_PPT_PAGE_HIGH_32BIT_4K_ALIGNED_SHIFT) |
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spt_index;
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else
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id =
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(ppt_index <<
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DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_SHIFT) |
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spt_index;
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return id;
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}
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/**
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* dp_cc_desc_va_find() - find TX/RX Descs virtual address by ID
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* @be_soc: be soc handle
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* @desc_id: TX/RX Dess ID
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* @page_4k_align: DDR page address 4K aligned or not
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*
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* Return: TX/RX Desc virtual address
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*/
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static inline void *dp_cc_desc_find(struct dp_soc *soc,
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uint32_t desc_id,
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bool page_4k_align)
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{
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struct dp_soc_be *be_soc;
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struct dp_hw_cookie_conversion_t *cc_ctx;
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uint16_t ppt_page_id, spt_va_id;
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uint64_t *spt_page_va;
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be_soc = dp_get_be_soc_from_dp_soc(soc);
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cc_ctx = &be_soc->hw_cc_ctx;
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if (qdf_likely(page_4k_align))
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ppt_page_id =
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(((desc_id &
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DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_MASK) >>
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DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_SHIFT) * 2) +
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((desc_id &
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DP_CC_DESC_ID_PPT_PAGE_HIGH_32BIT_4K_ALIGNED_MASK) >>
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DP_CC_DESC_ID_PPT_PAGE_HIGH_32BIT_4K_ALIGNED_SHIFT);
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else
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ppt_page_id =
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(desc_id &
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DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_MASK) >>
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DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_SHIFT;
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spt_va_id = (desc_id & DP_CC_DESC_ID_SPT_VA_OS_MASK) >>
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DP_CC_DESC_ID_SPT_VA_OS_SHIFT;
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/*
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* ppt index in cmem is same order where the page in the
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* page desc array during initialization.
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* entry size in DDR page is 64 bits, then
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* (1) 64 bits OS, (uint64_t *) --> (void *) conversion, no issue.
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* (2) 32 bits OS, TX/RX Desc VA size is 32bits, (uint64_t *) -->
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* (void *) conversion, lower 32 bits from uint64_t is saved, no issue
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* as higer 32 bits is 0.
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*/
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spt_page_va =
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(uint64_t *)cc_ctx->page_desc_base[ppt_page_id].page_v_addr;
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return (void *)(*(spt_page_va + spt_va_id));
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}
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#endif
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