dp_tx.c 113 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "enet.h"
  34. #include "dp_internal.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. /* TODO Add support in TSO */
  42. #define DP_DESC_NUM_FRAG(x) 0
  43. /* disable TQM_BYPASS */
  44. #define TQM_BYPASS_WAR 0
  45. /* invalid peer id for reinject*/
  46. #define DP_INVALID_PEER 0XFFFE
  47. /*mapping between hal encrypt type and cdp_sec_type*/
  48. #define MAX_CDP_SEC_TYPE 12
  49. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  50. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  51. HAL_TX_ENCRYPT_TYPE_WEP_128,
  52. HAL_TX_ENCRYPT_TYPE_WEP_104,
  53. HAL_TX_ENCRYPT_TYPE_WEP_40,
  54. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  56. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  57. HAL_TX_ENCRYPT_TYPE_WAPI,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  59. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  62. #ifdef QCA_TX_LIMIT_CHECK
  63. /**
  64. * dp_tx_limit_check - Check if allocated tx descriptors reached
  65. * soc max limit and pdev max limit
  66. * @vdev: DP vdev handle
  67. *
  68. * Return: true if allocated tx descriptors reached max configured value, else
  69. * false
  70. */
  71. static inline bool
  72. dp_tx_limit_check(struct dp_vdev *vdev)
  73. {
  74. struct dp_pdev *pdev = vdev->pdev;
  75. struct dp_soc *soc = pdev->soc;
  76. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  77. soc->num_tx_allowed) {
  78. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  79. "%s: queued packets are more than max tx, drop the frame",
  80. __func__);
  81. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  82. return true;
  83. }
  84. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  85. pdev->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. return false;
  93. }
  94. /**
  95. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  96. * @vdev: DP pdev handle
  97. *
  98. * Return: void
  99. */
  100. static inline void
  101. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  102. {
  103. struct dp_soc *soc = pdev->soc;
  104. qdf_atomic_inc(&pdev->num_tx_outstanding);
  105. qdf_atomic_inc(&soc->num_tx_outstanding);
  106. }
  107. /**
  108. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  109. * @vdev: DP pdev handle
  110. *
  111. * Return: void
  112. */
  113. static inline void
  114. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  115. {
  116. struct dp_soc *soc = pdev->soc;
  117. qdf_atomic_dec(&pdev->num_tx_outstanding);
  118. qdf_atomic_dec(&soc->num_tx_outstanding);
  119. }
  120. #else //QCA_TX_LIMIT_CHECK
  121. static inline bool
  122. dp_tx_limit_check(struct dp_vdev *vdev)
  123. {
  124. return false;
  125. }
  126. static inline void
  127. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  128. {
  129. }
  130. static inline void
  131. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  132. {
  133. }
  134. #endif //QCA_TX_LIMIT_CHECK
  135. #if defined(FEATURE_TSO)
  136. /**
  137. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  138. *
  139. * @soc - core txrx main context
  140. * @seg_desc - tso segment descriptor
  141. * @num_seg_desc - tso number segment descriptor
  142. */
  143. static void dp_tx_tso_unmap_segment(
  144. struct dp_soc *soc,
  145. struct qdf_tso_seg_elem_t *seg_desc,
  146. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  147. {
  148. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  149. if (qdf_unlikely(!seg_desc)) {
  150. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  151. __func__, __LINE__);
  152. qdf_assert(0);
  153. } else if (qdf_unlikely(!num_seg_desc)) {
  154. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  155. __func__, __LINE__);
  156. qdf_assert(0);
  157. } else {
  158. bool is_last_seg;
  159. /* no tso segment left to do dma unmap */
  160. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  161. return;
  162. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  163. true : false;
  164. qdf_nbuf_unmap_tso_segment(soc->osdev,
  165. seg_desc, is_last_seg);
  166. num_seg_desc->num_seg.tso_cmn_num_seg--;
  167. }
  168. }
  169. /**
  170. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  171. * back to the freelist
  172. *
  173. * @soc - soc device handle
  174. * @tx_desc - Tx software descriptor
  175. */
  176. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  177. struct dp_tx_desc_s *tx_desc)
  178. {
  179. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  180. if (qdf_unlikely(!tx_desc->tso_desc)) {
  181. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  182. "%s %d TSO desc is NULL!",
  183. __func__, __LINE__);
  184. qdf_assert(0);
  185. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  186. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  187. "%s %d TSO num desc is NULL!",
  188. __func__, __LINE__);
  189. qdf_assert(0);
  190. } else {
  191. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  192. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  193. /* Add the tso num segment into the free list */
  194. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  195. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  196. tx_desc->tso_num_desc);
  197. tx_desc->tso_num_desc = NULL;
  198. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  199. }
  200. /* Add the tso segment into the free list*/
  201. dp_tx_tso_desc_free(soc,
  202. tx_desc->pool_id, tx_desc->tso_desc);
  203. tx_desc->tso_desc = NULL;
  204. }
  205. }
  206. #else
  207. static void dp_tx_tso_unmap_segment(
  208. struct dp_soc *soc,
  209. struct qdf_tso_seg_elem_t *seg_desc,
  210. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  211. {
  212. }
  213. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  214. struct dp_tx_desc_s *tx_desc)
  215. {
  216. }
  217. #endif
  218. /**
  219. * dp_tx_desc_release() - Release Tx Descriptor
  220. * @tx_desc : Tx Descriptor
  221. * @desc_pool_id: Descriptor Pool ID
  222. *
  223. * Deallocate all resources attached to Tx descriptor and free the Tx
  224. * descriptor.
  225. *
  226. * Return:
  227. */
  228. static void
  229. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  230. {
  231. struct dp_pdev *pdev = tx_desc->pdev;
  232. struct dp_soc *soc;
  233. uint8_t comp_status = 0;
  234. qdf_assert(pdev);
  235. soc = pdev->soc;
  236. if (tx_desc->frm_type == dp_tx_frm_tso)
  237. dp_tx_tso_desc_release(soc, tx_desc);
  238. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  239. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  240. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  241. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  242. dp_tx_outstanding_dec(pdev);
  243. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  244. qdf_atomic_dec(&pdev->num_tx_exception);
  245. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  246. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  247. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  248. soc->hal_soc);
  249. else
  250. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  251. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  252. "Tx Completion Release desc %d status %d outstanding %d",
  253. tx_desc->id, comp_status,
  254. qdf_atomic_read(&pdev->num_tx_outstanding));
  255. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  256. return;
  257. }
  258. /**
  259. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  260. * @vdev: DP vdev Handle
  261. * @nbuf: skb
  262. * @msdu_info: msdu_info required to create HTT metadata
  263. *
  264. * Prepares and fills HTT metadata in the frame pre-header for special frames
  265. * that should be transmitted using varying transmit parameters.
  266. * There are 2 VDEV modes that currently needs this special metadata -
  267. * 1) Mesh Mode
  268. * 2) DSRC Mode
  269. *
  270. * Return: HTT metadata size
  271. *
  272. */
  273. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  274. struct dp_tx_msdu_info_s *msdu_info)
  275. {
  276. uint32_t *meta_data = msdu_info->meta_data;
  277. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  278. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  279. uint8_t htt_desc_size;
  280. /* Size rounded of multiple of 8 bytes */
  281. uint8_t htt_desc_size_aligned;
  282. uint8_t *hdr = NULL;
  283. /*
  284. * Metadata - HTT MSDU Extension header
  285. */
  286. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  287. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  288. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  289. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  290. meta_data[0])) {
  291. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  292. htt_desc_size_aligned)) {
  293. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  294. htt_desc_size_aligned);
  295. if (!nbuf) {
  296. /*
  297. * qdf_nbuf_realloc_headroom won't do skb_clone
  298. * as skb_realloc_headroom does. so, no free is
  299. * needed here.
  300. */
  301. DP_STATS_INC(vdev,
  302. tx_i.dropped.headroom_insufficient,
  303. 1);
  304. qdf_print(" %s[%d] skb_realloc_headroom failed",
  305. __func__, __LINE__);
  306. return 0;
  307. }
  308. }
  309. /* Fill and add HTT metaheader */
  310. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  311. if (!hdr) {
  312. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  313. "Error in filling HTT metadata");
  314. return 0;
  315. }
  316. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  317. } else if (vdev->opmode == wlan_op_mode_ocb) {
  318. /* Todo - Add support for DSRC */
  319. }
  320. return htt_desc_size_aligned;
  321. }
  322. /**
  323. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  324. * @tso_seg: TSO segment to process
  325. * @ext_desc: Pointer to MSDU extension descriptor
  326. *
  327. * Return: void
  328. */
  329. #if defined(FEATURE_TSO)
  330. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  331. void *ext_desc)
  332. {
  333. uint8_t num_frag;
  334. uint32_t tso_flags;
  335. /*
  336. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  337. * tcp_flag_mask
  338. *
  339. * Checksum enable flags are set in TCL descriptor and not in Extension
  340. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  341. */
  342. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  343. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  344. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  345. tso_seg->tso_flags.ip_len);
  346. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  347. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  348. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  349. uint32_t lo = 0;
  350. uint32_t hi = 0;
  351. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  352. (tso_seg->tso_frags[num_frag].length));
  353. qdf_dmaaddr_to_32s(
  354. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  355. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  356. tso_seg->tso_frags[num_frag].length);
  357. }
  358. return;
  359. }
  360. #else
  361. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  362. void *ext_desc)
  363. {
  364. return;
  365. }
  366. #endif
  367. #if defined(FEATURE_TSO)
  368. /**
  369. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  370. * allocated and free them
  371. *
  372. * @soc: soc handle
  373. * @free_seg: list of tso segments
  374. * @msdu_info: msdu descriptor
  375. *
  376. * Return - void
  377. */
  378. static void dp_tx_free_tso_seg_list(
  379. struct dp_soc *soc,
  380. struct qdf_tso_seg_elem_t *free_seg,
  381. struct dp_tx_msdu_info_s *msdu_info)
  382. {
  383. struct qdf_tso_seg_elem_t *next_seg;
  384. while (free_seg) {
  385. next_seg = free_seg->next;
  386. dp_tx_tso_desc_free(soc,
  387. msdu_info->tx_queue.desc_pool_id,
  388. free_seg);
  389. free_seg = next_seg;
  390. }
  391. }
  392. /**
  393. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  394. * allocated and free them
  395. *
  396. * @soc: soc handle
  397. * @free_num_seg: list of tso number segments
  398. * @msdu_info: msdu descriptor
  399. * Return - void
  400. */
  401. static void dp_tx_free_tso_num_seg_list(
  402. struct dp_soc *soc,
  403. struct qdf_tso_num_seg_elem_t *free_num_seg,
  404. struct dp_tx_msdu_info_s *msdu_info)
  405. {
  406. struct qdf_tso_num_seg_elem_t *next_num_seg;
  407. while (free_num_seg) {
  408. next_num_seg = free_num_seg->next;
  409. dp_tso_num_seg_free(soc,
  410. msdu_info->tx_queue.desc_pool_id,
  411. free_num_seg);
  412. free_num_seg = next_num_seg;
  413. }
  414. }
  415. /**
  416. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  417. * do dma unmap for each segment
  418. *
  419. * @soc: soc handle
  420. * @free_seg: list of tso segments
  421. * @num_seg_desc: tso number segment descriptor
  422. *
  423. * Return - void
  424. */
  425. static void dp_tx_unmap_tso_seg_list(
  426. struct dp_soc *soc,
  427. struct qdf_tso_seg_elem_t *free_seg,
  428. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  429. {
  430. struct qdf_tso_seg_elem_t *next_seg;
  431. if (qdf_unlikely(!num_seg_desc)) {
  432. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  433. return;
  434. }
  435. while (free_seg) {
  436. next_seg = free_seg->next;
  437. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  438. free_seg = next_seg;
  439. }
  440. }
  441. #ifdef FEATURE_TSO_STATS
  442. /**
  443. * dp_tso_get_stats_idx: Retrieve the tso packet id
  444. * @pdev - pdev handle
  445. *
  446. * Return: id
  447. */
  448. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  449. {
  450. uint32_t stats_idx;
  451. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  452. % CDP_MAX_TSO_PACKETS);
  453. return stats_idx;
  454. }
  455. #else
  456. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  457. {
  458. return 0;
  459. }
  460. #endif /* FEATURE_TSO_STATS */
  461. /**
  462. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  463. * free the tso segments descriptor and
  464. * tso num segments descriptor
  465. *
  466. * @soc: soc handle
  467. * @msdu_info: msdu descriptor
  468. * @tso_seg_unmap: flag to show if dma unmap is necessary
  469. *
  470. * Return - void
  471. */
  472. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  473. struct dp_tx_msdu_info_s *msdu_info,
  474. bool tso_seg_unmap)
  475. {
  476. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  477. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  478. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  479. tso_info->tso_num_seg_list;
  480. /* do dma unmap for each segment */
  481. if (tso_seg_unmap)
  482. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  483. /* free all tso number segment descriptor though looks only have 1 */
  484. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  485. /* free all tso segment descriptor */
  486. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  487. }
  488. /**
  489. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  490. * @vdev: virtual device handle
  491. * @msdu: network buffer
  492. * @msdu_info: meta data associated with the msdu
  493. *
  494. * Return: QDF_STATUS_SUCCESS success
  495. */
  496. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  497. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  498. {
  499. struct qdf_tso_seg_elem_t *tso_seg;
  500. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  501. struct dp_soc *soc = vdev->pdev->soc;
  502. struct dp_pdev *pdev = vdev->pdev;
  503. struct qdf_tso_info_t *tso_info;
  504. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  505. tso_info = &msdu_info->u.tso_info;
  506. tso_info->curr_seg = NULL;
  507. tso_info->tso_seg_list = NULL;
  508. tso_info->num_segs = num_seg;
  509. msdu_info->frm_type = dp_tx_frm_tso;
  510. tso_info->tso_num_seg_list = NULL;
  511. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  512. while (num_seg) {
  513. tso_seg = dp_tx_tso_desc_alloc(
  514. soc, msdu_info->tx_queue.desc_pool_id);
  515. if (tso_seg) {
  516. tso_seg->next = tso_info->tso_seg_list;
  517. tso_info->tso_seg_list = tso_seg;
  518. num_seg--;
  519. } else {
  520. dp_err_rl("Failed to alloc tso seg desc");
  521. DP_STATS_INC_PKT(vdev->pdev,
  522. tso_stats.tso_no_mem_dropped, 1,
  523. qdf_nbuf_len(msdu));
  524. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  525. return QDF_STATUS_E_NOMEM;
  526. }
  527. }
  528. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  529. tso_num_seg = dp_tso_num_seg_alloc(soc,
  530. msdu_info->tx_queue.desc_pool_id);
  531. if (tso_num_seg) {
  532. tso_num_seg->next = tso_info->tso_num_seg_list;
  533. tso_info->tso_num_seg_list = tso_num_seg;
  534. } else {
  535. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  536. __func__);
  537. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  538. return QDF_STATUS_E_NOMEM;
  539. }
  540. msdu_info->num_seg =
  541. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  542. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  543. msdu_info->num_seg);
  544. if (!(msdu_info->num_seg)) {
  545. /*
  546. * Free allocated TSO seg desc and number seg desc,
  547. * do unmap for segments if dma map has done.
  548. */
  549. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  550. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  551. return QDF_STATUS_E_INVAL;
  552. }
  553. tso_info->curr_seg = tso_info->tso_seg_list;
  554. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  555. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  556. msdu, msdu_info->num_seg);
  557. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  558. tso_info->msdu_stats_idx);
  559. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  560. return QDF_STATUS_SUCCESS;
  561. }
  562. #else
  563. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  564. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  565. {
  566. return QDF_STATUS_E_NOMEM;
  567. }
  568. #endif
  569. /**
  570. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  571. * @vdev: DP Vdev handle
  572. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  573. * @desc_pool_id: Descriptor Pool ID
  574. *
  575. * Return:
  576. */
  577. static
  578. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  579. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  580. {
  581. uint8_t i;
  582. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  583. struct dp_tx_seg_info_s *seg_info;
  584. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  585. struct dp_soc *soc = vdev->pdev->soc;
  586. /* Allocate an extension descriptor */
  587. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  588. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  589. if (!msdu_ext_desc) {
  590. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  591. return NULL;
  592. }
  593. if (msdu_info->exception_fw &&
  594. qdf_unlikely(vdev->mesh_vdev)) {
  595. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  596. &msdu_info->meta_data[0],
  597. sizeof(struct htt_tx_msdu_desc_ext2_t));
  598. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  599. }
  600. switch (msdu_info->frm_type) {
  601. case dp_tx_frm_sg:
  602. case dp_tx_frm_me:
  603. case dp_tx_frm_raw:
  604. seg_info = msdu_info->u.sg_info.curr_seg;
  605. /* Update the buffer pointers in MSDU Extension Descriptor */
  606. for (i = 0; i < seg_info->frag_cnt; i++) {
  607. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  608. seg_info->frags[i].paddr_lo,
  609. seg_info->frags[i].paddr_hi,
  610. seg_info->frags[i].len);
  611. }
  612. break;
  613. case dp_tx_frm_tso:
  614. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  615. &cached_ext_desc[0]);
  616. break;
  617. default:
  618. break;
  619. }
  620. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  621. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  622. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  623. msdu_ext_desc->vaddr);
  624. return msdu_ext_desc;
  625. }
  626. /**
  627. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  628. *
  629. * @skb: skb to be traced
  630. * @msdu_id: msdu_id of the packet
  631. * @vdev_id: vdev_id of the packet
  632. *
  633. * Return: None
  634. */
  635. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  636. uint8_t vdev_id)
  637. {
  638. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  639. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  640. DPTRACE(qdf_dp_trace_ptr(skb,
  641. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  642. QDF_TRACE_DEFAULT_PDEV_ID,
  643. qdf_nbuf_data_addr(skb),
  644. sizeof(qdf_nbuf_data(skb)),
  645. msdu_id, vdev_id));
  646. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  647. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  648. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  649. msdu_id, QDF_TX));
  650. }
  651. /**
  652. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  653. * @vdev: DP vdev handle
  654. * @nbuf: skb
  655. * @desc_pool_id: Descriptor pool ID
  656. * @meta_data: Metadata to the fw
  657. * @tx_exc_metadata: Handle that holds exception path metadata
  658. * Allocate and prepare Tx descriptor with msdu information.
  659. *
  660. * Return: Pointer to Tx Descriptor on success,
  661. * NULL on failure
  662. */
  663. static
  664. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  665. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  666. struct dp_tx_msdu_info_s *msdu_info,
  667. struct cdp_tx_exception_metadata *tx_exc_metadata)
  668. {
  669. uint8_t align_pad;
  670. uint8_t is_exception = 0;
  671. uint8_t htt_hdr_size;
  672. qdf_ether_header_t *eh;
  673. struct dp_tx_desc_s *tx_desc;
  674. struct dp_pdev *pdev = vdev->pdev;
  675. struct dp_soc *soc = pdev->soc;
  676. if (dp_tx_limit_check(vdev))
  677. return NULL;
  678. /* Allocate software Tx descriptor */
  679. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  680. if (qdf_unlikely(!tx_desc)) {
  681. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  682. return NULL;
  683. }
  684. dp_tx_outstanding_inc(pdev);
  685. /* Initialize the SW tx descriptor */
  686. tx_desc->nbuf = nbuf;
  687. tx_desc->frm_type = dp_tx_frm_std;
  688. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  689. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  690. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  691. tx_desc->vdev = vdev;
  692. tx_desc->pdev = pdev;
  693. tx_desc->msdu_ext_desc = NULL;
  694. tx_desc->pkt_offset = 0;
  695. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  696. if (qdf_unlikely(vdev->multipass_en)) {
  697. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  698. goto failure;
  699. }
  700. /*
  701. * For special modes (vdev_type == ocb or mesh), data frames should be
  702. * transmitted using varying transmit parameters (tx spec) which include
  703. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  704. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  705. * These frames are sent as exception packets to firmware.
  706. *
  707. * HW requirement is that metadata should always point to a
  708. * 8-byte aligned address. So we add alignment pad to start of buffer.
  709. * HTT Metadata should be ensured to be multiple of 8-bytes,
  710. * to get 8-byte aligned start address along with align_pad added
  711. *
  712. * |-----------------------------|
  713. * | |
  714. * |-----------------------------| <-----Buffer Pointer Address given
  715. * | | ^ in HW descriptor (aligned)
  716. * | HTT Metadata | |
  717. * | | |
  718. * | | | Packet Offset given in descriptor
  719. * | | |
  720. * |-----------------------------| |
  721. * | Alignment Pad | v
  722. * |-----------------------------| <----- Actual buffer start address
  723. * | SKB Data | (Unaligned)
  724. * | |
  725. * | |
  726. * | |
  727. * | |
  728. * | |
  729. * |-----------------------------|
  730. */
  731. if (qdf_unlikely((msdu_info->exception_fw)) ||
  732. (vdev->opmode == wlan_op_mode_ocb) ||
  733. (tx_exc_metadata &&
  734. tx_exc_metadata->is_tx_sniffer)) {
  735. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  736. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  737. DP_STATS_INC(vdev,
  738. tx_i.dropped.headroom_insufficient, 1);
  739. goto failure;
  740. }
  741. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  742. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  743. "qdf_nbuf_push_head failed");
  744. goto failure;
  745. }
  746. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  747. msdu_info);
  748. if (htt_hdr_size == 0)
  749. goto failure;
  750. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  751. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  752. is_exception = 1;
  753. }
  754. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  755. qdf_nbuf_map(soc->osdev, nbuf,
  756. QDF_DMA_TO_DEVICE))) {
  757. /* Handle failure */
  758. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  759. "qdf_nbuf_map failed");
  760. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  761. goto failure;
  762. }
  763. if (qdf_unlikely(vdev->nawds_enabled)) {
  764. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  765. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  766. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  767. is_exception = 1;
  768. }
  769. }
  770. #if !TQM_BYPASS_WAR
  771. if (is_exception || tx_exc_metadata)
  772. #endif
  773. {
  774. /* Temporary WAR due to TQM VP issues */
  775. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  776. qdf_atomic_inc(&pdev->num_tx_exception);
  777. }
  778. return tx_desc;
  779. failure:
  780. dp_tx_desc_release(tx_desc, desc_pool_id);
  781. return NULL;
  782. }
  783. /**
  784. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  785. * @vdev: DP vdev handle
  786. * @nbuf: skb
  787. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  788. * @desc_pool_id : Descriptor Pool ID
  789. *
  790. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  791. * information. For frames wth fragments, allocate and prepare
  792. * an MSDU extension descriptor
  793. *
  794. * Return: Pointer to Tx Descriptor on success,
  795. * NULL on failure
  796. */
  797. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  798. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  799. uint8_t desc_pool_id)
  800. {
  801. struct dp_tx_desc_s *tx_desc;
  802. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  803. struct dp_pdev *pdev = vdev->pdev;
  804. struct dp_soc *soc = pdev->soc;
  805. if (dp_tx_limit_check(vdev))
  806. return NULL;
  807. /* Allocate software Tx descriptor */
  808. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  809. if (!tx_desc) {
  810. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  811. return NULL;
  812. }
  813. dp_tx_outstanding_inc(pdev);
  814. /* Initialize the SW tx descriptor */
  815. tx_desc->nbuf = nbuf;
  816. tx_desc->frm_type = msdu_info->frm_type;
  817. tx_desc->tx_encap_type = vdev->tx_encap_type;
  818. tx_desc->vdev = vdev;
  819. tx_desc->pdev = pdev;
  820. tx_desc->pkt_offset = 0;
  821. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  822. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  823. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  824. /* Handle scattered frames - TSO/SG/ME */
  825. /* Allocate and prepare an extension descriptor for scattered frames */
  826. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  827. if (!msdu_ext_desc) {
  828. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  829. "%s Tx Extension Descriptor Alloc Fail",
  830. __func__);
  831. goto failure;
  832. }
  833. #if TQM_BYPASS_WAR
  834. /* Temporary WAR due to TQM VP issues */
  835. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  836. qdf_atomic_inc(&pdev->num_tx_exception);
  837. #endif
  838. if (qdf_unlikely(msdu_info->exception_fw))
  839. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  840. tx_desc->msdu_ext_desc = msdu_ext_desc;
  841. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  842. return tx_desc;
  843. failure:
  844. dp_tx_desc_release(tx_desc, desc_pool_id);
  845. return NULL;
  846. }
  847. /**
  848. * dp_tx_prepare_raw() - Prepare RAW packet TX
  849. * @vdev: DP vdev handle
  850. * @nbuf: buffer pointer
  851. * @seg_info: Pointer to Segment info Descriptor to be prepared
  852. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  853. * descriptor
  854. *
  855. * Return:
  856. */
  857. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  858. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  859. {
  860. qdf_nbuf_t curr_nbuf = NULL;
  861. uint16_t total_len = 0;
  862. qdf_dma_addr_t paddr;
  863. int32_t i;
  864. int32_t mapped_buf_num = 0;
  865. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  866. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  867. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  868. /* Continue only if frames are of DATA type */
  869. if (!DP_FRAME_IS_DATA(qos_wh)) {
  870. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  871. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  872. "Pkt. recd is of not data type");
  873. goto error;
  874. }
  875. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  876. if (vdev->raw_mode_war &&
  877. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  878. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  879. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  880. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  881. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  882. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  883. QDF_DMA_TO_DEVICE)) {
  884. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  885. "%s dma map error ", __func__);
  886. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  887. mapped_buf_num = i;
  888. goto error;
  889. }
  890. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  891. seg_info->frags[i].paddr_lo = paddr;
  892. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  893. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  894. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  895. total_len += qdf_nbuf_len(curr_nbuf);
  896. }
  897. seg_info->frag_cnt = i;
  898. seg_info->total_len = total_len;
  899. seg_info->next = NULL;
  900. sg_info->curr_seg = seg_info;
  901. msdu_info->frm_type = dp_tx_frm_raw;
  902. msdu_info->num_seg = 1;
  903. return nbuf;
  904. error:
  905. i = 0;
  906. while (nbuf) {
  907. curr_nbuf = nbuf;
  908. if (i < mapped_buf_num) {
  909. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  910. i++;
  911. }
  912. nbuf = qdf_nbuf_next(nbuf);
  913. qdf_nbuf_free(curr_nbuf);
  914. }
  915. return NULL;
  916. }
  917. /**
  918. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  919. * @soc: DP soc handle
  920. * @nbuf: Buffer pointer
  921. *
  922. * unmap the chain of nbufs that belong to this RAW frame.
  923. *
  924. * Return: None
  925. */
  926. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  927. qdf_nbuf_t nbuf)
  928. {
  929. qdf_nbuf_t cur_nbuf = nbuf;
  930. do {
  931. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  932. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  933. } while (cur_nbuf);
  934. }
  935. /**
  936. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  937. * @soc: DP Soc Handle
  938. * @vdev: DP vdev handle
  939. * @tx_desc: Tx Descriptor Handle
  940. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  941. * @fw_metadata: Metadata to send to Target Firmware along with frame
  942. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  943. * @tx_exc_metadata: Handle that holds exception path meta data
  944. *
  945. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  946. * from software Tx descriptor
  947. *
  948. * Return:
  949. */
  950. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  951. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  952. uint16_t fw_metadata, uint8_t ring_id,
  953. struct cdp_tx_exception_metadata
  954. *tx_exc_metadata)
  955. {
  956. uint8_t type;
  957. uint16_t length;
  958. void *hal_tx_desc, *hal_tx_desc_cached;
  959. qdf_dma_addr_t dma_addr;
  960. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  961. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  962. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  963. tx_exc_metadata->sec_type : vdev->sec_type);
  964. /* Return Buffer Manager ID */
  965. uint8_t bm_id = ring_id;
  966. hal_ring_handle_t hal_ring_hdl = soc->tcl_data_ring[ring_id].hal_srng;
  967. hal_tx_desc_cached = (void *) cached_desc;
  968. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  969. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  970. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  971. type = HAL_TX_BUF_TYPE_EXT_DESC;
  972. dma_addr = tx_desc->msdu_ext_desc->paddr;
  973. } else {
  974. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  975. type = HAL_TX_BUF_TYPE_BUFFER;
  976. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  977. }
  978. qdf_assert_always(dma_addr);
  979. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  980. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  981. dma_addr, bm_id, tx_desc->id,
  982. type, soc->hal_soc);
  983. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  984. return QDF_STATUS_E_RESOURCES;
  985. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  986. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  987. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  988. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  989. vdev->pdev->lmac_id);
  990. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  991. vdev->search_type);
  992. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  993. vdev->bss_ast_idx);
  994. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  995. vdev->dscp_tid_map_id);
  996. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  997. sec_type_map[sec_type]);
  998. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  999. (vdev->bss_ast_hash & 0xF));
  1000. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1001. length, type, (uint64_t)dma_addr,
  1002. tx_desc->pkt_offset, tx_desc->id);
  1003. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1004. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1005. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1006. vdev->hal_desc_addr_search_flags);
  1007. /* verify checksum offload configuration*/
  1008. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  1009. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1010. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1011. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1012. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1013. }
  1014. if (tid != HTT_TX_EXT_TID_INVALID)
  1015. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1016. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1017. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1018. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  1019. /* Sync cached descriptor with HW */
  1020. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1021. if (!hal_tx_desc) {
  1022. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1023. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1024. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1025. return QDF_STATUS_E_RESOURCES;
  1026. }
  1027. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1028. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1029. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  1030. return QDF_STATUS_SUCCESS;
  1031. }
  1032. /**
  1033. * dp_cce_classify() - Classify the frame based on CCE rules
  1034. * @vdev: DP vdev handle
  1035. * @nbuf: skb
  1036. *
  1037. * Classify frames based on CCE rules
  1038. * Return: bool( true if classified,
  1039. * else false)
  1040. */
  1041. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1042. {
  1043. qdf_ether_header_t *eh = NULL;
  1044. uint16_t ether_type;
  1045. qdf_llc_t *llcHdr;
  1046. qdf_nbuf_t nbuf_clone = NULL;
  1047. qdf_dot3_qosframe_t *qos_wh = NULL;
  1048. /* for mesh packets don't do any classification */
  1049. if (qdf_unlikely(vdev->mesh_vdev))
  1050. return false;
  1051. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1052. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1053. ether_type = eh->ether_type;
  1054. llcHdr = (qdf_llc_t *)(nbuf->data +
  1055. sizeof(qdf_ether_header_t));
  1056. } else {
  1057. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1058. /* For encrypted packets don't do any classification */
  1059. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1060. return false;
  1061. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1062. if (qdf_unlikely(
  1063. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1064. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1065. ether_type = *(uint16_t *)(nbuf->data
  1066. + QDF_IEEE80211_4ADDR_HDR_LEN
  1067. + sizeof(qdf_llc_t)
  1068. - sizeof(ether_type));
  1069. llcHdr = (qdf_llc_t *)(nbuf->data +
  1070. QDF_IEEE80211_4ADDR_HDR_LEN);
  1071. } else {
  1072. ether_type = *(uint16_t *)(nbuf->data
  1073. + QDF_IEEE80211_3ADDR_HDR_LEN
  1074. + sizeof(qdf_llc_t)
  1075. - sizeof(ether_type));
  1076. llcHdr = (qdf_llc_t *)(nbuf->data +
  1077. QDF_IEEE80211_3ADDR_HDR_LEN);
  1078. }
  1079. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1080. && (ether_type ==
  1081. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1082. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1083. return true;
  1084. }
  1085. }
  1086. return false;
  1087. }
  1088. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1089. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1090. sizeof(*llcHdr));
  1091. nbuf_clone = qdf_nbuf_clone(nbuf);
  1092. if (qdf_unlikely(nbuf_clone)) {
  1093. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1094. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1095. qdf_nbuf_pull_head(nbuf_clone,
  1096. sizeof(qdf_net_vlanhdr_t));
  1097. }
  1098. }
  1099. } else {
  1100. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1101. nbuf_clone = qdf_nbuf_clone(nbuf);
  1102. if (qdf_unlikely(nbuf_clone)) {
  1103. qdf_nbuf_pull_head(nbuf_clone,
  1104. sizeof(qdf_net_vlanhdr_t));
  1105. }
  1106. }
  1107. }
  1108. if (qdf_unlikely(nbuf_clone))
  1109. nbuf = nbuf_clone;
  1110. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1111. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1112. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1113. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1114. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1115. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1116. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1117. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1118. if (qdf_unlikely(nbuf_clone))
  1119. qdf_nbuf_free(nbuf_clone);
  1120. return true;
  1121. }
  1122. if (qdf_unlikely(nbuf_clone))
  1123. qdf_nbuf_free(nbuf_clone);
  1124. return false;
  1125. }
  1126. /**
  1127. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1128. * @vdev: DP vdev handle
  1129. * @nbuf: skb
  1130. *
  1131. * Extract the DSCP or PCP information from frame and map into TID value.
  1132. *
  1133. * Return: void
  1134. */
  1135. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1136. struct dp_tx_msdu_info_s *msdu_info)
  1137. {
  1138. uint8_t tos = 0, dscp_tid_override = 0;
  1139. uint8_t *hdr_ptr, *L3datap;
  1140. uint8_t is_mcast = 0;
  1141. qdf_ether_header_t *eh = NULL;
  1142. qdf_ethervlan_header_t *evh = NULL;
  1143. uint16_t ether_type;
  1144. qdf_llc_t *llcHdr;
  1145. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1146. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1147. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1148. eh = (qdf_ether_header_t *)nbuf->data;
  1149. hdr_ptr = eh->ether_dhost;
  1150. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1151. } else {
  1152. qdf_dot3_qosframe_t *qos_wh =
  1153. (qdf_dot3_qosframe_t *) nbuf->data;
  1154. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1155. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1156. return;
  1157. }
  1158. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1159. ether_type = eh->ether_type;
  1160. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1161. /*
  1162. * Check if packet is dot3 or eth2 type.
  1163. */
  1164. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1165. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1166. sizeof(*llcHdr));
  1167. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1168. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1169. sizeof(*llcHdr);
  1170. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1171. + sizeof(*llcHdr) +
  1172. sizeof(qdf_net_vlanhdr_t));
  1173. } else {
  1174. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1175. sizeof(*llcHdr);
  1176. }
  1177. } else {
  1178. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1179. evh = (qdf_ethervlan_header_t *) eh;
  1180. ether_type = evh->ether_type;
  1181. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1182. }
  1183. }
  1184. /*
  1185. * Find priority from IP TOS DSCP field
  1186. */
  1187. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1188. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1189. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1190. /* Only for unicast frames */
  1191. if (!is_mcast) {
  1192. /* send it on VO queue */
  1193. msdu_info->tid = DP_VO_TID;
  1194. }
  1195. } else {
  1196. /*
  1197. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1198. * from TOS byte.
  1199. */
  1200. tos = ip->ip_tos;
  1201. dscp_tid_override = 1;
  1202. }
  1203. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1204. /* TODO
  1205. * use flowlabel
  1206. *igmpmld cases to be handled in phase 2
  1207. */
  1208. unsigned long ver_pri_flowlabel;
  1209. unsigned long pri;
  1210. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1211. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1212. DP_IPV6_PRIORITY_SHIFT;
  1213. tos = pri;
  1214. dscp_tid_override = 1;
  1215. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1216. msdu_info->tid = DP_VO_TID;
  1217. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1218. /* Only for unicast frames */
  1219. if (!is_mcast) {
  1220. /* send ucast arp on VO queue */
  1221. msdu_info->tid = DP_VO_TID;
  1222. }
  1223. }
  1224. /*
  1225. * Assign all MCAST packets to BE
  1226. */
  1227. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1228. if (is_mcast) {
  1229. tos = 0;
  1230. dscp_tid_override = 1;
  1231. }
  1232. }
  1233. if (dscp_tid_override == 1) {
  1234. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1235. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1236. }
  1237. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1238. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1239. return;
  1240. }
  1241. /**
  1242. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1243. * @vdev: DP vdev handle
  1244. * @nbuf: skb
  1245. *
  1246. * Software based TID classification is required when more than 2 DSCP-TID
  1247. * mapping tables are needed.
  1248. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1249. *
  1250. * Return: void
  1251. */
  1252. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1253. struct dp_tx_msdu_info_s *msdu_info)
  1254. {
  1255. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1256. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1257. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1258. return;
  1259. /* for mesh packets don't do any classification */
  1260. if (qdf_unlikely(vdev->mesh_vdev))
  1261. return;
  1262. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1263. }
  1264. #ifdef FEATURE_WLAN_TDLS
  1265. /**
  1266. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1267. * @tx_desc: TX descriptor
  1268. *
  1269. * Return: None
  1270. */
  1271. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1272. {
  1273. if (tx_desc->vdev) {
  1274. if (tx_desc->vdev->is_tdls_frame) {
  1275. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1276. tx_desc->vdev->is_tdls_frame = false;
  1277. }
  1278. }
  1279. }
  1280. /**
  1281. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1282. * @tx_desc: TX descriptor
  1283. * @vdev: datapath vdev handle
  1284. *
  1285. * Return: None
  1286. */
  1287. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1288. struct dp_vdev *vdev)
  1289. {
  1290. struct hal_tx_completion_status ts = {0};
  1291. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1292. if (qdf_unlikely(!vdev)) {
  1293. dp_err("vdev is null!");
  1294. return;
  1295. }
  1296. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1297. if (vdev->tx_non_std_data_callback.func) {
  1298. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1299. vdev->tx_non_std_data_callback.func(
  1300. vdev->tx_non_std_data_callback.ctxt,
  1301. nbuf, ts.status);
  1302. return;
  1303. }
  1304. }
  1305. #else
  1306. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1307. {
  1308. }
  1309. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1310. struct dp_vdev *vdev)
  1311. {
  1312. }
  1313. #endif
  1314. /**
  1315. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1316. * @vdev: DP vdev handle
  1317. * @nbuf: skb
  1318. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1319. * @meta_data: Metadata to the fw
  1320. * @tx_q: Tx queue to be used for this Tx frame
  1321. * @peer_id: peer_id of the peer in case of NAWDS frames
  1322. * @tx_exc_metadata: Handle that holds exception path metadata
  1323. *
  1324. * Return: NULL on success,
  1325. * nbuf when it fails to send
  1326. */
  1327. qdf_nbuf_t
  1328. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1329. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1330. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1331. {
  1332. struct dp_pdev *pdev = vdev->pdev;
  1333. struct dp_soc *soc = pdev->soc;
  1334. struct dp_tx_desc_s *tx_desc;
  1335. QDF_STATUS status;
  1336. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1337. hal_ring_handle_t hal_ring_hdl =
  1338. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1339. uint16_t htt_tcl_metadata = 0;
  1340. uint8_t tid = msdu_info->tid;
  1341. struct cdp_tid_tx_stats *tid_stats = NULL;
  1342. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1343. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1344. msdu_info, tx_exc_metadata);
  1345. if (!tx_desc) {
  1346. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1347. vdev, tx_q->desc_pool_id);
  1348. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1349. tid_stats = &pdev->stats.tid_stats.
  1350. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1351. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1352. return nbuf;
  1353. }
  1354. if (qdf_unlikely(soc->cce_disable)) {
  1355. if (dp_cce_classify(vdev, nbuf) == true) {
  1356. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1357. tid = DP_VO_TID;
  1358. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1359. }
  1360. }
  1361. dp_tx_update_tdls_flags(tx_desc);
  1362. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1363. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1364. "%s %d : HAL RING Access Failed -- %pK",
  1365. __func__, __LINE__, hal_ring_hdl);
  1366. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1367. tid_stats = &pdev->stats.tid_stats.
  1368. tid_tx_stats[tx_q->ring_id][tid];
  1369. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1370. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1371. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1372. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1373. goto fail_return;
  1374. }
  1375. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1376. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1377. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1378. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1379. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1380. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1381. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1382. peer_id);
  1383. } else
  1384. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1385. if (msdu_info->exception_fw) {
  1386. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1387. }
  1388. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1389. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1390. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1391. if (status != QDF_STATUS_SUCCESS) {
  1392. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1393. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1394. __func__, tx_desc, tx_q->ring_id);
  1395. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1396. tid_stats = &pdev->stats.tid_stats.
  1397. tid_tx_stats[tx_q->ring_id][tid];
  1398. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1399. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1400. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1401. goto fail_return;
  1402. }
  1403. nbuf = NULL;
  1404. fail_return:
  1405. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1406. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1407. hif_pm_runtime_put(soc->hif_handle);
  1408. } else {
  1409. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1410. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1411. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1412. }
  1413. return nbuf;
  1414. }
  1415. /**
  1416. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1417. * @vdev: DP vdev handle
  1418. * @nbuf: skb
  1419. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1420. *
  1421. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1422. *
  1423. * Return: NULL on success,
  1424. * nbuf when it fails to send
  1425. */
  1426. #if QDF_LOCK_STATS
  1427. noinline
  1428. #else
  1429. #endif
  1430. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1431. struct dp_tx_msdu_info_s *msdu_info)
  1432. {
  1433. uint8_t i;
  1434. struct dp_pdev *pdev = vdev->pdev;
  1435. struct dp_soc *soc = pdev->soc;
  1436. struct dp_tx_desc_s *tx_desc;
  1437. bool is_cce_classified = false;
  1438. QDF_STATUS status;
  1439. uint16_t htt_tcl_metadata = 0;
  1440. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1441. hal_ring_handle_t hal_ring_hdl =
  1442. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1443. struct cdp_tid_tx_stats *tid_stats = NULL;
  1444. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1445. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1446. "%s %d : HAL RING Access Failed -- %pK",
  1447. __func__, __LINE__, hal_ring_hdl);
  1448. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1449. tid_stats = &pdev->stats.tid_stats.
  1450. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1451. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1452. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1453. return nbuf;
  1454. }
  1455. if (qdf_unlikely(soc->cce_disable)) {
  1456. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1457. if (is_cce_classified) {
  1458. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1459. msdu_info->tid = DP_VO_TID;
  1460. }
  1461. }
  1462. if (msdu_info->frm_type == dp_tx_frm_me)
  1463. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1464. i = 0;
  1465. /* Print statement to track i and num_seg */
  1466. /*
  1467. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1468. * descriptors using information in msdu_info
  1469. */
  1470. while (i < msdu_info->num_seg) {
  1471. /*
  1472. * Setup Tx descriptor for an MSDU, and MSDU extension
  1473. * descriptor
  1474. */
  1475. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1476. tx_q->desc_pool_id);
  1477. if (!tx_desc) {
  1478. if (msdu_info->frm_type == dp_tx_frm_me) {
  1479. dp_tx_me_free_buf(pdev,
  1480. (void *)(msdu_info->u.sg_info
  1481. .curr_seg->frags[0].vaddr));
  1482. i++;
  1483. continue;
  1484. }
  1485. goto done;
  1486. }
  1487. if (msdu_info->frm_type == dp_tx_frm_me) {
  1488. tx_desc->me_buffer =
  1489. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1490. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1491. }
  1492. if (is_cce_classified)
  1493. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1494. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1495. if (msdu_info->exception_fw) {
  1496. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1497. }
  1498. /*
  1499. * Enqueue the Tx MSDU descriptor to HW for transmit
  1500. */
  1501. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1502. htt_tcl_metadata, tx_q->ring_id, NULL);
  1503. if (status != QDF_STATUS_SUCCESS) {
  1504. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1505. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1506. __func__, tx_desc, tx_q->ring_id);
  1507. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1508. tid_stats = &pdev->stats.tid_stats.
  1509. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1510. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1511. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1512. if (msdu_info->frm_type == dp_tx_frm_me) {
  1513. i++;
  1514. continue;
  1515. }
  1516. goto done;
  1517. }
  1518. /*
  1519. * TODO
  1520. * if tso_info structure can be modified to have curr_seg
  1521. * as first element, following 2 blocks of code (for TSO and SG)
  1522. * can be combined into 1
  1523. */
  1524. /*
  1525. * For frames with multiple segments (TSO, ME), jump to next
  1526. * segment.
  1527. */
  1528. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1529. if (msdu_info->u.tso_info.curr_seg->next) {
  1530. msdu_info->u.tso_info.curr_seg =
  1531. msdu_info->u.tso_info.curr_seg->next;
  1532. /*
  1533. * If this is a jumbo nbuf, then increment the number of
  1534. * nbuf users for each additional segment of the msdu.
  1535. * This will ensure that the skb is freed only after
  1536. * receiving tx completion for all segments of an nbuf
  1537. */
  1538. qdf_nbuf_inc_users(nbuf);
  1539. /* Check with MCL if this is needed */
  1540. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1541. }
  1542. }
  1543. /*
  1544. * For Multicast-Unicast converted packets,
  1545. * each converted frame (for a client) is represented as
  1546. * 1 segment
  1547. */
  1548. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1549. (msdu_info->frm_type == dp_tx_frm_me)) {
  1550. if (msdu_info->u.sg_info.curr_seg->next) {
  1551. msdu_info->u.sg_info.curr_seg =
  1552. msdu_info->u.sg_info.curr_seg->next;
  1553. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1554. }
  1555. }
  1556. i++;
  1557. }
  1558. nbuf = NULL;
  1559. done:
  1560. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1561. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1562. hif_pm_runtime_put(soc->hif_handle);
  1563. } else {
  1564. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1565. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1566. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1567. }
  1568. return nbuf;
  1569. }
  1570. /**
  1571. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1572. * for SG frames
  1573. * @vdev: DP vdev handle
  1574. * @nbuf: skb
  1575. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1576. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1577. *
  1578. * Return: NULL on success,
  1579. * nbuf when it fails to send
  1580. */
  1581. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1582. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1583. {
  1584. uint32_t cur_frag, nr_frags;
  1585. qdf_dma_addr_t paddr;
  1586. struct dp_tx_sg_info_s *sg_info;
  1587. sg_info = &msdu_info->u.sg_info;
  1588. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1589. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1590. QDF_DMA_TO_DEVICE)) {
  1591. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1592. "dma map error");
  1593. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1594. qdf_nbuf_free(nbuf);
  1595. return NULL;
  1596. }
  1597. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1598. seg_info->frags[0].paddr_lo = paddr;
  1599. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1600. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1601. seg_info->frags[0].vaddr = (void *) nbuf;
  1602. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1603. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1604. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1605. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1606. "frag dma map error");
  1607. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1608. qdf_nbuf_free(nbuf);
  1609. return NULL;
  1610. }
  1611. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1612. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1613. seg_info->frags[cur_frag + 1].paddr_hi =
  1614. ((uint64_t) paddr) >> 32;
  1615. seg_info->frags[cur_frag + 1].len =
  1616. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1617. }
  1618. seg_info->frag_cnt = (cur_frag + 1);
  1619. seg_info->total_len = qdf_nbuf_len(nbuf);
  1620. seg_info->next = NULL;
  1621. sg_info->curr_seg = seg_info;
  1622. msdu_info->frm_type = dp_tx_frm_sg;
  1623. msdu_info->num_seg = 1;
  1624. return nbuf;
  1625. }
  1626. /**
  1627. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1628. * @vdev: DP vdev handle
  1629. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1630. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1631. *
  1632. * Return: NULL on failure,
  1633. * nbuf when extracted successfully
  1634. */
  1635. static
  1636. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1637. struct dp_tx_msdu_info_s *msdu_info,
  1638. uint16_t ppdu_cookie)
  1639. {
  1640. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1641. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1642. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1643. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1644. (msdu_info->meta_data[5], 1);
  1645. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1646. (msdu_info->meta_data[5], 1);
  1647. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1648. (msdu_info->meta_data[6], ppdu_cookie);
  1649. msdu_info->exception_fw = 1;
  1650. msdu_info->is_tx_sniffer = 1;
  1651. }
  1652. #ifdef MESH_MODE_SUPPORT
  1653. /**
  1654. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1655. and prepare msdu_info for mesh frames.
  1656. * @vdev: DP vdev handle
  1657. * @nbuf: skb
  1658. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1659. *
  1660. * Return: NULL on failure,
  1661. * nbuf when extracted successfully
  1662. */
  1663. static
  1664. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1665. struct dp_tx_msdu_info_s *msdu_info)
  1666. {
  1667. struct meta_hdr_s *mhdr;
  1668. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1669. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1670. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1671. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1672. msdu_info->exception_fw = 0;
  1673. goto remove_meta_hdr;
  1674. }
  1675. msdu_info->exception_fw = 1;
  1676. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1677. meta_data->host_tx_desc_pool = 1;
  1678. meta_data->update_peer_cache = 1;
  1679. meta_data->learning_frame = 1;
  1680. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1681. meta_data->power = mhdr->power;
  1682. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1683. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1684. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1685. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1686. meta_data->dyn_bw = 1;
  1687. meta_data->valid_pwr = 1;
  1688. meta_data->valid_mcs_mask = 1;
  1689. meta_data->valid_nss_mask = 1;
  1690. meta_data->valid_preamble_type = 1;
  1691. meta_data->valid_retries = 1;
  1692. meta_data->valid_bw_info = 1;
  1693. }
  1694. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1695. meta_data->encrypt_type = 0;
  1696. meta_data->valid_encrypt_type = 1;
  1697. meta_data->learning_frame = 0;
  1698. }
  1699. meta_data->valid_key_flags = 1;
  1700. meta_data->key_flags = (mhdr->keyix & 0x3);
  1701. remove_meta_hdr:
  1702. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1703. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1704. "qdf_nbuf_pull_head failed");
  1705. qdf_nbuf_free(nbuf);
  1706. return NULL;
  1707. }
  1708. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1709. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1710. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1711. " tid %d to_fw %d",
  1712. __func__, msdu_info->meta_data[0],
  1713. msdu_info->meta_data[1],
  1714. msdu_info->meta_data[2],
  1715. msdu_info->meta_data[3],
  1716. msdu_info->meta_data[4],
  1717. msdu_info->meta_data[5],
  1718. msdu_info->tid, msdu_info->exception_fw);
  1719. return nbuf;
  1720. }
  1721. #else
  1722. static
  1723. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1724. struct dp_tx_msdu_info_s *msdu_info)
  1725. {
  1726. return nbuf;
  1727. }
  1728. #endif
  1729. /**
  1730. * dp_check_exc_metadata() - Checks if parameters are valid
  1731. * @tx_exc - holds all exception path parameters
  1732. *
  1733. * Returns true when all the parameters are valid else false
  1734. *
  1735. */
  1736. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1737. {
  1738. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1739. HTT_INVALID_TID);
  1740. bool invalid_encap_type =
  1741. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1742. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1743. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1744. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1745. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1746. tx_exc->ppdu_cookie == 0);
  1747. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1748. invalid_cookie) {
  1749. return false;
  1750. }
  1751. return true;
  1752. }
  1753. /**
  1754. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1755. * @vap_dev: DP vdev handle
  1756. * @nbuf: skb
  1757. * @tx_exc_metadata: Handle that holds exception path meta data
  1758. *
  1759. * Entry point for Core Tx layer (DP_TX) invoked from
  1760. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1761. *
  1762. * Return: NULL on success,
  1763. * nbuf when it fails to send
  1764. */
  1765. qdf_nbuf_t
  1766. dp_tx_send_exception(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf,
  1767. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1768. {
  1769. qdf_ether_header_t *eh = NULL;
  1770. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1771. struct dp_tx_msdu_info_s msdu_info;
  1772. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1773. if (!tx_exc_metadata)
  1774. goto fail;
  1775. msdu_info.tid = tx_exc_metadata->tid;
  1776. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1777. dp_verbose_debug("skb %pM", nbuf->data);
  1778. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1779. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1780. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1781. "Invalid parameters in exception path");
  1782. goto fail;
  1783. }
  1784. /* Basic sanity checks for unsupported packets */
  1785. /* MESH mode */
  1786. if (qdf_unlikely(vdev->mesh_vdev)) {
  1787. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1788. "Mesh mode is not supported in exception path");
  1789. goto fail;
  1790. }
  1791. /* TSO or SG */
  1792. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1793. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1794. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1795. "TSO and SG are not supported in exception path");
  1796. goto fail;
  1797. }
  1798. /* RAW */
  1799. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1800. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1801. "Raw frame is not supported in exception path");
  1802. goto fail;
  1803. }
  1804. /* Mcast enhancement*/
  1805. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1806. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1807. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1808. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1809. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1810. }
  1811. }
  1812. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1813. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1814. qdf_nbuf_len(nbuf));
  1815. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1816. tx_exc_metadata->ppdu_cookie);
  1817. }
  1818. /*
  1819. * Get HW Queue to use for this frame.
  1820. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1821. * dedicated for data and 1 for command.
  1822. * "queue_id" maps to one hardware ring.
  1823. * With each ring, we also associate a unique Tx descriptor pool
  1824. * to minimize lock contention for these resources.
  1825. */
  1826. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1827. /* Single linear frame */
  1828. /*
  1829. * If nbuf is a simple linear frame, use send_single function to
  1830. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1831. * SRNG. There is no need to setup a MSDU extension descriptor.
  1832. */
  1833. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1834. tx_exc_metadata->peer_id, tx_exc_metadata);
  1835. return nbuf;
  1836. fail:
  1837. dp_verbose_debug("pkt send failed");
  1838. return nbuf;
  1839. }
  1840. /**
  1841. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1842. * @vap_dev: DP vdev handle
  1843. * @nbuf: skb
  1844. *
  1845. * Entry point for Core Tx layer (DP_TX) invoked from
  1846. * hard_start_xmit in OSIF/HDD
  1847. *
  1848. * Return: NULL on success,
  1849. * nbuf when it fails to send
  1850. */
  1851. #ifdef MESH_MODE_SUPPORT
  1852. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1853. {
  1854. struct meta_hdr_s *mhdr;
  1855. qdf_nbuf_t nbuf_mesh = NULL;
  1856. qdf_nbuf_t nbuf_clone = NULL;
  1857. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1858. uint8_t no_enc_frame = 0;
  1859. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1860. if (!nbuf_mesh) {
  1861. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1862. "qdf_nbuf_unshare failed");
  1863. return nbuf;
  1864. }
  1865. nbuf = nbuf_mesh;
  1866. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1867. if ((vdev->sec_type != cdp_sec_type_none) &&
  1868. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1869. no_enc_frame = 1;
  1870. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1871. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1872. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1873. !no_enc_frame) {
  1874. nbuf_clone = qdf_nbuf_clone(nbuf);
  1875. if (!nbuf_clone) {
  1876. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1877. "qdf_nbuf_clone failed");
  1878. return nbuf;
  1879. }
  1880. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1881. }
  1882. if (nbuf_clone) {
  1883. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1884. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1885. } else {
  1886. qdf_nbuf_free(nbuf_clone);
  1887. }
  1888. }
  1889. if (no_enc_frame)
  1890. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1891. else
  1892. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1893. nbuf = dp_tx_send(vap_dev, nbuf);
  1894. if ((!nbuf) && no_enc_frame) {
  1895. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1896. }
  1897. return nbuf;
  1898. }
  1899. #else
  1900. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1901. {
  1902. return dp_tx_send(vap_dev, nbuf);
  1903. }
  1904. #endif
  1905. /**
  1906. * dp_tx_send() - Transmit a frame on a given VAP
  1907. * @vap_dev: DP vdev handle
  1908. * @nbuf: skb
  1909. *
  1910. * Entry point for Core Tx layer (DP_TX) invoked from
  1911. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1912. * cases
  1913. *
  1914. * Return: NULL on success,
  1915. * nbuf when it fails to send
  1916. */
  1917. qdf_nbuf_t dp_tx_send(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1918. {
  1919. qdf_ether_header_t *eh = NULL;
  1920. struct dp_tx_msdu_info_s msdu_info;
  1921. struct dp_tx_seg_info_s seg_info;
  1922. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1923. uint16_t peer_id = HTT_INVALID_PEER;
  1924. qdf_nbuf_t nbuf_mesh = NULL;
  1925. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1926. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1927. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1928. dp_verbose_debug("skb %pM", nbuf->data);
  1929. /*
  1930. * Set Default Host TID value to invalid TID
  1931. * (TID override disabled)
  1932. */
  1933. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1934. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1935. if (qdf_unlikely(vdev->mesh_vdev)) {
  1936. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1937. &msdu_info);
  1938. if (!nbuf_mesh) {
  1939. dp_verbose_debug("Extracting mesh metadata failed");
  1940. return nbuf;
  1941. }
  1942. nbuf = nbuf_mesh;
  1943. }
  1944. /*
  1945. * Get HW Queue to use for this frame.
  1946. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1947. * dedicated for data and 1 for command.
  1948. * "queue_id" maps to one hardware ring.
  1949. * With each ring, we also associate a unique Tx descriptor pool
  1950. * to minimize lock contention for these resources.
  1951. */
  1952. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1953. /*
  1954. * TCL H/W supports 2 DSCP-TID mapping tables.
  1955. * Table 1 - Default DSCP-TID mapping table
  1956. * Table 2 - 1 DSCP-TID override table
  1957. *
  1958. * If we need a different DSCP-TID mapping for this vap,
  1959. * call tid_classify to extract DSCP/ToS from frame and
  1960. * map to a TID and store in msdu_info. This is later used
  1961. * to fill in TCL Input descriptor (per-packet TID override).
  1962. */
  1963. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1964. /*
  1965. * Classify the frame and call corresponding
  1966. * "prepare" function which extracts the segment (TSO)
  1967. * and fragmentation information (for TSO , SG, ME, or Raw)
  1968. * into MSDU_INFO structure which is later used to fill
  1969. * SW and HW descriptors.
  1970. */
  1971. if (qdf_nbuf_is_tso(nbuf)) {
  1972. dp_verbose_debug("TSO frame %pK", vdev);
  1973. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  1974. qdf_nbuf_len(nbuf));
  1975. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1976. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  1977. qdf_nbuf_len(nbuf));
  1978. return nbuf;
  1979. }
  1980. goto send_multiple;
  1981. }
  1982. /* SG */
  1983. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1984. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1985. if (!nbuf)
  1986. return NULL;
  1987. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1988. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1989. qdf_nbuf_len(nbuf));
  1990. goto send_multiple;
  1991. }
  1992. #ifdef ATH_SUPPORT_IQUE
  1993. /* Mcast to Ucast Conversion*/
  1994. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1995. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1996. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1997. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1998. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1999. DP_STATS_INC_PKT(vdev,
  2000. tx_i.mcast_en.mcast_pkt, 1,
  2001. qdf_nbuf_len(nbuf));
  2002. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2003. QDF_STATUS_SUCCESS) {
  2004. return NULL;
  2005. }
  2006. }
  2007. }
  2008. #endif
  2009. /* RAW */
  2010. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2011. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2012. if (!nbuf)
  2013. return NULL;
  2014. dp_verbose_debug("Raw frame %pK", vdev);
  2015. goto send_multiple;
  2016. }
  2017. /* Single linear frame */
  2018. /*
  2019. * If nbuf is a simple linear frame, use send_single function to
  2020. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2021. * SRNG. There is no need to setup a MSDU extension descriptor.
  2022. */
  2023. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2024. return nbuf;
  2025. send_multiple:
  2026. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2027. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2028. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2029. return nbuf;
  2030. }
  2031. /**
  2032. * dp_tx_reinject_handler() - Tx Reinject Handler
  2033. * @tx_desc: software descriptor head pointer
  2034. * @status : Tx completion status from HTT descriptor
  2035. *
  2036. * This function reinjects frames back to Target.
  2037. * Todo - Host queue needs to be added
  2038. *
  2039. * Return: none
  2040. */
  2041. static
  2042. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2043. {
  2044. struct dp_vdev *vdev;
  2045. struct dp_peer *peer = NULL;
  2046. uint32_t peer_id = HTT_INVALID_PEER;
  2047. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2048. qdf_nbuf_t nbuf_copy = NULL;
  2049. struct dp_tx_msdu_info_s msdu_info;
  2050. struct dp_peer *sa_peer = NULL;
  2051. struct dp_ast_entry *ast_entry = NULL;
  2052. struct dp_soc *soc = NULL;
  2053. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2054. #ifdef WDS_VENDOR_EXTENSION
  2055. int is_mcast = 0, is_ucast = 0;
  2056. int num_peers_3addr = 0;
  2057. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2058. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2059. #endif
  2060. vdev = tx_desc->vdev;
  2061. soc = vdev->pdev->soc;
  2062. qdf_assert(vdev);
  2063. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2064. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2065. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2066. "%s Tx reinject path", __func__);
  2067. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2068. qdf_nbuf_len(tx_desc->nbuf));
  2069. qdf_spin_lock_bh(&(soc->ast_lock));
  2070. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2071. (soc,
  2072. (uint8_t *)(eh->ether_shost),
  2073. vdev->pdev->pdev_id);
  2074. if (ast_entry)
  2075. sa_peer = ast_entry->peer;
  2076. qdf_spin_unlock_bh(&(soc->ast_lock));
  2077. #ifdef WDS_VENDOR_EXTENSION
  2078. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2079. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2080. } else {
  2081. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2082. }
  2083. is_ucast = !is_mcast;
  2084. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2085. if (peer->bss_peer)
  2086. continue;
  2087. /* Detect wds peers that use 3-addr framing for mcast.
  2088. * if there are any, the bss_peer is used to send the
  2089. * the mcast frame using 3-addr format. all wds enabled
  2090. * peers that use 4-addr framing for mcast frames will
  2091. * be duplicated and sent as 4-addr frames below.
  2092. */
  2093. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2094. num_peers_3addr = 1;
  2095. break;
  2096. }
  2097. }
  2098. #endif
  2099. if (qdf_unlikely(vdev->mesh_vdev)) {
  2100. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2101. } else {
  2102. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2103. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2104. #ifdef WDS_VENDOR_EXTENSION
  2105. /*
  2106. * . if 3-addr STA, then send on BSS Peer
  2107. * . if Peer WDS enabled and accept 4-addr mcast,
  2108. * send mcast on that peer only
  2109. * . if Peer WDS enabled and accept 4-addr ucast,
  2110. * send ucast on that peer only
  2111. */
  2112. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2113. (peer->wds_enabled &&
  2114. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2115. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2116. #else
  2117. ((peer->bss_peer &&
  2118. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2119. peer->nawds_enabled)) {
  2120. #endif
  2121. peer_id = DP_INVALID_PEER;
  2122. if (peer->nawds_enabled) {
  2123. peer_id = peer->peer_ids[0];
  2124. if (sa_peer == peer) {
  2125. QDF_TRACE(
  2126. QDF_MODULE_ID_DP,
  2127. QDF_TRACE_LEVEL_DEBUG,
  2128. " %s: multicast packet",
  2129. __func__);
  2130. DP_STATS_INC(peer,
  2131. tx.nawds_mcast_drop, 1);
  2132. continue;
  2133. }
  2134. }
  2135. nbuf_copy = qdf_nbuf_copy(nbuf);
  2136. if (!nbuf_copy) {
  2137. QDF_TRACE(QDF_MODULE_ID_DP,
  2138. QDF_TRACE_LEVEL_DEBUG,
  2139. FL("nbuf copy failed"));
  2140. break;
  2141. }
  2142. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2143. nbuf_copy,
  2144. &msdu_info,
  2145. peer_id,
  2146. NULL);
  2147. if (nbuf_copy) {
  2148. QDF_TRACE(QDF_MODULE_ID_DP,
  2149. QDF_TRACE_LEVEL_DEBUG,
  2150. FL("pkt send failed"));
  2151. qdf_nbuf_free(nbuf_copy);
  2152. } else {
  2153. if (peer_id != DP_INVALID_PEER)
  2154. DP_STATS_INC_PKT(peer,
  2155. tx.nawds_mcast,
  2156. 1, qdf_nbuf_len(nbuf));
  2157. }
  2158. }
  2159. }
  2160. }
  2161. if (vdev->nawds_enabled) {
  2162. peer_id = DP_INVALID_PEER;
  2163. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2164. 1, qdf_nbuf_len(nbuf));
  2165. nbuf = dp_tx_send_msdu_single(vdev,
  2166. nbuf,
  2167. &msdu_info,
  2168. peer_id, NULL);
  2169. if (nbuf) {
  2170. QDF_TRACE(QDF_MODULE_ID_DP,
  2171. QDF_TRACE_LEVEL_DEBUG,
  2172. FL("pkt send failed"));
  2173. qdf_nbuf_free(nbuf);
  2174. }
  2175. } else
  2176. qdf_nbuf_free(nbuf);
  2177. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2178. }
  2179. /**
  2180. * dp_tx_inspect_handler() - Tx Inspect Handler
  2181. * @tx_desc: software descriptor head pointer
  2182. * @status : Tx completion status from HTT descriptor
  2183. *
  2184. * Handles Tx frames sent back to Host for inspection
  2185. * (ProxyARP)
  2186. *
  2187. * Return: none
  2188. */
  2189. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2190. {
  2191. struct dp_soc *soc;
  2192. struct dp_pdev *pdev = tx_desc->pdev;
  2193. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2194. "%s Tx inspect path",
  2195. __func__);
  2196. qdf_assert(pdev);
  2197. soc = pdev->soc;
  2198. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2199. qdf_nbuf_len(tx_desc->nbuf));
  2200. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2201. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2202. }
  2203. #ifdef FEATURE_PERPKT_INFO
  2204. /**
  2205. * dp_get_completion_indication_for_stack() - send completion to stack
  2206. * @soc : dp_soc handle
  2207. * @pdev: dp_pdev handle
  2208. * @peer: dp peer handle
  2209. * @ts: transmit completion status structure
  2210. * @netbuf: Buffer pointer for free
  2211. *
  2212. * This function is used for indication whether buffer needs to be
  2213. * sent to stack for freeing or not
  2214. */
  2215. QDF_STATUS
  2216. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2217. struct dp_pdev *pdev,
  2218. struct dp_peer *peer,
  2219. struct hal_tx_completion_status *ts,
  2220. qdf_nbuf_t netbuf,
  2221. uint64_t time_latency)
  2222. {
  2223. struct tx_capture_hdr *ppdu_hdr;
  2224. uint16_t peer_id = ts->peer_id;
  2225. uint32_t ppdu_id = ts->ppdu_id;
  2226. uint8_t first_msdu = ts->first_msdu;
  2227. uint8_t last_msdu = ts->last_msdu;
  2228. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2229. !pdev->latency_capture_enable))
  2230. return QDF_STATUS_E_NOSUPPORT;
  2231. if (!peer) {
  2232. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2233. FL("Peer Invalid"));
  2234. return QDF_STATUS_E_INVAL;
  2235. }
  2236. if (pdev->mcopy_mode) {
  2237. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2238. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2239. return QDF_STATUS_E_INVAL;
  2240. }
  2241. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2242. pdev->m_copy_id.tx_peer_id = peer_id;
  2243. }
  2244. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2245. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2246. FL("No headroom"));
  2247. return QDF_STATUS_E_NOMEM;
  2248. }
  2249. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2250. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2251. QDF_MAC_ADDR_SIZE);
  2252. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2253. QDF_MAC_ADDR_SIZE);
  2254. ppdu_hdr->ppdu_id = ppdu_id;
  2255. ppdu_hdr->peer_id = peer_id;
  2256. ppdu_hdr->first_msdu = first_msdu;
  2257. ppdu_hdr->last_msdu = last_msdu;
  2258. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2259. ppdu_hdr->tsf = ts->tsf;
  2260. ppdu_hdr->time_latency = time_latency;
  2261. }
  2262. return QDF_STATUS_SUCCESS;
  2263. }
  2264. /**
  2265. * dp_send_completion_to_stack() - send completion to stack
  2266. * @soc : dp_soc handle
  2267. * @pdev: dp_pdev handle
  2268. * @peer_id: peer_id of the peer for which completion came
  2269. * @ppdu_id: ppdu_id
  2270. * @netbuf: Buffer pointer for free
  2271. *
  2272. * This function is used to send completion to stack
  2273. * to free buffer
  2274. */
  2275. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2276. uint16_t peer_id, uint32_t ppdu_id,
  2277. qdf_nbuf_t netbuf)
  2278. {
  2279. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2280. netbuf, peer_id,
  2281. WDI_NO_VAL, pdev->pdev_id);
  2282. }
  2283. #else
  2284. static QDF_STATUS
  2285. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2286. struct dp_pdev *pdev,
  2287. struct dp_peer *peer,
  2288. struct hal_tx_completion_status *ts,
  2289. qdf_nbuf_t netbuf,
  2290. uint64_t time_latency)
  2291. {
  2292. return QDF_STATUS_E_NOSUPPORT;
  2293. }
  2294. static void
  2295. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2296. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2297. {
  2298. }
  2299. #endif
  2300. /**
  2301. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2302. * @soc: Soc handle
  2303. * @desc: software Tx descriptor to be processed
  2304. *
  2305. * Return: none
  2306. */
  2307. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2308. struct dp_tx_desc_s *desc)
  2309. {
  2310. struct dp_vdev *vdev = desc->vdev;
  2311. qdf_nbuf_t nbuf = desc->nbuf;
  2312. /* nbuf already freed in vdev detach path */
  2313. if (!nbuf)
  2314. return;
  2315. /* If it is TDLS mgmt, don't unmap or free the frame */
  2316. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2317. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2318. /* 0 : MSDU buffer, 1 : MLE */
  2319. if (desc->msdu_ext_desc) {
  2320. /* TSO free */
  2321. if (hal_tx_ext_desc_get_tso_enable(
  2322. desc->msdu_ext_desc->vaddr)) {
  2323. /* unmap eash TSO seg before free the nbuf */
  2324. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2325. desc->tso_num_desc);
  2326. qdf_nbuf_free(nbuf);
  2327. return;
  2328. }
  2329. }
  2330. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2331. if (qdf_unlikely(!vdev)) {
  2332. qdf_nbuf_free(nbuf);
  2333. return;
  2334. }
  2335. if (qdf_likely(!vdev->mesh_vdev))
  2336. qdf_nbuf_free(nbuf);
  2337. else {
  2338. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2339. qdf_nbuf_free(nbuf);
  2340. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2341. } else
  2342. vdev->osif_tx_free_ext((nbuf));
  2343. }
  2344. }
  2345. #ifdef MESH_MODE_SUPPORT
  2346. /**
  2347. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2348. * in mesh meta header
  2349. * @tx_desc: software descriptor head pointer
  2350. * @ts: pointer to tx completion stats
  2351. * Return: none
  2352. */
  2353. static
  2354. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2355. struct hal_tx_completion_status *ts)
  2356. {
  2357. struct meta_hdr_s *mhdr;
  2358. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2359. if (!tx_desc->msdu_ext_desc) {
  2360. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2361. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2362. "netbuf %pK offset %d",
  2363. netbuf, tx_desc->pkt_offset);
  2364. return;
  2365. }
  2366. }
  2367. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2368. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2369. "netbuf %pK offset %lu", netbuf,
  2370. sizeof(struct meta_hdr_s));
  2371. return;
  2372. }
  2373. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2374. mhdr->rssi = ts->ack_frame_rssi;
  2375. mhdr->channel = tx_desc->pdev->operating_channel;
  2376. }
  2377. #else
  2378. static
  2379. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2380. struct hal_tx_completion_status *ts)
  2381. {
  2382. }
  2383. #endif
  2384. /**
  2385. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2386. * to pass in correct fields
  2387. *
  2388. * @vdev: pdev handle
  2389. * @tx_desc: tx descriptor
  2390. * @tid: tid value
  2391. * @ring_id: TCL or WBM ring number for transmit path
  2392. * Return: none
  2393. */
  2394. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2395. struct dp_tx_desc_s *tx_desc,
  2396. uint8_t tid, uint8_t ring_id)
  2397. {
  2398. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2399. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2400. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2401. return;
  2402. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2403. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2404. timestamp_hw_enqueue = tx_desc->timestamp;
  2405. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2406. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2407. timestamp_hw_enqueue);
  2408. interframe_delay = (uint32_t)(timestamp_ingress -
  2409. vdev->prev_tx_enq_tstamp);
  2410. /*
  2411. * Delay in software enqueue
  2412. */
  2413. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2414. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2415. /*
  2416. * Delay between packet enqueued to HW and Tx completion
  2417. */
  2418. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2419. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2420. /*
  2421. * Update interframe delay stats calculated at hardstart receive point.
  2422. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2423. * interframe delay will not be calculate correctly for 1st frame.
  2424. * On the other side, this will help in avoiding extra per packet check
  2425. * of !vdev->prev_tx_enq_tstamp.
  2426. */
  2427. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2428. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2429. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2430. }
  2431. /**
  2432. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2433. * per wbm ring
  2434. *
  2435. * @tx_desc: software descriptor head pointer
  2436. * @ts: Tx completion status
  2437. * @peer: peer handle
  2438. * @ring_id: ring number
  2439. *
  2440. * Return: None
  2441. */
  2442. static inline void
  2443. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2444. struct hal_tx_completion_status *ts,
  2445. struct dp_peer *peer, uint8_t ring_id)
  2446. {
  2447. struct dp_pdev *pdev = peer->vdev->pdev;
  2448. struct dp_soc *soc = NULL;
  2449. uint8_t mcs, pkt_type;
  2450. uint8_t tid = ts->tid;
  2451. uint32_t length;
  2452. struct cdp_tid_tx_stats *tid_stats;
  2453. if (!pdev)
  2454. return;
  2455. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2456. tid = CDP_MAX_DATA_TIDS - 1;
  2457. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2458. soc = pdev->soc;
  2459. mcs = ts->mcs;
  2460. pkt_type = ts->pkt_type;
  2461. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2462. dp_err("Release source is not from TQM");
  2463. return;
  2464. }
  2465. length = qdf_nbuf_len(tx_desc->nbuf);
  2466. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2467. if (qdf_unlikely(pdev->delay_stats_flag))
  2468. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2469. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2470. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2471. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2472. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2473. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2474. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2475. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2476. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2477. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2478. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2479. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2480. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2481. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2482. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2483. /*
  2484. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2485. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2486. * are no completions for failed cases. Hence updating tx_failed from
  2487. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2488. * then this has to be removed
  2489. */
  2490. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2491. peer->stats.tx.dropped.fw_rem_notx +
  2492. peer->stats.tx.dropped.fw_rem_tx +
  2493. peer->stats.tx.dropped.age_out +
  2494. peer->stats.tx.dropped.fw_reason1 +
  2495. peer->stats.tx.dropped.fw_reason2 +
  2496. peer->stats.tx.dropped.fw_reason3;
  2497. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2498. tid_stats->tqm_status_cnt[ts->status]++;
  2499. }
  2500. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2501. return;
  2502. }
  2503. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2504. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2505. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2506. /*
  2507. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2508. * Return from here if HTT PPDU events are enabled.
  2509. */
  2510. if (!(soc->process_tx_status))
  2511. return;
  2512. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2513. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2514. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2515. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2516. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2517. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2518. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2519. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2520. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2521. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2522. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2523. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2524. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2525. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2526. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2527. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2528. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2529. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2530. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2531. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2532. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2533. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2534. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2535. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2536. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2537. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2538. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2539. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2540. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2541. &peer->stats, ts->peer_id,
  2542. UPDATE_PEER_STATS, pdev->pdev_id);
  2543. #endif
  2544. }
  2545. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2546. /**
  2547. * dp_tx_flow_pool_lock() - take flow pool lock
  2548. * @soc: core txrx main context
  2549. * @tx_desc: tx desc
  2550. *
  2551. * Return: None
  2552. */
  2553. static inline
  2554. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2555. struct dp_tx_desc_s *tx_desc)
  2556. {
  2557. struct dp_tx_desc_pool_s *pool;
  2558. uint8_t desc_pool_id;
  2559. desc_pool_id = tx_desc->pool_id;
  2560. pool = &soc->tx_desc[desc_pool_id];
  2561. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2562. }
  2563. /**
  2564. * dp_tx_flow_pool_unlock() - release flow pool lock
  2565. * @soc: core txrx main context
  2566. * @tx_desc: tx desc
  2567. *
  2568. * Return: None
  2569. */
  2570. static inline
  2571. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2572. struct dp_tx_desc_s *tx_desc)
  2573. {
  2574. struct dp_tx_desc_pool_s *pool;
  2575. uint8_t desc_pool_id;
  2576. desc_pool_id = tx_desc->pool_id;
  2577. pool = &soc->tx_desc[desc_pool_id];
  2578. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2579. }
  2580. #else
  2581. static inline
  2582. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2583. {
  2584. }
  2585. static inline
  2586. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2587. {
  2588. }
  2589. #endif
  2590. /**
  2591. * dp_tx_notify_completion() - Notify tx completion for this desc
  2592. * @soc: core txrx main context
  2593. * @tx_desc: tx desc
  2594. * @netbuf: buffer
  2595. *
  2596. * Return: none
  2597. */
  2598. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2599. struct dp_tx_desc_s *tx_desc,
  2600. qdf_nbuf_t netbuf)
  2601. {
  2602. void *osif_dev;
  2603. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2604. qdf_assert(tx_desc);
  2605. dp_tx_flow_pool_lock(soc, tx_desc);
  2606. if (!tx_desc->vdev ||
  2607. !tx_desc->vdev->osif_vdev) {
  2608. dp_tx_flow_pool_unlock(soc, tx_desc);
  2609. return;
  2610. }
  2611. osif_dev = tx_desc->vdev->osif_vdev;
  2612. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2613. dp_tx_flow_pool_unlock(soc, tx_desc);
  2614. if (tx_compl_cbk)
  2615. tx_compl_cbk(netbuf, osif_dev);
  2616. }
  2617. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2618. * @pdev: pdev handle
  2619. * @tid: tid value
  2620. * @txdesc_ts: timestamp from txdesc
  2621. * @ppdu_id: ppdu id
  2622. *
  2623. * Return: none
  2624. */
  2625. #ifdef FEATURE_PERPKT_INFO
  2626. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2627. struct dp_peer *peer,
  2628. uint8_t tid,
  2629. uint64_t txdesc_ts,
  2630. uint32_t ppdu_id)
  2631. {
  2632. uint64_t delta_ms;
  2633. struct cdp_tx_sojourn_stats *sojourn_stats;
  2634. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2635. return;
  2636. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2637. tid >= CDP_DATA_TID_MAX))
  2638. return;
  2639. if (qdf_unlikely(!pdev->sojourn_buf))
  2640. return;
  2641. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2642. qdf_nbuf_data(pdev->sojourn_buf);
  2643. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2644. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2645. txdesc_ts;
  2646. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2647. delta_ms);
  2648. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2649. sojourn_stats->num_msdus[tid] = 1;
  2650. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2651. peer->avg_sojourn_msdu[tid].internal;
  2652. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2653. pdev->sojourn_buf, HTT_INVALID_PEER,
  2654. WDI_NO_VAL, pdev->pdev_id);
  2655. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2656. sojourn_stats->num_msdus[tid] = 0;
  2657. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2658. }
  2659. #else
  2660. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2661. uint8_t tid,
  2662. uint64_t txdesc_ts,
  2663. uint32_t ppdu_id)
  2664. {
  2665. }
  2666. #endif
  2667. /**
  2668. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2669. * @soc: DP Soc handle
  2670. * @tx_desc: software Tx descriptor
  2671. * @ts : Tx completion status from HAL/HTT descriptor
  2672. *
  2673. * Return: none
  2674. */
  2675. static inline void
  2676. dp_tx_comp_process_desc(struct dp_soc *soc,
  2677. struct dp_tx_desc_s *desc,
  2678. struct hal_tx_completion_status *ts,
  2679. struct dp_peer *peer)
  2680. {
  2681. uint64_t time_latency = 0;
  2682. /*
  2683. * m_copy/tx_capture modes are not supported for
  2684. * scatter gather packets
  2685. */
  2686. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2687. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2688. desc->timestamp);
  2689. }
  2690. if (!(desc->msdu_ext_desc)) {
  2691. if (QDF_STATUS_SUCCESS ==
  2692. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2693. return;
  2694. }
  2695. if (QDF_STATUS_SUCCESS ==
  2696. dp_get_completion_indication_for_stack(soc,
  2697. desc->pdev,
  2698. peer, ts,
  2699. desc->nbuf,
  2700. time_latency)) {
  2701. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2702. QDF_DMA_TO_DEVICE);
  2703. dp_send_completion_to_stack(soc,
  2704. desc->pdev,
  2705. ts->peer_id,
  2706. ts->ppdu_id,
  2707. desc->nbuf);
  2708. return;
  2709. }
  2710. }
  2711. dp_tx_comp_free_buf(soc, desc);
  2712. }
  2713. /**
  2714. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2715. * @tx_desc: software descriptor head pointer
  2716. * @ts: Tx completion status
  2717. * @peer: peer handle
  2718. * @ring_id: ring number
  2719. *
  2720. * Return: none
  2721. */
  2722. static inline
  2723. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2724. struct hal_tx_completion_status *ts,
  2725. struct dp_peer *peer, uint8_t ring_id)
  2726. {
  2727. uint32_t length;
  2728. qdf_ether_header_t *eh;
  2729. struct dp_soc *soc = NULL;
  2730. struct dp_vdev *vdev = tx_desc->vdev;
  2731. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2732. if (!vdev || !nbuf) {
  2733. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2734. "invalid tx descriptor. vdev or nbuf NULL");
  2735. goto out;
  2736. }
  2737. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2738. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2739. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2740. QDF_TRACE_DEFAULT_PDEV_ID,
  2741. qdf_nbuf_data_addr(nbuf),
  2742. sizeof(qdf_nbuf_data(nbuf)),
  2743. tx_desc->id,
  2744. ts->status));
  2745. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2746. "-------------------- \n"
  2747. "Tx Completion Stats: \n"
  2748. "-------------------- \n"
  2749. "ack_frame_rssi = %d \n"
  2750. "first_msdu = %d \n"
  2751. "last_msdu = %d \n"
  2752. "msdu_part_of_amsdu = %d \n"
  2753. "rate_stats valid = %d \n"
  2754. "bw = %d \n"
  2755. "pkt_type = %d \n"
  2756. "stbc = %d \n"
  2757. "ldpc = %d \n"
  2758. "sgi = %d \n"
  2759. "mcs = %d \n"
  2760. "ofdma = %d \n"
  2761. "tones_in_ru = %d \n"
  2762. "tsf = %d \n"
  2763. "ppdu_id = %d \n"
  2764. "transmit_cnt = %d \n"
  2765. "tid = %d \n"
  2766. "peer_id = %d\n",
  2767. ts->ack_frame_rssi, ts->first_msdu,
  2768. ts->last_msdu, ts->msdu_part_of_amsdu,
  2769. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2770. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2771. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2772. ts->transmit_cnt, ts->tid, ts->peer_id);
  2773. soc = vdev->pdev->soc;
  2774. /* Update SoC level stats */
  2775. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2776. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2777. /* Update per-packet stats for mesh mode */
  2778. if (qdf_unlikely(vdev->mesh_vdev) &&
  2779. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2780. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2781. length = qdf_nbuf_len(nbuf);
  2782. /* Update peer level stats */
  2783. if (!peer) {
  2784. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2785. "peer is null or deletion in progress");
  2786. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2787. goto out;
  2788. }
  2789. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2790. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2791. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2792. if ((peer->vdev->tx_encap_type ==
  2793. htt_cmn_pkt_type_ethernet) &&
  2794. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2795. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2796. }
  2797. }
  2798. } else {
  2799. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2800. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2801. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2802. }
  2803. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2804. #ifdef QCA_SUPPORT_RDK_STATS
  2805. if (soc->wlanstats_enabled)
  2806. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2807. tx_desc->timestamp,
  2808. ts->ppdu_id);
  2809. #endif
  2810. out:
  2811. return;
  2812. }
  2813. /**
  2814. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2815. * @soc: core txrx main context
  2816. * @comp_head: software descriptor head pointer
  2817. * @ring_id: ring number
  2818. *
  2819. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2820. * and release the software descriptors after processing is complete
  2821. *
  2822. * Return: none
  2823. */
  2824. static void
  2825. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2826. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2827. {
  2828. struct dp_tx_desc_s *desc;
  2829. struct dp_tx_desc_s *next;
  2830. struct hal_tx_completion_status ts = {0};
  2831. struct dp_peer *peer;
  2832. qdf_nbuf_t netbuf;
  2833. desc = comp_head;
  2834. while (desc) {
  2835. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2836. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2837. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2838. netbuf = desc->nbuf;
  2839. /* check tx complete notification */
  2840. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2841. dp_tx_notify_completion(soc, desc, netbuf);
  2842. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2843. if (peer)
  2844. dp_peer_unref_del_find_by_id(peer);
  2845. next = desc->next;
  2846. dp_tx_desc_release(desc, desc->pool_id);
  2847. desc = next;
  2848. }
  2849. }
  2850. /**
  2851. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2852. * @tx_desc: software descriptor head pointer
  2853. * @status : Tx completion status from HTT descriptor
  2854. * @ring_id: ring number
  2855. *
  2856. * This function will process HTT Tx indication messages from Target
  2857. *
  2858. * Return: none
  2859. */
  2860. static
  2861. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2862. uint8_t ring_id)
  2863. {
  2864. uint8_t tx_status;
  2865. struct dp_pdev *pdev;
  2866. struct dp_vdev *vdev;
  2867. struct dp_soc *soc;
  2868. struct hal_tx_completion_status ts = {0};
  2869. uint32_t *htt_desc = (uint32_t *)status;
  2870. struct dp_peer *peer;
  2871. struct cdp_tid_tx_stats *tid_stats = NULL;
  2872. struct htt_soc *htt_handle;
  2873. qdf_assert(tx_desc->pdev);
  2874. pdev = tx_desc->pdev;
  2875. vdev = tx_desc->vdev;
  2876. soc = pdev->soc;
  2877. if (!vdev)
  2878. return;
  2879. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2880. htt_handle = (struct htt_soc *)soc->htt_handle;
  2881. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  2882. switch (tx_status) {
  2883. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2884. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2885. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2886. {
  2887. uint8_t tid;
  2888. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2889. ts.peer_id =
  2890. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2891. htt_desc[2]);
  2892. ts.tid =
  2893. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2894. htt_desc[2]);
  2895. } else {
  2896. ts.peer_id = HTT_INVALID_PEER;
  2897. ts.tid = HTT_INVALID_TID;
  2898. }
  2899. ts.ppdu_id =
  2900. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2901. htt_desc[1]);
  2902. ts.ack_frame_rssi =
  2903. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2904. htt_desc[1]);
  2905. ts.first_msdu = 1;
  2906. ts.last_msdu = 1;
  2907. tid = ts.tid;
  2908. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2909. tid = CDP_MAX_DATA_TIDS - 1;
  2910. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2911. if (qdf_unlikely(pdev->delay_stats_flag))
  2912. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2913. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  2914. tid_stats->htt_status_cnt[tx_status]++;
  2915. }
  2916. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2917. if (qdf_likely(peer))
  2918. dp_peer_unref_del_find_by_id(peer);
  2919. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2920. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2921. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2922. break;
  2923. }
  2924. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2925. {
  2926. dp_tx_reinject_handler(tx_desc, status);
  2927. break;
  2928. }
  2929. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2930. {
  2931. dp_tx_inspect_handler(tx_desc, status);
  2932. break;
  2933. }
  2934. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2935. {
  2936. dp_tx_mec_handler(vdev, status);
  2937. break;
  2938. }
  2939. default:
  2940. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2941. "%s Invalid HTT tx_status %d\n",
  2942. __func__, tx_status);
  2943. break;
  2944. }
  2945. }
  2946. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2947. static inline
  2948. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2949. {
  2950. bool limit_hit = false;
  2951. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2952. limit_hit =
  2953. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2954. if (limit_hit)
  2955. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2956. return limit_hit;
  2957. }
  2958. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2959. {
  2960. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2961. }
  2962. #else
  2963. static inline
  2964. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2965. {
  2966. return false;
  2967. }
  2968. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2969. {
  2970. return false;
  2971. }
  2972. #endif
  2973. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2974. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  2975. uint32_t quota)
  2976. {
  2977. void *tx_comp_hal_desc;
  2978. uint8_t buffer_src;
  2979. uint8_t pool_id;
  2980. uint32_t tx_desc_id;
  2981. struct dp_tx_desc_s *tx_desc = NULL;
  2982. struct dp_tx_desc_s *head_desc = NULL;
  2983. struct dp_tx_desc_s *tail_desc = NULL;
  2984. uint32_t num_processed = 0;
  2985. uint32_t count = 0;
  2986. bool force_break = false;
  2987. DP_HIST_INIT();
  2988. more_data:
  2989. /* Re-initialize local variables to be re-used */
  2990. head_desc = NULL;
  2991. tail_desc = NULL;
  2992. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  2993. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2994. "%s %d : HAL RING Access Failed -- %pK",
  2995. __func__, __LINE__, hal_ring_hdl);
  2996. return 0;
  2997. }
  2998. /* Find head descriptor from completion ring */
  2999. while (qdf_likely(tx_comp_hal_desc =
  3000. hal_srng_dst_get_next(soc->hal_soc, hal_ring_hdl))) {
  3001. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3002. /* If this buffer was not released by TQM or FW, then it is not
  3003. * Tx completion indication, assert */
  3004. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3005. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3006. uint8_t wbm_internal_error;
  3007. QDF_TRACE(QDF_MODULE_ID_DP,
  3008. QDF_TRACE_LEVEL_FATAL,
  3009. "Tx comp release_src != TQM | FW but from %d",
  3010. buffer_src);
  3011. hal_dump_comp_desc(tx_comp_hal_desc);
  3012. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3013. /* When WBM sees NULL buffer_addr_info in any of
  3014. * ingress rings it sends an error indication,
  3015. * with wbm_internal_error=1, to a specific ring.
  3016. * The WBM2SW ring used to indicate these errors is
  3017. * fixed in HW, and that ring is being used as Tx
  3018. * completion ring. These errors are not related to
  3019. * Tx completions, and should just be ignored
  3020. */
  3021. wbm_internal_error =
  3022. hal_get_wbm_internal_error(tx_comp_hal_desc);
  3023. if (wbm_internal_error) {
  3024. QDF_TRACE(QDF_MODULE_ID_DP,
  3025. QDF_TRACE_LEVEL_ERROR,
  3026. "Tx comp wbm_internal_error!!!\n");
  3027. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3028. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3029. buffer_src)
  3030. dp_handle_wbm_internal_error(
  3031. soc,
  3032. tx_comp_hal_desc,
  3033. hal_tx_comp_get_buffer_type(
  3034. tx_comp_hal_desc));
  3035. continue;
  3036. } else {
  3037. qdf_assert_always(0);
  3038. }
  3039. }
  3040. /* Get descriptor id */
  3041. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3042. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3043. DP_TX_DESC_ID_POOL_OS;
  3044. /* Find Tx descriptor */
  3045. tx_desc = dp_tx_desc_find(soc, pool_id,
  3046. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3047. DP_TX_DESC_ID_PAGE_OS,
  3048. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3049. DP_TX_DESC_ID_OFFSET_OS);
  3050. /*
  3051. * If the descriptor is already freed in vdev_detach,
  3052. * continue to next descriptor
  3053. */
  3054. if (!tx_desc->vdev && !tx_desc->flags) {
  3055. QDF_TRACE(QDF_MODULE_ID_DP,
  3056. QDF_TRACE_LEVEL_INFO,
  3057. "Descriptor freed in vdev_detach %d",
  3058. tx_desc_id);
  3059. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3060. count++;
  3061. continue;
  3062. }
  3063. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3064. QDF_TRACE(QDF_MODULE_ID_DP,
  3065. QDF_TRACE_LEVEL_INFO,
  3066. "pdev in down state %d",
  3067. tx_desc_id);
  3068. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3069. count++;
  3070. dp_tx_comp_free_buf(soc, tx_desc);
  3071. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3072. continue;
  3073. }
  3074. /*
  3075. * If the release source is FW, process the HTT status
  3076. */
  3077. if (qdf_unlikely(buffer_src ==
  3078. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3079. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3080. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3081. htt_tx_status);
  3082. dp_tx_process_htt_completion(tx_desc,
  3083. htt_tx_status, ring_id);
  3084. } else {
  3085. /* Pool id is not matching. Error */
  3086. if (tx_desc->pool_id != pool_id) {
  3087. QDF_TRACE(QDF_MODULE_ID_DP,
  3088. QDF_TRACE_LEVEL_FATAL,
  3089. "Tx Comp pool id %d not matched %d",
  3090. pool_id, tx_desc->pool_id);
  3091. qdf_assert_always(0);
  3092. }
  3093. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3094. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3095. QDF_TRACE(QDF_MODULE_ID_DP,
  3096. QDF_TRACE_LEVEL_FATAL,
  3097. "Txdesc invalid, flgs = %x,id = %d",
  3098. tx_desc->flags, tx_desc_id);
  3099. qdf_assert_always(0);
  3100. }
  3101. /* First ring descriptor on the cycle */
  3102. if (!head_desc) {
  3103. head_desc = tx_desc;
  3104. tail_desc = tx_desc;
  3105. }
  3106. tail_desc->next = tx_desc;
  3107. tx_desc->next = NULL;
  3108. tail_desc = tx_desc;
  3109. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3110. /* Collect hw completion contents */
  3111. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3112. &tx_desc->comp, 1);
  3113. }
  3114. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3115. /*
  3116. * Processed packet count is more than given quota
  3117. * stop to processing
  3118. */
  3119. if (num_processed >= quota) {
  3120. force_break = true;
  3121. break;
  3122. }
  3123. count++;
  3124. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3125. break;
  3126. }
  3127. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3128. /* Process the reaped descriptors */
  3129. if (head_desc)
  3130. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3131. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3132. if (!force_break &&
  3133. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3134. hal_ring_hdl)) {
  3135. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3136. if (!hif_exec_should_yield(soc->hif_handle,
  3137. int_ctx->dp_intr_id))
  3138. goto more_data;
  3139. }
  3140. }
  3141. DP_TX_HIST_STATS_PER_PDEV();
  3142. return num_processed;
  3143. }
  3144. #ifdef FEATURE_WLAN_TDLS
  3145. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3146. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3147. {
  3148. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3149. struct dp_vdev *vdev = dp_get_vdev_from_soc_vdev_id_wifi3(soc, vdev_id);
  3150. if (!vdev) {
  3151. dp_err("vdev handle for id %d is NULL", vdev_id);
  3152. return NULL;
  3153. }
  3154. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3155. vdev->is_tdls_frame = true;
  3156. return dp_tx_send(dp_vdev_to_cdp_vdev(vdev), msdu_list);
  3157. }
  3158. #endif
  3159. /**
  3160. * dp_tx_vdev_attach() - attach vdev to dp tx
  3161. * @vdev: virtual device instance
  3162. *
  3163. * Return: QDF_STATUS_SUCCESS: success
  3164. * QDF_STATUS_E_RESOURCES: Error return
  3165. */
  3166. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3167. {
  3168. /*
  3169. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3170. */
  3171. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3172. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3173. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3174. vdev->vdev_id);
  3175. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3176. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3177. /*
  3178. * Set HTT Extension Valid bit to 0 by default
  3179. */
  3180. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3181. dp_tx_vdev_update_search_flags(vdev);
  3182. return QDF_STATUS_SUCCESS;
  3183. }
  3184. #ifndef FEATURE_WDS
  3185. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3186. {
  3187. return false;
  3188. }
  3189. #endif
  3190. /**
  3191. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3192. * @vdev: virtual device instance
  3193. *
  3194. * Return: void
  3195. *
  3196. */
  3197. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3198. {
  3199. struct dp_soc *soc = vdev->pdev->soc;
  3200. /*
  3201. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3202. * for TDLS link
  3203. *
  3204. * Enable AddrY (SA based search) only for non-WDS STA and
  3205. * ProxySTA VAP (in HKv1) modes.
  3206. *
  3207. * In all other VAP modes, only DA based search should be
  3208. * enabled
  3209. */
  3210. if (vdev->opmode == wlan_op_mode_sta &&
  3211. vdev->tdls_link_connected)
  3212. vdev->hal_desc_addr_search_flags =
  3213. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3214. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3215. !dp_tx_da_search_override(vdev))
  3216. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3217. else
  3218. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3219. /* Set search type only when peer map v2 messaging is enabled
  3220. * as we will have the search index (AST hash) only when v2 is
  3221. * enabled
  3222. */
  3223. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3224. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3225. else
  3226. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3227. }
  3228. static inline bool
  3229. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3230. struct dp_vdev *vdev,
  3231. struct dp_tx_desc_s *tx_desc)
  3232. {
  3233. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3234. return false;
  3235. /*
  3236. * if vdev is given, then only check whether desc
  3237. * vdev match. if vdev is NULL, then check whether
  3238. * desc pdev match.
  3239. */
  3240. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3241. }
  3242. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3243. /**
  3244. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3245. *
  3246. * @soc: Handle to DP SoC structure
  3247. * @tx_desc: pointer of one TX desc
  3248. * @desc_pool_id: TX Desc pool id
  3249. */
  3250. static inline void
  3251. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3252. uint8_t desc_pool_id)
  3253. {
  3254. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3255. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3256. tx_desc->vdev = NULL;
  3257. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3258. }
  3259. /**
  3260. * dp_tx_desc_flush() - release resources associated
  3261. * to TX Desc
  3262. *
  3263. * @dp_pdev: Handle to DP pdev structure
  3264. * @vdev: virtual device instance
  3265. * NULL: no specific Vdev is required and check all allcated TX desc
  3266. * on this pdev.
  3267. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3268. *
  3269. * @force_free:
  3270. * true: flush the TX desc.
  3271. * false: only reset the Vdev in each allocated TX desc
  3272. * that associated to current Vdev.
  3273. *
  3274. * This function will go through the TX desc pool to flush
  3275. * the outstanding TX data or reset Vdev to NULL in associated TX
  3276. * Desc.
  3277. */
  3278. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3279. struct dp_vdev *vdev,
  3280. bool force_free)
  3281. {
  3282. uint8_t i;
  3283. uint32_t j;
  3284. uint32_t num_desc, page_id, offset;
  3285. uint16_t num_desc_per_page;
  3286. struct dp_soc *soc = pdev->soc;
  3287. struct dp_tx_desc_s *tx_desc = NULL;
  3288. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3289. if (!vdev && !force_free) {
  3290. dp_err("Reset TX desc vdev, Vdev param is required!");
  3291. return;
  3292. }
  3293. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3294. tx_desc_pool = &soc->tx_desc[i];
  3295. if (!(tx_desc_pool->pool_size) ||
  3296. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3297. !(tx_desc_pool->desc_pages.cacheable_pages))
  3298. continue;
  3299. num_desc = tx_desc_pool->pool_size;
  3300. num_desc_per_page =
  3301. tx_desc_pool->desc_pages.num_element_per_page;
  3302. for (j = 0; j < num_desc; j++) {
  3303. page_id = j / num_desc_per_page;
  3304. offset = j % num_desc_per_page;
  3305. if (qdf_unlikely(!(tx_desc_pool->
  3306. desc_pages.cacheable_pages)))
  3307. break;
  3308. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3309. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3310. /*
  3311. * Free TX desc if force free is
  3312. * required, otherwise only reset vdev
  3313. * in this TX desc.
  3314. */
  3315. if (force_free) {
  3316. dp_tx_comp_free_buf(soc, tx_desc);
  3317. dp_tx_desc_release(tx_desc, i);
  3318. } else {
  3319. dp_tx_desc_reset_vdev(soc, tx_desc,
  3320. i);
  3321. }
  3322. }
  3323. }
  3324. }
  3325. }
  3326. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3327. static inline void
  3328. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3329. uint8_t desc_pool_id)
  3330. {
  3331. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3332. tx_desc->vdev = NULL;
  3333. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3334. }
  3335. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3336. struct dp_vdev *vdev,
  3337. bool force_free)
  3338. {
  3339. uint8_t i, num_pool;
  3340. uint32_t j;
  3341. uint32_t num_desc, page_id, offset;
  3342. uint16_t num_desc_per_page;
  3343. struct dp_soc *soc = pdev->soc;
  3344. struct dp_tx_desc_s *tx_desc = NULL;
  3345. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3346. if (!vdev && !force_free) {
  3347. dp_err("Reset TX desc vdev, Vdev param is required!");
  3348. return;
  3349. }
  3350. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3351. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3352. for (i = 0; i < num_pool; i++) {
  3353. tx_desc_pool = &soc->tx_desc[i];
  3354. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3355. continue;
  3356. num_desc_per_page =
  3357. tx_desc_pool->desc_pages.num_element_per_page;
  3358. for (j = 0; j < num_desc; j++) {
  3359. page_id = j / num_desc_per_page;
  3360. offset = j % num_desc_per_page;
  3361. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3362. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3363. if (force_free) {
  3364. dp_tx_comp_free_buf(soc, tx_desc);
  3365. dp_tx_desc_release(tx_desc, i);
  3366. } else {
  3367. dp_tx_desc_reset_vdev(soc, tx_desc,
  3368. i);
  3369. }
  3370. }
  3371. }
  3372. }
  3373. }
  3374. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3375. /**
  3376. * dp_tx_vdev_detach() - detach vdev from dp tx
  3377. * @vdev: virtual device instance
  3378. *
  3379. * Return: QDF_STATUS_SUCCESS: success
  3380. * QDF_STATUS_E_RESOURCES: Error return
  3381. */
  3382. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3383. {
  3384. struct dp_pdev *pdev = vdev->pdev;
  3385. /* Reset TX desc associated to this Vdev as NULL */
  3386. dp_tx_desc_flush(pdev, vdev, false);
  3387. dp_tx_vdev_multipass_deinit(vdev);
  3388. return QDF_STATUS_SUCCESS;
  3389. }
  3390. /**
  3391. * dp_tx_pdev_attach() - attach pdev to dp tx
  3392. * @pdev: physical device instance
  3393. *
  3394. * Return: QDF_STATUS_SUCCESS: success
  3395. * QDF_STATUS_E_RESOURCES: Error return
  3396. */
  3397. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3398. {
  3399. struct dp_soc *soc = pdev->soc;
  3400. /* Initialize Flow control counters */
  3401. qdf_atomic_init(&pdev->num_tx_exception);
  3402. qdf_atomic_init(&pdev->num_tx_outstanding);
  3403. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3404. /* Initialize descriptors in TCL Ring */
  3405. hal_tx_init_data_ring(soc->hal_soc,
  3406. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3407. }
  3408. return QDF_STATUS_SUCCESS;
  3409. }
  3410. /**
  3411. * dp_tx_pdev_detach() - detach pdev from dp tx
  3412. * @pdev: physical device instance
  3413. *
  3414. * Return: QDF_STATUS_SUCCESS: success
  3415. * QDF_STATUS_E_RESOURCES: Error return
  3416. */
  3417. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3418. {
  3419. /* flush TX outstanding data per pdev */
  3420. dp_tx_desc_flush(pdev, NULL, true);
  3421. dp_tx_me_exit(pdev);
  3422. return QDF_STATUS_SUCCESS;
  3423. }
  3424. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3425. /* Pools will be allocated dynamically */
  3426. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3427. int num_desc)
  3428. {
  3429. uint8_t i;
  3430. for (i = 0; i < num_pool; i++) {
  3431. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3432. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3433. }
  3434. return 0;
  3435. }
  3436. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3437. {
  3438. uint8_t i;
  3439. for (i = 0; i < num_pool; i++)
  3440. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3441. }
  3442. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3443. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3444. int num_desc)
  3445. {
  3446. uint8_t i;
  3447. /* Allocate software Tx descriptor pools */
  3448. for (i = 0; i < num_pool; i++) {
  3449. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3450. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3451. "%s Tx Desc Pool alloc %d failed %pK",
  3452. __func__, i, soc);
  3453. return ENOMEM;
  3454. }
  3455. }
  3456. return 0;
  3457. }
  3458. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3459. {
  3460. uint8_t i;
  3461. for (i = 0; i < num_pool; i++) {
  3462. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3463. if (dp_tx_desc_pool_free(soc, i)) {
  3464. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3465. "%s Tx Desc Pool Free failed", __func__);
  3466. }
  3467. }
  3468. }
  3469. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3470. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3471. /**
  3472. * dp_tso_attach_wifi3() - TSO attach handler
  3473. * @txrx_soc: Opaque Dp handle
  3474. *
  3475. * Reserve TSO descriptor buffers
  3476. *
  3477. * Return: QDF_STATUS_E_FAILURE on failure or
  3478. * QDF_STATUS_SUCCESS on success
  3479. */
  3480. static
  3481. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3482. {
  3483. return dp_tso_soc_attach(txrx_soc);
  3484. }
  3485. /**
  3486. * dp_tso_detach_wifi3() - TSO Detach handler
  3487. * @txrx_soc: Opaque Dp handle
  3488. *
  3489. * Deallocate TSO descriptor buffers
  3490. *
  3491. * Return: QDF_STATUS_E_FAILURE on failure or
  3492. * QDF_STATUS_SUCCESS on success
  3493. */
  3494. static
  3495. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3496. {
  3497. return dp_tso_soc_detach(txrx_soc);
  3498. }
  3499. #else
  3500. static
  3501. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3502. {
  3503. return QDF_STATUS_SUCCESS;
  3504. }
  3505. static
  3506. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3507. {
  3508. return QDF_STATUS_SUCCESS;
  3509. }
  3510. #endif
  3511. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3512. {
  3513. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3514. uint8_t i;
  3515. uint8_t num_pool;
  3516. uint32_t num_desc;
  3517. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3518. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3519. for (i = 0; i < num_pool; i++)
  3520. dp_tx_tso_desc_pool_free(soc, i);
  3521. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3522. __func__, num_pool, num_desc);
  3523. for (i = 0; i < num_pool; i++)
  3524. dp_tx_tso_num_seg_pool_free(soc, i);
  3525. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3526. __func__, num_pool, num_desc);
  3527. return QDF_STATUS_SUCCESS;
  3528. }
  3529. /**
  3530. * dp_tso_attach() - TSO attach handler
  3531. * @txrx_soc: Opaque Dp handle
  3532. *
  3533. * Reserve TSO descriptor buffers
  3534. *
  3535. * Return: QDF_STATUS_E_FAILURE on failure or
  3536. * QDF_STATUS_SUCCESS on success
  3537. */
  3538. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3539. {
  3540. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3541. uint8_t i;
  3542. uint8_t num_pool;
  3543. uint32_t num_desc;
  3544. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3545. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3546. for (i = 0; i < num_pool; i++) {
  3547. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3548. dp_err("TSO Desc Pool alloc %d failed %pK",
  3549. i, soc);
  3550. return QDF_STATUS_E_FAILURE;
  3551. }
  3552. }
  3553. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3554. __func__, num_pool, num_desc);
  3555. for (i = 0; i < num_pool; i++) {
  3556. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3557. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3558. i, soc);
  3559. return QDF_STATUS_E_FAILURE;
  3560. }
  3561. }
  3562. return QDF_STATUS_SUCCESS;
  3563. }
  3564. /**
  3565. * dp_tx_soc_detach() - detach soc from dp tx
  3566. * @soc: core txrx main context
  3567. *
  3568. * This function will detach dp tx into main device context
  3569. * will free dp tx resource and initialize resources
  3570. *
  3571. * Return: QDF_STATUS_SUCCESS: success
  3572. * QDF_STATUS_E_RESOURCES: Error return
  3573. */
  3574. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3575. {
  3576. uint8_t num_pool;
  3577. uint16_t num_desc;
  3578. uint16_t num_ext_desc;
  3579. uint8_t i;
  3580. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3581. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3582. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3583. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3584. dp_tx_flow_control_deinit(soc);
  3585. dp_tx_delete_static_pools(soc, num_pool);
  3586. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3587. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3588. __func__, num_pool, num_desc);
  3589. for (i = 0; i < num_pool; i++) {
  3590. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3591. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3592. "%s Tx Ext Desc Pool Free failed",
  3593. __func__);
  3594. return QDF_STATUS_E_RESOURCES;
  3595. }
  3596. }
  3597. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3598. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3599. __func__, num_pool, num_ext_desc);
  3600. status = dp_tso_detach_wifi3(soc);
  3601. if (status != QDF_STATUS_SUCCESS)
  3602. return status;
  3603. return QDF_STATUS_SUCCESS;
  3604. }
  3605. /**
  3606. * dp_tx_soc_attach() - attach soc to dp tx
  3607. * @soc: core txrx main context
  3608. *
  3609. * This function will attach dp tx into main device context
  3610. * will allocate dp tx resource and initialize resources
  3611. *
  3612. * Return: QDF_STATUS_SUCCESS: success
  3613. * QDF_STATUS_E_RESOURCES: Error return
  3614. */
  3615. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3616. {
  3617. uint8_t i;
  3618. uint8_t num_pool;
  3619. uint32_t num_desc;
  3620. uint32_t num_ext_desc;
  3621. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3622. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3623. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3624. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3625. if (num_pool > MAX_TXDESC_POOLS)
  3626. goto fail;
  3627. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3628. goto fail;
  3629. dp_tx_flow_control_init(soc);
  3630. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3631. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3632. __func__, num_pool, num_desc);
  3633. /* Allocate extension tx descriptor pools */
  3634. for (i = 0; i < num_pool; i++) {
  3635. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3636. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3637. "MSDU Ext Desc Pool alloc %d failed %pK",
  3638. i, soc);
  3639. goto fail;
  3640. }
  3641. }
  3642. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3643. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3644. __func__, num_pool, num_ext_desc);
  3645. status = dp_tso_attach_wifi3((void *)soc);
  3646. if (status != QDF_STATUS_SUCCESS)
  3647. goto fail;
  3648. /* Initialize descriptors in TCL Rings */
  3649. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3650. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3651. hal_tx_init_data_ring(soc->hal_soc,
  3652. soc->tcl_data_ring[i].hal_srng);
  3653. }
  3654. }
  3655. /*
  3656. * todo - Add a runtime config option to enable this.
  3657. */
  3658. /*
  3659. * Due to multiple issues on NPR EMU, enable it selectively
  3660. * only for NPR EMU, should be removed, once NPR platforms
  3661. * are stable.
  3662. */
  3663. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3664. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3665. "%s HAL Tx init Success", __func__);
  3666. return QDF_STATUS_SUCCESS;
  3667. fail:
  3668. /* Detach will take care of freeing only allocated resources */
  3669. dp_tx_soc_detach(soc);
  3670. return QDF_STATUS_E_RESOURCES;
  3671. }