dp_tx.c 75 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include <wlan_cfg.h>
  27. #ifdef MESH_MODE_SUPPORT
  28. #include "if_meta_hdr.h"
  29. #endif
  30. #ifdef TX_PER_PDEV_DESC_POOL
  31. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  32. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  33. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  34. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  35. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  36. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  37. #else
  38. #ifdef TX_PER_VDEV_DESC_POOL
  39. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  40. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  41. #else
  42. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  43. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  44. #endif /* TX_PER_VDEV_DESC_POOL */
  45. #endif /* TX_PER_PDEV_DESC_POOL */
  46. /* TODO Add support in TSO */
  47. #define DP_DESC_NUM_FRAG(x) 0
  48. /* disable TQM_BYPASS */
  49. #define TQM_BYPASS_WAR 0
  50. /**
  51. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  52. * @vdev: DP Virtual device handle
  53. * @nbuf: Buffer pointer
  54. * @queue: queue ids container for nbuf
  55. *
  56. * TX packet queue has 2 instances, software descriptors id and dma ring id
  57. * Based on tx feature and hardware configuration queue id combination could be
  58. * different.
  59. * For example -
  60. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  61. * With no XPS,lock based resource protection, Descriptor pool ids are different
  62. * for each vdev, dma ring id will be same as single pdev id
  63. *
  64. * Return: None
  65. */
  66. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  67. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  68. {
  69. /* get flow id */
  70. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  71. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  72. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  73. "%s, pool_id:%d ring_id: %d\n",
  74. __func__, queue->desc_pool_id, queue->ring_id);
  75. return;
  76. }
  77. #if defined(FEATURE_TSO)
  78. /**
  79. * dp_tx_tso_desc_release() - Release the tso segment
  80. * after unmapping all the fragments
  81. *
  82. * @pdev - physical device handle
  83. * @tx_desc - Tx software descriptor
  84. */
  85. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  86. struct dp_tx_desc_s *tx_desc)
  87. {
  88. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  89. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  90. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  91. "%s %d TSO desc is NULL!",
  92. __func__, __LINE__);
  93. qdf_assert(0);
  94. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  95. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  96. "%s %d TSO common info is NULL!",
  97. __func__, __LINE__);
  98. qdf_assert(0);
  99. } else {
  100. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  101. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  102. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  103. tso_num_desc->num_seg.tso_cmn_num_seg--;
  104. qdf_nbuf_unmap_tso_segment(soc->osdev,
  105. tx_desc->tso_desc, false);
  106. } else {
  107. tso_num_desc->num_seg.tso_cmn_num_seg--;
  108. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  109. qdf_nbuf_unmap_tso_segment(soc->osdev,
  110. tx_desc->tso_desc, true);
  111. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  112. tx_desc->tso_num_desc);
  113. tx_desc->tso_num_desc = NULL;
  114. }
  115. dp_tx_tso_desc_free(soc,
  116. tx_desc->pool_id, tx_desc->tso_desc);
  117. tx_desc->tso_desc = NULL;
  118. }
  119. }
  120. #else
  121. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  122. struct dp_tx_desc_s *tx_desc)
  123. {
  124. return;
  125. }
  126. #endif
  127. /**
  128. * dp_tx_desc_release() - Release Tx Descriptor
  129. * @tx_desc : Tx Descriptor
  130. * @desc_pool_id: Descriptor Pool ID
  131. *
  132. * Deallocate all resources attached to Tx descriptor and free the Tx
  133. * descriptor.
  134. *
  135. * Return:
  136. */
  137. static void
  138. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  139. {
  140. struct dp_pdev *pdev = tx_desc->pdev;
  141. struct dp_soc *soc;
  142. uint8_t comp_status = 0;
  143. qdf_assert(pdev);
  144. soc = pdev->soc;
  145. if (tx_desc->frm_type == dp_tx_frm_tso)
  146. dp_tx_tso_desc_release(soc, tx_desc);
  147. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  148. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  149. qdf_atomic_dec(&pdev->num_tx_outstanding);
  150. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  151. qdf_atomic_dec(&pdev->num_tx_exception);
  152. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  153. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  154. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  155. else
  156. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  157. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  158. "Tx Completion Release desc %d status %d outstanding %d\n",
  159. tx_desc->id, comp_status,
  160. qdf_atomic_read(&pdev->num_tx_outstanding));
  161. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  162. return;
  163. }
  164. /**
  165. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  166. * @vdev: DP vdev Handle
  167. * @nbuf: skb
  168. *
  169. * Prepares and fills HTT metadata in the frame pre-header for special frames
  170. * that should be transmitted using varying transmit parameters.
  171. * There are 2 VDEV modes that currently needs this special metadata -
  172. * 1) Mesh Mode
  173. * 2) DSRC Mode
  174. *
  175. * Return: HTT metadata size
  176. *
  177. */
  178. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  179. uint32_t *meta_data)
  180. {
  181. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  182. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  183. uint8_t htt_desc_size;
  184. /* Size rounded of multiple of 8 bytes */
  185. uint8_t htt_desc_size_aligned;
  186. uint8_t *hdr = NULL;
  187. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  188. /*
  189. * Metadata - HTT MSDU Extension header
  190. */
  191. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  192. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  193. if (vdev->mesh_vdev) {
  194. /* Fill and add HTT metaheader */
  195. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  196. if (hdr == NULL) {
  197. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  198. "Error in filling HTT metadata\n");
  199. return 0;
  200. }
  201. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  202. } else if (vdev->opmode == wlan_op_mode_ocb) {
  203. /* Todo - Add support for DSRC */
  204. }
  205. return htt_desc_size_aligned;
  206. }
  207. /**
  208. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  209. * @tso_seg: TSO segment to process
  210. * @ext_desc: Pointer to MSDU extension descriptor
  211. *
  212. * Return: void
  213. */
  214. #if defined(FEATURE_TSO)
  215. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  216. void *ext_desc)
  217. {
  218. uint8_t num_frag;
  219. uint32_t tso_flags;
  220. /*
  221. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  222. * tcp_flag_mask
  223. *
  224. * Checksum enable flags are set in TCL descriptor and not in Extension
  225. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  226. */
  227. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  228. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  229. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  230. tso_seg->tso_flags.ip_len);
  231. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  232. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  233. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  234. uint32_t lo = 0;
  235. uint32_t hi = 0;
  236. qdf_dmaaddr_to_32s(
  237. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  238. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  239. tso_seg->tso_frags[num_frag].length);
  240. }
  241. return;
  242. }
  243. #else
  244. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  245. void *ext_desc)
  246. {
  247. return;
  248. }
  249. #endif
  250. #if defined(FEATURE_TSO)
  251. /**
  252. * dp_tx_free_tso_seg() - Loop through the tso segments
  253. * allocated and free them
  254. *
  255. * @soc: soc handle
  256. * @free_seg: list of tso segments
  257. * @msdu_info: msdu descriptor
  258. *
  259. * Return - void
  260. */
  261. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  262. struct qdf_tso_seg_elem_t *free_seg,
  263. struct dp_tx_msdu_info_s *msdu_info)
  264. {
  265. struct qdf_tso_seg_elem_t *next_seg;
  266. while (free_seg) {
  267. next_seg = free_seg->next;
  268. dp_tx_tso_desc_free(soc,
  269. msdu_info->tx_queue.desc_pool_id,
  270. free_seg);
  271. free_seg = next_seg;
  272. }
  273. }
  274. /**
  275. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  276. * allocated and free them
  277. *
  278. * @soc: soc handle
  279. * @free_seg: list of tso segments
  280. * @msdu_info: msdu descriptor
  281. * Return - void
  282. */
  283. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  284. struct qdf_tso_num_seg_elem_t *free_seg,
  285. struct dp_tx_msdu_info_s *msdu_info)
  286. {
  287. struct qdf_tso_num_seg_elem_t *next_seg;
  288. while (free_seg) {
  289. next_seg = free_seg->next;
  290. dp_tso_num_seg_free(soc,
  291. msdu_info->tx_queue.desc_pool_id,
  292. free_seg);
  293. free_seg = next_seg;
  294. }
  295. }
  296. /**
  297. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  298. * @vdev: virtual device handle
  299. * @msdu: network buffer
  300. * @msdu_info: meta data associated with the msdu
  301. *
  302. * Return: QDF_STATUS_SUCCESS success
  303. */
  304. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  305. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  306. {
  307. struct qdf_tso_seg_elem_t *tso_seg;
  308. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  309. struct dp_soc *soc = vdev->pdev->soc;
  310. struct qdf_tso_info_t *tso_info;
  311. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  312. tso_info = &msdu_info->u.tso_info;
  313. tso_info->curr_seg = NULL;
  314. tso_info->tso_seg_list = NULL;
  315. tso_info->num_segs = num_seg;
  316. msdu_info->frm_type = dp_tx_frm_tso;
  317. tso_info->tso_num_seg_list = NULL;
  318. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  319. while (num_seg) {
  320. tso_seg = dp_tx_tso_desc_alloc(
  321. soc, msdu_info->tx_queue.desc_pool_id);
  322. if (tso_seg) {
  323. tso_seg->next = tso_info->tso_seg_list;
  324. tso_info->tso_seg_list = tso_seg;
  325. num_seg--;
  326. } else {
  327. struct qdf_tso_seg_elem_t *free_seg =
  328. tso_info->tso_seg_list;
  329. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  330. return QDF_STATUS_E_NOMEM;
  331. }
  332. }
  333. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  334. tso_num_seg = dp_tso_num_seg_alloc(soc,
  335. msdu_info->tx_queue.desc_pool_id);
  336. if (tso_num_seg) {
  337. tso_num_seg->next = tso_info->tso_num_seg_list;
  338. tso_info->tso_num_seg_list = tso_num_seg;
  339. } else {
  340. /* Bug: free tso_num_seg and tso_seg */
  341. /* Free the already allocated num of segments */
  342. struct qdf_tso_seg_elem_t *free_seg =
  343. tso_info->tso_seg_list;
  344. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  345. __func__);
  346. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  347. return QDF_STATUS_E_NOMEM;
  348. }
  349. msdu_info->num_seg =
  350. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  351. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  352. msdu_info->num_seg);
  353. if (!(msdu_info->num_seg)) {
  354. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  355. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  356. msdu_info);
  357. return QDF_STATUS_E_INVAL;
  358. }
  359. tso_info->curr_seg = tso_info->tso_seg_list;
  360. return QDF_STATUS_SUCCESS;
  361. }
  362. #else
  363. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  364. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  365. {
  366. return QDF_STATUS_E_NOMEM;
  367. }
  368. #endif
  369. /**
  370. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  371. * @vdev: DP Vdev handle
  372. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  373. * @desc_pool_id: Descriptor Pool ID
  374. *
  375. * Return:
  376. */
  377. static
  378. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  379. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  380. {
  381. uint8_t i;
  382. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  383. struct dp_tx_seg_info_s *seg_info;
  384. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  385. struct dp_soc *soc = vdev->pdev->soc;
  386. /* Allocate an extension descriptor */
  387. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  388. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  389. if (!msdu_ext_desc) {
  390. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  391. return NULL;
  392. }
  393. if (qdf_unlikely(vdev->mesh_vdev)) {
  394. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  395. &msdu_info->meta_data[0],
  396. sizeof(struct htt_tx_msdu_desc_ext2_t));
  397. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  398. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  399. }
  400. switch (msdu_info->frm_type) {
  401. case dp_tx_frm_sg:
  402. case dp_tx_frm_me:
  403. case dp_tx_frm_raw:
  404. seg_info = msdu_info->u.sg_info.curr_seg;
  405. /* Update the buffer pointers in MSDU Extension Descriptor */
  406. for (i = 0; i < seg_info->frag_cnt; i++) {
  407. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  408. seg_info->frags[i].paddr_lo,
  409. seg_info->frags[i].paddr_hi,
  410. seg_info->frags[i].len);
  411. }
  412. break;
  413. case dp_tx_frm_tso:
  414. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  415. &cached_ext_desc[0]);
  416. break;
  417. default:
  418. break;
  419. }
  420. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  421. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  422. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  423. msdu_ext_desc->vaddr);
  424. return msdu_ext_desc;
  425. }
  426. /**
  427. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  428. * @vdev: DP vdev handle
  429. * @nbuf: skb
  430. * @desc_pool_id: Descriptor pool ID
  431. * Allocate and prepare Tx descriptor with msdu information.
  432. *
  433. * Return: Pointer to Tx Descriptor on success,
  434. * NULL on failure
  435. */
  436. static
  437. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  438. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  439. uint32_t *meta_data)
  440. {
  441. uint8_t align_pad;
  442. uint8_t is_exception = 0;
  443. uint8_t htt_hdr_size;
  444. struct ether_header *eh;
  445. struct dp_tx_desc_s *tx_desc;
  446. struct dp_pdev *pdev = vdev->pdev;
  447. struct dp_soc *soc = pdev->soc;
  448. /* Allocate software Tx descriptor */
  449. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  450. if (qdf_unlikely(!tx_desc)) {
  451. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  452. "%s Tx Desc Alloc Failed\n", __func__);
  453. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  454. return NULL;
  455. }
  456. /* Flow control/Congestion Control counters */
  457. qdf_atomic_inc(&pdev->num_tx_outstanding);
  458. /* Initialize the SW tx descriptor */
  459. tx_desc->nbuf = nbuf;
  460. tx_desc->frm_type = dp_tx_frm_std;
  461. tx_desc->tx_encap_type = vdev->tx_encap_type;
  462. tx_desc->vdev = vdev;
  463. tx_desc->pdev = pdev;
  464. tx_desc->msdu_ext_desc = NULL;
  465. /**
  466. * For non-scatter regular frames, buffer pointer is directly
  467. * programmed in TCL input descriptor instead of using an MSDU
  468. * extension descriptor.For this cass, HW requirement is that
  469. * descriptor should always point to a 8-byte aligned address.
  470. *
  471. * So we add alignment pad to start of buffer, and specify the actual
  472. * start of data through pkt_offset
  473. */
  474. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  475. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  476. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  477. "qdf_nbuf_push_head failed\n");
  478. goto failure;
  479. }
  480. tx_desc->pkt_offset = align_pad;
  481. /*
  482. * For special modes (vdev_type == ocb or mesh), data frames should be
  483. * transmitted using varying transmit parameters (tx spec) which include
  484. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  485. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  486. * These frames are sent as exception packets to firmware.
  487. *
  488. * HTT Metadata should be ensured to be multiple of 8-bytes,
  489. * to get 8-byte aligned start address along with align_pad added above
  490. *
  491. * |-----------------------------|
  492. * | |
  493. * |-----------------------------| <-----Buffer Pointer Address given
  494. * | | ^ in HW descriptor (aligned)
  495. * | HTT Metadata | |
  496. * | | |
  497. * | | | Packet Offset given in descriptor
  498. * | | |
  499. * |-----------------------------| |
  500. * | Alignment Pad | v
  501. * |-----------------------------| <----- Actual buffer start address
  502. * | SKB Data | (Unaligned)
  503. * | |
  504. * | |
  505. * | |
  506. * | |
  507. * | |
  508. * |-----------------------------|
  509. */
  510. if (qdf_unlikely(vdev->mesh_vdev ||
  511. (vdev->opmode == wlan_op_mode_ocb))) {
  512. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  513. meta_data);
  514. if (htt_hdr_size == 0)
  515. goto failure;
  516. tx_desc->pkt_offset += htt_hdr_size;
  517. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  518. is_exception = 1;
  519. }
  520. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  521. qdf_nbuf_map(soc->osdev, nbuf,
  522. QDF_DMA_TO_DEVICE))) {
  523. /* Handle failure */
  524. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  525. "qdf_nbuf_map failed\n");
  526. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  527. goto failure;
  528. }
  529. if (qdf_unlikely(vdev->nawds_enabled)) {
  530. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  531. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  532. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  533. is_exception = 1;
  534. }
  535. }
  536. #if !TQM_BYPASS_WAR
  537. if (is_exception)
  538. #endif
  539. {
  540. /* Temporary WAR due to TQM VP issues */
  541. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  542. qdf_atomic_inc(&pdev->num_tx_exception);
  543. }
  544. return tx_desc;
  545. failure:
  546. dp_tx_desc_release(tx_desc, desc_pool_id);
  547. return NULL;
  548. }
  549. /**
  550. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  551. * @vdev: DP vdev handle
  552. * @nbuf: skb
  553. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  554. * @desc_pool_id : Descriptor Pool ID
  555. *
  556. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  557. * information. For frames wth fragments, allocate and prepare
  558. * an MSDU extension descriptor
  559. *
  560. * Return: Pointer to Tx Descriptor on success,
  561. * NULL on failure
  562. */
  563. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  564. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  565. uint8_t desc_pool_id)
  566. {
  567. struct dp_tx_desc_s *tx_desc;
  568. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  569. struct dp_pdev *pdev = vdev->pdev;
  570. struct dp_soc *soc = pdev->soc;
  571. /* Allocate software Tx descriptor */
  572. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  573. if (!tx_desc) {
  574. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  575. return NULL;
  576. }
  577. /* Flow control/Congestion Control counters */
  578. qdf_atomic_inc(&pdev->num_tx_outstanding);
  579. /* Initialize the SW tx descriptor */
  580. tx_desc->nbuf = nbuf;
  581. tx_desc->frm_type = msdu_info->frm_type;
  582. tx_desc->tx_encap_type = vdev->tx_encap_type;
  583. tx_desc->vdev = vdev;
  584. tx_desc->pdev = pdev;
  585. tx_desc->pkt_offset = 0;
  586. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  587. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  588. /* Handle scattered frames - TSO/SG/ME */
  589. /* Allocate and prepare an extension descriptor for scattered frames */
  590. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  591. if (!msdu_ext_desc) {
  592. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  593. "%s Tx Extension Descriptor Alloc Fail\n",
  594. __func__);
  595. goto failure;
  596. }
  597. #if TQM_BYPASS_WAR
  598. /* Temporary WAR due to TQM VP issues */
  599. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  600. qdf_atomic_inc(&pdev->num_tx_exception);
  601. #endif
  602. if (qdf_unlikely(vdev->mesh_vdev))
  603. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  604. tx_desc->msdu_ext_desc = msdu_ext_desc;
  605. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  606. return tx_desc;
  607. failure:
  608. dp_tx_desc_release(tx_desc, desc_pool_id);
  609. return NULL;
  610. }
  611. /**
  612. * dp_tx_prepare_raw() - Prepare RAW packet TX
  613. * @vdev: DP vdev handle
  614. * @nbuf: buffer pointer
  615. * @seg_info: Pointer to Segment info Descriptor to be prepared
  616. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  617. * descriptor
  618. *
  619. * Return:
  620. */
  621. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  622. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  623. {
  624. qdf_nbuf_t curr_nbuf = NULL;
  625. uint16_t total_len = 0;
  626. int32_t i;
  627. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  628. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  629. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  630. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  631. if ((qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  632. && (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU)) {
  633. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  634. }
  635. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  636. QDF_DMA_TO_DEVICE)) {
  637. qdf_print("dma map error\n");
  638. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  639. qdf_nbuf_free(nbuf);
  640. return NULL;
  641. }
  642. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  643. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  644. seg_info->frags[i].paddr_lo =
  645. qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  646. seg_info->frags[i].paddr_hi = 0x0;
  647. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  648. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  649. total_len += qdf_nbuf_len(curr_nbuf);
  650. }
  651. seg_info->frag_cnt = i;
  652. seg_info->total_len = total_len;
  653. seg_info->next = NULL;
  654. sg_info->curr_seg = seg_info;
  655. msdu_info->frm_type = dp_tx_frm_raw;
  656. msdu_info->num_seg = 1;
  657. return nbuf;
  658. }
  659. /**
  660. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  661. * @soc: DP Soc Handle
  662. * @vdev: DP vdev handle
  663. * @tx_desc: Tx Descriptor Handle
  664. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  665. * @fw_metadata: Metadata to send to Target Firmware along with frame
  666. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  667. *
  668. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  669. * from software Tx descriptor
  670. *
  671. * Return:
  672. */
  673. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  674. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  675. uint16_t fw_metadata, uint8_t ring_id)
  676. {
  677. uint8_t type;
  678. uint16_t length;
  679. void *hal_tx_desc, *hal_tx_desc_cached;
  680. qdf_dma_addr_t dma_addr;
  681. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  682. /* Return Buffer Manager ID */
  683. uint8_t bm_id = ring_id;
  684. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  685. hal_tx_desc_cached = (void *) cached_desc;
  686. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  687. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  688. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  689. type = HAL_TX_BUF_TYPE_EXT_DESC;
  690. dma_addr = tx_desc->msdu_ext_desc->paddr;
  691. } else {
  692. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  693. type = HAL_TX_BUF_TYPE_BUFFER;
  694. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  695. }
  696. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  697. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  698. dma_addr , bm_id, tx_desc->id, type);
  699. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  700. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  701. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  702. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  703. vdev->dscp_tid_map_id);
  704. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  705. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u\n",
  706. __func__, length, type, (uint64_t)dma_addr,
  707. tx_desc->pkt_offset, tx_desc->id);
  708. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  709. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  710. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  711. vdev->hal_desc_addr_search_flags);
  712. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  713. || qdf_nbuf_is_tso(tx_desc->nbuf)) {
  714. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  715. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  716. }
  717. if (tid != HTT_TX_EXT_TID_INVALID)
  718. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  719. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  720. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  721. /* Sync cached descriptor with HW */
  722. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  723. if (!hal_tx_desc) {
  724. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  725. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  726. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  727. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  728. return QDF_STATUS_E_RESOURCES;
  729. }
  730. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  731. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  732. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  733. /*
  734. * If one packet is enqueued in HW, PM usage count needs to be
  735. * incremented by one to prevent future runtime suspend. This
  736. * should be tied with the success of enqueuing. It will be
  737. * decremented after the packet has been sent.
  738. */
  739. hif_pm_runtime_get_noresume(soc->hif_handle);
  740. return QDF_STATUS_SUCCESS;
  741. }
  742. /**
  743. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  744. * @vdev: DP vdev handle
  745. * @nbuf: skb
  746. *
  747. * Extract the DSCP or PCP information from frame and map into TID value.
  748. * Software based TID classification is required when more than 2 DSCP-TID
  749. * mapping tables are needed.
  750. * Hardware supports 2 DSCP-TID mapping tables
  751. *
  752. * Return: void
  753. */
  754. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  755. struct dp_tx_msdu_info_s *msdu_info)
  756. {
  757. uint8_t tos = 0, dscp_tid_override = 0;
  758. uint8_t *hdr_ptr, *L3datap;
  759. uint8_t is_mcast = 0;
  760. struct ether_header *eh = NULL;
  761. qdf_ethervlan_header_t *evh = NULL;
  762. uint16_t ether_type;
  763. qdf_llc_t *llcHdr;
  764. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  765. /* for mesh packets don't do any classification */
  766. if (qdf_unlikely(vdev->mesh_vdev))
  767. return;
  768. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  769. eh = (struct ether_header *) nbuf->data;
  770. hdr_ptr = eh->ether_dhost;
  771. L3datap = hdr_ptr + sizeof(struct ether_header);
  772. } else {
  773. qdf_dot3_qosframe_t *qos_wh =
  774. (qdf_dot3_qosframe_t *) nbuf->data;
  775. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  776. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  777. return;
  778. }
  779. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  780. ether_type = eh->ether_type;
  781. /*
  782. * Check if packet is dot3 or eth2 type.
  783. */
  784. if (IS_LLC_PRESENT(ether_type)) {
  785. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  786. sizeof(*llcHdr));
  787. if (ether_type == htons(ETHERTYPE_8021Q)) {
  788. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  789. sizeof(*llcHdr);
  790. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  791. + sizeof(*llcHdr) +
  792. sizeof(qdf_net_vlanhdr_t));
  793. } else {
  794. L3datap = hdr_ptr + sizeof(struct ether_header) +
  795. sizeof(*llcHdr);
  796. }
  797. } else {
  798. if (ether_type == htons(ETHERTYPE_8021Q)) {
  799. evh = (qdf_ethervlan_header_t *) eh;
  800. ether_type = evh->ether_type;
  801. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  802. }
  803. }
  804. /*
  805. * Find priority from IP TOS DSCP field
  806. */
  807. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  808. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  809. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  810. /* Only for unicast frames */
  811. if (!is_mcast) {
  812. /* send it on VO queue */
  813. msdu_info->tid = DP_VO_TID;
  814. }
  815. } else {
  816. /*
  817. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  818. * from TOS byte.
  819. */
  820. tos = ip->ip_tos;
  821. dscp_tid_override = 1;
  822. }
  823. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  824. /* TODO
  825. * use flowlabel
  826. *igmpmld cases to be handled in phase 2
  827. */
  828. unsigned long ver_pri_flowlabel;
  829. unsigned long pri;
  830. ver_pri_flowlabel = *(unsigned long *) L3datap;
  831. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  832. DP_IPV6_PRIORITY_SHIFT;
  833. tos = pri;
  834. dscp_tid_override = 1;
  835. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  836. msdu_info->tid = DP_VO_TID;
  837. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  838. /* Only for unicast frames */
  839. if (!is_mcast) {
  840. /* send ucast arp on VO queue */
  841. msdu_info->tid = DP_VO_TID;
  842. }
  843. }
  844. /*
  845. * Assign all MCAST packets to BE
  846. */
  847. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  848. if (is_mcast) {
  849. tos = 0;
  850. dscp_tid_override = 1;
  851. }
  852. }
  853. if (dscp_tid_override == 1) {
  854. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  855. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  856. }
  857. return;
  858. }
  859. /**
  860. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  861. * @vdev: DP vdev handle
  862. * @nbuf: skb
  863. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  864. * @tx_q: Tx queue to be used for this Tx frame
  865. * @peer_id: peer_id of the peer in case of NAWDS frames
  866. *
  867. * Return: NULL on success,
  868. * nbuf when it fails to send
  869. */
  870. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  871. uint8_t tid, struct dp_tx_queue *tx_q,
  872. uint32_t *meta_data, uint16_t peer_id)
  873. {
  874. struct dp_pdev *pdev = vdev->pdev;
  875. struct dp_soc *soc = pdev->soc;
  876. struct dp_tx_desc_s *tx_desc;
  877. QDF_STATUS status;
  878. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  879. uint16_t htt_tcl_metadata = 0;
  880. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 0);
  881. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  882. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id, meta_data);
  883. if (!tx_desc) {
  884. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  885. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  886. __func__, vdev, tx_q->desc_pool_id);
  887. return nbuf;
  888. }
  889. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  890. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  891. "%s %d : HAL RING Access Failed -- %pK\n",
  892. __func__, __LINE__, hal_srng);
  893. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  894. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  895. goto fail_return;
  896. }
  897. if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  898. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  899. HTT_TCL_METADATA_TYPE_PEER_BASED);
  900. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  901. peer_id);
  902. } else
  903. htt_tcl_metadata = vdev->htt_tcl_metadata;
  904. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  905. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  906. htt_tcl_metadata, tx_q->ring_id);
  907. if (status != QDF_STATUS_SUCCESS) {
  908. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  909. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  910. __func__, tx_desc, tx_q->ring_id);
  911. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  912. goto fail_return;
  913. }
  914. nbuf = NULL;
  915. fail_return:
  916. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  917. hal_srng_access_end(soc->hal_soc, hal_srng);
  918. hif_pm_runtime_put(soc->hif_handle);
  919. } else {
  920. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  921. }
  922. return nbuf;
  923. }
  924. /**
  925. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  926. * @vdev: DP vdev handle
  927. * @nbuf: skb
  928. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  929. *
  930. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  931. *
  932. * Return: NULL on success,
  933. * nbuf when it fails to send
  934. */
  935. #if QDF_LOCK_STATS
  936. static noinline
  937. #else
  938. static
  939. #endif
  940. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  941. struct dp_tx_msdu_info_s *msdu_info)
  942. {
  943. uint8_t i;
  944. struct dp_pdev *pdev = vdev->pdev;
  945. struct dp_soc *soc = pdev->soc;
  946. struct dp_tx_desc_s *tx_desc;
  947. QDF_STATUS status;
  948. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  949. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  950. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  951. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  952. "%s %d : HAL RING Access Failed -- %pK\n",
  953. __func__, __LINE__, hal_srng);
  954. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  955. return nbuf;
  956. }
  957. if (msdu_info->frm_type == dp_tx_frm_me)
  958. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  959. i = 0;
  960. /* Print statement to track i and num_seg */
  961. /*
  962. * For each segment (maps to 1 MSDU) , prepare software and hardware
  963. * descriptors using information in msdu_info
  964. */
  965. while (i < msdu_info->num_seg) {
  966. /*
  967. * Setup Tx descriptor for an MSDU, and MSDU extension
  968. * descriptor
  969. */
  970. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  971. tx_q->desc_pool_id);
  972. if (!tx_desc) {
  973. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  974. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  975. __func__, vdev, tx_q->desc_pool_id);
  976. if (msdu_info->frm_type == dp_tx_frm_me) {
  977. dp_tx_me_free_buf(pdev,
  978. (void *)(msdu_info->u.sg_info
  979. .curr_seg->frags[0].vaddr));
  980. }
  981. goto done;
  982. }
  983. if (msdu_info->frm_type == dp_tx_frm_me) {
  984. tx_desc->me_buffer =
  985. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  986. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  987. }
  988. /*
  989. * Enqueue the Tx MSDU descriptor to HW for transmit
  990. */
  991. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  992. vdev->htt_tcl_metadata, tx_q->ring_id);
  993. if (status != QDF_STATUS_SUCCESS) {
  994. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  995. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  996. __func__, tx_desc, tx_q->ring_id);
  997. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  998. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  999. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1000. goto done;
  1001. }
  1002. /*
  1003. * TODO
  1004. * if tso_info structure can be modified to have curr_seg
  1005. * as first element, following 2 blocks of code (for TSO and SG)
  1006. * can be combined into 1
  1007. */
  1008. /*
  1009. * For frames with multiple segments (TSO, ME), jump to next
  1010. * segment.
  1011. */
  1012. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1013. if (msdu_info->u.tso_info.curr_seg->next) {
  1014. msdu_info->u.tso_info.curr_seg =
  1015. msdu_info->u.tso_info.curr_seg->next;
  1016. /*
  1017. * If this is a jumbo nbuf, then increment the number of
  1018. * nbuf users for each additional segment of the msdu.
  1019. * This will ensure that the skb is freed only after
  1020. * receiving tx completion for all segments of an nbuf
  1021. */
  1022. qdf_nbuf_inc_users(nbuf);
  1023. /* Check with MCL if this is needed */
  1024. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1025. }
  1026. }
  1027. /*
  1028. * For Multicast-Unicast converted packets,
  1029. * each converted frame (for a client) is represented as
  1030. * 1 segment
  1031. */
  1032. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1033. (msdu_info->frm_type == dp_tx_frm_me)) {
  1034. if (msdu_info->u.sg_info.curr_seg->next) {
  1035. msdu_info->u.sg_info.curr_seg =
  1036. msdu_info->u.sg_info.curr_seg->next;
  1037. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1038. }
  1039. }
  1040. i++;
  1041. }
  1042. nbuf = NULL;
  1043. done:
  1044. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1045. hal_srng_access_end(soc->hal_soc, hal_srng);
  1046. hif_pm_runtime_put(soc->hif_handle);
  1047. } else {
  1048. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1049. }
  1050. return nbuf;
  1051. }
  1052. /**
  1053. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1054. * for SG frames
  1055. * @vdev: DP vdev handle
  1056. * @nbuf: skb
  1057. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1058. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1059. *
  1060. * Return: NULL on success,
  1061. * nbuf when it fails to send
  1062. */
  1063. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1064. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1065. {
  1066. uint32_t cur_frag, nr_frags;
  1067. qdf_dma_addr_t paddr;
  1068. struct dp_tx_sg_info_s *sg_info;
  1069. sg_info = &msdu_info->u.sg_info;
  1070. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1071. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1072. QDF_DMA_TO_DEVICE)) {
  1073. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1074. "dma map error\n");
  1075. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1076. qdf_nbuf_free(nbuf);
  1077. return NULL;
  1078. }
  1079. seg_info->frags[0].paddr_lo = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1080. seg_info->frags[0].paddr_hi = 0;
  1081. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1082. seg_info->frags[0].vaddr = (void *) nbuf;
  1083. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1084. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1085. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1086. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1087. "frag dma map error\n");
  1088. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1089. qdf_nbuf_free(nbuf);
  1090. return NULL;
  1091. }
  1092. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1093. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1094. seg_info->frags[cur_frag + 1].paddr_hi =
  1095. ((uint64_t) paddr) >> 32;
  1096. seg_info->frags[cur_frag + 1].len =
  1097. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1098. }
  1099. seg_info->frag_cnt = (cur_frag + 1);
  1100. seg_info->total_len = qdf_nbuf_len(nbuf);
  1101. seg_info->next = NULL;
  1102. sg_info->curr_seg = seg_info;
  1103. msdu_info->frm_type = dp_tx_frm_sg;
  1104. msdu_info->num_seg = 1;
  1105. return nbuf;
  1106. }
  1107. #ifdef MESH_MODE_SUPPORT
  1108. /**
  1109. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1110. and prepare msdu_info for mesh frames.
  1111. * @vdev: DP vdev handle
  1112. * @nbuf: skb
  1113. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1114. *
  1115. * Return: NULL on failure,
  1116. * nbuf when extracted successfully
  1117. */
  1118. static
  1119. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1120. struct dp_tx_msdu_info_s *msdu_info)
  1121. {
  1122. struct meta_hdr_s *mhdr;
  1123. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1124. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1125. nbuf = qdf_nbuf_unshare(nbuf);
  1126. if (nbuf == NULL) {
  1127. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1128. "qdf_nbuf_unshare failed\n");
  1129. return nbuf;
  1130. }
  1131. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1132. qdf_mem_set(meta_data, 0, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1133. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1134. meta_data->power = mhdr->power;
  1135. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1136. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1137. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1138. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1139. meta_data->dyn_bw = 1;
  1140. meta_data->valid_pwr = 1;
  1141. meta_data->valid_mcs_mask = 1;
  1142. meta_data->valid_nss_mask = 1;
  1143. meta_data->valid_preamble_type = 1;
  1144. meta_data->valid_retries = 1;
  1145. meta_data->valid_bw_info = 1;
  1146. }
  1147. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1148. meta_data->encrypt_type = 0;
  1149. meta_data->valid_encrypt_type = 1;
  1150. }
  1151. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1152. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1153. else
  1154. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1155. meta_data->valid_key_flags = 1;
  1156. meta_data->key_flags = (mhdr->keyix & 0x3);
  1157. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1158. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1159. "qdf_nbuf_pull_head failed\n");
  1160. qdf_nbuf_free(nbuf);
  1161. return NULL;
  1162. }
  1163. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1164. "%s , Meta hdr %0x %0x %0x %0x %0x\n",
  1165. __func__, msdu_info->meta_data[0],
  1166. msdu_info->meta_data[1],
  1167. msdu_info->meta_data[2],
  1168. msdu_info->meta_data[3],
  1169. msdu_info->meta_data[4]);
  1170. return nbuf;
  1171. }
  1172. #else
  1173. static
  1174. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1175. struct dp_tx_msdu_info_s *msdu_info)
  1176. {
  1177. return nbuf;
  1178. }
  1179. #endif
  1180. /**
  1181. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1182. * @vdev: dp_vdev handle
  1183. * @nbuf: skb
  1184. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1185. * @tx_q: Tx queue to be used for this Tx frame
  1186. * @meta_data: Meta date for mesh
  1187. * @peer_id: peer_id of the peer in case of NAWDS frames
  1188. *
  1189. * return: NULL on success nbuf on failure
  1190. */
  1191. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1192. uint8_t tid, struct dp_tx_queue *tx_q, uint32_t *meta_data,
  1193. uint32_t peer_id)
  1194. {
  1195. struct dp_peer *peer = NULL;
  1196. qdf_nbuf_t nbuf_copy;
  1197. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1198. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1199. (peer->nawds_enabled || peer->bss_peer)) {
  1200. nbuf_copy = qdf_nbuf_copy(nbuf);
  1201. if (!nbuf_copy) {
  1202. QDF_TRACE(QDF_MODULE_ID_DP,
  1203. QDF_TRACE_LEVEL_ERROR,
  1204. "nbuf copy failed");
  1205. }
  1206. peer_id = peer->peer_ids[0];
  1207. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy, tid,
  1208. tx_q, meta_data, peer_id);
  1209. if (nbuf_copy != NULL) {
  1210. qdf_nbuf_free(nbuf);
  1211. return nbuf_copy;
  1212. }
  1213. }
  1214. }
  1215. if (peer_id == HTT_INVALID_PEER)
  1216. return nbuf;
  1217. qdf_nbuf_free(nbuf);
  1218. return NULL;
  1219. }
  1220. /**
  1221. * dp_tx_send() - Transmit a frame on a given VAP
  1222. * @vap_dev: DP vdev handle
  1223. * @nbuf: skb
  1224. *
  1225. * Entry point for Core Tx layer (DP_TX) invoked from
  1226. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1227. * cases
  1228. *
  1229. * Return: NULL on success,
  1230. * nbuf when it fails to send
  1231. */
  1232. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1233. {
  1234. struct ether_header *eh = NULL;
  1235. struct dp_tx_msdu_info_s msdu_info;
  1236. struct dp_tx_seg_info_s seg_info;
  1237. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1238. uint16_t peer_id = HTT_INVALID_PEER;
  1239. qdf_nbuf_t nbuf_mesh = NULL;
  1240. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1241. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1242. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1243. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1244. "%s , skb %0x:%0x:%0x:%0x:%0x:%0x\n",
  1245. __func__, nbuf->data[0], nbuf->data[1], nbuf->data[2],
  1246. nbuf->data[3], nbuf->data[4], nbuf->data[5]);
  1247. /*
  1248. * Set Default Host TID value to invalid TID
  1249. * (TID override disabled)
  1250. */
  1251. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1252. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1253. if (qdf_unlikely(vdev->mesh_vdev)) {
  1254. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1255. &msdu_info);
  1256. if (nbuf_mesh == NULL) {
  1257. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1258. "Extracting mesh metadata failed\n");
  1259. return nbuf;
  1260. }
  1261. nbuf = nbuf_mesh;
  1262. }
  1263. /*
  1264. * Get HW Queue to use for this frame.
  1265. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1266. * dedicated for data and 1 for command.
  1267. * "queue_id" maps to one hardware ring.
  1268. * With each ring, we also associate a unique Tx descriptor pool
  1269. * to minimize lock contention for these resources.
  1270. */
  1271. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1272. /*
  1273. * TCL H/W supports 2 DSCP-TID mapping tables.
  1274. * Table 1 - Default DSCP-TID mapping table
  1275. * Table 2 - 1 DSCP-TID override table
  1276. *
  1277. * If we need a different DSCP-TID mapping for this vap,
  1278. * call tid_classify to extract DSCP/ToS from frame and
  1279. * map to a TID and store in msdu_info. This is later used
  1280. * to fill in TCL Input descriptor (per-packet TID override).
  1281. */
  1282. if (vdev->dscp_tid_map_id > 1)
  1283. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1284. /* Reset the control block */
  1285. qdf_nbuf_reset_ctxt(nbuf);
  1286. /*
  1287. * Classify the frame and call corresponding
  1288. * "prepare" function which extracts the segment (TSO)
  1289. * and fragmentation information (for TSO , SG, ME, or Raw)
  1290. * into MSDU_INFO structure which is later used to fill
  1291. * SW and HW descriptors.
  1292. */
  1293. if (qdf_nbuf_is_tso(nbuf)) {
  1294. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1295. "%s TSO frame %pK\n", __func__, vdev);
  1296. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1297. qdf_nbuf_len(nbuf));
  1298. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1299. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1300. "%s tso_prepare fail vdev_id:%d\n",
  1301. __func__, vdev->vdev_id);
  1302. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1303. return nbuf;
  1304. }
  1305. goto send_multiple;
  1306. }
  1307. /* SG */
  1308. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1309. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1310. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1311. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1312. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1313. qdf_nbuf_len(nbuf));
  1314. goto send_multiple;
  1315. }
  1316. #ifdef ATH_SUPPORT_IQUE
  1317. /* Mcast to Ucast Conversion*/
  1318. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1319. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1320. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1321. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1322. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1323. DP_STATS_INC_PKT(vdev,
  1324. tx_i.mcast_en.mcast_pkt, 1,
  1325. qdf_nbuf_len(nbuf));
  1326. if (dp_tx_prepare_send_me(vdev, nbuf)) {
  1327. qdf_nbuf_free(nbuf);
  1328. return NULL;
  1329. }
  1330. return nbuf;
  1331. }
  1332. }
  1333. #endif
  1334. /* RAW */
  1335. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1336. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1337. if (nbuf == NULL)
  1338. return NULL;
  1339. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1340. "%s Raw frame %pK\n", __func__, vdev);
  1341. goto send_multiple;
  1342. }
  1343. if (vdev->nawds_enabled) {
  1344. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1345. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1346. nbuf = dp_tx_prepare_nawds(vdev, nbuf, msdu_info.tid,
  1347. &msdu_info.tx_queue,
  1348. msdu_info.meta_data, peer_id);
  1349. return nbuf;
  1350. }
  1351. }
  1352. /* Single linear frame */
  1353. /*
  1354. * If nbuf is a simple linear frame, use send_single function to
  1355. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1356. * SRNG. There is no need to setup a MSDU extension descriptor.
  1357. */
  1358. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info.tid,
  1359. &msdu_info.tx_queue, msdu_info.meta_data, peer_id);
  1360. return nbuf;
  1361. send_multiple:
  1362. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1363. return nbuf;
  1364. }
  1365. /**
  1366. * dp_tx_reinject_handler() - Tx Reinject Handler
  1367. * @tx_desc: software descriptor head pointer
  1368. * @status : Tx completion status from HTT descriptor
  1369. *
  1370. * This function reinjects frames back to Target.
  1371. * Todo - Host queue needs to be added
  1372. *
  1373. * Return: none
  1374. */
  1375. static
  1376. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1377. {
  1378. struct dp_vdev *vdev;
  1379. struct dp_peer *peer = NULL;
  1380. uint32_t peer_id = HTT_INVALID_PEER;
  1381. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1382. qdf_nbuf_t nbuf_copy = NULL;
  1383. struct dp_tx_msdu_info_s msdu_info;
  1384. vdev = tx_desc->vdev;
  1385. qdf_assert(vdev);
  1386. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1387. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1388. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1389. "%s Tx reinject path\n", __func__);
  1390. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1391. qdf_nbuf_len(tx_desc->nbuf));
  1392. if (!vdev->osif_proxy_arp) {
  1393. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1394. "function pointer to proxy arp not present\n");
  1395. return;
  1396. }
  1397. if (qdf_unlikely(vdev->mesh_vdev)) {
  1398. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1399. } else {
  1400. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1401. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1402. (peer->bss_peer || peer->nawds_enabled)
  1403. && !(vdev->osif_proxy_arp(
  1404. vdev->osif_vdev,
  1405. nbuf))) {
  1406. nbuf_copy = qdf_nbuf_copy(nbuf);
  1407. if (!nbuf_copy) {
  1408. QDF_TRACE(QDF_MODULE_ID_DP,
  1409. QDF_TRACE_LEVEL_ERROR,
  1410. FL("nbuf copy failed"));
  1411. break;
  1412. }
  1413. if (peer->nawds_enabled)
  1414. peer_id = peer->peer_ids[0];
  1415. else
  1416. peer_id = HTT_INVALID_PEER;
  1417. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1418. nbuf_copy, msdu_info.tid,
  1419. &msdu_info.tx_queue,
  1420. msdu_info.meta_data, peer_id);
  1421. if (nbuf_copy) {
  1422. QDF_TRACE(QDF_MODULE_ID_DP,
  1423. QDF_TRACE_LEVEL_ERROR,
  1424. FL("pkt send failed"));
  1425. qdf_nbuf_free(nbuf_copy);
  1426. }
  1427. }
  1428. }
  1429. }
  1430. qdf_nbuf_free(nbuf);
  1431. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1432. }
  1433. /**
  1434. * dp_tx_inspect_handler() - Tx Inspect Handler
  1435. * @tx_desc: software descriptor head pointer
  1436. * @status : Tx completion status from HTT descriptor
  1437. *
  1438. * Handles Tx frames sent back to Host for inspection
  1439. * (ProxyARP)
  1440. *
  1441. * Return: none
  1442. */
  1443. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1444. {
  1445. struct dp_soc *soc;
  1446. struct dp_pdev *pdev = tx_desc->pdev;
  1447. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1448. "%s Tx inspect path\n",
  1449. __func__);
  1450. qdf_assert(pdev);
  1451. soc = pdev->soc;
  1452. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1453. qdf_nbuf_len(tx_desc->nbuf));
  1454. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1455. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1456. }
  1457. /**
  1458. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1459. * @soc: Soc handle
  1460. * @desc: software Tx descriptor to be processed
  1461. *
  1462. * Return: none
  1463. */
  1464. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1465. struct dp_tx_desc_s *desc)
  1466. {
  1467. struct dp_vdev *vdev = desc->vdev;
  1468. qdf_nbuf_t nbuf = desc->nbuf;
  1469. /* 0 : MSDU buffer, 1 : MLE */
  1470. if (desc->msdu_ext_desc) {
  1471. /* TSO free */
  1472. if (hal_tx_ext_desc_get_tso_enable(
  1473. desc->msdu_ext_desc->vaddr)) {
  1474. /* If remaining number of segment is 0
  1475. * actual TSO may unmap and free */
  1476. if (!DP_DESC_NUM_FRAG(desc)) {
  1477. qdf_nbuf_unmap(soc->osdev, nbuf,
  1478. QDF_DMA_TO_DEVICE);
  1479. qdf_nbuf_free(nbuf);
  1480. return;
  1481. }
  1482. }
  1483. }
  1484. if (desc->flags & DP_TX_DESC_FLAG_ME)
  1485. dp_tx_me_free_buf(desc->pdev, desc->me_buffer);
  1486. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1487. if (!vdev->mesh_vdev) {
  1488. qdf_nbuf_free(nbuf);
  1489. } else {
  1490. vdev->osif_tx_free_ext((nbuf));
  1491. }
  1492. }
  1493. /**
  1494. * dp_tx_mec_handler() - Tx MEC Notify Handler
  1495. * @vdev: pointer to dp dev handler
  1496. * @status : Tx completion status from HTT descriptor
  1497. *
  1498. * Handles MEC notify event sent from fw to Host
  1499. *
  1500. * Return: none
  1501. */
  1502. #ifdef FEATURE_WDS
  1503. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1504. {
  1505. struct dp_soc *soc;
  1506. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  1507. struct dp_peer *peer;
  1508. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  1509. soc = vdev->pdev->soc;
  1510. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1511. peer = TAILQ_FIRST(&vdev->peer_list);
  1512. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1513. if (!peer) {
  1514. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1515. FL("peer is NULL"));
  1516. return;
  1517. }
  1518. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1519. "%s Tx MEC Handler\n",
  1520. __func__);
  1521. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  1522. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  1523. status[(DP_MAC_ADDR_LEN - 2) + i];
  1524. if (!dp_peer_add_ast(soc, peer, mac_addr, 2)) {
  1525. soc->cdp_soc.ol_ops->peer_add_wds_entry(
  1526. vdev->pdev->osif_pdev,
  1527. mac_addr,
  1528. vdev->mac_addr.raw,
  1529. flags);
  1530. }
  1531. }
  1532. #else
  1533. static void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1534. {
  1535. }
  1536. #endif
  1537. /**
  1538. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  1539. * @tx_desc: software descriptor head pointer
  1540. * @status : Tx completion status from HTT descriptor
  1541. *
  1542. * This function will process HTT Tx indication messages from Target
  1543. *
  1544. * Return: none
  1545. */
  1546. static
  1547. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1548. {
  1549. uint8_t tx_status;
  1550. struct dp_pdev *pdev;
  1551. struct dp_vdev *vdev;
  1552. struct dp_soc *soc;
  1553. uint32_t *htt_status_word = (uint32_t *) status;
  1554. qdf_assert(tx_desc->pdev);
  1555. pdev = tx_desc->pdev;
  1556. vdev = tx_desc->vdev;
  1557. soc = pdev->soc;
  1558. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  1559. switch (tx_status) {
  1560. case HTT_TX_FW2WBM_TX_STATUS_OK:
  1561. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  1562. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  1563. {
  1564. dp_tx_comp_free_buf(soc, tx_desc);
  1565. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1566. break;
  1567. }
  1568. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  1569. {
  1570. dp_tx_reinject_handler(tx_desc, status);
  1571. break;
  1572. }
  1573. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  1574. {
  1575. dp_tx_inspect_handler(tx_desc, status);
  1576. break;
  1577. }
  1578. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  1579. {
  1580. dp_tx_mec_handler(vdev, status);
  1581. break;
  1582. }
  1583. default:
  1584. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1585. "%s Invalid HTT tx_status %d\n",
  1586. __func__, tx_status);
  1587. break;
  1588. }
  1589. }
  1590. #ifdef MESH_MODE_SUPPORT
  1591. /**
  1592. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  1593. * in mesh meta header
  1594. * @tx_desc: software descriptor head pointer
  1595. * @ts: pointer to tx completion stats
  1596. * Return: none
  1597. */
  1598. static
  1599. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1600. struct hal_tx_completion_status *ts)
  1601. {
  1602. struct meta_hdr_s *mhdr;
  1603. qdf_nbuf_t netbuf = tx_desc->nbuf;
  1604. if (!tx_desc->msdu_ext_desc) {
  1605. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  1606. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1607. "netbuf %pK offset %d\n",
  1608. netbuf, tx_desc->pkt_offset);
  1609. return;
  1610. }
  1611. }
  1612. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1613. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1614. "netbuf %pK offset %d\n", netbuf,
  1615. sizeof(struct meta_hdr_s));
  1616. return;
  1617. }
  1618. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  1619. mhdr->rssi = ts->ack_frame_rssi;
  1620. mhdr->channel = tx_desc->pdev->operating_channel;
  1621. }
  1622. #else
  1623. static
  1624. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1625. struct hal_tx_completion_status *ts)
  1626. {
  1627. }
  1628. #endif
  1629. /**
  1630. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  1631. * @peer: Handle to DP peer
  1632. * @ts: pointer to HAL Tx completion stats
  1633. * @length: MSDU length
  1634. *
  1635. * Return: None
  1636. */
  1637. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  1638. struct hal_tx_completion_status *ts, uint32_t length)
  1639. {
  1640. struct dp_pdev *pdev = peer->vdev->pdev;
  1641. struct dp_soc *soc = pdev->soc;
  1642. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  1643. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  1644. return;
  1645. DP_STATS_INCC(peer, tx.tx_failed, 1,
  1646. !(ts->status == HAL_TX_TQM_RR_FRAME_ACKED));
  1647. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  1648. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  1649. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  1650. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  1651. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  1652. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  1653. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  1654. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  1655. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  1656. return;
  1657. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1658. ((ts->mcs >= MAX_MCS_11A) && (ts->pkt_type == DOT11_A)));
  1659. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1660. ((ts->mcs <= MAX_MCS_11A) && (ts->pkt_type == DOT11_A)));
  1661. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1662. ((ts->mcs >= MAX_MCS_11B) && (ts->pkt_type == DOT11_B)));
  1663. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1664. ((ts->mcs <= MAX_MCS_11B) && (ts->pkt_type == DOT11_B)));
  1665. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1666. ((ts->mcs >= MAX_MCS_11A) && (ts->pkt_type == DOT11_N)));
  1667. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1668. ((ts->mcs <= MAX_MCS_11A) && (ts->pkt_type == DOT11_N)));
  1669. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1670. ((ts->mcs >= MAX_MCS_11AC) && (ts->pkt_type == DOT11_AC)));
  1671. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1672. ((ts->mcs <= MAX_MCS_11AC) && (ts->pkt_type == DOT11_AC)));
  1673. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1674. ((ts->mcs >= (MAX_MCS-1)) && (ts->pkt_type == DOT11_AX)));
  1675. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1676. ((ts->mcs <= (MAX_MCS-1)) && (ts->pkt_type == DOT11_AX)));
  1677. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  1678. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  1679. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  1680. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  1681. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  1682. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  1683. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  1684. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  1685. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  1686. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  1687. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  1688. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  1689. &peer->stats, ts->peer_id,
  1690. UPDATE_PEER_STATS);
  1691. }
  1692. }
  1693. /**
  1694. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  1695. * @tx_desc: software descriptor head pointer
  1696. * @length: packet length
  1697. *
  1698. * Return: none
  1699. */
  1700. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  1701. uint32_t length)
  1702. {
  1703. struct hal_tx_completion_status ts;
  1704. struct dp_soc *soc = NULL;
  1705. struct dp_vdev *vdev = tx_desc->vdev;
  1706. struct dp_peer *peer = NULL;
  1707. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1708. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1709. "-------------------- \n"
  1710. "Tx Completion Stats: \n"
  1711. "-------------------- \n"
  1712. "ack_frame_rssi = %d \n"
  1713. "first_msdu = %d \n"
  1714. "last_msdu = %d \n"
  1715. "msdu_part_of_amsdu = %d \n"
  1716. "rate_stats valid = %d \n"
  1717. "bw = %d \n"
  1718. "pkt_type = %d \n"
  1719. "stbc = %d \n"
  1720. "ldpc = %d \n"
  1721. "sgi = %d \n"
  1722. "mcs = %d \n"
  1723. "ofdma = %d \n"
  1724. "tones_in_ru = %d \n"
  1725. "tsf = %d \n"
  1726. "ppdu_id = %d \n"
  1727. "transmit_cnt = %d \n"
  1728. "tid = %d \n"
  1729. "peer_id = %d \n",
  1730. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  1731. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  1732. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  1733. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  1734. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  1735. ts.peer_id);
  1736. if (!vdev) {
  1737. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1738. "invalid vdev");
  1739. goto out;
  1740. }
  1741. soc = vdev->pdev->soc;
  1742. /* Update SoC level stats */
  1743. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  1744. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  1745. /* Update per-packet stats */
  1746. if (qdf_unlikely(vdev->mesh_vdev))
  1747. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  1748. /* Update peer level stats */
  1749. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1750. if (!peer) {
  1751. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1752. "invalid peer");
  1753. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  1754. goto out;
  1755. }
  1756. dp_tx_update_peer_stats(peer, &ts, length);
  1757. out:
  1758. return;
  1759. }
  1760. /**
  1761. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  1762. * @soc: core txrx main context
  1763. * @comp_head: software descriptor head pointer
  1764. *
  1765. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  1766. * and release the software descriptors after processing is complete
  1767. *
  1768. * Return: none
  1769. */
  1770. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  1771. struct dp_tx_desc_s *comp_head)
  1772. {
  1773. struct dp_tx_desc_s *desc;
  1774. struct dp_tx_desc_s *next;
  1775. struct hal_tx_completion_status ts = {0};
  1776. uint32_t length;
  1777. struct dp_peer *peer;
  1778. DP_HIST_INIT();
  1779. desc = comp_head;
  1780. while (desc) {
  1781. hal_tx_comp_get_status(&desc->comp, &ts);
  1782. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1783. length = qdf_nbuf_len(desc->nbuf);
  1784. /* Process Tx status in descriptor */
  1785. if (soc->process_tx_status ||
  1786. (desc->vdev && desc->vdev->mesh_vdev))
  1787. dp_tx_comp_process_tx_status(desc, length);
  1788. dp_tx_comp_free_buf(soc, desc);
  1789. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  1790. next = desc->next;
  1791. dp_tx_desc_release(desc, desc->pool_id);
  1792. desc = next;
  1793. }
  1794. DP_TX_HIST_STATS_PER_PDEV();
  1795. }
  1796. /**
  1797. * dp_tx_comp_handler() - Tx completion handler
  1798. * @soc: core txrx main context
  1799. * @ring_id: completion ring id
  1800. * @quota: No. of packets/descriptors that can be serviced in one loop
  1801. *
  1802. * This function will collect hardware release ring element contents and
  1803. * handle descriptor contents. Based on contents, free packet or handle error
  1804. * conditions
  1805. *
  1806. * Return: none
  1807. */
  1808. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  1809. {
  1810. void *tx_comp_hal_desc;
  1811. uint8_t buffer_src;
  1812. uint8_t pool_id;
  1813. uint32_t tx_desc_id;
  1814. struct dp_tx_desc_s *tx_desc = NULL;
  1815. struct dp_tx_desc_s *head_desc = NULL;
  1816. struct dp_tx_desc_s *tail_desc = NULL;
  1817. uint32_t num_processed;
  1818. uint32_t count;
  1819. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1820. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1821. "%s %d : HAL RING Access Failed -- %pK\n",
  1822. __func__, __LINE__, hal_srng);
  1823. return 0;
  1824. }
  1825. num_processed = 0;
  1826. count = 0;
  1827. /* Find head descriptor from completion ring */
  1828. while (qdf_likely(tx_comp_hal_desc =
  1829. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  1830. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  1831. /* If this buffer was not released by TQM or FW, then it is not
  1832. * Tx completion indication, assert */
  1833. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  1834. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1835. QDF_TRACE(QDF_MODULE_ID_DP,
  1836. QDF_TRACE_LEVEL_FATAL,
  1837. "Tx comp release_src != TQM | FW");
  1838. qdf_assert_always(0);
  1839. }
  1840. /* Get descriptor id */
  1841. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  1842. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  1843. DP_TX_DESC_ID_POOL_OS;
  1844. /* Pool ID is out of limit. Error */
  1845. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  1846. soc->wlan_cfg_ctx)) {
  1847. QDF_TRACE(QDF_MODULE_ID_DP,
  1848. QDF_TRACE_LEVEL_FATAL,
  1849. "Tx Comp pool id %d not valid",
  1850. pool_id);
  1851. qdf_assert_always(0);
  1852. }
  1853. /* Find Tx descriptor */
  1854. tx_desc = dp_tx_desc_find(soc, pool_id,
  1855. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  1856. DP_TX_DESC_ID_PAGE_OS,
  1857. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  1858. DP_TX_DESC_ID_OFFSET_OS);
  1859. /* Pool id is not matching. Error */
  1860. if (tx_desc && (tx_desc->pool_id != pool_id)) {
  1861. QDF_TRACE(QDF_MODULE_ID_DP,
  1862. QDF_TRACE_LEVEL_FATAL,
  1863. "Tx Comp pool id %d not matched %d",
  1864. pool_id, tx_desc->pool_id);
  1865. qdf_assert_always(0);
  1866. }
  1867. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  1868. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  1869. QDF_TRACE(QDF_MODULE_ID_DP,
  1870. QDF_TRACE_LEVEL_FATAL,
  1871. "Txdesc invalid, flgs = %x,id = %d",
  1872. tx_desc->flags, tx_desc_id);
  1873. qdf_assert_always(0);
  1874. }
  1875. /*
  1876. * If the release source is FW, process the HTT status
  1877. */
  1878. if (qdf_unlikely(buffer_src ==
  1879. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1880. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1881. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  1882. htt_tx_status);
  1883. dp_tx_process_htt_completion(tx_desc,
  1884. htt_tx_status);
  1885. } else {
  1886. /* First ring descriptor on the cycle */
  1887. if (!head_desc) {
  1888. head_desc = tx_desc;
  1889. tail_desc = tx_desc;
  1890. }
  1891. tail_desc->next = tx_desc;
  1892. tx_desc->next = NULL;
  1893. tail_desc = tx_desc;
  1894. /* Collect hw completion contents */
  1895. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1896. &tx_desc->comp, soc->process_tx_status);
  1897. }
  1898. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  1899. /* Decrement PM usage count if the packet has been sent.*/
  1900. hif_pm_runtime_put(soc->hif_handle);
  1901. /*
  1902. * Processed packet count is more than given quota
  1903. * stop to processing
  1904. */
  1905. if ((num_processed >= quota))
  1906. break;
  1907. count++;
  1908. }
  1909. hal_srng_access_end(soc->hal_soc, hal_srng);
  1910. /* Process the reaped descriptors */
  1911. if (head_desc)
  1912. dp_tx_comp_process_desc(soc, head_desc);
  1913. return num_processed;
  1914. }
  1915. /**
  1916. * dp_tx_vdev_attach() - attach vdev to dp tx
  1917. * @vdev: virtual device instance
  1918. *
  1919. * Return: QDF_STATUS_SUCCESS: success
  1920. * QDF_STATUS_E_RESOURCES: Error return
  1921. */
  1922. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  1923. {
  1924. /*
  1925. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  1926. */
  1927. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  1928. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  1929. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  1930. vdev->vdev_id);
  1931. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  1932. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  1933. /*
  1934. * Set HTT Extension Valid bit to 0 by default
  1935. */
  1936. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  1937. dp_tx_vdev_update_search_flags(vdev);
  1938. return QDF_STATUS_SUCCESS;
  1939. }
  1940. /**
  1941. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  1942. * @vdev: virtual device instance
  1943. *
  1944. * Return: void
  1945. *
  1946. */
  1947. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  1948. {
  1949. /*
  1950. * Enable both AddrY (SA based search) and AddrX (Da based search)
  1951. * for TDLS link
  1952. *
  1953. * Enable AddrY (SA based search) only for non-WDS STA and
  1954. * ProxySTA VAP modes.
  1955. *
  1956. * In all other VAP modes, only DA based search should be
  1957. * enabled
  1958. */
  1959. if (vdev->opmode == wlan_op_mode_sta &&
  1960. vdev->tdls_link_connected)
  1961. vdev->hal_desc_addr_search_flags =
  1962. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  1963. else if ((vdev->opmode == wlan_op_mode_sta &&
  1964. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  1965. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  1966. else
  1967. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  1968. }
  1969. /**
  1970. * dp_tx_vdev_detach() - detach vdev from dp tx
  1971. * @vdev: virtual device instance
  1972. *
  1973. * Return: QDF_STATUS_SUCCESS: success
  1974. * QDF_STATUS_E_RESOURCES: Error return
  1975. */
  1976. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  1977. {
  1978. return QDF_STATUS_SUCCESS;
  1979. }
  1980. /**
  1981. * dp_tx_pdev_attach() - attach pdev to dp tx
  1982. * @pdev: physical device instance
  1983. *
  1984. * Return: QDF_STATUS_SUCCESS: success
  1985. * QDF_STATUS_E_RESOURCES: Error return
  1986. */
  1987. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  1988. {
  1989. struct dp_soc *soc = pdev->soc;
  1990. /* Initialize Flow control counters */
  1991. qdf_atomic_init(&pdev->num_tx_exception);
  1992. qdf_atomic_init(&pdev->num_tx_outstanding);
  1993. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1994. /* Initialize descriptors in TCL Ring */
  1995. hal_tx_init_data_ring(soc->hal_soc,
  1996. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  1997. }
  1998. return QDF_STATUS_SUCCESS;
  1999. }
  2000. /**
  2001. * dp_tx_pdev_detach() - detach pdev from dp tx
  2002. * @pdev: physical device instance
  2003. *
  2004. * Return: QDF_STATUS_SUCCESS: success
  2005. * QDF_STATUS_E_RESOURCES: Error return
  2006. */
  2007. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2008. {
  2009. /* What should do here? */
  2010. return QDF_STATUS_SUCCESS;
  2011. }
  2012. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2013. /* Pools will be allocated dynamically */
  2014. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2015. int num_desc)
  2016. {
  2017. uint8_t i;
  2018. for (i = 0; i < num_pool; i++) {
  2019. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2020. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2021. }
  2022. return 0;
  2023. }
  2024. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2025. {
  2026. uint8_t i;
  2027. for (i = 0; i < num_pool; i++)
  2028. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2029. }
  2030. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2031. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2032. int num_desc)
  2033. {
  2034. uint8_t i;
  2035. /* Allocate software Tx descriptor pools */
  2036. for (i = 0; i < num_pool; i++) {
  2037. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2038. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2039. "%s Tx Desc Pool alloc %d failed %pK\n",
  2040. __func__, i, soc);
  2041. return ENOMEM;
  2042. }
  2043. }
  2044. return 0;
  2045. }
  2046. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2047. {
  2048. uint8_t i;
  2049. for (i = 0; i < num_pool; i++) {
  2050. if (dp_tx_desc_pool_free(soc, i)) {
  2051. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2052. "%s Tx Desc Pool Free failed\n", __func__);
  2053. }
  2054. }
  2055. }
  2056. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2057. /**
  2058. * dp_tx_soc_detach() - detach soc from dp tx
  2059. * @soc: core txrx main context
  2060. *
  2061. * This function will detach dp tx into main device context
  2062. * will free dp tx resource and initialize resources
  2063. *
  2064. * Return: QDF_STATUS_SUCCESS: success
  2065. * QDF_STATUS_E_RESOURCES: Error return
  2066. */
  2067. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2068. {
  2069. uint8_t num_pool;
  2070. uint16_t num_desc;
  2071. uint16_t num_ext_desc;
  2072. uint8_t i;
  2073. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2074. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2075. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2076. dp_tx_flow_control_deinit(soc);
  2077. dp_tx_delete_static_pools(soc, num_pool);
  2078. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2079. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2080. __func__, num_pool, num_desc);
  2081. for (i = 0; i < num_pool; i++) {
  2082. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2083. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2084. "%s Tx Ext Desc Pool Free failed\n",
  2085. __func__);
  2086. return QDF_STATUS_E_RESOURCES;
  2087. }
  2088. }
  2089. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2090. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2091. __func__, num_pool, num_ext_desc);
  2092. for (i = 0; i < num_pool; i++) {
  2093. dp_tx_tso_desc_pool_free(soc, i);
  2094. }
  2095. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2096. "%s TSO Desc Pool %d Free descs = %d\n",
  2097. __func__, num_pool, num_desc);
  2098. for (i = 0; i < num_pool; i++)
  2099. dp_tx_tso_num_seg_pool_free(soc, i);
  2100. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2101. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2102. __func__, num_pool, num_desc);
  2103. return QDF_STATUS_SUCCESS;
  2104. }
  2105. /**
  2106. * dp_tx_soc_attach() - attach soc to dp tx
  2107. * @soc: core txrx main context
  2108. *
  2109. * This function will attach dp tx into main device context
  2110. * will allocate dp tx resource and initialize resources
  2111. *
  2112. * Return: QDF_STATUS_SUCCESS: success
  2113. * QDF_STATUS_E_RESOURCES: Error return
  2114. */
  2115. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2116. {
  2117. uint8_t i;
  2118. uint8_t num_pool;
  2119. uint32_t num_desc;
  2120. uint32_t num_ext_desc;
  2121. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2122. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2123. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2124. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2125. goto fail;
  2126. dp_tx_flow_control_init(soc);
  2127. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2128. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2129. __func__, num_pool, num_desc);
  2130. /* Allocate extension tx descriptor pools */
  2131. for (i = 0; i < num_pool; i++) {
  2132. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2133. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2134. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2135. i, soc);
  2136. goto fail;
  2137. }
  2138. }
  2139. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2140. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2141. __func__, num_pool, num_ext_desc);
  2142. for (i = 0; i < num_pool; i++) {
  2143. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2144. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2145. "TSO Desc Pool alloc %d failed %pK\n",
  2146. i, soc);
  2147. goto fail;
  2148. }
  2149. }
  2150. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2151. "%s TSO Desc Alloc %d, descs = %d\n",
  2152. __func__, num_pool, num_desc);
  2153. for (i = 0; i < num_pool; i++) {
  2154. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2155. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2156. "TSO Num of seg Pool alloc %d failed %pK\n",
  2157. i, soc);
  2158. goto fail;
  2159. }
  2160. }
  2161. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2162. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2163. __func__, num_pool, num_desc);
  2164. /* Initialize descriptors in TCL Rings */
  2165. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2166. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2167. hal_tx_init_data_ring(soc->hal_soc,
  2168. soc->tcl_data_ring[i].hal_srng);
  2169. }
  2170. }
  2171. /*
  2172. * todo - Add a runtime config option to enable this.
  2173. */
  2174. /*
  2175. * Due to multiple issues on NPR EMU, enable it selectively
  2176. * only for NPR EMU, should be removed, once NPR platforms
  2177. * are stable.
  2178. */
  2179. soc->process_tx_status = 0;
  2180. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2181. "%s HAL Tx init Success\n", __func__);
  2182. return QDF_STATUS_SUCCESS;
  2183. fail:
  2184. /* Detach will take care of freeing only allocated resources */
  2185. dp_tx_soc_detach(soc);
  2186. return QDF_STATUS_E_RESOURCES;
  2187. }
  2188. /*
  2189. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2190. * pdev: pointer to DP PDEV structure
  2191. * seg_info_head: Pointer to the head of list
  2192. *
  2193. * return: void
  2194. */
  2195. static inline void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2196. struct dp_tx_seg_info_s *seg_info_head)
  2197. {
  2198. struct dp_tx_me_buf_t *mc_uc_buf;
  2199. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2200. qdf_nbuf_t nbuf = NULL;
  2201. uint64_t phy_addr;
  2202. while (seg_info_head) {
  2203. nbuf = seg_info_head->nbuf;
  2204. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2205. seg_info_new->frags[0].vaddr;
  2206. phy_addr = seg_info_head->frags[0].paddr_hi;
  2207. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2208. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2209. phy_addr,
  2210. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2211. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2212. qdf_nbuf_free(nbuf);
  2213. seg_info_new = seg_info_head;
  2214. seg_info_head = seg_info_head->next;
  2215. qdf_mem_free(seg_info_new);
  2216. }
  2217. }
  2218. /**
  2219. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2220. * @vdev: DP VDEV handle
  2221. * @nbuf: Multicast nbuf
  2222. * @newmac: Table of the clients to which packets have to be sent
  2223. * @new_mac_cnt: No of clients
  2224. *
  2225. * return: no of converted packets
  2226. */
  2227. uint16_t
  2228. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2229. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2230. {
  2231. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2232. struct dp_pdev *pdev = vdev->pdev;
  2233. struct ether_header *eh;
  2234. uint8_t *data;
  2235. uint16_t len;
  2236. /* reference to frame dst addr */
  2237. uint8_t *dstmac;
  2238. /* copy of original frame src addr */
  2239. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2240. /* local index into newmac */
  2241. uint8_t new_mac_idx = 0;
  2242. struct dp_tx_me_buf_t *mc_uc_buf;
  2243. qdf_nbuf_t nbuf_clone;
  2244. struct dp_tx_msdu_info_s msdu_info;
  2245. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2246. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2247. struct dp_tx_seg_info_s *seg_info_new;
  2248. struct dp_tx_frag_info_s data_frag;
  2249. qdf_dma_addr_t paddr_data;
  2250. qdf_dma_addr_t paddr_mcbuf = 0;
  2251. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2252. QDF_STATUS status;
  2253. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2254. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2255. eh = (struct ether_header *) nbuf;
  2256. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2257. len = qdf_nbuf_len(nbuf);
  2258. data = qdf_nbuf_data(nbuf);
  2259. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2260. QDF_DMA_TO_DEVICE);
  2261. if (status) {
  2262. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2263. "Mapping failure Error:%d", status);
  2264. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2265. return 0;
  2266. }
  2267. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2268. /*preparing data fragment*/
  2269. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2270. data_frag.paddr_lo = (uint32_t)paddr_data;
  2271. data_frag.paddr_hi = ((uint64_t)paddr_data & 0xffffffff00000000) >> 32;
  2272. data_frag.len = len - DP_MAC_ADDR_LEN;
  2273. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2274. dstmac = newmac[new_mac_idx];
  2275. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2276. "added mac addr (%pM)", dstmac);
  2277. /* Check for NULL Mac Address */
  2278. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2279. continue;
  2280. /* frame to self mac. skip */
  2281. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2282. continue;
  2283. /*
  2284. * TODO: optimize to avoid malloc in per-packet path
  2285. * For eg. seg_pool can be made part of vdev structure
  2286. */
  2287. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2288. if (!seg_info_new) {
  2289. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2290. "alloc failed");
  2291. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2292. goto fail_seg_alloc;
  2293. }
  2294. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2295. if (mc_uc_buf == NULL)
  2296. goto fail_buf_alloc;
  2297. /*
  2298. * TODO: Check if we need to clone the nbuf
  2299. * Or can we just use the reference for all cases
  2300. */
  2301. if (new_mac_idx < (new_mac_cnt - 1)) {
  2302. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2303. if (nbuf_clone == NULL) {
  2304. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2305. goto fail_clone;
  2306. }
  2307. } else {
  2308. /*
  2309. * Update the ref
  2310. * to account for frame sent without cloning
  2311. */
  2312. qdf_nbuf_ref(nbuf);
  2313. nbuf_clone = nbuf;
  2314. }
  2315. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2316. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2317. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2318. &paddr_mcbuf);
  2319. if (status) {
  2320. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2321. "Mapping failure Error:%d", status);
  2322. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2323. goto fail_map;
  2324. }
  2325. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2326. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2327. seg_info_new->frags[0].paddr_hi =
  2328. ((u64)paddr_mcbuf & 0xffffffff00000000) >> 32;
  2329. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2330. seg_info_new->frags[1] = data_frag;
  2331. seg_info_new->nbuf = nbuf_clone;
  2332. seg_info_new->frag_cnt = 2;
  2333. seg_info_new->total_len = len;
  2334. seg_info_new->next = NULL;
  2335. if (seg_info_head == NULL)
  2336. seg_info_head = seg_info_new;
  2337. else
  2338. seg_info_tail->next = seg_info_new;
  2339. seg_info_tail = seg_info_new;
  2340. }
  2341. if (!seg_info_head)
  2342. return 0;
  2343. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2344. msdu_info.num_seg = new_mac_cnt;
  2345. msdu_info.frm_type = dp_tx_frm_me;
  2346. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2347. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2348. while (seg_info_head->next) {
  2349. seg_info_new = seg_info_head;
  2350. seg_info_head = seg_info_head->next;
  2351. qdf_mem_free(seg_info_new);
  2352. }
  2353. qdf_mem_free(seg_info_head);
  2354. return new_mac_cnt;
  2355. fail_map:
  2356. qdf_nbuf_free(nbuf_clone);
  2357. fail_clone:
  2358. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2359. fail_buf_alloc:
  2360. qdf_mem_free(seg_info_new);
  2361. fail_seg_alloc:
  2362. dp_tx_me_mem_free(pdev, seg_info_head);
  2363. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2364. return 0;
  2365. }