dp_main.c 152 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170517151725173517451755176517751785179518051815182518351845185518651875188518951905191519251935194519551965197519851995200520152025203520452055206520752085209521052115212521352145215521652175218521952205221522252235224522552265227522852295230523152325233523452355236523752385239524052415242524352445245524652475248524952505251525252535254525552565257525852595260526152625263526452655266526752685269527052715272527352745275527652775278527952805281528252835284528552865287528852895290529152925293529452955296529752985299530053015302530353045305530653075308530953105311531253135314531553165317531853195320532153225323532453255326532753285329533053315332533353345335533653375338533953405341534253435344534553465347534853495350535153525353535453555356535753585359536053615362536353645365536653675368536953705371537253735374537553765377537853795380538153825383538453855386538753885389539053915392539353945395539653975398539954005401540254035404540554065407540854095410541154125413541454155416541754185419542054215422542354245425542654275428542954305431543254335434543554365437543854395440544154425443544454455446544754485449545054515452545354545455545654575458545954605461546254635464546554665467546854695470547154725473547454755476547754785479548054815482548354845485548654875488548954905491549254935494549554965497549854995500550155025503550455055506550755085509551055115512551355145515551655175518551955205521552255235524552555265527
  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include <ol_cfg.h>
  52. #include "dp_ipa.h"
  53. #define DP_INTR_POLL_TIMER_MS 10
  54. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  55. #define DP_MCS_LENGTH (6*MAX_MCS)
  56. #define DP_NSS_LENGTH (6*SS_COUNT)
  57. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  58. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  59. #define DP_MAX_MCS_STRING_LEN 30
  60. #define DP_CURR_FW_STATS_AVAIL 19
  61. #define DP_HTT_DBG_EXT_STATS_MAX 256
  62. #ifdef IPA_OFFLOAD
  63. /* Exclude IPA rings from the interrupt context */
  64. #define TX_RING_MASK_VAL 0x7
  65. #define RX_RING_MASK_VAL 0x7
  66. #else
  67. #define TX_RING_MASK_VAL 0xF
  68. #define RX_RING_MASK_VAL 0xF
  69. #endif
  70. bool rx_hash = 1;
  71. qdf_declare_param(rx_hash, bool);
  72. /**
  73. * default_dscp_tid_map - Default DSCP-TID mapping
  74. *
  75. * DSCP TID AC
  76. * 000000 0 WME_AC_BE
  77. * 001000 1 WME_AC_BK
  78. * 010000 1 WME_AC_BK
  79. * 011000 0 WME_AC_BE
  80. * 100000 5 WME_AC_VI
  81. * 101000 5 WME_AC_VI
  82. * 110000 6 WME_AC_VO
  83. * 111000 6 WME_AC_VO
  84. */
  85. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  86. 0, 0, 0, 0, 0, 0, 0, 0,
  87. 1, 1, 1, 1, 1, 1, 1, 1,
  88. 1, 1, 1, 1, 1, 1, 1, 1,
  89. 0, 0, 0, 0, 0, 0, 0, 0,
  90. 5, 5, 5, 5, 5, 5, 5, 5,
  91. 5, 5, 5, 5, 5, 5, 5, 5,
  92. 6, 6, 6, 6, 6, 6, 6, 6,
  93. 6, 6, 6, 6, 6, 6, 6, 6,
  94. };
  95. /*
  96. * struct dp_rate_debug
  97. *
  98. * @mcs_type: print string for a given mcs
  99. * @valid: valid mcs rate?
  100. */
  101. struct dp_rate_debug {
  102. char mcs_type[DP_MAX_MCS_STRING_LEN];
  103. uint8_t valid;
  104. };
  105. #define MCS_VALID 1
  106. #define MCS_INVALID 0
  107. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  108. {
  109. {"CCK 11 Mbps Long ", MCS_VALID},
  110. {"CCK 5.5 Mbps Long ", MCS_VALID},
  111. {"CCK 2 Mbps Long ", MCS_VALID},
  112. {"CCK 1 Mbps Long ", MCS_VALID},
  113. {"CCK 11 Mbps Short ", MCS_VALID},
  114. {"CCK 5.5 Mbps Short", MCS_VALID},
  115. {"CCK 2 Mbps Short ", MCS_VALID},
  116. {"INVALID ", MCS_INVALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_INVALID},
  119. {"INVALID ", MCS_INVALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_VALID},
  122. },
  123. {
  124. {"OFDM 48 Mbps", MCS_VALID},
  125. {"OFDM 24 Mbps", MCS_VALID},
  126. {"OFDM 12 Mbps", MCS_VALID},
  127. {"OFDM 6 Mbps ", MCS_VALID},
  128. {"OFDM 54 Mbps", MCS_VALID},
  129. {"OFDM 36 Mbps", MCS_VALID},
  130. {"OFDM 18 Mbps", MCS_VALID},
  131. {"OFDM 9 Mbps ", MCS_VALID},
  132. {"INVALID ", MCS_INVALID},
  133. {"INVALID ", MCS_INVALID},
  134. {"INVALID ", MCS_INVALID},
  135. {"INVALID ", MCS_INVALID},
  136. {"INVALID ", MCS_VALID},
  137. },
  138. {
  139. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  140. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  141. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  142. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  143. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  144. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  145. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  146. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  147. {"INVALID ", MCS_INVALID},
  148. {"INVALID ", MCS_INVALID},
  149. {"INVALID ", MCS_INVALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_VALID},
  152. },
  153. {
  154. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  155. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  156. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  157. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  158. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  159. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  160. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  161. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  162. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  163. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  164. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  165. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  166. {"INVALID ", MCS_VALID},
  167. },
  168. {
  169. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  170. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  171. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  172. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  173. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  174. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  175. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  176. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  177. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  178. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  179. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  180. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  181. {"INVALID ", MCS_VALID},
  182. }
  183. };
  184. /**
  185. * @brief Cpu ring map types
  186. */
  187. enum dp_cpu_ring_map_types {
  188. DP_DEFAULT_MAP,
  189. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  190. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  191. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  192. DP_CPU_RING_MAP_MAX
  193. };
  194. /**
  195. * @brief Cpu to tx ring map
  196. */
  197. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  198. {0x0, 0x1, 0x2, 0x0},
  199. {0x1, 0x2, 0x1, 0x2},
  200. {0x0, 0x2, 0x0, 0x2},
  201. {0x2, 0x2, 0x2, 0x2}
  202. };
  203. /**
  204. * @brief Select the type of statistics
  205. */
  206. enum dp_stats_type {
  207. STATS_FW = 0,
  208. STATS_HOST = 1,
  209. STATS_TYPE_MAX = 2,
  210. };
  211. /**
  212. * @brief General Firmware statistics options
  213. *
  214. */
  215. enum dp_fw_stats {
  216. TXRX_FW_STATS_INVALID = -1,
  217. };
  218. /**
  219. * dp_stats_mapping_table - Firmware and Host statistics
  220. * currently supported
  221. */
  222. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  223. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  224. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  234. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  235. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  242. /* Last ENUM for HTT FW STATS */
  243. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  244. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  245. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  247. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  248. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  250. };
  251. /**
  252. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  253. * @ring_num: ring num of the ring being queried
  254. * @grp_mask: the grp_mask array for the ring type in question.
  255. *
  256. * The grp_mask array is indexed by group number and the bit fields correspond
  257. * to ring numbers. We are finding which interrupt group a ring belongs to.
  258. *
  259. * Return: the index in the grp_mask array with the ring number.
  260. * -QDF_STATUS_E_NOENT if no entry is found
  261. */
  262. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  263. {
  264. int ext_group_num;
  265. int mask = 1 << ring_num;
  266. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  267. ext_group_num++) {
  268. if (mask & grp_mask[ext_group_num])
  269. return ext_group_num;
  270. }
  271. return -QDF_STATUS_E_NOENT;
  272. }
  273. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  274. enum hal_ring_type ring_type,
  275. int ring_num)
  276. {
  277. int *grp_mask;
  278. switch (ring_type) {
  279. case WBM2SW_RELEASE:
  280. /* dp_tx_comp_handler - soc->tx_comp_ring */
  281. if (ring_num < 3)
  282. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  283. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  284. else if (ring_num == 3) {
  285. /* sw treats this as a separate ring type */
  286. grp_mask = &soc->wlan_cfg_ctx->
  287. int_rx_wbm_rel_ring_mask[0];
  288. ring_num = 0;
  289. } else {
  290. qdf_assert(0);
  291. return -QDF_STATUS_E_NOENT;
  292. }
  293. break;
  294. case REO_EXCEPTION:
  295. /* dp_rx_err_process - &soc->reo_exception_ring */
  296. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  297. break;
  298. case REO_DST:
  299. /* dp_rx_process - soc->reo_dest_ring */
  300. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  301. break;
  302. case REO_STATUS:
  303. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  304. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  305. break;
  306. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  307. case RXDMA_MONITOR_STATUS:
  308. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  309. case RXDMA_MONITOR_DST:
  310. /* dp_mon_process */
  311. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  312. break;
  313. case RXDMA_MONITOR_BUF:
  314. case RXDMA_BUF:
  315. /* TODO: support low_thresh interrupt */
  316. return -QDF_STATUS_E_NOENT;
  317. break;
  318. case TCL_DATA:
  319. case TCL_CMD:
  320. case REO_CMD:
  321. case SW2WBM_RELEASE:
  322. case WBM_IDLE_LINK:
  323. /* normally empty SW_TO_HW rings */
  324. return -QDF_STATUS_E_NOENT;
  325. break;
  326. case TCL_STATUS:
  327. case REO_REINJECT:
  328. case RXDMA_DST:
  329. /* misc unused rings */
  330. return -QDF_STATUS_E_NOENT;
  331. break;
  332. case CE_SRC:
  333. case CE_DST:
  334. case CE_DST_STATUS:
  335. /* CE_rings - currently handled by hif */
  336. default:
  337. return -QDF_STATUS_E_NOENT;
  338. break;
  339. }
  340. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  341. }
  342. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  343. *ring_params, int ring_type, int ring_num)
  344. {
  345. int msi_group_number;
  346. int msi_data_count;
  347. int ret;
  348. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  349. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  350. &msi_data_count, &msi_data_start,
  351. &msi_irq_start);
  352. if (ret)
  353. return;
  354. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  355. ring_num);
  356. if (msi_group_number < 0) {
  357. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  358. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  359. ring_type, ring_num);
  360. ring_params->msi_addr = 0;
  361. ring_params->msi_data = 0;
  362. return;
  363. }
  364. if (msi_group_number > msi_data_count) {
  365. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  366. FL("2 msi_groups will share an msi; msi_group_num %d"),
  367. msi_group_number);
  368. QDF_ASSERT(0);
  369. }
  370. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  371. ring_params->msi_addr = addr_low;
  372. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  373. ring_params->msi_data = (msi_group_number % msi_data_count)
  374. + msi_data_start;
  375. ring_params->flags |= HAL_SRNG_MSI_INTR;
  376. }
  377. /**
  378. * dp_print_ast_stats() - Dump AST table contents
  379. * @soc: Datapath soc handle
  380. *
  381. * return void
  382. */
  383. #ifdef FEATURE_WDS
  384. static void dp_print_ast_stats(struct dp_soc *soc)
  385. {
  386. uint8_t i;
  387. uint8_t num_entries = 0;
  388. struct dp_vdev *vdev;
  389. struct dp_pdev *pdev;
  390. struct dp_peer *peer;
  391. struct dp_ast_entry *ase, *tmp_ase;
  392. DP_PRINT_STATS("AST Stats:");
  393. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  394. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  395. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  396. DP_PRINT_STATS("AST Table:");
  397. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  398. pdev = soc->pdev_list[i];
  399. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  400. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  401. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  402. DP_PRINT_STATS("%6d mac_addr = %pM"
  403. " peer_mac_addr = %pM"
  404. " type = %d"
  405. " next_hop = %d"
  406. " is_active = %d"
  407. " is_bss = %d",
  408. ++num_entries,
  409. ase->mac_addr.raw,
  410. ase->peer->mac_addr.raw,
  411. ase->type,
  412. ase->next_hop,
  413. ase->is_active,
  414. ase->is_bss);
  415. }
  416. }
  417. }
  418. }
  419. }
  420. #else
  421. static void dp_print_ast_stats(struct dp_soc *soc)
  422. {
  423. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  424. return;
  425. }
  426. #endif
  427. /*
  428. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  429. */
  430. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  431. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  432. {
  433. void *hal_soc = soc->hal_soc;
  434. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  435. /* TODO: See if we should get align size from hal */
  436. uint32_t ring_base_align = 8;
  437. struct hal_srng_params ring_params;
  438. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  439. /* TODO: Currently hal layer takes care of endianness related settings.
  440. * See if these settings need to passed from DP layer
  441. */
  442. ring_params.flags = 0;
  443. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  444. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  445. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  446. srng->hal_srng = NULL;
  447. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  448. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  449. soc->osdev, soc->osdev->dev, srng->alloc_size,
  450. &(srng->base_paddr_unaligned));
  451. if (!srng->base_vaddr_unaligned) {
  452. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  453. FL("alloc failed - ring_type: %d, ring_num %d"),
  454. ring_type, ring_num);
  455. return QDF_STATUS_E_NOMEM;
  456. }
  457. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  458. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  459. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  460. ((unsigned long)(ring_params.ring_base_vaddr) -
  461. (unsigned long)srng->base_vaddr_unaligned);
  462. ring_params.num_entries = num_entries;
  463. if (soc->intr_mode == DP_INTR_MSI) {
  464. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  465. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  466. FL("Using MSI for ring_type: %d, ring_num %d"),
  467. ring_type, ring_num);
  468. } else {
  469. ring_params.msi_data = 0;
  470. ring_params.msi_addr = 0;
  471. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  472. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  473. ring_type, ring_num);
  474. }
  475. /*
  476. * Setup interrupt timer and batch counter thresholds for
  477. * interrupt mitigation based on ring type
  478. */
  479. if (ring_type == REO_DST) {
  480. ring_params.intr_timer_thres_us =
  481. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  482. ring_params.intr_batch_cntr_thres_entries =
  483. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  484. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  485. ring_params.intr_timer_thres_us =
  486. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  487. ring_params.intr_batch_cntr_thres_entries =
  488. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  489. } else {
  490. ring_params.intr_timer_thres_us =
  491. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  492. ring_params.intr_batch_cntr_thres_entries =
  493. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  494. }
  495. /* Enable low threshold interrupts for rx buffer rings (regular and
  496. * monitor buffer rings.
  497. * TODO: See if this is required for any other ring
  498. */
  499. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  500. /* TODO: Setting low threshold to 1/8th of ring size
  501. * see if this needs to be configurable
  502. */
  503. ring_params.low_threshold = num_entries >> 3;
  504. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  505. ring_params.intr_timer_thres_us = 0x1000;
  506. }
  507. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  508. mac_id, &ring_params);
  509. return 0;
  510. }
  511. /**
  512. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  513. * Any buffers allocated and attached to ring entries are expected to be freed
  514. * before calling this function.
  515. */
  516. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  517. int ring_type, int ring_num)
  518. {
  519. if (!srng->hal_srng) {
  520. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  521. FL("Ring type: %d, num:%d not setup"),
  522. ring_type, ring_num);
  523. return;
  524. }
  525. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  526. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  527. srng->alloc_size,
  528. srng->base_vaddr_unaligned,
  529. srng->base_paddr_unaligned, 0);
  530. srng->hal_srng = NULL;
  531. }
  532. #ifdef IPA_OFFLOAD
  533. /**
  534. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  535. * @soc: data path instance
  536. * @pdev: core txrx pdev context
  537. *
  538. * Free allocated TX buffers with WBM SRNG
  539. *
  540. * Return: none
  541. */
  542. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  543. {
  544. int idx;
  545. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  546. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  547. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  548. }
  549. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  550. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  551. }
  552. /**
  553. * dp_rx_ipa_uc_detach - free autonomy RX resources
  554. * @soc: data path instance
  555. * @pdev: core txrx pdev context
  556. *
  557. * This function will detach DP RX into main device context
  558. * will free DP Rx resources.
  559. *
  560. * Return: none
  561. */
  562. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  563. {
  564. }
  565. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  566. {
  567. /* TX resource detach */
  568. dp_tx_ipa_uc_detach(soc, pdev);
  569. /* RX resource detach */
  570. dp_rx_ipa_uc_detach(soc, pdev);
  571. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  572. return QDF_STATUS_SUCCESS; /* success */
  573. }
  574. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  575. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  576. /**
  577. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  578. * @soc: data path instance
  579. * @pdev: Physical device handle
  580. *
  581. * Allocate TX buffer from non-cacheable memory
  582. * Attache allocated TX buffers with WBM SRNG
  583. *
  584. * Return: int
  585. */
  586. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  587. {
  588. uint32_t tx_buffer_count;
  589. uint32_t ring_base_align = 8;
  590. void *buffer_vaddr_unaligned;
  591. void *buffer_vaddr;
  592. qdf_dma_addr_t buffer_paddr_unaligned;
  593. qdf_dma_addr_t buffer_paddr;
  594. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  595. uint32_t paddr_lo;
  596. uint32_t paddr_hi;
  597. void *ring_entry;
  598. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  599. int retval = QDF_STATUS_SUCCESS;
  600. /*
  601. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  602. * unsigned int uc_tx_buf_sz =
  603. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  604. */
  605. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  606. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  607. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  608. "requested %d buffers to be posted to wbm ring",
  609. ring_size);
  610. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  611. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  612. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  613. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  614. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  615. return -ENOMEM;
  616. }
  617. hal_srng_access_start(soc->hal_soc, wbm_srng);
  618. /* Allocate TX buffers as many as possible */
  619. for (tx_buffer_count = 0;
  620. tx_buffer_count < ring_size; tx_buffer_count++) {
  621. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  622. if (!ring_entry) {
  623. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  624. "Failed to get WBM ring entry\n");
  625. goto fail;
  626. }
  627. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  628. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  629. if (!buffer_vaddr_unaligned) {
  630. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  631. "IPA WDI TX buffer alloc fail %d allocated\n",
  632. tx_buffer_count);
  633. break;
  634. }
  635. buffer_vaddr = buffer_vaddr_unaligned +
  636. ((unsigned long)buffer_vaddr_unaligned %
  637. ring_base_align);
  638. buffer_paddr = buffer_paddr_unaligned +
  639. ((unsigned long)(buffer_vaddr) -
  640. (unsigned long)buffer_vaddr_unaligned);
  641. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  642. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  643. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  644. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  645. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  646. buffer_vaddr;
  647. }
  648. hal_srng_access_end(soc->hal_soc, wbm_srng);
  649. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  650. return retval;
  651. fail:
  652. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  653. return retval;
  654. }
  655. /**
  656. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  657. * @soc: data path instance
  658. * @pdev: core txrx pdev context
  659. *
  660. * This function will attach a DP RX instance into the main
  661. * device (SOC) context.
  662. *
  663. * Return: QDF_STATUS_SUCCESS: success
  664. * QDF_STATUS_E_RESOURCES: Error return
  665. */
  666. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  667. {
  668. return QDF_STATUS_SUCCESS;
  669. }
  670. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  671. {
  672. int error;
  673. /* TX resource attach */
  674. error = dp_tx_ipa_uc_attach(soc, pdev);
  675. if (error) {
  676. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  677. "DP IPA UC TX attach fail code %d\n", error);
  678. return error;
  679. }
  680. /* RX resource attach */
  681. error = dp_rx_ipa_uc_attach(soc, pdev);
  682. if (error) {
  683. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  684. "DP IPA UC RX attach fail code %d\n", error);
  685. dp_tx_ipa_uc_detach(soc, pdev);
  686. return error;
  687. }
  688. return QDF_STATUS_SUCCESS; /* success */
  689. }
  690. #else
  691. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  692. {
  693. return QDF_STATUS_SUCCESS;
  694. }
  695. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  696. {
  697. return QDF_STATUS_SUCCESS;
  698. }
  699. #endif
  700. /* TODO: Need this interface from HIF */
  701. void *hif_get_hal_handle(void *hif_handle);
  702. /*
  703. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  704. * @dp_ctx: DP SOC handle
  705. * @budget: Number of frames/descriptors that can be processed in one shot
  706. *
  707. * Return: remaining budget/quota for the soc device
  708. */
  709. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  710. {
  711. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  712. struct dp_soc *soc = int_ctx->soc;
  713. int ring = 0;
  714. uint32_t work_done = 0;
  715. int budget = dp_budget;
  716. uint8_t tx_mask = int_ctx->tx_ring_mask;
  717. uint8_t rx_mask = int_ctx->rx_ring_mask;
  718. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  719. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  720. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  721. uint32_t remaining_quota = dp_budget;
  722. /* Process Tx completion interrupts first to return back buffers */
  723. while (tx_mask) {
  724. if (tx_mask & 0x1) {
  725. work_done = dp_tx_comp_handler(soc,
  726. soc->tx_comp_ring[ring].hal_srng,
  727. remaining_quota);
  728. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  729. "tx mask 0x%x ring %d, budget %d, work_done %d",
  730. tx_mask, ring, budget, work_done);
  731. budget -= work_done;
  732. if (budget <= 0)
  733. goto budget_done;
  734. remaining_quota = budget;
  735. }
  736. tx_mask = tx_mask >> 1;
  737. ring++;
  738. }
  739. /* Process REO Exception ring interrupt */
  740. if (rx_err_mask) {
  741. work_done = dp_rx_err_process(soc,
  742. soc->reo_exception_ring.hal_srng,
  743. remaining_quota);
  744. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  745. "REO Exception Ring: work_done %d budget %d",
  746. work_done, budget);
  747. budget -= work_done;
  748. if (budget <= 0) {
  749. goto budget_done;
  750. }
  751. remaining_quota = budget;
  752. }
  753. /* Process Rx WBM release ring interrupt */
  754. if (rx_wbm_rel_mask) {
  755. work_done = dp_rx_wbm_err_process(soc,
  756. soc->rx_rel_ring.hal_srng, remaining_quota);
  757. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  758. "WBM Release Ring: work_done %d budget %d",
  759. work_done, budget);
  760. budget -= work_done;
  761. if (budget <= 0) {
  762. goto budget_done;
  763. }
  764. remaining_quota = budget;
  765. }
  766. /* Process Rx interrupts */
  767. if (rx_mask) {
  768. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  769. if (rx_mask & (1 << ring)) {
  770. work_done = dp_rx_process(int_ctx,
  771. soc->reo_dest_ring[ring].hal_srng,
  772. remaining_quota);
  773. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  774. "rx mask 0x%x ring %d, work_done %d budget %d",
  775. rx_mask, ring, work_done, budget);
  776. budget -= work_done;
  777. if (budget <= 0)
  778. goto budget_done;
  779. remaining_quota = budget;
  780. }
  781. }
  782. }
  783. if (reo_status_mask)
  784. dp_reo_status_ring_handler(soc);
  785. /* Process LMAC interrupts */
  786. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  787. if (soc->pdev_list[ring] == NULL)
  788. continue;
  789. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  790. work_done = dp_mon_process(soc, ring, remaining_quota);
  791. budget -= work_done;
  792. remaining_quota = budget;
  793. }
  794. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  795. work_done = dp_rxdma_err_process(soc, ring,
  796. remaining_quota);
  797. budget -= work_done;
  798. }
  799. }
  800. qdf_lro_flush(int_ctx->lro_ctx);
  801. budget_done:
  802. return dp_budget - budget;
  803. }
  804. #ifdef DP_INTR_POLL_BASED
  805. /* dp_interrupt_timer()- timer poll for interrupts
  806. *
  807. * @arg: SoC Handle
  808. *
  809. * Return:
  810. *
  811. */
  812. static void dp_interrupt_timer(void *arg)
  813. {
  814. struct dp_soc *soc = (struct dp_soc *) arg;
  815. int i;
  816. if (qdf_atomic_read(&soc->cmn_init_done)) {
  817. for (i = 0;
  818. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  819. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  820. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  821. }
  822. }
  823. /*
  824. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  825. * @txrx_soc: DP SOC handle
  826. *
  827. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  828. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  829. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  830. *
  831. * Return: 0 for success. nonzero for failure.
  832. */
  833. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  834. {
  835. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  836. int i;
  837. soc->intr_mode = DP_INTR_POLL;
  838. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  839. soc->intr_ctx[i].dp_intr_id = i;
  840. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  841. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  842. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  843. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  844. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  845. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  846. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  847. soc->intr_ctx[i].soc = soc;
  848. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  849. }
  850. qdf_timer_init(soc->osdev, &soc->int_timer,
  851. dp_interrupt_timer, (void *)soc,
  852. QDF_TIMER_TYPE_WAKE_APPS);
  853. return QDF_STATUS_SUCCESS;
  854. }
  855. #ifdef CONFIG_MCL
  856. extern int con_mode_monitor;
  857. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  858. /*
  859. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  860. * @txrx_soc: DP SOC handle
  861. *
  862. * Call the appropriate attach function based on the mode of operation.
  863. * This is a WAR for enabling monitor mode.
  864. *
  865. * Return: 0 for success. nonzero for failure.
  866. */
  867. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  868. {
  869. if (con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  870. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  871. FL("Attach interrupts in Poll mode"));
  872. return dp_soc_interrupt_attach_poll(txrx_soc);
  873. } else {
  874. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  875. FL("Attach interrupts in MSI mode"));
  876. return dp_soc_interrupt_attach(txrx_soc);
  877. }
  878. }
  879. #else
  880. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  881. {
  882. return dp_soc_interrupt_attach_poll(txrx_soc);
  883. }
  884. #endif
  885. #endif
  886. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  887. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  888. {
  889. int j;
  890. int num_irq = 0;
  891. int tx_mask =
  892. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  893. int rx_mask =
  894. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  895. int rx_mon_mask =
  896. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  897. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  898. soc->wlan_cfg_ctx, intr_ctx_num);
  899. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  900. soc->wlan_cfg_ctx, intr_ctx_num);
  901. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  902. soc->wlan_cfg_ctx, intr_ctx_num);
  903. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  904. if (tx_mask & (1 << j)) {
  905. irq_id_map[num_irq++] =
  906. (wbm2host_tx_completions_ring1 - j);
  907. }
  908. if (rx_mask & (1 << j)) {
  909. irq_id_map[num_irq++] =
  910. (reo2host_destination_ring1 - j);
  911. }
  912. if (rx_mon_mask & (1 << j)) {
  913. irq_id_map[num_irq++] =
  914. (ppdu_end_interrupts_mac1 - j);
  915. }
  916. if (rx_wbm_rel_ring_mask & (1 << j))
  917. irq_id_map[num_irq++] = wbm2host_rx_release;
  918. if (rx_err_ring_mask & (1 << j))
  919. irq_id_map[num_irq++] = reo2host_exception;
  920. if (reo_status_ring_mask & (1 << j))
  921. irq_id_map[num_irq++] = reo2host_status;
  922. }
  923. *num_irq_r = num_irq;
  924. }
  925. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  926. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  927. int msi_vector_count, int msi_vector_start)
  928. {
  929. int tx_mask = wlan_cfg_get_tx_ring_mask(
  930. soc->wlan_cfg_ctx, intr_ctx_num);
  931. int rx_mask = wlan_cfg_get_rx_ring_mask(
  932. soc->wlan_cfg_ctx, intr_ctx_num);
  933. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  934. soc->wlan_cfg_ctx, intr_ctx_num);
  935. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  936. soc->wlan_cfg_ctx, intr_ctx_num);
  937. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  938. soc->wlan_cfg_ctx, intr_ctx_num);
  939. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  940. soc->wlan_cfg_ctx, intr_ctx_num);
  941. unsigned int vector =
  942. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  943. int num_irq = 0;
  944. soc->intr_mode = DP_INTR_MSI;
  945. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  946. rx_wbm_rel_ring_mask | reo_status_ring_mask)
  947. irq_id_map[num_irq++] =
  948. pld_get_msi_irq(soc->osdev->dev, vector);
  949. *num_irq_r = num_irq;
  950. }
  951. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  952. int *irq_id_map, int *num_irq)
  953. {
  954. int msi_vector_count, ret;
  955. uint32_t msi_base_data, msi_vector_start;
  956. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  957. &msi_vector_count,
  958. &msi_base_data,
  959. &msi_vector_start);
  960. if (ret)
  961. return dp_soc_interrupt_map_calculate_integrated(soc,
  962. intr_ctx_num, irq_id_map, num_irq);
  963. else
  964. dp_soc_interrupt_map_calculate_msi(soc,
  965. intr_ctx_num, irq_id_map, num_irq,
  966. msi_vector_count, msi_vector_start);
  967. }
  968. /*
  969. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  970. * @txrx_soc: DP SOC handle
  971. *
  972. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  973. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  974. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  975. *
  976. * Return: 0 for success. nonzero for failure.
  977. */
  978. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  979. {
  980. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  981. int i = 0;
  982. int num_irq = 0;
  983. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  984. int ret = 0;
  985. /* Map of IRQ ids registered with one interrupt context */
  986. int irq_id_map[HIF_MAX_GRP_IRQ];
  987. int tx_mask =
  988. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  989. int rx_mask =
  990. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  991. int rx_mon_mask =
  992. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  993. int rx_err_ring_mask =
  994. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  995. int rx_wbm_rel_ring_mask =
  996. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  997. int reo_status_ring_mask =
  998. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  999. int rxdma2host_ring_mask =
  1000. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1001. soc->intr_ctx[i].dp_intr_id = i;
  1002. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1003. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1004. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1005. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1006. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1007. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1008. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1009. soc->intr_ctx[i].soc = soc;
  1010. num_irq = 0;
  1011. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1012. &num_irq);
  1013. ret = hif_register_ext_group(soc->hif_handle,
  1014. num_irq, irq_id_map, dp_service_srngs,
  1015. &soc->intr_ctx[i], "dp_intr",
  1016. HIF_EXEC_NAPI_TYPE, 2);
  1017. if (ret) {
  1018. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1019. FL("failed, ret = %d"), ret);
  1020. return QDF_STATUS_E_FAILURE;
  1021. }
  1022. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1023. }
  1024. hif_configure_ext_group_interrupts(soc->hif_handle);
  1025. return QDF_STATUS_SUCCESS;
  1026. }
  1027. /*
  1028. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  1029. * @txrx_soc: DP SOC handle
  1030. *
  1031. * Return: void
  1032. */
  1033. static void dp_soc_interrupt_detach(void *txrx_soc)
  1034. {
  1035. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1036. int i;
  1037. if (soc->intr_mode == DP_INTR_POLL) {
  1038. qdf_timer_stop(&soc->int_timer);
  1039. qdf_timer_free(&soc->int_timer);
  1040. } else {
  1041. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1042. }
  1043. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1044. soc->intr_ctx[i].tx_ring_mask = 0;
  1045. soc->intr_ctx[i].rx_ring_mask = 0;
  1046. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1047. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1048. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1049. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1050. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1051. }
  1052. }
  1053. #define AVG_MAX_MPDUS_PER_TID 128
  1054. #define AVG_TIDS_PER_CLIENT 2
  1055. #define AVG_FLOWS_PER_TID 2
  1056. #define AVG_MSDUS_PER_FLOW 128
  1057. #define AVG_MSDUS_PER_MPDU 4
  1058. /*
  1059. * Allocate and setup link descriptor pool that will be used by HW for
  1060. * various link and queue descriptors and managed by WBM
  1061. */
  1062. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1063. {
  1064. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1065. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1066. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1067. uint32_t num_mpdus_per_link_desc =
  1068. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1069. uint32_t num_msdus_per_link_desc =
  1070. hal_num_msdus_per_link_desc(soc->hal_soc);
  1071. uint32_t num_mpdu_links_per_queue_desc =
  1072. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1073. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1074. uint32_t total_link_descs, total_mem_size;
  1075. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1076. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1077. uint32_t num_link_desc_banks;
  1078. uint32_t last_bank_size = 0;
  1079. uint32_t entry_size, num_entries;
  1080. int i;
  1081. uint32_t desc_id = 0;
  1082. /* Only Tx queue descriptors are allocated from common link descriptor
  1083. * pool Rx queue descriptors are not included in this because (REO queue
  1084. * extension descriptors) they are expected to be allocated contiguously
  1085. * with REO queue descriptors
  1086. */
  1087. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1088. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1089. num_mpdu_queue_descs = num_mpdu_link_descs /
  1090. num_mpdu_links_per_queue_desc;
  1091. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1092. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1093. num_msdus_per_link_desc;
  1094. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1095. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1096. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1097. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1098. /* Round up to power of 2 */
  1099. total_link_descs = 1;
  1100. while (total_link_descs < num_entries)
  1101. total_link_descs <<= 1;
  1102. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1103. FL("total_link_descs: %u, link_desc_size: %d"),
  1104. total_link_descs, link_desc_size);
  1105. total_mem_size = total_link_descs * link_desc_size;
  1106. total_mem_size += link_desc_align;
  1107. if (total_mem_size <= max_alloc_size) {
  1108. num_link_desc_banks = 0;
  1109. last_bank_size = total_mem_size;
  1110. } else {
  1111. num_link_desc_banks = (total_mem_size) /
  1112. (max_alloc_size - link_desc_align);
  1113. last_bank_size = total_mem_size %
  1114. (max_alloc_size - link_desc_align);
  1115. }
  1116. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1117. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1118. total_mem_size, num_link_desc_banks);
  1119. for (i = 0; i < num_link_desc_banks; i++) {
  1120. soc->link_desc_banks[i].base_vaddr_unaligned =
  1121. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1122. max_alloc_size,
  1123. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1124. soc->link_desc_banks[i].size = max_alloc_size;
  1125. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1126. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1127. ((unsigned long)(
  1128. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1129. link_desc_align));
  1130. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1131. soc->link_desc_banks[i].base_paddr_unaligned) +
  1132. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1133. (unsigned long)(
  1134. soc->link_desc_banks[i].base_vaddr_unaligned));
  1135. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1136. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1137. FL("Link descriptor memory alloc failed"));
  1138. goto fail;
  1139. }
  1140. }
  1141. if (last_bank_size) {
  1142. /* Allocate last bank in case total memory required is not exact
  1143. * multiple of max_alloc_size
  1144. */
  1145. soc->link_desc_banks[i].base_vaddr_unaligned =
  1146. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1147. last_bank_size,
  1148. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1149. soc->link_desc_banks[i].size = last_bank_size;
  1150. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1151. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1152. ((unsigned long)(
  1153. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1154. link_desc_align));
  1155. soc->link_desc_banks[i].base_paddr =
  1156. (unsigned long)(
  1157. soc->link_desc_banks[i].base_paddr_unaligned) +
  1158. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1159. (unsigned long)(
  1160. soc->link_desc_banks[i].base_vaddr_unaligned));
  1161. }
  1162. /* Allocate and setup link descriptor idle list for HW internal use */
  1163. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1164. total_mem_size = entry_size * total_link_descs;
  1165. if (total_mem_size <= max_alloc_size) {
  1166. void *desc;
  1167. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1168. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1169. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1170. FL("Link desc idle ring setup failed"));
  1171. goto fail;
  1172. }
  1173. hal_srng_access_start_unlocked(soc->hal_soc,
  1174. soc->wbm_idle_link_ring.hal_srng);
  1175. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1176. soc->link_desc_banks[i].base_paddr; i++) {
  1177. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1178. ((unsigned long)(
  1179. soc->link_desc_banks[i].base_vaddr) -
  1180. (unsigned long)(
  1181. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1182. / link_desc_size;
  1183. unsigned long paddr = (unsigned long)(
  1184. soc->link_desc_banks[i].base_paddr);
  1185. while (num_entries && (desc = hal_srng_src_get_next(
  1186. soc->hal_soc,
  1187. soc->wbm_idle_link_ring.hal_srng))) {
  1188. hal_set_link_desc_addr(desc,
  1189. LINK_DESC_COOKIE(desc_id, i), paddr);
  1190. num_entries--;
  1191. desc_id++;
  1192. paddr += link_desc_size;
  1193. }
  1194. }
  1195. hal_srng_access_end_unlocked(soc->hal_soc,
  1196. soc->wbm_idle_link_ring.hal_srng);
  1197. } else {
  1198. uint32_t num_scatter_bufs;
  1199. uint32_t num_entries_per_buf;
  1200. uint32_t rem_entries;
  1201. uint8_t *scatter_buf_ptr;
  1202. uint16_t scatter_buf_num;
  1203. soc->wbm_idle_scatter_buf_size =
  1204. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1205. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1206. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1207. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1208. soc->hal_soc, total_mem_size,
  1209. soc->wbm_idle_scatter_buf_size);
  1210. for (i = 0; i < num_scatter_bufs; i++) {
  1211. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1212. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1213. soc->wbm_idle_scatter_buf_size,
  1214. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1215. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1216. QDF_TRACE(QDF_MODULE_ID_DP,
  1217. QDF_TRACE_LEVEL_ERROR,
  1218. FL("Scatter list memory alloc failed"));
  1219. goto fail;
  1220. }
  1221. }
  1222. /* Populate idle list scatter buffers with link descriptor
  1223. * pointers
  1224. */
  1225. scatter_buf_num = 0;
  1226. scatter_buf_ptr = (uint8_t *)(
  1227. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1228. rem_entries = num_entries_per_buf;
  1229. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1230. soc->link_desc_banks[i].base_paddr; i++) {
  1231. uint32_t num_link_descs =
  1232. (soc->link_desc_banks[i].size -
  1233. ((unsigned long)(
  1234. soc->link_desc_banks[i].base_vaddr) -
  1235. (unsigned long)(
  1236. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1237. / link_desc_size;
  1238. unsigned long paddr = (unsigned long)(
  1239. soc->link_desc_banks[i].base_paddr);
  1240. while (num_link_descs) {
  1241. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1242. LINK_DESC_COOKIE(desc_id, i), paddr);
  1243. num_link_descs--;
  1244. desc_id++;
  1245. paddr += link_desc_size;
  1246. rem_entries--;
  1247. if (rem_entries) {
  1248. scatter_buf_ptr += entry_size;
  1249. } else {
  1250. rem_entries = num_entries_per_buf;
  1251. scatter_buf_num++;
  1252. if (scatter_buf_num >= num_scatter_bufs)
  1253. break;
  1254. scatter_buf_ptr = (uint8_t *)(
  1255. soc->wbm_idle_scatter_buf_base_vaddr[
  1256. scatter_buf_num]);
  1257. }
  1258. }
  1259. }
  1260. /* Setup link descriptor idle list in HW */
  1261. hal_setup_link_idle_list(soc->hal_soc,
  1262. soc->wbm_idle_scatter_buf_base_paddr,
  1263. soc->wbm_idle_scatter_buf_base_vaddr,
  1264. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1265. (uint32_t)(scatter_buf_ptr -
  1266. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1267. scatter_buf_num-1])), total_link_descs);
  1268. }
  1269. return 0;
  1270. fail:
  1271. if (soc->wbm_idle_link_ring.hal_srng) {
  1272. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1273. WBM_IDLE_LINK, 0);
  1274. }
  1275. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1276. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1277. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1278. soc->wbm_idle_scatter_buf_size,
  1279. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1280. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1281. }
  1282. }
  1283. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1284. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1285. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1286. soc->link_desc_banks[i].size,
  1287. soc->link_desc_banks[i].base_vaddr_unaligned,
  1288. soc->link_desc_banks[i].base_paddr_unaligned,
  1289. 0);
  1290. }
  1291. }
  1292. return QDF_STATUS_E_FAILURE;
  1293. }
  1294. /*
  1295. * Free link descriptor pool that was setup HW
  1296. */
  1297. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1298. {
  1299. int i;
  1300. if (soc->wbm_idle_link_ring.hal_srng) {
  1301. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1302. WBM_IDLE_LINK, 0);
  1303. }
  1304. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1305. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1306. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1307. soc->wbm_idle_scatter_buf_size,
  1308. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1309. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1310. }
  1311. }
  1312. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1313. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1314. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1315. soc->link_desc_banks[i].size,
  1316. soc->link_desc_banks[i].base_vaddr_unaligned,
  1317. soc->link_desc_banks[i].base_paddr_unaligned,
  1318. 0);
  1319. }
  1320. }
  1321. }
  1322. /* TODO: Following should be configurable */
  1323. #define WBM_RELEASE_RING_SIZE 64
  1324. #define TCL_CMD_RING_SIZE 32
  1325. #define TCL_STATUS_RING_SIZE 32
  1326. #if defined(QCA_WIFI_QCA6290)
  1327. #define REO_DST_RING_SIZE 1024
  1328. #else
  1329. #define REO_DST_RING_SIZE 2048
  1330. #endif
  1331. #define REO_REINJECT_RING_SIZE 32
  1332. #define RX_RELEASE_RING_SIZE 1024
  1333. #define REO_EXCEPTION_RING_SIZE 128
  1334. #define REO_CMD_RING_SIZE 32
  1335. #define REO_STATUS_RING_SIZE 32
  1336. #define RXDMA_BUF_RING_SIZE 1024
  1337. #define RXDMA_REFILL_RING_SIZE 2048
  1338. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1339. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1340. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1341. #define RXDMA_MONITOR_DESC_RING_SIZE 2048
  1342. #define RXDMA_ERR_DST_RING_SIZE 1024
  1343. /*
  1344. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1345. * @soc: Datapath SOC handle
  1346. *
  1347. * This is a timer function used to age out stale WDS nodes from
  1348. * AST table
  1349. */
  1350. #ifdef FEATURE_WDS
  1351. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1352. {
  1353. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1354. struct dp_pdev *pdev;
  1355. struct dp_vdev *vdev;
  1356. struct dp_peer *peer;
  1357. struct dp_ast_entry *ase, *temp_ase;
  1358. int i;
  1359. qdf_spin_lock_bh(&soc->ast_lock);
  1360. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1361. pdev = soc->pdev_list[i];
  1362. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1363. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1364. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1365. /*
  1366. * Do not expire static ast entries
  1367. */
  1368. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1369. continue;
  1370. if (ase->is_active) {
  1371. ase->is_active = FALSE;
  1372. continue;
  1373. }
  1374. DP_STATS_INC(soc, ast.aged_out, 1);
  1375. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1376. pdev->osif_pdev,
  1377. ase->mac_addr.raw);
  1378. dp_peer_del_ast(soc, ase);
  1379. }
  1380. }
  1381. }
  1382. }
  1383. qdf_spin_unlock_bh(&soc->ast_lock);
  1384. if (qdf_atomic_read(&soc->cmn_init_done))
  1385. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1386. }
  1387. /*
  1388. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1389. * @soc: Datapath SOC handle
  1390. *
  1391. * Return: None
  1392. */
  1393. static void dp_soc_wds_attach(struct dp_soc *soc)
  1394. {
  1395. qdf_spinlock_create(&soc->ast_lock);
  1396. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1397. dp_wds_aging_timer_fn, (void *)soc,
  1398. QDF_TIMER_TYPE_WAKE_APPS);
  1399. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1400. }
  1401. /*
  1402. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1403. * @txrx_soc: DP SOC handle
  1404. *
  1405. * Return: None
  1406. */
  1407. static void dp_soc_wds_detach(struct dp_soc *soc)
  1408. {
  1409. qdf_timer_stop(&soc->wds_aging_timer);
  1410. qdf_timer_free(&soc->wds_aging_timer);
  1411. qdf_spinlock_destroy(&soc->ast_lock);
  1412. }
  1413. #else
  1414. static void dp_soc_wds_attach(struct dp_soc *soc)
  1415. {
  1416. }
  1417. static void dp_soc_wds_detach(struct dp_soc *soc)
  1418. {
  1419. }
  1420. #endif
  1421. /*
  1422. * dp_soc_reset_ring_map() - Reset cpu ring map
  1423. * @soc: Datapath soc handler
  1424. *
  1425. * This api resets the default cpu ring map
  1426. */
  1427. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1428. {
  1429. uint8_t i;
  1430. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1431. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1432. if (nss_config == 1) {
  1433. /*
  1434. * Setting Tx ring map for one nss offloaded radio
  1435. */
  1436. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1437. } else if (nss_config == 2) {
  1438. /*
  1439. * Setting Tx ring for two nss offloaded radios
  1440. */
  1441. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1442. } else {
  1443. /*
  1444. * Setting Tx ring map for all nss offloaded radios
  1445. */
  1446. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1447. }
  1448. }
  1449. }
  1450. #ifdef IPA_OFFLOAD
  1451. /**
  1452. * dp_reo_remap_config() - configure reo remap register value based
  1453. * nss configuration.
  1454. * based on offload_radio value below remap configuration
  1455. * get applied.
  1456. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1457. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1458. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1459. * 3 - both Radios handled by NSS (remap not required)
  1460. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1461. *
  1462. * @remap1: output parameter indicates reo remap 1 register value
  1463. * @remap2: output parameter indicates reo remap 2 register value
  1464. * Return: bool type, true if remap is configured else false.
  1465. */
  1466. static bool dp_reo_remap_config(struct dp_soc *soc,
  1467. uint32_t *remap1,
  1468. uint32_t *remap2)
  1469. {
  1470. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1471. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1472. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1473. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1474. return true;
  1475. }
  1476. #else
  1477. static bool dp_reo_remap_config(struct dp_soc *soc,
  1478. uint32_t *remap1,
  1479. uint32_t *remap2)
  1480. {
  1481. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1482. switch (offload_radio) {
  1483. case 0:
  1484. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1485. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1486. (0x3 << 18) | (0x4 << 21)) << 8;
  1487. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1488. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1489. (0x3 << 18) | (0x4 << 21)) << 8;
  1490. break;
  1491. case 1:
  1492. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1493. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1494. (0x2 << 18) | (0x3 << 21)) << 8;
  1495. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1496. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1497. (0x4 << 18) | (0x2 << 21)) << 8;
  1498. break;
  1499. case 2:
  1500. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1501. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1502. (0x1 << 18) | (0x3 << 21)) << 8;
  1503. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1504. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1505. (0x4 << 18) | (0x1 << 21)) << 8;
  1506. break;
  1507. case 3:
  1508. /* return false if both radios are offloaded to NSS */
  1509. return false;
  1510. }
  1511. return true;
  1512. }
  1513. #endif
  1514. /*
  1515. * dp_soc_cmn_setup() - Common SoC level initializion
  1516. * @soc: Datapath SOC handle
  1517. *
  1518. * This is an internal function used to setup common SOC data structures,
  1519. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1520. */
  1521. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1522. {
  1523. int i;
  1524. struct hal_reo_params reo_params;
  1525. int tx_ring_size;
  1526. int tx_comp_ring_size;
  1527. if (qdf_atomic_read(&soc->cmn_init_done))
  1528. return 0;
  1529. if (dp_peer_find_attach(soc))
  1530. goto fail0;
  1531. if (dp_hw_link_desc_pool_setup(soc))
  1532. goto fail1;
  1533. /* Setup SRNG rings */
  1534. /* Common rings */
  1535. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1536. WBM_RELEASE_RING_SIZE)) {
  1537. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1538. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1539. goto fail1;
  1540. }
  1541. soc->num_tcl_data_rings = 0;
  1542. /* Tx data rings */
  1543. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1544. soc->num_tcl_data_rings =
  1545. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1546. tx_comp_ring_size =
  1547. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1548. tx_ring_size =
  1549. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1550. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1551. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1552. TCL_DATA, i, 0, tx_ring_size)) {
  1553. QDF_TRACE(QDF_MODULE_ID_DP,
  1554. QDF_TRACE_LEVEL_ERROR,
  1555. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1556. goto fail1;
  1557. }
  1558. /*
  1559. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1560. * count
  1561. */
  1562. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1563. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1564. QDF_TRACE(QDF_MODULE_ID_DP,
  1565. QDF_TRACE_LEVEL_ERROR,
  1566. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1567. goto fail1;
  1568. }
  1569. }
  1570. } else {
  1571. /* This will be incremented during per pdev ring setup */
  1572. soc->num_tcl_data_rings = 0;
  1573. }
  1574. if (dp_tx_soc_attach(soc)) {
  1575. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1576. FL("dp_tx_soc_attach failed"));
  1577. goto fail1;
  1578. }
  1579. /* TCL command and status rings */
  1580. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1581. TCL_CMD_RING_SIZE)) {
  1582. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1583. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1584. goto fail1;
  1585. }
  1586. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1587. TCL_STATUS_RING_SIZE)) {
  1588. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1589. FL("dp_srng_setup failed for tcl_status_ring"));
  1590. goto fail1;
  1591. }
  1592. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1593. * descriptors
  1594. */
  1595. /* Rx data rings */
  1596. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1597. soc->num_reo_dest_rings =
  1598. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1599. QDF_TRACE(QDF_MODULE_ID_DP,
  1600. QDF_TRACE_LEVEL_ERROR,
  1601. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1602. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1603. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1604. i, 0, REO_DST_RING_SIZE)) {
  1605. QDF_TRACE(QDF_MODULE_ID_DP,
  1606. QDF_TRACE_LEVEL_ERROR,
  1607. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1608. goto fail1;
  1609. }
  1610. }
  1611. } else {
  1612. /* This will be incremented during per pdev ring setup */
  1613. soc->num_reo_dest_rings = 0;
  1614. }
  1615. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1616. /* REO reinjection ring */
  1617. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1618. REO_REINJECT_RING_SIZE)) {
  1619. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1620. FL("dp_srng_setup failed for reo_reinject_ring"));
  1621. goto fail1;
  1622. }
  1623. /* Rx release ring */
  1624. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1625. RX_RELEASE_RING_SIZE)) {
  1626. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1627. FL("dp_srng_setup failed for rx_rel_ring"));
  1628. goto fail1;
  1629. }
  1630. /* Rx exception ring */
  1631. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1632. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1633. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1634. FL("dp_srng_setup failed for reo_exception_ring"));
  1635. goto fail1;
  1636. }
  1637. /* REO command and status rings */
  1638. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1639. REO_CMD_RING_SIZE)) {
  1640. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1641. FL("dp_srng_setup failed for reo_cmd_ring"));
  1642. goto fail1;
  1643. }
  1644. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1645. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1646. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1647. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1648. REO_STATUS_RING_SIZE)) {
  1649. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1650. FL("dp_srng_setup failed for reo_status_ring"));
  1651. goto fail1;
  1652. }
  1653. dp_soc_wds_attach(soc);
  1654. /* Reset the cpu ring map if radio is NSS offloaded */
  1655. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1656. dp_soc_reset_cpu_ring_map(soc);
  1657. }
  1658. /* Setup HW REO */
  1659. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1660. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1661. /*
  1662. * Reo ring remap is not required if both radios
  1663. * are offloaded to NSS
  1664. */
  1665. if (!dp_reo_remap_config(soc,
  1666. &reo_params.remap1,
  1667. &reo_params.remap2))
  1668. goto out;
  1669. reo_params.rx_hash_enabled = true;
  1670. }
  1671. out:
  1672. hal_reo_setup(soc->hal_soc, &reo_params);
  1673. qdf_atomic_set(&soc->cmn_init_done, 1);
  1674. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1675. return 0;
  1676. fail1:
  1677. /*
  1678. * Cleanup will be done as part of soc_detach, which will
  1679. * be called on pdev attach failure
  1680. */
  1681. fail0:
  1682. return QDF_STATUS_E_FAILURE;
  1683. }
  1684. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1685. static void dp_lro_hash_setup(struct dp_soc *soc)
  1686. {
  1687. struct cdp_lro_hash_config lro_hash;
  1688. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1689. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1690. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1691. FL("LRO disabled RX hash disabled"));
  1692. return;
  1693. }
  1694. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1695. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1696. lro_hash.lro_enable = 1;
  1697. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1698. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1699. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1700. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1701. }
  1702. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  1703. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1704. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1705. LRO_IPV4_SEED_ARR_SZ));
  1706. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1707. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1708. LRO_IPV6_SEED_ARR_SZ));
  1709. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1710. "lro_hash: lro_enable: 0x%x"
  1711. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  1712. lro_hash.lro_enable, lro_hash.tcp_flag,
  1713. lro_hash.tcp_flag_mask);
  1714. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1715. FL("lro_hash: toeplitz_hash_ipv4:"));
  1716. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1717. QDF_TRACE_LEVEL_ERROR,
  1718. (void *)lro_hash.toeplitz_hash_ipv4,
  1719. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1720. LRO_IPV4_SEED_ARR_SZ));
  1721. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1722. FL("lro_hash: toeplitz_hash_ipv6:"));
  1723. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1724. QDF_TRACE_LEVEL_ERROR,
  1725. (void *)lro_hash.toeplitz_hash_ipv6,
  1726. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1727. LRO_IPV6_SEED_ARR_SZ));
  1728. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1729. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1730. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1731. (soc->osif_soc, &lro_hash);
  1732. }
  1733. /*
  1734. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1735. * @soc: data path SoC handle
  1736. * @pdev: Physical device handle
  1737. *
  1738. * Return: 0 - success, > 0 - failure
  1739. */
  1740. #ifdef QCA_HOST2FW_RXBUF_RING
  1741. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1742. struct dp_pdev *pdev)
  1743. {
  1744. int max_mac_rings =
  1745. wlan_cfg_get_num_mac_rings
  1746. (pdev->wlan_cfg_ctx);
  1747. int i;
  1748. for (i = 0; i < max_mac_rings; i++) {
  1749. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1750. "%s: pdev_id %d mac_id %d\n",
  1751. __func__, pdev->pdev_id, i);
  1752. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1753. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1754. QDF_TRACE(QDF_MODULE_ID_DP,
  1755. QDF_TRACE_LEVEL_ERROR,
  1756. FL("failed rx mac ring setup"));
  1757. return QDF_STATUS_E_FAILURE;
  1758. }
  1759. }
  1760. return QDF_STATUS_SUCCESS;
  1761. }
  1762. #else
  1763. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1764. struct dp_pdev *pdev)
  1765. {
  1766. return QDF_STATUS_SUCCESS;
  1767. }
  1768. #endif
  1769. /**
  1770. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1771. * @pdev - DP_PDEV handle
  1772. *
  1773. * Return: void
  1774. */
  1775. static inline void
  1776. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1777. {
  1778. uint8_t map_id;
  1779. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1780. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1781. sizeof(default_dscp_tid_map));
  1782. }
  1783. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1784. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1785. pdev->dscp_tid_map[map_id],
  1786. map_id);
  1787. }
  1788. }
  1789. /*
  1790. * dp_reset_intr_mask() - reset interrupt mask
  1791. * @dp_soc - DP Soc handle
  1792. * @dp_pdev - DP pdev handle
  1793. *
  1794. * Return: Return void
  1795. */
  1796. static inline
  1797. void dp_soc_reset_intr_mask(struct dp_soc *soc, struct dp_pdev *pdev)
  1798. {
  1799. /*
  1800. * We will set the interrupt mask to zero for NSS offloaded radio
  1801. */
  1802. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1803. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1804. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1805. }
  1806. /*
  1807. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1808. * @soc: data path SoC handle
  1809. *
  1810. * Return: none
  1811. */
  1812. #ifdef IPA_OFFLOAD
  1813. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1814. struct dp_pdev *pdev)
  1815. {
  1816. void *hal_srng;
  1817. struct hal_srng_params srng_params;
  1818. qdf_dma_addr_t hp_addr, tp_addr;
  1819. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1820. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1821. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1822. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1823. srng_params.ring_base_paddr;
  1824. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1825. srng_params.ring_base_vaddr;
  1826. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1827. srng_params.num_entries * srng_params.entry_size;
  1828. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1829. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1830. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1831. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1832. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1833. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1834. srng_params.ring_base_paddr;
  1835. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1836. srng_params.ring_base_vaddr;
  1837. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1838. srng_params.num_entries * srng_params.entry_size;
  1839. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1840. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1841. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1842. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1843. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1844. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1845. srng_params.ring_base_paddr;
  1846. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1847. srng_params.ring_base_vaddr;
  1848. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1849. srng_params.num_entries * srng_params.entry_size;
  1850. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1851. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1852. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1853. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1854. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1855. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1856. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1857. __func__);
  1858. return -EFAULT;
  1859. }
  1860. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1861. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1862. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1863. srng_params.ring_base_paddr;
  1864. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1865. srng_params.ring_base_vaddr;
  1866. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1867. srng_params.num_entries * srng_params.entry_size;
  1868. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1869. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1870. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1871. "%s: ring_base_paddr:%pK, ring_base_vaddr:%pK"
  1872. "_entries:%d, hp_addr:%pK\n",
  1873. __func__,
  1874. (void *)srng_params.ring_base_paddr,
  1875. (void *)srng_params.ring_base_vaddr,
  1876. srng_params.num_entries,
  1877. (void *)hp_addr);
  1878. return 0;
  1879. }
  1880. #else
  1881. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1882. struct dp_pdev *pdev)
  1883. {
  1884. return 0;
  1885. }
  1886. #endif
  1887. /*
  1888. * dp_pdev_attach_wifi3() - attach txrx pdev
  1889. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1890. * @txrx_soc: Datapath SOC handle
  1891. * @htc_handle: HTC handle for host-target interface
  1892. * @qdf_osdev: QDF OS device
  1893. * @pdev_id: PDEV ID
  1894. *
  1895. * Return: DP PDEV handle on success, NULL on failure
  1896. */
  1897. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1898. struct cdp_cfg *ctrl_pdev,
  1899. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1900. {
  1901. int tx_ring_size;
  1902. int tx_comp_ring_size;
  1903. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1904. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1905. if (!pdev) {
  1906. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1907. FL("DP PDEV memory allocation failed"));
  1908. goto fail0;
  1909. }
  1910. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1911. if (!pdev->wlan_cfg_ctx) {
  1912. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1913. FL("pdev cfg_attach failed"));
  1914. qdf_mem_free(pdev);
  1915. goto fail0;
  1916. }
  1917. /*
  1918. * set nss pdev config based on soc config
  1919. */
  1920. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1921. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1922. pdev->soc = soc;
  1923. pdev->osif_pdev = ctrl_pdev;
  1924. pdev->pdev_id = pdev_id;
  1925. soc->pdev_list[pdev_id] = pdev;
  1926. soc->pdev_count++;
  1927. TAILQ_INIT(&pdev->vdev_list);
  1928. pdev->vdev_count = 0;
  1929. qdf_spinlock_create(&pdev->tx_mutex);
  1930. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1931. TAILQ_INIT(&pdev->neighbour_peers_list);
  1932. if (dp_soc_cmn_setup(soc)) {
  1933. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1934. FL("dp_soc_cmn_setup failed"));
  1935. goto fail1;
  1936. }
  1937. /* Setup per PDEV TCL rings if configured */
  1938. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1939. tx_ring_size =
  1940. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1941. tx_comp_ring_size =
  1942. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1943. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1944. pdev_id, pdev_id, tx_ring_size)) {
  1945. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1946. FL("dp_srng_setup failed for tcl_data_ring"));
  1947. goto fail1;
  1948. }
  1949. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1950. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1951. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1952. FL("dp_srng_setup failed for tx_comp_ring"));
  1953. goto fail1;
  1954. }
  1955. soc->num_tcl_data_rings++;
  1956. }
  1957. /* Tx specific init */
  1958. if (dp_tx_pdev_attach(pdev)) {
  1959. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1960. FL("dp_tx_pdev_attach failed"));
  1961. goto fail1;
  1962. }
  1963. /* Setup per PDEV REO rings if configured */
  1964. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1965. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1966. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1967. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1968. FL("dp_srng_setup failed for reo_dest_ringn"));
  1969. goto fail1;
  1970. }
  1971. soc->num_reo_dest_rings++;
  1972. }
  1973. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1974. RXDMA_REFILL_RING_SIZE)) {
  1975. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1976. FL("dp_srng_setup failed rx refill ring"));
  1977. goto fail1;
  1978. }
  1979. if (dp_rxdma_ring_setup(soc, pdev)) {
  1980. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1981. FL("RXDMA ring config failed"));
  1982. goto fail1;
  1983. }
  1984. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1985. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1986. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1987. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1988. goto fail1;
  1989. }
  1990. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1991. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1992. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1993. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1994. goto fail1;
  1995. }
  1996. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  1997. RXDMA_MONITOR_STATUS, 0, pdev_id,
  1998. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  1999. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2000. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  2001. goto fail1;
  2002. }
  2003. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  2004. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  2005. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2006. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  2007. goto fail1;
  2008. }
  2009. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  2010. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  2011. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2012. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2013. goto fail1;
  2014. }
  2015. if (dp_ipa_ring_resource_setup(soc, pdev))
  2016. goto fail1;
  2017. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  2018. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2019. "%s: dp_ipa_uc_attach failed\n", __func__);
  2020. goto fail1;
  2021. }
  2022. /* Rx specific init */
  2023. if (dp_rx_pdev_attach(pdev)) {
  2024. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2025. FL("dp_rx_pdev_attach failed "));
  2026. goto fail0;
  2027. }
  2028. DP_STATS_INIT(pdev);
  2029. #ifndef CONFIG_WIN
  2030. /* MCL */
  2031. dp_local_peer_id_pool_init(pdev);
  2032. #endif
  2033. dp_dscp_tid_map_setup(pdev);
  2034. /* Rx monitor mode specific init */
  2035. if (dp_rx_pdev_mon_attach(pdev)) {
  2036. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2037. "dp_rx_pdev_attach failed\n");
  2038. goto fail1;
  2039. }
  2040. if (dp_wdi_event_attach(pdev)) {
  2041. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2042. "dp_wdi_evet_attach failed\n");
  2043. goto fail1;
  2044. }
  2045. /* set the reo destination during initialization */
  2046. pdev->reo_dest = pdev->pdev_id + 1;
  2047. /*
  2048. * reset the interrupt mask for offloaded radio
  2049. */
  2050. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  2051. dp_soc_reset_intr_mask(soc, pdev);
  2052. }
  2053. return (struct cdp_pdev *)pdev;
  2054. fail1:
  2055. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2056. fail0:
  2057. return NULL;
  2058. }
  2059. /*
  2060. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2061. * @soc: data path SoC handle
  2062. * @pdev: Physical device handle
  2063. *
  2064. * Return: void
  2065. */
  2066. #ifdef QCA_HOST2FW_RXBUF_RING
  2067. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2068. struct dp_pdev *pdev)
  2069. {
  2070. int max_mac_rings =
  2071. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2072. int i;
  2073. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2074. max_mac_rings : MAX_RX_MAC_RINGS;
  2075. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2076. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2077. RXDMA_BUF, 1);
  2078. }
  2079. #else
  2080. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2081. struct dp_pdev *pdev)
  2082. {
  2083. }
  2084. #endif
  2085. /*
  2086. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2087. * @pdev: device object
  2088. *
  2089. * Return: void
  2090. */
  2091. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2092. {
  2093. struct dp_neighbour_peer *peer = NULL;
  2094. struct dp_neighbour_peer *temp_peer = NULL;
  2095. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2096. neighbour_peer_list_elem, temp_peer) {
  2097. /* delete this peer from the list */
  2098. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2099. peer, neighbour_peer_list_elem);
  2100. qdf_mem_free(peer);
  2101. }
  2102. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2103. }
  2104. /*
  2105. * dp_pdev_detach_wifi3() - detach txrx pdev
  2106. * @txrx_pdev: Datapath PDEV handle
  2107. * @force: Force detach
  2108. *
  2109. */
  2110. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2111. {
  2112. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2113. struct dp_soc *soc = pdev->soc;
  2114. dp_wdi_event_detach(pdev);
  2115. dp_tx_pdev_detach(pdev);
  2116. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2117. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2118. TCL_DATA, pdev->pdev_id);
  2119. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2120. WBM2SW_RELEASE, pdev->pdev_id);
  2121. }
  2122. dp_rx_pdev_detach(pdev);
  2123. dp_rx_pdev_mon_detach(pdev);
  2124. dp_neighbour_peers_detach(pdev);
  2125. qdf_spinlock_destroy(&pdev->tx_mutex);
  2126. dp_ipa_uc_detach(soc, pdev);
  2127. /* Cleanup per PDEV REO rings if configured */
  2128. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2129. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2130. REO_DST, pdev->pdev_id);
  2131. }
  2132. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2133. dp_rxdma_ring_cleanup(soc, pdev);
  2134. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2135. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2136. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2137. RXDMA_MONITOR_STATUS, 0);
  2138. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2139. RXDMA_MONITOR_DESC, 0);
  2140. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2141. soc->pdev_list[pdev->pdev_id] = NULL;
  2142. soc->pdev_count--;
  2143. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2144. qdf_mem_free(pdev);
  2145. }
  2146. /*
  2147. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2148. * @soc: DP SOC handle
  2149. */
  2150. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2151. {
  2152. struct reo_desc_list_node *desc;
  2153. struct dp_rx_tid *rx_tid;
  2154. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2155. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2156. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2157. rx_tid = &desc->rx_tid;
  2158. qdf_mem_unmap_nbytes_single(soc->osdev,
  2159. rx_tid->hw_qdesc_paddr,
  2160. QDF_DMA_BIDIRECTIONAL,
  2161. rx_tid->hw_qdesc_alloc_size);
  2162. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2163. qdf_mem_free(desc);
  2164. }
  2165. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2166. qdf_list_destroy(&soc->reo_desc_freelist);
  2167. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2168. }
  2169. /*
  2170. * dp_soc_detach_wifi3() - Detach txrx SOC
  2171. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2172. */
  2173. static void dp_soc_detach_wifi3(void *txrx_soc)
  2174. {
  2175. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2176. int i;
  2177. qdf_atomic_set(&soc->cmn_init_done, 0);
  2178. qdf_flush_work(0, &soc->htt_stats.work);
  2179. qdf_disable_work(0, &soc->htt_stats.work);
  2180. /* Free pending htt stats messages */
  2181. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2182. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2183. if (soc->pdev_list[i])
  2184. dp_pdev_detach_wifi3(
  2185. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2186. }
  2187. dp_peer_find_detach(soc);
  2188. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2189. * SW descriptors
  2190. */
  2191. /* Free the ring memories */
  2192. /* Common rings */
  2193. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2194. dp_tx_soc_detach(soc);
  2195. /* Tx data rings */
  2196. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2197. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2198. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2199. TCL_DATA, i);
  2200. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2201. WBM2SW_RELEASE, i);
  2202. }
  2203. }
  2204. /* TCL command and status rings */
  2205. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2206. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2207. /* Rx data rings */
  2208. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2209. soc->num_reo_dest_rings =
  2210. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2211. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2212. /* TODO: Get number of rings and ring sizes
  2213. * from wlan_cfg
  2214. */
  2215. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2216. REO_DST, i);
  2217. }
  2218. }
  2219. /* REO reinjection ring */
  2220. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2221. /* Rx release ring */
  2222. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2223. /* Rx exception ring */
  2224. /* TODO: Better to store ring_type and ring_num in
  2225. * dp_srng during setup
  2226. */
  2227. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2228. /* REO command and status rings */
  2229. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2230. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2231. dp_hw_link_desc_pool_cleanup(soc);
  2232. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2233. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2234. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2235. htt_soc_detach(soc->htt_handle);
  2236. dp_reo_cmdlist_destroy(soc);
  2237. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2238. dp_reo_desc_freelist_destroy(soc);
  2239. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2240. dp_soc_wds_detach(soc);
  2241. qdf_mem_free(soc);
  2242. }
  2243. /*
  2244. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2245. * @soc: data path SoC handle
  2246. * @pdev: physical device handle
  2247. *
  2248. * Return: void
  2249. */
  2250. #ifdef IPA_OFFLOAD
  2251. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2252. struct dp_pdev *pdev)
  2253. {
  2254. htt_srng_setup(soc->htt_handle, 0,
  2255. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2256. }
  2257. #else
  2258. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2259. struct dp_pdev *pdev)
  2260. {
  2261. }
  2262. #endif
  2263. /*
  2264. * dp_rxdma_ring_config() - configure the RX DMA rings
  2265. *
  2266. * This function is used to configure the MAC rings.
  2267. * On MCL host provides buffers in Host2FW ring
  2268. * FW refills (copies) buffers to the ring and updates
  2269. * ring_idx in register
  2270. *
  2271. * @soc: data path SoC handle
  2272. *
  2273. * Return: void
  2274. */
  2275. #ifdef QCA_HOST2FW_RXBUF_RING
  2276. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2277. {
  2278. int i;
  2279. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2280. struct dp_pdev *pdev = soc->pdev_list[i];
  2281. if (pdev) {
  2282. int mac_id = 0;
  2283. int j;
  2284. bool dbs_enable = 0;
  2285. int max_mac_rings =
  2286. wlan_cfg_get_num_mac_rings
  2287. (pdev->wlan_cfg_ctx);
  2288. htt_srng_setup(soc->htt_handle, 0,
  2289. pdev->rx_refill_buf_ring.hal_srng,
  2290. RXDMA_BUF);
  2291. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2292. if (soc->cdp_soc.ol_ops->
  2293. is_hw_dbs_2x2_capable) {
  2294. dbs_enable = soc->cdp_soc.ol_ops->
  2295. is_hw_dbs_2x2_capable(soc->psoc);
  2296. }
  2297. if (dbs_enable) {
  2298. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2299. QDF_TRACE_LEVEL_ERROR,
  2300. FL("DBS enabled max_mac_rings %d\n"),
  2301. max_mac_rings);
  2302. } else {
  2303. max_mac_rings = 1;
  2304. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2305. QDF_TRACE_LEVEL_ERROR,
  2306. FL("DBS disabled, max_mac_rings %d\n"),
  2307. max_mac_rings);
  2308. }
  2309. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2310. FL("pdev_id %d max_mac_rings %d\n"),
  2311. pdev->pdev_id, max_mac_rings);
  2312. for (j = 0; j < max_mac_rings; j++) {
  2313. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2314. QDF_TRACE_LEVEL_ERROR,
  2315. FL("mac_id %d\n"), mac_id);
  2316. htt_srng_setup(soc->htt_handle, mac_id,
  2317. pdev->rx_mac_buf_ring[j]
  2318. .hal_srng,
  2319. RXDMA_BUF);
  2320. mac_id++;
  2321. }
  2322. /* Configure monitor mode rings */
  2323. htt_srng_setup(soc->htt_handle, i,
  2324. pdev->rxdma_mon_buf_ring.hal_srng,
  2325. RXDMA_MONITOR_BUF);
  2326. htt_srng_setup(soc->htt_handle, i,
  2327. pdev->rxdma_mon_dst_ring.hal_srng,
  2328. RXDMA_MONITOR_DST);
  2329. htt_srng_setup(soc->htt_handle, i,
  2330. pdev->rxdma_mon_status_ring.hal_srng,
  2331. RXDMA_MONITOR_STATUS);
  2332. htt_srng_setup(soc->htt_handle, i,
  2333. pdev->rxdma_mon_desc_ring.hal_srng,
  2334. RXDMA_MONITOR_DESC);
  2335. htt_srng_setup(soc->htt_handle, i,
  2336. pdev->rxdma_err_dst_ring.hal_srng,
  2337. RXDMA_DST);
  2338. }
  2339. }
  2340. }
  2341. #else
  2342. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2343. {
  2344. int i;
  2345. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2346. struct dp_pdev *pdev = soc->pdev_list[i];
  2347. if (pdev) {
  2348. htt_srng_setup(soc->htt_handle, i,
  2349. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2350. htt_srng_setup(soc->htt_handle, i,
  2351. pdev->rxdma_mon_buf_ring.hal_srng,
  2352. RXDMA_MONITOR_BUF);
  2353. htt_srng_setup(soc->htt_handle, i,
  2354. pdev->rxdma_mon_dst_ring.hal_srng,
  2355. RXDMA_MONITOR_DST);
  2356. htt_srng_setup(soc->htt_handle, i,
  2357. pdev->rxdma_mon_status_ring.hal_srng,
  2358. RXDMA_MONITOR_STATUS);
  2359. htt_srng_setup(soc->htt_handle, i,
  2360. pdev->rxdma_mon_desc_ring.hal_srng,
  2361. RXDMA_MONITOR_DESC);
  2362. htt_srng_setup(soc->htt_handle, i,
  2363. pdev->rxdma_err_dst_ring.hal_srng,
  2364. RXDMA_DST);
  2365. }
  2366. }
  2367. }
  2368. #endif
  2369. /*
  2370. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2371. * @txrx_soc: Datapath SOC handle
  2372. */
  2373. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2374. {
  2375. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2376. htt_soc_attach_target(soc->htt_handle);
  2377. dp_rxdma_ring_config(soc);
  2378. DP_STATS_INIT(soc);
  2379. /* initialize work queue for stats processing */
  2380. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2381. return 0;
  2382. }
  2383. /*
  2384. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2385. * @txrx_soc: Datapath SOC handle
  2386. */
  2387. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2388. {
  2389. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2390. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2391. }
  2392. /*
  2393. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2394. * @txrx_soc: Datapath SOC handle
  2395. * @nss_cfg: nss config
  2396. */
  2397. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2398. {
  2399. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2400. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2401. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2402. FL("nss-wifi<0> nss config is enabled"));
  2403. }
  2404. /*
  2405. * dp_vdev_attach_wifi3() - attach txrx vdev
  2406. * @txrx_pdev: Datapath PDEV handle
  2407. * @vdev_mac_addr: MAC address of the virtual interface
  2408. * @vdev_id: VDEV Id
  2409. * @wlan_op_mode: VDEV operating mode
  2410. *
  2411. * Return: DP VDEV handle on success, NULL on failure
  2412. */
  2413. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2414. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2415. {
  2416. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2417. struct dp_soc *soc = pdev->soc;
  2418. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2419. int tx_ring_size;
  2420. if (!vdev) {
  2421. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2422. FL("DP VDEV memory allocation failed"));
  2423. goto fail0;
  2424. }
  2425. vdev->pdev = pdev;
  2426. vdev->vdev_id = vdev_id;
  2427. vdev->opmode = op_mode;
  2428. vdev->osdev = soc->osdev;
  2429. vdev->osif_rx = NULL;
  2430. vdev->osif_rsim_rx_decap = NULL;
  2431. vdev->osif_get_key = NULL;
  2432. vdev->osif_rx_mon = NULL;
  2433. vdev->osif_tx_free_ext = NULL;
  2434. vdev->osif_vdev = NULL;
  2435. vdev->delete.pending = 0;
  2436. vdev->safemode = 0;
  2437. vdev->drop_unenc = 1;
  2438. #ifdef notyet
  2439. vdev->filters_num = 0;
  2440. #endif
  2441. qdf_mem_copy(
  2442. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2443. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2444. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2445. vdev->dscp_tid_map_id = 0;
  2446. vdev->mcast_enhancement_en = 0;
  2447. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2448. /* TODO: Initialize default HTT meta data that will be used in
  2449. * TCL descriptors for packets transmitted from this VDEV
  2450. */
  2451. TAILQ_INIT(&vdev->peer_list);
  2452. /* add this vdev into the pdev's list */
  2453. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2454. pdev->vdev_count++;
  2455. dp_tx_vdev_attach(vdev);
  2456. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2457. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2458. goto fail1;
  2459. if ((soc->intr_mode == DP_INTR_POLL) &&
  2460. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2461. if (pdev->vdev_count == 1)
  2462. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2463. }
  2464. dp_lro_hash_setup(soc);
  2465. /* LRO */
  2466. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2467. wlan_op_mode_sta == vdev->opmode)
  2468. vdev->lro_enable = true;
  2469. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2470. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2471. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2472. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2473. DP_STATS_INIT(vdev);
  2474. return (struct cdp_vdev *)vdev;
  2475. fail1:
  2476. dp_tx_vdev_detach(vdev);
  2477. qdf_mem_free(vdev);
  2478. fail0:
  2479. return NULL;
  2480. }
  2481. /**
  2482. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2483. * @vdev: Datapath VDEV handle
  2484. * @osif_vdev: OSIF vdev handle
  2485. * @txrx_ops: Tx and Rx operations
  2486. *
  2487. * Return: DP VDEV handle on success, NULL on failure
  2488. */
  2489. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2490. void *osif_vdev,
  2491. struct ol_txrx_ops *txrx_ops)
  2492. {
  2493. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2494. vdev->osif_vdev = osif_vdev;
  2495. vdev->osif_rx = txrx_ops->rx.rx;
  2496. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2497. vdev->osif_get_key = txrx_ops->get_key;
  2498. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2499. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2500. #ifdef notyet
  2501. #if ATH_SUPPORT_WAPI
  2502. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2503. #endif
  2504. #endif
  2505. #ifdef UMAC_SUPPORT_PROXY_ARP
  2506. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2507. #endif
  2508. vdev->me_convert = txrx_ops->me_convert;
  2509. /* TODO: Enable the following once Tx code is integrated */
  2510. txrx_ops->tx.tx = dp_tx_send;
  2511. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2512. "DP Vdev Register success");
  2513. }
  2514. /*
  2515. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2516. * @txrx_vdev: Datapath VDEV handle
  2517. * @callback: Callback OL_IF on completion of detach
  2518. * @cb_context: Callback context
  2519. *
  2520. */
  2521. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2522. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2523. {
  2524. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2525. struct dp_pdev *pdev = vdev->pdev;
  2526. struct dp_soc *soc = pdev->soc;
  2527. /* preconditions */
  2528. qdf_assert(vdev);
  2529. /* remove the vdev from its parent pdev's list */
  2530. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2531. /*
  2532. * Use peer_ref_mutex while accessing peer_list, in case
  2533. * a peer is in the process of being removed from the list.
  2534. */
  2535. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2536. /* check that the vdev has no peers allocated */
  2537. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2538. /* debug print - will be removed later */
  2539. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2540. FL("not deleting vdev object %pK (%pM)"
  2541. "until deletion finishes for all its peers"),
  2542. vdev, vdev->mac_addr.raw);
  2543. /* indicate that the vdev needs to be deleted */
  2544. vdev->delete.pending = 1;
  2545. vdev->delete.callback = callback;
  2546. vdev->delete.context = cb_context;
  2547. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2548. return;
  2549. }
  2550. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2551. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2552. vdev->vdev_id);
  2553. dp_tx_vdev_detach(vdev);
  2554. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2555. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  2556. qdf_mem_free(vdev);
  2557. if (callback)
  2558. callback(cb_context);
  2559. }
  2560. /*
  2561. * dp_peer_create_wifi3() - attach txrx peer
  2562. * @txrx_vdev: Datapath VDEV handle
  2563. * @peer_mac_addr: Peer MAC address
  2564. *
  2565. * Return: DP peeer handle on success, NULL on failure
  2566. */
  2567. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2568. uint8_t *peer_mac_addr)
  2569. {
  2570. struct dp_peer *peer;
  2571. int i;
  2572. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2573. struct dp_pdev *pdev;
  2574. struct dp_soc *soc;
  2575. /* preconditions */
  2576. qdf_assert(vdev);
  2577. qdf_assert(peer_mac_addr);
  2578. pdev = vdev->pdev;
  2579. soc = pdev->soc;
  2580. #ifdef notyet
  2581. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2582. soc->mempool_ol_ath_peer);
  2583. #else
  2584. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2585. #endif
  2586. if (!peer)
  2587. return NULL; /* failure */
  2588. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2589. TAILQ_INIT(&peer->ast_entry_list);
  2590. /* store provided params */
  2591. peer->vdev = vdev;
  2592. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2593. qdf_spinlock_create(&peer->peer_info_lock);
  2594. qdf_mem_copy(
  2595. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2596. /* TODO: See of rx_opt_proc is really required */
  2597. peer->rx_opt_proc = soc->rx_opt_proc;
  2598. /* initialize the peer_id */
  2599. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2600. peer->peer_ids[i] = HTT_INVALID_PEER;
  2601. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2602. qdf_atomic_init(&peer->ref_cnt);
  2603. /* keep one reference for attach */
  2604. qdf_atomic_inc(&peer->ref_cnt);
  2605. /* add this peer into the vdev's list */
  2606. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2607. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2608. /* TODO: See if hash based search is required */
  2609. dp_peer_find_hash_add(soc, peer);
  2610. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2611. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  2612. vdev, peer, peer->mac_addr.raw,
  2613. qdf_atomic_read(&peer->ref_cnt));
  2614. /*
  2615. * For every peer MAp message search and set if bss_peer
  2616. */
  2617. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2618. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2619. "vdev bss_peer!!!!");
  2620. peer->bss_peer = 1;
  2621. vdev->vap_bss_peer = peer;
  2622. }
  2623. #ifndef CONFIG_WIN
  2624. dp_local_peer_id_alloc(pdev, peer);
  2625. #endif
  2626. DP_STATS_INIT(peer);
  2627. return (void *)peer;
  2628. }
  2629. /*
  2630. * dp_peer_setup_wifi3() - initialize the peer
  2631. * @vdev_hdl: virtual device object
  2632. * @peer: Peer object
  2633. *
  2634. * Return: void
  2635. */
  2636. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2637. {
  2638. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2639. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2640. struct dp_pdev *pdev;
  2641. struct dp_soc *soc;
  2642. bool hash_based = 0;
  2643. enum cdp_host_reo_dest_ring reo_dest;
  2644. /* preconditions */
  2645. qdf_assert(vdev);
  2646. qdf_assert(peer);
  2647. pdev = vdev->pdev;
  2648. soc = pdev->soc;
  2649. dp_peer_rx_init(pdev, peer);
  2650. peer->last_assoc_rcvd = 0;
  2651. peer->last_disassoc_rcvd = 0;
  2652. peer->last_deauth_rcvd = 0;
  2653. /*
  2654. * hash based steering is disabled for Radios which are offloaded
  2655. * to NSS
  2656. */
  2657. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2658. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2659. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2660. FL("hash based steering for pdev: %d is %d\n"),
  2661. pdev->pdev_id, hash_based);
  2662. if (!hash_based)
  2663. reo_dest = pdev->reo_dest;
  2664. else
  2665. reo_dest = 1;
  2666. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2667. /* TODO: Check the destination ring number to be passed to FW */
  2668. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2669. pdev->osif_pdev, peer->mac_addr.raw,
  2670. peer->vdev->vdev_id, hash_based, reo_dest);
  2671. }
  2672. return;
  2673. }
  2674. /*
  2675. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2676. * @vdev_handle: virtual device object
  2677. * @htt_pkt_type: type of pkt
  2678. *
  2679. * Return: void
  2680. */
  2681. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2682. enum htt_cmn_pkt_type val)
  2683. {
  2684. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2685. vdev->tx_encap_type = val;
  2686. }
  2687. /*
  2688. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2689. * @vdev_handle: virtual device object
  2690. * @htt_pkt_type: type of pkt
  2691. *
  2692. * Return: void
  2693. */
  2694. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2695. enum htt_cmn_pkt_type val)
  2696. {
  2697. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2698. vdev->rx_decap_type = val;
  2699. }
  2700. /*
  2701. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2702. * @pdev_handle: physical device object
  2703. * @val: reo destination ring index (1 - 4)
  2704. *
  2705. * Return: void
  2706. */
  2707. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2708. enum cdp_host_reo_dest_ring val)
  2709. {
  2710. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2711. if (pdev)
  2712. pdev->reo_dest = val;
  2713. }
  2714. /*
  2715. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2716. * @pdev_handle: physical device object
  2717. *
  2718. * Return: reo destination ring index
  2719. */
  2720. static enum cdp_host_reo_dest_ring
  2721. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2722. {
  2723. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2724. if (pdev)
  2725. return pdev->reo_dest;
  2726. else
  2727. return cdp_host_reo_dest_ring_unknown;
  2728. }
  2729. #ifdef QCA_SUPPORT_SON
  2730. static void dp_son_peer_authorize(struct dp_peer *peer)
  2731. {
  2732. struct dp_soc *soc;
  2733. soc = peer->vdev->pdev->soc;
  2734. peer->peer_bs_inact_flag = 0;
  2735. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2736. return;
  2737. }
  2738. #else
  2739. static void dp_son_peer_authorize(struct dp_peer *peer)
  2740. {
  2741. return;
  2742. }
  2743. #endif
  2744. /*
  2745. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2746. * @pdev_handle: device object
  2747. * @val: value to be set
  2748. *
  2749. * Return: void
  2750. */
  2751. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2752. uint32_t val)
  2753. {
  2754. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2755. /* Enable/Disable smart mesh filtering. This flag will be checked
  2756. * during rx processing to check if packets are from NAC clients.
  2757. */
  2758. pdev->filter_neighbour_peers = val;
  2759. return 0;
  2760. }
  2761. /*
  2762. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2763. * address for smart mesh filtering
  2764. * @pdev_handle: device object
  2765. * @cmd: Add/Del command
  2766. * @macaddr: nac client mac address
  2767. *
  2768. * Return: void
  2769. */
  2770. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2771. uint32_t cmd, uint8_t *macaddr)
  2772. {
  2773. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2774. struct dp_neighbour_peer *peer = NULL;
  2775. if (!macaddr)
  2776. goto fail0;
  2777. /* Store address of NAC (neighbour peer) which will be checked
  2778. * against TA of received packets.
  2779. */
  2780. if (cmd == DP_NAC_PARAM_ADD) {
  2781. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2782. sizeof(*peer));
  2783. if (!peer) {
  2784. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2785. FL("DP neighbour peer node memory allocation failed"));
  2786. goto fail0;
  2787. }
  2788. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2789. macaddr, DP_MAC_ADDR_LEN);
  2790. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2791. /* add this neighbour peer into the list */
  2792. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2793. neighbour_peer_list_elem);
  2794. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2795. return 1;
  2796. } else if (cmd == DP_NAC_PARAM_DEL) {
  2797. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2798. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2799. neighbour_peer_list_elem) {
  2800. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2801. macaddr, DP_MAC_ADDR_LEN)) {
  2802. /* delete this peer from the list */
  2803. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2804. peer, neighbour_peer_list_elem);
  2805. qdf_mem_free(peer);
  2806. break;
  2807. }
  2808. }
  2809. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2810. return 1;
  2811. }
  2812. fail0:
  2813. return 0;
  2814. }
  2815. /*
  2816. * dp_get_sec_type() - Get the security type
  2817. * @peer: Datapath peer handle
  2818. * @sec_idx: Security id (mcast, ucast)
  2819. *
  2820. * return sec_type: Security type
  2821. */
  2822. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2823. {
  2824. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2825. return dpeer->security[sec_idx].sec_type;
  2826. }
  2827. /*
  2828. * dp_peer_authorize() - authorize txrx peer
  2829. * @peer_handle: Datapath peer handle
  2830. * @authorize
  2831. *
  2832. */
  2833. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2834. {
  2835. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2836. struct dp_soc *soc;
  2837. if (peer != NULL) {
  2838. soc = peer->vdev->pdev->soc;
  2839. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2840. dp_son_peer_authorize(peer);
  2841. peer->authorize = authorize ? 1 : 0;
  2842. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2843. }
  2844. }
  2845. /*
  2846. * dp_peer_unref_delete() - unref and delete peer
  2847. * @peer_handle: Datapath peer handle
  2848. *
  2849. */
  2850. void dp_peer_unref_delete(void *peer_handle)
  2851. {
  2852. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2853. struct dp_vdev *vdev = peer->vdev;
  2854. struct dp_pdev *pdev = vdev->pdev;
  2855. struct dp_soc *soc = pdev->soc;
  2856. struct dp_peer *tmppeer;
  2857. int found = 0;
  2858. uint16_t peer_id;
  2859. /*
  2860. * Hold the lock all the way from checking if the peer ref count
  2861. * is zero until the peer references are removed from the hash
  2862. * table and vdev list (if the peer ref count is zero).
  2863. * This protects against a new HL tx operation starting to use the
  2864. * peer object just after this function concludes it's done being used.
  2865. * Furthermore, the lock needs to be held while checking whether the
  2866. * vdev's list of peers is empty, to make sure that list is not modified
  2867. * concurrently with the empty check.
  2868. */
  2869. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2870. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2871. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  2872. peer, qdf_atomic_read(&peer->ref_cnt));
  2873. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2874. peer_id = peer->peer_ids[0];
  2875. /*
  2876. * Make sure that the reference to the peer in
  2877. * peer object map is removed
  2878. */
  2879. if (peer_id != HTT_INVALID_PEER)
  2880. soc->peer_id_to_obj_map[peer_id] = NULL;
  2881. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2882. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  2883. /* remove the reference to the peer from the hash table */
  2884. dp_peer_find_hash_remove(soc, peer);
  2885. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2886. if (tmppeer == peer) {
  2887. found = 1;
  2888. break;
  2889. }
  2890. }
  2891. if (found) {
  2892. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2893. peer_list_elem);
  2894. } else {
  2895. /*Ignoring the remove operation as peer not found*/
  2896. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2897. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  2898. peer, vdev, &peer->vdev->peer_list);
  2899. }
  2900. /* cleanup the peer data */
  2901. dp_peer_cleanup(vdev, peer);
  2902. /* check whether the parent vdev has no peers left */
  2903. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2904. /*
  2905. * Now that there are no references to the peer, we can
  2906. * release the peer reference lock.
  2907. */
  2908. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2909. /*
  2910. * Check if the parent vdev was waiting for its peers
  2911. * to be deleted, in order for it to be deleted too.
  2912. */
  2913. if (vdev->delete.pending) {
  2914. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2915. vdev->delete.callback;
  2916. void *vdev_delete_context =
  2917. vdev->delete.context;
  2918. QDF_TRACE(QDF_MODULE_ID_DP,
  2919. QDF_TRACE_LEVEL_INFO_HIGH,
  2920. FL("deleting vdev object %pK (%pM)"
  2921. " - its last peer is done"),
  2922. vdev, vdev->mac_addr.raw);
  2923. /* all peers are gone, go ahead and delete it */
  2924. qdf_mem_free(vdev);
  2925. if (vdev_delete_cb)
  2926. vdev_delete_cb(vdev_delete_context);
  2927. }
  2928. } else {
  2929. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2930. }
  2931. #ifdef notyet
  2932. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2933. #else
  2934. qdf_mem_free(peer);
  2935. #endif
  2936. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2937. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2938. vdev->vdev_id, peer->mac_addr.raw);
  2939. }
  2940. } else {
  2941. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2942. }
  2943. }
  2944. /*
  2945. * dp_peer_detach_wifi3() – Detach txrx peer
  2946. * @peer_handle: Datapath peer handle
  2947. *
  2948. */
  2949. static void dp_peer_delete_wifi3(void *peer_handle)
  2950. {
  2951. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2952. /* redirect the peer's rx delivery function to point to a
  2953. * discard func
  2954. */
  2955. peer->rx_opt_proc = dp_rx_discard;
  2956. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2957. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  2958. #ifndef CONFIG_WIN
  2959. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2960. #endif
  2961. qdf_spinlock_destroy(&peer->peer_info_lock);
  2962. /*
  2963. * Remove the reference added during peer_attach.
  2964. * The peer will still be left allocated until the
  2965. * PEER_UNMAP message arrives to remove the other
  2966. * reference, added by the PEER_MAP message.
  2967. */
  2968. dp_peer_unref_delete(peer_handle);
  2969. }
  2970. /*
  2971. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2972. * @peer_handle: Datapath peer handle
  2973. *
  2974. */
  2975. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2976. {
  2977. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2978. return vdev->mac_addr.raw;
  2979. }
  2980. /*
  2981. * dp_vdev_set_wds() - Enable per packet stats
  2982. * @vdev_handle: DP VDEV handle
  2983. * @val: value
  2984. *
  2985. * Return: none
  2986. */
  2987. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2988. {
  2989. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2990. vdev->wds_enabled = val;
  2991. return 0;
  2992. }
  2993. /*
  2994. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2995. * @peer_handle: Datapath peer handle
  2996. *
  2997. */
  2998. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  2999. uint8_t vdev_id)
  3000. {
  3001. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  3002. struct dp_vdev *vdev = NULL;
  3003. if (qdf_unlikely(!pdev))
  3004. return NULL;
  3005. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3006. if (vdev->vdev_id == vdev_id)
  3007. break;
  3008. }
  3009. return (struct cdp_vdev *)vdev;
  3010. }
  3011. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  3012. {
  3013. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3014. return vdev->opmode;
  3015. }
  3016. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  3017. {
  3018. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3019. struct dp_pdev *pdev = vdev->pdev;
  3020. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  3021. }
  3022. /**
  3023. * dp_reset_monitor_mode() - Disable monitor mode
  3024. * @pdev_handle: Datapath PDEV handle
  3025. *
  3026. * Return: 0 on success, not 0 on failure
  3027. */
  3028. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  3029. {
  3030. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3031. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3032. struct dp_soc *soc;
  3033. uint8_t pdev_id;
  3034. pdev_id = pdev->pdev_id;
  3035. soc = pdev->soc;
  3036. pdev->monitor_vdev = NULL;
  3037. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  3038. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3039. pdev->rxdma_mon_buf_ring.hal_srng,
  3040. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3041. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3042. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3043. RX_BUFFER_SIZE, &htt_tlv_filter);
  3044. return 0;
  3045. }
  3046. /**
  3047. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3048. * @vdev_handle: Datapath VDEV handle
  3049. * @smart_monitor: Flag to denote if its smart monitor mode
  3050. *
  3051. * Return: 0 on success, not 0 on failure
  3052. */
  3053. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3054. uint8_t smart_monitor)
  3055. {
  3056. /* Many monitor VAPs can exists in a system but only one can be up at
  3057. * anytime
  3058. */
  3059. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3060. struct dp_pdev *pdev;
  3061. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3062. struct dp_soc *soc;
  3063. uint8_t pdev_id;
  3064. qdf_assert(vdev);
  3065. pdev = vdev->pdev;
  3066. pdev_id = pdev->pdev_id;
  3067. soc = pdev->soc;
  3068. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3069. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  3070. pdev, pdev_id, soc, vdev);
  3071. /*Check if current pdev's monitor_vdev exists */
  3072. if (pdev->monitor_vdev) {
  3073. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3074. "vdev=%pK\n", vdev);
  3075. qdf_assert(vdev);
  3076. }
  3077. pdev->monitor_vdev = vdev;
  3078. /* If smart monitor mode, do not configure monitor ring */
  3079. if (smart_monitor)
  3080. return QDF_STATUS_SUCCESS;
  3081. htt_tlv_filter.mpdu_start = 1;
  3082. htt_tlv_filter.msdu_start = 1;
  3083. htt_tlv_filter.packet = 1;
  3084. htt_tlv_filter.msdu_end = 1;
  3085. htt_tlv_filter.mpdu_end = 1;
  3086. htt_tlv_filter.packet_header = 1;
  3087. htt_tlv_filter.attention = 1;
  3088. htt_tlv_filter.ppdu_start = 0;
  3089. htt_tlv_filter.ppdu_end = 0;
  3090. htt_tlv_filter.ppdu_end_user_stats = 0;
  3091. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3092. htt_tlv_filter.ppdu_end_status_done = 0;
  3093. htt_tlv_filter.header_per_msdu = 1;
  3094. htt_tlv_filter.enable_fp = 1;
  3095. htt_tlv_filter.enable_md = 0;
  3096. htt_tlv_filter.enable_mo = 1;
  3097. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3098. pdev->rxdma_mon_buf_ring.hal_srng,
  3099. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3100. htt_tlv_filter.mpdu_start = 1;
  3101. htt_tlv_filter.msdu_start = 1;
  3102. htt_tlv_filter.packet = 0;
  3103. htt_tlv_filter.msdu_end = 1;
  3104. htt_tlv_filter.mpdu_end = 1;
  3105. htt_tlv_filter.packet_header = 1;
  3106. htt_tlv_filter.attention = 1;
  3107. htt_tlv_filter.ppdu_start = 1;
  3108. htt_tlv_filter.ppdu_end = 1;
  3109. htt_tlv_filter.ppdu_end_user_stats = 1;
  3110. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3111. htt_tlv_filter.ppdu_end_status_done = 1;
  3112. htt_tlv_filter.header_per_msdu = 0;
  3113. htt_tlv_filter.enable_fp = 1;
  3114. htt_tlv_filter.enable_md = 0;
  3115. htt_tlv_filter.enable_mo = 1;
  3116. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3117. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3118. RX_BUFFER_SIZE, &htt_tlv_filter);
  3119. return QDF_STATUS_SUCCESS;
  3120. }
  3121. #ifdef MESH_MODE_SUPPORT
  3122. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3123. {
  3124. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3125. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3126. FL("val %d"), val);
  3127. vdev->mesh_vdev = val;
  3128. }
  3129. /*
  3130. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3131. * @vdev_hdl: virtual device object
  3132. * @val: value to be set
  3133. *
  3134. * Return: void
  3135. */
  3136. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3137. {
  3138. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3139. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3140. FL("val %d"), val);
  3141. vdev->mesh_rx_filter = val;
  3142. }
  3143. #endif
  3144. /**
  3145. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3146. * @vdev: DP VDEV handle
  3147. *
  3148. * return: void
  3149. */
  3150. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3151. {
  3152. struct dp_peer *peer = NULL;
  3153. struct dp_soc *soc = vdev->pdev->soc;
  3154. int i;
  3155. uint8_t pream_type;
  3156. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3157. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3158. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3159. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3160. for (i = 0; i < MAX_MCS; i++) {
  3161. DP_STATS_AGGR(vdev, peer,
  3162. tx.pkt_type[pream_type].mcs_count[i]);
  3163. DP_STATS_AGGR(vdev, peer,
  3164. rx.pkt_type[pream_type].mcs_count[i]);
  3165. }
  3166. }
  3167. for (i = 0; i < MAX_BW; i++) {
  3168. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3169. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3170. }
  3171. for (i = 0; i < SS_COUNT; i++)
  3172. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3173. for (i = 0; i < WME_AC_MAX; i++) {
  3174. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3175. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3176. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3177. }
  3178. for (i = 0; i < MAX_GI; i++) {
  3179. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3180. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3181. }
  3182. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3183. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3184. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3185. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3186. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3187. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3188. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3189. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3190. DP_STATS_AGGR(vdev, peer, tx.retries);
  3191. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3192. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3193. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3194. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3195. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3196. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3197. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3198. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3199. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3200. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3201. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3202. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3203. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3204. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3205. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3206. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3207. peer->stats.rx.multicast.num;
  3208. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3209. peer->stats.rx.multicast.bytes;
  3210. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3211. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3212. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3213. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3214. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3215. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3216. vdev->stats.tx.last_ack_rssi =
  3217. peer->stats.tx.last_ack_rssi;
  3218. }
  3219. if (soc->cdp_soc.ol_ops->update_dp_stats)
  3220. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3221. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3222. }
  3223. /**
  3224. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3225. * @pdev: DP PDEV handle
  3226. *
  3227. * return: void
  3228. */
  3229. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3230. {
  3231. struct dp_vdev *vdev = NULL;
  3232. uint8_t i;
  3233. uint8_t pream_type;
  3234. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3235. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3236. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3237. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3238. dp_aggregate_vdev_stats(vdev);
  3239. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3240. for (i = 0; i < MAX_MCS; i++) {
  3241. DP_STATS_AGGR(pdev, vdev,
  3242. tx.pkt_type[pream_type].mcs_count[i]);
  3243. DP_STATS_AGGR(pdev, vdev,
  3244. rx.pkt_type[pream_type].mcs_count[i]);
  3245. }
  3246. }
  3247. for (i = 0; i < MAX_BW; i++) {
  3248. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3249. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3250. }
  3251. for (i = 0; i < SS_COUNT; i++)
  3252. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3253. for (i = 0; i < WME_AC_MAX; i++) {
  3254. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3255. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3256. DP_STATS_AGGR(pdev, vdev,
  3257. tx.excess_retries_ac[i]);
  3258. }
  3259. for (i = 0; i < MAX_GI; i++) {
  3260. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3261. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3262. }
  3263. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3264. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3265. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3266. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3267. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3268. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3269. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3270. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3271. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3272. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3273. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3274. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3275. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3276. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3277. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3278. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3279. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3280. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3281. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3282. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3283. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3284. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3285. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3286. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3287. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3288. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3289. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3290. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3291. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3292. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3293. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3294. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3295. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3296. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3297. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3298. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3299. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3300. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3301. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3302. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3303. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3304. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3305. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3306. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3307. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3308. DP_STATS_AGGR(pdev, vdev,
  3309. tx_i.mcast_en.dropped_map_error);
  3310. DP_STATS_AGGR(pdev, vdev,
  3311. tx_i.mcast_en.dropped_self_mac);
  3312. DP_STATS_AGGR(pdev, vdev,
  3313. tx_i.mcast_en.dropped_send_fail);
  3314. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3315. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3316. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3317. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3318. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3319. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3320. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3321. pdev->stats.tx_i.dropped.dma_error +
  3322. pdev->stats.tx_i.dropped.ring_full +
  3323. pdev->stats.tx_i.dropped.enqueue_fail +
  3324. pdev->stats.tx_i.dropped.desc_na +
  3325. pdev->stats.tx_i.dropped.res_full;
  3326. pdev->stats.tx.last_ack_rssi =
  3327. vdev->stats.tx.last_ack_rssi;
  3328. pdev->stats.tx_i.tso.num_seg =
  3329. vdev->stats.tx_i.tso.num_seg;
  3330. }
  3331. }
  3332. /**
  3333. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3334. * @pdev: DP_PDEV Handle
  3335. *
  3336. * Return:void
  3337. */
  3338. static inline void
  3339. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3340. {
  3341. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3342. DP_PRINT_STATS("Received From Stack:");
  3343. DP_PRINT_STATS(" Packets = %d",
  3344. pdev->stats.tx_i.rcvd.num);
  3345. DP_PRINT_STATS(" Bytes = %d",
  3346. pdev->stats.tx_i.rcvd.bytes);
  3347. DP_PRINT_STATS("Processed:");
  3348. DP_PRINT_STATS(" Packets = %d",
  3349. pdev->stats.tx_i.processed.num);
  3350. DP_PRINT_STATS(" Bytes = %d",
  3351. pdev->stats.tx_i.processed.bytes);
  3352. DP_PRINT_STATS("Completions:");
  3353. DP_PRINT_STATS(" Packets = %d",
  3354. pdev->stats.tx.comp_pkt.num);
  3355. DP_PRINT_STATS(" Bytes = %d",
  3356. pdev->stats.tx.comp_pkt.bytes);
  3357. DP_PRINT_STATS("Dropped:");
  3358. DP_PRINT_STATS(" Total = %d",
  3359. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3360. DP_PRINT_STATS(" Dma_map_error = %d",
  3361. pdev->stats.tx_i.dropped.dma_error);
  3362. DP_PRINT_STATS(" Ring Full = %d",
  3363. pdev->stats.tx_i.dropped.ring_full);
  3364. DP_PRINT_STATS(" Descriptor Not available = %d",
  3365. pdev->stats.tx_i.dropped.desc_na);
  3366. DP_PRINT_STATS(" HW enqueue failed= %d",
  3367. pdev->stats.tx_i.dropped.enqueue_fail);
  3368. DP_PRINT_STATS(" Resources Full = %d",
  3369. pdev->stats.tx_i.dropped.res_full);
  3370. DP_PRINT_STATS(" FW removed = %d",
  3371. pdev->stats.tx.dropped.fw_rem);
  3372. DP_PRINT_STATS(" FW removed transmitted = %d",
  3373. pdev->stats.tx.dropped.fw_rem_tx);
  3374. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3375. pdev->stats.tx.dropped.fw_rem_notx);
  3376. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3377. pdev->stats.tx.dropped.age_out);
  3378. DP_PRINT_STATS("Scatter Gather:");
  3379. DP_PRINT_STATS(" Packets = %d",
  3380. pdev->stats.tx_i.sg.sg_pkt.num);
  3381. DP_PRINT_STATS(" Bytes = %d",
  3382. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3383. DP_PRINT_STATS(" Dropped By Host = %d",
  3384. pdev->stats.tx_i.sg.dropped_host);
  3385. DP_PRINT_STATS(" Dropped By Target = %d",
  3386. pdev->stats.tx_i.sg.dropped_target);
  3387. DP_PRINT_STATS("TSO:");
  3388. DP_PRINT_STATS(" Number of Segments = %d",
  3389. pdev->stats.tx_i.tso.num_seg);
  3390. DP_PRINT_STATS(" Packets = %d",
  3391. pdev->stats.tx_i.tso.tso_pkt.num);
  3392. DP_PRINT_STATS(" Bytes = %d",
  3393. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3394. DP_PRINT_STATS(" Dropped By Host = %d",
  3395. pdev->stats.tx_i.tso.dropped_host);
  3396. DP_PRINT_STATS("Mcast Enhancement:");
  3397. DP_PRINT_STATS(" Packets = %d",
  3398. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3399. DP_PRINT_STATS(" Bytes = %d",
  3400. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3401. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3402. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3403. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3404. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3405. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3406. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3407. DP_PRINT_STATS(" Unicast sent = %d",
  3408. pdev->stats.tx_i.mcast_en.ucast);
  3409. DP_PRINT_STATS("Raw:");
  3410. DP_PRINT_STATS(" Packets = %d",
  3411. pdev->stats.tx_i.raw.raw_pkt.num);
  3412. DP_PRINT_STATS(" Bytes = %d",
  3413. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3414. DP_PRINT_STATS(" DMA map error = %d",
  3415. pdev->stats.tx_i.raw.dma_map_error);
  3416. DP_PRINT_STATS("Reinjected:");
  3417. DP_PRINT_STATS(" Packets = %d",
  3418. pdev->stats.tx_i.reinject_pkts.num);
  3419. DP_PRINT_STATS("Bytes = %d\n",
  3420. pdev->stats.tx_i.reinject_pkts.bytes);
  3421. DP_PRINT_STATS("Inspected:");
  3422. DP_PRINT_STATS(" Packets = %d",
  3423. pdev->stats.tx_i.inspect_pkts.num);
  3424. DP_PRINT_STATS(" Bytes = %d",
  3425. pdev->stats.tx_i.inspect_pkts.bytes);
  3426. }
  3427. /**
  3428. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3429. * @pdev: DP_PDEV Handle
  3430. *
  3431. * Return: void
  3432. */
  3433. static inline void
  3434. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3435. {
  3436. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3437. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3438. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3439. pdev->stats.rx.rcvd_reo[0].num,
  3440. pdev->stats.rx.rcvd_reo[1].num,
  3441. pdev->stats.rx.rcvd_reo[2].num,
  3442. pdev->stats.rx.rcvd_reo[3].num);
  3443. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3444. pdev->stats.rx.rcvd_reo[0].bytes,
  3445. pdev->stats.rx.rcvd_reo[1].bytes,
  3446. pdev->stats.rx.rcvd_reo[2].bytes,
  3447. pdev->stats.rx.rcvd_reo[3].bytes);
  3448. DP_PRINT_STATS("Replenished:");
  3449. DP_PRINT_STATS(" Packets = %d",
  3450. pdev->stats.replenish.pkts.num);
  3451. DP_PRINT_STATS(" Bytes = %d",
  3452. pdev->stats.replenish.pkts.bytes);
  3453. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3454. pdev->stats.buf_freelist);
  3455. DP_PRINT_STATS("Dropped:");
  3456. DP_PRINT_STATS(" msdu_not_done = %d",
  3457. pdev->stats.dropped.msdu_not_done);
  3458. DP_PRINT_STATS("Sent To Stack:");
  3459. DP_PRINT_STATS(" Packets = %d",
  3460. pdev->stats.rx.to_stack.num);
  3461. DP_PRINT_STATS(" Bytes = %d",
  3462. pdev->stats.rx.to_stack.bytes);
  3463. DP_PRINT_STATS("Multicast/Broadcast:");
  3464. DP_PRINT_STATS(" Packets = %d",
  3465. pdev->stats.rx.multicast.num);
  3466. DP_PRINT_STATS(" Bytes = %d",
  3467. pdev->stats.rx.multicast.bytes);
  3468. DP_PRINT_STATS("Errors:");
  3469. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3470. pdev->stats.replenish.rxdma_err);
  3471. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3472. pdev->stats.err.desc_alloc_fail);
  3473. }
  3474. /**
  3475. * dp_print_soc_tx_stats(): Print SOC level stats
  3476. * @soc DP_SOC Handle
  3477. *
  3478. * Return: void
  3479. */
  3480. static inline void
  3481. dp_print_soc_tx_stats(struct dp_soc *soc)
  3482. {
  3483. DP_PRINT_STATS("SOC Tx Stats:\n");
  3484. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3485. soc->stats.tx.desc_in_use);
  3486. DP_PRINT_STATS("Invalid peer:");
  3487. DP_PRINT_STATS(" Packets = %d",
  3488. soc->stats.tx.tx_invalid_peer.num);
  3489. DP_PRINT_STATS(" Bytes = %d",
  3490. soc->stats.tx.tx_invalid_peer.bytes);
  3491. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3492. soc->stats.tx.tcl_ring_full[0],
  3493. soc->stats.tx.tcl_ring_full[1],
  3494. soc->stats.tx.tcl_ring_full[2]);
  3495. }
  3496. /**
  3497. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3498. * @soc: DP_SOC Handle
  3499. *
  3500. * Return:void
  3501. */
  3502. static inline void
  3503. dp_print_soc_rx_stats(struct dp_soc *soc)
  3504. {
  3505. uint32_t i;
  3506. char reo_error[DP_REO_ERR_LENGTH];
  3507. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3508. uint8_t index = 0;
  3509. DP_PRINT_STATS("SOC Rx Stats:\n");
  3510. DP_PRINT_STATS("Errors:\n");
  3511. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3512. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3513. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3514. DP_PRINT_STATS("Invalid RBM = %d",
  3515. soc->stats.rx.err.invalid_rbm);
  3516. DP_PRINT_STATS("Invalid Vdev = %d",
  3517. soc->stats.rx.err.invalid_vdev);
  3518. DP_PRINT_STATS("Invalid Pdev = %d",
  3519. soc->stats.rx.err.invalid_pdev);
  3520. DP_PRINT_STATS("Invalid Peer = %d",
  3521. soc->stats.rx.err.rx_invalid_peer.num);
  3522. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3523. soc->stats.rx.err.hal_ring_access_fail);
  3524. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3525. index += qdf_snprint(&rxdma_error[index],
  3526. DP_RXDMA_ERR_LENGTH - index,
  3527. " %d", soc->stats.rx.err.rxdma_error[i]);
  3528. }
  3529. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3530. rxdma_error);
  3531. index = 0;
  3532. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3533. index += qdf_snprint(&reo_error[index],
  3534. DP_REO_ERR_LENGTH - index,
  3535. " %d", soc->stats.rx.err.reo_error[i]);
  3536. }
  3537. DP_PRINT_STATS("REO Error(0-14):%s",
  3538. reo_error);
  3539. }
  3540. /**
  3541. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3542. * @vdev: DP_VDEV handle
  3543. *
  3544. * Return:void
  3545. */
  3546. static inline void
  3547. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3548. {
  3549. struct dp_peer *peer = NULL;
  3550. DP_STATS_CLR(vdev->pdev);
  3551. DP_STATS_CLR(vdev->pdev->soc);
  3552. DP_STATS_CLR(vdev);
  3553. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3554. if (!peer)
  3555. return;
  3556. DP_STATS_CLR(peer);
  3557. }
  3558. }
  3559. /**
  3560. * dp_print_rx_rates(): Print Rx rate stats
  3561. * @vdev: DP_VDEV handle
  3562. *
  3563. * Return:void
  3564. */
  3565. static inline void
  3566. dp_print_rx_rates(struct dp_vdev *vdev)
  3567. {
  3568. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3569. uint8_t i, mcs, pkt_type;
  3570. uint8_t index = 0;
  3571. char nss[DP_NSS_LENGTH];
  3572. DP_PRINT_STATS("Rx Rate Info:\n");
  3573. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3574. index = 0;
  3575. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3576. if (!dp_rate_string[pkt_type][mcs].valid)
  3577. continue;
  3578. DP_PRINT_STATS(" %s = %d",
  3579. dp_rate_string[pkt_type][mcs].mcs_type,
  3580. pdev->stats.rx.pkt_type[pkt_type].
  3581. mcs_count[mcs]);
  3582. }
  3583. DP_PRINT_STATS("\n");
  3584. }
  3585. index = 0;
  3586. for (i = 0; i < SS_COUNT; i++) {
  3587. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3588. " %d", pdev->stats.rx.nss[i]);
  3589. }
  3590. DP_PRINT_STATS("NSS(0-7) = %s",
  3591. nss);
  3592. DP_PRINT_STATS("SGI ="
  3593. " 0.8us %d,"
  3594. " 0.4us %d,"
  3595. " 1.6us %d,"
  3596. " 3.2us %d,",
  3597. pdev->stats.rx.sgi_count[0],
  3598. pdev->stats.rx.sgi_count[1],
  3599. pdev->stats.rx.sgi_count[2],
  3600. pdev->stats.rx.sgi_count[3]);
  3601. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3602. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3603. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3604. DP_PRINT_STATS("Reception Type ="
  3605. " SU: %d,"
  3606. " MU_MIMO:%d,"
  3607. " MU_OFDMA:%d,"
  3608. " MU_OFDMA_MIMO:%d\n",
  3609. pdev->stats.rx.reception_type[0],
  3610. pdev->stats.rx.reception_type[1],
  3611. pdev->stats.rx.reception_type[2],
  3612. pdev->stats.rx.reception_type[3]);
  3613. DP_PRINT_STATS("Aggregation:\n");
  3614. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3615. pdev->stats.rx.ampdu_cnt);
  3616. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3617. pdev->stats.rx.non_ampdu_cnt);
  3618. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3619. pdev->stats.rx.amsdu_cnt);
  3620. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3621. pdev->stats.rx.non_amsdu_cnt);
  3622. }
  3623. /**
  3624. * dp_print_tx_rates(): Print tx rates
  3625. * @vdev: DP_VDEV handle
  3626. *
  3627. * Return:void
  3628. */
  3629. static inline void
  3630. dp_print_tx_rates(struct dp_vdev *vdev)
  3631. {
  3632. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3633. uint8_t mcs, pkt_type;
  3634. uint32_t index;
  3635. DP_PRINT_STATS("Tx Rate Info:\n");
  3636. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3637. index = 0;
  3638. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3639. if (!dp_rate_string[pkt_type][mcs].valid)
  3640. continue;
  3641. DP_PRINT_STATS(" %s = %d",
  3642. dp_rate_string[pkt_type][mcs].mcs_type,
  3643. pdev->stats.tx.pkt_type[pkt_type].
  3644. mcs_count[mcs]);
  3645. }
  3646. DP_PRINT_STATS("\n");
  3647. }
  3648. DP_PRINT_STATS("SGI ="
  3649. " 0.8us %d"
  3650. " 0.4us %d"
  3651. " 1.6us %d"
  3652. " 3.2us %d",
  3653. pdev->stats.tx.sgi_count[0],
  3654. pdev->stats.tx.sgi_count[1],
  3655. pdev->stats.tx.sgi_count[2],
  3656. pdev->stats.tx.sgi_count[3]);
  3657. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3658. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3659. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3660. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3661. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3662. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3663. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3664. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3665. DP_PRINT_STATS("Aggregation:\n");
  3666. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3667. pdev->stats.tx.amsdu_cnt);
  3668. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3669. pdev->stats.tx.non_amsdu_cnt);
  3670. }
  3671. /**
  3672. * dp_print_peer_stats():print peer stats
  3673. * @peer: DP_PEER handle
  3674. *
  3675. * return void
  3676. */
  3677. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3678. {
  3679. uint8_t i, mcs, pkt_type;
  3680. uint32_t index;
  3681. char nss[DP_NSS_LENGTH];
  3682. DP_PRINT_STATS("Node Tx Stats:\n");
  3683. DP_PRINT_STATS("Total Packet Completions = %d",
  3684. peer->stats.tx.comp_pkt.num);
  3685. DP_PRINT_STATS("Total Bytes Completions = %d",
  3686. peer->stats.tx.comp_pkt.bytes);
  3687. DP_PRINT_STATS("Success Packets = %d",
  3688. peer->stats.tx.tx_success.num);
  3689. DP_PRINT_STATS("Success Bytes = %d",
  3690. peer->stats.tx.tx_success.bytes);
  3691. DP_PRINT_STATS("Packets Failed = %d",
  3692. peer->stats.tx.tx_failed);
  3693. DP_PRINT_STATS("Packets In OFDMA = %d",
  3694. peer->stats.tx.ofdma);
  3695. DP_PRINT_STATS("Packets In STBC = %d",
  3696. peer->stats.tx.stbc);
  3697. DP_PRINT_STATS("Packets In LDPC = %d",
  3698. peer->stats.tx.ldpc);
  3699. DP_PRINT_STATS("Packet Retries = %d",
  3700. peer->stats.tx.retries);
  3701. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3702. peer->stats.tx.amsdu_cnt);
  3703. DP_PRINT_STATS("Last Packet RSSI = %d",
  3704. peer->stats.tx.last_ack_rssi);
  3705. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3706. peer->stats.tx.dropped.fw_rem);
  3707. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3708. peer->stats.tx.dropped.fw_rem_tx);
  3709. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3710. peer->stats.tx.dropped.fw_rem_notx);
  3711. DP_PRINT_STATS("Dropped : Age Out = %d",
  3712. peer->stats.tx.dropped.age_out);
  3713. DP_PRINT_STATS("Rate Info:");
  3714. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3715. index = 0;
  3716. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3717. if (!dp_rate_string[pkt_type][mcs].valid)
  3718. continue;
  3719. DP_PRINT_STATS(" %s = %d",
  3720. dp_rate_string[pkt_type][mcs].mcs_type,
  3721. peer->stats.tx.pkt_type[pkt_type].
  3722. mcs_count[mcs]);
  3723. }
  3724. DP_PRINT_STATS("\n");
  3725. }
  3726. DP_PRINT_STATS("SGI = "
  3727. " 0.8us %d"
  3728. " 0.4us %d"
  3729. " 1.6us %d"
  3730. " 3.2us %d",
  3731. peer->stats.tx.sgi_count[0],
  3732. peer->stats.tx.sgi_count[1],
  3733. peer->stats.tx.sgi_count[2],
  3734. peer->stats.tx.sgi_count[3]);
  3735. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3736. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3737. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3738. DP_PRINT_STATS("Aggregation:");
  3739. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3740. peer->stats.tx.amsdu_cnt);
  3741. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3742. peer->stats.tx.non_amsdu_cnt);
  3743. DP_PRINT_STATS("Node Rx Stats:");
  3744. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3745. peer->stats.rx.to_stack.num);
  3746. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3747. peer->stats.rx.to_stack.bytes);
  3748. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3749. DP_PRINT_STATS("Packets Received = %d",
  3750. peer->stats.rx.rcvd_reo[i].num);
  3751. DP_PRINT_STATS("Bytes Received = %d",
  3752. peer->stats.rx.rcvd_reo[i].bytes);
  3753. }
  3754. DP_PRINT_STATS("Multicast Packets Received = %d",
  3755. peer->stats.rx.multicast.num);
  3756. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3757. peer->stats.rx.multicast.bytes);
  3758. DP_PRINT_STATS("WDS Packets Received = %d",
  3759. peer->stats.rx.wds.num);
  3760. DP_PRINT_STATS("WDS Bytes Received = %d",
  3761. peer->stats.rx.wds.bytes);
  3762. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3763. peer->stats.rx.intra_bss.pkts.num);
  3764. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3765. peer->stats.rx.intra_bss.pkts.bytes);
  3766. DP_PRINT_STATS("Raw Packets Received = %d",
  3767. peer->stats.rx.raw.num);
  3768. DP_PRINT_STATS("Raw Bytes Received = %d",
  3769. peer->stats.rx.raw.bytes);
  3770. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3771. peer->stats.rx.err.mic_err);
  3772. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3773. peer->stats.rx.err.decrypt_err);
  3774. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3775. peer->stats.rx.non_ampdu_cnt);
  3776. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3777. peer->stats.rx.ampdu_cnt);
  3778. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3779. peer->stats.rx.non_amsdu_cnt);
  3780. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3781. peer->stats.rx.amsdu_cnt);
  3782. DP_PRINT_STATS("SGI ="
  3783. " 0.8us %d"
  3784. " 0.4us %d"
  3785. " 1.6us %d"
  3786. " 3.2us %d",
  3787. peer->stats.rx.sgi_count[0],
  3788. peer->stats.rx.sgi_count[1],
  3789. peer->stats.rx.sgi_count[2],
  3790. peer->stats.rx.sgi_count[3]);
  3791. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3792. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3793. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3794. DP_PRINT_STATS("Reception Type ="
  3795. " SU %d,"
  3796. " MU_MIMO %d,"
  3797. " MU_OFDMA %d,"
  3798. " MU_OFDMA_MIMO %d",
  3799. peer->stats.rx.reception_type[0],
  3800. peer->stats.rx.reception_type[1],
  3801. peer->stats.rx.reception_type[2],
  3802. peer->stats.rx.reception_type[3]);
  3803. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3804. index = 0;
  3805. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3806. if (!dp_rate_string[pkt_type][mcs].valid)
  3807. continue;
  3808. DP_PRINT_STATS(" %s = %d",
  3809. dp_rate_string[pkt_type][mcs].mcs_type,
  3810. peer->stats.rx.pkt_type[pkt_type].
  3811. mcs_count[mcs]);
  3812. }
  3813. DP_PRINT_STATS("\n");
  3814. }
  3815. index = 0;
  3816. for (i = 0; i < SS_COUNT; i++) {
  3817. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3818. " %d", peer->stats.rx.nss[i]);
  3819. }
  3820. DP_PRINT_STATS("NSS(0-7) = %s",
  3821. nss);
  3822. DP_PRINT_STATS("Aggregation:");
  3823. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  3824. peer->stats.rx.ampdu_cnt);
  3825. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  3826. peer->stats.rx.non_ampdu_cnt);
  3827. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  3828. peer->stats.rx.amsdu_cnt);
  3829. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  3830. peer->stats.rx.non_amsdu_cnt);
  3831. }
  3832. /**
  3833. * dp_print_host_stats()- Function to print the stats aggregated at host
  3834. * @vdev_handle: DP_VDEV handle
  3835. * @type: host stats type
  3836. *
  3837. * Available Stat types
  3838. * TXRX_CLEAR_STATS : Clear the stats
  3839. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3840. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3841. * TXRX_TX_HOST_STATS: Print Tx Stats
  3842. * TXRX_RX_HOST_STATS: Print Rx Stats
  3843. * TXRX_AST_STATS: Print AST Stats
  3844. *
  3845. * Return: 0 on success, print error message in case of failure
  3846. */
  3847. static int
  3848. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3849. {
  3850. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3851. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3852. dp_aggregate_pdev_stats(pdev);
  3853. switch (type) {
  3854. case TXRX_CLEAR_STATS:
  3855. dp_txrx_host_stats_clr(vdev);
  3856. break;
  3857. case TXRX_RX_RATE_STATS:
  3858. dp_print_rx_rates(vdev);
  3859. break;
  3860. case TXRX_TX_RATE_STATS:
  3861. dp_print_tx_rates(vdev);
  3862. break;
  3863. case TXRX_TX_HOST_STATS:
  3864. dp_print_pdev_tx_stats(pdev);
  3865. dp_print_soc_tx_stats(pdev->soc);
  3866. break;
  3867. case TXRX_RX_HOST_STATS:
  3868. dp_print_pdev_rx_stats(pdev);
  3869. dp_print_soc_rx_stats(pdev->soc);
  3870. break;
  3871. case TXRX_AST_STATS:
  3872. dp_print_ast_stats(pdev->soc);
  3873. break;
  3874. default:
  3875. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3876. break;
  3877. }
  3878. return 0;
  3879. }
  3880. /*
  3881. * dp_get_host_peer_stats()- function to print peer stats
  3882. * @pdev_handle: DP_PDEV handle
  3883. * @mac_addr: mac address of the peer
  3884. *
  3885. * Return: void
  3886. */
  3887. static void
  3888. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  3889. {
  3890. struct dp_peer *peer;
  3891. uint8_t local_id;
  3892. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  3893. &local_id);
  3894. if (!peer) {
  3895. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3896. "%s: Invalid peer\n", __func__);
  3897. return;
  3898. }
  3899. dp_print_peer_stats(peer);
  3900. dp_peer_rxtid_stats(peer);
  3901. return;
  3902. }
  3903. /*
  3904. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  3905. * @pdev: DP_PDEV handle
  3906. *
  3907. * Return: void
  3908. */
  3909. static void
  3910. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  3911. {
  3912. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  3913. htt_tlv_filter.mpdu_start = 0;
  3914. htt_tlv_filter.msdu_start = 0;
  3915. htt_tlv_filter.packet = 0;
  3916. htt_tlv_filter.msdu_end = 0;
  3917. htt_tlv_filter.mpdu_end = 0;
  3918. htt_tlv_filter.packet_header = 1;
  3919. htt_tlv_filter.attention = 1;
  3920. htt_tlv_filter.ppdu_start = 1;
  3921. htt_tlv_filter.ppdu_end = 1;
  3922. htt_tlv_filter.ppdu_end_user_stats = 1;
  3923. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3924. htt_tlv_filter.ppdu_end_status_done = 1;
  3925. htt_tlv_filter.enable_fp = 1;
  3926. htt_tlv_filter.enable_md = 0;
  3927. htt_tlv_filter.enable_mo = 0;
  3928. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  3929. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3930. RX_BUFFER_SIZE, &htt_tlv_filter);
  3931. }
  3932. /*
  3933. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  3934. * @pdev_handle: DP_PDEV handle
  3935. *
  3936. * Return: void
  3937. */
  3938. static void
  3939. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3940. {
  3941. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3942. pdev->enhanced_stats_en = 1;
  3943. dp_ppdu_ring_cfg(pdev);
  3944. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  3945. }
  3946. /*
  3947. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  3948. * @pdev_handle: DP_PDEV handle
  3949. *
  3950. * Return: void
  3951. */
  3952. static void
  3953. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3954. {
  3955. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3956. pdev->enhanced_stats_en = 0;
  3957. }
  3958. /*
  3959. * dp_get_fw_peer_stats()- function to print peer stats
  3960. * @pdev_handle: DP_PDEV handle
  3961. * @mac_addr: mac address of the peer
  3962. * @cap: Type of htt stats requested
  3963. *
  3964. * Currently Supporting only MAC ID based requests Only
  3965. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  3966. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  3967. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  3968. *
  3969. * Return: void
  3970. */
  3971. static void
  3972. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  3973. uint32_t cap)
  3974. {
  3975. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3976. uint32_t config_param0 = 0;
  3977. uint32_t config_param1 = 0;
  3978. uint32_t config_param2 = 0;
  3979. uint32_t config_param3 = 0;
  3980. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  3981. config_param0 |= (1 << (cap + 1));
  3982. config_param1 = 0x8f;
  3983. config_param2 |= (mac_addr[0] & 0x000000ff);
  3984. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  3985. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  3986. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  3987. config_param3 |= (mac_addr[4] & 0x000000ff);
  3988. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  3989. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  3990. config_param0, config_param1, config_param2,
  3991. config_param3);
  3992. }
  3993. /*
  3994. * dp_set_vdev_param: function to set parameters in vdev
  3995. * @param: parameter type to be set
  3996. * @val: value of parameter to be set
  3997. *
  3998. * return: void
  3999. */
  4000. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  4001. enum cdp_vdev_param_type param, uint32_t val)
  4002. {
  4003. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4004. switch (param) {
  4005. case CDP_ENABLE_WDS:
  4006. vdev->wds_enabled = val;
  4007. break;
  4008. case CDP_ENABLE_NAWDS:
  4009. vdev->nawds_enabled = val;
  4010. break;
  4011. case CDP_ENABLE_MCAST_EN:
  4012. vdev->mcast_enhancement_en = val;
  4013. break;
  4014. case CDP_ENABLE_PROXYSTA:
  4015. vdev->proxysta_vdev = val;
  4016. break;
  4017. case CDP_UPDATE_TDLS_FLAGS:
  4018. vdev->tdls_link_connected = val;
  4019. break;
  4020. case CDP_CFG_WDS_AGING_TIMER:
  4021. if (val == 0)
  4022. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4023. else if (val != vdev->wds_aging_timer_val)
  4024. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4025. vdev->wds_aging_timer_val = val;
  4026. break;
  4027. case CDP_ENABLE_AP_BRIDGE:
  4028. if (wlan_op_mode_sta != vdev->opmode)
  4029. vdev->ap_bridge_enabled = val;
  4030. else
  4031. vdev->ap_bridge_enabled = false;
  4032. break;
  4033. default:
  4034. break;
  4035. }
  4036. dp_tx_vdev_update_search_flags(vdev);
  4037. }
  4038. /**
  4039. * dp_peer_set_nawds: set nawds bit in peer
  4040. * @peer_handle: pointer to peer
  4041. * @value: enable/disable nawds
  4042. *
  4043. * return: void
  4044. */
  4045. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4046. {
  4047. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4048. peer->nawds_enabled = value;
  4049. }
  4050. /*
  4051. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4052. * @vdev_handle: DP_VDEV handle
  4053. * @map_id:ID of map that needs to be updated
  4054. *
  4055. * Return: void
  4056. */
  4057. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4058. uint8_t map_id)
  4059. {
  4060. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4061. vdev->dscp_tid_map_id = map_id;
  4062. return;
  4063. }
  4064. /**
  4065. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4066. * @pdev: DP_PDEV handle
  4067. * @map_id: ID of map that needs to be updated
  4068. * @tos: index value in map
  4069. * @tid: tid value passed by the user
  4070. *
  4071. * Return: void
  4072. */
  4073. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4074. uint8_t map_id, uint8_t tos, uint8_t tid)
  4075. {
  4076. uint8_t dscp;
  4077. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4078. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4079. pdev->dscp_tid_map[map_id][dscp] = tid;
  4080. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4081. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4082. map_id, dscp);
  4083. return;
  4084. }
  4085. /**
  4086. * dp_fw_stats_process(): Process TxRX FW stats request
  4087. * @vdev_handle: DP VDEV handle
  4088. * @val: value passed by user
  4089. *
  4090. * return: int
  4091. */
  4092. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4093. {
  4094. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4095. struct dp_pdev *pdev = NULL;
  4096. if (!vdev) {
  4097. DP_TRACE(NONE, "VDEV not found");
  4098. return 1;
  4099. }
  4100. pdev = vdev->pdev;
  4101. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4102. }
  4103. /*
  4104. * dp_txrx_stats() - function to map to firmware and host stats
  4105. * @vdev: virtual handle
  4106. * @stats: type of statistics requested
  4107. *
  4108. * Return: integer
  4109. */
  4110. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4111. {
  4112. int host_stats;
  4113. int fw_stats;
  4114. if (stats >= CDP_TXRX_MAX_STATS)
  4115. return 0;
  4116. /*
  4117. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4118. * has to be updated if new FW HTT stats added
  4119. */
  4120. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4121. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4122. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4123. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4124. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4125. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4126. stats, fw_stats, host_stats);
  4127. if (fw_stats != TXRX_FW_STATS_INVALID)
  4128. return dp_fw_stats_process(vdev, fw_stats);
  4129. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4130. (host_stats <= TXRX_HOST_STATS_MAX))
  4131. return dp_print_host_stats(vdev, host_stats);
  4132. else
  4133. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4134. "Wrong Input for TxRx Stats");
  4135. return 0;
  4136. }
  4137. /*
  4138. * dp_print_napi_stats(): NAPI stats
  4139. * @soc - soc handle
  4140. */
  4141. static void dp_print_napi_stats(struct dp_soc *soc)
  4142. {
  4143. hif_print_napi_stats(soc->hif_handle);
  4144. }
  4145. /*
  4146. * dp_print_per_ring_stats(): Packet count per ring
  4147. * @soc - soc handle
  4148. */
  4149. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4150. {
  4151. uint8_t core, ring;
  4152. uint64_t total_packets;
  4153. DP_TRACE(FATAL, "Reo packets per ring:");
  4154. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4155. total_packets = 0;
  4156. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4157. for (core = 0; core < NR_CPUS; core++) {
  4158. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4159. core, soc->stats.rx.ring_packets[core][ring]);
  4160. total_packets += soc->stats.rx.ring_packets[core][ring];
  4161. }
  4162. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4163. ring, total_packets);
  4164. }
  4165. }
  4166. /*
  4167. * dp_txrx_path_stats() - Function to display dump stats
  4168. * @soc - soc handle
  4169. *
  4170. * return: none
  4171. */
  4172. static void dp_txrx_path_stats(struct dp_soc *soc)
  4173. {
  4174. uint8_t error_code;
  4175. uint8_t loop_pdev;
  4176. struct dp_pdev *pdev;
  4177. uint8_t i;
  4178. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4179. pdev = soc->pdev_list[loop_pdev];
  4180. dp_aggregate_pdev_stats(pdev);
  4181. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4182. "Tx path Statistics:");
  4183. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4184. pdev->stats.tx_i.rcvd.num,
  4185. pdev->stats.tx_i.rcvd.bytes);
  4186. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4187. pdev->stats.tx_i.processed.num,
  4188. pdev->stats.tx_i.processed.bytes);
  4189. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4190. pdev->stats.tx.tx_success.num,
  4191. pdev->stats.tx.tx_success.bytes);
  4192. DP_TRACE(FATAL, "Dropped in host:");
  4193. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4194. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4195. DP_TRACE(FATAL, "Descriptor not available: %u",
  4196. pdev->stats.tx_i.dropped.desc_na);
  4197. DP_TRACE(FATAL, "Ring full: %u",
  4198. pdev->stats.tx_i.dropped.ring_full);
  4199. DP_TRACE(FATAL, "Enqueue fail: %u",
  4200. pdev->stats.tx_i.dropped.enqueue_fail);
  4201. DP_TRACE(FATAL, "DMA Error: %u",
  4202. pdev->stats.tx_i.dropped.dma_error);
  4203. DP_TRACE(FATAL, "Dropped in hardware:");
  4204. DP_TRACE(FATAL, "total packets dropped: %u",
  4205. pdev->stats.tx.tx_failed);
  4206. DP_TRACE(FATAL, "mpdu age out: %u",
  4207. pdev->stats.tx.dropped.age_out);
  4208. DP_TRACE(FATAL, "firmware removed: %u",
  4209. pdev->stats.tx.dropped.fw_rem);
  4210. DP_TRACE(FATAL, "firmware removed tx: %u",
  4211. pdev->stats.tx.dropped.fw_rem_tx);
  4212. DP_TRACE(FATAL, "firmware removed notx %u",
  4213. pdev->stats.tx.dropped.fw_rem_notx);
  4214. DP_TRACE(FATAL, "peer_invalid: %u",
  4215. pdev->soc->stats.tx.tx_invalid_peer.num);
  4216. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4217. DP_TRACE(FATAL, "Single Packet: %u",
  4218. pdev->stats.tx_comp_histogram.pkts_1);
  4219. DP_TRACE(FATAL, "2-20 Packets: %u",
  4220. pdev->stats.tx_comp_histogram.pkts_2_20);
  4221. DP_TRACE(FATAL, "21-40 Packets: %u",
  4222. pdev->stats.tx_comp_histogram.pkts_21_40);
  4223. DP_TRACE(FATAL, "41-60 Packets: %u",
  4224. pdev->stats.tx_comp_histogram.pkts_41_60);
  4225. DP_TRACE(FATAL, "61-80 Packets: %u",
  4226. pdev->stats.tx_comp_histogram.pkts_61_80);
  4227. DP_TRACE(FATAL, "81-100 Packets: %u",
  4228. pdev->stats.tx_comp_histogram.pkts_81_100);
  4229. DP_TRACE(FATAL, "101-200 Packets: %u",
  4230. pdev->stats.tx_comp_histogram.pkts_101_200);
  4231. DP_TRACE(FATAL, " 201+ Packets: %u",
  4232. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4233. DP_TRACE(FATAL, "Rx path statistics");
  4234. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4235. pdev->stats.rx.to_stack.num,
  4236. pdev->stats.rx.to_stack.bytes);
  4237. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4238. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4239. i, pdev->stats.rx.rcvd_reo[i].num,
  4240. pdev->stats.rx.rcvd_reo[i].bytes);
  4241. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4242. pdev->stats.rx.intra_bss.pkts.num,
  4243. pdev->stats.rx.intra_bss.pkts.bytes);
  4244. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4245. pdev->stats.rx.raw.num,
  4246. pdev->stats.rx.raw.bytes);
  4247. DP_TRACE(FATAL, "dropped: error %u msdus",
  4248. pdev->stats.rx.err.mic_err);
  4249. DP_TRACE(FATAL, "peer invalid %u",
  4250. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4251. DP_TRACE(FATAL, "Reo Statistics");
  4252. DP_TRACE(FATAL, "rbm error: %u msdus",
  4253. pdev->soc->stats.rx.err.invalid_rbm);
  4254. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4255. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4256. DP_TRACE(FATAL, "Reo errors");
  4257. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4258. error_code++) {
  4259. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4260. error_code,
  4261. pdev->soc->stats.rx.err.reo_error[error_code]);
  4262. }
  4263. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4264. error_code++) {
  4265. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4266. error_code,
  4267. pdev->soc->stats.rx.err
  4268. .rxdma_error[error_code]);
  4269. }
  4270. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4271. DP_TRACE(FATAL, "Single Packet: %u",
  4272. pdev->stats.rx_ind_histogram.pkts_1);
  4273. DP_TRACE(FATAL, "2-20 Packets: %u",
  4274. pdev->stats.rx_ind_histogram.pkts_2_20);
  4275. DP_TRACE(FATAL, "21-40 Packets: %u",
  4276. pdev->stats.rx_ind_histogram.pkts_21_40);
  4277. DP_TRACE(FATAL, "41-60 Packets: %u",
  4278. pdev->stats.rx_ind_histogram.pkts_41_60);
  4279. DP_TRACE(FATAL, "61-80 Packets: %u",
  4280. pdev->stats.rx_ind_histogram.pkts_61_80);
  4281. DP_TRACE(FATAL, "81-100 Packets: %u",
  4282. pdev->stats.rx_ind_histogram.pkts_81_100);
  4283. DP_TRACE(FATAL, "101-200 Packets: %u",
  4284. pdev->stats.rx_ind_histogram.pkts_101_200);
  4285. DP_TRACE(FATAL, " 201+ Packets: %u",
  4286. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4287. }
  4288. }
  4289. /*
  4290. * dp_txrx_dump_stats() - Dump statistics
  4291. * @value - Statistics option
  4292. */
  4293. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4294. {
  4295. struct dp_soc *soc =
  4296. (struct dp_soc *)psoc;
  4297. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4298. if (!soc) {
  4299. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4300. "%s: soc is NULL", __func__);
  4301. return QDF_STATUS_E_INVAL;
  4302. }
  4303. switch (value) {
  4304. case CDP_TXRX_PATH_STATS:
  4305. dp_txrx_path_stats(soc);
  4306. break;
  4307. case CDP_RX_RING_STATS:
  4308. dp_print_per_ring_stats(soc);
  4309. break;
  4310. case CDP_TXRX_TSO_STATS:
  4311. /* TODO: NOT IMPLEMENTED */
  4312. break;
  4313. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4314. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4315. break;
  4316. case CDP_DP_NAPI_STATS:
  4317. dp_print_napi_stats(soc);
  4318. break;
  4319. case CDP_TXRX_DESC_STATS:
  4320. /* TODO: NOT IMPLEMENTED */
  4321. break;
  4322. default:
  4323. status = QDF_STATUS_E_INVAL;
  4324. break;
  4325. }
  4326. return status;
  4327. }
  4328. static struct cdp_wds_ops dp_ops_wds = {
  4329. .vdev_set_wds = dp_vdev_set_wds,
  4330. };
  4331. /*
  4332. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4333. * @soc - datapath soc handle
  4334. * @peer - datapath peer handle
  4335. *
  4336. * Delete the AST entries belonging to a peer
  4337. */
  4338. #ifdef FEATURE_WDS
  4339. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4340. struct dp_peer *peer)
  4341. {
  4342. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4343. qdf_spin_lock_bh(&soc->ast_lock);
  4344. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4345. if (ast_entry->next_hop) {
  4346. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4347. peer->vdev->pdev->osif_pdev,
  4348. ast_entry->mac_addr.raw);
  4349. }
  4350. dp_peer_del_ast(soc, ast_entry);
  4351. }
  4352. qdf_spin_unlock_bh(&soc->ast_lock);
  4353. }
  4354. #else
  4355. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4356. struct dp_peer *peer)
  4357. {
  4358. }
  4359. #endif
  4360. #ifdef CONFIG_WIN
  4361. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4362. {
  4363. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4364. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4365. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4366. dp_peer_delete_ast_entries(soc, peer);
  4367. }
  4368. #endif
  4369. static struct cdp_cmn_ops dp_ops_cmn = {
  4370. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4371. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4372. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4373. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4374. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4375. .txrx_peer_create = dp_peer_create_wifi3,
  4376. .txrx_peer_setup = dp_peer_setup_wifi3,
  4377. #ifdef CONFIG_WIN
  4378. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4379. #else
  4380. .txrx_peer_teardown = NULL,
  4381. #endif
  4382. .txrx_peer_delete = dp_peer_delete_wifi3,
  4383. .txrx_vdev_register = dp_vdev_register_wifi3,
  4384. .txrx_soc_detach = dp_soc_detach_wifi3,
  4385. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4386. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4387. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4388. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4389. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4390. .delba_process = dp_delba_process_wifi3,
  4391. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4392. .flush_cache_rx_queue = NULL,
  4393. /* TODO: get API's for dscp-tid need to be added*/
  4394. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4395. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4396. .txrx_stats = dp_txrx_stats,
  4397. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4398. .display_stats = dp_txrx_dump_stats,
  4399. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4400. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4401. #ifdef DP_INTR_POLL_BASED
  4402. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4403. #else
  4404. .txrx_intr_attach = dp_soc_interrupt_attach,
  4405. #endif
  4406. .txrx_intr_detach = dp_soc_interrupt_detach,
  4407. .set_pn_check = dp_set_pn_check_wifi3,
  4408. /* TODO: Add other functions */
  4409. };
  4410. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4411. .txrx_peer_authorize = dp_peer_authorize,
  4412. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4413. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4414. #ifdef MESH_MODE_SUPPORT
  4415. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4416. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4417. #endif
  4418. .txrx_set_vdev_param = dp_set_vdev_param,
  4419. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4420. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4421. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4422. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4423. .txrx_update_filter_neighbour_peers =
  4424. dp_update_filter_neighbour_peers,
  4425. .txrx_get_sec_type = dp_get_sec_type,
  4426. /* TODO: Add other functions */
  4427. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4428. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4429. };
  4430. static struct cdp_me_ops dp_ops_me = {
  4431. #ifdef ATH_SUPPORT_IQUE
  4432. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4433. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4434. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4435. #endif
  4436. };
  4437. static struct cdp_mon_ops dp_ops_mon = {
  4438. .txrx_monitor_set_filter_ucast_data = NULL,
  4439. .txrx_monitor_set_filter_mcast_data = NULL,
  4440. .txrx_monitor_set_filter_non_data = NULL,
  4441. .txrx_monitor_get_filter_ucast_data = NULL,
  4442. .txrx_monitor_get_filter_mcast_data = NULL,
  4443. .txrx_monitor_get_filter_non_data = NULL,
  4444. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  4445. };
  4446. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4447. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4448. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4449. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4450. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4451. /* TODO */
  4452. };
  4453. static struct cdp_raw_ops dp_ops_raw = {
  4454. /* TODO */
  4455. };
  4456. #ifdef CONFIG_WIN
  4457. static struct cdp_pflow_ops dp_ops_pflow = {
  4458. /* TODO */
  4459. };
  4460. #endif /* CONFIG_WIN */
  4461. #ifdef FEATURE_RUNTIME_PM
  4462. /**
  4463. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  4464. * @opaque_pdev: DP pdev context
  4465. *
  4466. * DP is ready to runtime suspend if there are no pending TX packets.
  4467. *
  4468. * Return: QDF_STATUS
  4469. */
  4470. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  4471. {
  4472. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4473. struct dp_soc *soc = pdev->soc;
  4474. /* Call DP TX flow control API to check if there is any
  4475. pending packets */
  4476. if (soc->intr_mode == DP_INTR_POLL)
  4477. qdf_timer_stop(&soc->int_timer);
  4478. return QDF_STATUS_SUCCESS;
  4479. }
  4480. /**
  4481. * dp_runtime_resume() - ensure DP is ready to runtime resume
  4482. * @opaque_pdev: DP pdev context
  4483. *
  4484. * Resume DP for runtime PM.
  4485. *
  4486. * Return: QDF_STATUS
  4487. */
  4488. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  4489. {
  4490. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4491. struct dp_soc *soc = pdev->soc;
  4492. void *hal_srng;
  4493. int i;
  4494. if (soc->intr_mode == DP_INTR_POLL)
  4495. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4496. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  4497. hal_srng = soc->tcl_data_ring[i].hal_srng;
  4498. if (hal_srng) {
  4499. /* We actually only need to acquire the lock */
  4500. hal_srng_access_start(soc->hal_soc, hal_srng);
  4501. /* Update SRC ring head pointer for HW to send
  4502. all pending packets */
  4503. hal_srng_access_end(soc->hal_soc, hal_srng);
  4504. }
  4505. }
  4506. return QDF_STATUS_SUCCESS;
  4507. }
  4508. #endif /* FEATURE_RUNTIME_PM */
  4509. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4510. {
  4511. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4512. struct dp_soc *soc = pdev->soc;
  4513. if (soc->intr_mode == DP_INTR_POLL)
  4514. qdf_timer_stop(&soc->int_timer);
  4515. return QDF_STATUS_SUCCESS;
  4516. }
  4517. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4518. {
  4519. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4520. struct dp_soc *soc = pdev->soc;
  4521. if (soc->intr_mode == DP_INTR_POLL)
  4522. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4523. return QDF_STATUS_SUCCESS;
  4524. }
  4525. #ifndef CONFIG_WIN
  4526. static struct cdp_misc_ops dp_ops_misc = {
  4527. .get_opmode = dp_get_opmode,
  4528. #ifdef FEATURE_RUNTIME_PM
  4529. .runtime_suspend = dp_runtime_suspend,
  4530. .runtime_resume = dp_runtime_resume,
  4531. #endif /* FEATURE_RUNTIME_PM */
  4532. };
  4533. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4534. /* WIFI 3.0 DP implement as required. */
  4535. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4536. .register_pause_cb = dp_txrx_register_pause_cb,
  4537. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4538. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4539. };
  4540. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4541. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4542. };
  4543. #ifdef IPA_OFFLOAD
  4544. static struct cdp_ipa_ops dp_ops_ipa = {
  4545. .ipa_get_resource = dp_ipa_get_resource,
  4546. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4547. .ipa_op_response = dp_ipa_op_response,
  4548. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4549. .ipa_get_stat = dp_ipa_get_stat,
  4550. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4551. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4552. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4553. .ipa_setup = dp_ipa_setup,
  4554. .ipa_cleanup = dp_ipa_cleanup,
  4555. .ipa_setup_iface = dp_ipa_setup_iface,
  4556. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4557. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4558. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4559. .ipa_set_perf_level = dp_ipa_set_perf_level
  4560. };
  4561. #endif
  4562. static struct cdp_bus_ops dp_ops_bus = {
  4563. .bus_suspend = dp_bus_suspend,
  4564. .bus_resume = dp_bus_resume
  4565. };
  4566. static struct cdp_ocb_ops dp_ops_ocb = {
  4567. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4568. };
  4569. static struct cdp_throttle_ops dp_ops_throttle = {
  4570. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4571. };
  4572. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4573. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4574. };
  4575. static struct cdp_cfg_ops dp_ops_cfg = {
  4576. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4577. };
  4578. static struct cdp_peer_ops dp_ops_peer = {
  4579. .register_peer = dp_register_peer,
  4580. .clear_peer = dp_clear_peer,
  4581. .find_peer_by_addr = dp_find_peer_by_addr,
  4582. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4583. .local_peer_id = dp_local_peer_id,
  4584. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4585. .peer_state_update = dp_peer_state_update,
  4586. .get_vdevid = dp_get_vdevid,
  4587. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4588. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4589. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4590. .get_peer_state = dp_get_peer_state,
  4591. .last_assoc_received = dp_get_last_assoc_received,
  4592. .last_disassoc_received = dp_get_last_disassoc_received,
  4593. .last_deauth_received = dp_get_last_deauth_received,
  4594. };
  4595. #endif
  4596. static struct cdp_ops dp_txrx_ops = {
  4597. .cmn_drv_ops = &dp_ops_cmn,
  4598. .ctrl_ops = &dp_ops_ctrl,
  4599. .me_ops = &dp_ops_me,
  4600. .mon_ops = &dp_ops_mon,
  4601. .host_stats_ops = &dp_ops_host_stats,
  4602. .wds_ops = &dp_ops_wds,
  4603. .raw_ops = &dp_ops_raw,
  4604. #ifdef CONFIG_WIN
  4605. .pflow_ops = &dp_ops_pflow,
  4606. #endif /* CONFIG_WIN */
  4607. #ifndef CONFIG_WIN
  4608. .misc_ops = &dp_ops_misc,
  4609. .cfg_ops = &dp_ops_cfg,
  4610. .flowctl_ops = &dp_ops_flowctl,
  4611. .l_flowctl_ops = &dp_ops_l_flowctl,
  4612. #ifdef IPA_OFFLOAD
  4613. .ipa_ops = &dp_ops_ipa,
  4614. #endif
  4615. .bus_ops = &dp_ops_bus,
  4616. .ocb_ops = &dp_ops_ocb,
  4617. .peer_ops = &dp_ops_peer,
  4618. .throttle_ops = &dp_ops_throttle,
  4619. .mob_stats_ops = &dp_ops_mob_stats,
  4620. #endif
  4621. };
  4622. /*
  4623. * dp_soc_set_txrx_ring_map()
  4624. * @dp_soc: DP handler for soc
  4625. *
  4626. * Return: Void
  4627. */
  4628. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4629. {
  4630. uint32_t i;
  4631. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4632. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4633. }
  4634. }
  4635. /*
  4636. * dp_soc_attach_wifi3() - Attach txrx SOC
  4637. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4638. * @htc_handle: Opaque HTC handle
  4639. * @hif_handle: Opaque HIF handle
  4640. * @qdf_osdev: QDF device
  4641. *
  4642. * Return: DP SOC handle on success, NULL on failure
  4643. */
  4644. /*
  4645. * Local prototype added to temporarily address warning caused by
  4646. * -Wmissing-prototypes. A more correct solution, namely to expose
  4647. * a prototype in an appropriate header file, will come later.
  4648. */
  4649. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4650. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4651. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4652. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4653. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4654. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4655. {
  4656. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4657. if (!soc) {
  4658. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4659. FL("DP SOC memory allocation failed"));
  4660. goto fail0;
  4661. }
  4662. soc->cdp_soc.ops = &dp_txrx_ops;
  4663. soc->cdp_soc.ol_ops = ol_ops;
  4664. soc->osif_soc = osif_soc;
  4665. soc->osdev = qdf_osdev;
  4666. soc->hif_handle = hif_handle;
  4667. soc->psoc = psoc;
  4668. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4669. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4670. soc->hal_soc, qdf_osdev);
  4671. if (!soc->htt_handle) {
  4672. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4673. FL("HTT attach failed"));
  4674. goto fail1;
  4675. }
  4676. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4677. if (!soc->wlan_cfg_ctx) {
  4678. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4679. FL("wlan_cfg_soc_attach failed"));
  4680. goto fail2;
  4681. }
  4682. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  4683. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4684. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4685. CDP_CFG_MAX_PEER_ID);
  4686. if (ret != -EINVAL) {
  4687. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4688. }
  4689. }
  4690. qdf_spinlock_create(&soc->peer_ref_mutex);
  4691. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4692. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4693. /* fill the tx/rx cpu ring map*/
  4694. dp_soc_set_txrx_ring_map(soc);
  4695. qdf_spinlock_create(&soc->htt_stats.lock);
  4696. /* initialize work queue for stats processing */
  4697. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4698. return (void *)soc;
  4699. fail2:
  4700. htt_soc_detach(soc->htt_handle);
  4701. fail1:
  4702. qdf_mem_free(soc);
  4703. fail0:
  4704. return NULL;
  4705. }
  4706. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4707. /*
  4708. * dp_set_pktlog_wifi3() - attach txrx vdev
  4709. * @pdev: Datapath PDEV handle
  4710. * @event: which event's notifications are being subscribed to
  4711. * @enable: WDI event subscribe or not. (True or False)
  4712. *
  4713. * Return: Success, NULL on failure
  4714. */
  4715. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4716. bool enable)
  4717. {
  4718. struct dp_soc *soc = pdev->soc;
  4719. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4720. if (enable) {
  4721. switch (event) {
  4722. case WDI_EVENT_RX_DESC:
  4723. if (pdev->monitor_vdev) {
  4724. /* Nothing needs to be done if monitor mode is
  4725. * enabled
  4726. */
  4727. return 0;
  4728. }
  4729. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4730. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4731. htt_tlv_filter.mpdu_start = 1;
  4732. htt_tlv_filter.msdu_start = 1;
  4733. htt_tlv_filter.msdu_end = 1;
  4734. htt_tlv_filter.mpdu_end = 1;
  4735. htt_tlv_filter.packet_header = 1;
  4736. htt_tlv_filter.attention = 1;
  4737. htt_tlv_filter.ppdu_start = 1;
  4738. htt_tlv_filter.ppdu_end = 1;
  4739. htt_tlv_filter.ppdu_end_user_stats = 1;
  4740. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4741. htt_tlv_filter.ppdu_end_status_done = 1;
  4742. htt_tlv_filter.enable_fp = 1;
  4743. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4744. pdev->pdev_id,
  4745. pdev->rxdma_mon_status_ring.hal_srng,
  4746. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4747. &htt_tlv_filter);
  4748. }
  4749. break;
  4750. case WDI_EVENT_LITE_RX:
  4751. if (pdev->monitor_vdev) {
  4752. /* Nothing needs to be done if monitor mode is
  4753. * enabled
  4754. */
  4755. return 0;
  4756. }
  4757. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4758. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4759. htt_tlv_filter.ppdu_start = 1;
  4760. htt_tlv_filter.ppdu_end = 1;
  4761. htt_tlv_filter.ppdu_end_user_stats = 1;
  4762. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4763. htt_tlv_filter.ppdu_end_status_done = 1;
  4764. htt_tlv_filter.enable_fp = 1;
  4765. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4766. pdev->pdev_id,
  4767. pdev->rxdma_mon_status_ring.hal_srng,
  4768. RXDMA_MONITOR_STATUS,
  4769. RX_BUFFER_SIZE_PKTLOG_LITE,
  4770. &htt_tlv_filter);
  4771. }
  4772. break;
  4773. case WDI_EVENT_LITE_T2H:
  4774. if (pdev->monitor_vdev) {
  4775. /* Nothing needs to be done if monitor mode is
  4776. * enabled
  4777. */
  4778. return 0;
  4779. }
  4780. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4781. * passing value 0xffff. Once these macros will define in htt
  4782. * header file will use proper macros
  4783. */
  4784. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4785. break;
  4786. default:
  4787. /* Nothing needs to be done for other pktlog types */
  4788. break;
  4789. }
  4790. } else {
  4791. switch (event) {
  4792. case WDI_EVENT_RX_DESC:
  4793. case WDI_EVENT_LITE_RX:
  4794. if (pdev->monitor_vdev) {
  4795. /* Nothing needs to be done if monitor mode is
  4796. * enabled
  4797. */
  4798. return 0;
  4799. }
  4800. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4801. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4802. /* htt_tlv_filter is initialized to 0 */
  4803. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4804. pdev->pdev_id,
  4805. pdev->rxdma_mon_status_ring.hal_srng,
  4806. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4807. &htt_tlv_filter);
  4808. }
  4809. break;
  4810. case WDI_EVENT_LITE_T2H:
  4811. if (pdev->monitor_vdev) {
  4812. /* Nothing needs to be done if monitor mode is
  4813. * enabled
  4814. */
  4815. return 0;
  4816. }
  4817. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4818. * passing value 0. Once these macros will define in htt
  4819. * header file will use proper macros
  4820. */
  4821. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4822. break;
  4823. default:
  4824. /* Nothing needs to be done for other pktlog types */
  4825. break;
  4826. }
  4827. }
  4828. return 0;
  4829. }
  4830. #endif