3efecb742f5210b85157b9c125c3717543f03130

Introduce Threshold IRQ and compose dynamically allocated buffer with CCI BURST WRITE Commands and finally write to the CCI HW register and manage Threshold Interrupts in optimized way. So, that SW Driver latencies will not affect the I2C BURST WRITE functionality. CRs-Fixed: 3562709 Change-Id: I5749ba3b61e28d8f2c1075f46f470f5a9c5bd6b5 Signed-off-by: Lokesh Kumar Aakulu <quic_lkumar@quicinc.com> (cherry picked from commit 1e4f481db9076c766b7300bb65364a13a61247c1)
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