android_kernel_samsung_sm8650-modules/qcom/opensource/graphics-kernel/adreno-gpulist.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved.
 * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#define ANY_ID (~0)

#define DEFINE_ADRENO_REV(_rev, _core, _major, _minor, _patchid) \
	.gpurev = _rev, .core = _core, .major = _major, .minor = _minor, \
	.patchid = _patchid

#define DEFINE_DEPRECATED_CORE(_name, _rev, _core, _major, _minor, _patchid) \
static const struct adreno_gpu_core adreno_gpu_core_##_name = { \
	DEFINE_ADRENO_REV(_rev, _core, _major, _minor, _patchid), \
	.features = ADRENO_DEPRECATED, \
}

#define MHZ_TO_KBPS(mhz, w) ((u64)(mhz * 1000000ULL * w) / (1024))

static const struct kgsl_regmap_list a306_vbif_regs[] = {
	{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },
	{ A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000A },
	{ A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000A },
};

static const struct adreno_a3xx_core adreno_gpu_core_a306 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A306, 3, 0, 6, 0),
		.features = ADRENO_SOFT_FAULT_DETECT,
		.gpudev = &adreno_a3xx_gpudev,
		.perfcounters = &adreno_a3xx_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_128K,
		.bus_width = 0,
		.snapshot_size = 600 * SZ_1K,
	},
	.pm4fw_name = "a300_pm4.fw",
	.pfpfw_name = "a300_pfp.fw",
	.vbif = a306_vbif_regs,
	.vbif_count = ARRAY_SIZE(a306_vbif_regs),
};

static const struct kgsl_regmap_list a306a_vbif_regs[] = {
	{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },
	{ A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000010 },
	{ A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000010 },
};

static const struct adreno_a3xx_core adreno_gpu_core_a306a = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A306A, 3, 0, 6, 0x20),
		.features = ADRENO_SOFT_FAULT_DETECT,
		.gpudev = &adreno_a3xx_gpudev,
		.perfcounters = &adreno_a3xx_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_128K,
		.bus_width = 16,
		.snapshot_size = 600 * SZ_1K,
	},
	.pm4fw_name = "a300_pm4.fw",
	.pfpfw_name = "a300_pfp.fw",
	.vbif = a306a_vbif_regs,
	.vbif_count = ARRAY_SIZE(a306a_vbif_regs),
};

static const struct kgsl_regmap_list a304_vbif_regs[] = {
	{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },
};

static const struct adreno_a3xx_core adreno_gpu_core_a304 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A304, 3, 0, 4, 0),
		.features = ADRENO_SOFT_FAULT_DETECT,
		.gpudev = &adreno_a3xx_gpudev,
		.perfcounters = &adreno_a3xx_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = (SZ_64K + SZ_32K),
		.bus_width = 0,
		.snapshot_size = 600 * SZ_1K,
	},
	.pm4fw_name = "a300_pm4.fw",
	.pfpfw_name = "a300_pfp.fw",
	.vbif = a304_vbif_regs,
	.vbif_count = ARRAY_SIZE(a304_vbif_regs),
};

DEFINE_DEPRECATED_CORE(a405, ADRENO_REV_A405, 4, 0, 5, ANY_ID);
DEFINE_DEPRECATED_CORE(a418, ADRENO_REV_A418, 4, 1, 8, ANY_ID);
DEFINE_DEPRECATED_CORE(a420, ADRENO_REV_A420, 4, 2, 0, ANY_ID);
DEFINE_DEPRECATED_CORE(a430, ADRENO_REV_A430, 4, 3, 0, ANY_ID);
DEFINE_DEPRECATED_CORE(a530v1, ADRENO_REV_A530, 5, 3, 0, 0);

static const struct kgsl_regmap_list a530_hwcg_regs[] = {
	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL_SP2, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL_SP3, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},
	{A5XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220},
	{A5XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220},
	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
	{A5XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
	{A5XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_TP2, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_TP3, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
	{A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},
	{A5XX_RBBM_CLOCK_CNTL3_TP2, 0x00002222},
	{A5XX_RBBM_CLOCK_CNTL3_TP3, 0x00002222},
	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
	{A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},
	{A5XX_RBBM_CLOCK_HYST3_TP2, 0x00007777},
	{A5XX_RBBM_CLOCK_HYST3_TP3, 0x00007777},
	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
	{A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},
	{A5XX_RBBM_CLOCK_DELAY3_TP2, 0x00001111},
	{A5XX_RBBM_CLOCK_DELAY3_TP3, 0x00001111},
	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},
	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB2, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB3, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_CCU2, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_CCU3, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU2, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU3, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
};

/* VBIF control registers for a530, a510, a508, a505 and a506 */
static const struct kgsl_regmap_list a530_vbif_regs[] = {
	{A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003},
};

static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A530, 5, 3, 0, 1),
		.features = ADRENO_SPTP_PC | ADRENO_LM |
			ADRENO_PREEMPTION |
			ADRENO_CONTENT_PROTECTION,
		.gpudev = &adreno_a5xx_gpudev,
		.perfcounters = &adreno_a5xx_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_1M,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
	},
	.gpmu_tsens = 0x00060007,
	.max_power = 5448,
	.pm4fw_name = "a530_pm4.fw",
	.pfpfw_name = "a530_pfp.fw",
	.gpmufw_name = "a530_gpmu.fw2",
	.regfw_name = "a530v2_seq.fw2",
	.zap_name = "a530_zap.mdt",
	.hwcg = a530_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a530_hwcg_regs),
	.vbif = a530_vbif_regs,
	.vbif_count = ARRAY_SIZE(a530_vbif_regs),
	.highest_bank_bit = 15,
};

static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A530, 5, 3, 0, ANY_ID),
		.features = ADRENO_SPTP_PC | ADRENO_LM |
			ADRENO_PREEMPTION |
			ADRENO_CONTENT_PROTECTION,
		.gpudev = &adreno_a5xx_gpudev,
		.perfcounters = &adreno_a5xx_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_1M,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
	},
	.gpmu_tsens = 0x00060007,
	.max_power = 5448,
	.pm4fw_name = "a530_pm4.fw",
	.pfpfw_name = "a530_pfp.fw",
	.gpmufw_name = "a530v3_gpmu.fw2",
	.regfw_name = "a530v3_seq.fw2",
	.zap_name = "a530_zap.mdt",
	.hwcg = a530_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a530_hwcg_regs),
	.vbif = a530_vbif_regs,
	.vbif_count = ARRAY_SIZE(a530_vbif_regs),
	.highest_bank_bit = 15,
};

/* For a505, a506 and a508 */
static const struct kgsl_regmap_list a50x_hwcg_regs[] = {
	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00FFFFF4},
	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}
};

static const struct adreno_a5xx_core adreno_gpu_core_a505 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A505, 5, 0, 5, ANY_ID),
		.features = ADRENO_PREEMPTION,
		.gpudev = &adreno_a5xx_gpudev,
		.perfcounters = &adreno_a5xx_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = (SZ_128K + SZ_8K),
		.bus_width = 16,
		.snapshot_size = SZ_1M,
	},
	.pm4fw_name = "a530_pm4.fw",
	.pfpfw_name = "a530_pfp.fw",
	.hwcg = a50x_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a50x_hwcg_regs),
	.vbif = a530_vbif_regs,
	.vbif_count = ARRAY_SIZE(a530_vbif_regs),
};

static const struct adreno_a5xx_core adreno_gpu_core_a506 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A506, 5, 0, 6, ANY_ID),
		.features = ADRENO_PREEMPTION |
			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
		.gpudev = &adreno_a5xx_gpudev,
		.perfcounters = &adreno_a5xx_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = (SZ_128K + SZ_8K),
		.bus_width = 16,
		.snapshot_size = SZ_1M,
	},
	.pm4fw_name = "a530_pm4.fw",
	.pfpfw_name = "a530_pfp.fw",
	.zap_name = "a506_zap.mdt",
	.hwcg = a50x_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a50x_hwcg_regs),
	.vbif = a530_vbif_regs,
	.vbif_count = ARRAY_SIZE(a530_vbif_regs),
	.highest_bank_bit = 14,
};

static const struct kgsl_regmap_list a510_hwcg_regs[] = {
	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},
	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
	{A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},
	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
	{A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},
	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
	{A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},
	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},
	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
};

static const struct adreno_a5xx_core adreno_gpu_core_a510 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A510, 5, 1, 0, ANY_ID),
		.gpudev = &adreno_a5xx_gpudev,
		.perfcounters = &adreno_a5xx_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_256K,
		.bus_width = 16,
		.snapshot_size = SZ_1M,
	},
	.pm4fw_name = "a530_pm4.fw",
	.pfpfw_name = "a530_pfp.fw",
	.hwcg = a510_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a510_hwcg_regs),
	.vbif = a530_vbif_regs,
	.vbif_count = ARRAY_SIZE(a530_vbif_regs),
};

DEFINE_DEPRECATED_CORE(a540v1, ADRENO_REV_A540, 5, 4, 0, 0);

static const struct kgsl_regmap_list a540_hwcg_regs[] = {
	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL_SP2, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL_SP3, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},
	{A5XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220},
	{A5XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220},
	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
	{A5XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
	{A5XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_TP2, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_TP3, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
	{A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},
	{A5XX_RBBM_CLOCK_CNTL3_TP2, 0x00002222},
	{A5XX_RBBM_CLOCK_CNTL3_TP3, 0x00002222},
	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
	{A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},
	{A5XX_RBBM_CLOCK_HYST3_TP2, 0x00007777},
	{A5XX_RBBM_CLOCK_HYST3_TP3, 0x00007777},
	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
	{A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},
	{A5XX_RBBM_CLOCK_DELAY3_TP2, 0x00001111},
	{A5XX_RBBM_CLOCK_DELAY3_TP3, 0x00001111},
	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},
	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB2, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB3, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_CCU2, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_CCU3, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU2, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU3, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A5XX_RBBM_CLOCK_HYST_GPMU, 0x00000222},
	{A5XX_RBBM_CLOCK_DELAY_GPMU, 0x00000770},
	{A5XX_RBBM_CLOCK_HYST_GPMU, 0x00000004},
};

static const struct kgsl_regmap_list a540_vbif_regs[] = {
	{A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003},
	{A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009},
};

static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A540, 5, 4, 0, ANY_ID),
		.features = ADRENO_PREEMPTION |
			ADRENO_CONTENT_PROTECTION |
			ADRENO_SPTP_PC,
		.gpudev = &adreno_a5xx_gpudev,
		.perfcounters = &adreno_a5xx_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_1M,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
	},
	.gpmu_tsens = 0x000c000d,
	.max_power = 5448,
	.pm4fw_name = "a530_pm4.fw",
	.pfpfw_name = "a530_pfp.fw",
	.gpmufw_name = "a540_gpmu.fw2",
	.zap_name = "a540_zap.mdt",
	.hwcg = a540_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a540_hwcg_regs),
	.vbif = a540_vbif_regs,
	.vbif_count = ARRAY_SIZE(a540_vbif_regs),
	.highest_bank_bit = 15,
};

static const struct kgsl_regmap_list a512_hwcg_regs[] = {
	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},
	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},
	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},
	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
	{A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},
	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
	{A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},
	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
	{A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},
	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},
	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},
	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},
	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},
	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},
	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
};

static const struct adreno_a5xx_core adreno_gpu_core_a512 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A512, 5, 1, 2, ANY_ID),
		.features = ADRENO_PREEMPTION |
			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
		.gpudev = &adreno_a5xx_gpudev,
		.perfcounters = &adreno_a5xx_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = (SZ_256K + SZ_16K),
		.bus_width = 32,
		.snapshot_size = SZ_1M,
	},
	.pm4fw_name = "a530_pm4.fw",
	.pfpfw_name = "a530_pfp.fw",
	.zap_name = "a512_zap.mdt",
	.hwcg = a512_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a512_hwcg_regs),
	.highest_bank_bit = 14,
};

static const struct adreno_a5xx_core adreno_gpu_core_a508 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A508, 5, 0, 8, ANY_ID),
		.features = ADRENO_PREEMPTION |
			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
		.gpudev = &adreno_a5xx_gpudev,
		.perfcounters = &adreno_a5xx_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = (SZ_128K + SZ_8K),
		.bus_width = 32,
		.snapshot_size = SZ_1M,
	},
	.pm4fw_name = "a530_pm4.fw",
	.pfpfw_name = "a530_pfp.fw",
	.zap_name = "a508_zap.mdt",
	.hwcg = a50x_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a50x_hwcg_regs),
	.vbif = a530_vbif_regs,
	.vbif_count = ARRAY_SIZE(a530_vbif_regs),
	.highest_bank_bit = 14,
};

DEFINE_DEPRECATED_CORE(a630v1, ADRENO_REV_A630, 6, 3, 0, 0);

static const struct kgsl_regmap_list a630_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL_SP2, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL_SP3, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
	{A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
	{A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
	{A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
	{A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
	{A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
	{A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
	{A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
	{A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
	{A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
	{A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
	{A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
	{A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
	{A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
	{A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
	{A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
	{A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
	{A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
	{A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
	{A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
	{A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
};

static const struct kgsl_regmap_list a630_vbif_regs[] = {
	{A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009},
	{A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3},
};


/* For a615, a616, a618, A619, a630, a640 and a680 */
static const struct adreno_protected_regs a630_protected_regs[] = {
	{ A6XX_CP_PROTECT_REG + 0, 0x00000, 0x004ff, 0 },
	{ A6XX_CP_PROTECT_REG + 1, 0x00501, 0x00506, 0 },
	{ A6XX_CP_PROTECT_REG + 2, 0x0050b, 0x007ff, 0 },
	{ A6XX_CP_PROTECT_REG + 3, 0x0050e, 0x0050e, 1 },
	{ A6XX_CP_PROTECT_REG + 4, 0x00510, 0x00510, 1 },
	{ A6XX_CP_PROTECT_REG + 5, 0x00534, 0x00534, 1 },
	{ A6XX_CP_PROTECT_REG + 6, 0x00800, 0x00882, 1 },
	{ A6XX_CP_PROTECT_REG + 7, 0x008a0, 0x008a8, 1 },
	{ A6XX_CP_PROTECT_REG + 8, 0x008ab, 0x008cf, 1 },
	{ A6XX_CP_PROTECT_REG + 9, 0x008d0, 0x0098c, 0 },
	{ A6XX_CP_PROTECT_REG + 10, 0x00900, 0x0094d, 1 },
	{ A6XX_CP_PROTECT_REG + 11, 0x0098d, 0x00bff, 1 },
	{ A6XX_CP_PROTECT_REG + 12, 0x00e00, 0x00e01, 1 },
	{ A6XX_CP_PROTECT_REG + 13, 0x00e03, 0x00e0f, 1 },
	{ A6XX_CP_PROTECT_REG + 14, 0x03c00, 0x03cc3, 1 },
	{ A6XX_CP_PROTECT_REG + 15, 0x03cc4, 0x05cc3, 0 },
	{ A6XX_CP_PROTECT_REG + 16, 0x08630, 0x087ff, 1 },
	{ A6XX_CP_PROTECT_REG + 17, 0x08e00, 0x08e00, 1 },
	{ A6XX_CP_PROTECT_REG + 18, 0x08e08, 0x08e08, 1 },
	{ A6XX_CP_PROTECT_REG + 19, 0x08e50, 0x08e6f, 1 },
	{ A6XX_CP_PROTECT_REG + 20, 0x09624, 0x097ff, 1 },
	{ A6XX_CP_PROTECT_REG + 21, 0x09e70, 0x09e71, 1 },
	{ A6XX_CP_PROTECT_REG + 22, 0x09e78, 0x09fff, 1 },
	{ A6XX_CP_PROTECT_REG + 23, 0x0a630, 0x0a7ff, 1 },
	{ A6XX_CP_PROTECT_REG + 24, 0x0ae02, 0x0ae02, 1 },
	{ A6XX_CP_PROTECT_REG + 25, 0x0ae50, 0x0b17f, 1 },
	{ A6XX_CP_PROTECT_REG + 26, 0x0b604, 0x0b604, 1 },
	{ A6XX_CP_PROTECT_REG + 27, 0x0be02, 0x0be03, 1 },
	{ A6XX_CP_PROTECT_REG + 28, 0x0be20, 0x0d5ff, 1 },
	{ A6XX_CP_PROTECT_REG + 29, 0x0f000, 0x0fbff, 1 },
	{ A6XX_CP_PROTECT_REG + 30, 0x0fc00, 0x11bff, 0 },
	{ A6XX_CP_PROTECT_REG + 31, 0x11c00, 0x11c00, 1 },
	{ 0 },
};

static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A630, 6, 3, 0, ANY_ID),
		.features = ADRENO_IFPC | ADRENO_CONTENT_PROTECTION |
			ADRENO_IOCOHERENT | ADRENO_PREEMPTION,
		.gpudev = &adreno_a630_gpudev.base,
		.perfcounters = &adreno_a630_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_1M,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
	},
	.prim_fifo_threshold = 0x0018000,
	.gmu_major = 1,
	.gmu_minor = 3,
	.sqefw_name = "a630_sqe.fw",
	.gmufw_name = "a630_gmu.bin",
	.zap_name = "a630_zap.mdt",
	.hwcg = a630_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a630_hwcg_regs),
	.vbif = a630_vbif_regs,
	.vbif_count = ARRAY_SIZE(a630_vbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = a630_protected_regs,
	.highest_bank_bit = 15,
};

/* For a615, a616, a618 and a619 */
static const struct kgsl_regmap_list a615_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_CNTL_SP0,  0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A6XX_RBBM_CLOCK_HYST_SP0,  0x0000F3CF},
	{A6XX_RBBM_CLOCK_CNTL_TP0,  0x02222222},
	{A6XX_RBBM_CLOCK_CNTL_TP1,  0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
	{A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
	{A6XX_RBBM_CLOCK_HYST_TP0,  0x77777777},
	{A6XX_RBBM_CLOCK_HYST_TP1,  0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
	{A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
	{A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
	{A6XX_RBBM_CLOCK_CNTL_UCHE,  0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
	{A6XX_RBBM_CLOCK_HYST_UCHE,  0x00000004},
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
	{A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
	{A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
	{A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}
};

/* For a615, a616, a618 and a619 */
static const struct kgsl_regmap_list a615_gbif_regs[] = {
	{A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3},
};

static const struct adreno_a6xx_core adreno_gpu_core_a615 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A615, 6, 1, 5, ANY_ID),
		.features = ADRENO_PREEMPTION |
			ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
			ADRENO_IOCOHERENT,
		.gpudev = &adreno_a630_gpudev.base,
		.perfcounters = &adreno_a6xx_legacy_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_512K,
		.bus_width = 32,
		.snapshot_size = 600 * SZ_1K,
	},
	.prim_fifo_threshold = 0x0018000,
	.gmu_major = 1,
	.gmu_minor = 3,
	.sqefw_name = "a630_sqe.fw",
	.gmufw_name = "a630_gmu.bin",
	.zap_name = "a615_zap.mdt",
	.hwcg = a615_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a615_hwcg_regs),
	.vbif = a615_gbif_regs,
	.vbif_count = ARRAY_SIZE(a615_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = a630_protected_regs,
	.highest_bank_bit = 14,
};

static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A618, 6, 1, 8, ANY_ID),
		.features = ADRENO_PREEMPTION |
			ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
			ADRENO_IOCOHERENT,
		.gpudev = &adreno_a630_gpudev.base,
		.perfcounters = &adreno_a6xx_legacy_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_512K,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
	},
	.prim_fifo_threshold = 0x0018000,
	.gmu_major = 1,
	.gmu_minor = 7,
	.sqefw_name = "a630_sqe.fw",
	.gmufw_name = "a630_gmu.bin",
	.zap_name = "a615_zap.mdt",
	.hwcg = a615_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a615_hwcg_regs),
	.vbif = a615_gbif_regs,
	.vbif_count = ARRAY_SIZE(a615_gbif_regs),
	.hang_detect_cycles = 0x3fffff,
	.protected_regs = a630_protected_regs,
	.highest_bank_bit = 14,
};

static const struct adreno_a6xx_core adreno_gpu_core_a619 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A619, 6, 1, 9, ANY_ID),
		.features = ADRENO_PREEMPTION |
			ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
			ADRENO_IOCOHERENT,
		.gpudev = &adreno_a630_gpudev.base,
		.perfcounters = &adreno_a6xx_legacy_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_512K,
		.bus_width = 32,
		.snapshot_size = SZ_2M,
	},
	.prim_fifo_threshold = 0x0018000,
	.gmu_major = 1,
	.gmu_minor = 9,
	.sqefw_name = "a630_sqe.fw",
	.gmufw_name = "a619_gmu.bin",
	.zap_name = "a615_zap.mdt",
	.hwcg = a615_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a615_hwcg_regs),
	.vbif = a615_gbif_regs,
	.vbif_count = ARRAY_SIZE(a615_gbif_regs),
	.hang_detect_cycles = 0x3fffff,
	.protected_regs = a630_protected_regs,
	.highest_bank_bit = 14,
};

static const struct adreno_a6xx_core adreno_gpu_core_a619_variant = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A619, 6, 1, 9, ANY_ID),
		.compatible = "qcom,adreno-gpu-a619-holi",
		.features =  ADRENO_PREEMPTION | ADRENO_CONTENT_PROTECTION,
		.gpudev = &adreno_a619_holi_gpudev,
		.perfcounters = &adreno_a6xx_legacy_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_512K,
		.bus_width = 32,
		.snapshot_size = SZ_2M,
	},
	.prim_fifo_threshold = 0x0018000,
	.sqefw_name = "a630_sqe.fw",
	.zap_name = "gen6_3_25_0_zap.mdt",
	.hwcg = a615_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a615_hwcg_regs),
	.vbif = a615_gbif_regs,
	.vbif_count = ARRAY_SIZE(a615_gbif_regs),
	.hang_detect_cycles = 0x3fffff,
	.protected_regs = a630_protected_regs,
	.gx_cpr_toggle = true,
	.highest_bank_bit = 14,
};

static const struct kgsl_regmap_list a620_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A6XX_RBBM_ISDB_CNT, 0x00000182},
	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
};

/* a620, a621 and a650 */
static const struct kgsl_regmap_list a650_gbif_regs[] = {
	{A6XX_GBIF_QSB_SIDE0, 0x00071620},
	{A6XX_GBIF_QSB_SIDE1, 0x00071620},
	{A6XX_GBIF_QSB_SIDE2, 0x00071620},
	{A6XX_GBIF_QSB_SIDE3, 0x00071620},
	{A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3},
};

/* These are for a620, a621 and a650 */
static const struct adreno_protected_regs a620_protected_regs[] = {
	{ A6XX_CP_PROTECT_REG + 0, 0x00000, 0x004ff, 0 },
	{ A6XX_CP_PROTECT_REG + 1, 0x00501, 0x00506, 0 },
	{ A6XX_CP_PROTECT_REG + 2, 0x0050b, 0x007ff, 0 },
	{ A6XX_CP_PROTECT_REG + 3, 0x0050e, 0x0050e, 1 },
	{ A6XX_CP_PROTECT_REG + 4, 0x00510, 0x00510, 1 },
	{ A6XX_CP_PROTECT_REG + 5, 0x00534, 0x00534, 1 },
	{ A6XX_CP_PROTECT_REG + 6, 0x00800, 0x00882, 1 },
	{ A6XX_CP_PROTECT_REG + 7, 0x008a0, 0x008a8, 1 },
	{ A6XX_CP_PROTECT_REG + 8, 0x008ab, 0x008cf, 1 },
	{ A6XX_CP_PROTECT_REG + 9, 0x008d0, 0x0098c, 0 },
	{ A6XX_CP_PROTECT_REG + 10, 0x00900, 0x0094d, 1 },
	{ A6XX_CP_PROTECT_REG + 11, 0x0098d, 0x00bff, 1 },
	{ A6XX_CP_PROTECT_REG + 12, 0x00e00, 0x00e01, 1 },
	{ A6XX_CP_PROTECT_REG + 13, 0x00e03, 0x00e0f, 1 },
	{ A6XX_CP_PROTECT_REG + 14, 0x03c00, 0x03cc3, 1 },
	{ A6XX_CP_PROTECT_REG + 15, 0x03cc4, 0x05cc3, 0 },
	{ A6XX_CP_PROTECT_REG + 16, 0x08630, 0x087ff, 1 },
	{ A6XX_CP_PROTECT_REG + 17, 0x08e00, 0x08e00, 1 },
	{ A6XX_CP_PROTECT_REG + 18, 0x08e08, 0x08e08, 1 },
	{ A6XX_CP_PROTECT_REG + 19, 0x08e50, 0x08e6f, 1 },
	{ A6XX_CP_PROTECT_REG + 20, 0x08e80, 0x090ff, 1 },
	{ A6XX_CP_PROTECT_REG + 21, 0x09624, 0x097ff, 1 },
	{ A6XX_CP_PROTECT_REG + 22, 0x09e60, 0x09e71, 1 },
	{ A6XX_CP_PROTECT_REG + 23, 0x09e78, 0x09fff, 1 },
	{ A6XX_CP_PROTECT_REG + 24, 0x0a630, 0x0a7ff, 1 },
	{ A6XX_CP_PROTECT_REG + 25, 0x0ae02, 0x0ae02, 1 },
	{ A6XX_CP_PROTECT_REG + 26, 0x0ae50, 0x0b17f, 1 },
	{ A6XX_CP_PROTECT_REG + 27, 0x0b604, 0x0b604, 1 },
	{ A6XX_CP_PROTECT_REG + 28, 0x0b608, 0x0b60f, 1 },
	{ A6XX_CP_PROTECT_REG + 29, 0x0be02, 0x0be03, 1 },
	{ A6XX_CP_PROTECT_REG + 30, 0x0be20, 0x0d5ff, 1 },
	{ A6XX_CP_PROTECT_REG + 31, 0x0f000, 0x0fbff, 1 },
	{ A6XX_CP_PROTECT_REG + 32, 0x0fc00, 0x11bff, 0 },
	{ A6XX_CP_PROTECT_REG + 33, 0x18400, 0x1a3ff, 1 },
	{ A6XX_CP_PROTECT_REG + 34, 0x1a800, 0x1c7ff, 1 },
	{ A6XX_CP_PROTECT_REG + 35, 0x1c800, 0x1e7ff, 1 },
	{ A6XX_CP_PROTECT_REG + 36, 0x1f400, 0x1f843, 1 },
	{ A6XX_CP_PROTECT_REG + 37, 0x1f844, 0x1f8bf, 0 },
	{ A6XX_CP_PROTECT_REG + 38, 0x1f887, 0x1f8a2, 1 },
	{ A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 },
	{ 0 },
};

static const struct adreno_a6xx_core adreno_gpu_core_a620 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A620, 6, 2, 0, ANY_ID),
		.features = ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |
			ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |
			ADRENO_APRIV,
		.gpudev = &adreno_a630_gpudev.base,
		.perfcounters = &adreno_a6xx_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_512K,
		.bus_width = 32,
		.snapshot_size = 2 * SZ_1M,
	},
	.prim_fifo_threshold = 0x0010000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a650_sqe.fw",
	.gmufw_name = "a650_gmu.bin",
	.zap_name = "a620_zap.mdt",
	.hwcg = a620_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a620_hwcg_regs),
	.vbif = a650_gbif_regs,
	.vbif_count = ARRAY_SIZE(a650_gbif_regs),
	.veto_fal10 = true,
	.hang_detect_cycles = 0x3ffff,
	.protected_regs = a620_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 14,
};

static const struct adreno_a6xx_core adreno_gpu_core_a621 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A621, 6, 2, 1, ANY_ID),
		.compatible = "qcom,adreno-gpu-a621",
		.features = ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |
			ADRENO_APRIV | ADRENO_LSR | ADRENO_PREEMPTION |
			ADRENO_IFPC,
		.gpudev = &adreno_a6xx_hwsched_gpudev.base,
		.perfcounters = &adreno_a6xx_hwsched_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_512K,
		.bus_width = 32,
		.snapshot_size = 2 * SZ_1M,
	},
	.prim_fifo_threshold = 0x0010000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a650_sqe.fw",
	.gmufw_name = "a621_gmu.bin",
	.zap_name = "a620_zap.mdt",
	.hwcg = a620_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a620_hwcg_regs),
	.vbif = a650_gbif_regs,
	.vbif_count = ARRAY_SIZE(a650_gbif_regs),
	.veto_fal10 = true,
	.pdc_in_aop = true,
	.hang_detect_cycles = 0x3ffff,
	.protected_regs = a620_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 13,
};

static const struct kgsl_regmap_list a640_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A6XX_RBBM_ISDB_CNT, 0x00000182},
	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
};

static const struct kgsl_regmap_list a680_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
	{A6XX_RBBM_CLOCK_HYST_TP0, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
	{A6XX_RBBM_ISDB_CNT, 0x00000182},
	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
	{A6XX_GMUGX_GMU_SP_RF_CONTROL_0, 0x00000001},
	{A6XX_GMUGX_GMU_SP_RF_CONTROL_1, 0x00000001},
};

/* These apply to a640, a680, a612, a610 and a702 */
static const struct kgsl_regmap_list a640_vbif_regs[] = {
	{A6XX_GBIF_QSB_SIDE0, 0x00071620},
	{A6XX_GBIF_QSB_SIDE1, 0x00071620},
	{A6XX_GBIF_QSB_SIDE2, 0x00071620},
	{A6XX_GBIF_QSB_SIDE3, 0x00071620},
	{A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3},
};

static const struct adreno_a6xx_core adreno_gpu_core_a640 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A640, 6, 4, 0, ANY_ID),
		.features = ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |
			ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_L3_VOTE,
		.gpudev = &adreno_a6xx_gmu_gpudev.base,
		.perfcounters = &adreno_a6xx_legacy_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_1M, //Verified 1MB
		.bus_width = 32,
		.snapshot_size = 2 * SZ_1M,
	},
	.prim_fifo_threshold = 0x00200000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a630_sqe.fw",
	.gmufw_name = "a640_gmu.bin",
	.zap_name = "a640_zap.mdt",
	.hwcg = a640_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a640_hwcg_regs),
	.vbif = a640_vbif_regs,
	.vbif_count = ARRAY_SIZE(a640_vbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = a630_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 15,
};

static const struct kgsl_regmap_list a650_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A6XX_RBBM_ISDB_CNT, 0x00000182},
	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
};

static const struct adreno_a6xx_core adreno_gpu_core_a650 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A650, 6, 5, 0, 0),
		.features = ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
			ADRENO_IFPC | ADRENO_APRIV | ADRENO_L3_VOTE,
		.gpudev = &adreno_a6xx_gmu_gpudev.base,
		.perfcounters = &adreno_a6xx_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
		.bus_width = 32,
		.snapshot_size = 2 * SZ_1M,
	},
	.prim_fifo_threshold = 0x00300000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a650_sqe.fw",
	.gmufw_name = "a650_gmu.bin",
	.zap_name = "a650_zap.mdt",
	.hwcg = a650_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a650_hwcg_regs),
	.vbif = a650_gbif_regs,
	.vbif_count = ARRAY_SIZE(a650_gbif_regs),
	.veto_fal10 = true,
	.pdc_in_aop = true,
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = a620_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 16,
};

static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A650, 6, 5, 0, ANY_ID),
		.features = ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
			ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |
			ADRENO_LM | ADRENO_APRIV | ADRENO_L3_VOTE,
		.gpudev = &adreno_a6xx_gmu_gpudev.base,
		.perfcounters = &adreno_a6xx_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
		.bus_width = 32,
		.snapshot_size = 2 * SZ_1M,
	},
	.prim_fifo_threshold = 0x00300000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a650_sqe.fw",
	.gmufw_name = "a650_gmu.bin",
	.zap_name = "a650_zap.mdt",
	.hwcg = a650_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a650_hwcg_regs),
	.vbif = a650_gbif_regs,
	.vbif_count = ARRAY_SIZE(a650_gbif_regs),
	.veto_fal10 = true,
	.pdc_in_aop = true,
	.hang_detect_cycles = 0x3ffff,
	.protected_regs = a620_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 16,
};

static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A680, 6, 8, 0, ANY_ID),
		.features = ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
			ADRENO_IFPC | ADRENO_PREEMPTION,
		.gpudev = &adreno_a6xx_gmu_gpudev.base,
		.perfcounters = &adreno_a6xx_legacy_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_2M,
		.bus_width = 32,
		.snapshot_size = SZ_2M,
	},
	.prim_fifo_threshold = 0x00400000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a630_sqe.fw",
	.gmufw_name = "a640_gmu.bin",
	.zap_name = "a640_zap.mdt",
	.hwcg = a680_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a680_hwcg_regs),
	.vbif = a640_vbif_regs,
	.vbif_count = ARRAY_SIZE(a640_vbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = a630_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 16,
};

static const struct kgsl_regmap_list a612_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A6XX_RBBM_ISDB_CNT, 0x00000182},
	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
};

static const struct adreno_a6xx_core adreno_gpu_core_a612 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A612, 6, 1, 2, ANY_ID),
		.features = ADRENO_CONTENT_PROTECTION |
			ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_IFPC,
		.gpudev = &adreno_a6xx_rgmu_gpudev,
		.perfcounters = &adreno_a6xx_legacy_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = (SZ_128K + SZ_4K),
		.bus_width = 32,
		.snapshot_size = SZ_1M,
	},
	.prim_fifo_threshold = 0x00080000,
	.sqefw_name = "a630_sqe.fw",
	.gmufw_name = "a612_rgmu.bin",
	.zap_name = "a612_zap.mdt",
	.hwcg = a612_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a612_hwcg_regs),
	.vbif = a640_vbif_regs,
	.vbif_count = ARRAY_SIZE(a640_vbif_regs),
	.hang_detect_cycles = 0x3fffff,
	.protected_regs = a630_protected_regs,
	.highest_bank_bit = 14,
};

static const struct adreno_a6xx_core adreno_gpu_core_a616 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A616, 6, 1, 6, ANY_ID),
		.features = ADRENO_PREEMPTION |
			ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
			ADRENO_IOCOHERENT,
		.gpudev = &adreno_a630_gpudev.base,
		.perfcounters = &adreno_a6xx_legacy_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = SZ_512K,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
	},
	.prim_fifo_threshold = 0x0018000,
	.gmu_major = 1,
	.gmu_minor = 3,
	.sqefw_name = "a630_sqe.fw",
	.gmufw_name = "a630_gmu.bin",
	.zap_name = "a615_zap.mdt",
	.hwcg = a615_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a615_hwcg_regs),
	.vbif = a615_gbif_regs,
	.vbif_count = ARRAY_SIZE(a615_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = a630_protected_regs,
	.highest_bank_bit = 14,
};

static const struct adreno_a6xx_core adreno_gpu_core_a610 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A610, 6, 1, 0, ANY_ID),
		.compatible = "qcom,adreno-gpu-a610",
		.features = ADRENO_CONTENT_PROTECTION |
			ADRENO_PREEMPTION,
		.gpudev = &adreno_a6xx_gpudev,
		.perfcounters = &adreno_a6xx_legacy_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = (SZ_128K + SZ_4K),
		.bus_width = 32,
		.snapshot_size = SZ_1M,
	},
	.prim_fifo_threshold = 0x00080000,
	.sqefw_name = "a630_sqe.fw",
	.zap_name = "a610_zap.mdt",
	.hwcg = a612_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a612_hwcg_regs),
	.vbif = a640_vbif_regs,
	.vbif_count = ARRAY_SIZE(a640_vbif_regs),
	.hang_detect_cycles = 0x3ffff,
	.protected_regs = a630_protected_regs,
	.highest_bank_bit = 14,
};

static const struct adreno_a6xx_core adreno_gpu_core_a611 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A611, 6, 1, 1, ANY_ID),
		.compatible = "qcom,adreno-gpu-a611",
		.features = ADRENO_CONTENT_PROTECTION |
			ADRENO_PREEMPTION,
		.gpudev = &adreno_a6xx_gpudev,
		.perfcounters = &adreno_a6xx_legacy_perfcounters,
		.uche_gmem_alignment = SZ_1M,
		.gmem_size = (SZ_128K + SZ_4K),
		.bus_width = 32,
		.snapshot_size = SZ_1M,
	},
	.prim_fifo_threshold = 0x00080000,
	.sqefw_name = "a630_sqe.fw",
	.zap_name = "a610_zap.mbn",
	.hwcg = a612_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a612_hwcg_regs),
	.vbif = a640_vbif_regs,
	.vbif_count = ARRAY_SIZE(a640_vbif_regs),
	.hang_detect_cycles = 0x3ffff,
	.protected_regs = a630_protected_regs,
	.highest_bank_bit = 14,
};

static const struct kgsl_regmap_list a660_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A6XX_RBBM_ISDB_CNT, 0x00000182},
	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
};

/* A660 protected register list */
static const struct adreno_protected_regs a660_protected_regs[] = {
	{ A6XX_CP_PROTECT_REG + 0, 0x00000, 0x004ff, 0 },
	{ A6XX_CP_PROTECT_REG + 1, 0x00501, 0x00506, 0 },
	{ A6XX_CP_PROTECT_REG + 2, 0x0050b, 0x007ff, 0 },
	{ A6XX_CP_PROTECT_REG + 3, 0x0050e, 0x0050e, 1 },
	{ A6XX_CP_PROTECT_REG + 4, 0x00510, 0x00510, 1 },
	{ A6XX_CP_PROTECT_REG + 5, 0x00534, 0x00534, 1 },
	{ A6XX_CP_PROTECT_REG + 6, 0x00800, 0x00882, 1 },
	{ A6XX_CP_PROTECT_REG + 7, 0x008a0, 0x008a8, 1 },
	{ A6XX_CP_PROTECT_REG + 8, 0x008ab, 0x008cf, 1 },
	{ A6XX_CP_PROTECT_REG + 9, 0x008d0, 0x0098c, 0 },
	{ A6XX_CP_PROTECT_REG + 10, 0x00900, 0x0094d, 1 },
	{ A6XX_CP_PROTECT_REG + 11, 0x0098d, 0x00bff, 1 },
	{ A6XX_CP_PROTECT_REG + 12, 0x00e00, 0x00e01, 1 },
	{ A6XX_CP_PROTECT_REG + 13, 0x00e03, 0x00e0f, 1 },
	{ A6XX_CP_PROTECT_REG + 14, 0x03c00, 0x03cc3, 1 },
	{ A6XX_CP_PROTECT_REG + 15, 0x03cc4, 0x05cc3, 0 },
	{ A6XX_CP_PROTECT_REG + 16, 0x08630, 0x087ff, 1 },
	{ A6XX_CP_PROTECT_REG + 17, 0x08e00, 0x08e00, 1 },
	{ A6XX_CP_PROTECT_REG + 18, 0x08e08, 0x08e08, 1 },
	{ A6XX_CP_PROTECT_REG + 19, 0x08e50, 0x08e6f, 1 },
	{ A6XX_CP_PROTECT_REG + 20, 0x08e80, 0x090ff, 1 },
	{ A6XX_CP_PROTECT_REG + 21, 0x09624, 0x097ff, 1 },
	{ A6XX_CP_PROTECT_REG + 22, 0x09e60, 0x09e71, 1 },
	{ A6XX_CP_PROTECT_REG + 23, 0x09e78, 0x09fff, 1 },
	{ A6XX_CP_PROTECT_REG + 24, 0x0a630, 0x0a7ff, 1 },
	{ A6XX_CP_PROTECT_REG + 25, 0x0ae02, 0x0ae02, 1 },
	{ A6XX_CP_PROTECT_REG + 26, 0x0ae50, 0x0af7f, 1 },
	{ A6XX_CP_PROTECT_REG + 27, 0x0b604, 0x0b604, 1 },
	{ A6XX_CP_PROTECT_REG + 28, 0x0b608, 0x0b60e, 1 },
	{ A6XX_CP_PROTECT_REG + 29, 0x0be02, 0x0be03, 1 },
	{ A6XX_CP_PROTECT_REG + 30, 0x0be20, 0x0bf7f, 1 },
	{ A6XX_CP_PROTECT_REG + 31, 0x0d000, 0x0d5ff, 1 },
	{ A6XX_CP_PROTECT_REG + 32, 0x0f000, 0x0fbff, 1 },
	{ A6XX_CP_PROTECT_REG + 33, 0x0fc00, 0x11bff, 0 },
	{ A6XX_CP_PROTECT_REG + 34, 0x18400, 0x1a3ff, 1 },
	{ A6XX_CP_PROTECT_REG + 35, 0x1a400, 0x1c3ff, 1 },
	{ A6XX_CP_PROTECT_REG + 36, 0x1c400, 0x1e3ff, 1 },
	{ A6XX_CP_PROTECT_REG + 37, 0x1f400, 0x1f843, 1 },
	{ A6XX_CP_PROTECT_REG + 38, 0x1f844, 0x1f8bf, 0 },
	{ A6XX_CP_PROTECT_REG + 39, 0x1f860, 0x1f860, 1 },
	{ A6XX_CP_PROTECT_REG + 40, 0x1f887, 0x1f8a2, 1 },
	{ A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 },
	{ 0 },
};

static const struct adreno_a6xx_core adreno_gpu_core_a660 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A660, 6, 6, 0, 0),
		.features = ADRENO_APRIV |
				ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
				ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_L3_VOTE,
		.gpudev = &adreno_a6xx_gmu_gpudev.base,
		.perfcounters = &adreno_a6xx_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_1M + SZ_512K,
		.bus_width = 32,
		.snapshot_size = SZ_2M,
	},
	.prim_fifo_threshold = 0x00300000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a660_sqe.fw",
	.gmufw_name = "a660_gmu.bin",
	.zap_name = "a660_zap.mdt",
	.hwcg = a660_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a660_hwcg_regs),
	.vbif = a650_gbif_regs,
	.vbif_count = ARRAY_SIZE(a650_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.veto_fal10 = true,
	.protected_regs = a660_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 16,
	.pdc_in_aop = true,
	.ctxt_record_size = 2496 * 1024,
};

static const struct adreno_a6xx_core adreno_gpu_core_a660v2 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A660, 6, 6, 0, ANY_ID),
		.features = ADRENO_APRIV |
				ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
				ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |
				ADRENO_L3_VOTE,
		.gpudev = &adreno_a6xx_gmu_gpudev.base,
		.perfcounters = &adreno_a6xx_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_1M + SZ_512K,
		.bus_width = 32,
		.snapshot_size = SZ_2M,
	},
	.prim_fifo_threshold = 0x00300000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a660_sqe.fw",
	.gmufw_name = "a660_gmu.bin",
	.zap_name = "a660_zap.mdt",
	.hwcg = a660_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a660_hwcg_regs),
	.vbif = a650_gbif_regs,
	.vbif_count = ARRAY_SIZE(a650_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.veto_fal10 = true,
	.protected_regs = a660_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 16,
	.pdc_in_aop = true,
	.ctxt_record_size = 2496 * 1024,
};

static const struct adreno_a6xx_core adreno_gpu_core_a660_shima = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A660, 6, 6, 0, ANY_ID),
		.compatible = "qcom,adreno-gpu-a660-shima",
		.features = ADRENO_APRIV |
				ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
				ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD,
		.gpudev = &adreno_a6xx_gmu_gpudev.base,
		.perfcounters = &adreno_a6xx_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_1M + SZ_512K,
		.bus_width = 32,
		.snapshot_size = SZ_2M,
	},
	.prim_fifo_threshold = 0x00300000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a660_sqe.fw",
	.gmufw_name = "a660_gmu.bin",
	.zap_name = "a660_zap.mdt",
	.hwcg = a660_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a660_hwcg_regs),
	.vbif = a650_gbif_regs,
	.vbif_count = ARRAY_SIZE(a650_gbif_regs),
	.hang_detect_cycles = 0x3ffff,
	.veto_fal10 = true,
	.protected_regs = a660_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 15,
	.pdc_in_aop = true,
	.ctxt_record_size = 2496 * 1024,
};

static const struct adreno_a6xx_core adreno_gpu_core_a635 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A635, 6, 3, 5, ANY_ID),
		.features = ADRENO_APRIV | ADRENO_IOCOHERENT |
				ADRENO_CONTENT_PROTECTION,
		.gpudev = &adreno_a6xx_gmu_gpudev.base,
		.perfcounters = &adreno_a6xx_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_512K,
		.bus_width = 32,
		.snapshot_size = SZ_2M,
	},
	.prim_fifo_threshold = 0x00200000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a660_sqe.fw",
	.gmufw_name = "a660_gmu.bin",
	.zap_name = "a660_zap.mdt",
	.hwcg = a660_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a660_hwcg_regs),
	.vbif = a650_gbif_regs,
	.vbif_count = ARRAY_SIZE(a650_gbif_regs),
	.hang_detect_cycles = 0x3ffff,
	.veto_fal10 = true,
	.protected_regs = a660_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 15,
	.pdc_in_aop = true,
	.ctxt_record_size = 2496 * 1024,
};

static const struct adreno_a6xx_core adreno_gpu_core_a662 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A662, ANY_ID, ANY_ID, ANY_ID, ANY_ID),
		.compatible = "qcom,adreno-gpu-a662",
		.features = ADRENO_APRIV | ADRENO_IOCOHERENT |
			ADRENO_CONTENT_PROTECTION | ADRENO_PREEMPTION |
			ADRENO_IFPC | ADRENO_BCL | ADRENO_ACD,
		.gpudev = &adreno_a6xx_gmu_gpudev.base,
		.perfcounters = &adreno_a6xx_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_1M + SZ_512K,
		.bus_width = 32,
		.snapshot_size = SZ_2M,
	},
	.prim_fifo_threshold = 0x00300000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a660_sqe.fw",
	.gmufw_name = "a662_gmu.bin",
	.zap_name = "a662_zap.mdt",
	.hwcg = a660_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a660_hwcg_regs),
	.vbif = a650_gbif_regs,
	.vbif_count = ARRAY_SIZE(a650_gbif_regs),
	.hang_detect_cycles = 0x3ffff,
	.veto_fal10 = true,
	.protected_regs = a660_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 15,
	.pdc_in_aop = true,
	.ctxt_record_size = 2496 * 1024,
};

extern const struct gen7_snapshot_block_list gen7_0_0_snapshot_block_list;

static const struct kgsl_regmap_list gen7_0_0_gbif_regs[] = {
	{ GEN7_GBIF_QSB_SIDE0, 0x00071620 },
	{ GEN7_GBIF_QSB_SIDE1, 0x00071620 },
	{ GEN7_GBIF_QSB_SIDE2, 0x00071620 },
	{ GEN7_GBIF_QSB_SIDE3, 0x00071620 },
	{ GEN7_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212 },
};

static const struct kgsl_regmap_list a702_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A6XX_RBBM_ISDB_CNT, 0x00000182},
	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
	{A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222},
	{A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002},
	{A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000},
};

static const struct adreno_a6xx_core adreno_gpu_core_a702 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A702, 7, 0, 2, ANY_ID),
		.features = ADRENO_CONTENT_PROTECTION |
					ADRENO_APRIV | ADRENO_PREEMPTION,
		.gpudev = &adreno_a6xx_gpudev,
		.perfcounters = &adreno_a6xx_legacy_perfcounters,
		.gmem_size = SZ_128K,
		.bus_width = 16,
		.snapshot_size = SZ_1M,
	},
	.prim_fifo_threshold = 0x0000c000,
	.sqefw_name = "a702_sqe.fw",
	.zap_name = "a702_zap.mdt",
	.hwcg = a702_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a702_hwcg_regs),
	.vbif = a640_vbif_regs,
	.vbif_count = ARRAY_SIZE(a640_vbif_regs),
	.hang_detect_cycles = 0x3ffff,
	.protected_regs = a620_protected_regs,
	.highest_bank_bit = 14,
};

static const struct kgsl_regmap_list gen7_0_0_hwcg_regs[] = {
	{ GEN7_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
	{ GEN7_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
	{ GEN7_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
	{ GEN7_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
	{ GEN7_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
	{ GEN7_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
	{ GEN7_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
	{ GEN7_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
	{ GEN7_RBBM_CLOCK_HYST_TP0, 0x77777777 },
	{ GEN7_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
	{ GEN7_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
	{ GEN7_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
	{ GEN7_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
	{ GEN7_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
	{ GEN7_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
	{ GEN7_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
	{ GEN7_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
	{ GEN7_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
	{ GEN7_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
	{ GEN7_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
	{ GEN7_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
	{ GEN7_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
	{ GEN7_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
	{ GEN7_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
	{ GEN7_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
	{ GEN7_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
	{ GEN7_RBBM_CLOCK_HYST_RAC, 0x00440044 },
	{ GEN7_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
	{ GEN7_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
	{ GEN7_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
	{ GEN7_RBBM_CLOCK_MODE_GPC, 0x02222223 },
	{ GEN7_RBBM_CLOCK_MODE_VFD, 0x00002222 },
	{ GEN7_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
	{ GEN7_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
	{ GEN7_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
	{ GEN7_RBBM_CLOCK_HYST_GPC, 0x04104004 },
	{ GEN7_RBBM_CLOCK_HYST_VFD, 0x00000000 },
	{ GEN7_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
	{ GEN7_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
	{ GEN7_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
	{ GEN7_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
	{ GEN7_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
	{ GEN7_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
	{ GEN7_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
	{ GEN7_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
	{ GEN7_RBBM_CLOCK_MODE_CP, 0x00000223 },
	{ GEN7_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
	{ GEN7_RBBM_ISDB_CNT, 0x00000182 },
	{ GEN7_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
	{ GEN7_RBBM_SP_HYST_CNT, 0x00000000 },
	{ GEN7_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
	{ GEN7_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
	{ GEN7_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
};

static const struct kgsl_regmap_list gen7_0_0_ao_hwcg_regs[] = {
	{ GEN7_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x00020000 },
	{ GEN7_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x00010111 },
	{ GEN7_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x00005555 },
};

/* GEN7_0_0 protected register list */
static const struct gen7_protected_regs gen7_0_0_protected_regs[] = {
	{ GEN7_CP_PROTECT_REG + 0, 0x00000, 0x004ff, 0 },
	{ GEN7_CP_PROTECT_REG + 1, 0x0050b, 0x00563, 0 },
	{ GEN7_CP_PROTECT_REG + 2, 0x0050e, 0x0050e, 1 },
	{ GEN7_CP_PROTECT_REG + 3, 0x00510, 0x00510, 1 },
	{ GEN7_CP_PROTECT_REG + 4, 0x00534, 0x00534, 1 },
	{ GEN7_CP_PROTECT_REG + 5, 0x005fb, 0x00698, 0 },
	{ GEN7_CP_PROTECT_REG + 6, 0x00699, 0x00882, 1 },
	{ GEN7_CP_PROTECT_REG + 7, 0x008a0, 0x008a8, 1 },
	{ GEN7_CP_PROTECT_REG + 8, 0x008ab, 0x008cf, 1 },
	{ GEN7_CP_PROTECT_REG + 9, 0x008d0, 0x00a40, 0 },
	{ GEN7_CP_PROTECT_REG + 10, 0x00900, 0x0094d, 1 },
	{ GEN7_CP_PROTECT_REG + 11, 0x0098d, 0x00a3f, 1 },
	{ GEN7_CP_PROTECT_REG + 12, 0x00a41, 0x00bff, 1 },
	{ GEN7_CP_PROTECT_REG + 13, 0x00df0, 0x00df1, 1 },
	{ GEN7_CP_PROTECT_REG + 14, 0x00e01, 0x00e01, 1 },
	{ GEN7_CP_PROTECT_REG + 15, 0x00e07, 0x00e0f, 1 },
	{ GEN7_CP_PROTECT_REG + 16, 0x03c00, 0x03cc3, 1 },
	{ GEN7_CP_PROTECT_REG + 17, 0x03cc4, 0x05cc3, 0 },
	{ GEN7_CP_PROTECT_REG + 18, 0x08630, 0x087ff, 1 },
	{ GEN7_CP_PROTECT_REG + 19, 0x08e00, 0x08e00, 1 },
	{ GEN7_CP_PROTECT_REG + 20, 0x08e08, 0x08e08, 1 },
	{ GEN7_CP_PROTECT_REG + 21, 0x08e50, 0x08e6f, 1 },
	{ GEN7_CP_PROTECT_REG + 22, 0x08e80, 0x09100, 1 },
	{ GEN7_CP_PROTECT_REG + 23, 0x09624, 0x097ff, 1 },
	{ GEN7_CP_PROTECT_REG + 24, 0x09e40, 0x09e40, 1 },
	{ GEN7_CP_PROTECT_REG + 25, 0x09e64, 0x09e71, 1 },
	{ GEN7_CP_PROTECT_REG + 26, 0x09e78, 0x09fff, 1 },
	{ GEN7_CP_PROTECT_REG + 27, 0x0a630, 0x0a7ff, 1 },
	{ GEN7_CP_PROTECT_REG + 28, 0x0ae02, 0x0ae02, 1 },
	{ GEN7_CP_PROTECT_REG + 29, 0x0ae50, 0x0ae5f, 1 },
	{ GEN7_CP_PROTECT_REG + 30, 0x0ae66, 0x0ae69, 1 },
	{ GEN7_CP_PROTECT_REG + 31, 0x0ae6f, 0x0ae72, 1 },
	{ GEN7_CP_PROTECT_REG + 32, 0x0b604, 0x0b607, 1 },
	{ GEN7_CP_PROTECT_REG + 33, 0x0ec00, 0x0fbff, 1 },
	{ GEN7_CP_PROTECT_REG + 34, 0x0fc00, 0x11bff, 0 },
	{ GEN7_CP_PROTECT_REG + 35, 0x18400, 0x1844a, 1 },
	{ GEN7_CP_PROTECT_REG + 36, 0x1844b, 0x1857f, 0 },
	{ GEN7_CP_PROTECT_REG + 37, 0x1844c, 0x18453, 1 },
	{ GEN7_CP_PROTECT_REG + 38, 0x18580, 0x1a57f, 1 },
	{ GEN7_CP_PROTECT_REG + 39, 0x1a580, 0x1c57f, 1 },
	{ GEN7_CP_PROTECT_REG + 40, 0x1c580, 0x1e57f, 1 },
	{ GEN7_CP_PROTECT_REG + 41, 0x1f400, 0x1f843, 1 },
	{ GEN7_CP_PROTECT_REG + 42, 0x1f844, 0x1f8bf, 0 },
	{ GEN7_CP_PROTECT_REG + 43, 0x1f860, 0x1f860, 1 },
	{ GEN7_CP_PROTECT_REG + 44, 0x1f87f, 0x1f8a2, 1 },
	{ GEN7_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 },
	{ 0 },
};

static const struct adreno_gen7_core adreno_gpu_core_gen7_0_0 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_GEN7_0_0,
				UINT_MAX, UINT_MAX, UINT_MAX, 0),
		.compatible = "qcom,adreno-gpu-gen7-0-0",
		.features = ADRENO_APRIV | ADRENO_IOCOHERENT |
				ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
				ADRENO_ACD | ADRENO_L3_VOTE | ADRENO_BCL |
				ADRENO_PREEMPTION,
		.gpudev = &adreno_gen7_gmu_gpudev.base,
		.perfcounters = &adreno_gen7_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_2M,
		.bus_width = 32,
		.snapshot_size = SZ_4M,
	},
	.gmu_fw_version = GMU_VERSION(4, 0, 0),
	.sqefw_name = "a730_sqe.fw",
	.gmufw_name = "gmu_gen70000.bin",
	.gmufw_bak_name = "c500_gmu.bin",
	.zap_name = "a730_zap.mdt",
	.hwcg = gen7_0_0_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(gen7_0_0_hwcg_regs),
	.ao_hwcg = gen7_0_0_ao_hwcg_regs,
	.ao_hwcg_count = ARRAY_SIZE(gen7_0_0_ao_hwcg_regs),
	.gbif = gen7_0_0_gbif_regs,
	.gbif_count = ARRAY_SIZE(gen7_0_0_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = gen7_0_0_protected_regs,
	.highest_bank_bit = 16,
	.gen7_snapshot_block_list = &gen7_0_0_snapshot_block_list,
	.preempt_level = 1,
	.ctxt_record_size = (2860 * SZ_1K),
	.fast_bus_hint = true,
};

static const struct adreno_gen7_core adreno_gpu_core_gen7_0_1 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_GEN7_0_1,
				UINT_MAX, UINT_MAX, UINT_MAX, ANY_ID),
		.compatible = "qcom,adreno-gpu-gen7-0-1",
		.features = ADRENO_APRIV | ADRENO_IOCOHERENT |
				ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
				ADRENO_ACD | ADRENO_L3_VOTE | ADRENO_BCL |
				ADRENO_PREEMPTION,
		.gpudev = &adreno_gen7_gmu_gpudev.base,
		.perfcounters = &adreno_gen7_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_2M,
		.bus_width = 32,
		.snapshot_size = SZ_4M,
	},
	.gmu_fw_version = GMU_VERSION(4, 0, 0),
	.sqefw_name = "a730_sqe.fw",
	.gmufw_name = "gmu_gen70000.bin",
	.gmufw_bak_name = "c500_gmu.bin",
	.zap_name = "a730_zap.mdt",
	.hwcg = gen7_0_0_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(gen7_0_0_hwcg_regs),
	.ao_hwcg = gen7_0_0_ao_hwcg_regs,
	.ao_hwcg_count = ARRAY_SIZE(gen7_0_0_ao_hwcg_regs),
	.gbif = gen7_0_0_gbif_regs,
	.gbif_count = ARRAY_SIZE(gen7_0_0_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = gen7_0_0_protected_regs,
	.highest_bank_bit = 16,
	.gen7_snapshot_block_list = &gen7_0_0_snapshot_block_list,
	.preempt_level = 1,
	.ctxt_record_size = (2860 * SZ_1K),
	.fast_bus_hint = true,
};

extern const struct gen7_snapshot_block_list gen7_2_0_snapshot_block_list;

static const struct kgsl_regmap_list gen7_2_0_gbif_regs[] = {
	{ GEN7_GBIF_QSB_SIDE0, 0x00071620 },
	{ GEN7_GBIF_QSB_SIDE1, 0x00071620 },
	{ GEN7_GBIF_QSB_SIDE2, 0x00071620 },
	{ GEN7_GBIF_QSB_SIDE3, 0x00071620 },
	{ GEN7_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212 },
	{ GEN7_GMU_CX_MRC_GBIF_QOS_CTRL, 0x33 },
};

static const struct kgsl_regmap_list gen7_2_0_hwcg_regs[] = {
	{ GEN7_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
	{ GEN7_RBBM_CLOCK_CNTL2_SP0, 0x22022222 },
	{ GEN7_RBBM_CLOCK_HYST_SP0, 0x003cf3cf },
	{ GEN7_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
	{ GEN7_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
	{ GEN7_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
	{ GEN7_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
	{ GEN7_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
	{ GEN7_RBBM_CLOCK_HYST_TP0, 0x77777777 },
	{ GEN7_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
	{ GEN7_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
	{ GEN7_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
	{ GEN7_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
	{ GEN7_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
	{ GEN7_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
	{ GEN7_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
	{ GEN7_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
	{ GEN7_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 },
	{ GEN7_RBBM_CLOCK_HYST_UCHE, 0x00000444 },
	{ GEN7_RBBM_CLOCK_DELAY_UCHE, 0x00000222 },
	{ GEN7_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
	{ GEN7_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
	{ GEN7_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
	{ GEN7_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
	{ GEN7_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
	{ GEN7_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
	{ GEN7_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
	{ GEN7_RBBM_CLOCK_HYST_RAC, 0x00440044 },
	{ GEN7_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
	{ GEN7_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
	{ GEN7_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
	{ GEN7_RBBM_CLOCK_MODE_GPC, 0x02222223 },
	{ GEN7_RBBM_CLOCK_MODE_VFD, 0x00222222 },
	{ GEN7_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
	{ GEN7_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
	{ GEN7_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
	{ GEN7_RBBM_CLOCK_HYST_GPC, 0x04104004 },
	{ GEN7_RBBM_CLOCK_HYST_VFD, 0x00000000 },
	{ GEN7_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 },
	{ GEN7_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
	{ GEN7_RBBM_CLOCK_DELAY_VFD, 0x00000000 },
	{ GEN7_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
	{ GEN7_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
	{ GEN7_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
	{ GEN7_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
	{ GEN7_RBBM_CLOCK_HYST2_VFD, 0x00000000 },
	{ GEN7_RBBM_CLOCK_MODE_CP, 0x00000222 },
	{ GEN7_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
	{ GEN7_RBBM_ISDB_CNT, 0x00000182 },
	{ GEN7_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
	{ GEN7_RBBM_SP_HYST_CNT, 0x00000000 },
	{ GEN7_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
	{ GEN7_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
	{ GEN7_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
};

static const struct kgsl_regmap_list gen7_2_0_ao_hwcg_regs[] = {
	{ GEN7_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x00020202 },
	{ GEN7_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x00010111 },
	{ GEN7_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x00005555 },
};

static const struct adreno_gen7_core adreno_gpu_core_gen7_2_0 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_GEN7_2_0,
				UINT_MAX, UINT_MAX, UINT_MAX, ANY_ID),
		.compatible = "qcom,adreno-gpu-gen7-2-0",
		.features = ADRENO_APRIV | ADRENO_IOCOHERENT | ADRENO_IFPC |
				ADRENO_CONTENT_PROTECTION | ADRENO_ACD |
				ADRENO_LPAC | ADRENO_BCL | ADRENO_L3_VOTE |
				ADRENO_PREEMPTION | ADRENO_DMS,
		.gpudev = &adreno_gen7_hwsched_gpudev.base,
		.perfcounters = &adreno_gen7_hwsched_perfcounters,
		.uche_gmem_alignment = SZ_16M,
		.gmem_size = 3 * SZ_1M,
		.bus_width = 32,
		.snapshot_size = SZ_8M,
	},
	.gmu_fw_version = GMU_VERSION(4, 1, 0),
	.sqefw_name = "a740_sqe.fw",
	.gmufw_name = "gmu_gen70200.bin",
	.zap_name = "a740_zap.mbn",
	.hwcg = gen7_2_0_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(gen7_2_0_hwcg_regs),
	.ao_hwcg = gen7_2_0_ao_hwcg_regs,
	.ao_hwcg_count = ARRAY_SIZE(gen7_2_0_ao_hwcg_regs),
	.gbif = gen7_2_0_gbif_regs,
	.gbif_count = ARRAY_SIZE(gen7_2_0_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = gen7_0_0_protected_regs,
	.highest_bank_bit = 16,
	.gmu_hub_clk_freq = 200000000,
	.gen7_snapshot_block_list = &gen7_2_0_snapshot_block_list,
	.bcl_data = 1,
	.preempt_level = 1,
	.ctxt_record_size = (4192 * SZ_1K),
	.fast_bus_hint = true,
};

static const struct adreno_gen7_core adreno_gpu_core_gen7_2_1 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_GEN7_2_1,
				UINT_MAX, UINT_MAX, UINT_MAX, ANY_ID),
		.compatible = "qcom,adreno-gpu-gen7-2-1",
		.features = ADRENO_APRIV | ADRENO_IOCOHERENT | ADRENO_IFPC |
				ADRENO_CONTENT_PROTECTION | ADRENO_LPAC |
				ADRENO_BCL | ADRENO_L3_VOTE | ADRENO_ACD |
				ADRENO_PREEMPTION | ADRENO_DMS,
		.gpudev = &adreno_gen7_hwsched_gpudev.base,
		.perfcounters = &adreno_gen7_hwsched_perfcounters,
		.uche_gmem_alignment = SZ_16M,
		.gmem_size = 3 * SZ_1M,
		.bus_width = 32,
		.snapshot_size = SZ_8M,
	},
	.gmu_fw_version = GMU_VERSION(4, 1, 0),
	.sqefw_name = "a740_sqe.fw",
	.gmufw_name = "gmu_gen70200.bin",
	.zap_name = "a740_zap.mbn",
	.hwcg = gen7_2_0_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(gen7_2_0_hwcg_regs),
	.ao_hwcg = gen7_2_0_ao_hwcg_regs,
	.ao_hwcg_count = ARRAY_SIZE(gen7_2_0_ao_hwcg_regs),
	.gbif = gen7_2_0_gbif_regs,
	.gbif_count = ARRAY_SIZE(gen7_2_0_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = gen7_0_0_protected_regs,
	.highest_bank_bit = 16,
	.gmu_hub_clk_freq = 200000000,
	.gen7_snapshot_block_list = &gen7_2_0_snapshot_block_list,
	.bcl_data = 1,
	.preempt_level = 1,
	.ctxt_record_size = (4192 * SZ_1K),
	.fast_bus_hint = true,
};

static const struct adreno_gen7_core adreno_gpu_core_gen7_4_0 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_GEN7_4_0,
				UINT_MAX, UINT_MAX, UINT_MAX, ANY_ID),
		.compatible = "qcom,adreno-gpu-gen7-4-0",
		.features = ADRENO_APRIV | ADRENO_IOCOHERENT |
				ADRENO_CONTENT_PROTECTION | ADRENO_L3_VOTE |
				ADRENO_PREEMPTION | ADRENO_IFPC | ADRENO_ACD |
				ADRENO_BCL,
		.gpudev = &adreno_gen7_gmu_gpudev.base,
		.perfcounters = &adreno_gen7_perfcounters,
		.uche_gmem_alignment = 0,
		.gmem_size = SZ_2M,
		.bus_width = 32,
		.snapshot_size = SZ_4M,
	},
	.gmu_fw_version = GMU_VERSION(4, 0, 7),
	.sqefw_name = "a730_sqe.fw",
	.gmufw_name = "gmu_gen70000.bin",
	.gmufw_bak_name = "c500_gmu.bin",
	.zap_name = "a730_zap.mdt",
	.hwcg = gen7_0_0_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(gen7_0_0_hwcg_regs),
	.ao_hwcg = gen7_0_0_ao_hwcg_regs,
	.ao_hwcg_count = ARRAY_SIZE(gen7_0_0_ao_hwcg_regs),
	.gbif = gen7_0_0_gbif_regs,
	.gbif_count = ARRAY_SIZE(gen7_0_0_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = gen7_0_0_protected_regs,
	.highest_bank_bit = 16,
	.gen7_snapshot_block_list = &gen7_0_0_snapshot_block_list,
	.preempt_level = 1,
	.ctxt_record_size = (2860 * SZ_1K),
	.fast_bus_hint = true,
};

extern const struct gen7_snapshot_block_list gen7_9_0_snapshot_block_list;

/* GEN7_9_0 protected register list */
static const struct gen7_protected_regs gen7_9_0_protected_regs[] = {
	{ GEN7_CP_PROTECT_REG + 0, 0x00000, 0x004ff, 0 },
	{ GEN7_CP_PROTECT_REG + 1, 0x0050b, 0x00563, 0 },
	{ GEN7_CP_PROTECT_REG + 2, 0x00584, 0x006c1, 0 },
	{ GEN7_CP_PROTECT_REG + 3, 0x00706, 0x00706, 0 },
	{ GEN7_CP_PROTECT_REG + 4, 0x00720, 0x0073f, 0 },
	{ GEN7_CP_PROTECT_REG + 5, 0x00760, 0x007ff, 0 },
	{ GEN7_CP_PROTECT_REG + 6, 0x00800, 0x00882, 1 },
	{ GEN7_CP_PROTECT_REG + 7, 0x008a0, 0x008a8, 1 },
	{ GEN7_CP_PROTECT_REG + 8, 0x008ab, 0x00a40, 0 },
	{ GEN7_CP_PROTECT_REG + 9, 0x00900, 0x0094d, 1 },
	{ GEN7_CP_PROTECT_REG + 10, 0x0098d, 0x00a3f, 1 },
	{ GEN7_CP_PROTECT_REG + 11, 0x00a41, 0x00bff, 1 },
	{ GEN7_CP_PROTECT_REG + 12, 0x00df0, 0x00df1, 1 },
	{ GEN7_CP_PROTECT_REG + 13, 0x00e01, 0x00e01, 1 },
	{ GEN7_CP_PROTECT_REG + 14, 0x00e07, 0x00e0f, 1 },
	{ GEN7_CP_PROTECT_REG + 15, 0x02840, 0x03cc3, 1 },
	{ GEN7_CP_PROTECT_REG + 16, 0x03cc4, 0x05cc3, 0 },
	{ GEN7_CP_PROTECT_REG + 17, 0x08630, 0x087ff, 1 },
	{ GEN7_CP_PROTECT_REG + 18, 0x08e00, 0x08e00, 1 },
	{ GEN7_CP_PROTECT_REG + 19, 0x08e08, 0x08e08, 1 },
	{ GEN7_CP_PROTECT_REG + 20, 0x08e50, 0x08e6f, 1 },
	{ GEN7_CP_PROTECT_REG + 21, 0x08e79, 0x09100, 1 },
	{ GEN7_CP_PROTECT_REG + 22, 0x09624, 0x097ff, 1 },
	{ GEN7_CP_PROTECT_REG + 23, 0x09b0b, 0x09dff, 0 },
	{ GEN7_CP_PROTECT_REG + 24, 0x09e1a, 0x09e1b, 1 },
	{ GEN7_CP_PROTECT_REG + 25, 0x09e40, 0x09e40, 1 },
	{ GEN7_CP_PROTECT_REG + 26, 0x09e64, 0x09e64, 1 },
	{ GEN7_CP_PROTECT_REG + 27, 0x09e70, 0x09e71, 1 },
	{ GEN7_CP_PROTECT_REG + 28, 0x09e78, 0x09fff, 1 },
	{ GEN7_CP_PROTECT_REG + 29, 0x0a630, 0x0a7ff, 1 },
	{ GEN7_CP_PROTECT_REG + 30, 0x0ae02, 0x0ae02, 1 },
	{ GEN7_CP_PROTECT_REG + 31, 0x0ae50, 0x0ae5f, 1 },
	{ GEN7_CP_PROTECT_REG + 32, 0x0ae66, 0x0ae69, 1 },
	{ GEN7_CP_PROTECT_REG + 33, 0x0ae6f, 0x0ae72, 1 },
	{ GEN7_CP_PROTECT_REG + 34, 0x0b602, 0x0b607, 1 },
	{ GEN7_CP_PROTECT_REG + 35, 0x0ec00, 0x0fbff, 1 },
	{ GEN7_CP_PROTECT_REG + 36, 0x0fc00, 0x11bff, 0 },
	{ GEN7_CP_PROTECT_REG + 37, 0x18400, 0x1857f, 0 },
	{ GEN7_CP_PROTECT_REG + 38, 0x18580, 0x1a57f, 1 },
	{ GEN7_CP_PROTECT_REG + 39, 0x1a580, 0x1c57f, 1 },
	{ GEN7_CP_PROTECT_REG + 40, 0x1c580, 0x1e57f, 1 },
	{ GEN7_CP_PROTECT_REG + 41, 0x1f400, 0x1f843, 1 },
	{ GEN7_CP_PROTECT_REG + 42, 0x1f844, 0x1f8b7, 0 },
	{ GEN7_CP_PROTECT_REG + 43, 0x1f87f, 0x1f8a2, 1 },
	{ GEN7_CP_PROTECT_REG + 44, 0x1f8b8, 0x218b7, 1 },
	{ GEN7_CP_PROTECT_REG + 45, 0x27800, 0x2787f, 1 },
	{ GEN7_CP_PROTECT_REG + 46, 0x27880, 0x27c01, 0 },
	{ GEN7_CP_PROTECT_REG + 47, 0x27c02, 0x27c02, 1 },
	{ 0 },
};

static const struct adreno_gen7_core adreno_gpu_core_gen7_9_0 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_GEN7_9_0,
				  UINT_MAX, UINT_MAX, UINT_MAX, ANY_ID),
		.compatible = "qcom,adreno-gpu-gen7-9-0",
		.features = ADRENO_APRIV | ADRENO_IOCOHERENT | ADRENO_AQE |
			ADRENO_CONTENT_PROTECTION | ADRENO_LPAC | ADRENO_IFPC |
			ADRENO_L3_VOTE | ADRENO_BCL | ADRENO_DMS |
			ADRENO_HW_FENCE | ADRENO_PREEMPTION | ADRENO_ACD |
			ADRENO_GMU_WARMBOOT,
		.gpudev = &adreno_gen7_9_0_hwsched_gpudev.base,
		.perfcounters = &adreno_gen7_9_0_hwsched_perfcounters,
		.uche_gmem_alignment = SZ_16M,
		.gmem_size = 3 * SZ_1M,
		.bus_width = 32,
		.snapshot_size = SZ_8M,
		.num_ddr_channels = 4,
	},
	.aqefw_name = "gen70900_aqe.fw",
	.sqefw_name = "gen70900_sqe.fw",
	.gmufw_name = "gmu_gen70900.bin",
	.zap_name = "gen70900_zap.mbn",
	.ao_hwcg = gen7_2_0_ao_hwcg_regs,
	.ao_hwcg_count = ARRAY_SIZE(gen7_2_0_ao_hwcg_regs),
	.gbif = gen7_2_0_gbif_regs,
	.gbif_count = ARRAY_SIZE(gen7_2_0_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = gen7_9_0_protected_regs,
	.highest_bank_bit = 16,
	.gmu_hub_clk_freq = 200000000,
	.gen7_snapshot_block_list = &gen7_9_0_snapshot_block_list,
	.bcl_data = 1,
	.acv_perfmode_vote = BIT(2),
	.acv_perfmode_ddr_freq = MHZ_TO_KBPS(2736, 4),
	.ctxt_record_size = (4208 * SZ_1K),
	.preempt_level = 1,
	.fast_bus_hint = true,
};

static const struct adreno_gen7_core adreno_gpu_core_gen7_9_1 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_GEN7_9_1,
				  UINT_MAX, UINT_MAX, UINT_MAX, ANY_ID),
		.compatible = "qcom,adreno-gpu-gen7-9-1",
		.features = ADRENO_APRIV | ADRENO_IOCOHERENT | ADRENO_AQE |
			ADRENO_CONTENT_PROTECTION | ADRENO_LPAC | ADRENO_IFPC |
			ADRENO_L3_VOTE | ADRENO_BCL | ADRENO_DMS |
			ADRENO_HW_FENCE | ADRENO_PREEMPTION | ADRENO_ACD |
			ADRENO_GMU_WARMBOOT,
		.gpudev = &adreno_gen7_9_0_hwsched_gpudev.base,
		.perfcounters = &adreno_gen7_9_0_hwsched_perfcounters,
		.uche_gmem_alignment = SZ_16M,
		.gmem_size = 3 * SZ_1M,
		.bus_width = 32,
		.snapshot_size = SZ_8M,
		.num_ddr_channels = 4,
	},
	.aqefw_name = "gen70900_aqe.fw",
	.sqefw_name = "gen70900_sqe.fw",
	.gmufw_name = "gmu_gen70900.bin",
	.zap_name = "gen70900_zap.mbn",
	.ao_hwcg = gen7_2_0_ao_hwcg_regs,
	.ao_hwcg_count = ARRAY_SIZE(gen7_2_0_ao_hwcg_regs),
	.gbif = gen7_0_0_gbif_regs,
	.gbif_count = ARRAY_SIZE(gen7_0_0_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = gen7_9_0_protected_regs,
	.highest_bank_bit = 16,
	.gmu_hub_clk_freq = 200000000,
	.gen7_snapshot_block_list = &gen7_9_0_snapshot_block_list,
	.bcl_data = 1,
	.acv_perfmode_vote = BIT(2),
	.acv_perfmode_ddr_freq = MHZ_TO_KBPS(2736, 4),
	.ctxt_record_size = (4208 * SZ_1K),
	.preempt_level = 1,
	.fast_bus_hint = true,
};

extern const struct gen7_snapshot_block_list gen7_11_0_snapshot_block_list;

static const struct adreno_gen7_core adreno_gpu_core_gen7_11_0 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_GEN7_11_0,
				  UINT_MAX, UINT_MAX, UINT_MAX, ANY_ID),
		.compatible = "qcom,adreno-gpu-gen7-11-0",
		.features = ADRENO_APRIV | ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
			ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_L3_VOTE |
			ADRENO_DMS | ADRENO_BCL,
		.gpudev = &adreno_gen7_hwsched_gpudev.base,
		.perfcounters = &adreno_gen7_hwsched_perfcounters,
		.uche_gmem_alignment = SZ_16M,
		.gmem_size = SZ_1M + SZ_512K,
		.bus_width = 32,
		.snapshot_size = SZ_4M,
		.num_ddr_channels = 4,
	},
	.sqefw_name = "gen71100_sqe.fw",
	.gmufw_name = "gen71100_gmu.bin",
	.zap_name = "gen71100_zap.mbn",
	.hwcg = gen7_2_0_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(gen7_2_0_hwcg_regs),
	.ao_hwcg = gen7_2_0_ao_hwcg_regs,
	.ao_hwcg_count = ARRAY_SIZE(gen7_2_0_ao_hwcg_regs),
	.gbif = gen7_2_0_gbif_regs,
	.gbif_count = ARRAY_SIZE(gen7_2_0_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = gen7_0_0_protected_regs,
	.highest_bank_bit = 16,
	.gmu_hub_clk_freq = 200000000,
	.gen7_snapshot_block_list = &gen7_11_0_snapshot_block_list,
	.preempt_level = 1,
	.acv_perfmode_vote = BIT(2),
	.bcl_data = 1,
	.fast_bus_hint = true,
	.ctxt_record_size = (2196 * SZ_1K),
};

static const struct kgsl_regmap_list a663_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
	{A6XX_RBBM_ISDB_CNT, 0x00000182},
	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
	{A6XX_GMUAO_GMU_CGC_MODE_CNTL, 0x00020200},
	{A6XX_GMUAO_GMU_CGC_DELAY_CNTL, 0x00010111},
	{A6XX_GMUAO_GMU_CGC_HYST_CNTL, 0x00005555},
	{A6XX_GMUCX_GMU_WFI_CONFIG, 0x00000000},
};

/* A633 protected register list */
static const struct adreno_protected_regs a663_protected_regs[] = {
	{ A6XX_CP_PROTECT_REG + 0, 0x00000, 0x004ff, 0 },
	{ A6XX_CP_PROTECT_REG + 1, 0x00501, 0x00506, 0 },
	{ A6XX_CP_PROTECT_REG + 2, 0x0050b, 0x007ff, 0 },
	{ A6XX_CP_PROTECT_REG + 3, 0x0050e, 0x0050e, 1 },
	{ A6XX_CP_PROTECT_REG + 4, 0x00510, 0x00510, 1 },
	{ A6XX_CP_PROTECT_REG + 5, 0x00534, 0x00534, 1 },
	{ A6XX_CP_PROTECT_REG + 6, 0x00800, 0x00882, 1 },
	{ A6XX_CP_PROTECT_REG + 7, 0x008a0, 0x008a8, 1 },
	{ A6XX_CP_PROTECT_REG + 8, 0x008ab, 0x008cf, 1 },
	{ A6XX_CP_PROTECT_REG + 9, 0x008d0, 0x0098c, 0 },
	{ A6XX_CP_PROTECT_REG + 10, 0x00900, 0x0094d, 1 },
	{ A6XX_CP_PROTECT_REG + 11, 0x0098d, 0x00bff, 1 },
	{ A6XX_CP_PROTECT_REG + 12, 0x00e00, 0x00e01, 1 },
	{ A6XX_CP_PROTECT_REG + 13, 0x00e03, 0x00e0f, 1 },
	{ A6XX_CP_PROTECT_REG + 14, 0x03c00, 0x03cc3, 1 },
	{ A6XX_CP_PROTECT_REG + 15, 0x03cc4, 0x05cc3, 0 },
	{ A6XX_CP_PROTECT_REG + 16, 0x08630, 0x087ff, 1 },
	{ A6XX_CP_PROTECT_REG + 17, 0x08e00, 0x08e00, 1 },
	{ A6XX_CP_PROTECT_REG + 18, 0x08e08, 0x08e08, 1 },
	{ A6XX_CP_PROTECT_REG + 19, 0x08e50, 0x08e6f, 1 },
	{ A6XX_CP_PROTECT_REG + 20, 0x08e80, 0x090ff, 1 },
	{ A6XX_CP_PROTECT_REG + 21, 0x09624, 0x097ff, 1 },
	{ A6XX_CP_PROTECT_REG + 22, 0x09e60, 0x09e71, 1 },
	{ A6XX_CP_PROTECT_REG + 23, 0x09e78, 0x09fff, 1 },
	{ A6XX_CP_PROTECT_REG + 24, 0x0a630, 0x0a7ff, 1 },
	{ A6XX_CP_PROTECT_REG + 25, 0x0ae02, 0x0ae02, 1 },
	{ A6XX_CP_PROTECT_REG + 26, 0x0ae50, 0x0af7f, 1 },
	{ A6XX_CP_PROTECT_REG + 27, 0x0b604, 0x0b604, 1 },
	{ A6XX_CP_PROTECT_REG + 28, 0x0b608, 0x0b60e, 1 },
	{ A6XX_CP_PROTECT_REG + 29, 0x0be02, 0x0be03, 1 },
	{ A6XX_CP_PROTECT_REG + 30, 0x0be20, 0x0bf7f, 1 },
	{ A6XX_CP_PROTECT_REG + 31, 0x0d000, 0x0d5ff, 1 },
	{ A6XX_CP_PROTECT_REG + 32, 0x0f000, 0x0fbff, 1 },
	{ A6XX_CP_PROTECT_REG + 33, 0x0fc00, 0x11bff, 0 },
	/* Note1:  lastspanunbound feature is enabled in
	 *         CP_PROTECT_CNTL and hence this last
	 *         protect register(REG_47) has infinite
	 *         span.
	 *
	 * Note2:  Although we are protecting the SMMU
	 *         range here the CP register protection
	 *         interrupt will not fire for this range
	 *         as GPU RAP can only cover the GPU 18-bit
	 *         DW address space.  So max address offset
	 *         is 0x3FFFF.  Also note that the max number
	 *         of bits for address in violation in
	 *         CP_PROT_STATUS is only 18.
	 */
	{ A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x00000, 1 },
	{ 0 },
};

static const struct adreno_a6xx_core adreno_gpu_core_a663 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_A663, 6, 6, 3, ANY_ID),
		.features = ADRENO_APRIV |
				ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
				ADRENO_PREEMPTION | ADRENO_ACD,
		.gpudev = &adreno_a6xx_gmu_gpudev.base,
		.perfcounters = &adreno_a6xx_perfcounters,
		.gmem_size = SZ_1M + SZ_512K,
		.bus_width = 32,
		.snapshot_size = SZ_2M,
	},
	.prim_fifo_threshold = 0x00300000,
	.gmu_major = 2,
	.gmu_minor = 0,
	.sqefw_name = "a660_sqe.fw",
	.gmufw_name = "a663_gmu.bin",
	.zap_name = "a663_zap.mdt",
	.hwcg = a663_hwcg_regs,
	.hwcg_count = ARRAY_SIZE(a663_hwcg_regs),
	.vbif = a650_gbif_regs,
	.vbif_count = ARRAY_SIZE(a650_gbif_regs),
	.hang_detect_cycles = 0xcfffff,
	.veto_fal10 = true,
	.protected_regs = a663_protected_regs,
	.disable_tseskip = true,
	.highest_bank_bit = 13,
	.pdc_in_aop = true,
	.ctxt_record_size = 2496 * 1024,
};

extern const struct gen8_snapshot_block_list gen8_3_0_snapshot_block_list;

static const struct kgsl_regmap_list gen8_3_0_gbif_cx_regs[] = {
	{ GEN8_GBIF_QSB_SIDE0, 0x00071e20 },
	{ GEN8_GBIF_QSB_SIDE1, 0x00071e20 },
	{ GEN8_GBIF_QSB_SIDE2, 0x00071e20 },
	{ GEN8_GBIF_QSB_SIDE3, 0x00071e20 },
	{ GEN8_GBIF_CX_CONFIG, 0x20023000 },
};

/* GEN8_3_0 noncontext register list */
static const struct gen8_nonctxt_regs gen8_3_0_nonctxt_regs[] = {
	{ GEN8_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
	{ GEN8_GRAS_DBG_ECO_CNTL, 0x00f80800, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
	{ GEN8_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
	{ GEN8_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
	{ GEN8_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
	{ GEN8_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
	{ GEN8_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
	{ GEN8_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
	{ GEN8_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
	{ GEN8_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
	{ GEN8_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
	/*
	 * BIT(22): Disable PS out of order retire
	 * BIT(23): Enable half wave mode and MM instruction src&dst is half precision
	 */
	{ GEN8_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) },
	{ GEN8_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
	{ GEN8_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
	{ GEN8_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
	{ GEN8_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
	{ GEN8_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
	{ GEN8_TPL1_DBG_ECO_CNTL1, 0x00000724, BIT(PIPE_NONE) },
	{ GEN8_UCHE_MODE_CNTL, 0x00020000, BIT(PIPE_NONE) },
	{ GEN8_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
	{ GEN8_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
	{ GEN8_UCHE_CACHE_WAYS, 0x00080000, BIT(PIPE_NONE) },
	{ GEN8_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
	{ GEN8_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
	{ GEN8_VSC_BIN_SIZE, 0x00010001, BIT(PIPE_NONE) },
	{ GEN8_RB_GC_GMEM_PROTECT, 0x00900000, BIT(PIPE_BR) },
	{ 0 },
};

static const struct kgsl_regmap_list gen8_ao_hwcg_regs[] = {
	{ GEN8_GMUAO_CGC_MODE_CNTL, 0x00020000 },
	{ GEN8_GMUAO_CGC_DELAY_CNTL, 0x00010111 },
	{ GEN8_GMUAO_CGC_HYST_CNTL, 0x00005555 },
};

/* GEN8_3_0 protected register list */
static const struct gen8_protected_regs gen8_3_0_protected_regs[] = {
	{ GEN8_CP_PROTECT_REG_GLOBAL + 0, 0x00000, 0x003a3, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 1, 0x003b4, 0x0043f, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 2, 0x00440, 0x0045f, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 3, 0x00580, 0x005df, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 4, 0x005e0, 0x006ff, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 5, 0x0074a, 0x0074f, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 6, 0x00759, 0x0077f, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 7, 0x00789, 0x00789, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 8, 0x0078c, 0x0079f, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 9, 0x00800, 0x00829, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 10, 0x00837, 0x008e6, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 11, 0x008e7, 0x009b0, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 12, 0x008ec, 0x009af, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 13, 0x009b1, 0x00c01, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 14, 0x00ce0, 0x00ce1, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 15, 0x00df0, 0x00df0, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 16, 0x00df1, 0x00df1, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 17, 0x00e01, 0x00e01, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 18, 0x00e03, 0x02e02, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 19, 0x03c00, 0x03cc5, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 20, 0x03cc6, 0x05cc5, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 21, 0x08600, 0x087ff, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 22, 0x08e00, 0x08eff, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 23, 0x08f00, 0x08f00, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 24, 0x08f01, 0x090bf, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 25, 0x09600, 0x097ff, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 26, 0x0981a, 0x09aff, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 27, 0x09e00, 0x09fff, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 28, 0x0a600, 0x0a7ff, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 29, 0x0ae00, 0x0ae06, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 30, 0x0ae08, 0x0ae0e, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 31, 0x0ae10, 0x0b17f, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 32, 0x0b600, 0x0d5ff, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 33, 0x0dc00, 0x0fbff, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 34, 0x0fc00, 0x11bff, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 35, 0x18400, 0x1843f, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 36, 0x18440, 0x1857f, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 37, 0x18580, 0x1a57f, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 38, 0x1b400, 0x1d3ff, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 39, 0x1f400, 0x1f877, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 40, 0x1f878, 0x1ffff, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 41, 0x1f930, 0x1fc59, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 42, 0x20000, 0x21fff, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 43, 0x27800, 0x2787f, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 44, 0x27880, 0x27c01, 0 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 45, 0x27882, 0x27883, 1 },
	{ GEN8_CP_PROTECT_REG_GLOBAL + 63, 0x27c02, 0x27c02, 1 },
	{ 0 },
};

static const struct adreno_gen8_core adreno_gpu_core_gen8_3_0 = {
	.base = {
		DEFINE_ADRENO_REV(ADRENO_REV_GEN8_3_0,
				  UINT_MAX, UINT_MAX, UINT_MAX, ANY_ID),
		.compatible = "qcom,adreno-gpu-gen8-3-0",
		.features = ADRENO_APRIV | ADRENO_IOCOHERENT |
			ADRENO_CONTENT_PROTECTION | ADRENO_IFPC | ADRENO_BCL |
			ADRENO_PREEMPTION | ADRENO_ACD,
		.gpudev = &adreno_gen8_hwsched_gpudev.base,
		.perfcounters = &adreno_gen8_perfcounters,
		.uche_gmem_alignment = SZ_64M,
		.gmem_size = (SZ_512K + SZ_64K),
		.bus_width = 32,
		.snapshot_size = SZ_8M,
		.num_ddr_channels = 2,
	},
	.sqefw_name = "gen80300_sqe.fw",
	.gmufw_name = "gen80300_gmu.bin",
	.zap_name = "gen80300_zap.mbn",
	.ao_hwcg = gen8_ao_hwcg_regs,
	.ao_hwcg_count = ARRAY_SIZE(gen8_ao_hwcg_regs),
	.gbif = gen8_3_0_gbif_cx_regs,
	.gbif_count = ARRAY_SIZE(gen8_3_0_gbif_cx_regs),
	.hang_detect_cycles = 0xcfffff,
	.protected_regs = gen8_3_0_protected_regs,
	.nonctxt_regs = gen8_3_0_nonctxt_regs,
	.highest_bank_bit = 15,
	.gmu_hub_clk_freq = 200000000,
	.gen8_snapshot_block_list = &gen8_3_0_snapshot_block_list,
	.ctxt_record_size = (4558 * SZ_1K),
	.bcl_data = 1,
	.noc_timeout_us = 6800, /* 6.8 msec */
};

static const struct adreno_gpu_core *adreno_gpulist[] = {
	&adreno_gpu_core_a306.base,
	&adreno_gpu_core_a306a.base,
	&adreno_gpu_core_a304.base,
	&adreno_gpu_core_a405,		/* Deprecated */
	&adreno_gpu_core_a418,		/* Deprecated */
	&adreno_gpu_core_a420,		/* Deprecated */
	&adreno_gpu_core_a430,		/* Deprecated */
	&adreno_gpu_core_a530v1,	/* Deprecated */
	&adreno_gpu_core_a530v2.base,
	&adreno_gpu_core_a530v3.base,
	&adreno_gpu_core_a505.base,
	&adreno_gpu_core_a506.base,
	&adreno_gpu_core_a510.base,
	&adreno_gpu_core_a540v1,	/* Deprecated */
	&adreno_gpu_core_a540v2.base,
	&adreno_gpu_core_a512.base,
	&adreno_gpu_core_a508.base,
	&adreno_gpu_core_a630v1,	/* Deprecated */
	&adreno_gpu_core_a630v2.base,
	&adreno_gpu_core_a615.base,
	&adreno_gpu_core_a618.base,
	&adreno_gpu_core_a619.base,
	&adreno_gpu_core_a619_variant.base,
	&adreno_gpu_core_a620.base,
	&adreno_gpu_core_a621.base,
	&adreno_gpu_core_a635.base,
	&adreno_gpu_core_a640.base,
	&adreno_gpu_core_a650.base,
	&adreno_gpu_core_a650v2.base,
	&adreno_gpu_core_a660.base,
	&adreno_gpu_core_a660v2.base,
	&adreno_gpu_core_a663.base,
	&adreno_gpu_core_a680.base,
	&adreno_gpu_core_a612.base,
	&adreno_gpu_core_a616.base,
	&adreno_gpu_core_a610.base,
	&adreno_gpu_core_a611.base,
	&adreno_gpu_core_a660_shima.base,
	&adreno_gpu_core_a702.base,
	&adreno_gpu_core_gen7_0_0.base,
	&adreno_gpu_core_gen7_0_1.base,
	&adreno_gpu_core_a662.base,
	&adreno_gpu_core_gen7_2_0.base,
	&adreno_gpu_core_gen7_2_1.base,
	&adreno_gpu_core_gen7_4_0.base,
	&adreno_gpu_core_gen7_9_0.base,
	&adreno_gpu_core_gen7_9_1.base,
	&adreno_gpu_core_gen7_11_0.base,
	&adreno_gpu_core_gen8_3_0.base,

};