msm_drv.h 47 KB

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  1. /*
  2. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #ifndef __MSM_DRV_H__
  20. #define __MSM_DRV_H__
  21. #include <linux/kernel.h>
  22. #include <linux/clk.h>
  23. #include <linux/cpufreq.h>
  24. #include <linux/module.h>
  25. #include <linux/component.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/pm.h>
  28. #include <linux/pm_runtime.h>
  29. #include <linux/slab.h>
  30. #include <linux/list.h>
  31. #include <linux/iommu.h>
  32. #include <linux/types.h>
  33. #include <linux/of_graph.h>
  34. #include <linux/of_device.h>
  35. #include <linux/sde_io_util.h>
  36. #include <linux/sde_vm_event.h>
  37. #include <linux/sizes.h>
  38. #include <linux/kthread.h>
  39. #include <linux/version.h>
  40. #include <drm/drm_atomic.h>
  41. #include <drm/drm_atomic_helper.h>
  42. #include <drm/drm_plane_helper.h>
  43. #include <drm/drm_fb_helper.h>
  44. #include <drm/msm_drm.h>
  45. #include <drm/sde_drm.h>
  46. #include <drm/drm_file.h>
  47. #include <drm/drm_gem.h>
  48. #include <drm/drm_dsc.h>
  49. #include <drm/drm_bridge.h>
  50. #include "sde_power_handle.h"
  51. #define GET_MAJOR_REV(rev) ((rev) >> 28)
  52. #define GET_MINOR_REV(rev) (((rev) >> 16) & 0xFFF)
  53. #define GET_STEP_REV(rev) ((rev) & 0xFFFF)
  54. struct msm_kms;
  55. struct msm_gpu;
  56. struct msm_mmu;
  57. struct msm_mdss;
  58. struct msm_rd_state;
  59. struct msm_perf_state;
  60. struct msm_gem_submit;
  61. struct msm_fence_context;
  62. struct msm_fence_cb;
  63. struct msm_gem_address_space;
  64. struct msm_gem_vma;
  65. #define NUM_DOMAINS 4 /* one for KMS, then one per gpu core (?) */
  66. #define MAX_CRTCS 16
  67. #define MAX_PLANES 20
  68. #define MAX_ENCODERS 16
  69. #define MAX_BRIDGES 16
  70. #define MAX_CONNECTORS 16
  71. #define MSM_RGB 0x0
  72. #define MSM_YUV 0x1
  73. #define MSM_CHROMA_444 0x0
  74. #define MSM_CHROMA_422 0x1
  75. #define MSM_CHROMA_420 0x2
  76. #define TEARDOWN_DEADLOCK_RETRY_MAX 5
  77. #define DISP_DEV_ERR(dev, fmt, ...) dev_err(dev, "[%s:%d] " fmt, __func__, __LINE__, ##__VA_ARGS__)
  78. struct msm_file_private {
  79. rwlock_t queuelock;
  80. struct list_head submitqueues;
  81. int queueid;
  82. /* update the refcount when user driver calls power_ctrl IOCTL */
  83. unsigned short enable_refcnt;
  84. /* protects enable_refcnt */
  85. struct mutex power_lock;
  86. };
  87. enum msm_mdp_plane_property {
  88. /* blob properties, always put these first */
  89. PLANE_PROP_CSC_V1,
  90. PLANE_PROP_CSC_DMA_V1,
  91. PLANE_PROP_INFO,
  92. PLANE_PROP_SCALER_LUT_ED,
  93. PLANE_PROP_SCALER_LUT_CIR,
  94. PLANE_PROP_SCALER_LUT_SEP,
  95. PLANE_PROP_SKIN_COLOR,
  96. PLANE_PROP_SKY_COLOR,
  97. PLANE_PROP_FOLIAGE_COLOR,
  98. PLANE_PROP_VIG_GAMUT,
  99. PLANE_PROP_VIG_IGC,
  100. PLANE_PROP_DMA_IGC,
  101. PLANE_PROP_DMA_GC,
  102. PLANE_PROP_FP16_GC,
  103. PLANE_PROP_FP16_CSC,
  104. /* # of blob properties */
  105. PLANE_PROP_BLOBCOUNT,
  106. /* range properties */
  107. PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT,
  108. PLANE_PROP_ALPHA,
  109. PLANE_PROP_COLOR_FILL,
  110. PLANE_PROP_H_DECIMATE,
  111. PLANE_PROP_V_DECIMATE,
  112. PLANE_PROP_INPUT_FENCE,
  113. PLANE_PROP_HUE_ADJUST,
  114. PLANE_PROP_SATURATION_ADJUST,
  115. PLANE_PROP_VALUE_ADJUST,
  116. PLANE_PROP_CONTRAST_ADJUST,
  117. PLANE_PROP_EXCL_RECT_V1,
  118. PLANE_PROP_PREFILL_SIZE,
  119. PLANE_PROP_PREFILL_TIME,
  120. PLANE_PROP_SCALER_V1,
  121. PLANE_PROP_SCALER_V2,
  122. PLANE_PROP_INVERSE_PMA,
  123. PLANE_PROP_FP16_IGC,
  124. PLANE_PROP_FP16_UNMULT,
  125. PLANE_PROP_UBWC_STATS_ROI,
  126. /* enum/bitmask properties */
  127. PLANE_PROP_BLEND_OP,
  128. PLANE_PROP_SRC_CONFIG,
  129. PLANE_PROP_FB_TRANSLATION_MODE,
  130. PLANE_PROP_MULTIRECT_MODE,
  131. /* total # of properties */
  132. PLANE_PROP_COUNT
  133. };
  134. enum msm_mdp_crtc_property {
  135. CRTC_PROP_INFO,
  136. CRTC_PROP_DEST_SCALER_LUT_ED,
  137. CRTC_PROP_DEST_SCALER_LUT_CIR,
  138. CRTC_PROP_DEST_SCALER_LUT_SEP,
  139. CRTC_PROP_DSPP_INFO,
  140. /* # of blob properties */
  141. CRTC_PROP_BLOBCOUNT,
  142. /* range properties */
  143. CRTC_PROP_INPUT_FENCE_TIMEOUT = CRTC_PROP_BLOBCOUNT,
  144. CRTC_PROP_OUTPUT_FENCE,
  145. CRTC_PROP_OUTPUT_FENCE_OFFSET,
  146. CRTC_PROP_DIM_LAYER_V1,
  147. CRTC_PROP_CORE_CLK,
  148. CRTC_PROP_CORE_AB,
  149. CRTC_PROP_CORE_IB,
  150. CRTC_PROP_LLCC_AB,
  151. CRTC_PROP_LLCC_IB,
  152. CRTC_PROP_DRAM_AB,
  153. CRTC_PROP_DRAM_IB,
  154. CRTC_PROP_ROT_PREFILL_BW,
  155. CRTC_PROP_ROT_CLK,
  156. CRTC_PROP_ROI_V1,
  157. CRTC_PROP_SECURITY_LEVEL,
  158. CRTC_PROP_DEST_SCALER,
  159. CRTC_PROP_CAPTURE_OUTPUT,
  160. CRTC_PROP_IDLE_PC_STATE,
  161. CRTC_PROP_CACHE_STATE,
  162. CRTC_PROP_VM_REQ_STATE,
  163. CRTC_PROP_NOISE_LAYER_V1,
  164. CRTC_PROP_FRAME_DATA_BUF,
  165. /* total # of properties */
  166. CRTC_PROP_COUNT
  167. };
  168. enum msm_mdp_conn_property {
  169. /* blob properties, always put these first */
  170. CONNECTOR_PROP_SDE_INFO,
  171. CONNECTOR_PROP_MODE_INFO,
  172. CONNECTOR_PROP_HDR_INFO,
  173. CONNECTOR_PROP_EXT_HDR_INFO,
  174. CONNECTOR_PROP_PP_DITHER,
  175. CONNECTOR_PROP_PP_CWB_DITHER,
  176. CONNECTOR_PROP_HDR_METADATA,
  177. CONNECTOR_PROP_DEMURA_PANEL_ID,
  178. CONNECTOR_PROP_DIMMING_BL_LUT,
  179. CONNECTOR_PROP_DNSC_BLUR,
  180. /* # of blob properties */
  181. CONNECTOR_PROP_BLOBCOUNT,
  182. /* range properties */
  183. CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT,
  184. CONNECTOR_PROP_RETIRE_FENCE,
  185. CONN_PROP_RETIRE_FENCE_OFFSET,
  186. CONNECTOR_PROP_DST_X,
  187. CONNECTOR_PROP_DST_Y,
  188. CONNECTOR_PROP_DST_W,
  189. CONNECTOR_PROP_DST_H,
  190. CONNECTOR_PROP_ROI_V1,
  191. CONNECTOR_PROP_BL_SCALE,
  192. CONNECTOR_PROP_SV_BL_SCALE,
  193. CONNECTOR_PROP_SUPPORTED_COLORSPACES,
  194. CONNECTOR_PROP_DYN_BIT_CLK,
  195. CONNECTOR_PROP_DIMMING_CTRL,
  196. CONNECTOR_PROP_DIMMING_MIN_BL,
  197. CONNECTOR_PROP_EARLY_FENCE_LINE,
  198. CONNECTOR_PROP_DYN_TRANSFER_TIME,
  199. /* enum/bitmask properties */
  200. CONNECTOR_PROP_TOPOLOGY_NAME,
  201. CONNECTOR_PROP_TOPOLOGY_CONTROL,
  202. CONNECTOR_PROP_AUTOREFRESH,
  203. CONNECTOR_PROP_LP,
  204. CONNECTOR_PROP_FB_TRANSLATION_MODE,
  205. CONNECTOR_PROP_QSYNC_MODE,
  206. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE,
  207. CONNECTOR_PROP_SET_PANEL_MODE,
  208. CONNECTOR_PROP_AVR_STEP,
  209. CONNECTOR_PROP_CACHE_STATE,
  210. CONNECTOR_PROP_DSC_MODE,
  211. CONNECTOR_PROP_WB_USAGE_TYPE,
  212. /* total # of properties */
  213. CONNECTOR_PROP_COUNT
  214. };
  215. #define MSM_GPU_MAX_RINGS 4
  216. #define MAX_H_TILES_PER_DISPLAY 2
  217. /**
  218. * enum msm_display_compression_type - compression method used for pixel stream
  219. * @MSM_DISPLAY_COMPRESSION_NONE: Pixel data is not compressed
  220. * @MSM_DISPLAY_COMPRESSION_DSC: DSC compresison is used
  221. * @MSM_DISPLAY_COMPRESSION_VDC: VDC compresison is used
  222. */
  223. enum msm_display_compression_type {
  224. MSM_DISPLAY_COMPRESSION_NONE,
  225. MSM_DISPLAY_COMPRESSION_DSC,
  226. MSM_DISPLAY_COMPRESSION_VDC
  227. };
  228. /**
  229. * enum msm_display_wd_jitter_type - Type of WD jitter used
  230. * @MSM_DISPLAY_WD_JITTER_NONE: No WD timer jitter enabled
  231. * @MSM_DISPLAY_WD_INSTANTANEOUS_JITTER: Instantaneous WD jitter enabled
  232. * @MSM_DISPLAY_WD_LTJ_JITTER: LTJ WD jitter enabled
  233. */
  234. enum msm_display_wd_jitter_type {
  235. MSM_DISPLAY_WD_JITTER_NONE = BIT(0),
  236. MSM_DISPLAY_WD_INSTANTANEOUS_JITTER = BIT(1),
  237. MSM_DISPLAY_WD_LTJ_JITTER = BIT(2),
  238. };
  239. #define MSM_DISPLAY_COMPRESSION_RATIO_NONE 1
  240. #define MSM_DISPLAY_COMPRESSION_RATIO_MAX 5
  241. /**
  242. * enum msm_display_spr_pack_type - sub pixel rendering pack patterns supported
  243. * @MSM_DISPLAY_SPR_TYPE_NONE: Bypass, no special packing
  244. * @MSM_DISPLAY_SPR_TYPE_PENTILE: pentile pack pattern
  245. * @MSM_DISPLAY_SPR_TYPE_RGBW: RGBW pack pattern
  246. * @MSM_DISPLAY_SPR_TYPE_YYGM: YYGM pack pattern
  247. * @MSM_DISPLAY_SPR_TYPE_YYGW: YYGW pack patterm
  248. * @MSM_DISPLAY_SPR_TYPE_MAX: max and invalid
  249. */
  250. enum msm_display_spr_pack_type {
  251. MSM_DISPLAY_SPR_TYPE_NONE,
  252. MSM_DISPLAY_SPR_TYPE_PENTILE,
  253. MSM_DISPLAY_SPR_TYPE_RGBW,
  254. MSM_DISPLAY_SPR_TYPE_YYGM,
  255. MSM_DISPLAY_SPR_TYPE_YYGW,
  256. MSM_DISPLAY_SPR_TYPE_MAX
  257. };
  258. static const char *msm_spr_pack_type_str[MSM_DISPLAY_SPR_TYPE_MAX] = {
  259. [MSM_DISPLAY_SPR_TYPE_NONE] = "",
  260. [MSM_DISPLAY_SPR_TYPE_PENTILE] = "pentile",
  261. [MSM_DISPLAY_SPR_TYPE_RGBW] = "rgbw",
  262. [MSM_DISPLAY_SPR_TYPE_YYGM] = "yygm",
  263. [MSM_DISPLAY_SPR_TYPE_YYGW] = "yygw",
  264. };
  265. /**
  266. * enum msm_display_caps - features/capabilities supported by displays
  267. * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
  268. * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
  269. * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
  270. * @MSM_DISPLAY_CAP_EDID: EDID supported
  271. * @MSM_DISPLAY_ESD_ENABLED: ESD feature enabled
  272. * @MSM_DISPLAY_CAP_MST_MODE: Display with MST support
  273. * @MSM_DISPLAY_SPLIT_LINK: Split Link enabled
  274. */
  275. enum msm_display_caps {
  276. MSM_DISPLAY_CAP_VID_MODE = BIT(0),
  277. MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
  278. MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
  279. MSM_DISPLAY_CAP_EDID = BIT(3),
  280. MSM_DISPLAY_ESD_ENABLED = BIT(4),
  281. MSM_DISPLAY_CAP_MST_MODE = BIT(5),
  282. MSM_DISPLAY_SPLIT_LINK = BIT(6),
  283. };
  284. /**
  285. * enum panel_mode - panel operation mode
  286. * @MSM_DISPLAY_VIDEO_MODE: video mode panel
  287. * @MSM_DISPLAY_CMD_MODE: Command mode panel
  288. * @MODE_MAX:
  289. */
  290. enum panel_op_mode {
  291. MSM_DISPLAY_VIDEO_MODE = BIT(0),
  292. MSM_DISPLAY_CMD_MODE = BIT(1),
  293. MSM_DISPLAY_MODE_MAX = BIT(2)
  294. };
  295. /**
  296. * enum msm_display_dsc_mode - panel dsc mode
  297. * @MSM_DISPLAY_DSC_MODE_NONE: No operation
  298. * @MSM_DISPLAY_DSC_MODE_ENABLED: DSC is enabled
  299. * @MSM_DISPLAY_DSC_MODE_DISABLED: DSC is disabled
  300. */
  301. enum msm_display_dsc_mode {
  302. MSM_DISPLAY_DSC_MODE_NONE,
  303. MSM_DISPLAY_DSC_MODE_ENABLED,
  304. MSM_DISPLAY_DSC_MODE_DISABLED,
  305. };
  306. /**
  307. * struct msm_display_mode - wrapper for drm_display_mode
  308. * @base: drm_display_mode attached to this msm_mode
  309. * @private_flags: integer holding private driver mode flags
  310. * @private: pointer to private driver information
  311. */
  312. struct msm_display_mode {
  313. struct drm_display_mode *base;
  314. u32 private_flags;
  315. u32 *private;
  316. };
  317. /**
  318. * struct msm_sub_mode - msm display sub mode
  319. * @dsc_enabled: boolean used to indicate if dsc should be enabled
  320. */
  321. struct msm_sub_mode {
  322. enum msm_display_dsc_mode dsc_mode;
  323. };
  324. /**
  325. * struct msm_ratio - integer ratio
  326. * @numer: numerator
  327. * @denom: denominator
  328. */
  329. struct msm_ratio {
  330. uint32_t numer;
  331. uint32_t denom;
  332. };
  333. /**
  334. * enum msm_event_wait - type of HW events to wait for
  335. * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
  336. * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
  337. * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
  338. * @MSM_ENC_ACTIVE_REGION - wait for the TG to be in active pixel region
  339. */
  340. enum msm_event_wait {
  341. MSM_ENC_COMMIT_DONE = 0,
  342. MSM_ENC_TX_COMPLETE,
  343. MSM_ENC_VBLANK,
  344. MSM_ENC_ACTIVE_REGION,
  345. };
  346. /**
  347. * struct msm_roi_alignment - region of interest alignment restrictions
  348. * @xstart_pix_align: left x offset alignment restriction
  349. * @width_pix_align: width alignment restriction
  350. * @ystart_pix_align: top y offset alignment restriction
  351. * @height_pix_align: height alignment restriction
  352. * @min_width: minimum width restriction
  353. * @min_height: minimum height restriction
  354. */
  355. struct msm_roi_alignment {
  356. uint32_t xstart_pix_align;
  357. uint32_t width_pix_align;
  358. uint32_t ystart_pix_align;
  359. uint32_t height_pix_align;
  360. uint32_t min_width;
  361. uint32_t min_height;
  362. };
  363. /**
  364. * struct msm_roi_caps - display's region of interest capabilities
  365. * @enabled: true if some region of interest is supported
  366. * @merge_rois: merge rois before sending to display
  367. * @num_roi: maximum number of rois supported
  368. * @align: roi alignment restrictions
  369. */
  370. struct msm_roi_caps {
  371. bool enabled;
  372. bool merge_rois;
  373. uint32_t num_roi;
  374. struct msm_roi_alignment align;
  375. };
  376. /**
  377. * struct msm_display_dsc_info - defines dsc configuration
  378. * @config DSC encoder configuration
  379. * @scr_rev: DSC revision.
  380. * @initial_lines: Number of initial lines stored in encoder.
  381. * @pkt_per_line: Number of packets per line.
  382. * @bytes_in_slice: Number of bytes in slice.
  383. * @eol_byte_num: Valid bytes at the end of line.
  384. * @bytes_per_pkt Number of bytes in DSI packet
  385. * @pclk_per_line: Compressed width.
  386. * @slice_last_group_size: Size of last group in pixels.
  387. * @slice_per_pkt: Number of slices per packet.
  388. * @num_active_ss_per_enc: Number of active soft slices per encoder.
  389. * @source_color_space: Source color space of DSC encoder
  390. * @chroma_format: Chroma_format of DSC encoder.
  391. * @det_thresh_flatness: Flatness threshold.
  392. * @extra_width: Extra width required in timing calculations.
  393. * @pps_delay_ms: Post PPS command delay in milliseconds.
  394. * @dsc_4hsmerge_en: Using DSC 4HS merge topology
  395. * @dsc_4hsmerge_padding 4HS merge DSC pair padding value in bytes
  396. * @dsc_4hsmerge_alignment 4HS merge DSC alignment value in bytes
  397. * @half_panel_pu True for single and dual dsc encoders if partial
  398. * update sets the roi width to half of mode width
  399. * False in all other cases
  400. */
  401. struct msm_display_dsc_info {
  402. struct drm_dsc_config config;
  403. u8 scr_rev;
  404. int initial_lines;
  405. int pkt_per_line;
  406. int bytes_in_slice;
  407. int bytes_per_pkt;
  408. int eol_byte_num;
  409. int pclk_per_line;
  410. int slice_last_group_size;
  411. int slice_per_pkt;
  412. int num_active_ss_per_enc;
  413. int source_color_space;
  414. int chroma_format;
  415. int det_thresh_flatness;
  416. u32 extra_width;
  417. u32 pps_delay_ms;
  418. bool dsc_4hsmerge_en;
  419. u32 dsc_4hsmerge_padding;
  420. u32 dsc_4hsmerge_alignment;
  421. bool half_panel_pu;
  422. };
  423. /**
  424. * struct msm_display_vdc_info - defines vdc configuration
  425. * @version_major: major version number of VDC encoder.
  426. * @version_minor: minor version number of VDC encoder.
  427. * @source_color_space: source color space of VDC encoder
  428. * @chroma_format: chroma_format of VDC encoder.
  429. * @mppf_bpc_r_y: MPPF bpc for R/Y color component
  430. * @mppf_bpc_g_cb: MPPF bpc for G/Cb color component
  431. * @mppf_bpc_b_cr: MPPF bpc for B/Cr color component
  432. * @mppf_bpc_y: MPPF bpc for Y color component
  433. * @mppf_bpc_co: MPPF bpc for Co color component
  434. * @mppf_bpc_cg: MPPF bpc for Cg color component
  435. * @flatqp_vf_fbls: flatness qp very flat FBLs
  436. * @flatqp_vf_nbls: flatness qp very flat NBLs
  437. * @flatqp_sw_fbls: flatness qp somewhat flat FBLs
  438. * @flatqp_sw_nbls: flatness qp somewhat flat NBLs
  439. * @chroma_samples: number of chroma samples
  440. * @split_panel_enable: indicates whether split panel is enabled
  441. * @traffic_mode: indicates burst/non-burst mode
  442. * @flatness_qp_lut: LUT used to determine flatness QP
  443. * @max_qp_lut: LUT used to determine maximum QP
  444. * @tar_del_lut: LUT used to calculate RC target rate
  445. * @lbda_brate_lut: lambda bitrate LUT for encoder
  446. * @lbda_bf_lut: lambda buffer fullness lut for encoder
  447. * @lbda_brate_lut_interp: interpolated lambda bitrate LUT
  448. * @lbda_bf_lut_interp: interpolated lambda buffer fullness lut
  449. * @num_of_active_ss: number of active soft slices
  450. * @bits_per_component: number of bits per component.
  451. * @max_pixels_per_line: maximum pixels per line
  452. * @max_pixels_per_hs_line: maximum pixels per hs line
  453. * @max_lines_per_frame: maximum lines per frame
  454. * @max_lines_per_slice: maximum lines per slice
  455. * @chunk_size: chunk size for encoder
  456. * @chunk_size_bits: number of bits in the chunk
  457. * @avg_block_bits: average block bits
  458. * @per_chunk_pad_bits: number of bits per chunk pad
  459. * @tot_pad_bits: total padding bits
  460. * @rc_stuffing_bits: rate control stuffing bits
  461. * @chunk_adj_bits: number of adjacent bits in the chunk
  462. * @rc_buf_init_size_temp: temporary rate control buffer init size
  463. * @init_tx_delay_temp: initial tx delay
  464. * @rc_buffer_init_size: rate control buffer init size
  465. * @rc_init_tx_delay: rate control buffer init tx delay
  466. * @rc_init_tx_delay_px_times: rate control buffer init tx
  467. * delay times pixels
  468. * @rc_buffer_max_size: max size of rate control buffer
  469. * @rc_tar_rate_scale_temp_a: rate control target rate scale parameter
  470. * @rc_tar_rate_scale_temp_b: rate control target rate scale parameter
  471. * @rc_tar_rate_scale: rate control target rate scale
  472. * @block_max_bits: max bits in the block
  473. * @rc_lambda_bitrate_scale: rate control lambda bitrate scale
  474. * @rc_buffer_fullness_scale: rate control lambda fullness scale
  475. * @rc_fullness_offset_thresh: rate control lambda fullness threshold
  476. * @ramp_blocks: number of ramp blocks
  477. * @bits_per_pixel: number of bits per pixel.
  478. * @num_extra_mux_bits_init: initial value of number of extra mux bits
  479. * @extra_crop_bits: number of extra crop bits
  480. * @num_extra_mux_bits: value of number of extra mux bits
  481. * @mppf_bits_comp_0: mppf bits in color component 0
  482. * @mppf_bits_comp_1: mppf bits in color component 1
  483. * @mppf_bits_comp_2: mppf bits in color component 2
  484. * @min_block_bits: min number of block bits
  485. * @slice_height: slice height configuration of encoder.
  486. * @slice_width: slice width configuration of encoder.
  487. * @frame_width: frame width configuration of encoder
  488. * @frame_height: frame height configuration of encoder
  489. * @bytes_in_slice: Number of bytes in slice.
  490. * @bytes_per_pkt: Number of bytes in packet.
  491. * @eol_byte_num: Valid bytes at the end of line.
  492. * @pclk_per_line: Compressed width.
  493. * @slice_per_pkt: Number of slices per packet.
  494. * @pkt_per_line: Number of packets per line.
  495. * @min_ssm_delay: Min Sub-stream multiplexing delay
  496. * @max_ssm_delay: Max Sub-stream multiplexing delay
  497. * @input_ssm_out_latency: input Sub-stream multiplexing output latency
  498. * @input_ssm_out_latency_min: min input Sub-stream multiplexing output latency
  499. * @obuf_latency: Output buffer latency
  500. * @base_hs_latency: base hard-slice latency
  501. * @base_hs_latency_min: base hard-slice min latency
  502. * @base_hs_latency_pixels: base hard-slice latency pixels
  503. * @base_hs_latency_pixels_min: base hard-slice latency pixels(min)
  504. * @base_initial_lines: base initial lines
  505. * @base_top_up: base top up
  506. * @output_rate: output rate
  507. * @output_rate_ratio_100: output rate times 100
  508. * @burst_accum_pixels: burst accumulated pixels
  509. * @ss_initial_lines: soft-slice initial lines
  510. * @burst_initial_lines: burst mode initial lines
  511. * @initial_lines: initial lines
  512. * @obuf_base: output buffer base
  513. * @obuf_extra_ss0: output buffer extra ss0
  514. * @obuf_extra_ss1: output buffer extra ss1
  515. * @obuf_extra_burst: output buffer extra burst
  516. * @obuf_ss0: output buffer ss0
  517. * @obuf_ss1: output buffer ss1
  518. * @obuf_margin_words: output buffer margin words
  519. * @ob0_max_addr: output buffer 0 max address
  520. * @ob1_max_addr: output buffer 1 max address
  521. * @slice_width_orig: original slice width
  522. * @r2b0_max_addr: r2b0 max addr
  523. * @r2b1_max_addr: r1b1 max addr
  524. * @slice_num_px: number of pixels per slice
  525. * @rc_target_rate_threshold: rate control target rate threshold
  526. * @rc_fullness_offset_slope: rate control fullness offset slop
  527. * @pps_delay_ms: Post PPS command delay in milliseconds.
  528. * @version_release: release version of VDC encoder.
  529. * @slice_num_bits: number of bits per slice
  530. * @ramp_bits: number of ramp bits
  531. */
  532. struct msm_display_vdc_info {
  533. u8 version_major;
  534. u8 version_minor;
  535. u8 source_color_space;
  536. u8 chroma_format;
  537. u8 mppf_bpc_r_y;
  538. u8 mppf_bpc_g_cb;
  539. u8 mppf_bpc_b_cr;
  540. u8 mppf_bpc_y;
  541. u8 mppf_bpc_co;
  542. u8 mppf_bpc_cg;
  543. u8 flatqp_vf_fbls;
  544. u8 flatqp_vf_nbls;
  545. u8 flatqp_sw_fbls;
  546. u8 flatqp_sw_nbls;
  547. u8 chroma_samples;
  548. u8 split_panel_enable;
  549. u8 traffic_mode;
  550. u16 flatness_qp_lut[8];
  551. u16 max_qp_lut[8];
  552. u16 tar_del_lut[16];
  553. u16 lbda_brate_lut[16];
  554. u16 lbda_bf_lut[16];
  555. u16 lbda_brate_lut_interp[64];
  556. u16 lbda_bf_lut_interp[64];
  557. u8 num_of_active_ss;
  558. u8 bits_per_component;
  559. u16 max_pixels_per_line;
  560. u16 max_pixels_per_hs_line;
  561. u16 max_lines_per_frame;
  562. u16 max_lines_per_slice;
  563. u16 chunk_size;
  564. u16 chunk_size_bits;
  565. u16 avg_block_bits;
  566. u16 per_chunk_pad_bits;
  567. u16 tot_pad_bits;
  568. u16 rc_stuffing_bits;
  569. u16 chunk_adj_bits;
  570. u16 rc_buf_init_size_temp;
  571. u16 init_tx_delay_temp;
  572. u16 rc_buffer_init_size;
  573. u16 rc_init_tx_delay;
  574. u16 rc_init_tx_delay_px_times;
  575. u16 rc_buffer_max_size;
  576. u16 rc_tar_rate_scale_temp_a;
  577. u16 rc_tar_rate_scale_temp_b;
  578. u16 rc_tar_rate_scale;
  579. u16 block_max_bits;
  580. u16 rc_lambda_bitrate_scale;
  581. u16 rc_buffer_fullness_scale;
  582. u16 rc_fullness_offset_thresh;
  583. u16 ramp_blocks;
  584. u16 bits_per_pixel;
  585. u16 num_extra_mux_bits_init;
  586. u16 extra_crop_bits;
  587. u16 num_extra_mux_bits;
  588. u16 mppf_bits_comp_0;
  589. u16 mppf_bits_comp_1;
  590. u16 mppf_bits_comp_2;
  591. u16 min_block_bits;
  592. int slice_height;
  593. int slice_width;
  594. int frame_width;
  595. int frame_height;
  596. int bytes_in_slice;
  597. int bytes_per_pkt;
  598. int eol_byte_num;
  599. int pclk_per_line;
  600. int slice_per_pkt;
  601. int pkt_per_line;
  602. int min_ssm_delay;
  603. int max_ssm_delay;
  604. int input_ssm_out_latency;
  605. int input_ssm_out_latency_min;
  606. int obuf_latency;
  607. int base_hs_latency;
  608. int base_hs_latency_min;
  609. int base_hs_latency_pixels;
  610. int base_hs_latency_pixels_min;
  611. int base_initial_lines;
  612. int base_top_up;
  613. int output_rate;
  614. int output_rate_ratio_100;
  615. int burst_accum_pixels;
  616. int ss_initial_lines;
  617. int burst_initial_lines;
  618. int initial_lines;
  619. int obuf_base;
  620. int obuf_extra_ss0;
  621. int obuf_extra_ss1;
  622. int obuf_extra_burst;
  623. int obuf_ss0;
  624. int obuf_ss1;
  625. int obuf_margin_words;
  626. int ob0_max_addr;
  627. int ob1_max_addr;
  628. int slice_width_orig;
  629. int r2b0_max_addr;
  630. int r2b1_max_addr;
  631. u32 slice_num_px;
  632. u32 rc_target_rate_threshold;
  633. u32 rc_fullness_offset_slope;
  634. u32 pps_delay_ms;
  635. u32 version_release;
  636. u64 slice_num_bits;
  637. u64 ramp_bits;
  638. };
  639. /**
  640. * Bits/pixel target >> 4 (removing the fractional bits)
  641. * returns the integer bpp value from the drm_dsc_config struct
  642. */
  643. #define DSC_BPP(config) ((config).bits_per_pixel >> 4)
  644. /**
  645. * struct msm_compression_info - defined panel compression
  646. * @enabled: enabled/disabled
  647. * @comp_type: type of compression supported
  648. * @comp_ratio: compression ratio
  649. * @src_bpp: bits per pixel before compression
  650. * @tgt_bpp: bits per pixel after compression
  651. * @dsc_info: dsc configuration if the compression
  652. * supported is DSC
  653. * @vdc_info: vdc configuration if the compression
  654. * supported is VDC
  655. */
  656. struct msm_compression_info {
  657. bool enabled;
  658. enum msm_display_compression_type comp_type;
  659. u32 comp_ratio;
  660. u32 src_bpp;
  661. u32 tgt_bpp;
  662. union{
  663. struct msm_display_dsc_info dsc_info;
  664. struct msm_display_vdc_info vdc_info;
  665. };
  666. };
  667. /**
  668. * struct msm_display_topology - defines a display topology pipeline
  669. * @num_lm: number of layer mixers used
  670. * @num_enc: number of compression encoder blocks used
  671. * @num_intf: number of interfaces the panel is mounted on
  672. * @comp_type: type of compression supported
  673. */
  674. struct msm_display_topology {
  675. u32 num_lm;
  676. u32 num_enc;
  677. u32 num_intf;
  678. enum msm_display_compression_type comp_type;
  679. };
  680. /**
  681. * struct msm_dyn_clk_list - list of dynamic clock rates.
  682. * @count: number of supported clock rates
  683. * @rates: list of supported clock rates
  684. * @type: dynamic clock feature support type
  685. * @front_porches: list of clock rate matching porch compensation values
  686. * @pixel_clks_khz: list of clock rate matching pixel clock values
  687. */
  688. struct msm_dyn_clk_list {
  689. u32 count;
  690. u32 *rates;
  691. u32 type;
  692. u32 *front_porches;
  693. u32 *pixel_clks_khz;
  694. };
  695. /**
  696. * struct msm_display_wd_jitter_config - defines jitter properties for WD timer
  697. * @jitter_type: Type of WD jitter enabled.
  698. * @inst_jitter_numer: Instantaneous jitter numerator.
  699. * @inst_jitter_denom: Instantaneous jitter denominator.
  700. * @ltj_max_numer: LTJ max numerator.
  701. * @ltj_max_denom: LTJ max denominator.
  702. * @ltj_time_sec: LTJ time in seconds.
  703. */
  704. struct msm_display_wd_jitter_config {
  705. enum msm_display_wd_jitter_type jitter_type;
  706. u32 inst_jitter_numer;
  707. u32 inst_jitter_denom;
  708. u32 ltj_max_numer;
  709. u32 ltj_max_denom;
  710. u32 ltj_time_sec;
  711. };
  712. /**
  713. * struct msm_mode_info - defines all msm custom mode info
  714. * @frame_rate: frame_rate of the mode
  715. * @vtotal: vtotal calculated for the mode
  716. * @prefill_lines: prefill lines based on porches.
  717. * @jitter_numer: display panel jitter numerator configuration
  718. * @jitter_denom: display panel jitter denominator configuration
  719. * @clk_rate: DSI bit clock per lane in HZ.
  720. * @dfps_maxfps: max FPS of dynamic FPS
  721. * @topology: supported topology for the mode
  722. * @comp_info: compression info supported
  723. * @roi_caps: panel roi capabilities
  724. * @wide_bus_en: wide-bus mode cfg for interface module
  725. * @panel_mode_caps panel mode capabilities
  726. * @mdp_transfer_time_us Specifies the mdp transfer time for command mode
  727. * panels in microseconds.
  728. * @mdp_transfer_time_us_min Specifies the minimum possible mdp transfer time
  729. * for command mode panels in microseconds.
  730. * @mdp_transfer_time_us_max Specifies the maximum possible mdp transfer time
  731. * for command mode panels in microseconds.
  732. * @allowed_mode_switches: bit mask to indicate supported mode switch.
  733. * @disable_rsc_solver: Dynamically disable RSC solver for the timing mode due to lower bitclk rate.
  734. * @dyn_clk_list: List of dynamic clock rates for RFI.
  735. * @qsync_min_fps: qsync min fps rate
  736. * @wd_jitter: Info for WD jitter.
  737. */
  738. struct msm_mode_info {
  739. uint32_t frame_rate;
  740. uint32_t vtotal;
  741. uint32_t prefill_lines;
  742. uint32_t jitter_numer;
  743. uint32_t jitter_denom;
  744. uint64_t clk_rate;
  745. uint32_t dfps_maxfps;
  746. struct msm_display_topology topology;
  747. struct msm_compression_info comp_info;
  748. struct msm_roi_caps roi_caps;
  749. bool wide_bus_en;
  750. u32 panel_mode_caps;
  751. u32 mdp_transfer_time_us;
  752. u32 mdp_transfer_time_us_min;
  753. u32 mdp_transfer_time_us_max;
  754. u32 allowed_mode_switches;
  755. bool disable_rsc_solver;
  756. struct msm_dyn_clk_list dyn_clk_list;
  757. u32 qsync_min_fps;
  758. struct msm_display_wd_jitter_config wd_jitter;
  759. };
  760. /**
  761. * struct msm_resource_caps_info - defines hw resources
  762. * @num_lm number of layer mixers available
  763. * @num_dsc number of dsc available
  764. * @num_vdc number of vdc available
  765. * @num_ctl number of ctl available
  766. * @num_3dmux number of 3d mux available
  767. * @max_mixer_width: max width supported by layer mixer
  768. */
  769. struct msm_resource_caps_info {
  770. uint32_t num_lm;
  771. uint32_t num_dsc;
  772. uint32_t num_vdc;
  773. uint32_t num_ctl;
  774. uint32_t num_3dmux;
  775. uint32_t max_mixer_width;
  776. };
  777. /**
  778. * struct msm_display_info - defines display properties
  779. * @intf_type: DRM_MODE_CONNECTOR_ display type
  780. * @capabilities: Bitmask of display flags
  781. * @num_of_h_tiles: Number of horizontal tiles in case of split interface
  782. * @h_tile_instance: Controller instance used per tile. Number of elements is
  783. * based on num_of_h_tiles
  784. * @is_connected: Set to true if display is connected
  785. * @width_mm: Physical width
  786. * @height_mm: Physical height
  787. * @max_width: Max width of display. In case of hot pluggable display
  788. * this is max width supported by controller
  789. * @max_height: Max height of display. In case of hot pluggable display
  790. * this is max height supported by controller
  791. * @clk_rate: DSI bit clock per lane in HZ.
  792. * @display_type: Enum for type of display
  793. * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
  794. * used instead of panel TE in cmd mode panels
  795. * @poms_align_vsync: poms with vsync aligned
  796. * @roi_caps: Region of interest capability info
  797. * @qsync_min_fps Minimum fps supported by Qsync feature
  798. * @has_qsync_min_fps_list True if dsi-supported-qsync-min-fps-list exits
  799. * @has_avr_step_req Panel has defined requirement for AVR steps
  800. * @te_source vsync source pin information
  801. * @dsc_count: max dsc hw blocks used by display (only available
  802. * for dsi display)
  803. * @lm_count: max layer mixer blocks used by display (only available
  804. * for dsi display)
  805. */
  806. struct msm_display_info {
  807. int intf_type;
  808. uint32_t capabilities;
  809. enum panel_op_mode curr_panel_mode;
  810. uint32_t num_of_h_tiles;
  811. uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
  812. bool is_connected;
  813. unsigned int width_mm;
  814. unsigned int height_mm;
  815. uint32_t max_width;
  816. uint32_t max_height;
  817. uint64_t clk_rate;
  818. uint32_t display_type;
  819. bool is_te_using_watchdog_timer;
  820. bool poms_align_vsync;
  821. struct msm_roi_caps roi_caps;
  822. uint32_t qsync_min_fps;
  823. bool has_qsync_min_fps_list;
  824. bool has_avr_step_req;
  825. uint32_t te_source;
  826. uint32_t dsc_count;
  827. uint32_t lm_count;
  828. };
  829. #define MSM_MAX_ROI 4
  830. /**
  831. * struct msm_roi_list - list of regions of interest for a drm object
  832. * @num_rects: number of valid rectangles in the roi array
  833. * @roi: list of roi rectangles
  834. */
  835. struct msm_roi_list {
  836. uint32_t num_rects;
  837. struct drm_clip_rect roi[MSM_MAX_ROI];
  838. };
  839. /**
  840. * struct - msm_display_kickoff_params - info for display features at kickoff
  841. * @rois: Regions of interest structure for mapping CRTC to Connector output
  842. */
  843. struct msm_display_kickoff_params {
  844. struct msm_roi_list *rois;
  845. struct drm_msm_ext_hdr_metadata *hdr_meta;
  846. };
  847. /**
  848. * struct - msm_display_conn_params - info of dpu display features
  849. * @qsync_mode: Qsync mode, where 0: disabled 1: continuous mode 2: oneshot
  850. * @qsync_update: Qsync settings were changed/updated
  851. */
  852. struct msm_display_conn_params {
  853. uint32_t qsync_mode;
  854. bool qsync_update;
  855. };
  856. /**
  857. * struct msm_drm_event - defines custom event notification struct
  858. * @base: base object required for event notification by DRM framework.
  859. * @event: event object required for event notification by DRM framework.
  860. */
  861. struct msm_drm_event {
  862. struct drm_pending_event base;
  863. struct drm_msm_event_resp event;
  864. };
  865. /* Commit/Event thread specific structure */
  866. struct msm_drm_thread {
  867. struct drm_device *dev;
  868. struct task_struct *thread;
  869. unsigned int crtc_id;
  870. struct kthread_worker worker;
  871. };
  872. struct msm_drm_private {
  873. struct drm_device *dev;
  874. struct msm_kms *kms;
  875. struct sde_power_handle phandle;
  876. /* subordinate devices, if present: */
  877. struct platform_device *gpu_pdev;
  878. /* top level MDSS wrapper device (for MDP5 only) */
  879. struct msm_mdss *mdss;
  880. /* possibly this should be in the kms component, but it is
  881. * shared by both mdp4 and mdp5..
  882. */
  883. struct hdmi *hdmi;
  884. /* eDP is for mdp5 only, but kms has not been created
  885. * when edp_bind() and edp_init() are called. Here is the only
  886. * place to keep the edp instance.
  887. */
  888. struct msm_edp *edp;
  889. /* DSI is shared by mdp4 and mdp5 */
  890. struct msm_dsi *dsi[2];
  891. /* when we have more than one 'msm_gpu' these need to be an array: */
  892. struct msm_gpu *gpu;
  893. struct msm_file_private *lastctx;
  894. struct drm_fb_helper *fbdev;
  895. struct msm_rd_state *rd; /* debugfs to dump all submits */
  896. struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
  897. struct msm_perf_state *perf;
  898. /*
  899. * List of inactive GEM objects. Every bo is either in the inactive_list
  900. * or gpu->active_list (for the gpu it is active on[1])
  901. *
  902. * These lists are protected by mm_lock. If struct_mutex is involved, it
  903. * should be aquired prior to mm_lock. One should *not* hold mm_lock in
  904. * get_pages()/vmap()/etc paths, as they can trigger the shrinker.
  905. *
  906. * [1] if someone ever added support for the old 2d cores, there could be
  907. * more than one gpu object
  908. */
  909. struct list_head inactive_list;
  910. struct mutex mm_lock;
  911. struct workqueue_struct *wq;
  912. /* crtcs pending async atomic updates: */
  913. uint32_t pending_crtcs;
  914. uint32_t pending_planes;
  915. wait_queue_head_t pending_crtcs_event;
  916. unsigned int num_planes;
  917. struct drm_plane *planes[MAX_PLANES];
  918. unsigned int num_crtcs;
  919. struct drm_crtc *crtcs[MAX_CRTCS];
  920. struct msm_drm_thread disp_thread[MAX_CRTCS];
  921. struct msm_drm_thread event_thread[MAX_CRTCS];
  922. struct task_struct *pp_event_thread;
  923. struct kthread_worker pp_event_worker;
  924. struct kthread_work thread_priority_work;
  925. unsigned int num_encoders;
  926. struct drm_encoder *encoders[MAX_ENCODERS];
  927. unsigned int num_bridges;
  928. struct drm_bridge *bridges[MAX_BRIDGES];
  929. unsigned int num_connectors;
  930. struct drm_connector *connectors[MAX_CONNECTORS];
  931. /* Properties */
  932. struct drm_property *plane_property[PLANE_PROP_COUNT];
  933. struct drm_property *crtc_property[CRTC_PROP_COUNT];
  934. struct drm_property *conn_property[CONNECTOR_PROP_COUNT];
  935. /* Color processing properties for the crtc */
  936. struct drm_property **cp_property;
  937. /* VRAM carveout, used when no IOMMU: */
  938. struct {
  939. unsigned long size;
  940. dma_addr_t paddr;
  941. /* NOTE: mm managed at the page level, size is in # of pages
  942. * and position mm_node->start is in # of pages:
  943. */
  944. struct drm_mm mm;
  945. spinlock_t lock; /* Protects drm_mm node allocation/removal */
  946. } vram;
  947. struct notifier_block vmap_notifier;
  948. struct shrinker shrinker;
  949. struct drm_atomic_state *pm_state;
  950. /* task holding struct_mutex.. currently only used in submit path
  951. * to detect and reject faults from copy_from_user() for submit
  952. * ioctl.
  953. */
  954. struct task_struct *struct_mutex_task;
  955. /* list of clients waiting for events */
  956. struct list_head client_event_list;
  957. /* whether registered and drm_dev_unregister should be called */
  958. bool registered;
  959. /* msm drv debug root node */
  960. struct dentry *debug_root;
  961. /* update the flag when msm driver receives shutdown notification */
  962. bool shutdown_in_progress;
  963. struct mutex vm_client_lock;
  964. struct list_head vm_client_list;
  965. };
  966. /* get struct msm_kms * from drm_device * */
  967. #define ddev_to_msm_kms(D) ((D) && (D)->dev_private ? \
  968. ((struct msm_drm_private *)((D)->dev_private))->kms : NULL)
  969. struct msm_format {
  970. uint32_t pixel_format;
  971. };
  972. int msm_atomic_prepare_fb(struct drm_plane *plane,
  973. struct drm_plane_state *new_state);
  974. void msm_atomic_commit_tail(struct drm_atomic_state *state);
  975. int msm_atomic_commit(struct drm_device *dev,
  976. struct drm_atomic_state *state, bool nonblock);
  977. /* callback from wq once fence has passed: */
  978. struct msm_fence_cb {
  979. struct work_struct work;
  980. uint32_t fence;
  981. void (*func)(struct msm_fence_cb *cb);
  982. };
  983. void __msm_fence_worker(struct work_struct *work);
  984. #define INIT_FENCE_CB(_cb, _func) do { \
  985. INIT_WORK(&(_cb)->work, __msm_fence_worker); \
  986. (_cb)->func = _func; \
  987. } while (0)
  988. struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
  989. void msm_atomic_state_clear(struct drm_atomic_state *state);
  990. void msm_atomic_state_free(struct drm_atomic_state *state);
  991. int msm_gem_init_vma(struct msm_gem_address_space *aspace,
  992. struct msm_gem_vma *vma, int npages);
  993. void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
  994. struct msm_gem_vma *vma, struct sg_table *sgt,
  995. unsigned int flags);
  996. int msm_gem_map_vma(struct msm_gem_address_space *aspace,
  997. struct msm_gem_vma *vma, struct sg_table *sgt, int npages,
  998. unsigned int flags);
  999. struct device *msm_gem_get_aspace_device(struct msm_gem_address_space *aspace);
  1000. void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
  1001. /* For SDE display */
  1002. struct msm_gem_address_space *
  1003. msm_gem_smmu_address_space_create(struct drm_device *dev, struct msm_mmu *mmu,
  1004. const char *name);
  1005. /**
  1006. * msm_gem_add_obj_to_aspace_active_list: adds obj to active obj list in aspace
  1007. */
  1008. void msm_gem_add_obj_to_aspace_active_list(
  1009. struct msm_gem_address_space *aspace,
  1010. struct drm_gem_object *obj);
  1011. /**
  1012. * msm_gem_remove_obj_from_aspace_active_list: removes obj from active obj
  1013. * list in aspace
  1014. */
  1015. void msm_gem_remove_obj_from_aspace_active_list(
  1016. struct msm_gem_address_space *aspace,
  1017. struct drm_gem_object *obj);
  1018. /**
  1019. * msm_gem_smmu_address_space_get: returns the aspace pointer for the requested
  1020. * domain
  1021. */
  1022. struct msm_gem_address_space *
  1023. msm_gem_smmu_address_space_get(struct drm_device *dev,
  1024. unsigned int domain);
  1025. int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
  1026. void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
  1027. /**
  1028. * msm_gem_aspace_domain_attach_detach: function to inform the attach/detach
  1029. * of the domain for this aspace
  1030. */
  1031. void msm_gem_aspace_domain_attach_detach_update(
  1032. struct msm_gem_address_space *aspace,
  1033. bool is_detach);
  1034. /**
  1035. * msm_gem_address_space_register_cb: function to register callback for attach
  1036. * and detach of the domain
  1037. */
  1038. int msm_gem_address_space_register_cb(
  1039. struct msm_gem_address_space *aspace,
  1040. void (*cb)(void *, bool),
  1041. void *cb_data);
  1042. /**
  1043. * msm_gem_address_space_register_cb: function to unregister callback
  1044. */
  1045. int msm_gem_address_space_unregister_cb(
  1046. struct msm_gem_address_space *aspace,
  1047. void (*cb)(void *, bool),
  1048. void *cb_data);
  1049. void msm_gem_submit_free(struct msm_gem_submit *submit);
  1050. int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
  1051. struct drm_file *file);
  1052. void msm_gem_shrinker_init(struct drm_device *dev);
  1053. void msm_gem_shrinker_cleanup(struct drm_device *dev);
  1054. void msm_gem_sync(struct drm_gem_object *obj);
  1055. int msm_gem_mmap_obj(struct drm_gem_object *obj,
  1056. struct vm_area_struct *vma);
  1057. int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
  1058. uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
  1059. int msm_gem_get_iova(struct drm_gem_object *obj,
  1060. struct msm_gem_address_space *aspace, uint64_t *iova);
  1061. uint64_t msm_gem_iova(struct drm_gem_object *obj,
  1062. struct msm_gem_address_space *aspace);
  1063. void msm_gem_unpin_iova(struct drm_gem_object *obj,
  1064. struct msm_gem_address_space *aspace);
  1065. struct page **msm_gem_get_pages(struct drm_gem_object *obj);
  1066. void msm_gem_put_pages(struct drm_gem_object *obj);
  1067. void msm_gem_put_iova(struct drm_gem_object *obj,
  1068. struct msm_gem_address_space *aspace);
  1069. dma_addr_t msm_gem_get_dma_addr(struct drm_gem_object *obj);
  1070. int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
  1071. struct drm_mode_create_dumb *args);
  1072. int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
  1073. uint32_t handle, uint64_t *offset);
  1074. struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
  1075. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  1076. int msm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
  1077. void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
  1078. #else
  1079. void *msm_gem_prime_vmap(struct drm_gem_object *obj);
  1080. void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
  1081. vm_fault_t msm_gem_fault(struct vm_fault *vmf);
  1082. #endif
  1083. int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
  1084. struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
  1085. struct dma_buf_attachment *attach, struct sg_table *sg);
  1086. int msm_gem_prime_pin(struct drm_gem_object *obj);
  1087. void msm_gem_prime_unpin(struct drm_gem_object *obj);
  1088. struct drm_gem_object *msm_gem_prime_import(struct drm_device *dev,
  1089. struct dma_buf *dma_buf);
  1090. void *msm_gem_get_vaddr(struct drm_gem_object *obj);
  1091. void msm_gem_put_vaddr(struct drm_gem_object *obj);
  1092. int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
  1093. int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
  1094. int msm_gem_cpu_fini(struct drm_gem_object *obj);
  1095. void msm_gem_free_object(struct drm_gem_object *obj);
  1096. int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
  1097. uint32_t size, uint32_t flags, uint32_t *handle, char *name);
  1098. struct drm_gem_object *msm_gem_new(struct drm_device *dev,
  1099. uint32_t size, uint32_t flags);
  1100. struct drm_gem_object *msm_gem_import(struct drm_device *dev,
  1101. struct dma_buf *dmabuf, struct sg_table *sgt);
  1102. __printf(2, 3)
  1103. void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...);
  1104. int msm_gem_delayed_import(struct drm_gem_object *obj);
  1105. #define MSM_FB_CACHE_NONE 0x0
  1106. #define MSM_FB_CACHE_WRITE_EN 0x1
  1107. #define MSM_FB_CACHE_READ_EN 0x2
  1108. int msm_framebuffer_prepare(struct drm_framebuffer *fb,
  1109. struct msm_gem_address_space *aspace);
  1110. void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
  1111. struct msm_gem_address_space *aspace);
  1112. uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
  1113. struct msm_gem_address_space *aspace, int plane);
  1114. uint32_t msm_framebuffer_phys(struct drm_framebuffer *fb, int plane);
  1115. struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
  1116. const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
  1117. struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
  1118. const struct drm_mode_fb_cmd2 *mode_cmd,
  1119. struct drm_gem_object **bos);
  1120. struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
  1121. struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
  1122. void msm_framebuffer_set_cache_hint(struct drm_framebuffer *fb, u32 flags, u32 type);
  1123. void msm_framebuffer_get_cache_hint(struct drm_framebuffer *fb, u32 *flags, u32 *type);
  1124. struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
  1125. void msm_fbdev_free(struct drm_device *dev);
  1126. struct hdmi;
  1127. #if IS_ENABLED(CONFIG_DRM_MSM_HDMI)
  1128. int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
  1129. struct drm_encoder *encoder);
  1130. void __init msm_hdmi_register(void);
  1131. void __exit msm_hdmi_unregister(void);
  1132. #else
  1133. static inline void __init msm_hdmi_register(void)
  1134. {
  1135. }
  1136. static inline void __exit msm_hdmi_unregister(void)
  1137. {
  1138. }
  1139. #endif /* CONFIG_DRM_MSM_HDMI */
  1140. struct msm_edp;
  1141. #if IS_ENABLED(CONFIG_DRM_MSM_EDP)
  1142. void __init msm_edp_register(void);
  1143. void __exit msm_edp_unregister(void);
  1144. int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
  1145. struct drm_encoder *encoder);
  1146. #else
  1147. static inline void __init msm_edp_register(void)
  1148. {
  1149. }
  1150. static inline void __exit msm_edp_unregister(void)
  1151. {
  1152. }
  1153. static inline int msm_edp_modeset_init(struct msm_edp *edp,
  1154. struct drm_device *dev, struct drm_encoder *encoder)
  1155. {
  1156. return -EINVAL;
  1157. }
  1158. #endif /* CONFIG_DRM_MSM_EDP */
  1159. struct msm_dsi;
  1160. /* *
  1161. * msm_mode_object_event_notify - notify user-space clients of drm object
  1162. * events.
  1163. * @obj: mode object (crtc/connector) that is generating the event.
  1164. * @event: event that needs to be notified.
  1165. * @payload: payload for the event.
  1166. */
  1167. void msm_mode_object_event_notify(struct drm_mode_object *obj,
  1168. struct drm_device *dev, struct drm_event *event, u8 *payload);
  1169. #if IS_ENABLED(CONFIG_DRM_MSM_DSI)
  1170. static inline void __init msm_dsi_register(void)
  1171. {
  1172. }
  1173. static inline void __exit msm_dsi_unregister(void)
  1174. {
  1175. }
  1176. static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
  1177. struct drm_device *dev,
  1178. struct drm_encoder *encoder)
  1179. {
  1180. return -EINVAL;
  1181. }
  1182. #else
  1183. void __init msm_dsi_register(void);
  1184. void __exit msm_dsi_unregister(void);
  1185. int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
  1186. struct drm_encoder *encoder);
  1187. #endif /* CONFIG_DRM_MSM_DSI */
  1188. #if IS_ENABLED(CONFIG_DRM_MSM_MDP5)
  1189. void __init msm_mdp_register(void);
  1190. void __exit msm_mdp_unregister(void);
  1191. #else
  1192. static inline void __init msm_mdp_register(void)
  1193. {
  1194. }
  1195. static inline void __exit msm_mdp_unregister(void)
  1196. {
  1197. }
  1198. #endif /* CONFIG_DRM_MSM_MDP5 */
  1199. #if IS_ENABLED(CONFIG_DEBUG_FS)
  1200. int msm_debugfs_late_init(struct drm_device *dev);
  1201. int msm_rd_debugfs_init(struct drm_minor *minor);
  1202. void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
  1203. __printf(3, 4)
  1204. void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
  1205. const char *fmt, ...);
  1206. int msm_perf_debugfs_init(struct drm_minor *minor);
  1207. void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
  1208. #else
  1209. static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
  1210. __printf(3, 4)
  1211. static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
  1212. const char *fmt, ...) {}
  1213. static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
  1214. static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
  1215. #endif /* CONFIG_DEBUG_FS */
  1216. #if IS_ENABLED(CONFIG_DRM_MSM_DSI)
  1217. void __init dsi_display_register(void);
  1218. void __exit dsi_display_unregister(void);
  1219. #else
  1220. static inline void __init dsi_display_register(void)
  1221. {
  1222. }
  1223. static inline void __exit dsi_display_unregister(void)
  1224. {
  1225. }
  1226. #endif /* CONFIG_DRM_MSM_DSI */
  1227. #if IS_ENABLED(CONFIG_HDCP_QSEECOM)
  1228. void __init msm_hdcp_register(void);
  1229. void __exit msm_hdcp_unregister(void);
  1230. #else
  1231. static inline void __init msm_hdcp_register(void)
  1232. {
  1233. }
  1234. static inline void __exit msm_hdcp_unregister(void)
  1235. {
  1236. }
  1237. #endif /* CONFIG_HDCP_QSEECOM */
  1238. #if IS_ENABLED(CONFIG_DRM_MSM_DP)
  1239. void __init dp_display_register(void);
  1240. void __exit dp_display_unregister(void);
  1241. #else
  1242. static inline void __init dp_display_register(void)
  1243. {
  1244. }
  1245. static inline void __exit dp_display_unregister(void)
  1246. {
  1247. }
  1248. #endif /* CONFIG_DRM_MSM_DP */
  1249. #if IS_ENABLED(CONFIG_DRM_SDE_RSC)
  1250. void __init sde_rsc_register(void);
  1251. void __exit sde_rsc_unregister(void);
  1252. void __init sde_rsc_rpmh_register(void);
  1253. #else
  1254. static inline void __init sde_rsc_register(void)
  1255. {
  1256. }
  1257. static inline void __exit sde_rsc_unregister(void)
  1258. {
  1259. }
  1260. static inline void __init sde_rsc_rpmh_register(void)
  1261. {
  1262. }
  1263. #endif /* CONFIG_DRM_SDE_RSC */
  1264. #if IS_ENABLED(CONFIG_DRM_SDE_WB)
  1265. void __init sde_wb_register(void);
  1266. void __exit sde_wb_unregister(void);
  1267. #else
  1268. static inline void __init sde_wb_register(void)
  1269. {
  1270. }
  1271. static inline void __exit sde_wb_unregister(void)
  1272. {
  1273. }
  1274. #endif /* CONFIG_DRM_SDE_WB */
  1275. #if IS_ENABLED(CONFIG_MSM_SDE_ROTATOR)
  1276. void sde_rotator_register(void);
  1277. void sde_rotator_unregister(void);
  1278. #else
  1279. static inline void sde_rotator_register(void)
  1280. {
  1281. }
  1282. static inline void sde_rotator_unregister(void)
  1283. {
  1284. }
  1285. #endif /* CONFIG_MSM_SDE_ROTATOR */
  1286. #if IS_ENABLED(CONFIG_MSM_SDE_ROTATOR)
  1287. void sde_rotator_smmu_driver_register(void);
  1288. void sde_rotator_smmu_driver_unregister(void);
  1289. #else
  1290. static inline void sde_rotator_smmu_driver_register(void)
  1291. {
  1292. }
  1293. static inline void sde_rotator_smmu_driver_unregister(void)
  1294. {
  1295. }
  1296. #endif /* CONFIG_MSM_SDE_ROTATOR */
  1297. struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
  1298. int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk);
  1299. struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
  1300. const char *name);
  1301. void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
  1302. const char *dbgname);
  1303. unsigned long msm_iomap_size(struct platform_device *pdev, const char *name);
  1304. unsigned long msm_get_phys_addr(struct platform_device *pdev, const char *name);
  1305. void msm_iounmap(struct platform_device *dev, void __iomem *addr);
  1306. void msm_writel(u32 data, void __iomem *addr);
  1307. u32 msm_readl(const void __iomem *addr);
  1308. #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
  1309. #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
  1310. static inline int align_pitch(int width, int bpp)
  1311. {
  1312. int bytespp = (bpp + 7) / 8;
  1313. /* adreno needs pitch aligned to 32 pixels: */
  1314. return bytespp * ALIGN(width, 32);
  1315. }
  1316. /* for the generated headers: */
  1317. #define INVALID_IDX(idx) ({BUG(); 0;})
  1318. #define fui(x) ({BUG(); 0;})
  1319. #define util_float_to_half(x) ({BUG(); 0;})
  1320. #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
  1321. /* for conditionally setting boolean flag(s): */
  1322. #define COND(bool, val) ((bool) ? (val) : 0)
  1323. static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
  1324. {
  1325. ktime_t now = ktime_get();
  1326. unsigned long remaining_jiffies;
  1327. if (ktime_compare(*timeout, now) < 0) {
  1328. remaining_jiffies = 0;
  1329. } else {
  1330. ktime_t rem = ktime_sub(*timeout, now);
  1331. remaining_jiffies = nsecs_to_jiffies(ktime_to_ns(rem));
  1332. }
  1333. return remaining_jiffies;
  1334. }
  1335. int msm_get_mixer_count(struct msm_drm_private *priv,
  1336. const struct drm_display_mode *mode,
  1337. const struct msm_resource_caps_info *res, u32 *num_lm);
  1338. int msm_get_dsc_count(struct msm_drm_private *priv,
  1339. u32 hdisplay, u32 *num_dsc);
  1340. int msm_get_src_bpc(int chroma_format, int bpc);
  1341. #endif /* __MSM_DRV_H__ */