aqt1000-mbhc.c 32 KB

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  1. /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/device.h>
  16. #include <linux/printk.h>
  17. #include <linux/ratelimit.h>
  18. #include <linux/kernel.h>
  19. #include <linux/gpio.h>
  20. #include <linux/delay.h>
  21. #include <linux/regmap.h>
  22. #include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include "aqt.h"
  28. #include "aqt-mbhc.h"
  29. #include <asoc/aqt_registers.h>
  30. #include "aqt_irq.h"
  31. #include "pdata.h"
  32. #include "../wcd9xxx-irq.h"
  33. #include "../wcdcal-hwdep.h"
  34. #include "../wcd-mbhc-v2-api.h"
  35. #define AQT_ZDET_SUPPORTED true
  36. /* Z value defined in milliohm */
  37. #define AQT_ZDET_VAL_32 32000
  38. #define AQT_ZDET_VAL_400 400000
  39. #define AQT_ZDET_VAL_1200 1200000
  40. #define AQT_ZDET_VAL_100K 100000000
  41. /* Z floating defined in ohms */
  42. #define AQT_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE
  43. #define AQT_ZDET_NUM_MEASUREMENTS 900
  44. #define AQT_MBHC_GET_C1(c) ((c & 0xC000) >> 14)
  45. #define AQT_MBHC_GET_X1(x) (x & 0x3FFF)
  46. /* Z value compared in milliOhm */
  47. #define AQT_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
  48. #define AQT_MBHC_ZDET_CONST (86 * 16384)
  49. #define AQT_MBHC_MOISTURE_RREF R_24_KOHM
  50. static struct wcd_mbhc_register
  51. wcd_mbhc_registers[WCD_MBHC_REG_FUNC_MAX] = {
  52. WCD_MBHC_REGISTER("WCD_MBHC_L_DET_EN",
  53. AQT_ANA_MBHC_MECH, 0x80, 7, 0),
  54. WCD_MBHC_REGISTER("WCD_MBHC_GND_DET_EN",
  55. AQT_ANA_MBHC_MECH, 0x40, 6, 0),
  56. WCD_MBHC_REGISTER("WCD_MBHC_MECH_DETECTION_TYPE",
  57. AQT_ANA_MBHC_MECH, 0x20, 5, 0),
  58. WCD_MBHC_REGISTER("WCD_MBHC_MIC_CLAMP_CTL",
  59. AQT_MBHC_NEW_PLUG_DETECT_CTL, 0x30, 4, 0),
  60. WCD_MBHC_REGISTER("WCD_MBHC_ELECT_DETECTION_TYPE",
  61. AQT_ANA_MBHC_ELECT, 0x08, 3, 0),
  62. WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_CTRL",
  63. AQT_MBHC_NEW_PLUG_DETECT_CTL, 0xC0, 6, 0),
  64. WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL",
  65. AQT_ANA_MBHC_MECH, 0x04, 2, 0),
  66. WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PLUG_TYPE",
  67. AQT_ANA_MBHC_MECH, 0x10, 4, 0),
  68. WCD_MBHC_REGISTER("WCD_MBHC_GND_PLUG_TYPE",
  69. AQT_ANA_MBHC_MECH, 0x08, 3, 0),
  70. WCD_MBHC_REGISTER("WCD_MBHC_SW_HPH_LP_100K_TO_GND",
  71. AQT_ANA_MBHC_MECH, 0x01, 0, 0),
  72. WCD_MBHC_REGISTER("WCD_MBHC_ELECT_SCHMT_ISRC",
  73. AQT_ANA_MBHC_ELECT, 0x06, 1, 0),
  74. WCD_MBHC_REGISTER("WCD_MBHC_FSM_EN",
  75. AQT_ANA_MBHC_ELECT, 0x80, 7, 0),
  76. WCD_MBHC_REGISTER("WCD_MBHC_INSREM_DBNC",
  77. AQT_MBHC_NEW_PLUG_DETECT_CTL, 0x0F, 0, 0),
  78. WCD_MBHC_REGISTER("WCD_MBHC_BTN_DBNC",
  79. AQT_MBHC_NEW_CTL_1, 0x03, 0, 0),
  80. WCD_MBHC_REGISTER("WCD_MBHC_HS_VREF",
  81. AQT_MBHC_NEW_CTL_2, 0x03, 0, 0),
  82. WCD_MBHC_REGISTER("WCD_MBHC_HS_COMP_RESULT",
  83. AQT_ANA_MBHC_RESULT_3, 0x08, 3, 0),
  84. WCD_MBHC_REGISTER("WCD_MBHC_MIC_SCHMT_RESULT",
  85. AQT_ANA_MBHC_RESULT_3, 0x20, 5, 0),
  86. WCD_MBHC_REGISTER("WCD_MBHC_HPHL_SCHMT_RESULT",
  87. AQT_ANA_MBHC_RESULT_3, 0x80, 7, 0),
  88. WCD_MBHC_REGISTER("WCD_MBHC_HPHR_SCHMT_RESULT",
  89. AQT_ANA_MBHC_RESULT_3, 0x40, 6, 0),
  90. WCD_MBHC_REGISTER("WCD_MBHC_OCP_FSM_EN",
  91. AQT_HPH_OCP_CTL, 0x10, 4, 0),
  92. WCD_MBHC_REGISTER("WCD_MBHC_BTN_RESULT",
  93. AQT_ANA_MBHC_RESULT_3, 0x07, 0, 0),
  94. WCD_MBHC_REGISTER("WCD_MBHC_BTN_ISRC_CTL",
  95. AQT_ANA_MBHC_ELECT, 0x70, 4, 0),
  96. WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT",
  97. AQT_ANA_MBHC_RESULT_3, 0xFF, 0, 0),
  98. WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL",
  99. AQT_ANA_MICB2, 0xC0, 6, 0),
  100. WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME",
  101. AQT_HPH_CNP_WG_TIME, 0xFF, 0, 0),
  102. WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN",
  103. AQT_ANA_HPH, 0x40, 6, 0),
  104. WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PA_EN",
  105. AQT_ANA_HPH, 0x80, 7, 0),
  106. WCD_MBHC_REGISTER("WCD_MBHC_HPH_PA_EN",
  107. AQT_ANA_HPH, 0xC0, 6, 0),
  108. WCD_MBHC_REGISTER("WCD_MBHC_SWCH_LEVEL_REMOVE",
  109. AQT_ANA_MBHC_RESULT_3, 0x10, 4, 0),
  110. WCD_MBHC_REGISTER("WCD_MBHC_PULLDOWN_CTRL",
  111. 0, 0, 0, 0),
  112. WCD_MBHC_REGISTER("WCD_MBHC_ANC_DET_EN",
  113. AQT_MBHC_CTL_BCS, 0x02, 1, 0),
  114. WCD_MBHC_REGISTER("WCD_MBHC_FSM_STATUS",
  115. AQT_MBHC_STATUS_SPARE_1, 0x01, 0, 0),
  116. WCD_MBHC_REGISTER("WCD_MBHC_MUX_CTL",
  117. AQT_MBHC_NEW_CTL_2, 0x70, 4, 0),
  118. WCD_MBHC_REGISTER("WCD_MBHC_HPHL_OCP_DET_EN",
  119. AQT_HPH_L_TEST, 0x01, 0, 0),
  120. WCD_MBHC_REGISTER("WCD_MBHC_HPHR_OCP_DET_EN",
  121. AQT_HPH_R_TEST, 0x01, 0, 0),
  122. WCD_MBHC_REGISTER("WCD_MBHC_HPHL_OCP_STATUS",
  123. AQT_INTR_PIN1_STATUS0, 0x04, 2, 0),
  124. WCD_MBHC_REGISTER("WCD_MBHC_HPHR_OCP_STATUS",
  125. AQT_INTR_PIN1_STATUS0, 0x08, 3, 0),
  126. WCD_MBHC_REGISTER("WCD_MBHC_ADC_EN",
  127. AQT_MBHC_NEW_CTL_1, 0x08, 3, 0),
  128. WCD_MBHC_REGISTER("WCD_MBHC_ADC_COMPLETE", AQT_MBHC_NEW_FSM_STATUS,
  129. 0x40, 6, 0),
  130. WCD_MBHC_REGISTER("WCD_MBHC_ADC_TIMEOUT", AQT_MBHC_NEW_FSM_STATUS,
  131. 0x80, 7, 0),
  132. WCD_MBHC_REGISTER("WCD_MBHC_ADC_RESULT", AQT_MBHC_NEW_ADC_RESULT,
  133. 0xFF, 0, 0),
  134. WCD_MBHC_REGISTER("WCD_MBHC_MICB2_VOUT", AQT_ANA_MICB2, 0x3F, 0, 0),
  135. WCD_MBHC_REGISTER("WCD_MBHC_ADC_MODE",
  136. AQT_MBHC_NEW_CTL_1, 0x10, 4, 0),
  137. WCD_MBHC_REGISTER("WCD_MBHC_DETECTION_DONE",
  138. AQT_MBHC_NEW_CTL_1, 0x04, 2, 0),
  139. WCD_MBHC_REGISTER("WCD_MBHC_ELECT_ISRC_EN",
  140. AQT_ANA_MBHC_ZDET, 0x02, 1, 0),
  141. };
  142. static const struct wcd_mbhc_intr intr_ids = {
  143. .mbhc_sw_intr = AQT_IRQ_MBHC_SW_DET,
  144. .mbhc_btn_press_intr = AQT_IRQ_MBHC_BUTTON_PRESS_DET,
  145. .mbhc_btn_release_intr = AQT_IRQ_MBHC_BUTTON_RELEASE_DET,
  146. .mbhc_hs_ins_intr = AQT_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
  147. .mbhc_hs_rem_intr = AQT_IRQ_MBHC_ELECT_INS_REM_DET,
  148. .hph_left_ocp = AQT_IRQ_HPH_PA_OCPL_FAULT,
  149. .hph_right_ocp = AQT_IRQ_HPH_PA_OCPR_FAULT,
  150. };
  151. static char on_demand_supply_name[][MAX_ON_DEMAND_SUPPLY_NAME_LENGTH] = {
  152. "cdc-vdd-mic-bias",
  153. };
  154. struct aqt_mbhc_zdet_param {
  155. u16 ldo_ctl;
  156. u16 noff;
  157. u16 nshift;
  158. u16 btn5;
  159. u16 btn6;
  160. u16 btn7;
  161. };
  162. static int aqt_mbhc_request_irq(struct snd_soc_codec *codec,
  163. int irq, irq_handler_t handler,
  164. const char *name, void *data)
  165. {
  166. struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
  167. struct wcd9xxx_core_resource *core_res =
  168. &wcd9xxx->core_res;
  169. return wcd9xxx_request_irq(core_res, irq, handler, name, data);
  170. }
  171. static void aqt_mbhc_irq_control(struct snd_soc_codec *codec,
  172. int irq, bool enable)
  173. {
  174. struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
  175. struct wcd9xxx_core_resource *core_res =
  176. &wcd9xxx->core_res;
  177. if (enable)
  178. wcd9xxx_enable_irq(core_res, irq);
  179. else
  180. wcd9xxx_disable_irq(core_res, irq);
  181. }
  182. static int aqt_mbhc_free_irq(struct snd_soc_codec *codec,
  183. int irq, void *data)
  184. {
  185. struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
  186. struct wcd9xxx_core_resource *core_res =
  187. &wcd9xxx->core_res;
  188. wcd9xxx_free_irq(core_res, irq, data);
  189. return 0;
  190. }
  191. static void aqt_mbhc_clk_setup(struct snd_soc_codec *codec,
  192. bool enable)
  193. {
  194. if (enable)
  195. snd_soc_update_bits(codec, AQT_MBHC_NEW_CTL_1,
  196. 0x80, 0x80);
  197. else
  198. snd_soc_update_bits(codec, AQT_MBHC_NEW_CTL_1,
  199. 0x80, 0x00);
  200. }
  201. static int aqt_mbhc_btn_to_num(struct snd_soc_codec *codec)
  202. {
  203. return snd_soc_read(codec, AQT_ANA_MBHC_RESULT_3) & 0x7;
  204. }
  205. static int aqt_enable_ext_mb_source(struct wcd_mbhc *mbhc,
  206. bool turn_on)
  207. {
  208. struct aqt_mbhc *aqt_mbhc;
  209. struct snd_soc_codec *codec = mbhc->codec;
  210. struct aqt_on_demand_supply *supply;
  211. int ret = 0;
  212. aqt_mbhc = container_of(mbhc, struct aqt_mbhc, wcd_mbhc);
  213. supply = &aqt_mbhc->on_demand_list[AQT_ON_DEMAND_MICBIAS];
  214. if (!supply->supply) {
  215. dev_dbg(codec->dev, "%s: warning supply not present ond for %s\n",
  216. __func__, "onDemand Micbias");
  217. return ret;
  218. }
  219. dev_dbg(codec->dev, "%s turn_on: %d count: %d\n", __func__, turn_on,
  220. supply->ondemand_supply_count);
  221. if (turn_on) {
  222. if (!(supply->ondemand_supply_count)) {
  223. ret = snd_soc_dapm_force_enable_pin(
  224. snd_soc_codec_get_dapm(codec),
  225. "MICBIAS_REGULATOR");
  226. snd_soc_dapm_sync(snd_soc_codec_get_dapm(codec));
  227. }
  228. supply->ondemand_supply_count++;
  229. } else {
  230. if (supply->ondemand_supply_count > 0)
  231. supply->ondemand_supply_count--;
  232. if (!(supply->ondemand_supply_count)) {
  233. ret = snd_soc_dapm_disable_pin(
  234. snd_soc_codec_get_dapm(codec),
  235. "MICBIAS_REGULATOR");
  236. snd_soc_dapm_sync(snd_soc_codec_get_dapm(codec));
  237. }
  238. }
  239. if (ret)
  240. dev_err(codec->dev, "%s: Failed to %s external micbias source\n",
  241. __func__, turn_on ? "enable" : "disabled");
  242. else
  243. dev_dbg(codec->dev, "%s: %s external micbias source\n",
  244. __func__, turn_on ? "Enabled" : "Disabled");
  245. return ret;
  246. }
  247. static void aqt_mbhc_mbhc_bias_control(struct snd_soc_codec *codec,
  248. bool enable)
  249. {
  250. if (enable)
  251. snd_soc_update_bits(codec, AQT_ANA_MBHC_ELECT,
  252. 0x01, 0x01);
  253. else
  254. snd_soc_update_bits(codec, AQT_ANA_MBHC_ELECT,
  255. 0x01, 0x00);
  256. }
  257. static void aqt_mbhc_program_btn_thr(struct snd_soc_codec *codec,
  258. s16 *btn_low, s16 *btn_high,
  259. int num_btn, bool is_micbias)
  260. {
  261. int i;
  262. int vth;
  263. if (num_btn > WCD_MBHC_DEF_BUTTONS) {
  264. dev_err(codec->dev, "%s: invalid number of buttons: %d\n",
  265. __func__, num_btn);
  266. return;
  267. }
  268. /*
  269. * Tavil just needs one set of thresholds for button detection
  270. * due to micbias voltage ramp to pullup upon button press. So
  271. * btn_low and is_micbias are ignored and always program button
  272. * thresholds using btn_high.
  273. */
  274. for (i = 0; i < num_btn; i++) {
  275. vth = ((btn_high[i] * 2) / 25) & 0x3F;
  276. snd_soc_update_bits(codec, AQT_ANA_MBHC_BTN0 + i,
  277. 0xFC, vth << 2);
  278. dev_dbg(codec->dev, "%s: btn_high[%d]: %d, vth: %d\n",
  279. __func__, i, btn_high[i], vth);
  280. }
  281. }
  282. static bool aqt_mbhc_lock_sleep(struct wcd_mbhc *mbhc, bool lock)
  283. {
  284. struct snd_soc_codec *codec = mbhc->codec;
  285. struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
  286. struct wcd9xxx_core_resource *core_res =
  287. &wcd9xxx->core_res;
  288. bool ret = 0;
  289. if (lock)
  290. ret = wcd9xxx_lock_sleep(core_res);
  291. else
  292. wcd9xxx_unlock_sleep(core_res);
  293. return ret;
  294. }
  295. static int aqt_mbhc_register_notifier(struct wcd_mbhc *mbhc,
  296. struct notifier_block *nblock,
  297. bool enable)
  298. {
  299. struct aqt_mbhc *aqt_mbhc;
  300. aqt_mbhc = container_of(mbhc, struct aqt_mbhc, wcd_mbhc);
  301. if (enable)
  302. return blocking_notifier_chain_register(&aqt_mbhc->notifier,
  303. nblock);
  304. else
  305. return blocking_notifier_chain_unregister(
  306. &aqt_mbhc->notifier, nblock);
  307. }
  308. static bool aqt_mbhc_micb_en_status(struct wcd_mbhc *mbhc, int micb_num)
  309. {
  310. u8 val;
  311. if (micb_num == MIC_BIAS_2) {
  312. val = (snd_soc_read(mbhc->codec, AQT_ANA_MICB2) >> 6);
  313. if (val == 0x01)
  314. return true;
  315. }
  316. return false;
  317. }
  318. static bool aqt_mbhc_hph_pa_on_status(struct snd_soc_codec *codec)
  319. {
  320. return (snd_soc_read(codec, AQT_ANA_HPH) & 0xC0) ? true : false;
  321. }
  322. static void aqt_mbhc_hph_l_pull_up_control(
  323. struct snd_soc_codec *codec,
  324. enum mbhc_hs_pullup_iref pull_up_cur)
  325. {
  326. /* Default pull up current to 2uA */
  327. if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA ||
  328. pull_up_cur == I_DEFAULT)
  329. pull_up_cur = I_2P0_UA;
  330. dev_dbg(codec->dev, "%s: HS pull up current:%d\n",
  331. __func__, pull_up_cur);
  332. snd_soc_update_bits(codec, AQT_MBHC_NEW_PLUG_DETECT_CTL,
  333. 0xC0, pull_up_cur << 6);
  334. }
  335. static int aqt_mbhc_request_micbias(struct snd_soc_codec *codec,
  336. int micb_num, int req)
  337. {
  338. int ret;
  339. /*
  340. * If micbias is requested, make sure that there
  341. * is vote to enable mclk
  342. */
  343. if (req == MICB_ENABLE)
  344. aqt_cdc_mclk_enable(codec, true);
  345. ret = aqt_micbias_control(codec, micb_num, req, false);
  346. /*
  347. * Release vote for mclk while requesting for
  348. * micbias disable
  349. */
  350. if (req == MICB_DISABLE)
  351. aqt_cdc_mclk_enable(codec, false);
  352. return ret;
  353. }
  354. static void aqt_mbhc_micb_ramp_control(struct snd_soc_codec *codec,
  355. bool enable)
  356. {
  357. if (enable) {
  358. snd_soc_update_bits(codec, AQT_ANA_MICB2_RAMP,
  359. 0x1C, 0x0C);
  360. snd_soc_update_bits(codec, AQT_ANA_MICB2_RAMP,
  361. 0x80, 0x80);
  362. } else {
  363. snd_soc_update_bits(codec, AQT_ANA_MICB2_RAMP,
  364. 0x80, 0x00);
  365. snd_soc_update_bits(codec, AQT_ANA_MICB2_RAMP,
  366. 0x1C, 0x00);
  367. }
  368. }
  369. static struct firmware_cal *aqt_get_hwdep_fw_cal(struct wcd_mbhc *mbhc,
  370. enum wcd_cal_type type)
  371. {
  372. struct aqt_mbhc *aqt_mbhc;
  373. struct firmware_cal *hwdep_cal;
  374. struct snd_soc_codec *codec = mbhc->codec;
  375. aqt_mbhc = container_of(mbhc, struct aqt_mbhc, wcd_mbhc);
  376. if (!codec) {
  377. pr_err("%s: NULL codec pointer\n", __func__);
  378. return NULL;
  379. }
  380. hwdep_cal = wcdcal_get_fw_cal(aqt_mbhc->fw_data, type);
  381. if (!hwdep_cal)
  382. dev_err(codec->dev, "%s: cal not sent by %d\n",
  383. __func__, type);
  384. return hwdep_cal;
  385. }
  386. static int aqt_mbhc_micb_ctrl_threshold_mic(struct snd_soc_codec *codec,
  387. int micb_num, bool req_en)
  388. {
  389. struct wcd9xxx_pdata *pdata = dev_get_platdata(codec->dev->parent);
  390. int rc, micb_mv;
  391. if (micb_num != MIC_BIAS_2)
  392. return -EINVAL;
  393. /*
  394. * If device tree micbias level is already above the minimum
  395. * voltage needed to detect threshold microphone, then do
  396. * not change the micbias, just return.
  397. */
  398. if (pdata->micbias.micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
  399. return 0;
  400. micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : pdata->micbias.micb2_mv;
  401. rc = aqt_mbhc_micb_adjust_voltage(codec, micb_mv, MIC_BIAS_2);
  402. return rc;
  403. }
  404. static inline void aqt_mbhc_get_result_params(struct wcd9xxx *wcd9xxx,
  405. s16 *d1_a, u16 noff,
  406. int32_t *zdet)
  407. {
  408. int i;
  409. int val, val1;
  410. s16 c1;
  411. s32 x1, d1;
  412. int32_t denom;
  413. int minCode_param[] = {
  414. 3277, 1639, 820, 410, 205, 103, 52, 26
  415. };
  416. regmap_update_bits(wcd9xxx->regmap, AQT_ANA_MBHC_ZDET, 0x20, 0x20);
  417. for (i = 0; i < AQT_ZDET_NUM_MEASUREMENTS; i++) {
  418. regmap_read(wcd9xxx->regmap, AQT_ANA_MBHC_RESULT_2, &val);
  419. if (val & 0x80)
  420. break;
  421. }
  422. val = val << 0x8;
  423. regmap_read(wcd9xxx->regmap, AQT_ANA_MBHC_RESULT_1, &val1);
  424. val |= val1;
  425. regmap_update_bits(wcd9xxx->regmap, AQT_ANA_MBHC_ZDET, 0x20, 0x00);
  426. x1 = AQT_MBHC_GET_X1(val);
  427. c1 = AQT_MBHC_GET_C1(val);
  428. /* If ramp is not complete, give additional 5ms */
  429. if ((c1 < 2) && x1)
  430. usleep_range(5000, 5050);
  431. if (!c1 || !x1) {
  432. dev_dbg(wcd9xxx->dev,
  433. "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
  434. __func__, c1, x1);
  435. goto ramp_down;
  436. }
  437. d1 = d1_a[c1];
  438. denom = (x1 * d1) - (1 << (14 - noff));
  439. if (denom > 0)
  440. *zdet = (AQT_MBHC_ZDET_CONST * 1000) / denom;
  441. else if (x1 < minCode_param[noff])
  442. *zdet = AQT_ZDET_FLOATING_IMPEDANCE;
  443. dev_dbg(wcd9xxx->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
  444. __func__, d1, c1, x1, *zdet);
  445. ramp_down:
  446. i = 0;
  447. while (x1) {
  448. regmap_bulk_read(wcd9xxx->regmap,
  449. AQT_ANA_MBHC_RESULT_1, (u8 *)&val, 2);
  450. x1 = AQT_MBHC_GET_X1(val);
  451. i++;
  452. if (i == AQT_ZDET_NUM_MEASUREMENTS)
  453. break;
  454. }
  455. }
  456. static void aqt_mbhc_zdet_ramp(struct snd_soc_codec *codec,
  457. struct aqt_mbhc_zdet_param *zdet_param,
  458. int32_t *zl, int32_t *zr, s16 *d1_a)
  459. {
  460. struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
  461. int32_t zdet = 0;
  462. snd_soc_update_bits(codec, AQT_MBHC_NEW_ZDET_ANA_CTL, 0x70,
  463. zdet_param->ldo_ctl << 4);
  464. snd_soc_update_bits(codec, AQT_ANA_MBHC_BTN5, 0xFC,
  465. zdet_param->btn5);
  466. snd_soc_update_bits(codec, AQT_ANA_MBHC_BTN6, 0xFC,
  467. zdet_param->btn6);
  468. snd_soc_update_bits(codec, AQT_ANA_MBHC_BTN7, 0xFC,
  469. zdet_param->btn7);
  470. snd_soc_update_bits(codec, AQT_MBHC_NEW_ZDET_ANA_CTL, 0x0F,
  471. zdet_param->noff);
  472. snd_soc_update_bits(codec, AQT_MBHC_NEW_ZDET_RAMP_CTL, 0x0F,
  473. zdet_param->nshift);
  474. if (!zl)
  475. goto z_right;
  476. /* Start impedance measurement for HPH_L */
  477. regmap_update_bits(wcd9xxx->regmap,
  478. AQT_ANA_MBHC_ZDET, 0x80, 0x80);
  479. dev_dbg(wcd9xxx->dev, "%s: ramp for HPH_L, noff = %d\n",
  480. __func__, zdet_param->noff);
  481. aqt_mbhc_get_result_params(wcd9xxx, d1_a, zdet_param->noff, &zdet);
  482. regmap_update_bits(wcd9xxx->regmap,
  483. AQT_ANA_MBHC_ZDET, 0x80, 0x00);
  484. *zl = zdet;
  485. z_right:
  486. if (!zr)
  487. return;
  488. /* Start impedance measurement for HPH_R */
  489. regmap_update_bits(wcd9xxx->regmap,
  490. AQT_ANA_MBHC_ZDET, 0x40, 0x40);
  491. dev_dbg(wcd9xxx->dev, "%s: ramp for HPH_R, noff = %d\n",
  492. __func__, zdet_param->noff);
  493. aqt_mbhc_get_result_params(wcd9xxx, d1_a, zdet_param->noff, &zdet);
  494. regmap_update_bits(wcd9xxx->regmap,
  495. AQT_ANA_MBHC_ZDET, 0x40, 0x00);
  496. *zr = zdet;
  497. }
  498. static inline void aqt_wcd_mbhc_qfuse_cal(struct snd_soc_codec *codec,
  499. int32_t *z_val, int flag_l_r)
  500. {
  501. s16 q1;
  502. int q1_cal;
  503. if (*z_val < (AQT_ZDET_VAL_400/1000))
  504. q1 = snd_soc_read(codec,
  505. AQT_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r));
  506. else
  507. q1 = snd_soc_read(codec,
  508. AQT_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r));
  509. if (q1 & 0x80)
  510. q1_cal = (10000 - ((q1 & 0x7F) * 25));
  511. else
  512. q1_cal = (10000 + (q1 * 25));
  513. if (q1_cal > 0)
  514. *z_val = ((*z_val) * 10000) / q1_cal;
  515. }
  516. static void aqt_wcd_mbhc_calc_impedance(struct wcd_mbhc *mbhc, uint32_t *zl,
  517. uint32_t *zr)
  518. {
  519. struct snd_soc_codec *codec = mbhc->codec;
  520. struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
  521. s16 reg0, reg1, reg2, reg3, reg4;
  522. int32_t z1L, z1R, z1Ls;
  523. int zMono, z_diff1, z_diff2;
  524. bool is_fsm_disable = false;
  525. struct aqt_mbhc_zdet_param zdet_param[] = {
  526. {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
  527. {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
  528. {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
  529. {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
  530. };
  531. struct aqt_mbhc_zdet_param *zdet_param_ptr = NULL;
  532. s16 d1_a[][4] = {
  533. {0, 30, 90, 30},
  534. {0, 30, 30, 5},
  535. {0, 30, 30, 5},
  536. {0, 30, 30, 5},
  537. };
  538. s16 *d1 = NULL;
  539. WCD_MBHC_RSC_ASSERT_LOCKED(mbhc);
  540. reg0 = snd_soc_read(codec, AQT_ANA_MBHC_BTN5);
  541. reg1 = snd_soc_read(codec, AQT_ANA_MBHC_BTN6);
  542. reg2 = snd_soc_read(codec, AQT_ANA_MBHC_BTN7);
  543. reg3 = snd_soc_read(codec, AQT_MBHC_CTL_CLK);
  544. reg4 = snd_soc_read(codec, AQT_MBHC_NEW_ZDET_ANA_CTL);
  545. if (snd_soc_read(codec, AQT_ANA_MBHC_ELECT) & 0x80) {
  546. is_fsm_disable = true;
  547. regmap_update_bits(wcd9xxx->regmap,
  548. AQT_ANA_MBHC_ELECT, 0x80, 0x00);
  549. }
  550. /* For NO-jack, disable L_DET_EN before Z-det measurements */
  551. if (mbhc->hphl_swh)
  552. regmap_update_bits(wcd9xxx->regmap,
  553. AQT_ANA_MBHC_MECH, 0x80, 0x00);
  554. /* Turn off 100k pull down on HPHL */
  555. regmap_update_bits(wcd9xxx->regmap,
  556. AQT_ANA_MBHC_MECH, 0x01, 0x00);
  557. /* First get impedance on Left */
  558. d1 = d1_a[1];
  559. zdet_param_ptr = &zdet_param[1];
  560. aqt_mbhc_zdet_ramp(codec, zdet_param_ptr, &z1L, NULL, d1);
  561. if (!AQT_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
  562. goto left_ch_impedance;
  563. /* Second ramp for left ch */
  564. if (z1L < AQT_ZDET_VAL_32) {
  565. zdet_param_ptr = &zdet_param[0];
  566. d1 = d1_a[0];
  567. } else if ((z1L > AQT_ZDET_VAL_400) && (z1L <= AQT_ZDET_VAL_1200)) {
  568. zdet_param_ptr = &zdet_param[2];
  569. d1 = d1_a[2];
  570. } else if (z1L > AQT_ZDET_VAL_1200) {
  571. zdet_param_ptr = &zdet_param[3];
  572. d1 = d1_a[3];
  573. }
  574. aqt_mbhc_zdet_ramp(codec, zdet_param_ptr, &z1L, NULL, d1);
  575. left_ch_impedance:
  576. if ((z1L == AQT_ZDET_FLOATING_IMPEDANCE) ||
  577. (z1L > AQT_ZDET_VAL_100K)) {
  578. *zl = AQT_ZDET_FLOATING_IMPEDANCE;
  579. zdet_param_ptr = &zdet_param[1];
  580. d1 = d1_a[1];
  581. } else {
  582. *zl = z1L/1000;
  583. aqt_wcd_mbhc_qfuse_cal(codec, zl, 0);
  584. }
  585. dev_dbg(codec->dev, "%s: impedance on HPH_L = %d(ohms)\n",
  586. __func__, *zl);
  587. /* Start of right impedance ramp and calculation */
  588. aqt_mbhc_zdet_ramp(codec, zdet_param_ptr, NULL, &z1R, d1);
  589. if (AQT_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
  590. if (((z1R > AQT_ZDET_VAL_1200) &&
  591. (zdet_param_ptr->noff == 0x6)) ||
  592. ((*zl) != AQT_ZDET_FLOATING_IMPEDANCE))
  593. goto right_ch_impedance;
  594. /* Second ramp for right ch */
  595. if (z1R < AQT_ZDET_VAL_32) {
  596. zdet_param_ptr = &zdet_param[0];
  597. d1 = d1_a[0];
  598. } else if ((z1R > AQT_ZDET_VAL_400) &&
  599. (z1R <= AQT_ZDET_VAL_1200)) {
  600. zdet_param_ptr = &zdet_param[2];
  601. d1 = d1_a[2];
  602. } else if (z1R > AQT_ZDET_VAL_1200) {
  603. zdet_param_ptr = &zdet_param[3];
  604. d1 = d1_a[3];
  605. }
  606. aqt_mbhc_zdet_ramp(codec, zdet_param_ptr, NULL, &z1R, d1);
  607. }
  608. right_ch_impedance:
  609. if ((z1R == AQT_ZDET_FLOATING_IMPEDANCE) ||
  610. (z1R > AQT_ZDET_VAL_100K)) {
  611. *zr = AQT_ZDET_FLOATING_IMPEDANCE;
  612. } else {
  613. *zr = z1R/1000;
  614. aqt_wcd_mbhc_qfuse_cal(codec, zr, 1);
  615. }
  616. dev_dbg(codec->dev, "%s: impedance on HPH_R = %d(ohms)\n",
  617. __func__, *zr);
  618. /* Mono/stereo detection */
  619. if ((*zl == AQT_ZDET_FLOATING_IMPEDANCE) &&
  620. (*zr == AQT_ZDET_FLOATING_IMPEDANCE)) {
  621. dev_dbg(codec->dev,
  622. "%s: plug type is invalid or extension cable\n",
  623. __func__);
  624. goto zdet_complete;
  625. }
  626. if ((*zl == AQT_ZDET_FLOATING_IMPEDANCE) ||
  627. (*zr == AQT_ZDET_FLOATING_IMPEDANCE) ||
  628. ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
  629. ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
  630. dev_dbg(codec->dev,
  631. "%s: Mono plug type with one ch floating or shorted to GND\n",
  632. __func__);
  633. mbhc->hph_type = WCD_MBHC_HPH_MONO;
  634. goto zdet_complete;
  635. }
  636. snd_soc_update_bits(codec, AQT_HPH_R_ATEST, 0x02, 0x02);
  637. snd_soc_update_bits(codec, AQT_HPH_PA_CTL2, 0x40, 0x01);
  638. if (*zl < (AQT_ZDET_VAL_32/1000))
  639. aqt_mbhc_zdet_ramp(codec, &zdet_param[0], &z1Ls, NULL, d1);
  640. else
  641. aqt_mbhc_zdet_ramp(codec, &zdet_param[1], &z1Ls, NULL, d1);
  642. snd_soc_update_bits(codec, AQT_HPH_PA_CTL2, 0x40, 0x00);
  643. snd_soc_update_bits(codec, AQT_HPH_R_ATEST, 0x02, 0x00);
  644. z1Ls /= 1000;
  645. aqt_wcd_mbhc_qfuse_cal(codec, &z1Ls, 0);
  646. /* Parallel of left Z and 9 ohm pull down resistor */
  647. zMono = ((*zl) * 9) / ((*zl) + 9);
  648. z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
  649. z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
  650. if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
  651. dev_dbg(codec->dev, "%s: stereo plug type detected\n",
  652. __func__);
  653. mbhc->hph_type = WCD_MBHC_HPH_STEREO;
  654. } else {
  655. dev_dbg(codec->dev, "%s: MONO plug type detected\n",
  656. __func__);
  657. mbhc->hph_type = WCD_MBHC_HPH_MONO;
  658. }
  659. zdet_complete:
  660. snd_soc_write(codec, AQT_ANA_MBHC_BTN5, reg0);
  661. snd_soc_write(codec, AQT_ANA_MBHC_BTN6, reg1);
  662. snd_soc_write(codec, AQT_ANA_MBHC_BTN7, reg2);
  663. /* Turn on 100k pull down on HPHL */
  664. regmap_update_bits(wcd9xxx->regmap,
  665. AQT_ANA_MBHC_MECH, 0x01, 0x01);
  666. /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
  667. if (mbhc->hphl_swh)
  668. regmap_update_bits(wcd9xxx->regmap,
  669. AQT_ANA_MBHC_MECH, 0x80, 0x80);
  670. snd_soc_write(codec, AQT_MBHC_NEW_ZDET_ANA_CTL, reg4);
  671. snd_soc_write(codec, AQT_MBHC_CTL_CLK, reg3);
  672. if (is_fsm_disable)
  673. regmap_update_bits(wcd9xxx->regmap,
  674. AQT_ANA_MBHC_ELECT, 0x80, 0x80);
  675. }
  676. static void aqt_mbhc_gnd_det_ctrl(struct snd_soc_codec *codec, bool enable)
  677. {
  678. if (enable) {
  679. snd_soc_update_bits(codec, AQT_ANA_MBHC_MECH,
  680. 0x02, 0x02);
  681. snd_soc_update_bits(codec, AQT_ANA_MBHC_MECH,
  682. 0x40, 0x40);
  683. } else {
  684. snd_soc_update_bits(codec, AQT_ANA_MBHC_MECH,
  685. 0x40, 0x00);
  686. snd_soc_update_bits(codec, AQT_ANA_MBHC_MECH,
  687. 0x02, 0x00);
  688. }
  689. }
  690. static void aqt_mbhc_hph_pull_down_ctrl(struct snd_soc_codec *codec,
  691. bool enable)
  692. {
  693. if (enable) {
  694. snd_soc_update_bits(codec, AQT_HPH_PA_CTL2,
  695. 0x40, 0x40);
  696. snd_soc_update_bits(codec, AQT_HPH_PA_CTL2,
  697. 0x10, 0x10);
  698. } else {
  699. snd_soc_update_bits(codec, AQT_HPH_PA_CTL2,
  700. 0x40, 0x00);
  701. snd_soc_update_bits(codec, AQT_HPH_PA_CTL2,
  702. 0x10, 0x00);
  703. }
  704. }
  705. static void aqt_mbhc_moisture_config(struct wcd_mbhc *mbhc)
  706. {
  707. struct snd_soc_codec *codec = mbhc->codec;
  708. if ((mbhc->moist_rref == R_OFF) ||
  709. (mbhc->mbhc_cfg->enable_usbc_analog)) {
  710. snd_soc_update_bits(codec, AQT_MBHC_NEW_CTL_2,
  711. 0x0C, R_OFF << 2);
  712. return;
  713. }
  714. /* Donot enable moisture detection if jack type is NC */
  715. if (!mbhc->hphl_swh) {
  716. dev_dbg(codec->dev, "%s: disable moisture detection for NC\n",
  717. __func__);
  718. snd_soc_update_bits(codec, AQT_MBHC_NEW_CTL_2,
  719. 0x0C, R_OFF << 2);
  720. return;
  721. }
  722. snd_soc_update_bits(codec, AQT_MBHC_NEW_CTL_2,
  723. 0x0C, mbhc->moist_rref << 2);
  724. }
  725. static bool aqt_hph_register_recovery(struct wcd_mbhc *mbhc)
  726. {
  727. struct snd_soc_codec *codec = mbhc->codec;
  728. struct aqt_mbhc *aqt_mbhc = aqt_soc_get_mbhc(codec);
  729. if (!aqt_mbhc)
  730. return false;
  731. aqt_mbhc->is_hph_recover = false;
  732. snd_soc_dapm_force_enable_pin(snd_soc_codec_get_dapm(codec),
  733. "RESET_HPH_REGISTERS");
  734. snd_soc_dapm_sync(snd_soc_codec_get_dapm(codec));
  735. snd_soc_dapm_disable_pin(snd_soc_codec_get_dapm(codec),
  736. "RESET_HPH_REGISTERS");
  737. snd_soc_dapm_sync(snd_soc_codec_get_dapm(codec));
  738. return aqt_mbhc->is_hph_recover;
  739. }
  740. static void aqt_update_anc_state(struct snd_soc_codec *codec, bool enable,
  741. int anc_num)
  742. {
  743. if (enable)
  744. snd_soc_update_bits(codec, AQT_CDC_RX1_RX_PATH_CFG0 +
  745. (20 * anc_num), 0x10, 0x10);
  746. else
  747. snd_soc_update_bits(codec, AQT_CDC_RX1_RX_PATH_CFG0 +
  748. (20 * anc_num), 0x10, 0x00);
  749. }
  750. static bool aqt_is_anc_on(struct wcd_mbhc *mbhc)
  751. {
  752. bool anc_on = false;
  753. u16 ancl, ancr;
  754. ancl =
  755. (snd_soc_read(mbhc->codec, AQT_CDC_RX1_RX_PATH_CFG0)) & 0x10;
  756. ancr =
  757. (snd_soc_read(mbhc->codec, AQT_CDC_RX2_RX_PATH_CFG0)) & 0x10;
  758. anc_on = !!(ancl | ancr);
  759. return anc_on;
  760. }
  761. static const struct wcd_mbhc_cb mbhc_cb = {
  762. .request_irq = aqt_mbhc_request_irq,
  763. .irq_control = aqt_mbhc_irq_control,
  764. .free_irq = aqt_mbhc_free_irq,
  765. .clk_setup = aqt_mbhc_clk_setup,
  766. .map_btn_code_to_num = aqt_mbhc_btn_to_num,
  767. .enable_mb_source = aqt_enable_ext_mb_source,
  768. .mbhc_bias = aqt_mbhc_mbhc_bias_control,
  769. .set_btn_thr = aqt_mbhc_program_btn_thr,
  770. .lock_sleep = aqt_mbhc_lock_sleep,
  771. .register_notifier = aqt_mbhc_register_notifier,
  772. .micbias_enable_status = aqt_mbhc_micb_en_status,
  773. .hph_pa_on_status = aqt_mbhc_hph_pa_on_status,
  774. .hph_pull_up_control = aqt_mbhc_hph_l_pull_up_control,
  775. .mbhc_micbias_control = aqt_mbhc_request_micbias,
  776. .mbhc_micb_ramp_control = aqt_mbhc_micb_ramp_control,
  777. .get_hwdep_fw_cal = aqt_get_hwdep_fw_cal,
  778. .mbhc_micb_ctrl_thr_mic = aqt_mbhc_micb_ctrl_threshold_mic,
  779. .compute_impedance = aqt_wcd_mbhc_calc_impedance,
  780. .mbhc_gnd_det_ctrl = aqt_mbhc_gnd_det_ctrl,
  781. .hph_pull_down_ctrl = aqt_mbhc_hph_pull_down_ctrl,
  782. .mbhc_moisture_config = aqt_mbhc_moisture_config,
  783. .hph_register_recovery = aqt_hph_register_recovery,
  784. .update_anc_state = aqt_update_anc_state,
  785. .is_anc_on = aqt_is_anc_on,
  786. };
  787. static struct regulator *aqt_codec_find_ondemand_regulator(
  788. struct snd_soc_codec *codec, const char *name)
  789. {
  790. int i;
  791. struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
  792. struct wcd9xxx_pdata *pdata = dev_get_platdata(codec->dev->parent);
  793. for (i = 0; i < wcd9xxx->num_of_supplies; ++i) {
  794. if (pdata->regulator[i].ondemand &&
  795. wcd9xxx->supplies[i].supply &&
  796. !strcmp(wcd9xxx->supplies[i].supply, name))
  797. return wcd9xxx->supplies[i].consumer;
  798. }
  799. dev_dbg(codec->dev, "Warning: regulator not found:%s\n",
  800. name);
  801. return NULL;
  802. }
  803. static int aqt_get_hph_type(struct snd_kcontrol *kcontrol,
  804. struct snd_ctl_elem_value *ucontrol)
  805. {
  806. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  807. struct aqt_mbhc *aqt_mbhc = aqt_soc_get_mbhc(codec);
  808. struct wcd_mbhc *mbhc;
  809. if (!aqt_mbhc) {
  810. dev_err(codec->dev, "%s: mbhc not initialized!\n", __func__);
  811. return -EINVAL;
  812. }
  813. mbhc = &aqt_mbhc->wcd_mbhc;
  814. ucontrol->value.integer.value[0] = (u32) mbhc->hph_type;
  815. dev_dbg(codec->dev, "%s: hph_type = %u\n", __func__, mbhc->hph_type);
  816. return 0;
  817. }
  818. static int aqt_hph_impedance_get(struct snd_kcontrol *kcontrol,
  819. struct snd_ctl_elem_value *ucontrol)
  820. {
  821. uint32_t zl, zr;
  822. bool hphr;
  823. struct soc_multi_mixer_control *mc;
  824. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  825. struct aqt_mbhc *aqt_mbhc = aqt_soc_get_mbhc(codec);
  826. if (!aqt_mbhc) {
  827. dev_err(codec->dev, "%s: mbhc not initialized!\n", __func__);
  828. return -EINVAL;
  829. }
  830. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  831. hphr = mc->shift;
  832. wcd_mbhc_get_impedance(&aqt_mbhc->wcd_mbhc, &zl, &zr);
  833. dev_dbg(codec->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
  834. ucontrol->value.integer.value[0] = hphr ? zr : zl;
  835. return 0;
  836. }
  837. static const struct snd_kcontrol_new hph_type_detect_controls[] = {
  838. SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0,
  839. aqt_get_hph_type, NULL),
  840. };
  841. static const struct snd_kcontrol_new impedance_detect_controls[] = {
  842. SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
  843. aqt_hph_impedance_get, NULL),
  844. SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
  845. aqt_hph_impedance_get, NULL),
  846. };
  847. /*
  848. * aqt_mbhc_get_impedance: get impedance of headphone left and right channels
  849. * @aqt_mbhc: handle to struct aqt_mbhc *
  850. * @zl: handle to left-ch impedance
  851. * @zr: handle to right-ch impedance
  852. * return 0 for success or error code in case of failure
  853. */
  854. int aqt_mbhc_get_impedance(struct aqt_mbhc *aqt_mbhc,
  855. uint32_t *zl, uint32_t *zr)
  856. {
  857. if (!aqt_mbhc) {
  858. pr_err("%s: mbhc not initialized!\n", __func__);
  859. return -EINVAL;
  860. }
  861. if (!zl || !zr) {
  862. pr_err("%s: zl or zr null!\n", __func__);
  863. return -EINVAL;
  864. }
  865. return wcd_mbhc_get_impedance(&aqt_mbhc->wcd_mbhc, zl, zr);
  866. }
  867. EXPORT_SYMBOL(aqt_mbhc_get_impedance);
  868. /*
  869. * aqt_mbhc_hs_detect: starts mbhc insertion/removal functionality
  870. * @codec: handle to snd_soc_codec *
  871. * @mbhc_cfg: handle to mbhc configuration structure
  872. * return 0 if mbhc_start is success or error code in case of failure
  873. */
  874. int aqt_mbhc_hs_detect(struct snd_soc_codec *codec,
  875. struct wcd_mbhc_config *mbhc_cfg)
  876. {
  877. struct aqt_mbhc *aqt_mbhc = aqt_soc_get_mbhc(codec);
  878. if (!aqt_mbhc) {
  879. dev_err(codec->dev, "%s: mbhc not initialized!\n", __func__);
  880. return -EINVAL;
  881. }
  882. return wcd_mbhc_start(&aqt_mbhc->wcd_mbhc, mbhc_cfg);
  883. }
  884. EXPORT_SYMBOL(aqt_mbhc_hs_detect);
  885. /*
  886. * aqt_mbhc_hs_detect_exit: stop mbhc insertion/removal functionality
  887. * @codec: handle to snd_soc_codec *
  888. */
  889. void aqt_mbhc_hs_detect_exit(struct snd_soc_codec *codec)
  890. {
  891. struct aqt_mbhc *aqt_mbhc = aqt_soc_get_mbhc(codec);
  892. if (!aqt_mbhc) {
  893. dev_err(codec->dev, "%s: mbhc not initialized!\n", __func__);
  894. return;
  895. }
  896. wcd_mbhc_stop(&aqt_mbhc->wcd_mbhc);
  897. }
  898. EXPORT_SYMBOL(aqt_mbhc_hs_detect_exit);
  899. /*
  900. * aqt_mbhc_post_ssr_init: initialize mbhc for aqt post subsystem restart
  901. * @mbhc: poniter to aqt_mbhc structure
  902. * @codec: handle to snd_soc_codec *
  903. *
  904. * return 0 if mbhc_init is success or error code in case of failure
  905. */
  906. int aqt_mbhc_post_ssr_init(struct aqt_mbhc *mbhc,
  907. struct snd_soc_codec *codec)
  908. {
  909. int ret;
  910. struct wcd_mbhc *wcd_mbhc;
  911. if (!mbhc || !codec)
  912. return -EINVAL;
  913. wcd_mbhc = &mbhc->wcd_mbhc;
  914. if (wcd_mbhc == NULL) {
  915. pr_err("%s: wcd_mbhc is NULL\n", __func__);
  916. return -EINVAL;
  917. }
  918. wcd_mbhc_deinit(wcd_mbhc);
  919. ret = wcd_mbhc_init(wcd_mbhc, codec, &mbhc_cb, &intr_ids,
  920. wcd_mbhc_registers, AQT_ZDET_SUPPORTED);
  921. if (ret) {
  922. dev_err(codec->dev, "%s: mbhc initialization failed\n",
  923. __func__);
  924. goto done;
  925. }
  926. done:
  927. return ret;
  928. }
  929. EXPORT_SYMBOL(aqt_mbhc_post_ssr_init);
  930. /*
  931. * aqt_mbhc_init: initialize mbhc for aqt
  932. * @mbhc: poniter to aqt_mbhc struct pointer to store the configs
  933. * @codec: handle to snd_soc_codec *
  934. * @fw_data: handle to firmware data
  935. *
  936. * return 0 if mbhc_init is success or error code in case of failure
  937. */
  938. int aqt_mbhc_init(struct aqt_mbhc **mbhc, struct snd_soc_codec *codec,
  939. struct fw_info *fw_data)
  940. {
  941. struct regulator *supply;
  942. struct aqt_mbhc *aqt_mbhc;
  943. struct wcd_mbhc *wcd_mbhc;
  944. int ret;
  945. aqt_mbhc = devm_kzalloc(codec->dev, sizeof(struct aqt_mbhc),
  946. GFP_KERNEL);
  947. if (!aqt_mbhc)
  948. return -ENOMEM;
  949. aqt_mbhc->wcd9xxx = dev_get_drvdata(codec->dev->parent);
  950. aqt_mbhc->fw_data = fw_data;
  951. BLOCKING_INIT_NOTIFIER_HEAD(&aqt_mbhc->notifier);
  952. wcd_mbhc = &aqt_mbhc->wcd_mbhc;
  953. if (wcd_mbhc == NULL) {
  954. pr_err("%s: wcd_mbhc is NULL\n", __func__);
  955. ret = -EINVAL;
  956. goto err;
  957. }
  958. /* Setting default mbhc detection logic to ADC */
  959. wcd_mbhc->mbhc_detection_logic = WCD_DETECTION_ADC;
  960. ret = wcd_mbhc_init(wcd_mbhc, codec, &mbhc_cb,
  961. &intr_ids, wcd_mbhc_registers,
  962. AQT_ZDET_SUPPORTED);
  963. if (ret) {
  964. dev_err(codec->dev, "%s: mbhc initialization failed\n",
  965. __func__);
  966. goto err;
  967. }
  968. supply = aqt_codec_find_ondemand_regulator(codec,
  969. on_demand_supply_name[AQT_ON_DEMAND_MICBIAS]);
  970. if (supply) {
  971. aqt_mbhc->on_demand_list[
  972. AQT_ON_DEMAND_MICBIAS].supply =
  973. supply;
  974. aqt_mbhc->on_demand_list[
  975. AQT_ON_DEMAND_MICBIAS].ondemand_supply_count =
  976. 0;
  977. }
  978. (*mbhc) = aqt_mbhc;
  979. snd_soc_add_codec_controls(codec, impedance_detect_controls,
  980. ARRAY_SIZE(impedance_detect_controls));
  981. snd_soc_add_codec_controls(codec, hph_type_detect_controls,
  982. ARRAY_SIZE(hph_type_detect_controls));
  983. return 0;
  984. err:
  985. devm_kfree(codec->dev, aqt_mbhc);
  986. return ret;
  987. }
  988. EXPORT_SYMBOL(aqt_mbhc_init);
  989. /*
  990. * aqt_mbhc_deinit: deinitialize mbhc for aqt
  991. * @codec: handle to snd_soc_codec *
  992. */
  993. void aqt_mbhc_deinit(struct snd_soc_codec *codec)
  994. {
  995. struct aqt_mbhc *aqt_mbhc = aqt_soc_get_mbhc(codec);
  996. if (aqt_mbhc) {
  997. wcd_mbhc_deinit(&aqt_mbhc->wcd_mbhc);
  998. devm_kfree(codec->dev, aqt_mbhc);
  999. }
  1000. }
  1001. EXPORT_SYMBOL(aqt_mbhc_deinit);