wcd938x.c 110 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #define WCD938X_DRV_NAME "wcd938x_codec"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD938X_VARIANT_ENTRY_SIZE 32
  28. #define WCD938X_VERSION_1_0 1
  29. #define WCD938X_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_AUX 1
  31. #define ADC_MODE_VAL_HIFI 0x01
  32. #define ADC_MODE_VAL_LO_HIF 0x02
  33. #define ADC_MODE_VAL_NORMAL 0x03
  34. #define ADC_MODE_VAL_LP 0x05
  35. #define ADC_MODE_VAL_ULP1 0x09
  36. #define ADC_MODE_VAL_ULP2 0x0B
  37. #define NUM_ATTEMPTS 5
  38. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  39. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  40. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  41. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  42. enum {
  43. CODEC_TX = 0,
  44. CODEC_RX,
  45. };
  46. enum {
  47. WCD_ADC1 = 0,
  48. WCD_ADC2,
  49. WCD_ADC3,
  50. WCD_ADC4,
  51. ALLOW_BUCK_DISABLE,
  52. HPH_COMP_DELAY,
  53. HPH_PA_DELAY,
  54. AMIC2_BCS_ENABLE,
  55. };
  56. enum {
  57. ADC_MODE_INVALID = 0,
  58. ADC_MODE_HIFI,
  59. ADC_MODE_LO_HIF,
  60. ADC_MODE_NORMAL,
  61. ADC_MODE_LP,
  62. ADC_MODE_ULP1,
  63. ADC_MODE_ULP2,
  64. };
  65. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  66. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  67. static int wcd938x_handle_post_irq(void *data);
  68. static int wcd938x_reset(struct device *dev);
  69. static int wcd938x_reset_low(struct device *dev);
  70. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  71. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  86. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  87. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  88. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  89. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  90. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  91. };
  92. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  93. .name = "wcd938x",
  94. .irqs = wcd938x_irqs,
  95. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  96. .num_regs = 3,
  97. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  98. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  99. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  100. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  101. .use_ack = 1,
  102. .runtime_pm = false,
  103. .handle_post_irq = wcd938x_handle_post_irq,
  104. .irq_drv_data = NULL,
  105. };
  106. static int wcd938x_handle_post_irq(void *data)
  107. {
  108. struct wcd938x_priv *wcd938x = data;
  109. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  110. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  111. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  112. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  113. wcd938x->tx_swr_dev->slave_irq_pending =
  114. ((sts1 || sts2 || sts3) ? true : false);
  115. return IRQ_HANDLED;
  116. }
  117. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  118. {
  119. int ret = 0;
  120. int bank = 0;
  121. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  122. if (ret)
  123. return -EINVAL;
  124. return ((bank & 0x40) ? 1: 0);
  125. }
  126. static int wcd938x_swr_slv_set_host_clk_div2(struct swr_device *dev,
  127. u8 devnum, int bank)
  128. {
  129. u8 val = (bank ? 1 : 0);
  130. return (swr_write(dev, devnum,
  131. (SWR_SCP_HOST_CLK_DIV2_CTL_BANK + (0x10 * bank)), &val));
  132. }
  133. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  134. int mode, int bank)
  135. {
  136. u8 mask = (bank ? 0xF0 : 0x0F);
  137. u8 val = 0;
  138. if ((mode == ADC_MODE_ULP1) || (mode == ADC_MODE_ULP2))
  139. val = (bank ? 0x60 : 0x06);
  140. else
  141. val = 0x00;
  142. snd_soc_component_update_bits(component,
  143. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  144. mask, val);
  145. return 0;
  146. }
  147. static int wcd938x_init_reg(struct snd_soc_component *component)
  148. {
  149. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  150. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  151. /* 1 msec delay as per HW requirement */
  152. usleep_range(1000, 1010);
  153. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  154. /* 1 msec delay as per HW requirement */
  155. usleep_range(1000, 1010);
  156. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  157. 0x10, 0x00);
  158. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  159. 0xF0, 0x80);
  160. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  161. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  162. /* 10 msec delay as per HW requirement */
  163. usleep_range(10000, 10010);
  164. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  165. snd_soc_component_update_bits(component,
  166. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  167. 0xF0, 0x00);
  168. snd_soc_component_update_bits(component,
  169. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  170. 0x1F, 0x15);
  171. snd_soc_component_update_bits(component,
  172. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  173. 0x1F, 0x15);
  174. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  175. 0xC0, 0x80);
  176. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  177. 0x02, 0x02);
  178. snd_soc_component_update_bits(component,
  179. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  180. 0xFF, 0x14);
  181. snd_soc_component_update_bits(component,
  182. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  183. 0x1F, 0x08);
  184. snd_soc_component_update_bits(component,
  185. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  186. snd_soc_component_update_bits(component,
  187. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  188. snd_soc_component_update_bits(component,
  189. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  190. snd_soc_component_update_bits(component,
  191. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  192. snd_soc_component_update_bits(component,
  193. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  194. snd_soc_component_update_bits(component,
  195. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  196. snd_soc_component_update_bits(component,
  197. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  198. snd_soc_component_update_bits(component,
  199. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  200. snd_soc_component_update_bits(component,
  201. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  202. snd_soc_component_update_bits(component,
  203. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  204. return 0;
  205. }
  206. static int wcd938x_set_port_params(struct snd_soc_component *component,
  207. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  208. u8 *ch_mask, u32 *ch_rate,
  209. u8 *port_type, u8 path)
  210. {
  211. int i, j;
  212. u8 num_ports = 0;
  213. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  214. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  215. switch (path) {
  216. case CODEC_RX:
  217. map = &wcd938x->rx_port_mapping;
  218. num_ports = wcd938x->num_rx_ports;
  219. break;
  220. case CODEC_TX:
  221. map = &wcd938x->tx_port_mapping;
  222. num_ports = wcd938x->num_tx_ports;
  223. break;
  224. default:
  225. dev_err(component->dev, "%s Invalid path selected %u\n",
  226. __func__, path);
  227. return -EINVAL;
  228. }
  229. for (i = 0; i <= num_ports; i++) {
  230. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  231. if ((*map)[i][j].slave_port_type == slv_prt_type)
  232. goto found;
  233. }
  234. }
  235. found:
  236. if (i > num_ports || j == MAX_CH_PER_PORT) {
  237. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  238. __func__, slv_prt_type);
  239. return -EINVAL;
  240. }
  241. *port_id = i;
  242. *num_ch = (*map)[i][j].num_ch;
  243. *ch_mask = (*map)[i][j].ch_mask;
  244. *ch_rate = (*map)[i][j].ch_rate;
  245. *port_type = (*map)[i][j].master_port_type;
  246. return 0;
  247. }
  248. static int wcd938x_parse_port_mapping(struct device *dev,
  249. char *prop, u8 path)
  250. {
  251. u32 *dt_array, map_size, map_length;
  252. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  253. u32 slave_port_type, master_port_type;
  254. u32 i, ch_iter = 0;
  255. int ret = 0;
  256. u8 *num_ports = NULL;
  257. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  258. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  259. switch (path) {
  260. case CODEC_RX:
  261. map = &wcd938x->rx_port_mapping;
  262. num_ports = &wcd938x->num_rx_ports;
  263. break;
  264. case CODEC_TX:
  265. map = &wcd938x->tx_port_mapping;
  266. num_ports = &wcd938x->num_tx_ports;
  267. break;
  268. default:
  269. dev_err(dev, "%s Invalid path selected %u\n",
  270. __func__, path);
  271. return -EINVAL;
  272. }
  273. if (!of_find_property(dev->of_node, prop,
  274. &map_size)) {
  275. dev_err(dev, "missing port mapping prop %s\n", prop);
  276. ret = -EINVAL;
  277. goto err_port_map;
  278. }
  279. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  280. dt_array = kzalloc(map_size, GFP_KERNEL);
  281. if (!dt_array) {
  282. ret = -ENOMEM;
  283. goto err_alloc;
  284. }
  285. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  286. NUM_SWRS_DT_PARAMS * map_length);
  287. if (ret) {
  288. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  289. __func__, prop);
  290. goto err_pdata_fail;
  291. }
  292. for (i = 0; i < map_length; i++) {
  293. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  294. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  295. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  296. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  297. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  298. if (port_num != old_port_num)
  299. ch_iter = 0;
  300. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  301. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  302. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  303. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  304. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  305. old_port_num = port_num;
  306. }
  307. *num_ports = port_num;
  308. kfree(dt_array);
  309. return 0;
  310. err_pdata_fail:
  311. kfree(dt_array);
  312. err_alloc:
  313. err_port_map:
  314. return ret;
  315. }
  316. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  317. u8 slv_port_type, u8 enable)
  318. {
  319. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  320. u8 port_id, num_ch, ch_mask, ch_type;
  321. u32 ch_rate;
  322. int slave_ch_idx;
  323. u8 num_port = 1;
  324. int ret = 0;
  325. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  326. &num_ch, &ch_mask, &ch_rate,
  327. &ch_type, CODEC_TX);
  328. if (ret)
  329. return ret;
  330. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  331. if (slave_ch_idx != -EINVAL)
  332. ch_type = wcd938x_slave_get_master_ch_val(slave_ch_idx);
  333. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  334. __func__, slave_ch_idx, ch_type);
  335. if (enable)
  336. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  337. num_port, &ch_mask, &ch_rate,
  338. &num_ch, &ch_type);
  339. else
  340. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  341. num_port, &ch_mask, &ch_type);
  342. return ret;
  343. }
  344. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  345. u8 slv_port_type, u8 enable)
  346. {
  347. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  348. u8 port_id, num_ch, ch_mask, port_type;
  349. u32 ch_rate;
  350. u8 num_port = 1;
  351. int ret = 0;
  352. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  353. &num_ch, &ch_mask, &ch_rate,
  354. &port_type, CODEC_RX);
  355. if (ret)
  356. return ret;
  357. if (enable)
  358. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  359. num_port, &ch_mask, &ch_rate,
  360. &num_ch, &port_type);
  361. else
  362. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  363. num_port, &ch_mask, &port_type);
  364. return ret;
  365. }
  366. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  367. {
  368. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  369. if (wcd938x->rx_clk_cnt == 0) {
  370. snd_soc_component_update_bits(component,
  371. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  372. snd_soc_component_update_bits(component,
  373. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  374. snd_soc_component_update_bits(component,
  375. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  376. snd_soc_component_update_bits(component,
  377. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  378. snd_soc_component_update_bits(component,
  379. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  380. snd_soc_component_update_bits(component,
  381. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  382. snd_soc_component_update_bits(component,
  383. WCD938X_AUX_AUXPA, 0x10, 0x10);
  384. }
  385. wcd938x->rx_clk_cnt++;
  386. return 0;
  387. }
  388. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  389. {
  390. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  391. wcd938x->rx_clk_cnt--;
  392. if (wcd938x->rx_clk_cnt == 0) {
  393. snd_soc_component_update_bits(component,
  394. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  395. snd_soc_component_update_bits(component,
  396. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  397. snd_soc_component_update_bits(component,
  398. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  399. snd_soc_component_update_bits(component,
  400. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  401. snd_soc_component_update_bits(component,
  402. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  403. }
  404. return 0;
  405. }
  406. /*
  407. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  408. * @component: handle to snd_soc_component *
  409. *
  410. * return wcd938x_mbhc handle or error code in case of failure
  411. */
  412. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  413. {
  414. struct wcd938x_priv *wcd938x;
  415. if (!component) {
  416. pr_err("%s: Invalid params, NULL component\n", __func__);
  417. return NULL;
  418. }
  419. wcd938x = snd_soc_component_get_drvdata(component);
  420. if (!wcd938x) {
  421. pr_err("%s: wcd938x is NULL\n", __func__);
  422. return NULL;
  423. }
  424. return wcd938x->mbhc;
  425. }
  426. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  427. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  428. struct snd_kcontrol *kcontrol,
  429. int event)
  430. {
  431. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  432. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  433. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  434. w->name, event);
  435. switch (event) {
  436. case SND_SOC_DAPM_PRE_PMU:
  437. wcd938x_rx_clk_enable(component);
  438. snd_soc_component_update_bits(component,
  439. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  440. snd_soc_component_update_bits(component,
  441. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  442. snd_soc_component_update_bits(component,
  443. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  444. break;
  445. case SND_SOC_DAPM_POST_PMU:
  446. snd_soc_component_update_bits(component,
  447. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  448. if (wcd938x->comp1_enable) {
  449. snd_soc_component_update_bits(component,
  450. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  451. /* 5msec compander delay as per HW requirement */
  452. if (!wcd938x->comp2_enable ||
  453. (snd_soc_component_read32(component,
  454. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  455. usleep_range(5000, 5010);
  456. snd_soc_component_update_bits(component,
  457. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  458. } else {
  459. snd_soc_component_update_bits(component,
  460. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  461. 0x02, 0x00);
  462. snd_soc_component_update_bits(component,
  463. WCD938X_HPH_L_EN, 0x20, 0x20);
  464. }
  465. break;
  466. case SND_SOC_DAPM_POST_PMD:
  467. snd_soc_component_update_bits(component,
  468. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  469. 0x0F, 0x01);
  470. break;
  471. }
  472. return 0;
  473. }
  474. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  475. struct snd_kcontrol *kcontrol,
  476. int event)
  477. {
  478. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  479. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  480. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  481. w->name, event);
  482. switch (event) {
  483. case SND_SOC_DAPM_PRE_PMU:
  484. wcd938x_rx_clk_enable(component);
  485. snd_soc_component_update_bits(component,
  486. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  487. snd_soc_component_update_bits(component,
  488. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  489. snd_soc_component_update_bits(component,
  490. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  491. break;
  492. case SND_SOC_DAPM_POST_PMU:
  493. snd_soc_component_update_bits(component,
  494. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  495. if (wcd938x->comp2_enable) {
  496. snd_soc_component_update_bits(component,
  497. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  498. /* 5msec compander delay as per HW requirement */
  499. if (!wcd938x->comp1_enable ||
  500. (snd_soc_component_read32(component,
  501. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  502. usleep_range(5000, 5010);
  503. snd_soc_component_update_bits(component,
  504. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  505. } else {
  506. snd_soc_component_update_bits(component,
  507. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  508. 0x01, 0x00);
  509. snd_soc_component_update_bits(component,
  510. WCD938X_HPH_R_EN, 0x20, 0x20);
  511. }
  512. break;
  513. case SND_SOC_DAPM_POST_PMD:
  514. snd_soc_component_update_bits(component,
  515. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  516. 0x0F, 0x01);
  517. break;
  518. }
  519. return 0;
  520. }
  521. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  522. struct snd_kcontrol *kcontrol,
  523. int event)
  524. {
  525. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  526. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  527. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  528. w->name, event);
  529. switch (event) {
  530. case SND_SOC_DAPM_PRE_PMU:
  531. wcd938x_rx_clk_enable(component);
  532. wcd938x->ear_rx_path =
  533. snd_soc_component_read32(
  534. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  535. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  536. snd_soc_component_update_bits(component,
  537. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  538. snd_soc_component_update_bits(component,
  539. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  540. snd_soc_component_update_bits(component,
  541. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  542. snd_soc_component_update_bits(component,
  543. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  544. } else {
  545. snd_soc_component_update_bits(component,
  546. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  547. snd_soc_component_update_bits(component,
  548. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  549. snd_soc_component_update_bits(component,
  550. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  551. }
  552. /* 5 msec delay as per HW requirement */
  553. usleep_range(5000, 5010);
  554. if (wcd938x->flyback_cur_det_disable == 0)
  555. snd_soc_component_update_bits(component,
  556. WCD938X_FLYBACK_EN,
  557. 0x04, 0x00);
  558. wcd938x->flyback_cur_det_disable++;
  559. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  560. WCD_CLSH_EVENT_PRE_DAC,
  561. WCD_CLSH_STATE_EAR,
  562. wcd938x->hph_mode);
  563. break;
  564. case SND_SOC_DAPM_POST_PMD:
  565. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  566. snd_soc_component_update_bits(component,
  567. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  568. }
  569. snd_soc_component_update_bits(component,
  570. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  571. snd_soc_component_update_bits(component,
  572. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  573. break;
  574. };
  575. return 0;
  576. }
  577. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  578. struct snd_kcontrol *kcontrol,
  579. int event)
  580. {
  581. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  582. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  583. int ret = 0;
  584. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  585. w->name, event);
  586. switch (event) {
  587. case SND_SOC_DAPM_PRE_PMU:
  588. wcd938x_rx_clk_enable(component);
  589. snd_soc_component_update_bits(component,
  590. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  591. snd_soc_component_update_bits(component,
  592. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  593. snd_soc_component_update_bits(component,
  594. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  595. if (wcd938x->flyback_cur_det_disable == 0)
  596. snd_soc_component_update_bits(component,
  597. WCD938X_FLYBACK_EN,
  598. 0x04, 0x00);
  599. wcd938x->flyback_cur_det_disable++;
  600. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  601. WCD_CLSH_EVENT_PRE_DAC,
  602. WCD_CLSH_STATE_AUX,
  603. wcd938x->hph_mode);
  604. break;
  605. case SND_SOC_DAPM_POST_PMD:
  606. snd_soc_component_update_bits(component,
  607. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  608. break;
  609. };
  610. return ret;
  611. }
  612. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  613. struct snd_kcontrol *kcontrol,
  614. int event)
  615. {
  616. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  617. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  618. int ret = 0;
  619. int hph_mode = wcd938x->hph_mode;
  620. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  621. w->name, event);
  622. switch (event) {
  623. case SND_SOC_DAPM_PRE_PMU:
  624. if (wcd938x->ldoh)
  625. snd_soc_component_update_bits(component,
  626. WCD938X_LDOH_MODE,
  627. 0x80, 0x80);
  628. if (wcd938x->update_wcd_event)
  629. wcd938x->update_wcd_event(wcd938x->handle,
  630. WCD_BOLERO_EVT_RX_MUTE,
  631. (WCD_RX2 << 0x10 | 0x1));
  632. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  633. wcd938x->rx_swr_dev->dev_num,
  634. true);
  635. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  636. WCD_CLSH_EVENT_PRE_DAC,
  637. WCD_CLSH_STATE_HPHR,
  638. hph_mode);
  639. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  640. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  641. 0x10, 0x10);
  642. wcd_clsh_set_hph_mode(component, hph_mode);
  643. /* 100 usec delay as per HW requirement */
  644. usleep_range(100, 110);
  645. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  646. snd_soc_component_update_bits(component,
  647. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  648. break;
  649. case SND_SOC_DAPM_POST_PMU:
  650. /*
  651. * 7ms sleep is required if compander is enabled as per
  652. * HW requirement. If compander is disabled, then
  653. * 20ms delay is required.
  654. */
  655. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  656. if (!wcd938x->comp2_enable)
  657. usleep_range(20000, 20100);
  658. else
  659. usleep_range(7000, 7100);
  660. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  661. }
  662. snd_soc_component_update_bits(component,
  663. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  664. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  665. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  666. snd_soc_component_update_bits(component,
  667. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  668. if (wcd938x->update_wcd_event)
  669. wcd938x->update_wcd_event(wcd938x->handle,
  670. WCD_BOLERO_EVT_RX_MUTE,
  671. (WCD_RX2 << 0x10));
  672. wcd_enable_irq(&wcd938x->irq_info,
  673. WCD938X_IRQ_HPHR_PDM_WD_INT);
  674. break;
  675. case SND_SOC_DAPM_PRE_PMD:
  676. if (wcd938x->update_wcd_event)
  677. wcd938x->update_wcd_event(wcd938x->handle,
  678. WCD_BOLERO_EVT_RX_MUTE,
  679. (WCD_RX2 << 0x10 | 0x1));
  680. wcd_disable_irq(&wcd938x->irq_info,
  681. WCD938X_IRQ_HPHR_PDM_WD_INT);
  682. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  683. wcd938x->update_wcd_event(wcd938x->handle,
  684. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  685. (WCD_RX2 << 0x10));
  686. /*
  687. * 7ms sleep is required if compander is enabled as per
  688. * HW requirement. If compander is disabled, then
  689. * 20ms delay is required.
  690. */
  691. if (!wcd938x->comp2_enable)
  692. usleep_range(20000, 20100);
  693. else
  694. usleep_range(7000, 7100);
  695. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  696. 0x40, 0x00);
  697. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  698. WCD_EVENT_PRE_HPHR_PA_OFF,
  699. &wcd938x->mbhc->wcd_mbhc);
  700. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  701. break;
  702. case SND_SOC_DAPM_POST_PMD:
  703. /*
  704. * 7ms sleep is required if compander is enabled as per
  705. * HW requirement. If compander is disabled, then
  706. * 20ms delay is required.
  707. */
  708. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  709. if (!wcd938x->comp2_enable)
  710. usleep_range(20000, 20100);
  711. else
  712. usleep_range(7000, 7100);
  713. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  714. }
  715. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  716. WCD_EVENT_POST_HPHR_PA_OFF,
  717. &wcd938x->mbhc->wcd_mbhc);
  718. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  719. 0x10, 0x00);
  720. snd_soc_component_update_bits(component,
  721. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  722. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  723. WCD_CLSH_EVENT_POST_PA,
  724. WCD_CLSH_STATE_HPHR,
  725. hph_mode);
  726. if (wcd938x->ldoh)
  727. snd_soc_component_update_bits(component,
  728. WCD938X_LDOH_MODE,
  729. 0x80, 0x00);
  730. break;
  731. };
  732. return ret;
  733. }
  734. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  735. struct snd_kcontrol *kcontrol,
  736. int event)
  737. {
  738. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  739. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  740. int ret = 0;
  741. int hph_mode = wcd938x->hph_mode;
  742. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  743. w->name, event);
  744. switch (event) {
  745. case SND_SOC_DAPM_PRE_PMU:
  746. if (wcd938x->ldoh)
  747. snd_soc_component_update_bits(component,
  748. WCD938X_LDOH_MODE,
  749. 0x80, 0x80);
  750. if (wcd938x->update_wcd_event)
  751. wcd938x->update_wcd_event(wcd938x->handle,
  752. WCD_BOLERO_EVT_RX_MUTE,
  753. (WCD_RX1 << 0x10 | 0x01));
  754. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  755. wcd938x->rx_swr_dev->dev_num,
  756. true);
  757. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  758. WCD_CLSH_EVENT_PRE_DAC,
  759. WCD_CLSH_STATE_HPHL,
  760. hph_mode);
  761. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  762. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  763. 0x20, 0x20);
  764. wcd_clsh_set_hph_mode(component, hph_mode);
  765. /* 100 usec delay as per HW requirement */
  766. usleep_range(100, 110);
  767. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  768. snd_soc_component_update_bits(component,
  769. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  770. break;
  771. case SND_SOC_DAPM_POST_PMU:
  772. /*
  773. * 7ms sleep is required if compander is enabled as per
  774. * HW requirement. If compander is disabled, then
  775. * 20ms delay is required.
  776. */
  777. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  778. if (!wcd938x->comp1_enable)
  779. usleep_range(20000, 20100);
  780. else
  781. usleep_range(7000, 7100);
  782. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  783. }
  784. snd_soc_component_update_bits(component,
  785. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  786. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  787. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  788. snd_soc_component_update_bits(component,
  789. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  790. if (wcd938x->update_wcd_event)
  791. wcd938x->update_wcd_event(wcd938x->handle,
  792. WCD_BOLERO_EVT_RX_MUTE,
  793. (WCD_RX1 << 0x10));
  794. wcd_enable_irq(&wcd938x->irq_info,
  795. WCD938X_IRQ_HPHL_PDM_WD_INT);
  796. break;
  797. case SND_SOC_DAPM_PRE_PMD:
  798. if (wcd938x->update_wcd_event)
  799. wcd938x->update_wcd_event(wcd938x->handle,
  800. WCD_BOLERO_EVT_RX_MUTE,
  801. (WCD_RX1 << 0x10 | 0x1));
  802. wcd_disable_irq(&wcd938x->irq_info,
  803. WCD938X_IRQ_HPHL_PDM_WD_INT);
  804. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  805. wcd938x->update_wcd_event(wcd938x->handle,
  806. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  807. (WCD_RX1 << 0x10));
  808. /*
  809. * 7ms sleep is required if compander is enabled as per
  810. * HW requirement. If compander is disabled, then
  811. * 20ms delay is required.
  812. */
  813. if (!wcd938x->comp1_enable)
  814. usleep_range(20000, 20100);
  815. else
  816. usleep_range(7000, 7100);
  817. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  818. 0x80, 0x00);
  819. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  820. WCD_EVENT_PRE_HPHL_PA_OFF,
  821. &wcd938x->mbhc->wcd_mbhc);
  822. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  823. break;
  824. case SND_SOC_DAPM_POST_PMD:
  825. /*
  826. * 7ms sleep is required if compander is enabled as per
  827. * HW requirement. If compander is disabled, then
  828. * 20ms delay is required.
  829. */
  830. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  831. if (!wcd938x->comp1_enable)
  832. usleep_range(21000, 21100);
  833. else
  834. usleep_range(7000, 7100);
  835. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  836. }
  837. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  838. WCD_EVENT_POST_HPHL_PA_OFF,
  839. &wcd938x->mbhc->wcd_mbhc);
  840. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  841. 0x20, 0x00);
  842. snd_soc_component_update_bits(component,
  843. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  844. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  845. WCD_CLSH_EVENT_POST_PA,
  846. WCD_CLSH_STATE_HPHL,
  847. hph_mode);
  848. if (wcd938x->ldoh)
  849. snd_soc_component_update_bits(component,
  850. WCD938X_LDOH_MODE,
  851. 0x80, 0x00);
  852. break;
  853. };
  854. return ret;
  855. }
  856. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  857. struct snd_kcontrol *kcontrol,
  858. int event)
  859. {
  860. struct snd_soc_component *component =
  861. snd_soc_dapm_to_component(w->dapm);
  862. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  863. int hph_mode = wcd938x->hph_mode;
  864. int ret = 0;
  865. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  866. w->name, event);
  867. switch (event) {
  868. case SND_SOC_DAPM_PRE_PMU:
  869. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  870. wcd938x->rx_swr_dev->dev_num,
  871. true);
  872. snd_soc_component_update_bits(component,
  873. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  874. break;
  875. case SND_SOC_DAPM_POST_PMU:
  876. /* 1 msec delay as per HW requirement */
  877. usleep_range(1000, 1010);
  878. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  879. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  880. snd_soc_component_update_bits(component,
  881. WCD938X_ANA_RX_SUPPLIES,
  882. 0x02, 0x02);
  883. if (wcd938x->update_wcd_event)
  884. wcd938x->update_wcd_event(wcd938x->handle,
  885. WCD_BOLERO_EVT_RX_MUTE,
  886. (WCD_RX3 << 0x10));
  887. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  888. break;
  889. case SND_SOC_DAPM_PRE_PMD:
  890. wcd_disable_irq(&wcd938x->irq_info,
  891. WCD938X_IRQ_AUX_PDM_WD_INT);
  892. if (wcd938x->update_wcd_event)
  893. wcd938x->update_wcd_event(wcd938x->handle,
  894. WCD_BOLERO_EVT_RX_MUTE,
  895. (WCD_RX3 << 0x10 | 0x1));
  896. break;
  897. case SND_SOC_DAPM_POST_PMD:
  898. /* 1 msec delay as per HW requirement */
  899. usleep_range(1000, 1010);
  900. snd_soc_component_update_bits(component,
  901. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  902. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  903. WCD_CLSH_EVENT_POST_PA,
  904. WCD_CLSH_STATE_AUX,
  905. hph_mode);
  906. wcd938x->flyback_cur_det_disable--;
  907. if (wcd938x->flyback_cur_det_disable == 0)
  908. snd_soc_component_update_bits(component,
  909. WCD938X_FLYBACK_EN,
  910. 0x04, 0x04);
  911. break;
  912. };
  913. return ret;
  914. }
  915. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  916. struct snd_kcontrol *kcontrol,
  917. int event)
  918. {
  919. struct snd_soc_component *component =
  920. snd_soc_dapm_to_component(w->dapm);
  921. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  922. int hph_mode = wcd938x->hph_mode;
  923. int ret = 0;
  924. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  925. w->name, event);
  926. switch (event) {
  927. case SND_SOC_DAPM_PRE_PMU:
  928. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  929. wcd938x->rx_swr_dev->dev_num,
  930. true);
  931. /*
  932. * Enable watchdog interrupt for HPHL or AUX
  933. * depending on mux value
  934. */
  935. wcd938x->ear_rx_path =
  936. snd_soc_component_read32(
  937. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  938. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  939. snd_soc_component_update_bits(component,
  940. WCD938X_DIGITAL_PDM_WD_CTL2,
  941. 0x05, 0x05);
  942. else
  943. snd_soc_component_update_bits(component,
  944. WCD938X_DIGITAL_PDM_WD_CTL0,
  945. 0x17, 0x13);
  946. if (!wcd938x->comp1_enable)
  947. snd_soc_component_update_bits(component,
  948. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  949. break;
  950. case SND_SOC_DAPM_POST_PMU:
  951. /* 6 msec delay as per HW requirement */
  952. usleep_range(6000, 6010);
  953. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  954. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  955. snd_soc_component_update_bits(component,
  956. WCD938X_ANA_RX_SUPPLIES,
  957. 0x02, 0x02);
  958. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  959. if (wcd938x->update_wcd_event)
  960. wcd938x->update_wcd_event(wcd938x->handle,
  961. WCD_BOLERO_EVT_RX_MUTE,
  962. (WCD_RX3 << 0x10));
  963. wcd_enable_irq(&wcd938x->irq_info,
  964. WCD938X_IRQ_AUX_PDM_WD_INT);
  965. } else {
  966. if (wcd938x->update_wcd_event)
  967. wcd938x->update_wcd_event(wcd938x->handle,
  968. WCD_BOLERO_EVT_RX_MUTE,
  969. (WCD_RX1 << 0x10));
  970. wcd_enable_irq(&wcd938x->irq_info,
  971. WCD938X_IRQ_HPHL_PDM_WD_INT);
  972. }
  973. break;
  974. case SND_SOC_DAPM_PRE_PMD:
  975. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  976. wcd_disable_irq(&wcd938x->irq_info,
  977. WCD938X_IRQ_AUX_PDM_WD_INT);
  978. if (wcd938x->update_wcd_event)
  979. wcd938x->update_wcd_event(wcd938x->handle,
  980. WCD_BOLERO_EVT_RX_MUTE,
  981. (WCD_RX3 << 0x10 | 0x1));
  982. } else {
  983. wcd_disable_irq(&wcd938x->irq_info,
  984. WCD938X_IRQ_HPHL_PDM_WD_INT);
  985. if (wcd938x->update_wcd_event)
  986. wcd938x->update_wcd_event(wcd938x->handle,
  987. WCD_BOLERO_EVT_RX_MUTE,
  988. (WCD_RX1 << 0x10 | 0x1));
  989. }
  990. break;
  991. case SND_SOC_DAPM_POST_PMD:
  992. if (!wcd938x->comp1_enable)
  993. snd_soc_component_update_bits(component,
  994. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  995. /* 7 msec delay as per HW requirement */
  996. usleep_range(7000, 7010);
  997. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  998. snd_soc_component_update_bits(component,
  999. WCD938X_DIGITAL_PDM_WD_CTL2,
  1000. 0x05, 0x00);
  1001. else
  1002. snd_soc_component_update_bits(component,
  1003. WCD938X_DIGITAL_PDM_WD_CTL0,
  1004. 0x17, 0x00);
  1005. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1006. WCD_CLSH_EVENT_POST_PA,
  1007. WCD_CLSH_STATE_EAR,
  1008. hph_mode);
  1009. wcd938x->flyback_cur_det_disable--;
  1010. if (wcd938x->flyback_cur_det_disable == 0)
  1011. snd_soc_component_update_bits(component,
  1012. WCD938X_FLYBACK_EN,
  1013. 0x04, 0x04);
  1014. break;
  1015. };
  1016. return ret;
  1017. }
  1018. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1019. struct snd_kcontrol *kcontrol,
  1020. int event)
  1021. {
  1022. struct snd_soc_component *component =
  1023. snd_soc_dapm_to_component(w->dapm);
  1024. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1025. int mode = wcd938x->hph_mode;
  1026. int ret = 0;
  1027. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1028. w->name, event);
  1029. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1030. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1031. wcd938x_rx_connect_port(component, CLSH,
  1032. SND_SOC_DAPM_EVENT_ON(event));
  1033. }
  1034. if (SND_SOC_DAPM_EVENT_OFF(event))
  1035. ret = swr_slvdev_datapath_control(
  1036. wcd938x->rx_swr_dev,
  1037. wcd938x->rx_swr_dev->dev_num,
  1038. false);
  1039. return ret;
  1040. }
  1041. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1042. struct snd_kcontrol *kcontrol,
  1043. int event)
  1044. {
  1045. struct snd_soc_component *component =
  1046. snd_soc_dapm_to_component(w->dapm);
  1047. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1048. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1049. w->name, event);
  1050. switch (event) {
  1051. case SND_SOC_DAPM_PRE_PMU:
  1052. wcd938x_rx_connect_port(component, HPH_L, true);
  1053. if (wcd938x->comp1_enable)
  1054. wcd938x_rx_connect_port(component, COMP_L, true);
  1055. break;
  1056. case SND_SOC_DAPM_POST_PMD:
  1057. wcd938x_rx_connect_port(component, HPH_L, false);
  1058. if (wcd938x->comp1_enable)
  1059. wcd938x_rx_connect_port(component, COMP_L, false);
  1060. wcd938x_rx_clk_disable(component);
  1061. snd_soc_component_update_bits(component,
  1062. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1063. 0x01, 0x00);
  1064. break;
  1065. };
  1066. return 0;
  1067. }
  1068. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1069. struct snd_kcontrol *kcontrol, int event)
  1070. {
  1071. struct snd_soc_component *component =
  1072. snd_soc_dapm_to_component(w->dapm);
  1073. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1074. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1075. w->name, event);
  1076. switch (event) {
  1077. case SND_SOC_DAPM_PRE_PMU:
  1078. wcd938x_rx_connect_port(component, HPH_R, true);
  1079. if (wcd938x->comp2_enable)
  1080. wcd938x_rx_connect_port(component, COMP_R, true);
  1081. break;
  1082. case SND_SOC_DAPM_POST_PMD:
  1083. wcd938x_rx_connect_port(component, HPH_R, false);
  1084. if (wcd938x->comp2_enable)
  1085. wcd938x_rx_connect_port(component, COMP_R, false);
  1086. wcd938x_rx_clk_disable(component);
  1087. snd_soc_component_update_bits(component,
  1088. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1089. 0x02, 0x00);
  1090. break;
  1091. };
  1092. return 0;
  1093. }
  1094. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1095. struct snd_kcontrol *kcontrol,
  1096. int event)
  1097. {
  1098. struct snd_soc_component *component =
  1099. snd_soc_dapm_to_component(w->dapm);
  1100. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1101. w->name, event);
  1102. switch (event) {
  1103. case SND_SOC_DAPM_PRE_PMU:
  1104. wcd938x_rx_connect_port(component, LO, true);
  1105. break;
  1106. case SND_SOC_DAPM_POST_PMD:
  1107. wcd938x_rx_connect_port(component, LO, false);
  1108. /* 6 msec delay as per HW requirement */
  1109. usleep_range(6000, 6010);
  1110. wcd938x_rx_clk_disable(component);
  1111. snd_soc_component_update_bits(component,
  1112. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1113. break;
  1114. }
  1115. return 0;
  1116. }
  1117. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1118. struct snd_kcontrol *kcontrol,
  1119. int event)
  1120. {
  1121. struct snd_soc_component *component =
  1122. snd_soc_dapm_to_component(w->dapm);
  1123. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1124. u16 dmic_clk_reg, dmic_clk_en_reg;
  1125. s32 *dmic_clk_cnt;
  1126. u8 dmic_ctl_shift = 0;
  1127. u8 dmic_clk_shift = 0;
  1128. u8 dmic_clk_mask = 0;
  1129. u16 dmic2_left_en = 0;
  1130. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1131. w->name, event);
  1132. switch (w->shift) {
  1133. case 0:
  1134. case 1:
  1135. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1136. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1137. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1138. dmic_clk_mask = 0x0F;
  1139. dmic_clk_shift = 0x00;
  1140. dmic_ctl_shift = 0x00;
  1141. break;
  1142. case 2:
  1143. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1144. case 3:
  1145. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1146. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1147. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1148. dmic_clk_mask = 0xF0;
  1149. dmic_clk_shift = 0x04;
  1150. dmic_ctl_shift = 0x01;
  1151. break;
  1152. case 4:
  1153. case 5:
  1154. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1155. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1156. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1157. dmic_clk_mask = 0x0F;
  1158. dmic_clk_shift = 0x00;
  1159. dmic_ctl_shift = 0x02;
  1160. break;
  1161. case 6:
  1162. case 7:
  1163. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1164. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1165. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1166. dmic_clk_mask = 0xF0;
  1167. dmic_clk_shift = 0x04;
  1168. dmic_ctl_shift = 0x03;
  1169. break;
  1170. default:
  1171. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1172. __func__);
  1173. return -EINVAL;
  1174. };
  1175. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1176. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1177. switch (event) {
  1178. case SND_SOC_DAPM_PRE_PMU:
  1179. snd_soc_component_update_bits(component,
  1180. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1181. (0x01 << dmic_ctl_shift), 0x00);
  1182. /* 250us sleep as per HW requirement */
  1183. usleep_range(250, 260);
  1184. if (dmic2_left_en)
  1185. snd_soc_component_update_bits(component,
  1186. dmic2_left_en, 0x80, 0x80);
  1187. /* Setting DMIC clock rate to 2.4MHz */
  1188. snd_soc_component_update_bits(component,
  1189. dmic_clk_reg, dmic_clk_mask,
  1190. (0x03 << dmic_clk_shift));
  1191. snd_soc_component_update_bits(component,
  1192. dmic_clk_en_reg, 0x08, 0x08);
  1193. /* enable clock scaling */
  1194. snd_soc_component_update_bits(component,
  1195. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1196. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1197. break;
  1198. case SND_SOC_DAPM_POST_PMD:
  1199. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1200. snd_soc_component_update_bits(component,
  1201. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1202. (0x01 << dmic_ctl_shift),
  1203. (0x01 << dmic_ctl_shift));
  1204. if (dmic2_left_en)
  1205. snd_soc_component_update_bits(component,
  1206. dmic2_left_en, 0x80, 0x00);
  1207. snd_soc_component_update_bits(component,
  1208. dmic_clk_en_reg, 0x08, 0x00);
  1209. break;
  1210. };
  1211. return 0;
  1212. }
  1213. /*
  1214. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1215. * @micb_mv: micbias in mv
  1216. *
  1217. * return register value converted
  1218. */
  1219. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1220. {
  1221. /* min micbias voltage is 1V and maximum is 2.85V */
  1222. if (micb_mv < 1000 || micb_mv > 2850) {
  1223. pr_err("%s: unsupported micbias voltage\n", __func__);
  1224. return -EINVAL;
  1225. }
  1226. return (micb_mv - 1000) / 50;
  1227. }
  1228. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1229. /*
  1230. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1231. * @component: handle to snd_soc_component *
  1232. * @req_volt: micbias voltage to be set
  1233. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1234. *
  1235. * return 0 if adjustment is success or error code in case of failure
  1236. */
  1237. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1238. int req_volt, int micb_num)
  1239. {
  1240. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1241. int cur_vout_ctl, req_vout_ctl;
  1242. int micb_reg, micb_val, micb_en;
  1243. int ret = 0;
  1244. switch (micb_num) {
  1245. case MIC_BIAS_1:
  1246. micb_reg = WCD938X_ANA_MICB1;
  1247. break;
  1248. case MIC_BIAS_2:
  1249. micb_reg = WCD938X_ANA_MICB2;
  1250. break;
  1251. case MIC_BIAS_3:
  1252. micb_reg = WCD938X_ANA_MICB3;
  1253. break;
  1254. case MIC_BIAS_4:
  1255. micb_reg = WCD938X_ANA_MICB4;
  1256. break;
  1257. default:
  1258. return -EINVAL;
  1259. }
  1260. mutex_lock(&wcd938x->micb_lock);
  1261. /*
  1262. * If requested micbias voltage is same as current micbias
  1263. * voltage, then just return. Otherwise, adjust voltage as
  1264. * per requested value. If micbias is already enabled, then
  1265. * to avoid slow micbias ramp-up or down enable pull-up
  1266. * momentarily, change the micbias value and then re-enable
  1267. * micbias.
  1268. */
  1269. micb_val = snd_soc_component_read32(component, micb_reg);
  1270. micb_en = (micb_val & 0xC0) >> 6;
  1271. cur_vout_ctl = micb_val & 0x3F;
  1272. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1273. if (req_vout_ctl < 0) {
  1274. ret = -EINVAL;
  1275. goto exit;
  1276. }
  1277. if (cur_vout_ctl == req_vout_ctl) {
  1278. ret = 0;
  1279. goto exit;
  1280. }
  1281. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1282. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1283. req_volt, micb_en);
  1284. if (micb_en == 0x1)
  1285. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1286. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1287. if (micb_en == 0x1) {
  1288. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1289. /*
  1290. * Add 2ms delay as per HW requirement after enabling
  1291. * micbias
  1292. */
  1293. usleep_range(2000, 2100);
  1294. }
  1295. exit:
  1296. mutex_unlock(&wcd938x->micb_lock);
  1297. return ret;
  1298. }
  1299. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1300. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1301. struct snd_kcontrol *kcontrol,
  1302. int event)
  1303. {
  1304. struct snd_soc_component *component =
  1305. snd_soc_dapm_to_component(w->dapm);
  1306. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1307. int ret = 0;
  1308. int bank = 0;
  1309. int mode = 0;
  1310. bank = wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1311. wcd938x->tx_swr_dev->dev_num);
  1312. wcd938x_swr_slv_set_host_clk_div2(wcd938x->tx_swr_dev,
  1313. wcd938x->tx_swr_dev->dev_num, bank);
  1314. switch (event) {
  1315. case SND_SOC_DAPM_PRE_PMU:
  1316. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1317. wcd938x->tx_swr_dev->dev_num,
  1318. true);
  1319. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1320. mode |= wcd938x->tx_mode[WCD_ADC1];
  1321. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1322. mode |= wcd938x->tx_mode[WCD_ADC2];
  1323. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1324. mode |= wcd938x->tx_mode[WCD_ADC3];
  1325. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1326. mode |= wcd938x->tx_mode[WCD_ADC4];
  1327. wcd938x_set_swr_clk_rate(component, mode, bank);
  1328. break;
  1329. case SND_SOC_DAPM_POST_PMD:
  1330. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1331. wcd938x->tx_swr_dev->dev_num,
  1332. false);
  1333. wcd938x_set_swr_clk_rate(component, ADC_MODE_INVALID, bank);
  1334. break;
  1335. };
  1336. return ret;
  1337. }
  1338. static int wcd938x_get_adc_mode(int val)
  1339. {
  1340. int ret = 0;
  1341. switch (val) {
  1342. case ADC_MODE_INVALID:
  1343. ret = ADC_MODE_VAL_NORMAL;
  1344. break;
  1345. case ADC_MODE_HIFI:
  1346. ret = ADC_MODE_VAL_HIFI;
  1347. break;
  1348. case ADC_MODE_LO_HIF:
  1349. ret = ADC_MODE_VAL_LO_HIF;
  1350. break;
  1351. case ADC_MODE_NORMAL:
  1352. ret = ADC_MODE_VAL_NORMAL;
  1353. break;
  1354. case ADC_MODE_LP:
  1355. ret = ADC_MODE_VAL_LP;
  1356. break;
  1357. case ADC_MODE_ULP1:
  1358. ret = ADC_MODE_VAL_ULP1;
  1359. break;
  1360. case ADC_MODE_ULP2:
  1361. ret = ADC_MODE_VAL_ULP2;
  1362. break;
  1363. default:
  1364. ret = -EINVAL;
  1365. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1366. break;
  1367. }
  1368. return ret;
  1369. }
  1370. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1371. struct snd_kcontrol *kcontrol,
  1372. int event){
  1373. struct snd_soc_component *component =
  1374. snd_soc_dapm_to_component(w->dapm);
  1375. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1376. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1377. w->name, event);
  1378. switch (event) {
  1379. case SND_SOC_DAPM_PRE_PMU:
  1380. snd_soc_component_update_bits(component,
  1381. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1382. snd_soc_component_update_bits(component,
  1383. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1384. set_bit(w->shift, &wcd938x->status_mask);
  1385. /* Enable BCS for Headset mic */
  1386. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1387. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1388. wcd938x_tx_connect_port(component, MBHC, true);
  1389. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1390. }
  1391. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1392. break;
  1393. case SND_SOC_DAPM_POST_PMD:
  1394. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1395. if (w->shift == 1 &&
  1396. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1397. wcd938x_tx_connect_port(component, MBHC, false);
  1398. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1399. }
  1400. snd_soc_component_update_bits(component,
  1401. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1402. clear_bit(w->shift, &wcd938x->status_mask);
  1403. break;
  1404. };
  1405. return 0;
  1406. }
  1407. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1408. bool bcs_disable)
  1409. {
  1410. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1411. if (wcd938x->update_wcd_event) {
  1412. if (bcs_disable)
  1413. wcd938x->update_wcd_event(wcd938x->handle,
  1414. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1415. else
  1416. wcd938x->update_wcd_event(wcd938x->handle,
  1417. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1418. }
  1419. }
  1420. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1421. int channel, int mode)
  1422. {
  1423. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1424. int ret = 0;
  1425. switch (channel) {
  1426. case 0:
  1427. reg = WCD938X_ANA_TX_CH2;
  1428. mask = 0x40;
  1429. break;
  1430. case 1:
  1431. reg = WCD938X_ANA_TX_CH2;
  1432. mask = 0x20;
  1433. break;
  1434. case 2:
  1435. reg = WCD938X_ANA_TX_CH4;
  1436. mask = 0x40;
  1437. break;
  1438. case 3:
  1439. reg = WCD938X_ANA_TX_CH4;
  1440. mask = 0x20;
  1441. break;
  1442. default:
  1443. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1444. ret = -EINVAL;
  1445. break;
  1446. }
  1447. if (!mode)
  1448. val = 0x00;
  1449. else
  1450. val = mask;
  1451. if (!ret)
  1452. snd_soc_component_update_bits(component, reg, mask, val);
  1453. return ret;
  1454. }
  1455. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1456. struct snd_kcontrol *kcontrol, int event)
  1457. {
  1458. struct snd_soc_component *component =
  1459. snd_soc_dapm_to_component(w->dapm);
  1460. int mode;
  1461. int ret = 0;
  1462. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1463. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1464. w->name, event);
  1465. switch (event) {
  1466. case SND_SOC_DAPM_PRE_PMU:
  1467. snd_soc_component_update_bits(component,
  1468. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1469. snd_soc_component_update_bits(component,
  1470. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1471. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1472. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1473. if (mode < 0) {
  1474. dev_info(component->dev,
  1475. "%s: invalid mode, setting to normal mode\n",
  1476. __func__);
  1477. mode = ADC_MODE_VAL_NORMAL;
  1478. }
  1479. switch (w->shift) {
  1480. case 0:
  1481. snd_soc_component_update_bits(component,
  1482. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1483. mode);
  1484. snd_soc_component_update_bits(component,
  1485. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1486. break;
  1487. case 1:
  1488. snd_soc_component_update_bits(component,
  1489. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1490. mode << 4);
  1491. snd_soc_component_update_bits(component,
  1492. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1493. break;
  1494. case 2:
  1495. snd_soc_component_update_bits(component,
  1496. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1497. mode);
  1498. snd_soc_component_update_bits(component,
  1499. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1500. break;
  1501. case 3:
  1502. snd_soc_component_update_bits(component,
  1503. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1504. mode << 4);
  1505. snd_soc_component_update_bits(component,
  1506. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1507. break;
  1508. default:
  1509. break;
  1510. }
  1511. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1512. break;
  1513. case SND_SOC_DAPM_POST_PMD:
  1514. switch (w->shift) {
  1515. case 0:
  1516. snd_soc_component_update_bits(component,
  1517. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1518. 0x00);
  1519. snd_soc_component_update_bits(component,
  1520. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1521. break;
  1522. case 1:
  1523. snd_soc_component_update_bits(component,
  1524. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1525. 0x00);
  1526. snd_soc_component_update_bits(component,
  1527. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1528. break;
  1529. case 2:
  1530. snd_soc_component_update_bits(component,
  1531. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1532. 0x00);
  1533. snd_soc_component_update_bits(component,
  1534. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1535. break;
  1536. case 3:
  1537. snd_soc_component_update_bits(component,
  1538. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1539. 0x00);
  1540. snd_soc_component_update_bits(component,
  1541. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1542. break;
  1543. default:
  1544. break;
  1545. }
  1546. snd_soc_component_update_bits(component,
  1547. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1548. break;
  1549. };
  1550. return ret;
  1551. }
  1552. int wcd938x_micbias_control(struct snd_soc_component *component,
  1553. int micb_num, int req, bool is_dapm)
  1554. {
  1555. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1556. int micb_index = micb_num - 1;
  1557. u16 micb_reg;
  1558. int pre_off_event = 0, post_off_event = 0;
  1559. int post_on_event = 0, post_dapm_off = 0;
  1560. int post_dapm_on = 0;
  1561. int ret = 0;
  1562. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1563. dev_err(component->dev,
  1564. "%s: Invalid micbias index, micb_ind:%d\n",
  1565. __func__, micb_index);
  1566. return -EINVAL;
  1567. }
  1568. if (NULL == wcd938x) {
  1569. dev_err(component->dev,
  1570. "%s: wcd938x private data is NULL\n", __func__);
  1571. return -EINVAL;
  1572. }
  1573. switch (micb_num) {
  1574. case MIC_BIAS_1:
  1575. micb_reg = WCD938X_ANA_MICB1;
  1576. break;
  1577. case MIC_BIAS_2:
  1578. micb_reg = WCD938X_ANA_MICB2;
  1579. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1580. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1581. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1582. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1583. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1584. break;
  1585. case MIC_BIAS_3:
  1586. micb_reg = WCD938X_ANA_MICB3;
  1587. break;
  1588. case MIC_BIAS_4:
  1589. micb_reg = WCD938X_ANA_MICB4;
  1590. break;
  1591. default:
  1592. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1593. __func__, micb_num);
  1594. return -EINVAL;
  1595. };
  1596. mutex_lock(&wcd938x->micb_lock);
  1597. switch (req) {
  1598. case MICB_PULLUP_ENABLE:
  1599. if (!wcd938x->dev_up) {
  1600. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1601. __func__, req);
  1602. ret = -ENODEV;
  1603. goto done;
  1604. }
  1605. wcd938x->pullup_ref[micb_index]++;
  1606. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1607. (wcd938x->micb_ref[micb_index] == 0))
  1608. snd_soc_component_update_bits(component, micb_reg,
  1609. 0xC0, 0x80);
  1610. break;
  1611. case MICB_PULLUP_DISABLE:
  1612. if (wcd938x->pullup_ref[micb_index] > 0)
  1613. wcd938x->pullup_ref[micb_index]--;
  1614. if (!wcd938x->dev_up) {
  1615. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1616. __func__, req);
  1617. ret = -ENODEV;
  1618. goto done;
  1619. }
  1620. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1621. (wcd938x->micb_ref[micb_index] == 0))
  1622. snd_soc_component_update_bits(component, micb_reg,
  1623. 0xC0, 0x00);
  1624. break;
  1625. case MICB_ENABLE:
  1626. if (!wcd938x->dev_up) {
  1627. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1628. __func__, req);
  1629. ret = -ENODEV;
  1630. goto done;
  1631. }
  1632. wcd938x->micb_ref[micb_index]++;
  1633. if (wcd938x->micb_ref[micb_index] == 1) {
  1634. snd_soc_component_update_bits(component,
  1635. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1636. snd_soc_component_update_bits(component,
  1637. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1638. snd_soc_component_update_bits(component,
  1639. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1640. snd_soc_component_update_bits(component,
  1641. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1642. snd_soc_component_update_bits(component,
  1643. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1644. snd_soc_component_update_bits(component,
  1645. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1646. snd_soc_component_update_bits(component,
  1647. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1648. snd_soc_component_update_bits(component,
  1649. micb_reg, 0xC0, 0x40);
  1650. if (post_on_event)
  1651. blocking_notifier_call_chain(
  1652. &wcd938x->mbhc->notifier,
  1653. post_on_event,
  1654. &wcd938x->mbhc->wcd_mbhc);
  1655. }
  1656. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1657. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1658. post_dapm_on,
  1659. &wcd938x->mbhc->wcd_mbhc);
  1660. break;
  1661. case MICB_DISABLE:
  1662. if (wcd938x->micb_ref[micb_index] > 0)
  1663. wcd938x->micb_ref[micb_index]--;
  1664. if (!wcd938x->dev_up) {
  1665. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1666. __func__, req);
  1667. ret = -ENODEV;
  1668. goto done;
  1669. }
  1670. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1671. (wcd938x->pullup_ref[micb_index] > 0))
  1672. snd_soc_component_update_bits(component, micb_reg,
  1673. 0xC0, 0x80);
  1674. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1675. (wcd938x->pullup_ref[micb_index] == 0)) {
  1676. if (pre_off_event && wcd938x->mbhc)
  1677. blocking_notifier_call_chain(
  1678. &wcd938x->mbhc->notifier,
  1679. pre_off_event,
  1680. &wcd938x->mbhc->wcd_mbhc);
  1681. snd_soc_component_update_bits(component, micb_reg,
  1682. 0xC0, 0x00);
  1683. if (post_off_event && wcd938x->mbhc)
  1684. blocking_notifier_call_chain(
  1685. &wcd938x->mbhc->notifier,
  1686. post_off_event,
  1687. &wcd938x->mbhc->wcd_mbhc);
  1688. }
  1689. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1690. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1691. post_dapm_off,
  1692. &wcd938x->mbhc->wcd_mbhc);
  1693. break;
  1694. };
  1695. dev_dbg(component->dev,
  1696. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1697. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1698. wcd938x->pullup_ref[micb_index]);
  1699. done:
  1700. mutex_unlock(&wcd938x->micb_lock);
  1701. return ret;
  1702. }
  1703. EXPORT_SYMBOL(wcd938x_micbias_control);
  1704. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1705. {
  1706. int ret = 0;
  1707. uint8_t devnum = 0;
  1708. int num_retry = NUM_ATTEMPTS;
  1709. do {
  1710. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1711. if (ret) {
  1712. dev_err(&swr_dev->dev,
  1713. "%s get devnum %d for dev addr %lx failed\n",
  1714. __func__, devnum, swr_dev->addr);
  1715. /* retry after 1ms */
  1716. usleep_range(1000, 1010);
  1717. }
  1718. } while (ret && --num_retry);
  1719. swr_dev->dev_num = devnum;
  1720. return 0;
  1721. }
  1722. static int wcd938x_event_notify(struct notifier_block *block,
  1723. unsigned long val,
  1724. void *data)
  1725. {
  1726. u16 event = (val & 0xffff);
  1727. int ret = 0;
  1728. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1729. struct snd_soc_component *component = wcd938x->component;
  1730. struct wcd_mbhc *mbhc;
  1731. switch (event) {
  1732. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1733. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1734. snd_soc_component_update_bits(component,
  1735. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1736. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1737. }
  1738. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1739. snd_soc_component_update_bits(component,
  1740. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1741. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1742. }
  1743. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1744. snd_soc_component_update_bits(component,
  1745. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1746. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1747. }
  1748. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1749. snd_soc_component_update_bits(component,
  1750. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1751. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1752. }
  1753. break;
  1754. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1755. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1756. 0xC0, 0x00);
  1757. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1758. 0x80, 0x00);
  1759. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1760. 0x80, 0x00);
  1761. break;
  1762. case BOLERO_WCD_EVT_SSR_DOWN:
  1763. wcd938x->dev_up = false;
  1764. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1765. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1766. wcd938x_reset_low(wcd938x->dev);
  1767. break;
  1768. case BOLERO_WCD_EVT_SSR_UP:
  1769. wcd938x_reset(wcd938x->dev);
  1770. /* allow reset to take effect */
  1771. usleep_range(10000, 10010);
  1772. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1773. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1774. wcd938x_init_reg(component);
  1775. regcache_mark_dirty(wcd938x->regmap);
  1776. regcache_sync(wcd938x->regmap);
  1777. /* Initialize MBHC module */
  1778. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1779. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1780. if (ret) {
  1781. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1782. __func__);
  1783. } else {
  1784. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1785. }
  1786. wcd938x->dev_up = true;
  1787. break;
  1788. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1789. snd_soc_component_update_bits(component,
  1790. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1791. ((val >> 0x10) << 0x01));
  1792. break;
  1793. default:
  1794. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1795. break;
  1796. }
  1797. return 0;
  1798. }
  1799. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1800. int event)
  1801. {
  1802. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1803. int micb_num;
  1804. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1805. __func__, w->name, event);
  1806. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1807. micb_num = MIC_BIAS_1;
  1808. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1809. micb_num = MIC_BIAS_2;
  1810. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1811. micb_num = MIC_BIAS_3;
  1812. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1813. micb_num = MIC_BIAS_4;
  1814. else
  1815. return -EINVAL;
  1816. switch (event) {
  1817. case SND_SOC_DAPM_PRE_PMU:
  1818. wcd938x_micbias_control(component, micb_num,
  1819. MICB_ENABLE, true);
  1820. break;
  1821. case SND_SOC_DAPM_POST_PMU:
  1822. /* 1 msec delay as per HW requirement */
  1823. usleep_range(1000, 1100);
  1824. break;
  1825. case SND_SOC_DAPM_POST_PMD:
  1826. wcd938x_micbias_control(component, micb_num,
  1827. MICB_DISABLE, true);
  1828. break;
  1829. };
  1830. return 0;
  1831. }
  1832. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1833. struct snd_kcontrol *kcontrol,
  1834. int event)
  1835. {
  1836. return __wcd938x_codec_enable_micbias(w, event);
  1837. }
  1838. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1839. int event)
  1840. {
  1841. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1842. int micb_num;
  1843. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1844. __func__, w->name, event);
  1845. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1846. micb_num = MIC_BIAS_1;
  1847. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1848. micb_num = MIC_BIAS_2;
  1849. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1850. micb_num = MIC_BIAS_3;
  1851. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1852. micb_num = MIC_BIAS_4;
  1853. else
  1854. return -EINVAL;
  1855. switch (event) {
  1856. case SND_SOC_DAPM_PRE_PMU:
  1857. wcd938x_micbias_control(component, micb_num,
  1858. MICB_PULLUP_ENABLE, true);
  1859. break;
  1860. case SND_SOC_DAPM_POST_PMU:
  1861. /* 1 msec delay as per HW requirement */
  1862. usleep_range(1000, 1100);
  1863. break;
  1864. case SND_SOC_DAPM_POST_PMD:
  1865. wcd938x_micbias_control(component, micb_num,
  1866. MICB_PULLUP_DISABLE, true);
  1867. break;
  1868. };
  1869. return 0;
  1870. }
  1871. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1872. struct snd_kcontrol *kcontrol,
  1873. int event)
  1874. {
  1875. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1876. }
  1877. static int wcd938x_wakeup(void *handle, bool enable)
  1878. {
  1879. struct wcd938x_priv *priv;
  1880. int ret = 0;
  1881. if (!handle) {
  1882. pr_err("%s: NULL handle\n", __func__);
  1883. return -EINVAL;
  1884. }
  1885. priv = (struct wcd938x_priv *)handle;
  1886. if (!priv->tx_swr_dev) {
  1887. pr_err("%s: tx swr dev is NULL\n", __func__);
  1888. return -EINVAL;
  1889. }
  1890. mutex_lock(&priv->wakeup_lock);
  1891. if (enable)
  1892. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  1893. else
  1894. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  1895. mutex_unlock(&priv->wakeup_lock);
  1896. return ret;
  1897. }
  1898. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  1899. struct snd_kcontrol *kcontrol,
  1900. int event)
  1901. {
  1902. int ret = 0;
  1903. struct snd_soc_component *component =
  1904. snd_soc_dapm_to_component(w->dapm);
  1905. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1906. switch (event) {
  1907. case SND_SOC_DAPM_PRE_PMU:
  1908. wcd938x_wakeup(wcd938x, true);
  1909. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  1910. wcd938x_wakeup(wcd938x, false);
  1911. break;
  1912. case SND_SOC_DAPM_POST_PMD:
  1913. wcd938x_wakeup(wcd938x, true);
  1914. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  1915. wcd938x_wakeup(wcd938x, false);
  1916. break;
  1917. }
  1918. return ret;
  1919. }
  1920. static inline int wcd938x_tx_path_get(const char *wname,
  1921. unsigned int *path_num)
  1922. {
  1923. int ret = 0;
  1924. char *widget_name = NULL;
  1925. char *w_name = NULL;
  1926. char *path_num_char = NULL;
  1927. char *path_name = NULL;
  1928. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1929. if (!widget_name)
  1930. return -EINVAL;
  1931. w_name = widget_name;
  1932. path_name = strsep(&widget_name, " ");
  1933. if (!path_name) {
  1934. pr_err("%s: Invalid widget name = %s\n",
  1935. __func__, widget_name);
  1936. ret = -EINVAL;
  1937. goto err;
  1938. }
  1939. path_num_char = strpbrk(path_name, "0123");
  1940. if (!path_num_char) {
  1941. pr_err("%s: tx path index not found\n",
  1942. __func__);
  1943. ret = -EINVAL;
  1944. goto err;
  1945. }
  1946. ret = kstrtouint(path_num_char, 10, path_num);
  1947. if (ret < 0)
  1948. pr_err("%s: Invalid tx path = %s\n",
  1949. __func__, w_name);
  1950. err:
  1951. kfree(w_name);
  1952. return ret;
  1953. }
  1954. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1955. struct snd_ctl_elem_value *ucontrol)
  1956. {
  1957. struct snd_soc_component *component =
  1958. snd_soc_kcontrol_component(kcontrol);
  1959. struct wcd938x_priv *wcd938x = NULL;
  1960. int ret = 0;
  1961. unsigned int path = 0;
  1962. if (!component)
  1963. return -EINVAL;
  1964. wcd938x = snd_soc_component_get_drvdata(component);
  1965. if (!wcd938x)
  1966. return -EINVAL;
  1967. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1968. if (ret < 0)
  1969. return ret;
  1970. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1971. return 0;
  1972. }
  1973. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1974. struct snd_ctl_elem_value *ucontrol)
  1975. {
  1976. struct snd_soc_component *component =
  1977. snd_soc_kcontrol_component(kcontrol);
  1978. struct wcd938x_priv *wcd938x = NULL;
  1979. u32 mode_val;
  1980. unsigned int path = 0;
  1981. int ret = 0;
  1982. if (!component)
  1983. return -EINVAL;
  1984. wcd938x = snd_soc_component_get_drvdata(component);
  1985. if (!wcd938x)
  1986. return -EINVAL;
  1987. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1988. if (ret)
  1989. return ret;
  1990. mode_val = ucontrol->value.enumerated.item[0];
  1991. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1992. wcd938x->tx_mode[path] = mode_val;
  1993. return 0;
  1994. }
  1995. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1996. struct snd_ctl_elem_value *ucontrol)
  1997. {
  1998. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1999. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2000. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2001. return 0;
  2002. }
  2003. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2004. struct snd_ctl_elem_value *ucontrol)
  2005. {
  2006. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2007. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2008. u32 mode_val;
  2009. mode_val = ucontrol->value.enumerated.item[0];
  2010. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2011. if (wcd938x->variant == WCD9380) {
  2012. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2013. dev_info(component->dev,
  2014. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2015. __func__);
  2016. mode_val = CLS_H_ULP;
  2017. }
  2018. }
  2019. if (mode_val == CLS_H_NORMAL) {
  2020. dev_info(component->dev,
  2021. "%s:Invalid HPH Mode, default to class_AB\n",
  2022. __func__);
  2023. mode_val = CLS_H_ULP;
  2024. }
  2025. wcd938x->hph_mode = mode_val;
  2026. return 0;
  2027. }
  2028. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2029. struct snd_ctl_elem_value *ucontrol)
  2030. {
  2031. u8 ear_pa_gain = 0;
  2032. struct snd_soc_component *component =
  2033. snd_soc_kcontrol_component(kcontrol);
  2034. ear_pa_gain = snd_soc_component_read32(component,
  2035. WCD938X_ANA_EAR_COMPANDER_CTL);
  2036. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2037. ucontrol->value.integer.value[0] = ear_pa_gain;
  2038. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2039. ear_pa_gain);
  2040. return 0;
  2041. }
  2042. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2043. struct snd_ctl_elem_value *ucontrol)
  2044. {
  2045. u8 ear_pa_gain = 0;
  2046. struct snd_soc_component *component =
  2047. snd_soc_kcontrol_component(kcontrol);
  2048. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2049. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2050. __func__, ucontrol->value.integer.value[0]);
  2051. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2052. if (!wcd938x->comp1_enable) {
  2053. snd_soc_component_update_bits(component,
  2054. WCD938X_ANA_EAR_COMPANDER_CTL,
  2055. 0x7C, ear_pa_gain);
  2056. }
  2057. return 0;
  2058. }
  2059. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2060. struct snd_ctl_elem_value *ucontrol)
  2061. {
  2062. struct snd_soc_component *component =
  2063. snd_soc_kcontrol_component(kcontrol);
  2064. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2065. bool hphr;
  2066. struct soc_multi_mixer_control *mc;
  2067. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2068. hphr = mc->shift;
  2069. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2070. wcd938x->comp1_enable;
  2071. return 0;
  2072. }
  2073. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2074. struct snd_ctl_elem_value *ucontrol)
  2075. {
  2076. struct snd_soc_component *component =
  2077. snd_soc_kcontrol_component(kcontrol);
  2078. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2079. int value = ucontrol->value.integer.value[0];
  2080. bool hphr;
  2081. struct soc_multi_mixer_control *mc;
  2082. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2083. hphr = mc->shift;
  2084. if (hphr)
  2085. wcd938x->comp2_enable = value;
  2086. else
  2087. wcd938x->comp1_enable = value;
  2088. return 0;
  2089. }
  2090. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2091. struct snd_ctl_elem_value *ucontrol)
  2092. {
  2093. struct snd_soc_component *component =
  2094. snd_soc_kcontrol_component(kcontrol);
  2095. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2096. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2097. return 0;
  2098. }
  2099. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2100. struct snd_ctl_elem_value *ucontrol)
  2101. {
  2102. struct snd_soc_component *component =
  2103. snd_soc_kcontrol_component(kcontrol);
  2104. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2105. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2106. return 0;
  2107. }
  2108. const char * const tx_master_ch_text[] = {
  2109. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2110. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2111. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2112. "SWRM_PCM_IN",
  2113. };
  2114. const struct soc_enum tx_master_ch_enum =
  2115. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2116. tx_master_ch_text);
  2117. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2118. {
  2119. u8 ch_type = 0;
  2120. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2121. ch_type = ADC1;
  2122. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2123. ch_type = ADC2;
  2124. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2125. ch_type = ADC3;
  2126. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2127. ch_type = ADC4;
  2128. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2129. ch_type = DMIC0;
  2130. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2131. ch_type = DMIC1;
  2132. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2133. ch_type = MBHC;
  2134. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2135. ch_type = DMIC2;
  2136. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2137. ch_type = DMIC3;
  2138. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2139. ch_type = DMIC4;
  2140. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2141. ch_type = DMIC5;
  2142. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2143. ch_type = DMIC6;
  2144. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2145. ch_type = DMIC7;
  2146. else
  2147. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2148. if (ch_type)
  2149. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2150. else
  2151. *ch_idx = -EINVAL;
  2152. }
  2153. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2154. struct snd_ctl_elem_value *ucontrol)
  2155. {
  2156. struct snd_soc_component *component =
  2157. snd_soc_kcontrol_component(kcontrol);
  2158. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2159. int slave_ch_idx;
  2160. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2161. if (slave_ch_idx != -EINVAL)
  2162. ucontrol->value.integer.value[0] =
  2163. wcd938x_slave_get_master_ch_val(
  2164. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2165. return 0;
  2166. }
  2167. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2168. struct snd_ctl_elem_value *ucontrol)
  2169. {
  2170. struct snd_soc_component *component =
  2171. snd_soc_kcontrol_component(kcontrol);
  2172. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2173. int slave_ch_idx;
  2174. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2175. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2176. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2177. __func__, ucontrol->value.enumerated.item[0]);
  2178. if (slave_ch_idx != -EINVAL)
  2179. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2180. wcd938x_slave_get_master_ch(
  2181. ucontrol->value.enumerated.item[0]);
  2182. return 0;
  2183. }
  2184. static const char * const tx_mode_mux_text_wcd9380[] = {
  2185. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2186. };
  2187. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2188. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2189. tx_mode_mux_text_wcd9380);
  2190. static const char * const tx_mode_mux_text[] = {
  2191. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2192. "ADC_ULP1", "ADC_ULP2",
  2193. };
  2194. static const struct soc_enum tx_mode_mux_enum =
  2195. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2196. tx_mode_mux_text);
  2197. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2198. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2199. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2200. "CLS_AB_LOHIFI",
  2201. };
  2202. static const char * const wcd938x_ear_pa_gain_text[] = {
  2203. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2204. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2205. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2206. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2207. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2208. };
  2209. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2210. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2211. rx_hph_mode_mux_text_wcd9380);
  2212. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2213. wcd938x_ear_pa_gain_text);
  2214. static const char * const rx_hph_mode_mux_text[] = {
  2215. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2216. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2217. };
  2218. static const struct soc_enum rx_hph_mode_mux_enum =
  2219. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2220. rx_hph_mode_mux_text);
  2221. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2222. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2223. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2224. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2225. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2226. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2227. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2228. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2229. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2230. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2231. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2232. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2233. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2234. };
  2235. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2236. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2237. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2238. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2239. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2240. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2241. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2242. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2243. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2244. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2245. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2246. };
  2247. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2248. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2249. wcd938x_get_compander, wcd938x_set_compander),
  2250. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2251. wcd938x_get_compander, wcd938x_set_compander),
  2252. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2253. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2254. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2255. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2256. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2257. analog_gain),
  2258. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2259. analog_gain),
  2260. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2261. analog_gain),
  2262. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2263. analog_gain),
  2264. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2265. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2266. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2267. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2268. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2269. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2270. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2271. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2272. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2273. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2274. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2275. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2276. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2277. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2278. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2279. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2280. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2281. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2282. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2283. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2284. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2285. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2286. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2287. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2288. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2289. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2290. };
  2291. static const struct snd_kcontrol_new adc1_switch[] = {
  2292. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2293. };
  2294. static const struct snd_kcontrol_new adc2_switch[] = {
  2295. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2296. };
  2297. static const struct snd_kcontrol_new adc3_switch[] = {
  2298. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2299. };
  2300. static const struct snd_kcontrol_new adc4_switch[] = {
  2301. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2302. };
  2303. static const struct snd_kcontrol_new dmic1_switch[] = {
  2304. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2305. };
  2306. static const struct snd_kcontrol_new dmic2_switch[] = {
  2307. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2308. };
  2309. static const struct snd_kcontrol_new dmic3_switch[] = {
  2310. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2311. };
  2312. static const struct snd_kcontrol_new dmic4_switch[] = {
  2313. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2314. };
  2315. static const struct snd_kcontrol_new dmic5_switch[] = {
  2316. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2317. };
  2318. static const struct snd_kcontrol_new dmic6_switch[] = {
  2319. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2320. };
  2321. static const struct snd_kcontrol_new dmic7_switch[] = {
  2322. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2323. };
  2324. static const struct snd_kcontrol_new dmic8_switch[] = {
  2325. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2326. };
  2327. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2328. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2329. };
  2330. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2331. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2332. };
  2333. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2334. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2335. };
  2336. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2337. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2338. };
  2339. static const char * const adc2_mux_text[] = {
  2340. "INP2", "INP3"
  2341. };
  2342. static const struct soc_enum adc2_enum =
  2343. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2344. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2345. static const struct snd_kcontrol_new tx_adc2_mux =
  2346. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2347. static const char * const adc3_mux_text[] = {
  2348. "INP4", "INP6"
  2349. };
  2350. static const struct soc_enum adc3_enum =
  2351. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2352. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2353. static const struct snd_kcontrol_new tx_adc3_mux =
  2354. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2355. static const char * const adc4_mux_text[] = {
  2356. "INP5", "INP7"
  2357. };
  2358. static const struct soc_enum adc4_enum =
  2359. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2360. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2361. static const struct snd_kcontrol_new tx_adc4_mux =
  2362. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2363. static const char * const rdac3_mux_text[] = {
  2364. "RX1", "RX3"
  2365. };
  2366. static const char * const hdr12_mux_text[] = {
  2367. "NO_HDR12", "HDR12"
  2368. };
  2369. static const struct soc_enum hdr12_enum =
  2370. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2371. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2372. static const struct snd_kcontrol_new tx_hdr12_mux =
  2373. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2374. static const char * const hdr34_mux_text[] = {
  2375. "NO_HDR34", "HDR34"
  2376. };
  2377. static const struct soc_enum hdr34_enum =
  2378. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2379. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2380. static const struct snd_kcontrol_new tx_hdr34_mux =
  2381. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2382. static const struct soc_enum rdac3_enum =
  2383. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2384. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2385. static const struct snd_kcontrol_new rx_rdac3_mux =
  2386. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2387. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2388. /*input widgets*/
  2389. SND_SOC_DAPM_INPUT("AMIC1"),
  2390. SND_SOC_DAPM_INPUT("AMIC2"),
  2391. SND_SOC_DAPM_INPUT("AMIC3"),
  2392. SND_SOC_DAPM_INPUT("AMIC4"),
  2393. SND_SOC_DAPM_INPUT("AMIC5"),
  2394. SND_SOC_DAPM_INPUT("AMIC6"),
  2395. SND_SOC_DAPM_INPUT("AMIC7"),
  2396. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2397. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2398. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2399. /*tx widgets*/
  2400. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2401. wcd938x_codec_enable_adc,
  2402. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2403. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2404. wcd938x_codec_enable_adc,
  2405. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2406. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2407. wcd938x_codec_enable_adc,
  2408. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2409. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2410. wcd938x_codec_enable_adc,
  2411. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2412. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2413. wcd938x_codec_enable_dmic,
  2414. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2415. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2416. wcd938x_codec_enable_dmic,
  2417. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2418. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2419. wcd938x_codec_enable_dmic,
  2420. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2421. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2422. wcd938x_codec_enable_dmic,
  2423. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2424. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2425. wcd938x_codec_enable_dmic,
  2426. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2427. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2428. wcd938x_codec_enable_dmic,
  2429. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2430. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2431. wcd938x_codec_enable_dmic,
  2432. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2433. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2434. wcd938x_codec_enable_dmic,
  2435. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2436. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2437. NULL, 0, wcd938x_enable_req,
  2438. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2439. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2440. NULL, 0, wcd938x_enable_req,
  2441. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2442. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2443. NULL, 0, wcd938x_enable_req,
  2444. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2445. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2446. NULL, 0, wcd938x_enable_req,
  2447. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2448. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2449. &tx_adc2_mux),
  2450. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2451. &tx_adc3_mux),
  2452. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2453. &tx_adc4_mux),
  2454. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2455. &tx_hdr12_mux),
  2456. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2457. &tx_hdr34_mux),
  2458. /*tx mixers*/
  2459. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2460. adc1_switch, ARRAY_SIZE(adc1_switch),
  2461. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2462. SND_SOC_DAPM_POST_PMD),
  2463. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2464. adc2_switch, ARRAY_SIZE(adc2_switch),
  2465. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2466. SND_SOC_DAPM_POST_PMD),
  2467. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2468. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2469. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2470. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2471. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2472. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2473. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2474. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2475. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2476. SND_SOC_DAPM_POST_PMD),
  2477. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2478. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2479. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2480. SND_SOC_DAPM_POST_PMD),
  2481. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2482. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2483. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2484. SND_SOC_DAPM_POST_PMD),
  2485. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2486. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2487. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2488. SND_SOC_DAPM_POST_PMD),
  2489. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2490. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2491. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2492. SND_SOC_DAPM_POST_PMD),
  2493. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2494. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2495. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2496. SND_SOC_DAPM_POST_PMD),
  2497. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2498. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2499. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2500. SND_SOC_DAPM_POST_PMD),
  2501. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2502. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2503. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2504. SND_SOC_DAPM_POST_PMD),
  2505. /* micbias widgets*/
  2506. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2507. wcd938x_codec_enable_micbias,
  2508. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2509. SND_SOC_DAPM_POST_PMD),
  2510. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2511. wcd938x_codec_enable_micbias,
  2512. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2513. SND_SOC_DAPM_POST_PMD),
  2514. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2515. wcd938x_codec_enable_micbias,
  2516. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2517. SND_SOC_DAPM_POST_PMD),
  2518. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2519. wcd938x_codec_enable_micbias,
  2520. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2521. SND_SOC_DAPM_POST_PMD),
  2522. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2523. wcd938x_codec_force_enable_micbias,
  2524. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2525. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2526. wcd938x_codec_force_enable_micbias,
  2527. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2528. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2529. wcd938x_codec_force_enable_micbias,
  2530. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2531. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2532. wcd938x_codec_force_enable_micbias,
  2533. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2534. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2535. wcd938x_enable_clsh,
  2536. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2537. /*rx widgets*/
  2538. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2539. wcd938x_codec_enable_ear_pa,
  2540. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2541. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2542. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2543. wcd938x_codec_enable_aux_pa,
  2544. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2545. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2546. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2547. wcd938x_codec_enable_hphl_pa,
  2548. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2549. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2550. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2551. wcd938x_codec_enable_hphr_pa,
  2552. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2553. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2554. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2555. wcd938x_codec_hphl_dac_event,
  2556. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2557. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2558. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2559. wcd938x_codec_hphr_dac_event,
  2560. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2561. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2562. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2563. wcd938x_codec_ear_dac_event,
  2564. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2565. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2566. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2567. wcd938x_codec_aux_dac_event,
  2568. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2569. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2570. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2571. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2572. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2573. SND_SOC_DAPM_POST_PMD),
  2574. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2575. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2576. SND_SOC_DAPM_POST_PMD),
  2577. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2578. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2579. SND_SOC_DAPM_POST_PMD),
  2580. /* rx mixer widgets*/
  2581. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2582. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2583. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2584. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2585. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2586. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2587. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2588. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2589. /*output widgets tx*/
  2590. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2591. /*output widgets rx*/
  2592. SND_SOC_DAPM_OUTPUT("EAR"),
  2593. SND_SOC_DAPM_OUTPUT("AUX"),
  2594. SND_SOC_DAPM_OUTPUT("HPHL"),
  2595. SND_SOC_DAPM_OUTPUT("HPHR"),
  2596. /* micbias pull up widgets*/
  2597. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2598. wcd938x_codec_enable_micbias_pullup,
  2599. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2600. SND_SOC_DAPM_POST_PMD),
  2601. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2602. wcd938x_codec_enable_micbias_pullup,
  2603. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2604. SND_SOC_DAPM_POST_PMD),
  2605. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2606. wcd938x_codec_enable_micbias_pullup,
  2607. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2608. SND_SOC_DAPM_POST_PMD),
  2609. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2610. wcd938x_codec_enable_micbias_pullup,
  2611. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2612. SND_SOC_DAPM_POST_PMD),
  2613. };
  2614. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2615. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2616. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2617. {"ADC1 REQ", NULL, "ADC1"},
  2618. {"ADC1", NULL, "AMIC1"},
  2619. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2620. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2621. {"ADC2 REQ", NULL, "ADC2"},
  2622. {"ADC2", NULL, "HDR12 MUX"},
  2623. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2624. {"HDR12 MUX", "HDR12", "AMIC1"},
  2625. {"ADC2 MUX", "INP3", "AMIC3"},
  2626. {"ADC2 MUX", "INP2", "AMIC2"},
  2627. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2628. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2629. {"ADC3 REQ", NULL, "ADC3"},
  2630. {"ADC3", NULL, "HDR34 MUX"},
  2631. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2632. {"HDR34 MUX", "HDR34", "AMIC5"},
  2633. {"ADC3 MUX", "INP4", "AMIC4"},
  2634. {"ADC3 MUX", "INP6", "AMIC6"},
  2635. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  2636. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2637. {"ADC4 REQ", NULL, "ADC4"},
  2638. {"ADC4", NULL, "ADC4 MUX"},
  2639. {"ADC4 MUX", "INP5", "AMIC5"},
  2640. {"ADC4 MUX", "INP7", "AMIC7"},
  2641. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2642. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2643. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2644. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2645. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2646. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2647. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2648. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2649. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2650. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2651. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2652. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2653. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  2654. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2655. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  2656. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2657. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2658. {"RX1", NULL, "IN1_HPHL"},
  2659. {"RDAC1", NULL, "RX1"},
  2660. {"HPHL_RDAC", "Switch", "RDAC1"},
  2661. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2662. {"HPHL", NULL, "HPHL PGA"},
  2663. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2664. {"RX2", NULL, "IN2_HPHR"},
  2665. {"RDAC2", NULL, "RX2"},
  2666. {"HPHR_RDAC", "Switch", "RDAC2"},
  2667. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2668. {"HPHR", NULL, "HPHR PGA"},
  2669. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2670. {"RX3", NULL, "IN3_AUX"},
  2671. {"RDAC4", NULL, "RX3"},
  2672. {"AUX_RDAC", "Switch", "RDAC4"},
  2673. {"AUX PGA", NULL, "AUX_RDAC"},
  2674. {"AUX", NULL, "AUX PGA"},
  2675. {"RDAC3_MUX", "RX3", "RX3"},
  2676. {"RDAC3_MUX", "RX1", "RX1"},
  2677. {"RDAC3", NULL, "RDAC3_MUX"},
  2678. {"EAR_RDAC", "Switch", "RDAC3"},
  2679. {"EAR PGA", NULL, "EAR_RDAC"},
  2680. {"EAR", NULL, "EAR PGA"},
  2681. };
  2682. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2683. void *file_private_data,
  2684. struct file *file,
  2685. char __user *buf, size_t count,
  2686. loff_t pos)
  2687. {
  2688. struct wcd938x_priv *priv;
  2689. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2690. int len = 0;
  2691. priv = (struct wcd938x_priv *) entry->private_data;
  2692. if (!priv) {
  2693. pr_err("%s: wcd938x priv is null\n", __func__);
  2694. return -EINVAL;
  2695. }
  2696. switch (priv->version) {
  2697. case WCD938X_VERSION_1_0:
  2698. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2699. break;
  2700. default:
  2701. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2702. }
  2703. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2704. }
  2705. static struct snd_info_entry_ops wcd938x_info_ops = {
  2706. .read = wcd938x_version_read,
  2707. };
  2708. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2709. void *file_private_data,
  2710. struct file *file,
  2711. char __user *buf, size_t count,
  2712. loff_t pos)
  2713. {
  2714. struct wcd938x_priv *priv;
  2715. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2716. int len = 0;
  2717. priv = (struct wcd938x_priv *) entry->private_data;
  2718. if (!priv) {
  2719. pr_err("%s: wcd938x priv is null\n", __func__);
  2720. return -EINVAL;
  2721. }
  2722. switch (priv->variant) {
  2723. case WCD9380:
  2724. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2725. break;
  2726. case WCD9385:
  2727. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2728. break;
  2729. default:
  2730. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2731. }
  2732. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2733. }
  2734. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2735. .read = wcd938x_variant_read,
  2736. };
  2737. /*
  2738. * wcd938x_get_codec_variant
  2739. * @component: component instance
  2740. *
  2741. * Return: codec variant or -EINVAL in error.
  2742. */
  2743. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  2744. {
  2745. struct wcd938x_priv *priv = NULL;
  2746. if (!component)
  2747. return -EINVAL;
  2748. priv = snd_soc_component_get_drvdata(component);
  2749. if (!priv) {
  2750. dev_err(component->dev,
  2751. "%s:wcd938x not probed\n", __func__);
  2752. return 0;
  2753. }
  2754. return priv->variant;
  2755. }
  2756. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  2757. /*
  2758. * wcd938x_info_create_codec_entry - creates wcd938x module
  2759. * @codec_root: The parent directory
  2760. * @component: component instance
  2761. *
  2762. * Creates wcd938x module, variant and version entry under the given
  2763. * parent directory.
  2764. *
  2765. * Return: 0 on success or negative error code on failure.
  2766. */
  2767. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2768. struct snd_soc_component *component)
  2769. {
  2770. struct snd_info_entry *version_entry;
  2771. struct snd_info_entry *variant_entry;
  2772. struct wcd938x_priv *priv;
  2773. struct snd_soc_card *card;
  2774. if (!codec_root || !component)
  2775. return -EINVAL;
  2776. priv = snd_soc_component_get_drvdata(component);
  2777. if (priv->entry) {
  2778. dev_dbg(priv->dev,
  2779. "%s:wcd938x module already created\n", __func__);
  2780. return 0;
  2781. }
  2782. card = component->card;
  2783. priv->entry = snd_info_create_module_entry(codec_root->module,
  2784. "wcd938x", codec_root);
  2785. if (!priv->entry) {
  2786. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2787. __func__);
  2788. return -ENOMEM;
  2789. }
  2790. priv->entry->mode = S_IFDIR | 0555;
  2791. if (snd_info_register(priv->entry) < 0) {
  2792. snd_info_free_entry(priv->entry);
  2793. return -ENOMEM;
  2794. }
  2795. version_entry = snd_info_create_card_entry(card->snd_card,
  2796. "version",
  2797. priv->entry);
  2798. if (!version_entry) {
  2799. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2800. __func__);
  2801. snd_info_free_entry(priv->entry);
  2802. return -ENOMEM;
  2803. }
  2804. version_entry->private_data = priv;
  2805. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2806. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2807. version_entry->c.ops = &wcd938x_info_ops;
  2808. if (snd_info_register(version_entry) < 0) {
  2809. snd_info_free_entry(version_entry);
  2810. snd_info_free_entry(priv->entry);
  2811. return -ENOMEM;
  2812. }
  2813. priv->version_entry = version_entry;
  2814. variant_entry = snd_info_create_card_entry(card->snd_card,
  2815. "variant",
  2816. priv->entry);
  2817. if (!variant_entry) {
  2818. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  2819. __func__);
  2820. snd_info_free_entry(version_entry);
  2821. snd_info_free_entry(priv->entry);
  2822. return -ENOMEM;
  2823. }
  2824. variant_entry->private_data = priv;
  2825. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  2826. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2827. variant_entry->c.ops = &wcd938x_variant_ops;
  2828. if (snd_info_register(variant_entry) < 0) {
  2829. snd_info_free_entry(variant_entry);
  2830. snd_info_free_entry(version_entry);
  2831. snd_info_free_entry(priv->entry);
  2832. return -ENOMEM;
  2833. }
  2834. priv->variant_entry = variant_entry;
  2835. return 0;
  2836. }
  2837. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2838. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  2839. struct wcd938x_pdata *pdata)
  2840. {
  2841. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  2842. int rc = 0;
  2843. if (!pdata) {
  2844. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  2845. return -ENODEV;
  2846. }
  2847. /* set micbias voltage */
  2848. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2849. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2850. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2851. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  2852. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  2853. vout_ctl_4 < 0) {
  2854. rc = -EINVAL;
  2855. goto done;
  2856. }
  2857. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  2858. vout_ctl_1);
  2859. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  2860. vout_ctl_2);
  2861. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  2862. vout_ctl_3);
  2863. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  2864. vout_ctl_4);
  2865. done:
  2866. return rc;
  2867. }
  2868. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2869. {
  2870. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2871. struct snd_soc_dapm_context *dapm =
  2872. snd_soc_component_get_dapm(component);
  2873. int variant;
  2874. int ret = -EINVAL;
  2875. dev_info(component->dev, "%s()\n", __func__);
  2876. wcd938x = snd_soc_component_get_drvdata(component);
  2877. if (!wcd938x)
  2878. return -EINVAL;
  2879. wcd938x->component = component;
  2880. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2881. variant = (snd_soc_component_read32(component,
  2882. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2883. wcd938x->variant = variant;
  2884. wcd938x->fw_data = devm_kzalloc(component->dev,
  2885. sizeof(*(wcd938x->fw_data)),
  2886. GFP_KERNEL);
  2887. if (!wcd938x->fw_data) {
  2888. dev_err(component->dev, "Failed to allocate fw_data\n");
  2889. ret = -ENOMEM;
  2890. goto err;
  2891. }
  2892. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2893. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2894. WCD9XXX_CODEC_HWDEP_NODE, component);
  2895. if (ret < 0) {
  2896. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2897. goto err_hwdep;
  2898. }
  2899. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2900. if (ret) {
  2901. pr_err("%s: mbhc initialization failed\n", __func__);
  2902. goto err_hwdep;
  2903. }
  2904. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2905. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2906. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2907. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2908. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2909. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2910. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2911. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2912. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2913. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2914. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2915. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2916. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2917. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2918. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2919. snd_soc_dapm_sync(dapm);
  2920. wcd_cls_h_init(&wcd938x->clsh_info);
  2921. wcd938x_init_reg(component);
  2922. if (wcd938x->variant == WCD9380) {
  2923. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  2924. ARRAY_SIZE(wcd9380_snd_controls));
  2925. if (ret < 0) {
  2926. dev_err(component->dev,
  2927. "%s: Failed to add snd ctrls for variant: %d\n",
  2928. __func__, wcd938x->variant);
  2929. goto err_hwdep;
  2930. }
  2931. }
  2932. if (wcd938x->variant == WCD9385) {
  2933. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  2934. ARRAY_SIZE(wcd9385_snd_controls));
  2935. if (ret < 0) {
  2936. dev_err(component->dev,
  2937. "%s: Failed to add snd ctrls for variant: %d\n",
  2938. __func__, wcd938x->variant);
  2939. goto err_hwdep;
  2940. }
  2941. }
  2942. wcd938x->version = WCD938X_VERSION_1_0;
  2943. /* Register event notifier */
  2944. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2945. if (wcd938x->register_notifier) {
  2946. ret = wcd938x->register_notifier(wcd938x->handle,
  2947. &wcd938x->nblock,
  2948. true);
  2949. if (ret) {
  2950. dev_err(component->dev,
  2951. "%s: Failed to register notifier %d\n",
  2952. __func__, ret);
  2953. return ret;
  2954. }
  2955. }
  2956. wcd938x->dev_up = true;
  2957. return ret;
  2958. err_hwdep:
  2959. wcd938x->fw_data = NULL;
  2960. err:
  2961. return ret;
  2962. }
  2963. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2964. {
  2965. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2966. if (!wcd938x) {
  2967. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2968. __func__);
  2969. return;
  2970. }
  2971. if (wcd938x->register_notifier)
  2972. wcd938x->register_notifier(wcd938x->handle,
  2973. &wcd938x->nblock,
  2974. false);
  2975. }
  2976. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2977. .name = WCD938X_DRV_NAME,
  2978. .probe = wcd938x_soc_codec_probe,
  2979. .remove = wcd938x_soc_codec_remove,
  2980. .controls = wcd938x_snd_controls,
  2981. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2982. .dapm_widgets = wcd938x_dapm_widgets,
  2983. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2984. .dapm_routes = wcd938x_audio_map,
  2985. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2986. };
  2987. static int wcd938x_reset(struct device *dev)
  2988. {
  2989. struct wcd938x_priv *wcd938x = NULL;
  2990. int rc = 0;
  2991. int value = 0;
  2992. if (!dev)
  2993. return -ENODEV;
  2994. wcd938x = dev_get_drvdata(dev);
  2995. if (!wcd938x)
  2996. return -EINVAL;
  2997. if (!wcd938x->rst_np) {
  2998. dev_err(dev, "%s: reset gpio device node not specified\n",
  2999. __func__);
  3000. return -EINVAL;
  3001. }
  3002. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3003. if (value > 0)
  3004. return 0;
  3005. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3006. if (rc) {
  3007. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3008. __func__);
  3009. return rc;
  3010. }
  3011. /* 20us sleep required after pulling the reset gpio to LOW */
  3012. usleep_range(20, 30);
  3013. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3014. if (rc) {
  3015. dev_err(dev, "%s: wcd active state request fail!\n",
  3016. __func__);
  3017. return rc;
  3018. }
  3019. /* 20us sleep required after pulling the reset gpio to HIGH */
  3020. usleep_range(20, 30);
  3021. return rc;
  3022. }
  3023. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3024. u32 *val)
  3025. {
  3026. int rc = 0;
  3027. rc = of_property_read_u32(dev->of_node, name, val);
  3028. if (rc)
  3029. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3030. __func__, name, dev->of_node->full_name);
  3031. return rc;
  3032. }
  3033. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3034. struct wcd938x_micbias_setting *mb)
  3035. {
  3036. u32 prop_val = 0;
  3037. int rc = 0;
  3038. /* MB1 */
  3039. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3040. NULL)) {
  3041. rc = wcd938x_read_of_property_u32(dev,
  3042. "qcom,cdc-micbias1-mv",
  3043. &prop_val);
  3044. if (!rc)
  3045. mb->micb1_mv = prop_val;
  3046. } else {
  3047. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3048. __func__);
  3049. }
  3050. /* MB2 */
  3051. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3052. NULL)) {
  3053. rc = wcd938x_read_of_property_u32(dev,
  3054. "qcom,cdc-micbias2-mv",
  3055. &prop_val);
  3056. if (!rc)
  3057. mb->micb2_mv = prop_val;
  3058. } else {
  3059. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3060. __func__);
  3061. }
  3062. /* MB3 */
  3063. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3064. NULL)) {
  3065. rc = wcd938x_read_of_property_u32(dev,
  3066. "qcom,cdc-micbias3-mv",
  3067. &prop_val);
  3068. if (!rc)
  3069. mb->micb3_mv = prop_val;
  3070. } else {
  3071. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3072. __func__);
  3073. }
  3074. /* MB4 */
  3075. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3076. NULL)) {
  3077. rc = wcd938x_read_of_property_u32(dev,
  3078. "qcom,cdc-micbias4-mv",
  3079. &prop_val);
  3080. if (!rc)
  3081. mb->micb4_mv = prop_val;
  3082. } else {
  3083. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3084. __func__);
  3085. }
  3086. }
  3087. static int wcd938x_reset_low(struct device *dev)
  3088. {
  3089. struct wcd938x_priv *wcd938x = NULL;
  3090. int rc = 0;
  3091. if (!dev)
  3092. return -ENODEV;
  3093. wcd938x = dev_get_drvdata(dev);
  3094. if (!wcd938x)
  3095. return -EINVAL;
  3096. if (!wcd938x->rst_np) {
  3097. dev_err(dev, "%s: reset gpio device node not specified\n",
  3098. __func__);
  3099. return -EINVAL;
  3100. }
  3101. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3102. if (rc) {
  3103. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3104. __func__);
  3105. return rc;
  3106. }
  3107. /* 20us sleep required after pulling the reset gpio to LOW */
  3108. usleep_range(20, 30);
  3109. return rc;
  3110. }
  3111. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3112. {
  3113. struct wcd938x_pdata *pdata = NULL;
  3114. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3115. GFP_KERNEL);
  3116. if (!pdata)
  3117. return NULL;
  3118. pdata->rst_np = of_parse_phandle(dev->of_node,
  3119. "qcom,wcd-rst-gpio-node", 0);
  3120. if (!pdata->rst_np) {
  3121. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3122. __func__, "qcom,wcd-rst-gpio-node",
  3123. dev->of_node->full_name);
  3124. return NULL;
  3125. }
  3126. /* Parse power supplies */
  3127. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3128. &pdata->num_supplies);
  3129. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3130. dev_err(dev, "%s: no power supplies defined for codec\n",
  3131. __func__);
  3132. return NULL;
  3133. }
  3134. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3135. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3136. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3137. return pdata;
  3138. }
  3139. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3140. {
  3141. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3142. __func__, irq);
  3143. return IRQ_HANDLED;
  3144. }
  3145. static int wcd938x_bind(struct device *dev)
  3146. {
  3147. int ret = 0, i = 0;
  3148. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3149. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3150. /*
  3151. * Add 5msec delay to provide sufficient time for
  3152. * soundwire auto enumeration of slave devices as
  3153. * as per HW requirement.
  3154. */
  3155. usleep_range(5000, 5010);
  3156. ret = component_bind_all(dev, wcd938x);
  3157. if (ret) {
  3158. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3159. __func__, ret);
  3160. return ret;
  3161. }
  3162. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3163. if (!wcd938x->rx_swr_dev) {
  3164. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3165. __func__);
  3166. ret = -ENODEV;
  3167. goto err;
  3168. }
  3169. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3170. if (!wcd938x->tx_swr_dev) {
  3171. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3172. __func__);
  3173. ret = -ENODEV;
  3174. goto err;
  3175. }
  3176. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3177. &wcd938x_regmap_config);
  3178. if (!wcd938x->regmap) {
  3179. dev_err(dev, "%s: Regmap init failed\n",
  3180. __func__);
  3181. goto err;
  3182. }
  3183. /* Set all interupts as edge triggered */
  3184. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3185. regmap_write(wcd938x->regmap,
  3186. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3187. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3188. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3189. wcd938x->irq_info.codec_name = "WCD938X";
  3190. wcd938x->irq_info.regmap = wcd938x->regmap;
  3191. wcd938x->irq_info.dev = dev;
  3192. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3193. if (ret) {
  3194. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3195. __func__, ret);
  3196. goto err;
  3197. }
  3198. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3199. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3200. if (ret < 0) {
  3201. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3202. goto err_irq;
  3203. }
  3204. /* Request for watchdog interrupt */
  3205. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3206. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3207. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3208. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3209. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3210. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3211. /* Disable watchdog interrupt for HPH and AUX */
  3212. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3213. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3214. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3215. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3216. NULL, 0);
  3217. if (ret) {
  3218. dev_err(dev, "%s: Codec registration failed\n",
  3219. __func__);
  3220. goto err_irq;
  3221. }
  3222. return ret;
  3223. err_irq:
  3224. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3225. err:
  3226. component_unbind_all(dev, wcd938x);
  3227. return ret;
  3228. }
  3229. static void wcd938x_unbind(struct device *dev)
  3230. {
  3231. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3232. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3233. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3234. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3235. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3236. snd_soc_unregister_component(dev);
  3237. component_unbind_all(dev, wcd938x);
  3238. }
  3239. static const struct of_device_id wcd938x_dt_match[] = {
  3240. { .compatible = "qcom,wcd938x-codec" },
  3241. {}
  3242. };
  3243. static const struct component_master_ops wcd938x_comp_ops = {
  3244. .bind = wcd938x_bind,
  3245. .unbind = wcd938x_unbind,
  3246. };
  3247. static int wcd938x_compare_of(struct device *dev, void *data)
  3248. {
  3249. return dev->of_node == data;
  3250. }
  3251. static void wcd938x_release_of(struct device *dev, void *data)
  3252. {
  3253. of_node_put(data);
  3254. }
  3255. static int wcd938x_add_slave_components(struct device *dev,
  3256. struct component_match **matchptr)
  3257. {
  3258. struct device_node *np, *rx_node, *tx_node;
  3259. np = dev->of_node;
  3260. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3261. if (!rx_node) {
  3262. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3263. return -ENODEV;
  3264. }
  3265. of_node_get(rx_node);
  3266. component_match_add_release(dev, matchptr,
  3267. wcd938x_release_of,
  3268. wcd938x_compare_of,
  3269. rx_node);
  3270. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3271. if (!tx_node) {
  3272. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3273. return -ENODEV;
  3274. }
  3275. of_node_get(tx_node);
  3276. component_match_add_release(dev, matchptr,
  3277. wcd938x_release_of,
  3278. wcd938x_compare_of,
  3279. tx_node);
  3280. return 0;
  3281. }
  3282. static int wcd938x_probe(struct platform_device *pdev)
  3283. {
  3284. struct component_match *match = NULL;
  3285. struct wcd938x_priv *wcd938x = NULL;
  3286. struct wcd938x_pdata *pdata = NULL;
  3287. struct wcd_ctrl_platform_data *plat_data = NULL;
  3288. struct device *dev = &pdev->dev;
  3289. int ret;
  3290. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3291. GFP_KERNEL);
  3292. if (!wcd938x)
  3293. return -ENOMEM;
  3294. dev_set_drvdata(dev, wcd938x);
  3295. wcd938x->dev = dev;
  3296. pdata = wcd938x_populate_dt_data(dev);
  3297. if (!pdata) {
  3298. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3299. return -EINVAL;
  3300. }
  3301. dev->platform_data = pdata;
  3302. wcd938x->rst_np = pdata->rst_np;
  3303. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3304. pdata->regulator, pdata->num_supplies);
  3305. if (!wcd938x->supplies) {
  3306. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3307. __func__);
  3308. return ret;
  3309. }
  3310. plat_data = dev_get_platdata(dev->parent);
  3311. if (!plat_data) {
  3312. dev_err(dev, "%s: platform data from parent is NULL\n",
  3313. __func__);
  3314. return -EINVAL;
  3315. }
  3316. wcd938x->handle = (void *)plat_data->handle;
  3317. if (!wcd938x->handle) {
  3318. dev_err(dev, "%s: handle is NULL\n", __func__);
  3319. return -EINVAL;
  3320. }
  3321. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3322. if (!wcd938x->update_wcd_event) {
  3323. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3324. __func__);
  3325. return -EINVAL;
  3326. }
  3327. wcd938x->register_notifier = plat_data->register_notifier;
  3328. if (!wcd938x->register_notifier) {
  3329. dev_err(dev, "%s: register_notifier api is null!\n",
  3330. __func__);
  3331. return -EINVAL;
  3332. }
  3333. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3334. pdata->regulator,
  3335. pdata->num_supplies);
  3336. if (ret) {
  3337. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3338. __func__);
  3339. return ret;
  3340. }
  3341. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3342. CODEC_RX);
  3343. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3344. CODEC_TX);
  3345. if (ret) {
  3346. dev_err(dev, "Failed to read port mapping\n");
  3347. goto err;
  3348. }
  3349. mutex_init(&wcd938x->wakeup_lock);
  3350. mutex_init(&wcd938x->micb_lock);
  3351. ret = wcd938x_add_slave_components(dev, &match);
  3352. if (ret)
  3353. goto err_lock_init;
  3354. wcd938x_reset(dev);
  3355. wcd938x->wakeup = wcd938x_wakeup;
  3356. return component_master_add_with_match(dev,
  3357. &wcd938x_comp_ops, match);
  3358. err_lock_init:
  3359. mutex_destroy(&wcd938x->micb_lock);
  3360. mutex_destroy(&wcd938x->wakeup_lock);
  3361. err:
  3362. return ret;
  3363. }
  3364. static int wcd938x_remove(struct platform_device *pdev)
  3365. {
  3366. struct wcd938x_priv *wcd938x = NULL;
  3367. wcd938x = platform_get_drvdata(pdev);
  3368. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3369. mutex_destroy(&wcd938x->micb_lock);
  3370. mutex_destroy(&wcd938x->wakeup_lock);
  3371. dev_set_drvdata(&pdev->dev, NULL);
  3372. return 0;
  3373. }
  3374. #ifdef CONFIG_PM_SLEEP
  3375. static int wcd938x_suspend(struct device *dev)
  3376. {
  3377. return 0;
  3378. }
  3379. static int wcd938x_resume(struct device *dev)
  3380. {
  3381. return 0;
  3382. }
  3383. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3384. SET_SYSTEM_SLEEP_PM_OPS(
  3385. wcd938x_suspend,
  3386. wcd938x_resume
  3387. )
  3388. };
  3389. #endif
  3390. static struct platform_driver wcd938x_codec_driver = {
  3391. .probe = wcd938x_probe,
  3392. .remove = wcd938x_remove,
  3393. .driver = {
  3394. .name = "wcd938x_codec",
  3395. .owner = THIS_MODULE,
  3396. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3397. #ifdef CONFIG_PM_SLEEP
  3398. .pm = &wcd938x_dev_pm_ops,
  3399. #endif
  3400. .suppress_bind_attrs = true,
  3401. },
  3402. };
  3403. module_platform_driver(wcd938x_codec_driver);
  3404. MODULE_DESCRIPTION("WCD938X Codec driver");
  3405. MODULE_LICENSE("GPL v2");