qmi.c 106 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/soc/qcom/qmi.h>
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "main.h"
  11. #include "qmi.h"
  12. #include "genl.h"
  13. #define WLFW_SERVICE_INS_ID_V01 1
  14. #define WLFW_CLIENT_ID 0x4b4e454c
  15. #define BDF_FILE_NAME_PREFIX "bdwlan"
  16. #define ELF_BDF_FILE_NAME "bdwlan.elf"
  17. #define ELF_BDF_FILE_NAME_GF "bdwlang.elf"
  18. #define ELF_BDF_FILE_NAME_PREFIX "bdwlan.e"
  19. #define ELF_BDF_FILE_NAME_GF_PREFIX "bdwlang.e"
  20. #define BIN_BDF_FILE_NAME "bdwlan.bin"
  21. #define BIN_BDF_FILE_NAME_GF "bdwlang.bin"
  22. #define BIN_BDF_FILE_NAME_PREFIX "bdwlan.b"
  23. #define BIN_BDF_FILE_NAME_GF_PREFIX "bdwlang.b"
  24. #define REGDB_FILE_NAME "regdb.bin"
  25. #define HDS_FILE_NAME "hds.bin"
  26. #define CHIP_ID_GF_MASK 0x10
  27. #define QDSS_TRACE_CONFIG_FILE "qdss_trace_config"
  28. /*
  29. * Download QDSS config file based on build type. Add build type string to
  30. * file name. Download "qdss_trace_config_debug_v<n>.cfg" for debug build
  31. * and "qdss_trace_config_perf_v<n>.cfg" for perf build.
  32. */
  33. #ifdef CONFIG_CNSS2_DEBUG
  34. #define QDSS_FILE_BUILD_STR "debug_"
  35. #else
  36. #define QDSS_FILE_BUILD_STR "perf_"
  37. #endif
  38. #define HW_V1_NUMBER "v1"
  39. #define HW_V2_NUMBER "v2"
  40. #define CE_MSI_NAME "CE"
  41. #define QMI_WLFW_TIMEOUT_MS (plat_priv->ctrl_params.qmi_timeout)
  42. #define QMI_WLFW_TIMEOUT_JF msecs_to_jiffies(QMI_WLFW_TIMEOUT_MS)
  43. #define COEX_TIMEOUT QMI_WLFW_TIMEOUT_JF
  44. #define IMS_TIMEOUT QMI_WLFW_TIMEOUT_JF
  45. #define QMI_WLFW_MAX_RECV_BUF_SIZE SZ_8K
  46. #define IMSPRIVATE_SERVICE_MAX_MSG_LEN SZ_8K
  47. #define DMS_QMI_MAX_MSG_LEN SZ_256
  48. #define MAX_SHADOW_REG_RESERVED 2
  49. #define MAX_NUM_SHADOW_REG_V3 (QMI_WLFW_MAX_NUM_SHADOW_REG_V3_USAGE_V01 - \
  50. MAX_SHADOW_REG_RESERVED)
  51. #define QMI_WLFW_MAC_READY_TIMEOUT_MS 50
  52. #define QMI_WLFW_MAC_READY_MAX_RETRY 200
  53. enum nm_modem_bit {
  54. SLEEP_CLOCK_SELECT_INTERNAL_BIT = BIT(1),
  55. HOST_CSTATE_BIT = BIT(2),
  56. };
  57. #ifdef CONFIG_CNSS2_DEBUG
  58. static bool ignore_qmi_failure;
  59. #define CNSS_QMI_ASSERT() CNSS_ASSERT(ignore_qmi_failure)
  60. void cnss_ignore_qmi_failure(bool ignore)
  61. {
  62. ignore_qmi_failure = ignore;
  63. }
  64. #else
  65. #define CNSS_QMI_ASSERT() do { } while (0)
  66. void cnss_ignore_qmi_failure(bool ignore) { }
  67. #endif
  68. static char *cnss_qmi_mode_to_str(enum cnss_driver_mode mode)
  69. {
  70. switch (mode) {
  71. case CNSS_MISSION:
  72. return "MISSION";
  73. case CNSS_FTM:
  74. return "FTM";
  75. case CNSS_EPPING:
  76. return "EPPING";
  77. case CNSS_WALTEST:
  78. return "WALTEST";
  79. case CNSS_OFF:
  80. return "OFF";
  81. case CNSS_CCPM:
  82. return "CCPM";
  83. case CNSS_QVIT:
  84. return "QVIT";
  85. case CNSS_CALIBRATION:
  86. return "CALIBRATION";
  87. default:
  88. return "UNKNOWN";
  89. }
  90. }
  91. static int qmi_send_wait(struct qmi_handle *qmi, void *req, void *rsp,
  92. struct qmi_elem_info *req_ei,
  93. struct qmi_elem_info *rsp_ei,
  94. int req_id, size_t req_len,
  95. unsigned long timeout)
  96. {
  97. struct qmi_txn txn;
  98. int ret;
  99. char *err_msg;
  100. struct qmi_response_type_v01 *resp = rsp;
  101. ret = qmi_txn_init(qmi, &txn, rsp_ei, rsp);
  102. if (ret < 0) {
  103. err_msg = "Qmi fail: fail to init txn,";
  104. goto out;
  105. }
  106. ret = qmi_send_request(qmi, NULL, &txn, req_id,
  107. req_len, req_ei, req);
  108. if (ret < 0) {
  109. qmi_txn_cancel(&txn);
  110. err_msg = "Qmi fail: fail to send req,";
  111. goto out;
  112. }
  113. ret = qmi_txn_wait(&txn, timeout);
  114. if (ret < 0) {
  115. err_msg = "Qmi fail: wait timeout,";
  116. goto out;
  117. } else if (resp->result != QMI_RESULT_SUCCESS_V01) {
  118. err_msg = "Qmi fail: request rejected,";
  119. cnss_pr_err("Qmi fail: respons with error:%d\n",
  120. resp->error);
  121. ret = -resp->result;
  122. goto out;
  123. }
  124. cnss_pr_dbg("req %x success\n", req_id);
  125. return 0;
  126. out:
  127. cnss_pr_err("%s req %x, ret %d\n", err_msg, req_id, ret);
  128. return ret;
  129. }
  130. static int cnss_wlfw_ind_register_send_sync(struct cnss_plat_data *plat_priv)
  131. {
  132. struct wlfw_ind_register_req_msg_v01 *req;
  133. struct wlfw_ind_register_resp_msg_v01 *resp;
  134. struct qmi_txn txn;
  135. int ret = 0;
  136. cnss_pr_dbg("Sending indication register message, state: 0x%lx\n",
  137. plat_priv->driver_state);
  138. req = kzalloc(sizeof(*req), GFP_KERNEL);
  139. if (!req)
  140. return -ENOMEM;
  141. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  142. if (!resp) {
  143. kfree(req);
  144. return -ENOMEM;
  145. }
  146. req->client_id_valid = 1;
  147. req->client_id = WLFW_CLIENT_ID;
  148. req->request_mem_enable_valid = 1;
  149. req->request_mem_enable = 1;
  150. req->fw_mem_ready_enable_valid = 1;
  151. req->fw_mem_ready_enable = 1;
  152. /* fw_ready indication is replaced by fw_init_done in HST/HSP */
  153. req->fw_init_done_enable_valid = 1;
  154. req->fw_init_done_enable = 1;
  155. req->pin_connect_result_enable_valid = 1;
  156. req->pin_connect_result_enable = 1;
  157. req->cal_done_enable_valid = 1;
  158. req->cal_done_enable = 1;
  159. req->qdss_trace_req_mem_enable_valid = 1;
  160. req->qdss_trace_req_mem_enable = 1;
  161. req->qdss_trace_save_enable_valid = 1;
  162. req->qdss_trace_save_enable = 1;
  163. req->qdss_trace_free_enable_valid = 1;
  164. req->qdss_trace_free_enable = 1;
  165. req->respond_get_info_enable_valid = 1;
  166. req->respond_get_info_enable = 1;
  167. req->wfc_call_twt_config_enable_valid = 1;
  168. req->wfc_call_twt_config_enable = 1;
  169. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  170. wlfw_ind_register_resp_msg_v01_ei, resp);
  171. if (ret < 0) {
  172. cnss_pr_err("Failed to initialize txn for indication register request, err: %d\n",
  173. ret);
  174. goto out;
  175. }
  176. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  177. QMI_WLFW_IND_REGISTER_REQ_V01,
  178. WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN,
  179. wlfw_ind_register_req_msg_v01_ei, req);
  180. if (ret < 0) {
  181. qmi_txn_cancel(&txn);
  182. cnss_pr_err("Failed to send indication register request, err: %d\n",
  183. ret);
  184. goto out;
  185. }
  186. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  187. if (ret < 0) {
  188. cnss_pr_err("Failed to wait for response of indication register request, err: %d\n",
  189. ret);
  190. goto out;
  191. }
  192. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  193. cnss_pr_err("Indication register request failed, result: %d, err: %d\n",
  194. resp->resp.result, resp->resp.error);
  195. ret = -resp->resp.result;
  196. goto out;
  197. }
  198. if (resp->fw_status_valid) {
  199. if (resp->fw_status & QMI_WLFW_ALREADY_REGISTERED_V01) {
  200. ret = -EALREADY;
  201. goto qmi_registered;
  202. }
  203. }
  204. kfree(req);
  205. kfree(resp);
  206. return 0;
  207. out:
  208. CNSS_QMI_ASSERT();
  209. qmi_registered:
  210. kfree(req);
  211. kfree(resp);
  212. return ret;
  213. }
  214. static void cnss_wlfw_host_cap_parse_mlo(struct cnss_plat_data *plat_priv,
  215. struct wlfw_host_cap_req_msg_v01 *req)
  216. {
  217. if (plat_priv->device_id == KIWI_DEVICE_ID ||
  218. plat_priv->device_id == MANGO_DEVICE_ID ||
  219. plat_priv->device_id == PEACH_DEVICE_ID) {
  220. req->mlo_capable_valid = 1;
  221. req->mlo_capable = 1;
  222. req->mlo_chip_id_valid = 1;
  223. req->mlo_chip_id = 0;
  224. req->mlo_group_id_valid = 1;
  225. req->mlo_group_id = 0;
  226. req->max_mlo_peer_valid = 1;
  227. /* Max peer number generally won't change for the same device
  228. * but needs to be synced with host driver.
  229. */
  230. req->max_mlo_peer = 32;
  231. req->mlo_num_chips_valid = 1;
  232. req->mlo_num_chips = 1;
  233. req->mlo_chip_info_valid = 1;
  234. req->mlo_chip_info[0].chip_id = 0;
  235. req->mlo_chip_info[0].num_local_links = 2;
  236. req->mlo_chip_info[0].hw_link_id[0] = 0;
  237. req->mlo_chip_info[0].hw_link_id[1] = 1;
  238. req->mlo_chip_info[0].valid_mlo_link_id[0] = 1;
  239. req->mlo_chip_info[0].valid_mlo_link_id[1] = 1;
  240. }
  241. }
  242. static int cnss_wlfw_host_cap_send_sync(struct cnss_plat_data *plat_priv)
  243. {
  244. struct wlfw_host_cap_req_msg_v01 *req;
  245. struct wlfw_host_cap_resp_msg_v01 *resp;
  246. struct qmi_txn txn;
  247. int ret = 0;
  248. u64 iova_start = 0, iova_size = 0,
  249. iova_ipa_start = 0, iova_ipa_size = 0;
  250. u64 feature_list = 0;
  251. cnss_pr_dbg("Sending host capability message, state: 0x%lx\n",
  252. plat_priv->driver_state);
  253. req = kzalloc(sizeof(*req), GFP_KERNEL);
  254. if (!req)
  255. return -ENOMEM;
  256. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  257. if (!resp) {
  258. kfree(req);
  259. return -ENOMEM;
  260. }
  261. req->num_clients_valid = 1;
  262. req->num_clients = 1;
  263. cnss_pr_dbg("Number of clients is %d\n", req->num_clients);
  264. req->wake_msi = cnss_bus_get_wake_irq(plat_priv);
  265. if (req->wake_msi) {
  266. cnss_pr_dbg("WAKE MSI base data is %d\n", req->wake_msi);
  267. req->wake_msi_valid = 1;
  268. }
  269. req->bdf_support_valid = 1;
  270. req->bdf_support = 1;
  271. req->m3_support_valid = 1;
  272. req->m3_support = 1;
  273. req->m3_cache_support_valid = 1;
  274. req->m3_cache_support = 1;
  275. req->cal_done_valid = 1;
  276. req->cal_done = plat_priv->cal_done;
  277. cnss_pr_dbg("Calibration done is %d\n", plat_priv->cal_done);
  278. if (plat_priv->sleep_clk) {
  279. req->nm_modem_valid = 1;
  280. /* Notify firmware about the sleep clock selection,
  281. * nm_modem_bit[1] is used for this purpose.
  282. */
  283. req->nm_modem |= SLEEP_CLOCK_SELECT_INTERNAL_BIT;
  284. }
  285. if (plat_priv->supported_link_speed) {
  286. req->pcie_link_info_valid = 1;
  287. req->pcie_link_info.pci_link_speed =
  288. plat_priv->supported_link_speed;
  289. cnss_pr_dbg("Supported link speed in Host Cap %d\n",
  290. plat_priv->supported_link_speed);
  291. }
  292. if (cnss_bus_is_smmu_s1_enabled(plat_priv) &&
  293. !cnss_bus_get_iova(plat_priv, &iova_start, &iova_size) &&
  294. !cnss_bus_get_iova_ipa(plat_priv, &iova_ipa_start,
  295. &iova_ipa_size)) {
  296. req->ddr_range_valid = 1;
  297. req->ddr_range[0].start = iova_start;
  298. req->ddr_range[0].size = iova_size + iova_ipa_size;
  299. cnss_pr_dbg("Sending iova starting 0x%llx with size 0x%llx\n",
  300. req->ddr_range[0].start, req->ddr_range[0].size);
  301. }
  302. req->host_build_type_valid = 1;
  303. req->host_build_type = cnss_get_host_build_type();
  304. cnss_wlfw_host_cap_parse_mlo(plat_priv, req);
  305. ret = cnss_get_feature_list(plat_priv, &feature_list);
  306. if (!ret) {
  307. req->feature_list_valid = 1;
  308. req->feature_list = feature_list;
  309. cnss_pr_dbg("Sending feature list 0x%llx\n",
  310. req->feature_list);
  311. }
  312. if (cnss_get_platform_name(plat_priv, req->platform_name,
  313. QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01))
  314. req->platform_name_valid = 1;
  315. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  316. wlfw_host_cap_resp_msg_v01_ei, resp);
  317. if (ret < 0) {
  318. cnss_pr_err("Failed to initialize txn for host capability request, err: %d\n",
  319. ret);
  320. goto out;
  321. }
  322. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  323. QMI_WLFW_HOST_CAP_REQ_V01,
  324. WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  325. wlfw_host_cap_req_msg_v01_ei, req);
  326. if (ret < 0) {
  327. qmi_txn_cancel(&txn);
  328. cnss_pr_err("Failed to send host capability request, err: %d\n",
  329. ret);
  330. goto out;
  331. }
  332. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  333. if (ret < 0) {
  334. cnss_pr_err("Failed to wait for response of host capability request, err: %d\n",
  335. ret);
  336. goto out;
  337. }
  338. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  339. cnss_pr_err("Host capability request failed, result: %d, err: %d\n",
  340. resp->resp.result, resp->resp.error);
  341. ret = -resp->resp.result;
  342. goto out;
  343. }
  344. kfree(req);
  345. kfree(resp);
  346. return 0;
  347. out:
  348. CNSS_QMI_ASSERT();
  349. kfree(req);
  350. kfree(resp);
  351. return ret;
  352. }
  353. int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv)
  354. {
  355. struct wlfw_respond_mem_req_msg_v01 *req;
  356. struct wlfw_respond_mem_resp_msg_v01 *resp;
  357. struct qmi_txn txn;
  358. struct cnss_fw_mem *fw_mem = plat_priv->fw_mem;
  359. int ret = 0, i;
  360. cnss_pr_dbg("Sending respond memory message, state: 0x%lx\n",
  361. plat_priv->driver_state);
  362. req = kzalloc(sizeof(*req), GFP_KERNEL);
  363. if (!req)
  364. return -ENOMEM;
  365. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  366. if (!resp) {
  367. kfree(req);
  368. return -ENOMEM;
  369. }
  370. if (plat_priv->fw_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  371. cnss_pr_err("Invalid seg len %u\n", plat_priv->fw_mem_seg_len);
  372. ret = -EINVAL;
  373. goto out;
  374. }
  375. req->mem_seg_len = plat_priv->fw_mem_seg_len;
  376. for (i = 0; i < req->mem_seg_len; i++) {
  377. if (!fw_mem[i].pa || !fw_mem[i].size) {
  378. if (fw_mem[i].type == 0) {
  379. cnss_pr_err("Invalid memory for FW type, segment = %d\n",
  380. i);
  381. ret = -EINVAL;
  382. goto out;
  383. }
  384. cnss_pr_err("Memory for FW is not available for type: %u\n",
  385. fw_mem[i].type);
  386. ret = -ENOMEM;
  387. goto out;
  388. }
  389. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  390. fw_mem[i].va, &fw_mem[i].pa,
  391. fw_mem[i].size, fw_mem[i].type);
  392. req->mem_seg[i].addr = fw_mem[i].pa;
  393. req->mem_seg[i].size = fw_mem[i].size;
  394. req->mem_seg[i].type = fw_mem[i].type;
  395. }
  396. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  397. wlfw_respond_mem_resp_msg_v01_ei, resp);
  398. if (ret < 0) {
  399. cnss_pr_err("Failed to initialize txn for respond memory request, err: %d\n",
  400. ret);
  401. goto out;
  402. }
  403. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  404. QMI_WLFW_RESPOND_MEM_REQ_V01,
  405. WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN,
  406. wlfw_respond_mem_req_msg_v01_ei, req);
  407. if (ret < 0) {
  408. qmi_txn_cancel(&txn);
  409. cnss_pr_err("Failed to send respond memory request, err: %d\n",
  410. ret);
  411. goto out;
  412. }
  413. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  414. if (ret < 0) {
  415. cnss_pr_err("Failed to wait for response of respond memory request, err: %d\n",
  416. ret);
  417. goto out;
  418. }
  419. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  420. cnss_pr_err("Respond memory request failed, result: %d, err: %d\n",
  421. resp->resp.result, resp->resp.error);
  422. ret = -resp->resp.result;
  423. goto out;
  424. }
  425. kfree(req);
  426. kfree(resp);
  427. return 0;
  428. out:
  429. CNSS_QMI_ASSERT();
  430. kfree(req);
  431. kfree(resp);
  432. return ret;
  433. }
  434. int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv)
  435. {
  436. struct wlfw_cap_req_msg_v01 *req;
  437. struct wlfw_cap_resp_msg_v01 *resp;
  438. struct qmi_txn txn;
  439. char *fw_build_timestamp;
  440. int ret = 0, i;
  441. cnss_pr_dbg("Sending target capability message, state: 0x%lx\n",
  442. plat_priv->driver_state);
  443. req = kzalloc(sizeof(*req), GFP_KERNEL);
  444. if (!req)
  445. return -ENOMEM;
  446. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  447. if (!resp) {
  448. kfree(req);
  449. return -ENOMEM;
  450. }
  451. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  452. wlfw_cap_resp_msg_v01_ei, resp);
  453. if (ret < 0) {
  454. cnss_pr_err("Failed to initialize txn for target capability request, err: %d\n",
  455. ret);
  456. goto out;
  457. }
  458. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  459. QMI_WLFW_CAP_REQ_V01,
  460. WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  461. wlfw_cap_req_msg_v01_ei, req);
  462. if (ret < 0) {
  463. qmi_txn_cancel(&txn);
  464. cnss_pr_err("Failed to send respond target capability request, err: %d\n",
  465. ret);
  466. goto out;
  467. }
  468. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  469. if (ret < 0) {
  470. cnss_pr_err("Failed to wait for response of target capability request, err: %d\n",
  471. ret);
  472. goto out;
  473. }
  474. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  475. cnss_pr_err("Target capability request failed, result: %d, err: %d\n",
  476. resp->resp.result, resp->resp.error);
  477. ret = -resp->resp.result;
  478. goto out;
  479. }
  480. if (resp->chip_info_valid) {
  481. plat_priv->chip_info.chip_id = resp->chip_info.chip_id;
  482. plat_priv->chip_info.chip_family = resp->chip_info.chip_family;
  483. }
  484. if (resp->board_info_valid)
  485. plat_priv->board_info.board_id = resp->board_info.board_id;
  486. else
  487. plat_priv->board_info.board_id = 0xFF;
  488. if (resp->soc_info_valid)
  489. plat_priv->soc_info.soc_id = resp->soc_info.soc_id;
  490. if (resp->fw_version_info_valid) {
  491. plat_priv->fw_version_info.fw_version =
  492. resp->fw_version_info.fw_version;
  493. fw_build_timestamp = resp->fw_version_info.fw_build_timestamp;
  494. fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN] = '\0';
  495. strlcpy(plat_priv->fw_version_info.fw_build_timestamp,
  496. resp->fw_version_info.fw_build_timestamp,
  497. QMI_WLFW_MAX_TIMESTAMP_LEN + 1);
  498. }
  499. if (resp->fw_build_id_valid) {
  500. resp->fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN] = '\0';
  501. strlcpy(plat_priv->fw_build_id, resp->fw_build_id,
  502. QMI_WLFW_MAX_BUILD_ID_LEN + 1);
  503. }
  504. /* FW will send aop retention volatage for qca6490 */
  505. if (resp->voltage_mv_valid) {
  506. plat_priv->cpr_info.voltage = resp->voltage_mv;
  507. cnss_pr_dbg("Voltage for CPR: %dmV\n",
  508. plat_priv->cpr_info.voltage);
  509. cnss_update_cpr_info(plat_priv);
  510. }
  511. if (resp->time_freq_hz_valid) {
  512. plat_priv->device_freq_hz = resp->time_freq_hz;
  513. cnss_pr_dbg("Device frequency is %d HZ\n",
  514. plat_priv->device_freq_hz);
  515. }
  516. if (resp->otp_version_valid)
  517. plat_priv->otp_version = resp->otp_version;
  518. if (resp->dev_mem_info_valid) {
  519. for (i = 0; i < QMI_WLFW_MAX_DEV_MEM_NUM_V01; i++) {
  520. plat_priv->dev_mem_info[i].start =
  521. resp->dev_mem_info[i].start;
  522. plat_priv->dev_mem_info[i].size =
  523. resp->dev_mem_info[i].size;
  524. cnss_pr_buf("Device memory info[%d]: start = 0x%llx, size = 0x%llx\n",
  525. i, plat_priv->dev_mem_info[i].start,
  526. plat_priv->dev_mem_info[i].size);
  527. }
  528. }
  529. if (resp->fw_caps_valid) {
  530. plat_priv->fw_pcie_gen_switch =
  531. !!(resp->fw_caps & QMI_WLFW_HOST_PCIE_GEN_SWITCH_V01);
  532. plat_priv->fw_aux_uc_support =
  533. !!(resp->fw_caps & QMI_WLFW_AUX_UC_SUPPORT_V01);
  534. cnss_pr_dbg("FW aux uc support capability: %d\n",
  535. plat_priv->fw_aux_uc_support);
  536. plat_priv->fw_caps = resp->fw_caps;
  537. }
  538. if (resp->hang_data_length_valid &&
  539. resp->hang_data_length &&
  540. resp->hang_data_length <= WLFW_MAX_HANG_EVENT_DATA_SIZE)
  541. plat_priv->hang_event_data_len = resp->hang_data_length;
  542. else
  543. plat_priv->hang_event_data_len = 0;
  544. if (resp->hang_data_addr_offset_valid)
  545. plat_priv->hang_data_addr_offset = resp->hang_data_addr_offset;
  546. else
  547. plat_priv->hang_data_addr_offset = 0;
  548. if (resp->hwid_bitmap_valid)
  549. plat_priv->hwid_bitmap = resp->hwid_bitmap;
  550. if (resp->ol_cpr_cfg_valid)
  551. cnss_aop_ol_cpr_cfg_setup(plat_priv, &resp->ol_cpr_cfg);
  552. /* Disable WLAN PDC in AOP firmware for boards which support on chip PMIC
  553. * so AOP will ignore SW_CTRL changes and do not update regulator votes.
  554. **/
  555. for (i = 0; i < plat_priv->on_chip_pmic_devices_count; i++) {
  556. if (plat_priv->board_info.board_id ==
  557. plat_priv->on_chip_pmic_board_ids[i]) {
  558. cnss_pr_dbg("Disabling WLAN PDC for board_id: %02x\n",
  559. plat_priv->board_info.board_id);
  560. ret = cnss_aop_send_msg(plat_priv,
  561. "{class: wlan_pdc, ss: rf, res: pdc, enable: 0}");
  562. if (ret < 0)
  563. cnss_pr_dbg("Failed to Send AOP Msg");
  564. break;
  565. }
  566. }
  567. cnss_pr_dbg("Target capability: chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x, otp_version: 0x%x\n",
  568. plat_priv->chip_info.chip_id,
  569. plat_priv->chip_info.chip_family,
  570. plat_priv->board_info.board_id, plat_priv->soc_info.soc_id,
  571. plat_priv->otp_version);
  572. cnss_pr_dbg("fw_version: 0x%x, fw_build_timestamp: %s, fw_build_id: %s, hwid_bitmap:0x%x\n",
  573. plat_priv->fw_version_info.fw_version,
  574. plat_priv->fw_version_info.fw_build_timestamp,
  575. plat_priv->fw_build_id,
  576. plat_priv->hwid_bitmap);
  577. cnss_pr_dbg("Hang event params, Length: 0x%x, Offset Address: 0x%x\n",
  578. plat_priv->hang_event_data_len,
  579. plat_priv->hang_data_addr_offset);
  580. kfree(req);
  581. kfree(resp);
  582. return 0;
  583. out:
  584. CNSS_QMI_ASSERT();
  585. kfree(req);
  586. kfree(resp);
  587. return ret;
  588. }
  589. static char *cnss_bdf_type_to_str(enum cnss_bdf_type bdf_type)
  590. {
  591. switch (bdf_type) {
  592. case CNSS_BDF_BIN:
  593. case CNSS_BDF_ELF:
  594. return "BDF";
  595. case CNSS_BDF_REGDB:
  596. return "REGDB";
  597. case CNSS_BDF_HDS:
  598. return "HDS";
  599. default:
  600. return "UNKNOWN";
  601. }
  602. }
  603. static int cnss_get_bdf_file_name(struct cnss_plat_data *plat_priv,
  604. u32 bdf_type, char *filename,
  605. u32 filename_len)
  606. {
  607. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  608. int ret = 0;
  609. switch (bdf_type) {
  610. case CNSS_BDF_ELF:
  611. /* Board ID will be equal or less than 0xFF in GF mask case */
  612. if (plat_priv->board_info.board_id == 0xFF) {
  613. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  614. snprintf(filename_tmp, filename_len,
  615. ELF_BDF_FILE_NAME_GF);
  616. else
  617. snprintf(filename_tmp, filename_len,
  618. ELF_BDF_FILE_NAME);
  619. } else if (plat_priv->board_info.board_id < 0xFF) {
  620. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  621. snprintf(filename_tmp, filename_len,
  622. ELF_BDF_FILE_NAME_GF_PREFIX "%02x",
  623. plat_priv->board_info.board_id);
  624. else
  625. snprintf(filename_tmp, filename_len,
  626. ELF_BDF_FILE_NAME_PREFIX "%02x",
  627. plat_priv->board_info.board_id);
  628. } else {
  629. snprintf(filename_tmp, filename_len,
  630. BDF_FILE_NAME_PREFIX "%02x.e%02x",
  631. plat_priv->board_info.board_id >> 8 & 0xFF,
  632. plat_priv->board_info.board_id & 0xFF);
  633. }
  634. break;
  635. case CNSS_BDF_BIN:
  636. if (plat_priv->board_info.board_id == 0xFF) {
  637. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  638. snprintf(filename_tmp, filename_len,
  639. BIN_BDF_FILE_NAME_GF);
  640. else
  641. snprintf(filename_tmp, filename_len,
  642. BIN_BDF_FILE_NAME);
  643. } else if (plat_priv->board_info.board_id < 0xFF) {
  644. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  645. snprintf(filename_tmp, filename_len,
  646. BIN_BDF_FILE_NAME_GF_PREFIX "%02x",
  647. plat_priv->board_info.board_id);
  648. else
  649. snprintf(filename_tmp, filename_len,
  650. BIN_BDF_FILE_NAME_PREFIX "%02x",
  651. plat_priv->board_info.board_id);
  652. } else {
  653. snprintf(filename_tmp, filename_len,
  654. BDF_FILE_NAME_PREFIX "%02x.b%02x",
  655. plat_priv->board_info.board_id >> 8 & 0xFF,
  656. plat_priv->board_info.board_id & 0xFF);
  657. }
  658. break;
  659. case CNSS_BDF_REGDB:
  660. snprintf(filename_tmp, filename_len, REGDB_FILE_NAME);
  661. break;
  662. case CNSS_BDF_HDS:
  663. snprintf(filename_tmp, filename_len, HDS_FILE_NAME);
  664. break;
  665. default:
  666. cnss_pr_err("Invalid BDF type: %d\n",
  667. plat_priv->ctrl_params.bdf_type);
  668. ret = -EINVAL;
  669. break;
  670. }
  671. if (!ret)
  672. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  673. return ret;
  674. }
  675. int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv,
  676. u32 bdf_type)
  677. {
  678. struct wlfw_bdf_download_req_msg_v01 *req;
  679. struct wlfw_bdf_download_resp_msg_v01 *resp;
  680. struct qmi_txn txn;
  681. char filename[MAX_FIRMWARE_NAME_LEN];
  682. const struct firmware *fw_entry = NULL;
  683. const u8 *temp;
  684. unsigned int remaining;
  685. int ret = 0;
  686. cnss_pr_dbg("Sending QMI_WLFW_BDF_DOWNLOAD_REQ_V01 message for bdf_type: %d (%s), state: 0x%lx\n",
  687. bdf_type, cnss_bdf_type_to_str(bdf_type), plat_priv->driver_state);
  688. req = kzalloc(sizeof(*req), GFP_KERNEL);
  689. if (!req)
  690. return -ENOMEM;
  691. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  692. if (!resp) {
  693. kfree(req);
  694. return -ENOMEM;
  695. }
  696. ret = cnss_get_bdf_file_name(plat_priv, bdf_type,
  697. filename, sizeof(filename));
  698. if (ret)
  699. goto err_req_fw;
  700. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n", filename);
  701. if (bdf_type == CNSS_BDF_REGDB)
  702. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  703. filename);
  704. else
  705. ret = firmware_request_nowarn(&fw_entry, filename,
  706. &plat_priv->plat_dev->dev);
  707. if (ret) {
  708. cnss_pr_err("Failed to load %s: %s, ret: %d\n",
  709. cnss_bdf_type_to_str(bdf_type), filename, ret);
  710. goto err_req_fw;
  711. }
  712. temp = fw_entry->data;
  713. remaining = fw_entry->size;
  714. cnss_pr_dbg("Downloading %s: %s, size: %u\n",
  715. cnss_bdf_type_to_str(bdf_type), filename, remaining);
  716. while (remaining) {
  717. req->valid = 1;
  718. req->file_id_valid = 1;
  719. req->file_id = plat_priv->board_info.board_id;
  720. req->total_size_valid = 1;
  721. req->total_size = remaining;
  722. req->seg_id_valid = 1;
  723. req->data_valid = 1;
  724. req->end_valid = 1;
  725. req->bdf_type_valid = 1;
  726. req->bdf_type = bdf_type;
  727. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  728. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  729. } else {
  730. req->data_len = remaining;
  731. req->end = 1;
  732. }
  733. memcpy(req->data, temp, req->data_len);
  734. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  735. wlfw_bdf_download_resp_msg_v01_ei, resp);
  736. if (ret < 0) {
  737. cnss_pr_err("Failed to initialize txn for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  738. cnss_bdf_type_to_str(bdf_type), ret);
  739. goto err_send;
  740. }
  741. ret = qmi_send_request
  742. (&plat_priv->qmi_wlfw, NULL, &txn,
  743. QMI_WLFW_BDF_DOWNLOAD_REQ_V01,
  744. WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  745. wlfw_bdf_download_req_msg_v01_ei, req);
  746. if (ret < 0) {
  747. qmi_txn_cancel(&txn);
  748. cnss_pr_err("Failed to send QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  749. cnss_bdf_type_to_str(bdf_type), ret);
  750. goto err_send;
  751. }
  752. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  753. if (ret < 0) {
  754. cnss_pr_err("Timeout while waiting for FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, err: %d\n",
  755. cnss_bdf_type_to_str(bdf_type), ret);
  756. goto err_send;
  757. }
  758. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  759. cnss_pr_err("FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s failed, result: %d, err: %d\n",
  760. cnss_bdf_type_to_str(bdf_type), resp->resp.result,
  761. resp->resp.error);
  762. ret = -resp->resp.result;
  763. goto err_send;
  764. }
  765. remaining -= req->data_len;
  766. temp += req->data_len;
  767. req->seg_id++;
  768. }
  769. release_firmware(fw_entry);
  770. if (resp->host_bdf_data_valid) {
  771. /* QCA6490 enable S3E regulator for IPA configuration only */
  772. if (!(resp->host_bdf_data & QMI_WLFW_HW_XPA_V01))
  773. cnss_enable_int_pow_amp_vreg(plat_priv);
  774. plat_priv->cbc_file_download =
  775. resp->host_bdf_data & QMI_WLFW_CBC_FILE_DOWNLOAD_V01;
  776. cnss_pr_info("Host BDF config: HW_XPA: %d CalDB: %d\n",
  777. resp->host_bdf_data & QMI_WLFW_HW_XPA_V01,
  778. plat_priv->cbc_file_download);
  779. }
  780. kfree(req);
  781. kfree(resp);
  782. return 0;
  783. err_send:
  784. release_firmware(fw_entry);
  785. err_req_fw:
  786. if (!(bdf_type == CNSS_BDF_REGDB ||
  787. test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state) ||
  788. ret == -EAGAIN))
  789. CNSS_QMI_ASSERT();
  790. kfree(req);
  791. kfree(resp);
  792. return ret;
  793. }
  794. int cnss_wlfw_tme_patch_dnld_send_sync(struct cnss_plat_data *plat_priv,
  795. enum wlfw_tme_lite_file_type_v01 file)
  796. {
  797. struct wlfw_tme_lite_info_req_msg_v01 *req;
  798. struct wlfw_tme_lite_info_resp_msg_v01 *resp;
  799. struct qmi_txn txn;
  800. struct cnss_fw_mem *tme_lite_mem = &plat_priv->tme_lite_mem;
  801. int ret = 0;
  802. cnss_pr_dbg("Sending TME patch information message, state: 0x%lx\n",
  803. plat_priv->driver_state);
  804. if (plat_priv->device_id != PEACH_DEVICE_ID)
  805. return 0;
  806. req = kzalloc(sizeof(*req), GFP_KERNEL);
  807. if (!req)
  808. return -ENOMEM;
  809. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  810. if (!resp) {
  811. kfree(req);
  812. return -ENOMEM;
  813. }
  814. if (!tme_lite_mem->pa || !tme_lite_mem->size) {
  815. cnss_pr_err("Memory for TME patch is not available\n");
  816. ret = -ENOMEM;
  817. goto out;
  818. }
  819. cnss_pr_dbg("TME-L patch memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  820. tme_lite_mem->va, &tme_lite_mem->pa, tme_lite_mem->size);
  821. req->tme_file = file;
  822. req->addr = plat_priv->tme_lite_mem.pa;
  823. req->size = plat_priv->tme_lite_mem.size;
  824. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  825. wlfw_tme_lite_info_resp_msg_v01_ei, resp);
  826. if (ret < 0) {
  827. cnss_pr_err("Failed to initialize txn for TME patch information request, err: %d\n",
  828. ret);
  829. goto out;
  830. }
  831. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  832. QMI_WLFW_TME_LITE_INFO_REQ_V01,
  833. WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  834. wlfw_tme_lite_info_req_msg_v01_ei, req);
  835. if (ret < 0) {
  836. qmi_txn_cancel(&txn);
  837. cnss_pr_err("Failed to send TME patch information request, err: %d\n",
  838. ret);
  839. goto out;
  840. }
  841. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  842. if (ret < 0) {
  843. cnss_pr_err("Failed to wait for response of TME patch information request, err: %d\n",
  844. ret);
  845. goto out;
  846. }
  847. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  848. cnss_pr_err("TME patch information request failed, result: %d, err: %d\n",
  849. resp->resp.result, resp->resp.error);
  850. ret = -resp->resp.result;
  851. goto out;
  852. }
  853. kfree(req);
  854. kfree(resp);
  855. return 0;
  856. out:
  857. kfree(req);
  858. kfree(resp);
  859. return ret;
  860. }
  861. int cnss_wlfw_m3_dnld_send_sync(struct cnss_plat_data *plat_priv)
  862. {
  863. struct wlfw_m3_info_req_msg_v01 *req;
  864. struct wlfw_m3_info_resp_msg_v01 *resp;
  865. struct qmi_txn txn;
  866. struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem;
  867. int ret = 0;
  868. cnss_pr_dbg("Sending M3 information message, state: 0x%lx\n",
  869. plat_priv->driver_state);
  870. req = kzalloc(sizeof(*req), GFP_KERNEL);
  871. if (!req)
  872. return -ENOMEM;
  873. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  874. if (!resp) {
  875. kfree(req);
  876. return -ENOMEM;
  877. }
  878. if (!m3_mem->pa || !m3_mem->size) {
  879. cnss_pr_err("Memory for M3 is not available\n");
  880. ret = -ENOMEM;
  881. goto out;
  882. }
  883. cnss_pr_dbg("M3 memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  884. m3_mem->va, &m3_mem->pa, m3_mem->size);
  885. req->addr = plat_priv->m3_mem.pa;
  886. req->size = plat_priv->m3_mem.size;
  887. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  888. wlfw_m3_info_resp_msg_v01_ei, resp);
  889. if (ret < 0) {
  890. cnss_pr_err("Failed to initialize txn for M3 information request, err: %d\n",
  891. ret);
  892. goto out;
  893. }
  894. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  895. QMI_WLFW_M3_INFO_REQ_V01,
  896. WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  897. wlfw_m3_info_req_msg_v01_ei, req);
  898. if (ret < 0) {
  899. qmi_txn_cancel(&txn);
  900. cnss_pr_err("Failed to send M3 information request, err: %d\n",
  901. ret);
  902. goto out;
  903. }
  904. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  905. if (ret < 0) {
  906. cnss_pr_err("Failed to wait for response of M3 information request, err: %d\n",
  907. ret);
  908. goto out;
  909. }
  910. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  911. cnss_pr_err("M3 information request failed, result: %d, err: %d\n",
  912. resp->resp.result, resp->resp.error);
  913. ret = -resp->resp.result;
  914. goto out;
  915. }
  916. kfree(req);
  917. kfree(resp);
  918. return 0;
  919. out:
  920. CNSS_QMI_ASSERT();
  921. kfree(req);
  922. kfree(resp);
  923. return ret;
  924. }
  925. int cnss_wlfw_aux_dnld_send_sync(struct cnss_plat_data *plat_priv)
  926. {
  927. struct wlfw_aux_uc_info_req_msg_v01 *req;
  928. struct wlfw_aux_uc_info_resp_msg_v01 *resp;
  929. struct qmi_txn txn;
  930. struct cnss_fw_mem *aux_mem = &plat_priv->aux_mem;
  931. int ret = 0;
  932. cnss_pr_dbg("Sending QMI_WLFW_AUX_UC_INFO_REQ_V01 message, state: 0x%lx\n",
  933. plat_priv->driver_state);
  934. req = kzalloc(sizeof(*req), GFP_KERNEL);
  935. if (!req)
  936. return -ENOMEM;
  937. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  938. if (!resp) {
  939. kfree(req);
  940. return -ENOMEM;
  941. }
  942. if (!aux_mem->pa || !aux_mem->size) {
  943. cnss_pr_err("Memory for AUX is not available\n");
  944. ret = -ENOMEM;
  945. goto out;
  946. }
  947. cnss_pr_dbg("AUX memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  948. aux_mem->va, &aux_mem->pa, aux_mem->size);
  949. req->addr = plat_priv->aux_mem.pa;
  950. req->size = plat_priv->aux_mem.size;
  951. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  952. wlfw_aux_uc_info_resp_msg_v01_ei, resp);
  953. if (ret < 0) {
  954. cnss_pr_err("Failed to initialize txn for QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  955. ret);
  956. goto out;
  957. }
  958. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  959. QMI_WLFW_AUX_UC_INFO_REQ_V01,
  960. WLFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  961. wlfw_aux_uc_info_req_msg_v01_ei, req);
  962. if (ret < 0) {
  963. qmi_txn_cancel(&txn);
  964. cnss_pr_err("Failed to send QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  965. ret);
  966. goto out;
  967. }
  968. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  969. if (ret < 0) {
  970. cnss_pr_err("Failed to wait for response of QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  971. ret);
  972. goto out;
  973. }
  974. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  975. cnss_pr_err("QMI_WLFW_AUX_UC_INFO_REQ_V01 request failed, result: %d, err: %d\n",
  976. resp->resp.result, resp->resp.error);
  977. ret = -resp->resp.result;
  978. goto out;
  979. }
  980. kfree(req);
  981. kfree(resp);
  982. return 0;
  983. out:
  984. CNSS_QMI_ASSERT();
  985. kfree(req);
  986. kfree(resp);
  987. return ret;
  988. }
  989. int cnss_wlfw_wlan_mac_req_send_sync(struct cnss_plat_data *plat_priv,
  990. u8 *mac, u32 mac_len)
  991. {
  992. struct wlfw_mac_addr_req_msg_v01 req;
  993. struct wlfw_mac_addr_resp_msg_v01 resp = {0};
  994. struct qmi_txn txn;
  995. int ret;
  996. if (!plat_priv || !mac || mac_len != QMI_WLFW_MAC_ADDR_SIZE_V01)
  997. return -EINVAL;
  998. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  999. wlfw_mac_addr_resp_msg_v01_ei, &resp);
  1000. if (ret < 0) {
  1001. cnss_pr_err("Failed to initialize txn for mac req, err: %d\n",
  1002. ret);
  1003. ret = -EIO;
  1004. goto out;
  1005. }
  1006. cnss_pr_dbg("Sending WLAN mac req [%pM], state: 0x%lx\n",
  1007. mac, plat_priv->driver_state);
  1008. memcpy(req.mac_addr, mac, mac_len);
  1009. req.mac_addr_valid = 1;
  1010. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1011. QMI_WLFW_MAC_ADDR_REQ_V01,
  1012. WLFW_MAC_ADDR_REQ_MSG_V01_MAX_MSG_LEN,
  1013. wlfw_mac_addr_req_msg_v01_ei, &req);
  1014. if (ret < 0) {
  1015. qmi_txn_cancel(&txn);
  1016. cnss_pr_err("Failed to send mac req, err: %d\n", ret);
  1017. ret = -EIO;
  1018. goto out;
  1019. }
  1020. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1021. if (ret < 0) {
  1022. cnss_pr_err("Failed to wait for resp of mac req, err: %d\n",
  1023. ret);
  1024. ret = -EIO;
  1025. goto out;
  1026. }
  1027. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1028. cnss_pr_err("WLAN mac req failed, result: %d, err: %d\n",
  1029. resp.resp.result);
  1030. ret = -resp.resp.result;
  1031. }
  1032. out:
  1033. return ret;
  1034. }
  1035. int cnss_wlfw_qdss_data_send_sync(struct cnss_plat_data *plat_priv, char *file_name,
  1036. u32 total_size)
  1037. {
  1038. int ret = 0;
  1039. struct wlfw_qdss_trace_data_req_msg_v01 *req;
  1040. struct wlfw_qdss_trace_data_resp_msg_v01 *resp;
  1041. unsigned char *p_qdss_trace_data_temp, *p_qdss_trace_data = NULL;
  1042. unsigned int remaining;
  1043. struct qmi_txn txn;
  1044. cnss_pr_dbg("%s\n", __func__);
  1045. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1046. if (!req)
  1047. return -ENOMEM;
  1048. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1049. if (!resp) {
  1050. kfree(req);
  1051. return -ENOMEM;
  1052. }
  1053. p_qdss_trace_data = kzalloc(total_size, GFP_KERNEL);
  1054. if (!p_qdss_trace_data) {
  1055. ret = ENOMEM;
  1056. goto end;
  1057. }
  1058. remaining = total_size;
  1059. p_qdss_trace_data_temp = p_qdss_trace_data;
  1060. while (remaining && resp->end == 0) {
  1061. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1062. wlfw_qdss_trace_data_resp_msg_v01_ei, resp);
  1063. if (ret < 0) {
  1064. cnss_pr_err("Fail to init txn for QDSS trace resp %d\n",
  1065. ret);
  1066. goto fail;
  1067. }
  1068. ret = qmi_send_request
  1069. (&plat_priv->qmi_wlfw, NULL, &txn,
  1070. QMI_WLFW_QDSS_TRACE_DATA_REQ_V01,
  1071. WLFW_QDSS_TRACE_DATA_REQ_MSG_V01_MAX_MSG_LEN,
  1072. wlfw_qdss_trace_data_req_msg_v01_ei, req);
  1073. if (ret < 0) {
  1074. qmi_txn_cancel(&txn);
  1075. cnss_pr_err("Fail to send QDSS trace data req %d\n",
  1076. ret);
  1077. goto fail;
  1078. }
  1079. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1080. if (ret < 0) {
  1081. cnss_pr_err("QDSS trace resp wait failed with rc %d\n",
  1082. ret);
  1083. goto fail;
  1084. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1085. cnss_pr_err("QMI QDSS trace request rejected, result:%d error:%d\n",
  1086. resp->resp.result, resp->resp.error);
  1087. ret = -resp->resp.result;
  1088. goto fail;
  1089. } else {
  1090. ret = 0;
  1091. }
  1092. cnss_pr_dbg("%s: response total size %d data len %d",
  1093. __func__, resp->total_size, resp->data_len);
  1094. if ((resp->total_size_valid == 1 &&
  1095. resp->total_size == total_size) &&
  1096. (resp->seg_id_valid == 1 && resp->seg_id == req->seg_id) &&
  1097. (resp->data_valid == 1 &&
  1098. resp->data_len <= QMI_WLFW_MAX_DATA_SIZE_V01) &&
  1099. resp->data_len <= remaining) {
  1100. memcpy(p_qdss_trace_data_temp,
  1101. resp->data, resp->data_len);
  1102. } else {
  1103. cnss_pr_err("%s: Unmatched qdss trace data, Expect total_size %u, seg_id %u, Recv total_size_valid %u, total_size %u, seg_id_valid %u, seg_id %u, data_len_valid %u, data_len %u",
  1104. __func__,
  1105. total_size, req->seg_id,
  1106. resp->total_size_valid,
  1107. resp->total_size,
  1108. resp->seg_id_valid,
  1109. resp->seg_id,
  1110. resp->data_valid,
  1111. resp->data_len);
  1112. ret = -1;
  1113. goto fail;
  1114. }
  1115. remaining -= resp->data_len;
  1116. p_qdss_trace_data_temp += resp->data_len;
  1117. req->seg_id++;
  1118. }
  1119. if (remaining == 0 && (resp->end_valid && resp->end)) {
  1120. ret = cnss_genl_send_msg(p_qdss_trace_data,
  1121. CNSS_GENL_MSG_TYPE_QDSS, file_name,
  1122. total_size);
  1123. if (ret < 0) {
  1124. cnss_pr_err("Fail to save QDSS trace data: %d\n",
  1125. ret);
  1126. ret = -1;
  1127. goto fail;
  1128. }
  1129. } else {
  1130. cnss_pr_err("%s: QDSS trace file corrupted: remaining %u, end_valid %u, end %u",
  1131. __func__,
  1132. remaining, resp->end_valid, resp->end);
  1133. ret = -1;
  1134. goto fail;
  1135. }
  1136. fail:
  1137. kfree(p_qdss_trace_data);
  1138. end:
  1139. kfree(req);
  1140. kfree(resp);
  1141. return ret;
  1142. }
  1143. void cnss_get_qdss_cfg_filename(struct cnss_plat_data *plat_priv,
  1144. char *filename, u32 filename_len,
  1145. bool fallback_file)
  1146. {
  1147. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  1148. char *build_str = QDSS_FILE_BUILD_STR;
  1149. if (fallback_file)
  1150. build_str = "";
  1151. if (plat_priv->device_version.major_version == FW_V2_NUMBER)
  1152. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1153. "_%s%s.cfg", build_str, HW_V2_NUMBER);
  1154. else
  1155. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1156. "_%s%s.cfg", build_str, HW_V1_NUMBER);
  1157. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  1158. }
  1159. int cnss_wlfw_qdss_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1160. {
  1161. struct wlfw_qdss_trace_config_download_req_msg_v01 *req;
  1162. struct wlfw_qdss_trace_config_download_resp_msg_v01 *resp;
  1163. struct qmi_txn txn;
  1164. const struct firmware *fw_entry = NULL;
  1165. const u8 *temp;
  1166. char qdss_cfg_filename[MAX_FIRMWARE_NAME_LEN];
  1167. unsigned int remaining;
  1168. int ret = 0;
  1169. cnss_pr_dbg("Sending QDSS config download message, state: 0x%lx\n",
  1170. plat_priv->driver_state);
  1171. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1172. if (!req)
  1173. return -ENOMEM;
  1174. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1175. if (!resp) {
  1176. kfree(req);
  1177. return -ENOMEM;
  1178. }
  1179. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1180. sizeof(qdss_cfg_filename), false);
  1181. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n",
  1182. qdss_cfg_filename);
  1183. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1184. qdss_cfg_filename);
  1185. if (ret) {
  1186. cnss_pr_dbg("Unable to load %s ret %d, try default file\n",
  1187. qdss_cfg_filename, ret);
  1188. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1189. sizeof(qdss_cfg_filename),
  1190. true);
  1191. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n",
  1192. qdss_cfg_filename);
  1193. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1194. qdss_cfg_filename);
  1195. if (ret) {
  1196. cnss_pr_err("Unable to load %s ret %d\n",
  1197. qdss_cfg_filename, ret);
  1198. goto err_req_fw;
  1199. }
  1200. }
  1201. temp = fw_entry->data;
  1202. remaining = fw_entry->size;
  1203. cnss_pr_dbg("Downloading QDSS: %s, size: %u\n",
  1204. qdss_cfg_filename, remaining);
  1205. while (remaining) {
  1206. req->total_size_valid = 1;
  1207. req->total_size = remaining;
  1208. req->seg_id_valid = 1;
  1209. req->data_valid = 1;
  1210. req->end_valid = 1;
  1211. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1212. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  1213. } else {
  1214. req->data_len = remaining;
  1215. req->end = 1;
  1216. }
  1217. memcpy(req->data, temp, req->data_len);
  1218. ret = qmi_txn_init
  1219. (&plat_priv->qmi_wlfw, &txn,
  1220. wlfw_qdss_trace_config_download_resp_msg_v01_ei,
  1221. resp);
  1222. if (ret < 0) {
  1223. cnss_pr_err("Failed to initialize txn for QDSS download request, err: %d\n",
  1224. ret);
  1225. goto err_send;
  1226. }
  1227. ret = qmi_send_request
  1228. (&plat_priv->qmi_wlfw, NULL, &txn,
  1229. QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01,
  1230. WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  1231. wlfw_qdss_trace_config_download_req_msg_v01_ei, req);
  1232. if (ret < 0) {
  1233. qmi_txn_cancel(&txn);
  1234. cnss_pr_err("Failed to send respond QDSS download request, err: %d\n",
  1235. ret);
  1236. goto err_send;
  1237. }
  1238. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1239. if (ret < 0) {
  1240. cnss_pr_err("Failed to wait for response of QDSS download request, err: %d\n",
  1241. ret);
  1242. goto err_send;
  1243. }
  1244. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1245. cnss_pr_err("QDSS download request failed, result: %d, err: %d\n",
  1246. resp->resp.result, resp->resp.error);
  1247. ret = -resp->resp.result;
  1248. goto err_send;
  1249. }
  1250. remaining -= req->data_len;
  1251. temp += req->data_len;
  1252. req->seg_id++;
  1253. }
  1254. release_firmware(fw_entry);
  1255. kfree(req);
  1256. kfree(resp);
  1257. return 0;
  1258. err_send:
  1259. release_firmware(fw_entry);
  1260. err_req_fw:
  1261. kfree(req);
  1262. kfree(resp);
  1263. return ret;
  1264. }
  1265. static int wlfw_send_qdss_trace_mode_req
  1266. (struct cnss_plat_data *plat_priv,
  1267. enum wlfw_qdss_trace_mode_enum_v01 mode,
  1268. unsigned long long option)
  1269. {
  1270. int rc = 0;
  1271. int tmp = 0;
  1272. struct wlfw_qdss_trace_mode_req_msg_v01 *req;
  1273. struct wlfw_qdss_trace_mode_resp_msg_v01 *resp;
  1274. struct qmi_txn txn;
  1275. if (!plat_priv)
  1276. return -ENODEV;
  1277. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1278. if (!req)
  1279. return -ENOMEM;
  1280. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1281. if (!resp) {
  1282. kfree(req);
  1283. return -ENOMEM;
  1284. }
  1285. req->mode_valid = 1;
  1286. req->mode = mode;
  1287. req->option_valid = 1;
  1288. req->option = option;
  1289. tmp = plat_priv->hw_trc_override;
  1290. req->hw_trc_disable_override_valid = 1;
  1291. req->hw_trc_disable_override =
  1292. (tmp > QMI_PARAM_DISABLE_V01 ? QMI_PARAM_DISABLE_V01 :
  1293. (tmp < 0 ? QMI_PARAM_INVALID_V01 : tmp));
  1294. cnss_pr_dbg("%s: mode %u, option %llu, hw_trc_disable_override: %u",
  1295. __func__, mode, option, req->hw_trc_disable_override);
  1296. rc = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1297. wlfw_qdss_trace_mode_resp_msg_v01_ei, resp);
  1298. if (rc < 0) {
  1299. cnss_pr_err("Fail to init txn for QDSS Mode resp %d\n",
  1300. rc);
  1301. goto out;
  1302. }
  1303. rc = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1304. QMI_WLFW_QDSS_TRACE_MODE_REQ_V01,
  1305. WLFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1306. wlfw_qdss_trace_mode_req_msg_v01_ei, req);
  1307. if (rc < 0) {
  1308. qmi_txn_cancel(&txn);
  1309. cnss_pr_err("Fail to send QDSS Mode req %d\n", rc);
  1310. goto out;
  1311. }
  1312. rc = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1313. if (rc < 0) {
  1314. cnss_pr_err("QDSS Mode resp wait failed with rc %d\n",
  1315. rc);
  1316. goto out;
  1317. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1318. cnss_pr_err("QMI QDSS Mode request rejected, result:%d error:%d\n",
  1319. resp->resp.result, resp->resp.error);
  1320. rc = -resp->resp.result;
  1321. goto out;
  1322. }
  1323. kfree(resp);
  1324. kfree(req);
  1325. return rc;
  1326. out:
  1327. kfree(resp);
  1328. kfree(req);
  1329. CNSS_QMI_ASSERT();
  1330. return rc;
  1331. }
  1332. int wlfw_qdss_trace_start(struct cnss_plat_data *plat_priv)
  1333. {
  1334. return wlfw_send_qdss_trace_mode_req(plat_priv,
  1335. QMI_WLFW_QDSS_TRACE_ON_V01, 0);
  1336. }
  1337. int wlfw_qdss_trace_stop(struct cnss_plat_data *plat_priv, unsigned long long option)
  1338. {
  1339. return wlfw_send_qdss_trace_mode_req(plat_priv, QMI_WLFW_QDSS_TRACE_OFF_V01,
  1340. option);
  1341. }
  1342. int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv,
  1343. enum cnss_driver_mode mode)
  1344. {
  1345. struct wlfw_wlan_mode_req_msg_v01 *req;
  1346. struct wlfw_wlan_mode_resp_msg_v01 *resp;
  1347. struct qmi_txn txn;
  1348. int ret = 0;
  1349. if (!plat_priv)
  1350. return -ENODEV;
  1351. cnss_pr_dbg("Sending mode message, mode: %s(%d), state: 0x%lx\n",
  1352. cnss_qmi_mode_to_str(mode), mode, plat_priv->driver_state);
  1353. if (mode == CNSS_OFF &&
  1354. test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1355. cnss_pr_dbg("Recovery is in progress, ignore mode off request\n");
  1356. return 0;
  1357. }
  1358. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1359. if (!req)
  1360. return -ENOMEM;
  1361. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1362. if (!resp) {
  1363. kfree(req);
  1364. return -ENOMEM;
  1365. }
  1366. req->mode = (enum wlfw_driver_mode_enum_v01)mode;
  1367. req->hw_debug_valid = 1;
  1368. req->hw_debug = 0;
  1369. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1370. wlfw_wlan_mode_resp_msg_v01_ei, resp);
  1371. if (ret < 0) {
  1372. cnss_pr_err("Failed to initialize txn for mode request, mode: %s(%d), err: %d\n",
  1373. cnss_qmi_mode_to_str(mode), mode, ret);
  1374. goto out;
  1375. }
  1376. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1377. QMI_WLFW_WLAN_MODE_REQ_V01,
  1378. WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1379. wlfw_wlan_mode_req_msg_v01_ei, req);
  1380. if (ret < 0) {
  1381. qmi_txn_cancel(&txn);
  1382. cnss_pr_err("Failed to send mode request, mode: %s(%d), err: %d\n",
  1383. cnss_qmi_mode_to_str(mode), mode, ret);
  1384. goto out;
  1385. }
  1386. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1387. if (ret < 0) {
  1388. cnss_pr_err("Failed to wait for response of mode request, mode: %s(%d), err: %d\n",
  1389. cnss_qmi_mode_to_str(mode), mode, ret);
  1390. goto out;
  1391. }
  1392. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1393. cnss_pr_err("Mode request failed, mode: %s(%d), result: %d, err: %d\n",
  1394. cnss_qmi_mode_to_str(mode), mode, resp->resp.result,
  1395. resp->resp.error);
  1396. ret = -resp->resp.result;
  1397. goto out;
  1398. }
  1399. kfree(req);
  1400. kfree(resp);
  1401. return 0;
  1402. out:
  1403. if (mode == CNSS_OFF) {
  1404. cnss_pr_dbg("WLFW service is disconnected while sending mode off request\n");
  1405. ret = 0;
  1406. } else {
  1407. CNSS_QMI_ASSERT();
  1408. }
  1409. kfree(req);
  1410. kfree(resp);
  1411. return ret;
  1412. }
  1413. int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv,
  1414. struct cnss_wlan_enable_cfg *config,
  1415. const char *host_version)
  1416. {
  1417. struct wlfw_wlan_cfg_req_msg_v01 *req;
  1418. struct wlfw_wlan_cfg_resp_msg_v01 *resp;
  1419. struct qmi_txn txn;
  1420. u32 i, ce_id, num_vectors, user_base_data, base_vector;
  1421. int ret = 0;
  1422. if (!plat_priv)
  1423. return -ENODEV;
  1424. cnss_pr_dbg("Sending WLAN config message, state: 0x%lx\n",
  1425. plat_priv->driver_state);
  1426. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1427. if (!req)
  1428. return -ENOMEM;
  1429. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1430. if (!resp) {
  1431. kfree(req);
  1432. return -ENOMEM;
  1433. }
  1434. req->host_version_valid = 1;
  1435. strlcpy(req->host_version, host_version,
  1436. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  1437. req->tgt_cfg_valid = 1;
  1438. if (config->num_ce_tgt_cfg > QMI_WLFW_MAX_NUM_CE_V01)
  1439. req->tgt_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1440. else
  1441. req->tgt_cfg_len = config->num_ce_tgt_cfg;
  1442. for (i = 0; i < req->tgt_cfg_len; i++) {
  1443. req->tgt_cfg[i].pipe_num = config->ce_tgt_cfg[i].pipe_num;
  1444. req->tgt_cfg[i].pipe_dir = config->ce_tgt_cfg[i].pipe_dir;
  1445. req->tgt_cfg[i].nentries = config->ce_tgt_cfg[i].nentries;
  1446. req->tgt_cfg[i].nbytes_max = config->ce_tgt_cfg[i].nbytes_max;
  1447. req->tgt_cfg[i].flags = config->ce_tgt_cfg[i].flags;
  1448. }
  1449. req->svc_cfg_valid = 1;
  1450. if (config->num_ce_svc_pipe_cfg > QMI_WLFW_MAX_NUM_SVC_V01)
  1451. req->svc_cfg_len = QMI_WLFW_MAX_NUM_SVC_V01;
  1452. else
  1453. req->svc_cfg_len = config->num_ce_svc_pipe_cfg;
  1454. for (i = 0; i < req->svc_cfg_len; i++) {
  1455. req->svc_cfg[i].service_id = config->ce_svc_cfg[i].service_id;
  1456. req->svc_cfg[i].pipe_dir = config->ce_svc_cfg[i].pipe_dir;
  1457. req->svc_cfg[i].pipe_num = config->ce_svc_cfg[i].pipe_num;
  1458. }
  1459. if (plat_priv->device_id != KIWI_DEVICE_ID &&
  1460. plat_priv->device_id != MANGO_DEVICE_ID &&
  1461. plat_priv->device_id != PEACH_DEVICE_ID) {
  1462. if (plat_priv->device_id == QCN7605_DEVICE_ID &&
  1463. config->num_shadow_reg_cfg) {
  1464. req->shadow_reg_valid = 1;
  1465. if (config->num_shadow_reg_cfg >
  1466. QMI_WLFW_MAX_NUM_SHADOW_REG_V01)
  1467. req->shadow_reg_len =
  1468. QMI_WLFW_MAX_NUM_SHADOW_REG_V01;
  1469. else
  1470. req->shadow_reg_len =
  1471. config->num_shadow_reg_cfg;
  1472. memcpy(req->shadow_reg, config->shadow_reg_cfg,
  1473. sizeof(struct wlfw_shadow_reg_cfg_s_v01) *
  1474. req->shadow_reg_len);
  1475. } else {
  1476. req->shadow_reg_v2_valid = 1;
  1477. if (config->num_shadow_reg_v2_cfg >
  1478. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01)
  1479. req->shadow_reg_v2_len =
  1480. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01;
  1481. else
  1482. req->shadow_reg_v2_len =
  1483. config->num_shadow_reg_v2_cfg;
  1484. memcpy(req->shadow_reg_v2, config->shadow_reg_v2_cfg,
  1485. sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01) *
  1486. req->shadow_reg_v2_len);
  1487. }
  1488. } else {
  1489. req->shadow_reg_v3_valid = 1;
  1490. if (config->num_shadow_reg_v3_cfg >
  1491. MAX_NUM_SHADOW_REG_V3)
  1492. req->shadow_reg_v3_len = MAX_NUM_SHADOW_REG_V3;
  1493. else
  1494. req->shadow_reg_v3_len = config->num_shadow_reg_v3_cfg;
  1495. plat_priv->num_shadow_regs_v3 = req->shadow_reg_v3_len;
  1496. cnss_pr_dbg("Shadow reg v3 len: %d\n",
  1497. plat_priv->num_shadow_regs_v3);
  1498. memcpy(req->shadow_reg_v3, config->shadow_reg_v3_cfg,
  1499. sizeof(struct wlfw_shadow_reg_v3_cfg_s_v01) *
  1500. req->shadow_reg_v3_len);
  1501. }
  1502. if (config->rri_over_ddr_cfg_valid) {
  1503. req->rri_over_ddr_cfg_valid = 1;
  1504. req->rri_over_ddr_cfg.base_addr_low =
  1505. config->rri_over_ddr_cfg.base_addr_low;
  1506. req->rri_over_ddr_cfg.base_addr_high =
  1507. config->rri_over_ddr_cfg.base_addr_high;
  1508. }
  1509. if (config->send_msi_ce) {
  1510. ret = cnss_bus_get_msi_assignment(plat_priv,
  1511. CE_MSI_NAME,
  1512. &num_vectors,
  1513. &user_base_data,
  1514. &base_vector);
  1515. if (!ret) {
  1516. req->msi_cfg_valid = 1;
  1517. req->msi_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1518. for (ce_id = 0; ce_id < QMI_WLFW_MAX_NUM_CE_V01;
  1519. ce_id++) {
  1520. req->msi_cfg[ce_id].ce_id = ce_id;
  1521. req->msi_cfg[ce_id].msi_vector =
  1522. (ce_id % num_vectors) + base_vector;
  1523. }
  1524. }
  1525. }
  1526. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1527. wlfw_wlan_cfg_resp_msg_v01_ei, resp);
  1528. if (ret < 0) {
  1529. cnss_pr_err("Failed to initialize txn for WLAN config request, err: %d\n",
  1530. ret);
  1531. goto out;
  1532. }
  1533. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1534. QMI_WLFW_WLAN_CFG_REQ_V01,
  1535. WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN,
  1536. wlfw_wlan_cfg_req_msg_v01_ei, req);
  1537. if (ret < 0) {
  1538. qmi_txn_cancel(&txn);
  1539. cnss_pr_err("Failed to send WLAN config request, err: %d\n",
  1540. ret);
  1541. goto out;
  1542. }
  1543. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1544. if (ret < 0) {
  1545. cnss_pr_err("Failed to wait for response of WLAN config request, err: %d\n",
  1546. ret);
  1547. goto out;
  1548. }
  1549. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1550. cnss_pr_err("WLAN config request failed, result: %d, err: %d\n",
  1551. resp->resp.result, resp->resp.error);
  1552. ret = -resp->resp.result;
  1553. goto out;
  1554. }
  1555. kfree(req);
  1556. kfree(resp);
  1557. return 0;
  1558. out:
  1559. CNSS_QMI_ASSERT();
  1560. kfree(req);
  1561. kfree(resp);
  1562. return ret;
  1563. }
  1564. int cnss_wlfw_athdiag_read_send_sync(struct cnss_plat_data *plat_priv,
  1565. u32 offset, u32 mem_type,
  1566. u32 data_len, u8 *data)
  1567. {
  1568. struct wlfw_athdiag_read_req_msg_v01 *req;
  1569. struct wlfw_athdiag_read_resp_msg_v01 *resp;
  1570. struct qmi_txn txn;
  1571. int ret = 0;
  1572. if (!plat_priv)
  1573. return -ENODEV;
  1574. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1575. cnss_pr_err("Invalid parameters for athdiag read: data %pK, data_len %u\n",
  1576. data, data_len);
  1577. return -EINVAL;
  1578. }
  1579. cnss_pr_dbg("athdiag read: state 0x%lx, offset %x, mem_type %x, data_len %u\n",
  1580. plat_priv->driver_state, offset, mem_type, data_len);
  1581. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1582. if (!req)
  1583. return -ENOMEM;
  1584. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1585. if (!resp) {
  1586. kfree(req);
  1587. return -ENOMEM;
  1588. }
  1589. req->offset = offset;
  1590. req->mem_type = mem_type;
  1591. req->data_len = data_len;
  1592. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1593. wlfw_athdiag_read_resp_msg_v01_ei, resp);
  1594. if (ret < 0) {
  1595. cnss_pr_err("Failed to initialize txn for athdiag read request, err: %d\n",
  1596. ret);
  1597. goto out;
  1598. }
  1599. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1600. QMI_WLFW_ATHDIAG_READ_REQ_V01,
  1601. WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN,
  1602. wlfw_athdiag_read_req_msg_v01_ei, req);
  1603. if (ret < 0) {
  1604. qmi_txn_cancel(&txn);
  1605. cnss_pr_err("Failed to send athdiag read request, err: %d\n",
  1606. ret);
  1607. goto out;
  1608. }
  1609. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1610. if (ret < 0) {
  1611. cnss_pr_err("Failed to wait for response of athdiag read request, err: %d\n",
  1612. ret);
  1613. goto out;
  1614. }
  1615. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1616. cnss_pr_err("Athdiag read request failed, result: %d, err: %d\n",
  1617. resp->resp.result, resp->resp.error);
  1618. ret = -resp->resp.result;
  1619. goto out;
  1620. }
  1621. if (!resp->data_valid || resp->data_len != data_len) {
  1622. cnss_pr_err("athdiag read data is invalid, data_valid = %u, data_len = %u\n",
  1623. resp->data_valid, resp->data_len);
  1624. ret = -EINVAL;
  1625. goto out;
  1626. }
  1627. memcpy(data, resp->data, resp->data_len);
  1628. kfree(req);
  1629. kfree(resp);
  1630. return 0;
  1631. out:
  1632. kfree(req);
  1633. kfree(resp);
  1634. return ret;
  1635. }
  1636. int cnss_wlfw_athdiag_write_send_sync(struct cnss_plat_data *plat_priv,
  1637. u32 offset, u32 mem_type,
  1638. u32 data_len, u8 *data)
  1639. {
  1640. struct wlfw_athdiag_write_req_msg_v01 *req;
  1641. struct wlfw_athdiag_write_resp_msg_v01 *resp;
  1642. struct qmi_txn txn;
  1643. int ret = 0;
  1644. if (!plat_priv)
  1645. return -ENODEV;
  1646. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1647. cnss_pr_err("Invalid parameters for athdiag write: data %pK, data_len %u\n",
  1648. data, data_len);
  1649. return -EINVAL;
  1650. }
  1651. cnss_pr_dbg("athdiag write: state 0x%lx, offset %x, mem_type %x, data_len %u, data %pK\n",
  1652. plat_priv->driver_state, offset, mem_type, data_len, data);
  1653. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1654. if (!req)
  1655. return -ENOMEM;
  1656. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1657. if (!resp) {
  1658. kfree(req);
  1659. return -ENOMEM;
  1660. }
  1661. req->offset = offset;
  1662. req->mem_type = mem_type;
  1663. req->data_len = data_len;
  1664. memcpy(req->data, data, data_len);
  1665. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1666. wlfw_athdiag_write_resp_msg_v01_ei, resp);
  1667. if (ret < 0) {
  1668. cnss_pr_err("Failed to initialize txn for athdiag write request, err: %d\n",
  1669. ret);
  1670. goto out;
  1671. }
  1672. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1673. QMI_WLFW_ATHDIAG_WRITE_REQ_V01,
  1674. WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN,
  1675. wlfw_athdiag_write_req_msg_v01_ei, req);
  1676. if (ret < 0) {
  1677. qmi_txn_cancel(&txn);
  1678. cnss_pr_err("Failed to send athdiag write request, err: %d\n",
  1679. ret);
  1680. goto out;
  1681. }
  1682. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1683. if (ret < 0) {
  1684. cnss_pr_err("Failed to wait for response of athdiag write request, err: %d\n",
  1685. ret);
  1686. goto out;
  1687. }
  1688. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1689. cnss_pr_err("Athdiag write request failed, result: %d, err: %d\n",
  1690. resp->resp.result, resp->resp.error);
  1691. ret = -resp->resp.result;
  1692. goto out;
  1693. }
  1694. kfree(req);
  1695. kfree(resp);
  1696. return 0;
  1697. out:
  1698. kfree(req);
  1699. kfree(resp);
  1700. return ret;
  1701. }
  1702. int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv,
  1703. u8 fw_log_mode)
  1704. {
  1705. struct wlfw_ini_req_msg_v01 *req;
  1706. struct wlfw_ini_resp_msg_v01 *resp;
  1707. struct qmi_txn txn;
  1708. int ret = 0;
  1709. if (!plat_priv)
  1710. return -ENODEV;
  1711. cnss_pr_dbg("Sending ini sync request, state: 0x%lx, fw_log_mode: %d\n",
  1712. plat_priv->driver_state, fw_log_mode);
  1713. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1714. if (!req)
  1715. return -ENOMEM;
  1716. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1717. if (!resp) {
  1718. kfree(req);
  1719. return -ENOMEM;
  1720. }
  1721. req->enablefwlog_valid = 1;
  1722. req->enablefwlog = fw_log_mode;
  1723. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1724. wlfw_ini_resp_msg_v01_ei, resp);
  1725. if (ret < 0) {
  1726. cnss_pr_err("Failed to initialize txn for ini request, fw_log_mode: %d, err: %d\n",
  1727. fw_log_mode, ret);
  1728. goto out;
  1729. }
  1730. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1731. QMI_WLFW_INI_REQ_V01,
  1732. WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN,
  1733. wlfw_ini_req_msg_v01_ei, req);
  1734. if (ret < 0) {
  1735. qmi_txn_cancel(&txn);
  1736. cnss_pr_err("Failed to send ini request, fw_log_mode: %d, err: %d\n",
  1737. fw_log_mode, ret);
  1738. goto out;
  1739. }
  1740. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1741. if (ret < 0) {
  1742. cnss_pr_err("Failed to wait for response of ini request, fw_log_mode: %d, err: %d\n",
  1743. fw_log_mode, ret);
  1744. goto out;
  1745. }
  1746. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1747. cnss_pr_err("Ini request failed, fw_log_mode: %d, result: %d, err: %d\n",
  1748. fw_log_mode, resp->resp.result, resp->resp.error);
  1749. ret = -resp->resp.result;
  1750. goto out;
  1751. }
  1752. kfree(req);
  1753. kfree(resp);
  1754. return 0;
  1755. out:
  1756. kfree(req);
  1757. kfree(resp);
  1758. return ret;
  1759. }
  1760. int cnss_wlfw_send_pcie_gen_speed_sync(struct cnss_plat_data *plat_priv)
  1761. {
  1762. struct wlfw_pcie_gen_switch_req_msg_v01 req;
  1763. struct wlfw_pcie_gen_switch_resp_msg_v01 resp = {0};
  1764. struct qmi_txn txn;
  1765. int ret = 0;
  1766. if (!plat_priv)
  1767. return -ENODEV;
  1768. if (plat_priv->pcie_gen_speed == QMI_PCIE_GEN_SPEED_INVALID_V01 ||
  1769. !plat_priv->fw_pcie_gen_switch) {
  1770. cnss_pr_dbg("PCIE Gen speed not setup\n");
  1771. return 0;
  1772. }
  1773. cnss_pr_dbg("Sending PCIE Gen speed: %d state: 0x%lx\n",
  1774. plat_priv->pcie_gen_speed, plat_priv->driver_state);
  1775. req.pcie_speed = (enum wlfw_pcie_gen_speed_v01)
  1776. plat_priv->pcie_gen_speed;
  1777. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1778. wlfw_pcie_gen_switch_resp_msg_v01_ei, &resp);
  1779. if (ret < 0) {
  1780. cnss_pr_err("Failed to initialize txn for PCIE speed switch err: %d\n",
  1781. ret);
  1782. goto out;
  1783. }
  1784. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1785. QMI_WLFW_PCIE_GEN_SWITCH_REQ_V01,
  1786. WLFW_PCIE_GEN_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1787. wlfw_pcie_gen_switch_req_msg_v01_ei, &req);
  1788. if (ret < 0) {
  1789. qmi_txn_cancel(&txn);
  1790. cnss_pr_err("Failed to send PCIE speed switch, err: %d\n", ret);
  1791. goto out;
  1792. }
  1793. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1794. if (ret < 0) {
  1795. cnss_pr_err("Failed to wait for PCIE Gen switch resp, err: %d\n",
  1796. ret);
  1797. goto out;
  1798. }
  1799. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1800. cnss_pr_err("PCIE Gen Switch req failed, Speed: %d, result: %d, err: %d\n",
  1801. plat_priv->pcie_gen_speed, resp.resp.result,
  1802. resp.resp.error);
  1803. ret = -resp.resp.result;
  1804. }
  1805. out:
  1806. /* Reset PCIE Gen speed after one time use */
  1807. plat_priv->pcie_gen_speed = QMI_PCIE_GEN_SPEED_INVALID_V01;
  1808. return ret;
  1809. }
  1810. int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv)
  1811. {
  1812. struct wlfw_antenna_switch_req_msg_v01 *req;
  1813. struct wlfw_antenna_switch_resp_msg_v01 *resp;
  1814. struct qmi_txn txn;
  1815. int ret = 0;
  1816. if (!plat_priv)
  1817. return -ENODEV;
  1818. cnss_pr_dbg("Sending antenna switch sync request, state: 0x%lx\n",
  1819. plat_priv->driver_state);
  1820. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1821. if (!req)
  1822. return -ENOMEM;
  1823. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1824. if (!resp) {
  1825. kfree(req);
  1826. return -ENOMEM;
  1827. }
  1828. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1829. wlfw_antenna_switch_resp_msg_v01_ei, resp);
  1830. if (ret < 0) {
  1831. cnss_pr_err("Failed to initialize txn for antenna switch request, err: %d\n",
  1832. ret);
  1833. goto out;
  1834. }
  1835. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1836. QMI_WLFW_ANTENNA_SWITCH_REQ_V01,
  1837. WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1838. wlfw_antenna_switch_req_msg_v01_ei, req);
  1839. if (ret < 0) {
  1840. qmi_txn_cancel(&txn);
  1841. cnss_pr_err("Failed to send antenna switch request, err: %d\n",
  1842. ret);
  1843. goto out;
  1844. }
  1845. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1846. if (ret < 0) {
  1847. cnss_pr_err("Failed to wait for response of antenna switch request, err: %d\n",
  1848. ret);
  1849. goto out;
  1850. }
  1851. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1852. cnss_pr_dbg("Antenna switch request failed, result: %d, err: %d\n",
  1853. resp->resp.result, resp->resp.error);
  1854. ret = -resp->resp.result;
  1855. goto out;
  1856. }
  1857. if (resp->antenna_valid)
  1858. plat_priv->antenna = resp->antenna;
  1859. cnss_pr_dbg("Antenna valid: %u, antenna 0x%llx\n",
  1860. resp->antenna_valid, resp->antenna);
  1861. kfree(req);
  1862. kfree(resp);
  1863. return 0;
  1864. out:
  1865. kfree(req);
  1866. kfree(resp);
  1867. return ret;
  1868. }
  1869. int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv)
  1870. {
  1871. struct wlfw_antenna_grant_req_msg_v01 *req;
  1872. struct wlfw_antenna_grant_resp_msg_v01 *resp;
  1873. struct qmi_txn txn;
  1874. int ret = 0;
  1875. if (!plat_priv)
  1876. return -ENODEV;
  1877. cnss_pr_dbg("Sending antenna grant sync request, state: 0x%lx, grant 0x%llx\n",
  1878. plat_priv->driver_state, plat_priv->grant);
  1879. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1880. if (!req)
  1881. return -ENOMEM;
  1882. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1883. if (!resp) {
  1884. kfree(req);
  1885. return -ENOMEM;
  1886. }
  1887. req->grant_valid = 1;
  1888. req->grant = plat_priv->grant;
  1889. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1890. wlfw_antenna_grant_resp_msg_v01_ei, resp);
  1891. if (ret < 0) {
  1892. cnss_pr_err("Failed to initialize txn for antenna grant request, err: %d\n",
  1893. ret);
  1894. goto out;
  1895. }
  1896. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1897. QMI_WLFW_ANTENNA_GRANT_REQ_V01,
  1898. WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN,
  1899. wlfw_antenna_grant_req_msg_v01_ei, req);
  1900. if (ret < 0) {
  1901. qmi_txn_cancel(&txn);
  1902. cnss_pr_err("Failed to send antenna grant request, err: %d\n",
  1903. ret);
  1904. goto out;
  1905. }
  1906. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1907. if (ret < 0) {
  1908. cnss_pr_err("Failed to wait for response of antenna grant request, err: %d\n",
  1909. ret);
  1910. goto out;
  1911. }
  1912. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1913. cnss_pr_err("Antenna grant request failed, result: %d, err: %d\n",
  1914. resp->resp.result, resp->resp.error);
  1915. ret = -resp->resp.result;
  1916. goto out;
  1917. }
  1918. kfree(req);
  1919. kfree(resp);
  1920. return 0;
  1921. out:
  1922. kfree(req);
  1923. kfree(resp);
  1924. return ret;
  1925. }
  1926. int cnss_wlfw_qdss_trace_mem_info_send_sync(struct cnss_plat_data *plat_priv)
  1927. {
  1928. struct wlfw_qdss_trace_mem_info_req_msg_v01 *req;
  1929. struct wlfw_qdss_trace_mem_info_resp_msg_v01 *resp;
  1930. struct qmi_txn txn;
  1931. struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem;
  1932. int ret = 0;
  1933. int i;
  1934. cnss_pr_dbg("Sending QDSS trace mem info, state: 0x%lx\n",
  1935. plat_priv->driver_state);
  1936. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1937. if (!req)
  1938. return -ENOMEM;
  1939. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1940. if (!resp) {
  1941. kfree(req);
  1942. return -ENOMEM;
  1943. }
  1944. if (plat_priv->qdss_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  1945. cnss_pr_err("Invalid seg len %u\n", plat_priv->qdss_mem_seg_len);
  1946. ret = -EINVAL;
  1947. goto out;
  1948. }
  1949. req->mem_seg_len = plat_priv->qdss_mem_seg_len;
  1950. for (i = 0; i < req->mem_seg_len; i++) {
  1951. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  1952. qdss_mem[i].va, &qdss_mem[i].pa,
  1953. qdss_mem[i].size, qdss_mem[i].type);
  1954. req->mem_seg[i].addr = qdss_mem[i].pa;
  1955. req->mem_seg[i].size = qdss_mem[i].size;
  1956. req->mem_seg[i].type = qdss_mem[i].type;
  1957. }
  1958. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1959. wlfw_qdss_trace_mem_info_resp_msg_v01_ei, resp);
  1960. if (ret < 0) {
  1961. cnss_pr_err("Fail to initialize txn for QDSS trace mem request: err %d\n",
  1962. ret);
  1963. goto out;
  1964. }
  1965. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1966. QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01,
  1967. WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  1968. wlfw_qdss_trace_mem_info_req_msg_v01_ei, req);
  1969. if (ret < 0) {
  1970. qmi_txn_cancel(&txn);
  1971. cnss_pr_err("Fail to send QDSS trace mem info request: err %d\n",
  1972. ret);
  1973. goto out;
  1974. }
  1975. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1976. if (ret < 0) {
  1977. cnss_pr_err("Fail to wait for response of QDSS trace mem info request, err %d\n",
  1978. ret);
  1979. goto out;
  1980. }
  1981. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1982. cnss_pr_err("QDSS trace mem info request failed, result: %d, err: %d\n",
  1983. resp->resp.result, resp->resp.error);
  1984. ret = -resp->resp.result;
  1985. goto out;
  1986. }
  1987. kfree(req);
  1988. kfree(resp);
  1989. return 0;
  1990. out:
  1991. kfree(req);
  1992. kfree(resp);
  1993. return ret;
  1994. }
  1995. int cnss_wlfw_send_host_wfc_call_status(struct cnss_plat_data *plat_priv,
  1996. struct cnss_wfc_cfg cfg)
  1997. {
  1998. struct wlfw_wfc_call_status_req_msg_v01 *req;
  1999. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2000. struct qmi_txn txn;
  2001. int ret = 0;
  2002. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2003. cnss_pr_err("Drop host WFC indication as FW not initialized\n");
  2004. return -EINVAL;
  2005. }
  2006. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2007. if (!req)
  2008. return -ENOMEM;
  2009. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2010. if (!resp) {
  2011. kfree(req);
  2012. return -ENOMEM;
  2013. }
  2014. req->wfc_call_active_valid = 1;
  2015. req->wfc_call_active = cfg.mode;
  2016. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2017. plat_priv->driver_state);
  2018. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2019. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2020. if (ret < 0) {
  2021. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2022. ret);
  2023. goto out;
  2024. }
  2025. cnss_pr_dbg("Send WFC Mode: %d\n", cfg.mode);
  2026. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2027. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2028. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2029. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2030. if (ret < 0) {
  2031. qmi_txn_cancel(&txn);
  2032. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2033. ret);
  2034. goto out;
  2035. }
  2036. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2037. if (ret < 0) {
  2038. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2039. ret);
  2040. goto out;
  2041. }
  2042. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2043. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2044. resp->resp.result, resp->resp.error);
  2045. ret = -EINVAL;
  2046. goto out;
  2047. }
  2048. ret = 0;
  2049. out:
  2050. kfree(req);
  2051. kfree(resp);
  2052. return ret;
  2053. }
  2054. static int cnss_wlfw_wfc_call_status_send_sync
  2055. (struct cnss_plat_data *plat_priv,
  2056. const struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg)
  2057. {
  2058. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2059. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2060. struct qmi_txn txn;
  2061. int ret = 0;
  2062. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2063. cnss_pr_err("Drop IMS WFC indication as FW not initialized\n");
  2064. return -EINVAL;
  2065. }
  2066. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2067. if (!req)
  2068. return -ENOMEM;
  2069. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2070. if (!resp) {
  2071. kfree(req);
  2072. return -ENOMEM;
  2073. }
  2074. /**
  2075. * WFC Call r1 design has CNSS as pass thru using opaque hex buffer.
  2076. * But in r2 update QMI structure is expanded and as an effect qmi
  2077. * decoded structures have padding. Thus we cannot use buffer design.
  2078. * For backward compatibility for r1 design copy only wfc_call_active
  2079. * value in hex buffer.
  2080. */
  2081. req->wfc_call_status_len = sizeof(ind_msg->wfc_call_active);
  2082. req->wfc_call_status[0] = ind_msg->wfc_call_active;
  2083. /* wfc_call_active is mandatory in IMS indication */
  2084. req->wfc_call_active_valid = 1;
  2085. req->wfc_call_active = ind_msg->wfc_call_active;
  2086. req->all_wfc_calls_held_valid = ind_msg->all_wfc_calls_held_valid;
  2087. req->all_wfc_calls_held = ind_msg->all_wfc_calls_held;
  2088. req->is_wfc_emergency_valid = ind_msg->is_wfc_emergency_valid;
  2089. req->is_wfc_emergency = ind_msg->is_wfc_emergency;
  2090. req->twt_ims_start_valid = ind_msg->twt_ims_start_valid;
  2091. req->twt_ims_start = ind_msg->twt_ims_start;
  2092. req->twt_ims_int_valid = ind_msg->twt_ims_int_valid;
  2093. req->twt_ims_int = ind_msg->twt_ims_int;
  2094. req->media_quality_valid = ind_msg->media_quality_valid;
  2095. req->media_quality =
  2096. (enum wlfw_wfc_media_quality_v01)ind_msg->media_quality;
  2097. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2098. plat_priv->driver_state);
  2099. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2100. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2101. if (ret < 0) {
  2102. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2103. ret);
  2104. goto out;
  2105. }
  2106. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2107. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2108. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2109. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2110. if (ret < 0) {
  2111. qmi_txn_cancel(&txn);
  2112. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2113. ret);
  2114. goto out;
  2115. }
  2116. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2117. if (ret < 0) {
  2118. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2119. ret);
  2120. goto out;
  2121. }
  2122. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2123. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2124. resp->resp.result, resp->resp.error);
  2125. ret = -resp->resp.result;
  2126. goto out;
  2127. }
  2128. ret = 0;
  2129. out:
  2130. kfree(req);
  2131. kfree(resp);
  2132. return ret;
  2133. }
  2134. int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv)
  2135. {
  2136. struct wlfw_dynamic_feature_mask_req_msg_v01 *req;
  2137. struct wlfw_dynamic_feature_mask_resp_msg_v01 *resp;
  2138. struct qmi_txn txn;
  2139. int ret = 0;
  2140. cnss_pr_dbg("Sending dynamic feature mask 0x%llx, state: 0x%lx\n",
  2141. plat_priv->dynamic_feature,
  2142. plat_priv->driver_state);
  2143. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2144. if (!req)
  2145. return -ENOMEM;
  2146. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2147. if (!resp) {
  2148. kfree(req);
  2149. return -ENOMEM;
  2150. }
  2151. req->mask_valid = 1;
  2152. req->mask = plat_priv->dynamic_feature;
  2153. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2154. wlfw_dynamic_feature_mask_resp_msg_v01_ei, resp);
  2155. if (ret < 0) {
  2156. cnss_pr_err("Fail to initialize txn for dynamic feature mask request: err %d\n",
  2157. ret);
  2158. goto out;
  2159. }
  2160. ret = qmi_send_request
  2161. (&plat_priv->qmi_wlfw, NULL, &txn,
  2162. QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01,
  2163. WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN,
  2164. wlfw_dynamic_feature_mask_req_msg_v01_ei, req);
  2165. if (ret < 0) {
  2166. qmi_txn_cancel(&txn);
  2167. cnss_pr_err("Fail to send dynamic feature mask request: err %d\n",
  2168. ret);
  2169. goto out;
  2170. }
  2171. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2172. if (ret < 0) {
  2173. cnss_pr_err("Fail to wait for response of dynamic feature mask request, err %d\n",
  2174. ret);
  2175. goto out;
  2176. }
  2177. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2178. cnss_pr_err("Dynamic feature mask request failed, result: %d, err: %d\n",
  2179. resp->resp.result, resp->resp.error);
  2180. ret = -resp->resp.result;
  2181. goto out;
  2182. }
  2183. out:
  2184. kfree(req);
  2185. kfree(resp);
  2186. return ret;
  2187. }
  2188. int cnss_wlfw_get_info_send_sync(struct cnss_plat_data *plat_priv, int type,
  2189. void *cmd, int cmd_len)
  2190. {
  2191. struct wlfw_get_info_req_msg_v01 *req;
  2192. struct wlfw_get_info_resp_msg_v01 *resp;
  2193. struct qmi_txn txn;
  2194. int ret = 0;
  2195. cnss_pr_buf("Sending get info message, type: %d, cmd length: %d, state: 0x%lx\n",
  2196. type, cmd_len, plat_priv->driver_state);
  2197. if (cmd_len > QMI_WLFW_MAX_DATA_SIZE_V01)
  2198. return -EINVAL;
  2199. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2200. if (!req)
  2201. return -ENOMEM;
  2202. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2203. if (!resp) {
  2204. kfree(req);
  2205. return -ENOMEM;
  2206. }
  2207. req->type = type;
  2208. req->data_len = cmd_len;
  2209. memcpy(req->data, cmd, req->data_len);
  2210. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2211. wlfw_get_info_resp_msg_v01_ei, resp);
  2212. if (ret < 0) {
  2213. cnss_pr_err("Failed to initialize txn for get info request, err: %d\n",
  2214. ret);
  2215. goto out;
  2216. }
  2217. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2218. QMI_WLFW_GET_INFO_REQ_V01,
  2219. WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2220. wlfw_get_info_req_msg_v01_ei, req);
  2221. if (ret < 0) {
  2222. qmi_txn_cancel(&txn);
  2223. cnss_pr_err("Failed to send get info request, err: %d\n",
  2224. ret);
  2225. goto out;
  2226. }
  2227. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2228. if (ret < 0) {
  2229. cnss_pr_err("Failed to wait for response of get info request, err: %d\n",
  2230. ret);
  2231. goto out;
  2232. }
  2233. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2234. cnss_pr_err("Get info request failed, result: %d, err: %d\n",
  2235. resp->resp.result, resp->resp.error);
  2236. ret = -resp->resp.result;
  2237. goto out;
  2238. }
  2239. kfree(req);
  2240. kfree(resp);
  2241. return 0;
  2242. out:
  2243. kfree(req);
  2244. kfree(resp);
  2245. return ret;
  2246. }
  2247. unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv)
  2248. {
  2249. return QMI_WLFW_TIMEOUT_MS;
  2250. }
  2251. static void cnss_wlfw_request_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2252. struct sockaddr_qrtr *sq,
  2253. struct qmi_txn *txn, const void *data)
  2254. {
  2255. struct cnss_plat_data *plat_priv =
  2256. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2257. const struct wlfw_request_mem_ind_msg_v01 *ind_msg = data;
  2258. int i;
  2259. cnss_pr_dbg("Received QMI WLFW request memory indication\n");
  2260. if (!txn) {
  2261. cnss_pr_err("Spurious indication\n");
  2262. return;
  2263. }
  2264. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2265. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2266. return;
  2267. }
  2268. plat_priv->fw_mem_seg_len = ind_msg->mem_seg_len;
  2269. for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
  2270. cnss_pr_dbg("FW requests for memory, size: 0x%x, type: %u\n",
  2271. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2272. plat_priv->fw_mem[i].type = ind_msg->mem_seg[i].type;
  2273. plat_priv->fw_mem[i].size = ind_msg->mem_seg[i].size;
  2274. if (!plat_priv->fw_mem[i].va &&
  2275. plat_priv->fw_mem[i].type == CNSS_MEM_TYPE_DDR)
  2276. plat_priv->fw_mem[i].attrs |=
  2277. DMA_ATTR_FORCE_CONTIGUOUS;
  2278. if (plat_priv->fw_mem[i].type == CNSS_MEM_CAL_V01)
  2279. plat_priv->cal_mem = &plat_priv->fw_mem[i];
  2280. }
  2281. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_REQUEST_MEM,
  2282. 0, NULL);
  2283. }
  2284. static void cnss_wlfw_fw_mem_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2285. struct sockaddr_qrtr *sq,
  2286. struct qmi_txn *txn, const void *data)
  2287. {
  2288. struct cnss_plat_data *plat_priv =
  2289. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2290. cnss_pr_dbg("Received QMI WLFW FW memory ready indication\n");
  2291. if (!txn) {
  2292. cnss_pr_err("Spurious indication\n");
  2293. return;
  2294. }
  2295. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_READY,
  2296. 0, NULL);
  2297. }
  2298. /**
  2299. * cnss_wlfw_fw_ready_ind_cb: FW ready indication handler (Helium arch)
  2300. *
  2301. * This event is not required for HST/ HSP as FW calibration done is
  2302. * provided in QMI_WLFW_CAL_DONE_IND_V01
  2303. */
  2304. static void cnss_wlfw_fw_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2305. struct sockaddr_qrtr *sq,
  2306. struct qmi_txn *txn, const void *data)
  2307. {
  2308. struct cnss_plat_data *plat_priv =
  2309. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2310. struct cnss_cal_info *cal_info;
  2311. if (!txn) {
  2312. cnss_pr_err("Spurious indication\n");
  2313. return;
  2314. }
  2315. if (plat_priv->device_id == QCA6390_DEVICE_ID ||
  2316. plat_priv->device_id == QCA6490_DEVICE_ID) {
  2317. cnss_pr_dbg("Ignore FW Ready Indication for HST/HSP");
  2318. return;
  2319. }
  2320. cnss_pr_dbg("Received QMI WLFW FW ready indication.\n");
  2321. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2322. if (!cal_info)
  2323. return;
  2324. cal_info->cal_status = CNSS_CAL_DONE;
  2325. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2326. 0, cal_info);
  2327. }
  2328. static void cnss_wlfw_fw_init_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2329. struct sockaddr_qrtr *sq,
  2330. struct qmi_txn *txn, const void *data)
  2331. {
  2332. struct cnss_plat_data *plat_priv =
  2333. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2334. cnss_pr_dbg("Received QMI WLFW FW initialization done indication\n");
  2335. if (!txn) {
  2336. cnss_pr_err("Spurious indication\n");
  2337. return;
  2338. }
  2339. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_READY, 0, NULL);
  2340. }
  2341. static void cnss_wlfw_pin_result_ind_cb(struct qmi_handle *qmi_wlfw,
  2342. struct sockaddr_qrtr *sq,
  2343. struct qmi_txn *txn, const void *data)
  2344. {
  2345. struct cnss_plat_data *plat_priv =
  2346. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2347. const struct wlfw_pin_connect_result_ind_msg_v01 *ind_msg = data;
  2348. cnss_pr_dbg("Received QMI WLFW pin connect result indication\n");
  2349. if (!txn) {
  2350. cnss_pr_err("Spurious indication\n");
  2351. return;
  2352. }
  2353. if (ind_msg->pwr_pin_result_valid)
  2354. plat_priv->pin_result.fw_pwr_pin_result =
  2355. ind_msg->pwr_pin_result;
  2356. if (ind_msg->phy_io_pin_result_valid)
  2357. plat_priv->pin_result.fw_phy_io_pin_result =
  2358. ind_msg->phy_io_pin_result;
  2359. if (ind_msg->rf_pin_result_valid)
  2360. plat_priv->pin_result.fw_rf_pin_result = ind_msg->rf_pin_result;
  2361. cnss_pr_dbg("Pin connect Result: pwr_pin: 0x%x phy_io_pin: 0x%x rf_io_pin: 0x%x\n",
  2362. ind_msg->pwr_pin_result, ind_msg->phy_io_pin_result,
  2363. ind_msg->rf_pin_result);
  2364. }
  2365. int cnss_wlfw_cal_report_req_send_sync(struct cnss_plat_data *plat_priv,
  2366. u32 cal_file_download_size)
  2367. {
  2368. struct wlfw_cal_report_req_msg_v01 req = {0};
  2369. struct wlfw_cal_report_resp_msg_v01 resp = {0};
  2370. struct qmi_txn txn;
  2371. int ret = 0;
  2372. cnss_pr_dbg("Sending cal file report request. File size: %d, state: 0x%lx\n",
  2373. cal_file_download_size, plat_priv->driver_state);
  2374. req.cal_file_download_size_valid = 1;
  2375. req.cal_file_download_size = cal_file_download_size;
  2376. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2377. wlfw_cal_report_resp_msg_v01_ei, &resp);
  2378. if (ret < 0) {
  2379. cnss_pr_err("Failed to initialize txn for Cal Report request, err: %d\n",
  2380. ret);
  2381. goto out;
  2382. }
  2383. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2384. QMI_WLFW_CAL_REPORT_REQ_V01,
  2385. WLFW_CAL_REPORT_REQ_MSG_V01_MAX_MSG_LEN,
  2386. wlfw_cal_report_req_msg_v01_ei, &req);
  2387. if (ret < 0) {
  2388. qmi_txn_cancel(&txn);
  2389. cnss_pr_err("Failed to send Cal Report request, err: %d\n",
  2390. ret);
  2391. goto out;
  2392. }
  2393. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2394. if (ret < 0) {
  2395. cnss_pr_err("Failed to wait for response of Cal Report request, err: %d\n",
  2396. ret);
  2397. goto out;
  2398. }
  2399. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  2400. cnss_pr_err("Cal Report request failed, result: %d, err: %d\n",
  2401. resp.resp.result, resp.resp.error);
  2402. ret = -resp.resp.result;
  2403. goto out;
  2404. }
  2405. out:
  2406. return ret;
  2407. }
  2408. static void cnss_wlfw_cal_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2409. struct sockaddr_qrtr *sq,
  2410. struct qmi_txn *txn, const void *data)
  2411. {
  2412. struct cnss_plat_data *plat_priv =
  2413. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2414. const struct wlfw_cal_done_ind_msg_v01 *ind = data;
  2415. struct cnss_cal_info *cal_info;
  2416. cnss_pr_dbg("Received Cal done indication. File size: %d\n",
  2417. ind->cal_file_upload_size);
  2418. cnss_pr_info("Calibration took %d ms\n",
  2419. jiffies_to_msecs(jiffies - plat_priv->cal_time));
  2420. if (!txn) {
  2421. cnss_pr_err("Spurious indication\n");
  2422. return;
  2423. }
  2424. if (ind->cal_file_upload_size_valid)
  2425. plat_priv->cal_file_size = ind->cal_file_upload_size;
  2426. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2427. if (!cal_info)
  2428. return;
  2429. cal_info->cal_status = CNSS_CAL_DONE;
  2430. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2431. 0, cal_info);
  2432. }
  2433. static void cnss_wlfw_qdss_trace_req_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2434. struct sockaddr_qrtr *sq,
  2435. struct qmi_txn *txn,
  2436. const void *data)
  2437. {
  2438. struct cnss_plat_data *plat_priv =
  2439. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2440. const struct wlfw_qdss_trace_req_mem_ind_msg_v01 *ind_msg = data;
  2441. int i;
  2442. cnss_pr_dbg("Received QMI WLFW QDSS trace request mem indication\n");
  2443. if (!txn) {
  2444. cnss_pr_err("Spurious indication\n");
  2445. return;
  2446. }
  2447. if (plat_priv->qdss_mem_seg_len) {
  2448. cnss_pr_err("Ignore double allocation for QDSS trace, current len %u\n",
  2449. plat_priv->qdss_mem_seg_len);
  2450. return;
  2451. }
  2452. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2453. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2454. return;
  2455. }
  2456. plat_priv->qdss_mem_seg_len = ind_msg->mem_seg_len;
  2457. for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) {
  2458. cnss_pr_dbg("QDSS requests for memory, size: 0x%x, type: %u\n",
  2459. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2460. plat_priv->qdss_mem[i].type = ind_msg->mem_seg[i].type;
  2461. plat_priv->qdss_mem[i].size = ind_msg->mem_seg[i].size;
  2462. }
  2463. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
  2464. 0, NULL);
  2465. }
  2466. /**
  2467. * cnss_wlfw_fw_mem_file_save_ind_cb: Save given FW mem to filesystem
  2468. *
  2469. * QDSS_TRACE_SAVE_IND feature is overloaded to provide any host allocated
  2470. * fw memory segment for dumping to file system. Only one type of mem can be
  2471. * saved per indication and is provided in mem seg index 0.
  2472. *
  2473. * Return: None
  2474. */
  2475. static void cnss_wlfw_fw_mem_file_save_ind_cb(struct qmi_handle *qmi_wlfw,
  2476. struct sockaddr_qrtr *sq,
  2477. struct qmi_txn *txn,
  2478. const void *data)
  2479. {
  2480. struct cnss_plat_data *plat_priv =
  2481. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2482. const struct wlfw_qdss_trace_save_ind_msg_v01 *ind_msg = data;
  2483. struct cnss_qmi_event_fw_mem_file_save_data *event_data;
  2484. int i = 0;
  2485. if (!txn || !data) {
  2486. cnss_pr_err("Spurious indication\n");
  2487. return;
  2488. }
  2489. cnss_pr_dbg_buf("QMI fw_mem_file_save: source: %d mem_seg: %d type: %u len: %u\n",
  2490. ind_msg->source, ind_msg->mem_seg_valid,
  2491. ind_msg->mem_seg[0].type, ind_msg->mem_seg_len);
  2492. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2493. if (!event_data)
  2494. return;
  2495. event_data->mem_type = ind_msg->mem_seg[0].type;
  2496. event_data->mem_seg_len = ind_msg->mem_seg_len;
  2497. event_data->total_size = ind_msg->total_size;
  2498. if (ind_msg->mem_seg_valid) {
  2499. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_STR_LEN_V01) {
  2500. cnss_pr_err("Invalid seg len indication\n");
  2501. goto free_event_data;
  2502. }
  2503. for (i = 0; i < ind_msg->mem_seg_len; i++) {
  2504. event_data->mem_seg[i].addr = ind_msg->mem_seg[i].addr;
  2505. event_data->mem_seg[i].size = ind_msg->mem_seg[i].size;
  2506. if (event_data->mem_type != ind_msg->mem_seg[i].type) {
  2507. cnss_pr_err("FW Mem file save ind cannot have multiple mem types\n");
  2508. goto free_event_data;
  2509. }
  2510. cnss_pr_dbg_buf("seg-%d: addr 0x%llx size 0x%x\n",
  2511. i, ind_msg->mem_seg[i].addr,
  2512. ind_msg->mem_seg[i].size);
  2513. }
  2514. }
  2515. if (ind_msg->file_name_valid)
  2516. strlcpy(event_data->file_name, ind_msg->file_name,
  2517. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2518. if (ind_msg->source == 1) {
  2519. if (!ind_msg->file_name_valid)
  2520. strlcpy(event_data->file_name, "qdss_trace_wcss_etb",
  2521. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2522. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
  2523. 0, event_data);
  2524. } else {
  2525. if (event_data->mem_type == QMI_WLFW_MEM_QDSS_V01) {
  2526. if (!ind_msg->file_name_valid)
  2527. strlcpy(event_data->file_name, "qdss_trace_ddr",
  2528. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2529. } else {
  2530. if (!ind_msg->file_name_valid)
  2531. strlcpy(event_data->file_name, "fw_mem_dump",
  2532. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2533. }
  2534. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
  2535. 0, event_data);
  2536. }
  2537. return;
  2538. free_event_data:
  2539. kfree(event_data);
  2540. }
  2541. static void cnss_wlfw_qdss_trace_free_ind_cb(struct qmi_handle *qmi_wlfw,
  2542. struct sockaddr_qrtr *sq,
  2543. struct qmi_txn *txn,
  2544. const void *data)
  2545. {
  2546. struct cnss_plat_data *plat_priv =
  2547. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2548. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
  2549. 0, NULL);
  2550. }
  2551. static void cnss_wlfw_respond_get_info_ind_cb(struct qmi_handle *qmi_wlfw,
  2552. struct sockaddr_qrtr *sq,
  2553. struct qmi_txn *txn,
  2554. const void *data)
  2555. {
  2556. struct cnss_plat_data *plat_priv =
  2557. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2558. const struct wlfw_respond_get_info_ind_msg_v01 *ind_msg = data;
  2559. cnss_pr_buf("Received QMI WLFW respond get info indication\n");
  2560. if (!txn) {
  2561. cnss_pr_err("Spurious indication\n");
  2562. return;
  2563. }
  2564. cnss_pr_buf("Extract message with event length: %d, type: %d, is last: %d, seq no: %d\n",
  2565. ind_msg->data_len, ind_msg->type,
  2566. ind_msg->is_last, ind_msg->seq_no);
  2567. if (plat_priv->get_info_cb_ctx && plat_priv->get_info_cb)
  2568. plat_priv->get_info_cb(plat_priv->get_info_cb_ctx,
  2569. (void *)ind_msg->data,
  2570. ind_msg->data_len);
  2571. }
  2572. static int cnss_ims_wfc_call_twt_cfg_send_sync
  2573. (struct cnss_plat_data *plat_priv,
  2574. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg)
  2575. {
  2576. struct ims_private_service_wfc_call_twt_config_req_msg_v01 *req;
  2577. struct ims_private_service_wfc_call_twt_config_rsp_msg_v01 *resp;
  2578. struct qmi_txn txn;
  2579. int ret = 0;
  2580. if (!test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  2581. cnss_pr_err("Drop FW WFC indication as IMS QMI not connected\n");
  2582. return -EINVAL;
  2583. }
  2584. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2585. if (!req)
  2586. return -ENOMEM;
  2587. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2588. if (!resp) {
  2589. kfree(req);
  2590. return -ENOMEM;
  2591. }
  2592. req->twt_sta_start_valid = ind_msg->twt_sta_start_valid;
  2593. req->twt_sta_start = ind_msg->twt_sta_start;
  2594. req->twt_sta_int_valid = ind_msg->twt_sta_int_valid;
  2595. req->twt_sta_int = ind_msg->twt_sta_int;
  2596. req->twt_sta_upo_valid = ind_msg->twt_sta_upo_valid;
  2597. req->twt_sta_upo = ind_msg->twt_sta_upo;
  2598. req->twt_sta_sp_valid = ind_msg->twt_sta_sp_valid;
  2599. req->twt_sta_sp = ind_msg->twt_sta_sp;
  2600. req->twt_sta_dl_valid = req->twt_sta_dl_valid;
  2601. req->twt_sta_dl = req->twt_sta_dl;
  2602. req->twt_sta_config_changed_valid =
  2603. ind_msg->twt_sta_config_changed_valid;
  2604. req->twt_sta_config_changed = ind_msg->twt_sta_config_changed;
  2605. cnss_pr_dbg("CNSS->IMS: TWT_CFG_REQ: state: 0x%lx\n",
  2606. plat_priv->driver_state);
  2607. ret =
  2608. qmi_txn_init(&plat_priv->ims_qmi, &txn,
  2609. ims_private_service_wfc_call_twt_config_rsp_msg_v01_ei,
  2610. resp);
  2611. if (ret < 0) {
  2612. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Txn Init Err: %d\n",
  2613. ret);
  2614. goto out;
  2615. }
  2616. ret =
  2617. qmi_send_request(&plat_priv->ims_qmi, NULL, &txn,
  2618. QMI_IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_V01,
  2619. IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_MSG_V01_MAX_MSG_LEN,
  2620. ims_private_service_wfc_call_twt_config_req_msg_v01_ei, req);
  2621. if (ret < 0) {
  2622. qmi_txn_cancel(&txn);
  2623. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Send Err: %d\n", ret);
  2624. goto out;
  2625. }
  2626. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2627. if (ret < 0) {
  2628. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: QMI Wait Err: %d\n", ret);
  2629. goto out;
  2630. }
  2631. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2632. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: Result: %d Err: %d\n",
  2633. resp->resp.result, resp->resp.error);
  2634. ret = -resp->resp.result;
  2635. goto out;
  2636. }
  2637. ret = 0;
  2638. out:
  2639. kfree(req);
  2640. kfree(resp);
  2641. return ret;
  2642. }
  2643. int cnss_process_twt_cfg_ind_event(struct cnss_plat_data *plat_priv,
  2644. void *data)
  2645. {
  2646. int ret;
  2647. struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2648. ret = cnss_ims_wfc_call_twt_cfg_send_sync(plat_priv, ind_msg);
  2649. kfree(data);
  2650. return ret;
  2651. }
  2652. static void cnss_wlfw_process_twt_cfg_ind(struct qmi_handle *qmi_wlfw,
  2653. struct sockaddr_qrtr *sq,
  2654. struct qmi_txn *txn,
  2655. const void *data)
  2656. {
  2657. struct cnss_plat_data *plat_priv =
  2658. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2659. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2660. struct wlfw_wfc_call_twt_config_ind_msg_v01 *event_data;
  2661. if (!txn) {
  2662. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Spurious indication\n");
  2663. return;
  2664. }
  2665. if (!ind_msg) {
  2666. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Invalid indication\n");
  2667. return;
  2668. }
  2669. cnss_pr_dbg("FW->CNSS: TWT_CFG_IND: %x %llx, %x %x, %x %x, %x %x, %x %x, %x %x\n",
  2670. ind_msg->twt_sta_start_valid, ind_msg->twt_sta_start,
  2671. ind_msg->twt_sta_int_valid, ind_msg->twt_sta_int,
  2672. ind_msg->twt_sta_upo_valid, ind_msg->twt_sta_upo,
  2673. ind_msg->twt_sta_sp_valid, ind_msg->twt_sta_sp,
  2674. ind_msg->twt_sta_dl_valid, ind_msg->twt_sta_dl,
  2675. ind_msg->twt_sta_config_changed_valid,
  2676. ind_msg->twt_sta_config_changed);
  2677. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  2678. if (!event_data)
  2679. return;
  2680. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND, 0,
  2681. event_data);
  2682. }
  2683. static struct qmi_msg_handler qmi_wlfw_msg_handlers[] = {
  2684. {
  2685. .type = QMI_INDICATION,
  2686. .msg_id = QMI_WLFW_REQUEST_MEM_IND_V01,
  2687. .ei = wlfw_request_mem_ind_msg_v01_ei,
  2688. .decoded_size = sizeof(struct wlfw_request_mem_ind_msg_v01),
  2689. .fn = cnss_wlfw_request_mem_ind_cb
  2690. },
  2691. {
  2692. .type = QMI_INDICATION,
  2693. .msg_id = QMI_WLFW_FW_MEM_READY_IND_V01,
  2694. .ei = wlfw_fw_mem_ready_ind_msg_v01_ei,
  2695. .decoded_size = sizeof(struct wlfw_fw_mem_ready_ind_msg_v01),
  2696. .fn = cnss_wlfw_fw_mem_ready_ind_cb
  2697. },
  2698. {
  2699. .type = QMI_INDICATION,
  2700. .msg_id = QMI_WLFW_FW_READY_IND_V01,
  2701. .ei = wlfw_fw_ready_ind_msg_v01_ei,
  2702. .decoded_size = sizeof(struct wlfw_fw_ready_ind_msg_v01),
  2703. .fn = cnss_wlfw_fw_ready_ind_cb
  2704. },
  2705. {
  2706. .type = QMI_INDICATION,
  2707. .msg_id = QMI_WLFW_FW_INIT_DONE_IND_V01,
  2708. .ei = wlfw_fw_init_done_ind_msg_v01_ei,
  2709. .decoded_size = sizeof(struct wlfw_fw_init_done_ind_msg_v01),
  2710. .fn = cnss_wlfw_fw_init_done_ind_cb
  2711. },
  2712. {
  2713. .type = QMI_INDICATION,
  2714. .msg_id = QMI_WLFW_PIN_CONNECT_RESULT_IND_V01,
  2715. .ei = wlfw_pin_connect_result_ind_msg_v01_ei,
  2716. .decoded_size =
  2717. sizeof(struct wlfw_pin_connect_result_ind_msg_v01),
  2718. .fn = cnss_wlfw_pin_result_ind_cb
  2719. },
  2720. {
  2721. .type = QMI_INDICATION,
  2722. .msg_id = QMI_WLFW_CAL_DONE_IND_V01,
  2723. .ei = wlfw_cal_done_ind_msg_v01_ei,
  2724. .decoded_size = sizeof(struct wlfw_cal_done_ind_msg_v01),
  2725. .fn = cnss_wlfw_cal_done_ind_cb
  2726. },
  2727. {
  2728. .type = QMI_INDICATION,
  2729. .msg_id = QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01,
  2730. .ei = wlfw_qdss_trace_req_mem_ind_msg_v01_ei,
  2731. .decoded_size =
  2732. sizeof(struct wlfw_qdss_trace_req_mem_ind_msg_v01),
  2733. .fn = cnss_wlfw_qdss_trace_req_mem_ind_cb
  2734. },
  2735. {
  2736. .type = QMI_INDICATION,
  2737. .msg_id = QMI_WLFW_QDSS_TRACE_SAVE_IND_V01,
  2738. .ei = wlfw_qdss_trace_save_ind_msg_v01_ei,
  2739. .decoded_size =
  2740. sizeof(struct wlfw_qdss_trace_save_ind_msg_v01),
  2741. .fn = cnss_wlfw_fw_mem_file_save_ind_cb
  2742. },
  2743. {
  2744. .type = QMI_INDICATION,
  2745. .msg_id = QMI_WLFW_QDSS_TRACE_FREE_IND_V01,
  2746. .ei = wlfw_qdss_trace_free_ind_msg_v01_ei,
  2747. .decoded_size =
  2748. sizeof(struct wlfw_qdss_trace_free_ind_msg_v01),
  2749. .fn = cnss_wlfw_qdss_trace_free_ind_cb
  2750. },
  2751. {
  2752. .type = QMI_INDICATION,
  2753. .msg_id = QMI_WLFW_RESPOND_GET_INFO_IND_V01,
  2754. .ei = wlfw_respond_get_info_ind_msg_v01_ei,
  2755. .decoded_size =
  2756. sizeof(struct wlfw_respond_get_info_ind_msg_v01),
  2757. .fn = cnss_wlfw_respond_get_info_ind_cb
  2758. },
  2759. {
  2760. .type = QMI_INDICATION,
  2761. .msg_id = QMI_WLFW_WFC_CALL_TWT_CONFIG_IND_V01,
  2762. .ei = wlfw_wfc_call_twt_config_ind_msg_v01_ei,
  2763. .decoded_size =
  2764. sizeof(struct wlfw_wfc_call_twt_config_ind_msg_v01),
  2765. .fn = cnss_wlfw_process_twt_cfg_ind
  2766. },
  2767. {}
  2768. };
  2769. static int cnss_wlfw_connect_to_server(struct cnss_plat_data *plat_priv,
  2770. void *data)
  2771. {
  2772. struct cnss_qmi_event_server_arrive_data *event_data = data;
  2773. struct qmi_handle *qmi_wlfw = &plat_priv->qmi_wlfw;
  2774. struct sockaddr_qrtr sq = { 0 };
  2775. int ret = 0;
  2776. if (!event_data)
  2777. return -EINVAL;
  2778. sq.sq_family = AF_QIPCRTR;
  2779. sq.sq_node = event_data->node;
  2780. sq.sq_port = event_data->port;
  2781. ret = kernel_connect(qmi_wlfw->sock, (struct sockaddr *)&sq,
  2782. sizeof(sq), 0);
  2783. if (ret < 0) {
  2784. cnss_pr_err("Failed to connect to QMI WLFW remote service port\n");
  2785. goto out;
  2786. }
  2787. set_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2788. cnss_pr_info("QMI WLFW service connected, state: 0x%lx\n",
  2789. plat_priv->driver_state);
  2790. kfree(data);
  2791. return 0;
  2792. out:
  2793. CNSS_QMI_ASSERT();
  2794. kfree(data);
  2795. return ret;
  2796. }
  2797. int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, void *data)
  2798. {
  2799. int ret = 0;
  2800. if (!plat_priv)
  2801. return -ENODEV;
  2802. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  2803. cnss_pr_err("Unexpected WLFW server arrive\n");
  2804. CNSS_ASSERT(0);
  2805. return -EINVAL;
  2806. }
  2807. cnss_ignore_qmi_failure(false);
  2808. ret = cnss_wlfw_connect_to_server(plat_priv, data);
  2809. if (ret < 0)
  2810. goto out;
  2811. ret = cnss_wlfw_ind_register_send_sync(plat_priv);
  2812. if (ret < 0) {
  2813. if (ret == -EALREADY)
  2814. ret = 0;
  2815. goto out;
  2816. }
  2817. ret = cnss_wlfw_host_cap_send_sync(plat_priv);
  2818. if (ret < 0)
  2819. goto out;
  2820. return 0;
  2821. out:
  2822. return ret;
  2823. }
  2824. int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv)
  2825. {
  2826. int ret;
  2827. if (!plat_priv)
  2828. return -ENODEV;
  2829. clear_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2830. cnss_pr_info("QMI WLFW service disconnected, state: 0x%lx\n",
  2831. plat_priv->driver_state);
  2832. cnss_qmi_deinit(plat_priv);
  2833. clear_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2834. ret = cnss_qmi_init(plat_priv);
  2835. if (ret < 0) {
  2836. cnss_pr_err("QMI WLFW service registraton failed, ret\n", ret);
  2837. CNSS_ASSERT(0);
  2838. }
  2839. return 0;
  2840. }
  2841. static int wlfw_new_server(struct qmi_handle *qmi_wlfw,
  2842. struct qmi_service *service)
  2843. {
  2844. struct cnss_plat_data *plat_priv =
  2845. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2846. struct cnss_qmi_event_server_arrive_data *event_data;
  2847. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2848. cnss_pr_info("WLFW server delete in progress, Ignore server arrive, state: 0x%lx\n",
  2849. plat_priv->driver_state);
  2850. return 0;
  2851. }
  2852. cnss_pr_dbg("WLFW server arriving: node %u port %u\n",
  2853. service->node, service->port);
  2854. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2855. if (!event_data)
  2856. return -ENOMEM;
  2857. event_data->node = service->node;
  2858. event_data->port = service->port;
  2859. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_ARRIVE,
  2860. 0, event_data);
  2861. return 0;
  2862. }
  2863. static void wlfw_del_server(struct qmi_handle *qmi_wlfw,
  2864. struct qmi_service *service)
  2865. {
  2866. struct cnss_plat_data *plat_priv =
  2867. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2868. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2869. cnss_pr_info("WLFW server delete in progress, Ignore server delete, state: 0x%lx\n",
  2870. plat_priv->driver_state);
  2871. return;
  2872. }
  2873. cnss_pr_dbg("WLFW server exiting\n");
  2874. if (plat_priv) {
  2875. cnss_ignore_qmi_failure(true);
  2876. set_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2877. }
  2878. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_EXIT,
  2879. 0, NULL);
  2880. }
  2881. static struct qmi_ops qmi_wlfw_ops = {
  2882. .new_server = wlfw_new_server,
  2883. .del_server = wlfw_del_server,
  2884. };
  2885. static int cnss_qmi_add_lookup(struct cnss_plat_data *plat_priv)
  2886. {
  2887. unsigned int id = WLFW_SERVICE_INS_ID_V01;
  2888. /* In order to support dual wlan card attach case,
  2889. * need separate qmi service instance id for each dev
  2890. */
  2891. if (cnss_is_dual_wlan_enabled() && plat_priv->qrtr_node_id != 0 &&
  2892. plat_priv->wlfw_service_instance_id != 0)
  2893. id = plat_priv->wlfw_service_instance_id;
  2894. return qmi_add_lookup(&plat_priv->qmi_wlfw, WLFW_SERVICE_ID_V01,
  2895. WLFW_SERVICE_VERS_V01, id);
  2896. }
  2897. int cnss_qmi_init(struct cnss_plat_data *plat_priv)
  2898. {
  2899. int ret = 0;
  2900. cnss_get_qrtr_info(plat_priv);
  2901. ret = qmi_handle_init(&plat_priv->qmi_wlfw,
  2902. QMI_WLFW_MAX_RECV_BUF_SIZE,
  2903. &qmi_wlfw_ops, qmi_wlfw_msg_handlers);
  2904. if (ret < 0) {
  2905. cnss_pr_err("Failed to initialize WLFW QMI handle, err: %d\n",
  2906. ret);
  2907. goto out;
  2908. }
  2909. ret = cnss_qmi_add_lookup(plat_priv);
  2910. if (ret < 0)
  2911. cnss_pr_err("Failed to add WLFW QMI lookup, err: %d\n", ret);
  2912. out:
  2913. return ret;
  2914. }
  2915. void cnss_qmi_deinit(struct cnss_plat_data *plat_priv)
  2916. {
  2917. qmi_handle_release(&plat_priv->qmi_wlfw);
  2918. }
  2919. int cnss_qmi_get_dms_mac(struct cnss_plat_data *plat_priv)
  2920. {
  2921. struct dms_get_mac_address_req_msg_v01 req;
  2922. struct dms_get_mac_address_resp_msg_v01 resp;
  2923. struct qmi_txn txn;
  2924. int ret = 0;
  2925. if (!test_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state)) {
  2926. cnss_pr_err("DMS QMI connection not established\n");
  2927. return -EINVAL;
  2928. }
  2929. cnss_pr_dbg("Requesting DMS MAC address");
  2930. memset(&resp, 0, sizeof(resp));
  2931. ret = qmi_txn_init(&plat_priv->qmi_dms, &txn,
  2932. dms_get_mac_address_resp_msg_v01_ei, &resp);
  2933. if (ret < 0) {
  2934. cnss_pr_err("Failed to initialize txn for dms, err: %d\n",
  2935. ret);
  2936. goto out;
  2937. }
  2938. req.device = DMS_DEVICE_MAC_WLAN_V01;
  2939. ret = qmi_send_request(&plat_priv->qmi_dms, NULL, &txn,
  2940. QMI_DMS_GET_MAC_ADDRESS_REQ_V01,
  2941. DMS_GET_MAC_ADDRESS_REQ_MSG_V01_MAX_MSG_LEN,
  2942. dms_get_mac_address_req_msg_v01_ei, &req);
  2943. if (ret < 0) {
  2944. qmi_txn_cancel(&txn);
  2945. cnss_pr_err("Failed to send QMI_DMS_GET_MAC_ADDRESS_REQ_V01, err: %d\n",
  2946. ret);
  2947. goto out;
  2948. }
  2949. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2950. if (ret < 0) {
  2951. cnss_pr_err("Failed to wait for QMI_DMS_GET_MAC_ADDRESS_RESP_V01, err: %d\n",
  2952. ret);
  2953. goto out;
  2954. }
  2955. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  2956. cnss_pr_err("QMI_DMS_GET_MAC_ADDRESS_REQ_V01 failed, result: %d, err: %d\n",
  2957. resp.resp.result, resp.resp.error);
  2958. ret = -resp.resp.result;
  2959. goto out;
  2960. }
  2961. if (!resp.mac_address_valid ||
  2962. resp.mac_address_len != QMI_WLFW_MAC_ADDR_SIZE_V01) {
  2963. cnss_pr_err("Invalid MAC address received from DMS\n");
  2964. plat_priv->dms.mac_valid = false;
  2965. goto out;
  2966. }
  2967. plat_priv->dms.mac_valid = true;
  2968. memcpy(plat_priv->dms.mac, resp.mac_address, QMI_WLFW_MAC_ADDR_SIZE_V01);
  2969. cnss_pr_info("Received DMS MAC: [%pM]\n", plat_priv->dms.mac);
  2970. out:
  2971. return ret;
  2972. }
  2973. static int cnss_dms_connect_to_server(struct cnss_plat_data *plat_priv,
  2974. unsigned int node, unsigned int port)
  2975. {
  2976. struct qmi_handle *qmi_dms = &plat_priv->qmi_dms;
  2977. struct sockaddr_qrtr sq = {0};
  2978. int ret = 0;
  2979. sq.sq_family = AF_QIPCRTR;
  2980. sq.sq_node = node;
  2981. sq.sq_port = port;
  2982. ret = kernel_connect(qmi_dms->sock, (struct sockaddr *)&sq,
  2983. sizeof(sq), 0);
  2984. if (ret < 0) {
  2985. cnss_pr_err("Failed to connect to QMI DMS remote service Node: %d Port: %d\n",
  2986. node, port);
  2987. goto out;
  2988. }
  2989. set_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  2990. cnss_pr_info("QMI DMS service connected, state: 0x%lx\n",
  2991. plat_priv->driver_state);
  2992. out:
  2993. return ret;
  2994. }
  2995. static int dms_new_server(struct qmi_handle *qmi_dms,
  2996. struct qmi_service *service)
  2997. {
  2998. struct cnss_plat_data *plat_priv =
  2999. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3000. if (!service)
  3001. return -EINVAL;
  3002. return cnss_dms_connect_to_server(plat_priv, service->node,
  3003. service->port);
  3004. }
  3005. static void cnss_dms_server_exit_work(struct work_struct *work)
  3006. {
  3007. int ret;
  3008. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  3009. cnss_dms_deinit(plat_priv);
  3010. cnss_pr_info("QMI DMS Server Exit");
  3011. clear_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3012. ret = cnss_dms_init(plat_priv);
  3013. if (ret < 0)
  3014. cnss_pr_err("QMI DMS service registraton failed, ret\n", ret);
  3015. }
  3016. static DECLARE_WORK(cnss_dms_del_work, cnss_dms_server_exit_work);
  3017. static void dms_del_server(struct qmi_handle *qmi_dms,
  3018. struct qmi_service *service)
  3019. {
  3020. struct cnss_plat_data *plat_priv =
  3021. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3022. if (!plat_priv)
  3023. return;
  3024. if (test_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state)) {
  3025. cnss_pr_info("DMS server delete or cnss remove in progress, Ignore server delete: 0x%lx\n",
  3026. plat_priv->driver_state);
  3027. return;
  3028. }
  3029. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3030. clear_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3031. cnss_pr_info("QMI DMS service disconnected, state: 0x%lx\n",
  3032. plat_priv->driver_state);
  3033. schedule_work(&cnss_dms_del_work);
  3034. }
  3035. void cnss_cancel_dms_work(void)
  3036. {
  3037. cancel_work_sync(&cnss_dms_del_work);
  3038. }
  3039. static struct qmi_ops qmi_dms_ops = {
  3040. .new_server = dms_new_server,
  3041. .del_server = dms_del_server,
  3042. };
  3043. int cnss_dms_init(struct cnss_plat_data *plat_priv)
  3044. {
  3045. int ret = 0;
  3046. ret = qmi_handle_init(&plat_priv->qmi_dms, DMS_QMI_MAX_MSG_LEN,
  3047. &qmi_dms_ops, NULL);
  3048. if (ret < 0) {
  3049. cnss_pr_err("Failed to initialize DMS handle, err: %d\n", ret);
  3050. goto out;
  3051. }
  3052. ret = qmi_add_lookup(&plat_priv->qmi_dms, DMS_SERVICE_ID_V01,
  3053. DMS_SERVICE_VERS_V01, 0);
  3054. if (ret < 0)
  3055. cnss_pr_err("Failed to add DMS lookup, err: %d\n", ret);
  3056. out:
  3057. return ret;
  3058. }
  3059. void cnss_dms_deinit(struct cnss_plat_data *plat_priv)
  3060. {
  3061. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3062. qmi_handle_release(&plat_priv->qmi_dms);
  3063. }
  3064. int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv)
  3065. {
  3066. int ret;
  3067. struct coex_antenna_switch_to_wlan_req_msg_v01 *req;
  3068. struct coex_antenna_switch_to_wlan_resp_msg_v01 *resp;
  3069. struct qmi_txn txn;
  3070. if (!plat_priv)
  3071. return -ENODEV;
  3072. cnss_pr_dbg("Sending coex antenna switch_to_wlan\n");
  3073. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3074. if (!req)
  3075. return -ENOMEM;
  3076. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3077. if (!resp) {
  3078. kfree(req);
  3079. return -ENOMEM;
  3080. }
  3081. req->antenna = plat_priv->antenna;
  3082. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3083. coex_antenna_switch_to_wlan_resp_msg_v01_ei, resp);
  3084. if (ret < 0) {
  3085. cnss_pr_err("Fail to init txn for coex antenna switch_to_wlan resp %d\n",
  3086. ret);
  3087. goto out;
  3088. }
  3089. ret = qmi_send_request
  3090. (&plat_priv->coex_qmi, NULL, &txn,
  3091. QMI_COEX_SWITCH_ANTENNA_TO_WLAN_REQ_V01,
  3092. COEX_ANTENNA_SWITCH_TO_WLAN_REQ_MSG_V01_MAX_MSG_LEN,
  3093. coex_antenna_switch_to_wlan_req_msg_v01_ei, req);
  3094. if (ret < 0) {
  3095. qmi_txn_cancel(&txn);
  3096. cnss_pr_err("Fail to send coex antenna switch_to_wlan req %d\n",
  3097. ret);
  3098. goto out;
  3099. }
  3100. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3101. if (ret < 0) {
  3102. cnss_pr_err("Coex antenna switch_to_wlan resp wait failed with ret %d\n",
  3103. ret);
  3104. goto out;
  3105. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3106. cnss_pr_err("Coex antenna switch_to_wlan request rejected, result:%d error:%d\n",
  3107. resp->resp.result, resp->resp.error);
  3108. ret = -resp->resp.result;
  3109. goto out;
  3110. }
  3111. if (resp->grant_valid)
  3112. plat_priv->grant = resp->grant;
  3113. cnss_pr_dbg("Coex antenna grant: 0x%llx\n", resp->grant);
  3114. kfree(resp);
  3115. kfree(req);
  3116. return 0;
  3117. out:
  3118. kfree(resp);
  3119. kfree(req);
  3120. return ret;
  3121. }
  3122. int coex_antenna_switch_to_mdm_send_sync_msg(struct cnss_plat_data *plat_priv)
  3123. {
  3124. int ret;
  3125. struct coex_antenna_switch_to_mdm_req_msg_v01 *req;
  3126. struct coex_antenna_switch_to_mdm_resp_msg_v01 *resp;
  3127. struct qmi_txn txn;
  3128. if (!plat_priv)
  3129. return -ENODEV;
  3130. cnss_pr_dbg("Sending coex antenna switch_to_mdm\n");
  3131. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3132. if (!req)
  3133. return -ENOMEM;
  3134. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3135. if (!resp) {
  3136. kfree(req);
  3137. return -ENOMEM;
  3138. }
  3139. req->antenna = plat_priv->antenna;
  3140. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3141. coex_antenna_switch_to_mdm_resp_msg_v01_ei, resp);
  3142. if (ret < 0) {
  3143. cnss_pr_err("Fail to init txn for coex antenna switch_to_mdm resp %d\n",
  3144. ret);
  3145. goto out;
  3146. }
  3147. ret = qmi_send_request
  3148. (&plat_priv->coex_qmi, NULL, &txn,
  3149. QMI_COEX_SWITCH_ANTENNA_TO_MDM_REQ_V01,
  3150. COEX_ANTENNA_SWITCH_TO_MDM_REQ_MSG_V01_MAX_MSG_LEN,
  3151. coex_antenna_switch_to_mdm_req_msg_v01_ei, req);
  3152. if (ret < 0) {
  3153. qmi_txn_cancel(&txn);
  3154. cnss_pr_err("Fail to send coex antenna switch_to_mdm req %d\n",
  3155. ret);
  3156. goto out;
  3157. }
  3158. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3159. if (ret < 0) {
  3160. cnss_pr_err("Coex antenna switch_to_mdm resp wait failed with ret %d\n",
  3161. ret);
  3162. goto out;
  3163. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3164. cnss_pr_err("Coex antenna switch_to_mdm request rejected, result:%d error:%d\n",
  3165. resp->resp.result, resp->resp.error);
  3166. ret = -resp->resp.result;
  3167. goto out;
  3168. }
  3169. kfree(resp);
  3170. kfree(req);
  3171. return 0;
  3172. out:
  3173. kfree(resp);
  3174. kfree(req);
  3175. return ret;
  3176. }
  3177. int cnss_send_subsys_restart_level_msg(struct cnss_plat_data *plat_priv)
  3178. {
  3179. int ret;
  3180. struct wlfw_subsys_restart_level_req_msg_v01 req;
  3181. struct wlfw_subsys_restart_level_resp_msg_v01 resp;
  3182. u8 pcss_enabled;
  3183. if (!plat_priv)
  3184. return -ENODEV;
  3185. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  3186. cnss_pr_dbg("Can't send pcss cmd before fw ready\n");
  3187. return 0;
  3188. }
  3189. pcss_enabled = plat_priv->recovery_pcss_enabled;
  3190. cnss_pr_dbg("Sending pcss recovery status: %d\n", pcss_enabled);
  3191. req.restart_level_type_valid = 1;
  3192. req.restart_level_type = pcss_enabled;
  3193. ret = qmi_send_wait(&plat_priv->qmi_wlfw, &req, &resp,
  3194. wlfw_subsys_restart_level_req_msg_v01_ei,
  3195. wlfw_subsys_restart_level_resp_msg_v01_ei,
  3196. QMI_WLFW_SUBSYS_RESTART_LEVEL_REQ_V01,
  3197. WLFW_SUBSYS_RESTART_LEVEL_REQ_MSG_V01_MAX_MSG_LEN,
  3198. QMI_WLFW_TIMEOUT_JF);
  3199. if (ret < 0)
  3200. cnss_pr_err("pcss recovery setting failed with ret %d\n", ret);
  3201. return ret;
  3202. }
  3203. static int coex_new_server(struct qmi_handle *qmi,
  3204. struct qmi_service *service)
  3205. {
  3206. struct cnss_plat_data *plat_priv =
  3207. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3208. struct sockaddr_qrtr sq = { 0 };
  3209. int ret = 0;
  3210. cnss_pr_dbg("COEX server arrive: node %u port %u\n",
  3211. service->node, service->port);
  3212. sq.sq_family = AF_QIPCRTR;
  3213. sq.sq_node = service->node;
  3214. sq.sq_port = service->port;
  3215. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3216. if (ret < 0) {
  3217. cnss_pr_err("Fail to connect to remote service port\n");
  3218. return ret;
  3219. }
  3220. set_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3221. cnss_pr_dbg("COEX Server Connected: 0x%lx\n",
  3222. plat_priv->driver_state);
  3223. return 0;
  3224. }
  3225. static void coex_del_server(struct qmi_handle *qmi,
  3226. struct qmi_service *service)
  3227. {
  3228. struct cnss_plat_data *plat_priv =
  3229. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3230. cnss_pr_dbg("COEX server exit\n");
  3231. clear_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3232. }
  3233. static struct qmi_ops coex_qmi_ops = {
  3234. .new_server = coex_new_server,
  3235. .del_server = coex_del_server,
  3236. };
  3237. int cnss_register_coex_service(struct cnss_plat_data *plat_priv)
  3238. { int ret;
  3239. ret = qmi_handle_init(&plat_priv->coex_qmi,
  3240. COEX_SERVICE_MAX_MSG_LEN,
  3241. &coex_qmi_ops, NULL);
  3242. if (ret < 0)
  3243. return ret;
  3244. ret = qmi_add_lookup(&plat_priv->coex_qmi, COEX_SERVICE_ID_V01,
  3245. COEX_SERVICE_VERS_V01, 0);
  3246. return ret;
  3247. }
  3248. void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv)
  3249. {
  3250. qmi_handle_release(&plat_priv->coex_qmi);
  3251. }
  3252. /* IMS Service */
  3253. int ims_subscribe_for_indication_send_async(struct cnss_plat_data *plat_priv)
  3254. {
  3255. int ret;
  3256. struct ims_private_service_subscribe_for_indications_req_msg_v01 *req;
  3257. struct qmi_txn *txn;
  3258. if (!plat_priv)
  3259. return -ENODEV;
  3260. cnss_pr_dbg("Sending ASYNC ims subscribe for indication\n");
  3261. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3262. if (!req)
  3263. return -ENOMEM;
  3264. req->wfc_call_status_valid = 1;
  3265. req->wfc_call_status = 1;
  3266. txn = &plat_priv->txn;
  3267. ret = qmi_txn_init(&plat_priv->ims_qmi, txn, NULL, NULL);
  3268. if (ret < 0) {
  3269. cnss_pr_err("Fail to init txn for ims subscribe for indication resp %d\n",
  3270. ret);
  3271. goto out;
  3272. }
  3273. ret = qmi_send_request
  3274. (&plat_priv->ims_qmi, NULL, txn,
  3275. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3276. IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_MSG_V01_MAX_MSG_LEN,
  3277. ims_private_service_subscribe_for_indications_req_msg_v01_ei, req);
  3278. if (ret < 0) {
  3279. qmi_txn_cancel(txn);
  3280. cnss_pr_err("Fail to send ims subscribe for indication req %d\n",
  3281. ret);
  3282. goto out;
  3283. }
  3284. kfree(req);
  3285. return 0;
  3286. out:
  3287. kfree(req);
  3288. return ret;
  3289. }
  3290. static void ims_subscribe_for_indication_resp_cb(struct qmi_handle *qmi,
  3291. struct sockaddr_qrtr *sq,
  3292. struct qmi_txn *txn,
  3293. const void *data)
  3294. {
  3295. const
  3296. struct ims_private_service_subscribe_for_indications_rsp_msg_v01 *resp =
  3297. data;
  3298. cnss_pr_dbg("Received IMS subscribe indication response\n");
  3299. if (!txn) {
  3300. cnss_pr_err("spurious response\n");
  3301. return;
  3302. }
  3303. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3304. cnss_pr_err("IMS subscribe for indication request rejected, result:%d error:%d\n",
  3305. resp->resp.result, resp->resp.error);
  3306. txn->result = -resp->resp.result;
  3307. }
  3308. }
  3309. int cnss_process_wfc_call_ind_event(struct cnss_plat_data *plat_priv,
  3310. void *data)
  3311. {
  3312. int ret;
  3313. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3314. ret = cnss_wlfw_wfc_call_status_send_sync(plat_priv, ind_msg);
  3315. kfree(data);
  3316. return ret;
  3317. }
  3318. static void
  3319. cnss_ims_process_wfc_call_ind_cb(struct qmi_handle *ims_qmi,
  3320. struct sockaddr_qrtr *sq,
  3321. struct qmi_txn *txn, const void *data)
  3322. {
  3323. struct cnss_plat_data *plat_priv =
  3324. container_of(ims_qmi, struct cnss_plat_data, ims_qmi);
  3325. const
  3326. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3327. struct ims_private_service_wfc_call_status_ind_msg_v01 *event_data;
  3328. if (!txn) {
  3329. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Spurious indication\n");
  3330. return;
  3331. }
  3332. if (!ind_msg) {
  3333. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Invalid indication\n");
  3334. return;
  3335. }
  3336. cnss_pr_dbg("IMS->CNSS: WFC_CALL_IND: %x, %x %x, %x %x, %x %llx, %x %x, %x %x\n",
  3337. ind_msg->wfc_call_active, ind_msg->all_wfc_calls_held_valid,
  3338. ind_msg->all_wfc_calls_held,
  3339. ind_msg->is_wfc_emergency_valid, ind_msg->is_wfc_emergency,
  3340. ind_msg->twt_ims_start_valid, ind_msg->twt_ims_start,
  3341. ind_msg->twt_ims_int_valid, ind_msg->twt_ims_int,
  3342. ind_msg->media_quality_valid, ind_msg->media_quality);
  3343. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  3344. if (!event_data)
  3345. return;
  3346. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
  3347. 0, event_data);
  3348. }
  3349. static struct qmi_msg_handler qmi_ims_msg_handlers[] = {
  3350. {
  3351. .type = QMI_RESPONSE,
  3352. .msg_id =
  3353. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3354. .ei =
  3355. ims_private_service_subscribe_for_indications_rsp_msg_v01_ei,
  3356. .decoded_size = sizeof(struct
  3357. ims_private_service_subscribe_for_indications_rsp_msg_v01),
  3358. .fn = ims_subscribe_for_indication_resp_cb
  3359. },
  3360. {
  3361. .type = QMI_INDICATION,
  3362. .msg_id = QMI_IMS_PRIVATE_SERVICE_WFC_CALL_STATUS_IND_V01,
  3363. .ei = ims_private_service_wfc_call_status_ind_msg_v01_ei,
  3364. .decoded_size =
  3365. sizeof(struct ims_private_service_wfc_call_status_ind_msg_v01),
  3366. .fn = cnss_ims_process_wfc_call_ind_cb
  3367. },
  3368. {}
  3369. };
  3370. static int ims_new_server(struct qmi_handle *qmi,
  3371. struct qmi_service *service)
  3372. {
  3373. struct cnss_plat_data *plat_priv =
  3374. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3375. struct sockaddr_qrtr sq = { 0 };
  3376. int ret = 0;
  3377. cnss_pr_dbg("IMS server arrive: node %u port %u\n",
  3378. service->node, service->port);
  3379. sq.sq_family = AF_QIPCRTR;
  3380. sq.sq_node = service->node;
  3381. sq.sq_port = service->port;
  3382. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3383. if (ret < 0) {
  3384. cnss_pr_err("Fail to connect to remote service port\n");
  3385. return ret;
  3386. }
  3387. set_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3388. cnss_pr_dbg("IMS Server Connected: 0x%lx\n",
  3389. plat_priv->driver_state);
  3390. ret = ims_subscribe_for_indication_send_async(plat_priv);
  3391. return ret;
  3392. }
  3393. static void ims_del_server(struct qmi_handle *qmi,
  3394. struct qmi_service *service)
  3395. {
  3396. struct cnss_plat_data *plat_priv =
  3397. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3398. cnss_pr_dbg("IMS server exit\n");
  3399. clear_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3400. }
  3401. static struct qmi_ops ims_qmi_ops = {
  3402. .new_server = ims_new_server,
  3403. .del_server = ims_del_server,
  3404. };
  3405. int cnss_register_ims_service(struct cnss_plat_data *plat_priv)
  3406. { int ret;
  3407. ret = qmi_handle_init(&plat_priv->ims_qmi,
  3408. IMSPRIVATE_SERVICE_MAX_MSG_LEN,
  3409. &ims_qmi_ops, qmi_ims_msg_handlers);
  3410. if (ret < 0)
  3411. return ret;
  3412. ret = qmi_add_lookup(&plat_priv->ims_qmi, IMSPRIVATE_SERVICE_ID_V01,
  3413. IMSPRIVATE_SERVICE_VERS_V01, 0);
  3414. return ret;
  3415. }
  3416. void cnss_unregister_ims_service(struct cnss_plat_data *plat_priv)
  3417. {
  3418. qmi_handle_release(&plat_priv->ims_qmi);
  3419. }