dp_ipa.c 122 KB

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  1. /*
  2. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <wlan_ipa_ucfg_api.h>
  18. #include <wlan_ipa_core.h>
  19. #include <qdf_ipa_wdi3.h>
  20. #include <qdf_types.h>
  21. #include <qdf_lock.h>
  22. #include <hal_hw_headers.h>
  23. #include <hal_api.h>
  24. #include <hal_reo.h>
  25. #include <hif.h>
  26. #include <htt.h>
  27. #include <wdi_event.h>
  28. #include <queue.h>
  29. #include "dp_types.h"
  30. #include "dp_htt.h"
  31. #include "dp_tx.h"
  32. #include "dp_rx.h"
  33. #include "dp_ipa.h"
  34. #include "dp_internal.h"
  35. #ifdef WIFI_MONITOR_SUPPORT
  36. #include "dp_mon.h"
  37. #endif
  38. #ifdef FEATURE_WDS
  39. #include "dp_txrx_wds.h"
  40. #endif
  41. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  42. #include <pld_common.h>
  43. #endif
  44. #ifdef IPA_OFFLOAD
  45. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  46. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  47. /* WAR for IPA_OFFLOAD case. In some cases, its observed that WBM tries to
  48. * release a buffer into WBM2SW RELEASE ring for IPA, and the ring is full.
  49. * This causes back pressure, resulting in a FW crash.
  50. * By leaving some entries with no buffer attached, WBM will be able to write
  51. * to the ring, and from dumps we can figure out the buffer which is causing
  52. * this issue.
  53. */
  54. #define DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES 16
  55. /**
  56. * struct dp_ipa_reo_remap_record - history for dp ipa reo remaps
  57. * @timestamp: Timestamp when remap occurs
  58. * @ix0_reg: reo destination ring IX0 value
  59. * @ix2_reg: reo destination ring IX2 value
  60. * @ix3_reg: reo destination ring IX3 value
  61. */
  62. struct dp_ipa_reo_remap_record {
  63. uint64_t timestamp;
  64. uint32_t ix0_reg;
  65. uint32_t ix2_reg;
  66. uint32_t ix3_reg;
  67. };
  68. #ifdef IPA_WDS_EASYMESH_FEATURE
  69. #define WLAN_IPA_META_DATA_MASK htonl(0x000000FF)
  70. #else
  71. #define WLAN_IPA_META_DATA_MASK htonl(0x00FF0000)
  72. #endif
  73. #define REO_REMAP_HISTORY_SIZE 32
  74. #if defined(IPA_WDI3_TX_TWO_PIPES) && defined(QCA_IPA_LL_TX_FLOW_CONTROL)
  75. static bool dp_ipa_is_alt_tx_required(struct dp_soc *soc)
  76. {
  77. uint8_t num_radio = soc->pdev_count;
  78. if (num_radio > 1)
  79. return true;
  80. else
  81. return false;
  82. }
  83. #elif defined(IPA_WDI3_TX_TWO_PIPES)
  84. static bool dp_ipa_is_alt_tx_required(struct dp_soc *soc)
  85. {
  86. return true;
  87. }
  88. #else
  89. static bool dp_ipa_is_alt_tx_required(struct dp_soc *soc)
  90. {
  91. return false;
  92. }
  93. #endif
  94. struct dp_ipa_reo_remap_record dp_ipa_reo_remap_history[REO_REMAP_HISTORY_SIZE];
  95. static qdf_atomic_t dp_ipa_reo_remap_history_index;
  96. static int dp_ipa_reo_remap_record_index_next(qdf_atomic_t *index)
  97. {
  98. int next = qdf_atomic_inc_return(index);
  99. if (next == REO_REMAP_HISTORY_SIZE)
  100. qdf_atomic_sub(REO_REMAP_HISTORY_SIZE, index);
  101. return next % REO_REMAP_HISTORY_SIZE;
  102. }
  103. /**
  104. * dp_ipa_reo_remap_history_add() - Record dp ipa reo remap values
  105. * @ix0_val: reo destination ring IX0 value
  106. * @ix2_val: reo destination ring IX2 value
  107. * @ix3_val: reo destination ring IX3 value
  108. *
  109. * Return: None
  110. */
  111. static void dp_ipa_reo_remap_history_add(uint32_t ix0_val, uint32_t ix2_val,
  112. uint32_t ix3_val)
  113. {
  114. int idx = dp_ipa_reo_remap_record_index_next(
  115. &dp_ipa_reo_remap_history_index);
  116. struct dp_ipa_reo_remap_record *record = &dp_ipa_reo_remap_history[idx];
  117. record->timestamp = qdf_get_log_timestamp();
  118. record->ix0_reg = ix0_val;
  119. record->ix2_reg = ix2_val;
  120. record->ix3_reg = ix3_val;
  121. }
  122. static QDF_STATUS __dp_ipa_handle_buf_smmu_mapping(struct dp_soc *soc,
  123. qdf_nbuf_t nbuf,
  124. uint32_t size,
  125. bool create,
  126. const char *func,
  127. uint32_t line)
  128. {
  129. qdf_mem_info_t mem_map_table = {0};
  130. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  131. qdf_ipa_wdi_hdl_t hdl;
  132. /* Need to handle the case when one soc will
  133. * have multiple pdev(radio's), Currently passing
  134. * pdev_id as 0 assuming 1 soc has only 1 radio.
  135. */
  136. hdl = wlan_ipa_get_hdl(soc->ctrl_psoc, 0);
  137. if (hdl == DP_IPA_HDL_INVALID) {
  138. dp_err("IPA handle is invalid");
  139. return QDF_STATUS_E_INVAL;
  140. }
  141. qdf_update_mem_map_table(soc->osdev, &mem_map_table,
  142. qdf_nbuf_get_frag_paddr(nbuf, 0),
  143. size);
  144. if (create) {
  145. /* Assert if PA is zero */
  146. qdf_assert_always(mem_map_table.pa);
  147. ret = qdf_nbuf_smmu_map_debug(nbuf, hdl, 1, &mem_map_table,
  148. func, line);
  149. } else {
  150. ret = qdf_nbuf_smmu_unmap_debug(nbuf, hdl, 1, &mem_map_table,
  151. func, line);
  152. }
  153. qdf_assert_always(!ret);
  154. /* Return status of mapping/unmapping is stored in
  155. * mem_map_table.result field, assert if the result
  156. * is failure
  157. */
  158. if (create)
  159. qdf_assert_always(!mem_map_table.result);
  160. else
  161. qdf_assert_always(mem_map_table.result >= mem_map_table.size);
  162. return ret;
  163. }
  164. QDF_STATUS dp_ipa_handle_rx_buf_smmu_mapping(struct dp_soc *soc,
  165. qdf_nbuf_t nbuf,
  166. uint32_t size,
  167. bool create, const char *func,
  168. uint32_t line)
  169. {
  170. struct dp_pdev *pdev;
  171. int i;
  172. for (i = 0; i < soc->pdev_count; i++) {
  173. pdev = soc->pdev_list[i];
  174. if (pdev && dp_monitor_is_configured(pdev))
  175. return QDF_STATUS_SUCCESS;
  176. }
  177. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx) ||
  178. !qdf_mem_smmu_s1_enabled(soc->osdev))
  179. return QDF_STATUS_SUCCESS;
  180. /*
  181. * Even if ipa pipes is disabled, but if it's unmap
  182. * operation and nbuf has done ipa smmu map before,
  183. * do ipa smmu unmap as well.
  184. */
  185. if (!qdf_atomic_read(&soc->ipa_pipes_enabled)) {
  186. if (!create && qdf_nbuf_is_rx_ipa_smmu_map(nbuf)) {
  187. DP_STATS_INC(soc, rx.err.ipa_unmap_no_pipe, 1);
  188. } else {
  189. return QDF_STATUS_SUCCESS;
  190. }
  191. }
  192. if (qdf_unlikely(create == qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  193. if (create) {
  194. DP_STATS_INC(soc, rx.err.ipa_smmu_map_dup, 1);
  195. } else {
  196. DP_STATS_INC(soc, rx.err.ipa_smmu_unmap_dup, 1);
  197. }
  198. return QDF_STATUS_E_INVAL;
  199. }
  200. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  201. return __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, size, create,
  202. func, line);
  203. }
  204. static QDF_STATUS __dp_ipa_tx_buf_smmu_mapping(
  205. struct dp_soc *soc,
  206. struct dp_pdev *pdev,
  207. bool create,
  208. const char *func,
  209. uint32_t line)
  210. {
  211. uint32_t index;
  212. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  213. uint32_t tx_buffer_cnt = soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  214. qdf_nbuf_t nbuf;
  215. uint32_t buf_len;
  216. if (!ipa_is_ready()) {
  217. dp_info("IPA is not READY");
  218. return 0;
  219. }
  220. for (index = 0; index < tx_buffer_cnt; index++) {
  221. nbuf = (qdf_nbuf_t)
  222. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[index];
  223. if (!nbuf)
  224. continue;
  225. buf_len = qdf_nbuf_get_data_len(nbuf);
  226. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  227. create, func, line);
  228. }
  229. return ret;
  230. }
  231. #ifndef QCA_OL_DP_SRNG_LOCK_LESS_ACCESS
  232. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  233. bool lock_required)
  234. {
  235. hal_ring_handle_t hal_ring_hdl;
  236. int ring;
  237. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  238. hal_ring_hdl = soc->reo_dest_ring[ring].hal_srng;
  239. hal_srng_lock(hal_ring_hdl);
  240. soc->ipa_reo_ctx_lock_required[ring] = lock_required;
  241. hal_srng_unlock(hal_ring_hdl);
  242. }
  243. }
  244. #else
  245. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  246. bool lock_required)
  247. {
  248. }
  249. #endif
  250. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  251. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  252. struct dp_pdev *pdev,
  253. bool create,
  254. const char *func,
  255. uint32_t line)
  256. {
  257. struct rx_desc_pool *rx_pool;
  258. uint8_t pdev_id;
  259. uint32_t num_desc, page_id, offset, i;
  260. uint16_t num_desc_per_page;
  261. union dp_rx_desc_list_elem_t *rx_desc_elem;
  262. struct dp_rx_desc *rx_desc;
  263. qdf_nbuf_t nbuf;
  264. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  265. if (!qdf_ipa_is_ready())
  266. return ret;
  267. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  268. return ret;
  269. pdev_id = pdev->pdev_id;
  270. rx_pool = &soc->rx_desc_buf[pdev_id];
  271. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  272. qdf_spin_lock_bh(&rx_pool->lock);
  273. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  274. num_desc = rx_pool->pool_size;
  275. num_desc_per_page = rx_pool->desc_pages.num_element_per_page;
  276. for (i = 0; i < num_desc; i++) {
  277. page_id = i / num_desc_per_page;
  278. offset = i % num_desc_per_page;
  279. if (qdf_unlikely(!(rx_pool->desc_pages.cacheable_pages)))
  280. break;
  281. rx_desc_elem = dp_rx_desc_find(page_id, offset, rx_pool);
  282. rx_desc = &rx_desc_elem->rx_desc;
  283. if ((!(rx_desc->in_use)) || rx_desc->unmapped)
  284. continue;
  285. nbuf = rx_desc->nbuf;
  286. if (qdf_unlikely(create ==
  287. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  288. if (create) {
  289. DP_STATS_INC(soc,
  290. rx.err.ipa_smmu_map_dup, 1);
  291. } else {
  292. DP_STATS_INC(soc,
  293. rx.err.ipa_smmu_unmap_dup, 1);
  294. }
  295. continue;
  296. }
  297. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  298. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  299. rx_pool->buf_size,
  300. create, func, line);
  301. }
  302. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  303. qdf_spin_unlock_bh(&rx_pool->lock);
  304. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  305. return ret;
  306. }
  307. #else
  308. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(
  309. struct dp_soc *soc,
  310. struct dp_pdev *pdev,
  311. bool create,
  312. const char *func,
  313. uint32_t line)
  314. {
  315. struct rx_desc_pool *rx_pool;
  316. uint8_t pdev_id;
  317. qdf_nbuf_t nbuf;
  318. int i;
  319. if (!qdf_ipa_is_ready())
  320. return QDF_STATUS_SUCCESS;
  321. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  322. return QDF_STATUS_SUCCESS;
  323. pdev_id = pdev->pdev_id;
  324. rx_pool = &soc->rx_desc_buf[pdev_id];
  325. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  326. qdf_spin_lock_bh(&rx_pool->lock);
  327. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  328. for (i = 0; i < rx_pool->pool_size; i++) {
  329. if ((!(rx_pool->array[i].rx_desc.in_use)) ||
  330. rx_pool->array[i].rx_desc.unmapped)
  331. continue;
  332. nbuf = rx_pool->array[i].rx_desc.nbuf;
  333. if (qdf_unlikely(create ==
  334. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  335. if (create) {
  336. DP_STATS_INC(soc,
  337. rx.err.ipa_smmu_map_dup, 1);
  338. } else {
  339. DP_STATS_INC(soc,
  340. rx.err.ipa_smmu_unmap_dup, 1);
  341. }
  342. continue;
  343. }
  344. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  345. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, rx_pool->buf_size,
  346. create, func, line);
  347. }
  348. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  349. qdf_spin_unlock_bh(&rx_pool->lock);
  350. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  351. return QDF_STATUS_SUCCESS;
  352. }
  353. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  354. static QDF_STATUS dp_ipa_get_shared_mem_info(qdf_device_t osdev,
  355. qdf_shared_mem_t *shared_mem,
  356. void *cpu_addr,
  357. qdf_dma_addr_t dma_addr,
  358. uint32_t size)
  359. {
  360. qdf_dma_addr_t paddr;
  361. int ret;
  362. shared_mem->vaddr = cpu_addr;
  363. qdf_mem_set_dma_size(osdev, &shared_mem->mem_info, size);
  364. *qdf_mem_get_dma_addr_ptr(osdev, &shared_mem->mem_info) = dma_addr;
  365. paddr = qdf_mem_paddr_from_dmaaddr(osdev, dma_addr);
  366. qdf_mem_set_dma_pa(osdev, &shared_mem->mem_info, paddr);
  367. ret = qdf_mem_dma_get_sgtable(osdev->dev, &shared_mem->sgtable,
  368. shared_mem->vaddr, dma_addr, size);
  369. if (ret) {
  370. dp_err("Unable to get DMA sgtable");
  371. return QDF_STATUS_E_NOMEM;
  372. }
  373. qdf_dma_get_sgtable_dma_addr(&shared_mem->sgtable);
  374. return QDF_STATUS_SUCCESS;
  375. }
  376. /**
  377. * dp_ipa_get_tx_bank_id() - API to get TCL bank id
  378. * @soc: dp_soc handle
  379. * @bank_id: out parameter for bank id
  380. *
  381. * Return: QDF_STATUS
  382. */
  383. static QDF_STATUS dp_ipa_get_tx_bank_id(struct dp_soc *soc, uint8_t *bank_id)
  384. {
  385. if (soc->arch_ops.ipa_get_bank_id) {
  386. *bank_id = soc->arch_ops.ipa_get_bank_id(soc);
  387. if (*bank_id < 0) {
  388. return QDF_STATUS_E_INVAL;
  389. } else {
  390. dp_info("bank_id %u", *bank_id);
  391. return QDF_STATUS_SUCCESS;
  392. }
  393. } else {
  394. return QDF_STATUS_E_NOSUPPORT;
  395. }
  396. }
  397. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  398. defined(CONFIG_IPA_WDI_UNIFIED_API)
  399. static void dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  400. qdf_ipa_wdi_pipe_setup_info_t *tx)
  401. {
  402. uint8_t bank_id;
  403. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  404. QDF_IPA_WDI_SETUP_INFO_RX_BANK_ID(tx, bank_id);
  405. }
  406. static void
  407. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  408. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  409. {
  410. uint8_t bank_id;
  411. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  412. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_BANK_ID(tx_smmu, bank_id);
  413. }
  414. #else
  415. static inline void
  416. dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  417. qdf_ipa_wdi_pipe_setup_info_t *tx)
  418. {
  419. }
  420. static inline void
  421. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  422. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  423. {
  424. }
  425. #endif
  426. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  427. static void
  428. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  429. qdf_ipa_wdi_pipe_setup_info_t *tx)
  430. {
  431. uint8_t pmac_id = 0;
  432. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  433. if (soc->pdev_count > 1)
  434. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  435. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  436. }
  437. static void
  438. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  439. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  440. {
  441. uint8_t pmac_id = 0;
  442. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  443. if (soc->pdev_count > 1)
  444. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  445. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  446. }
  447. static void
  448. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  449. qdf_ipa_wdi_pipe_setup_info_t *tx)
  450. {
  451. uint8_t pmac_id;
  452. pmac_id = soc->pdev_list[0]->lmac_id;
  453. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  454. }
  455. static void
  456. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  457. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  458. {
  459. uint8_t pmac_id;
  460. pmac_id = soc->pdev_list[0]->lmac_id;
  461. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  462. }
  463. #else
  464. static inline void
  465. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  466. qdf_ipa_wdi_pipe_setup_info_t *tx)
  467. {
  468. }
  469. static inline void
  470. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  471. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  472. {
  473. }
  474. static inline void
  475. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  476. qdf_ipa_wdi_pipe_setup_info_t *tx)
  477. {
  478. }
  479. static inline void
  480. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  481. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  482. {
  483. }
  484. #endif
  485. #ifdef IPA_WDI3_TX_TWO_PIPES
  486. static void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  487. {
  488. struct dp_ipa_resources *ipa_res;
  489. qdf_nbuf_t nbuf;
  490. int idx;
  491. for (idx = 0; idx < soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt; idx++) {
  492. nbuf = (qdf_nbuf_t)
  493. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx];
  494. if (!nbuf)
  495. continue;
  496. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  497. qdf_mem_dp_tx_skb_cnt_dec();
  498. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  499. qdf_nbuf_free(nbuf);
  500. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx] =
  501. (void *)NULL;
  502. }
  503. qdf_mem_free(soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  504. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  505. ipa_res = &pdev->ipa_resource;
  506. if (!ipa_res->is_db_ddr_mapped && ipa_res->tx_alt_comp_doorbell_vaddr)
  507. iounmap(ipa_res->tx_alt_comp_doorbell_vaddr);
  508. qdf_mem_free_sgtable(&ipa_res->tx_alt_ring.sgtable);
  509. qdf_mem_free_sgtable(&ipa_res->tx_alt_comp_ring.sgtable);
  510. }
  511. static int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  512. {
  513. uint32_t tx_buffer_count;
  514. uint32_t ring_base_align = 8;
  515. qdf_dma_addr_t buffer_paddr;
  516. struct hal_srng *wbm_srng = (struct hal_srng *)
  517. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  518. struct hal_srng_params srng_params;
  519. uint32_t wbm_bm_id;
  520. void *ring_entry;
  521. int num_entries;
  522. qdf_nbuf_t nbuf;
  523. int retval = QDF_STATUS_SUCCESS;
  524. int max_alloc_count = 0;
  525. /*
  526. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  527. * unsigned int uc_tx_buf_sz =
  528. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  529. */
  530. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  531. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  532. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  533. IPA_TX_ALT_RING_IDX);
  534. hal_get_srng_params(soc->hal_soc,
  535. hal_srng_to_hal_ring_handle(wbm_srng),
  536. &srng_params);
  537. num_entries = srng_params.num_entries;
  538. max_alloc_count =
  539. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  540. if (max_alloc_count <= 0) {
  541. dp_err("incorrect value for buffer count %u", max_alloc_count);
  542. return -EINVAL;
  543. }
  544. dp_info("requested %d buffers to be posted to wbm ring",
  545. max_alloc_count);
  546. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned =
  547. qdf_mem_malloc(num_entries *
  548. sizeof(*soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned));
  549. if (!soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned) {
  550. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  551. return -ENOMEM;
  552. }
  553. hal_srng_access_start_unlocked(soc->hal_soc,
  554. hal_srng_to_hal_ring_handle(wbm_srng));
  555. /*
  556. * Allocate Tx buffers as many as possible.
  557. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  558. * Populate Tx buffers into WBM2IPA ring
  559. * This initial buffer population will simulate H/W as source ring,
  560. * and update HP
  561. */
  562. for (tx_buffer_count = 0;
  563. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  564. nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
  565. if (!nbuf)
  566. break;
  567. ring_entry = hal_srng_dst_get_next_hp(
  568. soc->hal_soc,
  569. hal_srng_to_hal_ring_handle(wbm_srng));
  570. if (!ring_entry) {
  571. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  572. "%s: Failed to get WBM ring entry",
  573. __func__);
  574. qdf_nbuf_free(nbuf);
  575. break;
  576. }
  577. qdf_nbuf_map_single(soc->osdev, nbuf,
  578. QDF_DMA_BIDIRECTIONAL);
  579. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  580. qdf_mem_dp_tx_skb_cnt_inc();
  581. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  582. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  583. buffer_paddr, 0, wbm_bm_id);
  584. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[
  585. tx_buffer_count] = (void *)nbuf;
  586. }
  587. hal_srng_access_end_unlocked(soc->hal_soc,
  588. hal_srng_to_hal_ring_handle(wbm_srng));
  589. soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt = tx_buffer_count;
  590. if (tx_buffer_count) {
  591. dp_info("IPA TX buffer pool2: %d allocated", tx_buffer_count);
  592. } else {
  593. dp_err("Failed to allocate IPA TX buffer pool2");
  594. qdf_mem_free(
  595. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  596. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  597. retval = -ENOMEM;
  598. }
  599. return retval;
  600. }
  601. static QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  602. {
  603. struct dp_soc *soc = pdev->soc;
  604. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  605. ipa_res->tx_alt_ring_num_alloc_buffer =
  606. (uint32_t)soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt;
  607. dp_ipa_get_shared_mem_info(
  608. soc->osdev, &ipa_res->tx_alt_ring,
  609. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  610. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  611. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  612. dp_ipa_get_shared_mem_info(
  613. soc->osdev, &ipa_res->tx_alt_comp_ring,
  614. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  615. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  616. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  617. if (!qdf_mem_get_dma_addr(soc->osdev,
  618. &ipa_res->tx_alt_comp_ring.mem_info))
  619. return QDF_STATUS_E_FAILURE;
  620. return QDF_STATUS_SUCCESS;
  621. }
  622. static void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  623. {
  624. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  625. struct hal_srng *hal_srng;
  626. struct hal_srng_params srng_params;
  627. unsigned long addr_offset, dev_base_paddr;
  628. /* IPA TCL_DATA Alternative Ring - HAL_SRNG_SW2TCL2 */
  629. hal_srng = (struct hal_srng *)
  630. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng;
  631. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  632. hal_srng_to_hal_ring_handle(hal_srng),
  633. &srng_params);
  634. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr =
  635. srng_params.ring_base_paddr;
  636. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr =
  637. srng_params.ring_base_vaddr;
  638. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size =
  639. (srng_params.num_entries * srng_params.entry_size) << 2;
  640. /*
  641. * For the register backed memory addresses, use the scn->mem_pa to
  642. * calculate the physical address of the shadow registers
  643. */
  644. dev_base_paddr =
  645. (unsigned long)
  646. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  647. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  648. (unsigned long)(hal_soc->dev_base_addr);
  649. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr =
  650. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  651. dp_info("IPA TCL_DATA Alt Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  652. (unsigned int)addr_offset,
  653. (unsigned int)dev_base_paddr,
  654. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr),
  655. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  656. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  657. srng_params.num_entries,
  658. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  659. /* IPA TX Alternative COMP Ring - HAL_SRNG_WBM2SW4_RELEASE */
  660. hal_srng = (struct hal_srng *)
  661. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  662. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  663. hal_srng_to_hal_ring_handle(hal_srng),
  664. &srng_params);
  665. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr =
  666. srng_params.ring_base_paddr;
  667. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr =
  668. srng_params.ring_base_vaddr;
  669. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size =
  670. (srng_params.num_entries * srng_params.entry_size) << 2;
  671. soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr =
  672. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  673. hal_srng_to_hal_ring_handle(hal_srng));
  674. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  675. (unsigned long)(hal_soc->dev_base_addr);
  676. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr =
  677. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  678. dp_info("IPA TX Alt COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  679. (unsigned int)addr_offset,
  680. (unsigned int)dev_base_paddr,
  681. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr),
  682. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  683. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  684. srng_params.num_entries,
  685. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  686. }
  687. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  688. {
  689. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  690. uint32_t rx_ready_doorbell_dmaaddr;
  691. uint32_t tx_comp_doorbell_dmaaddr;
  692. struct dp_soc *soc = pdev->soc;
  693. int ret = 0;
  694. if (ipa_res->is_db_ddr_mapped)
  695. ipa_res->tx_comp_doorbell_vaddr =
  696. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  697. else
  698. ipa_res->tx_comp_doorbell_vaddr =
  699. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  700. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  701. ret = pld_smmu_map(soc->osdev->dev,
  702. ipa_res->tx_comp_doorbell_paddr,
  703. &tx_comp_doorbell_dmaaddr,
  704. sizeof(uint32_t));
  705. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  706. qdf_assert_always(!ret);
  707. ret = pld_smmu_map(soc->osdev->dev,
  708. ipa_res->rx_ready_doorbell_paddr,
  709. &rx_ready_doorbell_dmaaddr,
  710. sizeof(uint32_t));
  711. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  712. qdf_assert_always(!ret);
  713. }
  714. /* Setup for alternative TX pipe */
  715. if (dp_ipa_is_alt_tx_required(soc)) {
  716. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  717. return;
  718. if (ipa_res->is_db_ddr_mapped)
  719. ipa_res->tx_alt_comp_doorbell_vaddr =
  720. phys_to_virt(ipa_res->tx_alt_comp_doorbell_paddr);
  721. else
  722. ipa_res->tx_alt_comp_doorbell_vaddr =
  723. ioremap(ipa_res->tx_alt_comp_doorbell_paddr, 4);
  724. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  725. ret = pld_smmu_map(soc->osdev->dev,
  726. ipa_res->tx_alt_comp_doorbell_paddr,
  727. &tx_comp_doorbell_dmaaddr,
  728. sizeof(uint32_t));
  729. ipa_res->tx_alt_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  730. qdf_assert_always(!ret);
  731. }
  732. }
  733. }
  734. static void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  735. {
  736. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  737. struct dp_soc *soc = pdev->soc;
  738. int ret = 0;
  739. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  740. return;
  741. /* Unmap must be in reverse order of map */
  742. if (dp_ipa_is_alt_tx_required(soc)) {
  743. if (ipa_res->tx_alt_comp_doorbell_paddr) {
  744. ret = pld_smmu_unmap(soc->osdev->dev,
  745. ipa_res->tx_alt_comp_doorbell_paddr,
  746. sizeof(uint32_t));
  747. qdf_assert_always(!ret);
  748. }
  749. }
  750. ret = pld_smmu_unmap(soc->osdev->dev,
  751. ipa_res->rx_ready_doorbell_paddr,
  752. sizeof(uint32_t));
  753. qdf_assert_always(!ret);
  754. ret = pld_smmu_unmap(soc->osdev->dev,
  755. ipa_res->tx_comp_doorbell_paddr,
  756. sizeof(uint32_t));
  757. qdf_assert_always(!ret);
  758. }
  759. static QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  760. struct dp_pdev *pdev,
  761. bool create, const char *func,
  762. uint32_t line)
  763. {
  764. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  765. struct ipa_dp_tx_rsc *rsc;
  766. uint32_t tx_buffer_cnt;
  767. uint32_t buf_len;
  768. qdf_nbuf_t nbuf;
  769. uint32_t index;
  770. if (!ipa_is_ready()) {
  771. dp_info("IPA is not READY");
  772. return QDF_STATUS_SUCCESS;
  773. }
  774. rsc = &soc->ipa_uc_tx_rsc_alt;
  775. tx_buffer_cnt = rsc->alloc_tx_buf_cnt;
  776. for (index = 0; index < tx_buffer_cnt; index++) {
  777. nbuf = (qdf_nbuf_t)rsc->tx_buf_pool_vaddr_unaligned[index];
  778. if (!nbuf)
  779. continue;
  780. buf_len = qdf_nbuf_get_data_len(nbuf);
  781. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  782. create, func, line);
  783. }
  784. return ret;
  785. }
  786. static void dp_ipa_wdi_tx_alt_pipe_params(struct dp_soc *soc,
  787. struct dp_ipa_resources *ipa_res,
  788. qdf_ipa_wdi_pipe_setup_info_t *tx)
  789. {
  790. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS1;
  791. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  792. qdf_mem_get_dma_addr(soc->osdev,
  793. &ipa_res->tx_alt_comp_ring.mem_info);
  794. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  795. qdf_mem_get_dma_size(soc->osdev,
  796. &ipa_res->tx_alt_comp_ring.mem_info);
  797. /* WBM Tail Pointer Address */
  798. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  799. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  800. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  801. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  802. qdf_mem_get_dma_addr(soc->osdev,
  803. &ipa_res->tx_alt_ring.mem_info);
  804. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  805. qdf_mem_get_dma_size(soc->osdev,
  806. &ipa_res->tx_alt_ring.mem_info);
  807. /* TCL Head Pointer Address */
  808. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  809. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  810. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  811. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  812. ipa_res->tx_alt_ring_num_alloc_buffer;
  813. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  814. dp_ipa_setup_tx_params_bank_id(soc, tx);
  815. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  816. dp_ipa_setup_tx_alt_params_pmac_id(soc, tx);
  817. }
  818. static void
  819. dp_ipa_wdi_tx_alt_pipe_smmu_params(struct dp_soc *soc,
  820. struct dp_ipa_resources *ipa_res,
  821. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  822. {
  823. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) = IPA_CLIENT_WLAN2_CONS1;
  824. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  825. &ipa_res->tx_alt_comp_ring.sgtable,
  826. sizeof(sgtable_t));
  827. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  828. qdf_mem_get_dma_size(soc->osdev,
  829. &ipa_res->tx_alt_comp_ring.mem_info);
  830. /* WBM Tail Pointer Address */
  831. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  832. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  833. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  834. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  835. &ipa_res->tx_alt_ring.sgtable,
  836. sizeof(sgtable_t));
  837. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  838. qdf_mem_get_dma_size(soc->osdev,
  839. &ipa_res->tx_alt_ring.mem_info);
  840. /* TCL Head Pointer Address */
  841. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  842. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  843. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  844. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  845. ipa_res->tx_alt_ring_num_alloc_buffer;
  846. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  847. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  848. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  849. dp_ipa_setup_tx_alt_smmu_params_pmac_id(soc, tx_smmu);
  850. }
  851. static void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc,
  852. struct dp_ipa_resources *res,
  853. qdf_ipa_wdi_conn_in_params_t *in)
  854. {
  855. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu = NULL;
  856. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  857. qdf_ipa_ep_cfg_t *tx_cfg;
  858. QDF_IPA_WDI_CONN_IN_PARAMS_IS_TX1_USED(in) = true;
  859. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  860. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE_SMMU(in);
  861. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  862. dp_ipa_wdi_tx_alt_pipe_smmu_params(soc, res, tx_smmu);
  863. } else {
  864. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE(in);
  865. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx);
  866. dp_ipa_wdi_tx_alt_pipe_params(soc, res, tx);
  867. }
  868. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  869. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  870. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  871. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  872. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  873. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  874. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  875. }
  876. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  877. qdf_ipa_wdi_conn_out_params_t *out)
  878. {
  879. res->tx_comp_doorbell_paddr =
  880. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  881. res->rx_ready_doorbell_paddr =
  882. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  883. res->tx_alt_comp_doorbell_paddr =
  884. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_ALT_DB_PA(out);
  885. }
  886. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  887. uint8_t session_id)
  888. {
  889. bool is_2g_iface = session_id & IPA_SESSION_ID_SHIFT;
  890. session_id = session_id >> IPA_SESSION_ID_SHIFT;
  891. dp_debug("session_id %u is_2g_iface %d", session_id, is_2g_iface);
  892. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  893. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_TX1_USED(in) = is_2g_iface;
  894. }
  895. static void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  896. struct dp_ipa_resources *res)
  897. {
  898. struct hal_srng *wbm_srng;
  899. /* Init first TX comp ring */
  900. wbm_srng = (struct hal_srng *)
  901. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  902. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  903. res->tx_comp_doorbell_vaddr);
  904. /* Init the alternate TX comp ring */
  905. if (dp_ipa_is_alt_tx_required(soc)) {
  906. if (!res->tx_alt_comp_doorbell_paddr)
  907. return;
  908. wbm_srng = (struct hal_srng *)
  909. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  910. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  911. res->tx_alt_comp_doorbell_vaddr);
  912. }
  913. }
  914. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  915. struct dp_ipa_resources *ipa_res)
  916. {
  917. struct hal_srng *wbm_srng;
  918. wbm_srng = (struct hal_srng *)
  919. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  920. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  921. ipa_res->tx_comp_doorbell_paddr);
  922. dp_info("paddr %pK vaddr %pK",
  923. (void *)ipa_res->tx_comp_doorbell_paddr,
  924. (void *)ipa_res->tx_comp_doorbell_vaddr);
  925. /* Setup for alternative TX comp ring */
  926. if (dp_ipa_is_alt_tx_required(soc)) {
  927. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  928. return;
  929. wbm_srng = (struct hal_srng *)
  930. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  931. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  932. ipa_res->tx_alt_comp_doorbell_paddr);
  933. dp_info("paddr %pK vaddr %pK",
  934. (void *)ipa_res->tx_alt_comp_doorbell_paddr,
  935. (void *)ipa_res->tx_alt_comp_doorbell_vaddr);
  936. }
  937. }
  938. #ifdef IPA_SET_RESET_TX_DB_PA
  939. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  940. struct dp_ipa_resources *ipa_res)
  941. {
  942. hal_ring_handle_t wbm_srng;
  943. qdf_dma_addr_t hp_addr;
  944. wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  945. if (!wbm_srng)
  946. return QDF_STATUS_E_FAILURE;
  947. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  948. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  949. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  950. if (!dp_ipa_is_alt_tx_required(soc))
  951. return QDF_STATUS_SUCCESS;
  952. /* Reset alternative TX comp ring */
  953. wbm_srng = soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  954. if (!wbm_srng)
  955. return QDF_STATUS_E_FAILURE;
  956. hp_addr = soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr;
  957. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  958. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  959. return QDF_STATUS_SUCCESS;
  960. }
  961. #endif /* IPA_SET_RESET_TX_DB_PA */
  962. #else /* !IPA_WDI3_TX_TWO_PIPES */
  963. static inline
  964. void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  965. {
  966. }
  967. static inline void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  968. {
  969. }
  970. static inline int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  971. {
  972. return 0;
  973. }
  974. static inline QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  975. {
  976. return QDF_STATUS_SUCCESS;
  977. }
  978. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  979. {
  980. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  981. uint32_t rx_ready_doorbell_dmaaddr;
  982. uint32_t tx_comp_doorbell_dmaaddr;
  983. struct dp_soc *soc = pdev->soc;
  984. int ret = 0;
  985. if (ipa_res->is_db_ddr_mapped)
  986. ipa_res->tx_comp_doorbell_vaddr =
  987. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  988. else
  989. ipa_res->tx_comp_doorbell_vaddr =
  990. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  991. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  992. ret = pld_smmu_map(soc->osdev->dev,
  993. ipa_res->tx_comp_doorbell_paddr,
  994. &tx_comp_doorbell_dmaaddr,
  995. sizeof(uint32_t));
  996. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  997. qdf_assert_always(!ret);
  998. ret = pld_smmu_map(soc->osdev->dev,
  999. ipa_res->rx_ready_doorbell_paddr,
  1000. &rx_ready_doorbell_dmaaddr,
  1001. sizeof(uint32_t));
  1002. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  1003. qdf_assert_always(!ret);
  1004. }
  1005. }
  1006. static inline void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  1007. {
  1008. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1009. struct dp_soc *soc = pdev->soc;
  1010. int ret = 0;
  1011. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  1012. return;
  1013. ret = pld_smmu_unmap(soc->osdev->dev,
  1014. ipa_res->rx_ready_doorbell_paddr,
  1015. sizeof(uint32_t));
  1016. qdf_assert_always(!ret);
  1017. ret = pld_smmu_unmap(soc->osdev->dev,
  1018. ipa_res->tx_comp_doorbell_paddr,
  1019. sizeof(uint32_t));
  1020. qdf_assert_always(!ret);
  1021. }
  1022. static inline QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  1023. struct dp_pdev *pdev,
  1024. bool create,
  1025. const char *func,
  1026. uint32_t line)
  1027. {
  1028. return QDF_STATUS_SUCCESS;
  1029. }
  1030. static inline
  1031. void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc, struct dp_ipa_resources *res,
  1032. qdf_ipa_wdi_conn_in_params_t *in)
  1033. {
  1034. }
  1035. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  1036. qdf_ipa_wdi_conn_out_params_t *out)
  1037. {
  1038. res->tx_comp_doorbell_paddr =
  1039. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  1040. res->rx_ready_doorbell_paddr =
  1041. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  1042. }
  1043. #ifdef IPA_WDS_EASYMESH_FEATURE
  1044. /**
  1045. * dp_ipa_setup_iface_session_id() - Pass vdev id to IPA
  1046. * @in: ipa in params
  1047. * @session_id: vdev id
  1048. *
  1049. * Pass Vdev id to IPA, IPA metadata order is changed and vdev id
  1050. * is stored at higher nibble so, no shift is required.
  1051. *
  1052. * Return: none
  1053. */
  1054. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1055. uint8_t session_id)
  1056. {
  1057. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id);
  1058. }
  1059. #else
  1060. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1061. uint8_t session_id)
  1062. {
  1063. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  1064. }
  1065. #endif
  1066. static inline void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  1067. struct dp_ipa_resources *res)
  1068. {
  1069. struct hal_srng *wbm_srng = (struct hal_srng *)
  1070. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1071. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  1072. res->tx_comp_doorbell_vaddr);
  1073. }
  1074. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  1075. struct dp_ipa_resources *ipa_res)
  1076. {
  1077. struct hal_srng *wbm_srng = (struct hal_srng *)
  1078. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1079. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  1080. ipa_res->tx_comp_doorbell_paddr);
  1081. dp_info("paddr %pK vaddr %pK",
  1082. (void *)ipa_res->tx_comp_doorbell_paddr,
  1083. (void *)ipa_res->tx_comp_doorbell_vaddr);
  1084. }
  1085. #ifdef IPA_SET_RESET_TX_DB_PA
  1086. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  1087. struct dp_ipa_resources *ipa_res)
  1088. {
  1089. hal_ring_handle_t wbm_srng =
  1090. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1091. qdf_dma_addr_t hp_addr;
  1092. if (!wbm_srng)
  1093. return QDF_STATUS_E_FAILURE;
  1094. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  1095. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  1096. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  1097. return QDF_STATUS_SUCCESS;
  1098. }
  1099. #endif /* IPA_SET_RESET_TX_DB_PA */
  1100. #endif /* IPA_WDI3_TX_TWO_PIPES */
  1101. /**
  1102. * dp_tx_ipa_uc_detach() - Free autonomy TX resources
  1103. * @soc: data path instance
  1104. * @pdev: core txrx pdev context
  1105. *
  1106. * Free allocated TX buffers with WBM SRNG
  1107. *
  1108. * Return: none
  1109. */
  1110. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1111. {
  1112. int idx;
  1113. qdf_nbuf_t nbuf;
  1114. struct dp_ipa_resources *ipa_res;
  1115. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  1116. nbuf = (qdf_nbuf_t)
  1117. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx];
  1118. if (!nbuf)
  1119. continue;
  1120. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  1121. qdf_mem_dp_tx_skb_cnt_dec();
  1122. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  1123. qdf_nbuf_free(nbuf);
  1124. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
  1125. (void *)NULL;
  1126. }
  1127. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1128. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1129. ipa_res = &pdev->ipa_resource;
  1130. qdf_mem_free_sgtable(&ipa_res->tx_ring.sgtable);
  1131. qdf_mem_free_sgtable(&ipa_res->tx_comp_ring.sgtable);
  1132. }
  1133. /**
  1134. * dp_rx_ipa_uc_detach() - free autonomy RX resources
  1135. * @soc: data path instance
  1136. * @pdev: core txrx pdev context
  1137. *
  1138. * This function will detach DP RX into main device context
  1139. * will free DP Rx resources.
  1140. *
  1141. * Return: none
  1142. */
  1143. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1144. {
  1145. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1146. qdf_mem_free_sgtable(&ipa_res->rx_rdy_ring.sgtable);
  1147. qdf_mem_free_sgtable(&ipa_res->rx_refill_ring.sgtable);
  1148. }
  1149. /**
  1150. * dp_rx_alt_ipa_uc_detach() - free autonomy RX resources
  1151. * @soc: data path instance
  1152. * @pdev: core txrx pdev context
  1153. *
  1154. * This function will detach DP RX into main device context
  1155. * will free DP Rx resources.
  1156. *
  1157. * Return: none
  1158. */
  1159. #ifdef IPA_WDI3_VLAN_SUPPORT
  1160. static void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1161. {
  1162. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1163. if (!wlan_ipa_is_vlan_enabled())
  1164. return;
  1165. qdf_mem_free_sgtable(&ipa_res->rx_alt_rdy_ring.sgtable);
  1166. qdf_mem_free_sgtable(&ipa_res->rx_alt_refill_ring.sgtable);
  1167. }
  1168. #else
  1169. static inline
  1170. void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1171. { }
  1172. #endif
  1173. /**
  1174. * dp_ipa_opt_wifi_dp_cleanup() - Cleanup ipa opt wifi dp filter setup
  1175. * @soc: data path instance
  1176. * @pdev: core txrx pdev context
  1177. *
  1178. * This function will cleanup filter setup for optional wifi dp.
  1179. *
  1180. * Return: none
  1181. */
  1182. #ifdef IPA_OPT_WIFI_DP
  1183. static void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1184. {
  1185. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1186. struct hif_softc *hif = (struct hif_softc *)(hal_soc->hif_handle);
  1187. int count = qdf_atomic_read(&hif->opt_wifi_dp_rtpm_cnt);
  1188. int i;
  1189. for (i = count; i > 0; i--) {
  1190. dp_info("opt_dp: cleanup call pcie link down");
  1191. dp_ipa_pcie_link_down((struct cdp_soc_t *)soc);
  1192. }
  1193. }
  1194. #else
  1195. static inline
  1196. void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1197. {
  1198. }
  1199. #endif
  1200. int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1201. {
  1202. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1203. return QDF_STATUS_SUCCESS;
  1204. /* TX resource detach */
  1205. dp_tx_ipa_uc_detach(soc, pdev);
  1206. /* Cleanup 2nd TX pipe resources */
  1207. if (dp_ipa_is_alt_tx_required(soc))
  1208. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1209. /* RX resource detach */
  1210. dp_rx_ipa_uc_detach(soc, pdev);
  1211. /* Cleanup 2nd RX pipe resources */
  1212. dp_rx_alt_ipa_uc_detach(soc, pdev);
  1213. dp_ipa_opt_wifi_dp_cleanup(soc, pdev);
  1214. return QDF_STATUS_SUCCESS; /* success */
  1215. }
  1216. /**
  1217. * dp_tx_ipa_uc_attach() - Allocate autonomy TX resources
  1218. * @soc: data path instance
  1219. * @pdev: Physical device handle
  1220. *
  1221. * Allocate TX buffer from non-cacheable memory
  1222. * Attach allocated TX buffers with WBM SRNG
  1223. *
  1224. * Return: int
  1225. */
  1226. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1227. {
  1228. uint32_t tx_buffer_count;
  1229. uint32_t ring_base_align = 8;
  1230. qdf_dma_addr_t buffer_paddr;
  1231. struct hal_srng *wbm_srng = (struct hal_srng *)
  1232. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1233. struct hal_srng_params srng_params;
  1234. void *ring_entry;
  1235. int num_entries;
  1236. qdf_nbuf_t nbuf;
  1237. int retval = QDF_STATUS_SUCCESS;
  1238. int max_alloc_count = 0;
  1239. uint32_t wbm_bm_id;
  1240. /*
  1241. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  1242. * unsigned int uc_tx_buf_sz =
  1243. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  1244. */
  1245. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  1246. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  1247. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  1248. IPA_TCL_DATA_RING_IDX);
  1249. hal_get_srng_params(soc->hal_soc, hal_srng_to_hal_ring_handle(wbm_srng),
  1250. &srng_params);
  1251. num_entries = srng_params.num_entries;
  1252. max_alloc_count =
  1253. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  1254. if (max_alloc_count <= 0) {
  1255. dp_err("incorrect value for buffer count %u", max_alloc_count);
  1256. return -EINVAL;
  1257. }
  1258. dp_info("requested %d buffers to be posted to wbm ring",
  1259. max_alloc_count);
  1260. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned =
  1261. qdf_mem_malloc(num_entries *
  1262. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned));
  1263. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned) {
  1264. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  1265. return -ENOMEM;
  1266. }
  1267. hal_srng_access_start_unlocked(soc->hal_soc,
  1268. hal_srng_to_hal_ring_handle(wbm_srng));
  1269. /*
  1270. * Allocate Tx buffers as many as possible.
  1271. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  1272. * Populate Tx buffers into WBM2IPA ring
  1273. * This initial buffer population will simulate H/W as source ring,
  1274. * and update HP
  1275. */
  1276. for (tx_buffer_count = 0;
  1277. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  1278. nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
  1279. if (!nbuf)
  1280. break;
  1281. ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
  1282. hal_srng_to_hal_ring_handle(wbm_srng));
  1283. if (!ring_entry) {
  1284. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1285. "%s: Failed to get WBM ring entry",
  1286. __func__);
  1287. qdf_nbuf_free(nbuf);
  1288. break;
  1289. }
  1290. qdf_nbuf_map_single(soc->osdev, nbuf,
  1291. QDF_DMA_BIDIRECTIONAL);
  1292. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1293. qdf_mem_dp_tx_skb_cnt_inc();
  1294. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  1295. /*
  1296. * TODO - KIWI code can directly call the be handler
  1297. * instead of hal soc ops.
  1298. */
  1299. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  1300. buffer_paddr, 0, wbm_bm_id);
  1301. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
  1302. = (void *)nbuf;
  1303. }
  1304. hal_srng_access_end_unlocked(soc->hal_soc,
  1305. hal_srng_to_hal_ring_handle(wbm_srng));
  1306. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  1307. if (tx_buffer_count) {
  1308. dp_info("IPA WDI TX buffer: %d allocated", tx_buffer_count);
  1309. } else {
  1310. dp_err("No IPA WDI TX buffer allocated!");
  1311. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1312. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1313. retval = -ENOMEM;
  1314. }
  1315. return retval;
  1316. }
  1317. /**
  1318. * dp_rx_ipa_uc_attach() - Allocate autonomy RX resources
  1319. * @soc: data path instance
  1320. * @pdev: core txrx pdev context
  1321. *
  1322. * This function will attach a DP RX instance into the main
  1323. * device (SOC) context.
  1324. *
  1325. * Return: QDF_STATUS_SUCCESS: success
  1326. * QDF_STATUS_E_RESOURCES: Error return
  1327. */
  1328. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1329. {
  1330. return QDF_STATUS_SUCCESS;
  1331. }
  1332. int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1333. {
  1334. int error;
  1335. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1336. return QDF_STATUS_SUCCESS;
  1337. /* TX resource attach */
  1338. error = dp_tx_ipa_uc_attach(soc, pdev);
  1339. if (error) {
  1340. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1341. "%s: DP IPA UC TX attach fail code %d",
  1342. __func__, error);
  1343. return error;
  1344. }
  1345. /* Setup 2nd TX pipe */
  1346. if (dp_ipa_is_alt_tx_required(soc)) {
  1347. error = dp_ipa_tx_alt_pool_attach(soc);
  1348. if (error) {
  1349. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1350. "%s: DP IPA TX pool2 attach fail code %d",
  1351. __func__, error);
  1352. dp_tx_ipa_uc_detach(soc, pdev);
  1353. return error;
  1354. }
  1355. }
  1356. /* RX resource attach */
  1357. error = dp_rx_ipa_uc_attach(soc, pdev);
  1358. if (error) {
  1359. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1360. "%s: DP IPA UC RX attach fail code %d",
  1361. __func__, error);
  1362. if (dp_ipa_is_alt_tx_required(soc))
  1363. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1364. dp_tx_ipa_uc_detach(soc, pdev);
  1365. return error;
  1366. }
  1367. return QDF_STATUS_SUCCESS; /* success */
  1368. }
  1369. #ifdef IPA_WDI3_VLAN_SUPPORT
  1370. /**
  1371. * dp_ipa_rx_alt_ring_resource_setup() - setup IPA 2nd RX ring resources
  1372. * @soc: data path SoC handle
  1373. * @pdev: data path pdev handle
  1374. *
  1375. * Return: none
  1376. */
  1377. static
  1378. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1379. {
  1380. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1381. struct hal_srng *hal_srng;
  1382. struct hal_srng_params srng_params;
  1383. unsigned long addr_offset, dev_base_paddr;
  1384. qdf_dma_addr_t hp_addr;
  1385. if (!wlan_ipa_is_vlan_enabled())
  1386. return;
  1387. dev_base_paddr =
  1388. (unsigned long)
  1389. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1390. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW3 */
  1391. hal_srng = (struct hal_srng *)
  1392. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1393. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1394. hal_srng_to_hal_ring_handle(hal_srng),
  1395. &srng_params);
  1396. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr =
  1397. srng_params.ring_base_paddr;
  1398. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr =
  1399. srng_params.ring_base_vaddr;
  1400. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size =
  1401. (srng_params.num_entries * srng_params.entry_size) << 2;
  1402. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1403. (unsigned long)(hal_soc->dev_base_addr);
  1404. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr =
  1405. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1406. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1407. (unsigned int)addr_offset,
  1408. (unsigned int)dev_base_paddr,
  1409. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr),
  1410. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1411. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1412. srng_params.num_entries,
  1413. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1414. hal_srng = (struct hal_srng *)
  1415. pdev->rx_refill_buf_ring3.hal_srng;
  1416. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1417. hal_srng_to_hal_ring_handle(hal_srng),
  1418. &srng_params);
  1419. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr =
  1420. srng_params.ring_base_paddr;
  1421. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr =
  1422. srng_params.ring_base_vaddr;
  1423. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size =
  1424. (srng_params.num_entries * srng_params.entry_size) << 2;
  1425. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1426. hal_srng_to_hal_ring_handle(hal_srng));
  1427. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr =
  1428. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1429. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1430. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr),
  1431. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1432. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1433. srng_params.num_entries,
  1434. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1435. }
  1436. #else
  1437. static inline
  1438. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1439. { }
  1440. #endif
  1441. int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1442. struct dp_pdev *pdev)
  1443. {
  1444. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1445. struct hal_srng *hal_srng;
  1446. struct hal_srng_params srng_params;
  1447. qdf_dma_addr_t hp_addr;
  1448. unsigned long addr_offset, dev_base_paddr;
  1449. uint32_t ix0;
  1450. uint8_t ix0_map[8];
  1451. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1452. return QDF_STATUS_SUCCESS;
  1453. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL3 */
  1454. hal_srng = (struct hal_srng *)
  1455. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1456. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1457. hal_srng_to_hal_ring_handle(hal_srng),
  1458. &srng_params);
  1459. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1460. srng_params.ring_base_paddr;
  1461. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1462. srng_params.ring_base_vaddr;
  1463. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1464. (srng_params.num_entries * srng_params.entry_size) << 2;
  1465. /*
  1466. * For the register backed memory addresses, use the scn->mem_pa to
  1467. * calculate the physical address of the shadow registers
  1468. */
  1469. dev_base_paddr =
  1470. (unsigned long)
  1471. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1472. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  1473. (unsigned long)(hal_soc->dev_base_addr);
  1474. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr =
  1475. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1476. dp_info("IPA TCL_DATA Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1477. (unsigned int)addr_offset,
  1478. (unsigned int)dev_base_paddr,
  1479. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr),
  1480. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1481. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1482. srng_params.num_entries,
  1483. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1484. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW2_RELEASE */
  1485. hal_srng = (struct hal_srng *)
  1486. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1487. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1488. hal_srng_to_hal_ring_handle(hal_srng),
  1489. &srng_params);
  1490. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1491. srng_params.ring_base_paddr;
  1492. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1493. srng_params.ring_base_vaddr;
  1494. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1495. (srng_params.num_entries * srng_params.entry_size) << 2;
  1496. soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr =
  1497. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1498. hal_srng_to_hal_ring_handle(hal_srng));
  1499. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1500. (unsigned long)(hal_soc->dev_base_addr);
  1501. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr =
  1502. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1503. dp_info("IPA TX COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  1504. (unsigned int)addr_offset,
  1505. (unsigned int)dev_base_paddr,
  1506. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr),
  1507. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1508. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1509. srng_params.num_entries,
  1510. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1511. dp_ipa_tx_alt_ring_resource_setup(soc);
  1512. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1513. hal_srng = (struct hal_srng *)
  1514. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1515. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1516. hal_srng_to_hal_ring_handle(hal_srng),
  1517. &srng_params);
  1518. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1519. srng_params.ring_base_paddr;
  1520. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1521. srng_params.ring_base_vaddr;
  1522. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1523. (srng_params.num_entries * srng_params.entry_size) << 2;
  1524. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1525. (unsigned long)(hal_soc->dev_base_addr);
  1526. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr =
  1527. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1528. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1529. (unsigned int)addr_offset,
  1530. (unsigned int)dev_base_paddr,
  1531. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr),
  1532. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1533. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1534. srng_params.num_entries,
  1535. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1536. hal_srng = (struct hal_srng *)
  1537. pdev->rx_refill_buf_ring2.hal_srng;
  1538. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1539. hal_srng_to_hal_ring_handle(hal_srng),
  1540. &srng_params);
  1541. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1542. srng_params.ring_base_paddr;
  1543. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1544. srng_params.ring_base_vaddr;
  1545. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1546. (srng_params.num_entries * srng_params.entry_size) << 2;
  1547. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1548. hal_srng_to_hal_ring_handle(hal_srng));
  1549. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr =
  1550. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1551. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1552. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr),
  1553. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1554. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1555. srng_params.num_entries,
  1556. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1557. /*
  1558. * Set DEST_RING_MAPPING_4 to SW2 as default value for
  1559. * DESTINATION_RING_CTRL_IX_0.
  1560. */
  1561. ix0_map[0] = REO_REMAP_SW1;
  1562. ix0_map[1] = REO_REMAP_SW1;
  1563. ix0_map[2] = REO_REMAP_SW2;
  1564. ix0_map[3] = REO_REMAP_SW3;
  1565. ix0_map[4] = REO_REMAP_SW2;
  1566. ix0_map[5] = REO_REMAP_RELEASE;
  1567. ix0_map[6] = REO_REMAP_FW;
  1568. ix0_map[7] = REO_REMAP_FW;
  1569. dp_ipa_opt_dp_ixo_remap(ix0_map);
  1570. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1571. ix0_map);
  1572. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL, NULL, NULL);
  1573. dp_ipa_rx_alt_ring_resource_setup(soc, pdev);
  1574. return 0;
  1575. }
  1576. #ifdef IPA_WDI3_VLAN_SUPPORT
  1577. /**
  1578. * dp_ipa_rx_alt_ring_get_resource() - get IPA 2nd RX ring resources
  1579. * @pdev: data path pdev handle
  1580. *
  1581. * Return: Success if resourece is found
  1582. */
  1583. static QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1584. {
  1585. struct dp_soc *soc = pdev->soc;
  1586. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1587. if (!wlan_ipa_is_vlan_enabled())
  1588. return QDF_STATUS_SUCCESS;
  1589. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_alt_rdy_ring,
  1590. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1591. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1592. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1593. dp_ipa_get_shared_mem_info(
  1594. soc->osdev, &ipa_res->rx_alt_refill_ring,
  1595. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1596. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1597. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1598. if (!qdf_mem_get_dma_addr(soc->osdev,
  1599. &ipa_res->rx_alt_rdy_ring.mem_info) ||
  1600. !qdf_mem_get_dma_addr(soc->osdev,
  1601. &ipa_res->rx_alt_refill_ring.mem_info))
  1602. return QDF_STATUS_E_FAILURE;
  1603. return QDF_STATUS_SUCCESS;
  1604. }
  1605. #else
  1606. static inline QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1607. {
  1608. return QDF_STATUS_SUCCESS;
  1609. }
  1610. #endif
  1611. QDF_STATUS dp_ipa_get_resource(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1612. {
  1613. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1614. struct dp_pdev *pdev =
  1615. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1616. struct dp_ipa_resources *ipa_res;
  1617. if (!pdev) {
  1618. dp_err("Invalid instance");
  1619. return QDF_STATUS_E_FAILURE;
  1620. }
  1621. ipa_res = &pdev->ipa_resource;
  1622. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1623. return QDF_STATUS_SUCCESS;
  1624. ipa_res->tx_num_alloc_buffer =
  1625. (uint32_t)soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  1626. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_ring,
  1627. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1628. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1629. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1630. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_comp_ring,
  1631. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1632. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1633. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1634. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_rdy_ring,
  1635. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1636. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1637. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1638. dp_ipa_get_shared_mem_info(
  1639. soc->osdev, &ipa_res->rx_refill_ring,
  1640. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1641. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1642. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1643. if (!qdf_mem_get_dma_addr(soc->osdev, &ipa_res->tx_ring.mem_info) ||
  1644. !qdf_mem_get_dma_addr(soc->osdev,
  1645. &ipa_res->tx_comp_ring.mem_info) ||
  1646. !qdf_mem_get_dma_addr(soc->osdev, &ipa_res->rx_rdy_ring.mem_info) ||
  1647. !qdf_mem_get_dma_addr(soc->osdev,
  1648. &ipa_res->rx_refill_ring.mem_info))
  1649. return QDF_STATUS_E_FAILURE;
  1650. if (dp_ipa_is_alt_tx_required(soc)) {
  1651. if (dp_ipa_tx_alt_ring_get_resource(pdev))
  1652. return QDF_STATUS_E_FAILURE;
  1653. }
  1654. if (dp_ipa_rx_alt_ring_get_resource(pdev))
  1655. return QDF_STATUS_E_FAILURE;
  1656. return QDF_STATUS_SUCCESS;
  1657. }
  1658. #ifdef IPA_SET_RESET_TX_DB_PA
  1659. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res)
  1660. #else
  1661. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res) \
  1662. dp_ipa_set_tx_doorbell_paddr(soc, ipa_res)
  1663. #endif
  1664. #ifdef IPA_WDI3_VLAN_SUPPORT
  1665. /**
  1666. * dp_ipa_map_rx_alt_ring_doorbell_paddr() - Map 2nd rx ring doorbell paddr
  1667. * @pdev: data path pdev handle
  1668. *
  1669. * Return: none
  1670. */
  1671. static void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1672. {
  1673. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1674. uint32_t rx_ready_doorbell_dmaaddr;
  1675. struct dp_soc *soc = pdev->soc;
  1676. struct hal_srng *reo_srng = (struct hal_srng *)
  1677. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1678. int ret = 0;
  1679. if (!wlan_ipa_is_vlan_enabled())
  1680. return;
  1681. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1682. ret = pld_smmu_map(soc->osdev->dev,
  1683. ipa_res->rx_alt_ready_doorbell_paddr,
  1684. &rx_ready_doorbell_dmaaddr,
  1685. sizeof(uint32_t));
  1686. ipa_res->rx_alt_ready_doorbell_paddr =
  1687. rx_ready_doorbell_dmaaddr;
  1688. qdf_assert_always(!ret);
  1689. }
  1690. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1691. ipa_res->rx_alt_ready_doorbell_paddr);
  1692. }
  1693. /**
  1694. * dp_ipa_unmap_rx_alt_ring_doorbell_paddr() - Unmap 2nd rx ring doorbell paddr
  1695. * @pdev: data path pdev handle
  1696. *
  1697. * Return: none
  1698. */
  1699. static void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1700. {
  1701. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1702. struct dp_soc *soc = pdev->soc;
  1703. int ret = 0;
  1704. if (!wlan_ipa_is_vlan_enabled())
  1705. return;
  1706. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  1707. return;
  1708. ret = pld_smmu_unmap(soc->osdev->dev,
  1709. ipa_res->rx_alt_ready_doorbell_paddr,
  1710. sizeof(uint32_t));
  1711. qdf_assert_always(!ret);
  1712. }
  1713. #else
  1714. static inline void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1715. { }
  1716. static inline void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1717. { }
  1718. #endif
  1719. QDF_STATUS dp_ipa_set_doorbell_paddr(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1720. {
  1721. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1722. struct dp_pdev *pdev =
  1723. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1724. struct dp_ipa_resources *ipa_res;
  1725. struct hal_srng *reo_srng = (struct hal_srng *)
  1726. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1727. if (!pdev) {
  1728. dp_err("Invalid instance");
  1729. return QDF_STATUS_E_FAILURE;
  1730. }
  1731. ipa_res = &pdev->ipa_resource;
  1732. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1733. return QDF_STATUS_SUCCESS;
  1734. dp_ipa_map_ring_doorbell_paddr(pdev);
  1735. dp_ipa_map_rx_alt_ring_doorbell_paddr(pdev);
  1736. DP_IPA_SET_TX_DB_PADDR(soc, ipa_res);
  1737. /*
  1738. * For RX, REO module on Napier/Hastings does reordering on incoming
  1739. * Ethernet packets and writes one or more descriptors to REO2IPA Rx
  1740. * ring.It then updates the ring’s Write/Head ptr and rings a doorbell
  1741. * to IPA.
  1742. * Set the doorbell addr for the REO ring.
  1743. */
  1744. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1745. ipa_res->rx_ready_doorbell_paddr);
  1746. return QDF_STATUS_SUCCESS;
  1747. }
  1748. QDF_STATUS dp_ipa_iounmap_doorbell_vaddr(struct cdp_soc_t *soc_hdl,
  1749. uint8_t pdev_id)
  1750. {
  1751. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1752. struct dp_pdev *pdev =
  1753. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1754. struct dp_ipa_resources *ipa_res;
  1755. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1756. return QDF_STATUS_SUCCESS;
  1757. if (!pdev) {
  1758. dp_err("Invalid instance");
  1759. return QDF_STATUS_E_FAILURE;
  1760. }
  1761. ipa_res = &pdev->ipa_resource;
  1762. if (!ipa_res->is_db_ddr_mapped)
  1763. iounmap(ipa_res->tx_comp_doorbell_vaddr);
  1764. return QDF_STATUS_SUCCESS;
  1765. }
  1766. QDF_STATUS dp_ipa_op_response(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1767. uint8_t *op_msg)
  1768. {
  1769. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1770. struct dp_pdev *pdev =
  1771. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1772. if (!pdev) {
  1773. dp_err("Invalid instance");
  1774. return QDF_STATUS_E_FAILURE;
  1775. }
  1776. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1777. return QDF_STATUS_SUCCESS;
  1778. if (pdev->ipa_uc_op_cb) {
  1779. pdev->ipa_uc_op_cb(op_msg, pdev->usr_ctxt);
  1780. } else {
  1781. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1782. "%s: IPA callback function is not registered", __func__);
  1783. qdf_mem_free(op_msg);
  1784. return QDF_STATUS_E_FAILURE;
  1785. }
  1786. return QDF_STATUS_SUCCESS;
  1787. }
  1788. QDF_STATUS dp_ipa_register_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1789. ipa_uc_op_cb_type op_cb,
  1790. void *usr_ctxt)
  1791. {
  1792. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1793. struct dp_pdev *pdev =
  1794. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1795. if (!pdev) {
  1796. dp_err("Invalid instance");
  1797. return QDF_STATUS_E_FAILURE;
  1798. }
  1799. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1800. return QDF_STATUS_SUCCESS;
  1801. pdev->ipa_uc_op_cb = op_cb;
  1802. pdev->usr_ctxt = usr_ctxt;
  1803. return QDF_STATUS_SUCCESS;
  1804. }
  1805. void dp_ipa_deregister_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1806. {
  1807. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1808. struct dp_pdev *pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1809. if (!pdev) {
  1810. dp_err("Invalid instance");
  1811. return;
  1812. }
  1813. dp_debug("Deregister OP handler callback");
  1814. pdev->ipa_uc_op_cb = NULL;
  1815. pdev->usr_ctxt = NULL;
  1816. }
  1817. QDF_STATUS dp_ipa_get_stat(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1818. {
  1819. /* TBD */
  1820. return QDF_STATUS_SUCCESS;
  1821. }
  1822. qdf_nbuf_t dp_tx_send_ipa_data_frame(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1823. qdf_nbuf_t skb)
  1824. {
  1825. qdf_nbuf_t ret;
  1826. /* Terminate the (single-element) list of tx frames */
  1827. qdf_nbuf_set_next(skb, NULL);
  1828. ret = dp_tx_send(soc_hdl, vdev_id, skb);
  1829. if (ret) {
  1830. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1831. "%s: Failed to tx", __func__);
  1832. return ret;
  1833. }
  1834. return NULL;
  1835. }
  1836. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  1837. /**
  1838. * dp_ipa_is_target_ready() - check if target is ready or not
  1839. * @soc: datapath soc handle
  1840. *
  1841. * Return: true if target is ready
  1842. */
  1843. static inline
  1844. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1845. {
  1846. if (hif_get_target_status(soc->hif_handle) == TARGET_STATUS_RESET)
  1847. return false;
  1848. else
  1849. return true;
  1850. }
  1851. /**
  1852. * dp_ipa_update_txr_db_status() - Indicate transfer ring DB is SMMU mapped or not
  1853. * @dev: Pointer to device
  1854. * @txrx_smmu: WDI TX/RX configuration
  1855. *
  1856. * Return: None
  1857. */
  1858. static inline
  1859. void dp_ipa_update_txr_db_status(struct device *dev,
  1860. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1861. {
  1862. int pcie_slot = pld_get_pci_slot(dev);
  1863. if (pcie_slot)
  1864. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1865. else
  1866. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1867. }
  1868. /**
  1869. * dp_ipa_update_evt_db_status() - Indicate evt ring DB is SMMU mapped or not
  1870. * @dev: Pointer to device
  1871. * @txrx_smmu: WDI TX/RX configuration
  1872. *
  1873. * Return: None
  1874. */
  1875. static inline
  1876. void dp_ipa_update_evt_db_status(struct device *dev,
  1877. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1878. {
  1879. int pcie_slot = pld_get_pci_slot(dev);
  1880. if (pcie_slot)
  1881. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1882. else
  1883. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1884. }
  1885. #else
  1886. static inline
  1887. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1888. {
  1889. return true;
  1890. }
  1891. static inline
  1892. void dp_ipa_update_txr_db_status(struct device *dev,
  1893. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1894. {
  1895. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1896. }
  1897. static inline
  1898. void dp_ipa_update_evt_db_status(struct device *dev,
  1899. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1900. {
  1901. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1902. }
  1903. #endif
  1904. QDF_STATUS dp_ipa_enable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1905. {
  1906. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1907. struct dp_pdev *pdev =
  1908. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1909. uint32_t ix0;
  1910. uint32_t ix2;
  1911. uint8_t ix_map[8];
  1912. if (!pdev) {
  1913. dp_err("Invalid instance");
  1914. return QDF_STATUS_E_FAILURE;
  1915. }
  1916. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1917. return QDF_STATUS_SUCCESS;
  1918. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1919. return QDF_STATUS_E_AGAIN;
  1920. if (!dp_ipa_is_target_ready(soc))
  1921. return QDF_STATUS_E_AGAIN;
  1922. /* Call HAL API to remap REO rings to REO2IPA ring */
  1923. ix_map[0] = REO_REMAP_SW1;
  1924. ix_map[1] = REO_REMAP_SW4;
  1925. ix_map[2] = REO_REMAP_SW1;
  1926. if (wlan_ipa_is_vlan_enabled())
  1927. ix_map[3] = REO_REMAP_SW3;
  1928. else
  1929. ix_map[3] = REO_REMAP_SW4;
  1930. ix_map[4] = REO_REMAP_SW4;
  1931. ix_map[5] = REO_REMAP_RELEASE;
  1932. ix_map[6] = REO_REMAP_FW;
  1933. ix_map[7] = REO_REMAP_FW;
  1934. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1935. ix_map);
  1936. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1937. ix_map[0] = REO_REMAP_SW4;
  1938. ix_map[1] = REO_REMAP_SW4;
  1939. ix_map[2] = REO_REMAP_SW4;
  1940. ix_map[3] = REO_REMAP_SW4;
  1941. ix_map[4] = REO_REMAP_SW4;
  1942. ix_map[5] = REO_REMAP_SW4;
  1943. ix_map[6] = REO_REMAP_SW4;
  1944. ix_map[7] = REO_REMAP_SW4;
  1945. ix2 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX2,
  1946. ix_map);
  1947. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1948. &ix2, &ix2);
  1949. dp_ipa_reo_remap_history_add(ix0, ix2, ix2);
  1950. } else {
  1951. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1952. NULL, NULL);
  1953. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1954. }
  1955. return QDF_STATUS_SUCCESS;
  1956. }
  1957. QDF_STATUS dp_ipa_disable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1958. {
  1959. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1960. struct dp_pdev *pdev =
  1961. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1962. uint8_t ix0_map[8];
  1963. uint32_t ix0;
  1964. uint32_t ix1;
  1965. uint32_t ix2;
  1966. uint32_t ix3;
  1967. if (!pdev) {
  1968. dp_err("Invalid instance");
  1969. return QDF_STATUS_E_FAILURE;
  1970. }
  1971. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1972. return QDF_STATUS_SUCCESS;
  1973. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1974. return QDF_STATUS_E_AGAIN;
  1975. if (!dp_ipa_is_target_ready(soc))
  1976. return QDF_STATUS_E_AGAIN;
  1977. ix0_map[0] = REO_REMAP_SW1;
  1978. ix0_map[1] = REO_REMAP_SW1;
  1979. ix0_map[2] = REO_REMAP_SW2;
  1980. ix0_map[3] = REO_REMAP_SW3;
  1981. ix0_map[4] = REO_REMAP_SW2;
  1982. ix0_map[5] = REO_REMAP_RELEASE;
  1983. ix0_map[6] = REO_REMAP_FW;
  1984. ix0_map[7] = REO_REMAP_FW;
  1985. /* Call HAL API to remap REO rings to REO2IPA ring */
  1986. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1987. ix0_map);
  1988. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1989. dp_reo_remap_config(soc, &ix1, &ix2, &ix3);
  1990. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1991. &ix2, &ix3);
  1992. dp_ipa_reo_remap_history_add(ix0, ix2, ix3);
  1993. } else {
  1994. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1995. NULL, NULL);
  1996. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1997. }
  1998. return QDF_STATUS_SUCCESS;
  1999. }
  2000. /* This should be configurable per H/W configuration enable status */
  2001. #define L3_HEADER_PADDING 2
  2002. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  2003. defined(CONFIG_IPA_WDI_UNIFIED_API)
  2004. #if !defined(QCA_LL_TX_FLOW_CONTROL_V2) && !defined(QCA_IPA_LL_TX_FLOW_CONTROL)
  2005. static inline void dp_setup_mcc_sys_pipes(
  2006. qdf_ipa_sys_connect_params_t *sys_in,
  2007. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  2008. {
  2009. int i = 0;
  2010. /* Setup MCC sys pipe */
  2011. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) =
  2012. DP_IPA_MAX_IFACE;
  2013. for (i = 0; i < DP_IPA_MAX_IFACE; i++)
  2014. memcpy(&QDF_IPA_WDI_CONN_IN_PARAMS_SYS_IN(pipe_in)[i],
  2015. &sys_in[i], sizeof(qdf_ipa_sys_connect_params_t));
  2016. }
  2017. #else
  2018. static inline void dp_setup_mcc_sys_pipes(
  2019. qdf_ipa_sys_connect_params_t *sys_in,
  2020. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  2021. {
  2022. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) = 0;
  2023. }
  2024. #endif
  2025. static void dp_ipa_wdi_tx_params(struct dp_soc *soc,
  2026. struct dp_ipa_resources *ipa_res,
  2027. qdf_ipa_wdi_pipe_setup_info_t *tx,
  2028. bool over_gsi)
  2029. {
  2030. if (over_gsi)
  2031. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS;
  2032. else
  2033. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2034. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2035. qdf_mem_get_dma_addr(soc->osdev,
  2036. &ipa_res->tx_comp_ring.mem_info);
  2037. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2038. qdf_mem_get_dma_size(soc->osdev,
  2039. &ipa_res->tx_comp_ring.mem_info);
  2040. /* WBM Tail Pointer Address */
  2041. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2042. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2043. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  2044. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2045. qdf_mem_get_dma_addr(soc->osdev,
  2046. &ipa_res->tx_ring.mem_info);
  2047. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  2048. qdf_mem_get_dma_size(soc->osdev,
  2049. &ipa_res->tx_ring.mem_info);
  2050. /* TCL Head Pointer Address */
  2051. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2052. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2053. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  2054. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2055. ipa_res->tx_num_alloc_buffer;
  2056. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2057. dp_ipa_setup_tx_params_bank_id(soc, tx);
  2058. /* Set Pmac ID, extract pmac_id from pdev_id 0 for TX ring */
  2059. dp_ipa_setup_tx_params_pmac_id(soc, tx);
  2060. }
  2061. static void dp_ipa_wdi_rx_params(struct dp_soc *soc,
  2062. struct dp_ipa_resources *ipa_res,
  2063. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2064. bool over_gsi)
  2065. {
  2066. if (over_gsi)
  2067. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2068. IPA_CLIENT_WLAN2_PROD;
  2069. else
  2070. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2071. IPA_CLIENT_WLAN1_PROD;
  2072. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2073. qdf_mem_get_dma_addr(soc->osdev,
  2074. &ipa_res->rx_rdy_ring.mem_info);
  2075. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2076. qdf_mem_get_dma_size(soc->osdev,
  2077. &ipa_res->rx_rdy_ring.mem_info);
  2078. /* REO Tail Pointer Address */
  2079. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2080. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2081. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2082. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2083. qdf_mem_get_dma_addr(soc->osdev,
  2084. &ipa_res->rx_refill_ring.mem_info);
  2085. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2086. qdf_mem_get_dma_size(soc->osdev,
  2087. &ipa_res->rx_refill_ring.mem_info);
  2088. /* FW Head Pointer Address */
  2089. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2090. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2091. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2092. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2093. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2094. }
  2095. static void
  2096. dp_ipa_wdi_tx_smmu_params(struct dp_soc *soc,
  2097. struct dp_ipa_resources *ipa_res,
  2098. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu,
  2099. bool over_gsi,
  2100. qdf_ipa_wdi_hdl_t hdl)
  2101. {
  2102. if (over_gsi) {
  2103. if (hdl == DP_IPA_HDL_FIRST)
  2104. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2105. IPA_CLIENT_WLAN2_CONS;
  2106. else if (hdl == DP_IPA_HDL_SECOND)
  2107. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2108. IPA_CLIENT_WLAN4_CONS;
  2109. else if (hdl == DP_IPA_HDL_THIRD)
  2110. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2111. IPA_CLIENT_WLAN1_CONS;
  2112. } else {
  2113. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2114. IPA_CLIENT_WLAN1_CONS;
  2115. }
  2116. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  2117. &ipa_res->tx_comp_ring.sgtable,
  2118. sizeof(sgtable_t));
  2119. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  2120. qdf_mem_get_dma_size(soc->osdev,
  2121. &ipa_res->tx_comp_ring.mem_info);
  2122. /* WBM Tail Pointer Address */
  2123. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  2124. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2125. dp_ipa_update_txr_db_status(soc->osdev->dev, tx_smmu);
  2126. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  2127. &ipa_res->tx_ring.sgtable,
  2128. sizeof(sgtable_t));
  2129. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  2130. qdf_mem_get_dma_size(soc->osdev,
  2131. &ipa_res->tx_ring.mem_info);
  2132. /* TCL Head Pointer Address */
  2133. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  2134. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2135. dp_ipa_update_evt_db_status(soc->osdev->dev, tx_smmu);
  2136. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  2137. ipa_res->tx_num_alloc_buffer;
  2138. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  2139. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  2140. /* Set Pmac ID, extract pmac_id from first pdev for TX ring */
  2141. dp_ipa_setup_tx_smmu_params_pmac_id(soc, tx_smmu);
  2142. }
  2143. static void
  2144. dp_ipa_wdi_rx_smmu_params(struct dp_soc *soc,
  2145. struct dp_ipa_resources *ipa_res,
  2146. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2147. bool over_gsi,
  2148. qdf_ipa_wdi_hdl_t hdl)
  2149. {
  2150. if (over_gsi) {
  2151. if (hdl == DP_IPA_HDL_FIRST)
  2152. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2153. IPA_CLIENT_WLAN2_PROD;
  2154. else if (hdl == DP_IPA_HDL_SECOND)
  2155. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2156. IPA_CLIENT_WLAN3_PROD;
  2157. else if (hdl == DP_IPA_HDL_THIRD)
  2158. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2159. IPA_CLIENT_WLAN1_PROD;
  2160. } else {
  2161. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2162. IPA_CLIENT_WLAN1_PROD;
  2163. }
  2164. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2165. &ipa_res->rx_rdy_ring.sgtable,
  2166. sizeof(sgtable_t));
  2167. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2168. qdf_mem_get_dma_size(soc->osdev,
  2169. &ipa_res->rx_rdy_ring.mem_info);
  2170. /* REO Tail Pointer Address */
  2171. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2172. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2173. dp_ipa_update_txr_db_status(soc->osdev->dev, rx_smmu);
  2174. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2175. &ipa_res->rx_refill_ring.sgtable,
  2176. sizeof(sgtable_t));
  2177. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2178. qdf_mem_get_dma_size(soc->osdev,
  2179. &ipa_res->rx_refill_ring.mem_info);
  2180. /* FW Head Pointer Address */
  2181. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2182. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2183. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2184. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2185. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2186. }
  2187. #ifdef IPA_WDI3_VLAN_SUPPORT
  2188. /**
  2189. * dp_ipa_wdi_rx_alt_pipe_smmu_params() - Setup 2nd rx pipe smmu params
  2190. * @soc: data path soc handle
  2191. * @ipa_res: ipa resource pointer
  2192. * @rx_smmu: smmu pipe info handle
  2193. * @over_gsi: flag for IPA offload over gsi
  2194. * @hdl: ipa registered handle
  2195. *
  2196. * Return: none
  2197. */
  2198. static void
  2199. dp_ipa_wdi_rx_alt_pipe_smmu_params(struct dp_soc *soc,
  2200. struct dp_ipa_resources *ipa_res,
  2201. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2202. bool over_gsi,
  2203. qdf_ipa_wdi_hdl_t hdl)
  2204. {
  2205. if (!wlan_ipa_is_vlan_enabled())
  2206. return;
  2207. if (over_gsi) {
  2208. if (hdl == DP_IPA_HDL_FIRST)
  2209. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2210. IPA_CLIENT_WLAN2_PROD1;
  2211. else if (hdl == DP_IPA_HDL_SECOND)
  2212. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2213. IPA_CLIENT_WLAN3_PROD1;
  2214. else if (hdl == DP_IPA_HDL_THIRD)
  2215. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx_smmu) =
  2216. IPA_CLIENT_WLAN1_PROD1;
  2217. } else {
  2218. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2219. IPA_CLIENT_WLAN1_PROD;
  2220. }
  2221. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2222. &ipa_res->rx_alt_rdy_ring.sgtable,
  2223. sizeof(sgtable_t));
  2224. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2225. qdf_mem_get_dma_size(soc->osdev,
  2226. &ipa_res->rx_alt_rdy_ring.mem_info);
  2227. /* REO Tail Pointer Address */
  2228. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2229. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2230. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  2231. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2232. &ipa_res->rx_alt_refill_ring.sgtable,
  2233. sizeof(sgtable_t));
  2234. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2235. qdf_mem_get_dma_size(soc->osdev,
  2236. &ipa_res->rx_alt_refill_ring.mem_info);
  2237. /* FW Head Pointer Address */
  2238. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2239. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2240. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2241. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2242. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2243. }
  2244. /**
  2245. * dp_ipa_wdi_rx_alt_pipe_params() - Setup 2nd rx pipe params
  2246. * @soc: data path soc handle
  2247. * @ipa_res: ipa resource pointer
  2248. * @rx: pipe info handle
  2249. * @over_gsi: flag for IPA offload over gsi
  2250. * @hdl: ipa registered handle
  2251. *
  2252. * Return: none
  2253. */
  2254. static void dp_ipa_wdi_rx_alt_pipe_params(struct dp_soc *soc,
  2255. struct dp_ipa_resources *ipa_res,
  2256. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2257. bool over_gsi,
  2258. qdf_ipa_wdi_hdl_t hdl)
  2259. {
  2260. if (!wlan_ipa_is_vlan_enabled())
  2261. return;
  2262. if (over_gsi) {
  2263. if (hdl == DP_IPA_HDL_FIRST)
  2264. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2265. IPA_CLIENT_WLAN2_PROD1;
  2266. else if (hdl == DP_IPA_HDL_SECOND)
  2267. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2268. IPA_CLIENT_WLAN3_PROD1;
  2269. else if (hdl == DP_IPA_HDL_THIRD)
  2270. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2271. IPA_CLIENT_WLAN1_PROD1;
  2272. } else {
  2273. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2274. IPA_CLIENT_WLAN1_PROD;
  2275. }
  2276. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2277. qdf_mem_get_dma_addr(soc->osdev,
  2278. &ipa_res->rx_alt_rdy_ring.mem_info);
  2279. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2280. qdf_mem_get_dma_size(soc->osdev,
  2281. &ipa_res->rx_alt_rdy_ring.mem_info);
  2282. /* REO Tail Pointer Address */
  2283. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2284. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2285. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2286. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2287. qdf_mem_get_dma_addr(soc->osdev,
  2288. &ipa_res->rx_alt_refill_ring.mem_info);
  2289. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2290. qdf_mem_get_dma_size(soc->osdev,
  2291. &ipa_res->rx_alt_refill_ring.mem_info);
  2292. /* FW Head Pointer Address */
  2293. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2294. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2295. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2296. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2297. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2298. }
  2299. /**
  2300. * dp_ipa_setup_rx_alt_pipe() - Setup 2nd rx pipe for IPA offload
  2301. * @soc: data path soc handle
  2302. * @res: ipa resource pointer
  2303. * @in: pipe in handle
  2304. * @over_gsi: flag for IPA offload over gsi
  2305. * @hdl: ipa registered handle
  2306. *
  2307. * Return: none
  2308. */
  2309. static void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2310. struct dp_ipa_resources *res,
  2311. qdf_ipa_wdi_conn_in_params_t *in,
  2312. bool over_gsi,
  2313. qdf_ipa_wdi_hdl_t hdl)
  2314. {
  2315. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2316. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2317. qdf_ipa_ep_cfg_t *rx_cfg;
  2318. if (!wlan_ipa_is_vlan_enabled())
  2319. return;
  2320. QDF_IPA_WDI_CONN_IN_PARAMS_IS_RX1_USED(in) = true;
  2321. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  2322. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT_SMMU(in);
  2323. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2324. dp_ipa_wdi_rx_alt_pipe_smmu_params(soc, res, rx_smmu,
  2325. over_gsi, hdl);
  2326. } else {
  2327. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT(in);
  2328. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx);
  2329. dp_ipa_wdi_rx_alt_pipe_params(soc, res, rx, over_gsi, hdl);
  2330. }
  2331. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2332. /* Update with wds len(96) + 4 if wds support is enabled */
  2333. if (ucfg_ipa_is_wds_enabled())
  2334. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST_VLAN;
  2335. else
  2336. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2337. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2338. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2339. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2340. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2341. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2342. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2343. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2344. }
  2345. /**
  2346. * dp_ipa_set_rx_alt_pipe_db() - Setup 2nd rx pipe doorbell
  2347. * @res: ipa resource pointer
  2348. * @out: pipe out handle
  2349. *
  2350. * Return: none
  2351. */
  2352. static void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2353. qdf_ipa_wdi_conn_out_params_t *out)
  2354. {
  2355. if (!wlan_ipa_is_vlan_enabled())
  2356. return;
  2357. res->rx_alt_ready_doorbell_paddr =
  2358. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_ALT_UC_DB_PA(out);
  2359. dp_debug("Setting DB 0x%x for RX alt pipe",
  2360. res->rx_alt_ready_doorbell_paddr);
  2361. }
  2362. #else
  2363. static inline
  2364. void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2365. struct dp_ipa_resources *res,
  2366. qdf_ipa_wdi_conn_in_params_t *in,
  2367. bool over_gsi,
  2368. qdf_ipa_wdi_hdl_t hdl)
  2369. { }
  2370. static inline
  2371. void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2372. qdf_ipa_wdi_conn_out_params_t *out)
  2373. { }
  2374. #endif
  2375. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2376. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2377. void *ipa_wdi_meter_notifier_cb,
  2378. uint32_t ipa_desc_size, void *ipa_priv,
  2379. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2380. uint32_t *rx_pipe_handle, bool is_smmu_enabled,
  2381. qdf_ipa_sys_connect_params_t *sys_in, bool over_gsi,
  2382. qdf_ipa_wdi_hdl_t hdl, qdf_ipa_wdi_hdl_t id,
  2383. void *ipa_ast_notify_cb)
  2384. {
  2385. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2386. struct dp_pdev *pdev =
  2387. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2388. struct dp_ipa_resources *ipa_res;
  2389. qdf_ipa_ep_cfg_t *tx_cfg;
  2390. qdf_ipa_ep_cfg_t *rx_cfg;
  2391. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  2392. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2393. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu;
  2394. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2395. qdf_ipa_wdi_conn_in_params_t *pipe_in = NULL;
  2396. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2397. int ret;
  2398. if (!pdev) {
  2399. dp_err("Invalid instance");
  2400. return QDF_STATUS_E_FAILURE;
  2401. }
  2402. ipa_res = &pdev->ipa_resource;
  2403. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2404. return QDF_STATUS_SUCCESS;
  2405. pipe_in = qdf_mem_malloc(sizeof(*pipe_in));
  2406. if (!pipe_in)
  2407. return QDF_STATUS_E_NOMEM;
  2408. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2409. if (is_smmu_enabled)
  2410. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = true;
  2411. else
  2412. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = false;
  2413. dp_setup_mcc_sys_pipes(sys_in, pipe_in);
  2414. /* TX PIPE */
  2415. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2416. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_SMMU(pipe_in);
  2417. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  2418. } else {
  2419. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(pipe_in);
  2420. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(tx);
  2421. }
  2422. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  2423. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2424. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  2425. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  2426. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  2427. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  2428. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  2429. /*
  2430. * Transfer Ring: WBM Ring
  2431. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2432. * Event Ring: TCL ring
  2433. * Event Ring Doorbell PA: TCL Head Pointer Address
  2434. */
  2435. if (is_smmu_enabled)
  2436. dp_ipa_wdi_tx_smmu_params(soc, ipa_res, tx_smmu, over_gsi, id);
  2437. else
  2438. dp_ipa_wdi_tx_params(soc, ipa_res, tx, over_gsi);
  2439. if (dp_ipa_is_alt_tx_required(soc))
  2440. dp_ipa_setup_tx_alt_pipe(soc, ipa_res, pipe_in);
  2441. /* RX PIPE */
  2442. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2443. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_SMMU(pipe_in);
  2444. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2445. } else {
  2446. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(pipe_in);
  2447. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(rx);
  2448. }
  2449. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2450. if (ucfg_ipa_is_wds_enabled())
  2451. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST;
  2452. else
  2453. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2454. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2455. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2456. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2457. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2458. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2459. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2460. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2461. /*
  2462. * Transfer Ring: REO Ring
  2463. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2464. * Event Ring: FW ring
  2465. * Event Ring Doorbell PA: FW Head Pointer Address
  2466. */
  2467. if (is_smmu_enabled)
  2468. dp_ipa_wdi_rx_smmu_params(soc, ipa_res, rx_smmu, over_gsi, id);
  2469. else
  2470. dp_ipa_wdi_rx_params(soc, ipa_res, rx, over_gsi);
  2471. /* setup 2nd rx pipe */
  2472. dp_ipa_setup_rx_alt_pipe(soc, ipa_res, pipe_in, over_gsi, id);
  2473. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(pipe_in) = ipa_w2i_cb;
  2474. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(pipe_in) = ipa_priv;
  2475. QDF_IPA_WDI_CONN_IN_PARAMS_HANDLE(pipe_in) = hdl;
  2476. dp_ipa_ast_notify_cb(pipe_in, ipa_ast_notify_cb);
  2477. /* Connect WDI IPA PIPEs */
  2478. ret = qdf_ipa_wdi_conn_pipes(pipe_in, &pipe_out);
  2479. if (ret) {
  2480. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2481. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2482. __func__, ret);
  2483. qdf_mem_free(pipe_in);
  2484. return QDF_STATUS_E_FAILURE;
  2485. }
  2486. /* IPA uC Doorbell registers */
  2487. dp_info("Tx DB PA=0x%x, Rx DB PA=0x%x",
  2488. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2489. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2490. dp_ipa_set_pipe_db(ipa_res, &pipe_out);
  2491. dp_ipa_set_rx_alt_pipe_db(ipa_res, &pipe_out);
  2492. ipa_res->is_db_ddr_mapped =
  2493. QDF_IPA_WDI_CONN_OUT_PARAMS_IS_DB_DDR_MAPPED(&pipe_out);
  2494. soc->ipa_first_tx_db_access = true;
  2495. qdf_mem_free(pipe_in);
  2496. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2497. soc->ipa_rx_buf_map_lock_initialized = true;
  2498. return QDF_STATUS_SUCCESS;
  2499. }
  2500. #ifdef IPA_WDI3_VLAN_SUPPORT
  2501. /**
  2502. * dp_ipa_set_rx1_used() - Set rx1 used flag for 2nd rx offload ring
  2503. * @in: pipe in handle
  2504. *
  2505. * Return: none
  2506. */
  2507. static inline
  2508. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2509. {
  2510. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_RX1_USED(in) = true;
  2511. }
  2512. /**
  2513. * dp_ipa_set_v4_vlan_hdr() - Set v4 vlan hdr
  2514. * @in: pipe in handle
  2515. * @hdr: pointer to hdr
  2516. *
  2517. * Return: none
  2518. */
  2519. static inline
  2520. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2521. qdf_ipa_wdi_hdr_info_t *hdr)
  2522. {
  2523. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v4_VLAN]),
  2524. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2525. }
  2526. /**
  2527. * dp_ipa_set_v6_vlan_hdr() - Set v6 vlan hdr
  2528. * @in: pipe in handle
  2529. * @hdr: pointer to hdr
  2530. *
  2531. * Return: none
  2532. */
  2533. static inline
  2534. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2535. qdf_ipa_wdi_hdr_info_t *hdr)
  2536. {
  2537. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v6_VLAN]),
  2538. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2539. }
  2540. #else
  2541. static inline
  2542. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2543. { }
  2544. static inline
  2545. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2546. qdf_ipa_wdi_hdr_info_t *hdr)
  2547. { }
  2548. static inline
  2549. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2550. qdf_ipa_wdi_hdr_info_t *hdr)
  2551. { }
  2552. #endif
  2553. #ifdef IPA_WDS_EASYMESH_FEATURE
  2554. /**
  2555. * dp_ipa_set_wdi_hdr_type() - Set wdi hdr type for IPA
  2556. * @hdr_info: Header info
  2557. *
  2558. * Return: None
  2559. */
  2560. static inline void
  2561. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2562. {
  2563. if (ucfg_ipa_is_wds_enabled())
  2564. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2565. IPA_HDR_L2_ETHERNET_II_AST;
  2566. else
  2567. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2568. IPA_HDR_L2_ETHERNET_II;
  2569. }
  2570. #else
  2571. static inline void
  2572. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2573. {
  2574. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2575. }
  2576. #endif
  2577. #ifdef IPA_WDI3_VLAN_SUPPORT
  2578. /**
  2579. * dp_ipa_set_wdi_vlan_hdr_type() - Set wdi vlan hdr type for IPA
  2580. * @hdr_info: Header info
  2581. *
  2582. * Return: None
  2583. */
  2584. static inline void
  2585. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2586. {
  2587. if (ucfg_ipa_is_wds_enabled())
  2588. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2589. IPA_HDR_L2_802_1Q_AST;
  2590. else
  2591. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2592. IPA_HDR_L2_802_1Q;
  2593. }
  2594. #else
  2595. static inline void
  2596. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2597. { }
  2598. #endif
  2599. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2600. qdf_ipa_client_type_t prod_client,
  2601. qdf_ipa_client_type_t cons_client,
  2602. uint8_t session_id, bool is_ipv6_enabled,
  2603. qdf_ipa_wdi_hdl_t hdl)
  2604. {
  2605. qdf_ipa_wdi_reg_intf_in_params_t in;
  2606. qdf_ipa_wdi_hdr_info_t hdr_info;
  2607. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2608. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2609. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr;
  2610. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr_v6;
  2611. int ret = -EINVAL;
  2612. qdf_mem_zero(&in, sizeof(qdf_ipa_wdi_reg_intf_in_params_t));
  2613. /* Need to reset the values to 0 as all the fields are not
  2614. * updated in the Header, Unused fields will be set to 0.
  2615. */
  2616. qdf_mem_zero(&uc_tx_vlan_hdr, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2617. qdf_mem_zero(&uc_tx_vlan_hdr_v6, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2618. dp_debug("Add Partial hdr: %s, "QDF_MAC_ADDR_FMT, ifname,
  2619. QDF_MAC_ADDR_REF(mac_addr));
  2620. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2621. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2622. /* IPV4 header */
  2623. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2624. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2625. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2626. dp_ipa_set_wdi_hdr_type(&hdr_info);
  2627. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2628. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2629. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2630. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2631. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2632. QDF_IPA_WDI_REG_INTF_IN_PARAMS_ALT_DST_PIPE(&in) = cons_client;
  2633. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2634. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = WLAN_IPA_META_DATA_MASK;
  2635. QDF_IPA_WDI_REG_INTF_IN_PARAMS_HANDLE(&in) = hdl;
  2636. dp_ipa_setup_iface_session_id(&in, session_id);
  2637. dp_debug("registering for session_id: %u", session_id);
  2638. /* IPV6 header */
  2639. if (is_ipv6_enabled) {
  2640. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2641. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2642. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2643. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2644. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2645. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2646. }
  2647. if (wlan_ipa_is_vlan_enabled()) {
  2648. /* Add vlan specific headers if vlan supporti is enabled */
  2649. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2650. dp_ipa_set_rx1_used(&in);
  2651. qdf_ether_addr_copy(uc_tx_vlan_hdr.eth.h_source, mac_addr);
  2652. /* IPV4 Vlan header */
  2653. uc_tx_vlan_hdr.eth.h_vlan_proto = qdf_htons(ETH_P_8021Q);
  2654. uc_tx_vlan_hdr.eth.h_vlan_encapsulated_proto = qdf_htons(ETH_P_IP);
  2655. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2656. (uint8_t *)&uc_tx_vlan_hdr;
  2657. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) =
  2658. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2659. dp_ipa_set_wdi_vlan_hdr_type(&hdr_info);
  2660. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2661. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2662. dp_ipa_set_v4_vlan_hdr(&in, &hdr_info);
  2663. /* IPV6 Vlan header */
  2664. if (is_ipv6_enabled) {
  2665. qdf_mem_copy(&uc_tx_vlan_hdr_v6, &uc_tx_vlan_hdr,
  2666. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN);
  2667. uc_tx_vlan_hdr_v6.eth.h_vlan_proto =
  2668. qdf_htons(ETH_P_8021Q);
  2669. uc_tx_vlan_hdr_v6.eth.h_vlan_encapsulated_proto =
  2670. qdf_htons(ETH_P_IPV6);
  2671. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2672. (uint8_t *)&uc_tx_vlan_hdr_v6;
  2673. dp_ipa_set_v6_vlan_hdr(&in, &hdr_info);
  2674. }
  2675. }
  2676. ret = qdf_ipa_wdi_reg_intf(&in);
  2677. if (ret) {
  2678. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2679. "%s: ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2680. __func__, ret);
  2681. return QDF_STATUS_E_FAILURE;
  2682. }
  2683. return QDF_STATUS_SUCCESS;
  2684. }
  2685. #else /* !CONFIG_IPA_WDI_UNIFIED_API */
  2686. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2687. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2688. void *ipa_wdi_meter_notifier_cb,
  2689. uint32_t ipa_desc_size, void *ipa_priv,
  2690. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2691. uint32_t *rx_pipe_handle)
  2692. {
  2693. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2694. struct dp_pdev *pdev =
  2695. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2696. struct dp_ipa_resources *ipa_res;
  2697. qdf_ipa_wdi_pipe_setup_info_t *tx;
  2698. qdf_ipa_wdi_pipe_setup_info_t *rx;
  2699. qdf_ipa_wdi_conn_in_params_t pipe_in;
  2700. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2701. struct tcl_data_cmd *tcl_desc_ptr;
  2702. uint8_t *desc_addr;
  2703. uint32_t desc_size;
  2704. int ret;
  2705. if (!pdev) {
  2706. dp_err("Invalid instance");
  2707. return QDF_STATUS_E_FAILURE;
  2708. }
  2709. ipa_res = &pdev->ipa_resource;
  2710. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2711. return QDF_STATUS_SUCCESS;
  2712. qdf_mem_zero(&tx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2713. qdf_mem_zero(&rx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2714. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  2715. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2716. /* TX PIPE */
  2717. /*
  2718. * Transfer Ring: WBM Ring
  2719. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2720. * Event Ring: TCL ring
  2721. * Event Ring Doorbell PA: TCL Head Pointer Address
  2722. */
  2723. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  2724. QDF_IPA_WDI_SETUP_INFO_NAT_EN(tx) = IPA_BYPASS_NAT;
  2725. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(tx) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2726. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(tx) = 0;
  2727. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(tx) = 0;
  2728. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(tx) = 0;
  2729. QDF_IPA_WDI_SETUP_INFO_MODE(tx) = IPA_BASIC;
  2730. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(tx) = true;
  2731. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2732. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2733. ipa_res->tx_comp_ring_base_paddr;
  2734. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2735. ipa_res->tx_comp_ring_size;
  2736. /* WBM Tail Pointer Address */
  2737. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2738. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2739. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2740. ipa_res->tx_ring_base_paddr;
  2741. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) = ipa_res->tx_ring_size;
  2742. /* TCL Head Pointer Address */
  2743. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2744. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2745. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2746. ipa_res->tx_num_alloc_buffer;
  2747. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2748. /* Preprogram TCL descriptor */
  2749. desc_addr =
  2750. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  2751. desc_size = sizeof(struct tcl_data_cmd);
  2752. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  2753. tcl_desc_ptr = (struct tcl_data_cmd *)
  2754. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  2755. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  2756. HAL_RX_BUF_RBM_SW2_BM;
  2757. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  2758. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  2759. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  2760. /* RX PIPE */
  2761. /*
  2762. * Transfer Ring: REO Ring
  2763. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2764. * Event Ring: FW ring
  2765. * Event Ring Doorbell PA: FW Head Pointer Address
  2766. */
  2767. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  2768. QDF_IPA_WDI_SETUP_INFO_NAT_EN(rx) = IPA_BYPASS_NAT;
  2769. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(rx) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2770. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(rx) = 0;
  2771. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(rx) = 0;
  2772. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(rx) = 0;
  2773. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_METADATA_VALID(rx) = 0;
  2774. QDF_IPA_WDI_SETUP_INFO_HDR_METADATA_REG_VALID(rx) = 1;
  2775. QDF_IPA_WDI_SETUP_INFO_MODE(rx) = IPA_BASIC;
  2776. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(rx) = true;
  2777. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) = IPA_CLIENT_WLAN1_PROD;
  2778. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2779. ipa_res->rx_rdy_ring_base_paddr;
  2780. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2781. ipa_res->rx_rdy_ring_size;
  2782. /* REO Tail Pointer Address */
  2783. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2784. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2785. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2786. ipa_res->rx_refill_ring_base_paddr;
  2787. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2788. ipa_res->rx_refill_ring_size;
  2789. /* FW Head Pointer Address */
  2790. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2791. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2792. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) = soc->rx_pkt_tlv_size +
  2793. L3_HEADER_PADDING;
  2794. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  2795. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  2796. /* Connect WDI IPA PIPE */
  2797. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  2798. if (ret) {
  2799. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2800. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2801. __func__, ret);
  2802. return QDF_STATUS_E_FAILURE;
  2803. }
  2804. /* IPA uC Doorbell registers */
  2805. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2806. "%s: Tx DB PA=0x%x, Rx DB PA=0x%x",
  2807. __func__,
  2808. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2809. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2810. ipa_res->tx_comp_doorbell_paddr =
  2811. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  2812. ipa_res->tx_comp_doorbell_vaddr =
  2813. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_VA(&pipe_out);
  2814. ipa_res->rx_ready_doorbell_paddr =
  2815. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  2816. soc->ipa_first_tx_db_access = true;
  2817. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2818. soc->ipa_rx_buf_map_lock_initialized = true;
  2819. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2820. "%s: Tx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2821. __func__,
  2822. "transfer_ring_base_pa",
  2823. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx),
  2824. "transfer_ring_size",
  2825. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx),
  2826. "transfer_ring_doorbell_pa",
  2827. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx),
  2828. "event_ring_base_pa",
  2829. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx),
  2830. "event_ring_size",
  2831. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx),
  2832. "event_ring_doorbell_pa",
  2833. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx),
  2834. "num_pkt_buffers",
  2835. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx),
  2836. "tx_comp_doorbell_paddr",
  2837. (void *)ipa_res->tx_comp_doorbell_paddr);
  2838. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2839. "%s: Rx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2840. __func__,
  2841. "transfer_ring_base_pa",
  2842. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx),
  2843. "transfer_ring_size",
  2844. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx),
  2845. "transfer_ring_doorbell_pa",
  2846. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx),
  2847. "event_ring_base_pa",
  2848. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx),
  2849. "event_ring_size",
  2850. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx),
  2851. "event_ring_doorbell_pa",
  2852. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx),
  2853. "num_pkt_buffers",
  2854. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(rx),
  2855. "tx_comp_doorbell_paddr",
  2856. (void *)ipa_res->rx_ready_doorbell_paddr);
  2857. return QDF_STATUS_SUCCESS;
  2858. }
  2859. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2860. qdf_ipa_client_type_t prod_client,
  2861. qdf_ipa_client_type_t cons_client,
  2862. uint8_t session_id, bool is_ipv6_enabled,
  2863. qdf_ipa_wdi_hdl_t hdl)
  2864. {
  2865. qdf_ipa_wdi_reg_intf_in_params_t in;
  2866. qdf_ipa_wdi_hdr_info_t hdr_info;
  2867. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2868. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2869. int ret = -EINVAL;
  2870. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2871. "%s: Add Partial hdr: %s, "QDF_MAC_ADDR_FMT,
  2872. __func__, ifname, QDF_MAC_ADDR_REF(mac_addr));
  2873. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2874. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2875. /* IPV4 header */
  2876. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2877. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2878. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2879. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2880. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2881. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2882. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2883. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2884. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2885. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2886. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  2887. htonl(session_id << 16);
  2888. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  2889. /* IPV6 header */
  2890. if (is_ipv6_enabled) {
  2891. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2892. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2893. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2894. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2895. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2896. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2897. }
  2898. ret = qdf_ipa_wdi_reg_intf(&in);
  2899. if (ret) {
  2900. dp_err("ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2901. ret);
  2902. return QDF_STATUS_E_FAILURE;
  2903. }
  2904. return QDF_STATUS_SUCCESS;
  2905. }
  2906. #endif /* CONFIG_IPA_WDI_UNIFIED_API */
  2907. QDF_STATUS dp_ipa_cleanup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2908. uint32_t tx_pipe_handle, uint32_t rx_pipe_handle,
  2909. qdf_ipa_wdi_hdl_t hdl)
  2910. {
  2911. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2912. QDF_STATUS status = QDF_STATUS_SUCCESS;
  2913. struct dp_pdev *pdev;
  2914. int ret;
  2915. ret = qdf_ipa_wdi_disconn_pipes(hdl);
  2916. if (ret) {
  2917. dp_err("ipa_wdi_disconn_pipes: IPA pipe cleanup failed: ret=%d",
  2918. ret);
  2919. status = QDF_STATUS_E_FAILURE;
  2920. }
  2921. if (soc->ipa_rx_buf_map_lock_initialized) {
  2922. qdf_spinlock_destroy(&soc->ipa_rx_buf_map_lock);
  2923. soc->ipa_rx_buf_map_lock_initialized = false;
  2924. }
  2925. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2926. if (qdf_unlikely(!pdev)) {
  2927. dp_err_rl("Invalid pdev for pdev_id %d", pdev_id);
  2928. status = QDF_STATUS_E_FAILURE;
  2929. goto exit;
  2930. }
  2931. dp_ipa_unmap_ring_doorbell_paddr(pdev);
  2932. dp_ipa_unmap_rx_alt_ring_doorbell_paddr(pdev);
  2933. exit:
  2934. return status;
  2935. }
  2936. QDF_STATUS dp_ipa_cleanup_iface(char *ifname, bool is_ipv6_enabled,
  2937. qdf_ipa_wdi_hdl_t hdl)
  2938. {
  2939. int ret;
  2940. ret = qdf_ipa_wdi_dereg_intf(ifname, hdl);
  2941. if (ret) {
  2942. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2943. "%s: ipa_wdi_dereg_intf: IPA pipe deregistration failed: ret=%d",
  2944. __func__, ret);
  2945. return QDF_STATUS_E_FAILURE;
  2946. }
  2947. return QDF_STATUS_SUCCESS;
  2948. }
  2949. #ifdef IPA_SET_RESET_TX_DB_PA
  2950. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res) \
  2951. dp_ipa_set_tx_doorbell_paddr((soc), (ipa_res))
  2952. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res) \
  2953. dp_ipa_reset_tx_doorbell_pa((soc), (ipa_res))
  2954. #else
  2955. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res)
  2956. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res)
  2957. #endif
  2958. QDF_STATUS dp_ipa_enable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2959. qdf_ipa_wdi_hdl_t hdl)
  2960. {
  2961. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2962. struct dp_pdev *pdev =
  2963. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2964. struct dp_ipa_resources *ipa_res;
  2965. QDF_STATUS result;
  2966. if (!pdev) {
  2967. dp_err("Invalid instance");
  2968. return QDF_STATUS_E_FAILURE;
  2969. }
  2970. ipa_res = &pdev->ipa_resource;
  2971. qdf_atomic_set(&soc->ipa_pipes_enabled, 1);
  2972. DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res);
  2973. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, true,
  2974. __func__, __LINE__);
  2975. result = qdf_ipa_wdi_enable_pipes(hdl);
  2976. if (result) {
  2977. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2978. "%s: Enable WDI PIPE fail, code %d",
  2979. __func__, result);
  2980. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  2981. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  2982. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  2983. __func__, __LINE__);
  2984. return QDF_STATUS_E_FAILURE;
  2985. }
  2986. if (soc->ipa_first_tx_db_access) {
  2987. dp_ipa_tx_comp_ring_init_hp(soc, ipa_res);
  2988. soc->ipa_first_tx_db_access = false;
  2989. }
  2990. return QDF_STATUS_SUCCESS;
  2991. }
  2992. QDF_STATUS dp_ipa_disable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2993. qdf_ipa_wdi_hdl_t hdl)
  2994. {
  2995. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2996. struct dp_pdev *pdev =
  2997. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2998. QDF_STATUS result;
  2999. struct dp_ipa_resources *ipa_res;
  3000. if (!pdev) {
  3001. dp_err("Invalid instance");
  3002. return QDF_STATUS_E_FAILURE;
  3003. }
  3004. ipa_res = &pdev->ipa_resource;
  3005. qdf_sleep(TX_COMP_DRAIN_WAIT_TIMEOUT_MS);
  3006. /*
  3007. * Reset the tx completion doorbell address before invoking IPA disable
  3008. * pipes API to ensure that there is no access to IPA tx doorbell
  3009. * address post disable pipes.
  3010. */
  3011. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  3012. result = qdf_ipa_wdi_disable_pipes(hdl);
  3013. if (result) {
  3014. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3015. "%s: Disable WDI PIPE fail, code %d",
  3016. __func__, result);
  3017. qdf_assert_always(0);
  3018. return QDF_STATUS_E_FAILURE;
  3019. }
  3020. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  3021. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  3022. __func__, __LINE__);
  3023. return result ? QDF_STATUS_E_FAILURE : QDF_STATUS_SUCCESS;
  3024. }
  3025. QDF_STATUS dp_ipa_set_perf_level(int client, uint32_t max_supported_bw_mbps,
  3026. qdf_ipa_wdi_hdl_t hdl)
  3027. {
  3028. qdf_ipa_wdi_perf_profile_t profile;
  3029. QDF_STATUS result;
  3030. profile.client = client;
  3031. profile.max_supported_bw_mbps = max_supported_bw_mbps;
  3032. result = qdf_ipa_wdi_set_perf_profile(hdl, &profile);
  3033. if (result) {
  3034. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3035. "%s: ipa_wdi_set_perf_profile fail, code %d",
  3036. __func__, result);
  3037. return QDF_STATUS_E_FAILURE;
  3038. }
  3039. return QDF_STATUS_SUCCESS;
  3040. }
  3041. /**
  3042. * dp_ipa_intrabss_send() - send IPA RX intra-bss frames
  3043. * @pdev: pdev
  3044. * @vdev: vdev
  3045. * @nbuf: skb
  3046. *
  3047. * Return: nbuf if TX fails and NULL if TX succeeds
  3048. */
  3049. static qdf_nbuf_t dp_ipa_intrabss_send(struct dp_pdev *pdev,
  3050. struct dp_vdev *vdev,
  3051. qdf_nbuf_t nbuf)
  3052. {
  3053. struct dp_peer *vdev_peer;
  3054. uint16_t len;
  3055. vdev_peer = dp_vdev_bss_peer_ref_n_get(pdev->soc, vdev, DP_MOD_ID_IPA);
  3056. if (qdf_unlikely(!vdev_peer))
  3057. return nbuf;
  3058. if (qdf_unlikely(!vdev_peer->txrx_peer)) {
  3059. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3060. return nbuf;
  3061. }
  3062. qdf_mem_zero(nbuf->cb, sizeof(nbuf->cb));
  3063. len = qdf_nbuf_len(nbuf);
  3064. if (dp_tx_send((struct cdp_soc_t *)pdev->soc, vdev->vdev_id, nbuf)) {
  3065. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3066. rx.intra_bss.fail, 1, len,
  3067. 0);
  3068. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3069. return nbuf;
  3070. }
  3071. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3072. rx.intra_bss.pkts, 1, len, 0);
  3073. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3074. return NULL;
  3075. }
  3076. #ifdef IPA_OPT_WIFI_DP
  3077. /**
  3078. * dp_ipa_rx_super_rule_setup()- pass cce super rule params to fw from ipa
  3079. *
  3080. * @soc_hdl: cdp soc
  3081. * @flt_params: filter tuple
  3082. *
  3083. * Return: QDF_STATUS
  3084. */
  3085. QDF_STATUS dp_ipa_rx_super_rule_setup(struct cdp_soc_t *soc_hdl,
  3086. void *flt_params)
  3087. {
  3088. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3089. return htt_h2t_rx_cce_super_rule_setup(soc->htt_handle, flt_params);
  3090. }
  3091. /**
  3092. * dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb()- send cce super rule filter
  3093. * add/remove result to ipa
  3094. *
  3095. * @flt0_rslt : result for filter0 add/remove
  3096. * @flt1_rslt : result for filter1 add/remove
  3097. *
  3098. * Return: void
  3099. */
  3100. void dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(int flt0_rslt, int flt1_rslt)
  3101. {
  3102. wlan_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(flt0_rslt, flt1_rslt);
  3103. }
  3104. int dp_ipa_pcie_link_up(struct cdp_soc_t *soc_hdl)
  3105. {
  3106. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3107. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3108. int response = 0;
  3109. response = hif_prevent_l1((hal_soc->hif_handle));
  3110. return response;
  3111. }
  3112. void dp_ipa_pcie_link_down(struct cdp_soc_t *soc_hdl)
  3113. {
  3114. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3115. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3116. hif_allow_l1(hal_soc->hif_handle);
  3117. }
  3118. /**
  3119. * dp_ipa_wdi_opt_dpath_notify_flt_rlsd()- send cce super rule release
  3120. * notification to ipa
  3121. *
  3122. * @flt0_rslt : result for filter0 release
  3123. * @flt1_rslt : result for filter1 release
  3124. *
  3125. *Return: void
  3126. */
  3127. void dp_ipa_wdi_opt_dpath_notify_flt_rlsd(int flt0_rslt, int flt1_rslt)
  3128. {
  3129. wlan_ipa_wdi_opt_dpath_notify_flt_rlsd(flt0_rslt, flt1_rslt);
  3130. }
  3131. /**
  3132. * dp_ipa_wdi_opt_dpath_notify_flt_rsvd()- send cce super rule reserve
  3133. * notification to ipa
  3134. *
  3135. *@is_success : result of filter reservatiom
  3136. *
  3137. *Return: void
  3138. */
  3139. void dp_ipa_wdi_opt_dpath_notify_flt_rsvd(bool is_success)
  3140. {
  3141. wlan_ipa_wdi_opt_dpath_notify_flt_rsvd(is_success);
  3142. }
  3143. #endif
  3144. #ifdef IPA_WDS_EASYMESH_FEATURE
  3145. /**
  3146. * dp_ipa_peer_check() - Check for peer for given mac
  3147. * @soc: dp soc object
  3148. * @peer_mac_addr: peer mac address
  3149. * @vdev_id: vdev id
  3150. *
  3151. * Return: true if peer is found, else false
  3152. */
  3153. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3154. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3155. {
  3156. struct dp_ast_entry *ast_entry = NULL;
  3157. struct dp_peer *peer = NULL;
  3158. qdf_spin_lock_bh(&soc->ast_lock);
  3159. ast_entry = dp_peer_ast_hash_find_soc(soc, peer_mac_addr);
  3160. if ((!ast_entry) ||
  3161. (ast_entry->delete_in_progress && !ast_entry->callback)) {
  3162. qdf_spin_unlock_bh(&soc->ast_lock);
  3163. return false;
  3164. }
  3165. peer = dp_peer_get_ref_by_id(soc, ast_entry->peer_id,
  3166. DP_MOD_ID_IPA);
  3167. if (!peer) {
  3168. qdf_spin_unlock_bh(&soc->ast_lock);
  3169. return false;
  3170. } else {
  3171. if (peer->vdev->vdev_id == vdev_id) {
  3172. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3173. qdf_spin_unlock_bh(&soc->ast_lock);
  3174. return true;
  3175. }
  3176. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3177. qdf_spin_unlock_bh(&soc->ast_lock);
  3178. return false;
  3179. }
  3180. }
  3181. #else
  3182. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3183. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3184. {
  3185. struct cdp_peer_info peer_info = {0};
  3186. struct dp_peer *peer = NULL;
  3187. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac_addr, false,
  3188. CDP_WILD_PEER_TYPE);
  3189. peer = dp_peer_hash_find_wrapper(soc, &peer_info, DP_MOD_ID_IPA);
  3190. if (peer) {
  3191. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3192. return true;
  3193. } else {
  3194. return false;
  3195. }
  3196. }
  3197. #endif
  3198. bool dp_ipa_rx_intrabss_fwd(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3199. qdf_nbuf_t nbuf, bool *fwd_success)
  3200. {
  3201. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3202. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3203. DP_MOD_ID_IPA);
  3204. struct dp_pdev *pdev;
  3205. qdf_nbuf_t nbuf_copy;
  3206. uint8_t da_is_bcmc;
  3207. struct ethhdr *eh;
  3208. bool status = false;
  3209. *fwd_success = false; /* set default as failure */
  3210. /*
  3211. * WDI 3.0 skb->cb[] info from IPA driver
  3212. * skb->cb[0] = vdev_id
  3213. * skb->cb[1].bit#1 = da_is_bcmc
  3214. */
  3215. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3216. if (qdf_unlikely(!vdev))
  3217. return false;
  3218. pdev = vdev->pdev;
  3219. if (qdf_unlikely(!pdev))
  3220. goto out;
  3221. /* no fwd for station mode and just pass up to stack */
  3222. if (vdev->opmode == wlan_op_mode_sta)
  3223. goto out;
  3224. if (da_is_bcmc) {
  3225. nbuf_copy = qdf_nbuf_copy(nbuf);
  3226. if (!nbuf_copy)
  3227. goto out;
  3228. if (dp_ipa_intrabss_send(pdev, vdev, nbuf_copy))
  3229. qdf_nbuf_free(nbuf_copy);
  3230. else
  3231. *fwd_success = true;
  3232. /* return false to pass original pkt up to stack */
  3233. goto out;
  3234. }
  3235. eh = (struct ethhdr *)qdf_nbuf_data(nbuf);
  3236. if (!qdf_mem_cmp(eh->h_dest, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  3237. goto out;
  3238. if (!dp_ipa_peer_check(soc, eh->h_dest, vdev->vdev_id))
  3239. goto out;
  3240. if (!dp_ipa_peer_check(soc, eh->h_source, vdev->vdev_id))
  3241. goto out;
  3242. /*
  3243. * In intra-bss forwarding scenario, skb is allocated by IPA driver.
  3244. * Need to add skb to internal tracking table to avoid nbuf memory
  3245. * leak check for unallocated skb.
  3246. */
  3247. qdf_net_buf_debug_acquire_skb(nbuf, __FILE__, __LINE__);
  3248. if (dp_ipa_intrabss_send(pdev, vdev, nbuf))
  3249. qdf_nbuf_free(nbuf);
  3250. else
  3251. *fwd_success = true;
  3252. status = true;
  3253. out:
  3254. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3255. return status;
  3256. }
  3257. #ifdef MDM_PLATFORM
  3258. bool dp_ipa_is_mdm_platform(void)
  3259. {
  3260. return true;
  3261. }
  3262. #else
  3263. bool dp_ipa_is_mdm_platform(void)
  3264. {
  3265. return false;
  3266. }
  3267. #endif
  3268. /**
  3269. * dp_ipa_frag_nbuf_linearize() - linearize nbuf for IPA
  3270. * @soc: soc
  3271. * @nbuf: source skb
  3272. *
  3273. * Return: new nbuf if success and otherwise NULL
  3274. */
  3275. static qdf_nbuf_t dp_ipa_frag_nbuf_linearize(struct dp_soc *soc,
  3276. qdf_nbuf_t nbuf)
  3277. {
  3278. uint8_t *src_nbuf_data;
  3279. uint8_t *dst_nbuf_data;
  3280. qdf_nbuf_t dst_nbuf;
  3281. qdf_nbuf_t temp_nbuf = nbuf;
  3282. uint32_t nbuf_len = qdf_nbuf_len(nbuf);
  3283. bool is_nbuf_head = true;
  3284. uint32_t copy_len = 0;
  3285. dst_nbuf = qdf_nbuf_alloc(soc->osdev, RX_DATA_BUFFER_SIZE,
  3286. RX_BUFFER_RESERVATION,
  3287. RX_DATA_BUFFER_ALIGNMENT, FALSE);
  3288. if (!dst_nbuf) {
  3289. dp_err_rl("nbuf allocate fail");
  3290. return NULL;
  3291. }
  3292. if ((nbuf_len + L3_HEADER_PADDING) > RX_DATA_BUFFER_SIZE) {
  3293. qdf_nbuf_free(dst_nbuf);
  3294. dp_err_rl("nbuf is jumbo data");
  3295. return NULL;
  3296. }
  3297. /* prepeare to copy all data into new skb */
  3298. dst_nbuf_data = qdf_nbuf_data(dst_nbuf);
  3299. while (temp_nbuf) {
  3300. src_nbuf_data = qdf_nbuf_data(temp_nbuf);
  3301. /* first head nbuf */
  3302. if (is_nbuf_head) {
  3303. qdf_mem_copy(dst_nbuf_data, src_nbuf_data,
  3304. soc->rx_pkt_tlv_size);
  3305. /* leave extra 2 bytes L3_HEADER_PADDING */
  3306. dst_nbuf_data += (soc->rx_pkt_tlv_size +
  3307. L3_HEADER_PADDING);
  3308. src_nbuf_data += soc->rx_pkt_tlv_size;
  3309. copy_len = qdf_nbuf_headlen(temp_nbuf) -
  3310. soc->rx_pkt_tlv_size;
  3311. temp_nbuf = qdf_nbuf_get_ext_list(temp_nbuf);
  3312. is_nbuf_head = false;
  3313. } else {
  3314. copy_len = qdf_nbuf_len(temp_nbuf);
  3315. temp_nbuf = qdf_nbuf_queue_next(temp_nbuf);
  3316. }
  3317. qdf_mem_copy(dst_nbuf_data, src_nbuf_data, copy_len);
  3318. dst_nbuf_data += copy_len;
  3319. }
  3320. qdf_nbuf_set_len(dst_nbuf, nbuf_len);
  3321. /* copy is done, free original nbuf */
  3322. qdf_nbuf_free(nbuf);
  3323. return dst_nbuf;
  3324. }
  3325. qdf_nbuf_t dp_ipa_handle_rx_reo_reinject(struct dp_soc *soc, qdf_nbuf_t nbuf)
  3326. {
  3327. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  3328. return nbuf;
  3329. /* WLAN IPA is run-time disabled */
  3330. if (!qdf_atomic_read(&soc->ipa_pipes_enabled))
  3331. return nbuf;
  3332. if (!qdf_nbuf_is_frag(nbuf))
  3333. return nbuf;
  3334. /* linearize skb for IPA */
  3335. return dp_ipa_frag_nbuf_linearize(soc, nbuf);
  3336. }
  3337. QDF_STATUS dp_ipa_tx_buf_smmu_mapping(
  3338. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3339. const char *func, uint32_t line)
  3340. {
  3341. QDF_STATUS ret;
  3342. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3343. struct dp_pdev *pdev =
  3344. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3345. if (!pdev) {
  3346. dp_err("%s invalid instance", __func__);
  3347. return QDF_STATUS_E_FAILURE;
  3348. }
  3349. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3350. dp_debug("SMMU S1 disabled");
  3351. return QDF_STATUS_SUCCESS;
  3352. }
  3353. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, true, func, line);
  3354. if (ret)
  3355. return ret;
  3356. if (dp_ipa_is_alt_tx_required(soc)) {
  3357. ret = dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, true, func,
  3358. line);
  3359. if (ret)
  3360. __dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func,
  3361. line);
  3362. }
  3363. return ret;
  3364. }
  3365. QDF_STATUS dp_ipa_tx_buf_smmu_unmapping(
  3366. struct cdp_soc_t *soc_hdl, uint8_t pdev_id, const char *func,
  3367. uint32_t line)
  3368. {
  3369. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3370. struct dp_pdev *pdev =
  3371. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3372. if (!pdev) {
  3373. dp_err("%s invalid instance", __func__);
  3374. return QDF_STATUS_E_FAILURE;
  3375. }
  3376. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3377. dp_debug("SMMU S1 disabled");
  3378. return QDF_STATUS_SUCCESS;
  3379. }
  3380. if (__dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line))
  3381. return QDF_STATUS_E_FAILURE;
  3382. if (dp_ipa_is_alt_tx_required(soc)) {
  3383. if (dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, false, func,
  3384. line))
  3385. return QDF_STATUS_E_FAILURE;
  3386. }
  3387. return QDF_STATUS_SUCCESS;
  3388. }
  3389. #ifdef IPA_WDS_EASYMESH_FEATURE
  3390. QDF_STATUS dp_ipa_ast_create(struct cdp_soc_t *soc_hdl,
  3391. qdf_ipa_ast_info_type_t *data)
  3392. {
  3393. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3394. uint8_t *rx_tlv_hdr;
  3395. struct dp_peer *peer;
  3396. struct hal_rx_msdu_metadata msdu_metadata;
  3397. qdf_ipa_ast_info_type_t *ast_info;
  3398. if (!data) {
  3399. dp_err("Data is NULL !!!");
  3400. return QDF_STATUS_E_FAILURE;
  3401. }
  3402. ast_info = data;
  3403. rx_tlv_hdr = qdf_nbuf_data(ast_info->skb);
  3404. peer = dp_peer_get_ref_by_id(soc, ast_info->ta_peer_id,
  3405. DP_MOD_ID_IPA);
  3406. if (!peer) {
  3407. dp_err("Peer is NULL !!!!");
  3408. return QDF_STATUS_E_FAILURE;
  3409. }
  3410. hal_rx_msdu_metadata_get(soc->hal_soc, rx_tlv_hdr, &msdu_metadata);
  3411. dp_rx_ipa_wds_srcport_learn(soc, peer, ast_info->skb, msdu_metadata,
  3412. ast_info->mac_addr_ad4_valid,
  3413. ast_info->first_msdu_in_mpdu_flag);
  3414. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3415. return QDF_STATUS_SUCCESS;
  3416. }
  3417. #endif
  3418. #ifdef QCA_ENHANCED_STATS_SUPPORT
  3419. QDF_STATUS dp_ipa_update_peer_rx_stats(struct cdp_soc_t *soc,
  3420. uint8_t vdev_id, uint8_t *peer_mac,
  3421. qdf_nbuf_t nbuf)
  3422. {
  3423. struct dp_peer *peer = dp_peer_find_hash_find((struct dp_soc *)soc,
  3424. peer_mac, 0, vdev_id,
  3425. DP_MOD_ID_IPA);
  3426. struct dp_txrx_peer *txrx_peer;
  3427. uint8_t da_is_bcmc;
  3428. qdf_ether_header_t *eh;
  3429. if (!peer)
  3430. return QDF_STATUS_E_FAILURE;
  3431. txrx_peer = dp_get_txrx_peer(peer);
  3432. if (!txrx_peer) {
  3433. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3434. return QDF_STATUS_E_FAILURE;
  3435. }
  3436. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3437. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3438. if (da_is_bcmc) {
  3439. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.multicast, 1,
  3440. qdf_nbuf_len(nbuf), 0);
  3441. if (QDF_IS_ADDR_BROADCAST(eh->ether_dhost))
  3442. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.bcast,
  3443. 1, qdf_nbuf_len(nbuf), 0);
  3444. }
  3445. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3446. return QDF_STATUS_SUCCESS;
  3447. }
  3448. void
  3449. dp_peer_aggregate_tid_stats(struct dp_peer *peer)
  3450. {
  3451. uint8_t i = 0;
  3452. struct dp_rx_tid *rx_tid = NULL;
  3453. struct cdp_pkt_info rx_total = {0};
  3454. struct dp_txrx_peer *txrx_peer = NULL;
  3455. if (!peer->rx_tid)
  3456. return;
  3457. txrx_peer = dp_get_txrx_peer(peer);
  3458. if (!txrx_peer)
  3459. return;
  3460. for (i = 0; i < DP_MAX_TIDS; i++) {
  3461. rx_tid = &peer->rx_tid[i];
  3462. rx_total.num += rx_tid->rx_msdu_cnt.num;
  3463. rx_total.bytes += rx_tid->rx_msdu_cnt.bytes;
  3464. }
  3465. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.num,
  3466. rx_total.num, 0);
  3467. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.bytes,
  3468. rx_total.bytes, 0);
  3469. }
  3470. /**
  3471. * dp_ipa_update_vdev_stats(): update vdev stats
  3472. * @soc: soc handle
  3473. * @srcobj: DP_PEER object
  3474. * @arg: point to vdev stats structure
  3475. *
  3476. * Return: void
  3477. */
  3478. static inline
  3479. void dp_ipa_update_vdev_stats(struct dp_soc *soc, struct dp_peer *srcobj,
  3480. void *arg)
  3481. {
  3482. dp_peer_aggregate_tid_stats(srcobj);
  3483. dp_update_vdev_stats(soc, srcobj, arg);
  3484. }
  3485. /**
  3486. * dp_ipa_aggregate_vdev_stats - Aggregate vdev_stats
  3487. * @vdev: Data path vdev
  3488. * @vdev_stats: buffer to hold vdev stats
  3489. *
  3490. * Return: void
  3491. */
  3492. static inline
  3493. void dp_ipa_aggregate_vdev_stats(struct dp_vdev *vdev,
  3494. struct cdp_vdev_stats *vdev_stats)
  3495. {
  3496. struct dp_soc *soc = NULL;
  3497. if (!vdev || !vdev->pdev)
  3498. return;
  3499. soc = vdev->pdev->soc;
  3500. dp_update_vdev_ingress_stats(vdev);
  3501. qdf_mem_copy(vdev_stats, &vdev->stats, sizeof(vdev->stats));
  3502. dp_vdev_iterate_peer(vdev, dp_ipa_update_vdev_stats, vdev_stats,
  3503. DP_MOD_ID_GENERIC_STATS);
  3504. dp_update_vdev_rate_stats(vdev_stats, &vdev->stats);
  3505. vdev_stats->tx.ucast.num = vdev_stats->tx.tx_ucast_total.num;
  3506. vdev_stats->tx.ucast.bytes = vdev_stats->tx.tx_ucast_total.bytes;
  3507. vdev_stats->tx.tx_success.num = vdev_stats->tx.tx_ucast_success.num;
  3508. vdev_stats->tx.tx_success.bytes = vdev_stats->tx.tx_ucast_success.bytes;
  3509. if (vdev_stats->rx.rx_total.num >= vdev_stats->rx.multicast.num)
  3510. vdev_stats->rx.unicast.num = vdev_stats->rx.rx_total.num -
  3511. vdev_stats->rx.multicast.num;
  3512. if (vdev_stats->rx.rx_total.bytes >= vdev_stats->rx.multicast.bytes)
  3513. vdev_stats->rx.unicast.bytes = vdev_stats->rx.rx_total.bytes -
  3514. vdev_stats->rx.multicast.bytes;
  3515. vdev_stats->rx.to_stack.num = vdev_stats->rx.rx_total.num;
  3516. vdev_stats->rx.to_stack.bytes = vdev_stats->rx.rx_total.bytes;
  3517. }
  3518. /**
  3519. * dp_ipa_aggregate_pdev_stats - Aggregate pdev stats
  3520. * @pdev: Data path pdev
  3521. *
  3522. * Return: void
  3523. */
  3524. static inline
  3525. void dp_ipa_aggregate_pdev_stats(struct dp_pdev *pdev)
  3526. {
  3527. struct dp_vdev *vdev = NULL;
  3528. struct dp_soc *soc;
  3529. struct cdp_vdev_stats *vdev_stats =
  3530. qdf_mem_malloc_atomic(sizeof(struct cdp_vdev_stats));
  3531. if (!vdev_stats) {
  3532. dp_err("%pK: DP alloc failure - unable to get alloc vdev stats",
  3533. pdev->soc);
  3534. return;
  3535. }
  3536. soc = pdev->soc;
  3537. qdf_mem_zero(&pdev->stats.tx, sizeof(pdev->stats.tx));
  3538. qdf_mem_zero(&pdev->stats.rx, sizeof(pdev->stats.rx));
  3539. qdf_mem_zero(&pdev->stats.tx_i, sizeof(pdev->stats.tx_i));
  3540. qdf_mem_zero(&pdev->stats.rx_i, sizeof(pdev->stats.rx_i));
  3541. qdf_spin_lock_bh(&pdev->vdev_list_lock);
  3542. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3543. dp_ipa_aggregate_vdev_stats(vdev, vdev_stats);
  3544. dp_update_pdev_stats(pdev, vdev_stats);
  3545. dp_update_pdev_ingress_stats(pdev, vdev);
  3546. }
  3547. qdf_spin_unlock_bh(&pdev->vdev_list_lock);
  3548. qdf_mem_free(vdev_stats);
  3549. }
  3550. /**
  3551. * dp_ipa_get_peer_stats - Get peer stats
  3552. * @peer: Data path peer
  3553. * @peer_stats: buffer to hold peer stats
  3554. *
  3555. * Return: void
  3556. */
  3557. static
  3558. void dp_ipa_get_peer_stats(struct dp_peer *peer,
  3559. struct cdp_peer_stats *peer_stats)
  3560. {
  3561. dp_peer_aggregate_tid_stats(peer);
  3562. dp_get_peer_stats(peer, peer_stats);
  3563. peer_stats->tx.tx_success.num =
  3564. peer_stats->tx.tx_ucast_success.num;
  3565. peer_stats->tx.tx_success.bytes =
  3566. peer_stats->tx.tx_ucast_success.bytes;
  3567. peer_stats->tx.ucast.num =
  3568. peer_stats->tx.tx_ucast_total.num;
  3569. peer_stats->tx.ucast.bytes =
  3570. peer_stats->tx.tx_ucast_total.bytes;
  3571. if (peer_stats->rx.rx_total.num >= peer_stats->rx.multicast.num)
  3572. peer_stats->rx.unicast.num = peer_stats->rx.rx_total.num -
  3573. peer_stats->rx.multicast.num;
  3574. if (peer_stats->rx.rx_total.bytes >= peer_stats->rx.multicast.bytes)
  3575. peer_stats->rx.unicast.bytes = peer_stats->rx.rx_total.bytes -
  3576. peer_stats->rx.multicast.bytes;
  3577. }
  3578. QDF_STATUS
  3579. dp_ipa_txrx_get_pdev_stats(struct cdp_soc_t *soc, uint8_t pdev_id,
  3580. struct cdp_pdev_stats *pdev_stats)
  3581. {
  3582. struct dp_pdev *pdev =
  3583. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)soc,
  3584. pdev_id);
  3585. if (!pdev)
  3586. return QDF_STATUS_E_FAILURE;
  3587. dp_ipa_aggregate_pdev_stats(pdev);
  3588. qdf_mem_copy(pdev_stats, &pdev->stats, sizeof(struct cdp_pdev_stats));
  3589. return QDF_STATUS_SUCCESS;
  3590. }
  3591. int dp_ipa_txrx_get_vdev_stats(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3592. void *buf, bool is_aggregate)
  3593. {
  3594. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3595. struct cdp_vdev_stats *vdev_stats;
  3596. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3597. DP_MOD_ID_IPA);
  3598. if (!vdev)
  3599. return 1;
  3600. vdev_stats = (struct cdp_vdev_stats *)buf;
  3601. dp_ipa_aggregate_vdev_stats(vdev, buf);
  3602. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3603. return 0;
  3604. }
  3605. QDF_STATUS dp_ipa_txrx_get_peer_stats(struct cdp_soc_t *soc, uint8_t vdev_id,
  3606. uint8_t *peer_mac,
  3607. struct cdp_peer_stats *peer_stats)
  3608. {
  3609. struct dp_peer *peer = NULL;
  3610. struct cdp_peer_info peer_info = { 0 };
  3611. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac, false,
  3612. CDP_WILD_PEER_TYPE);
  3613. peer = dp_peer_hash_find_wrapper((struct dp_soc *)soc, &peer_info,
  3614. DP_MOD_ID_IPA);
  3615. qdf_mem_zero(peer_stats, sizeof(struct cdp_peer_stats));
  3616. if (!peer)
  3617. return QDF_STATUS_E_FAILURE;
  3618. dp_ipa_get_peer_stats(peer, peer_stats);
  3619. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3620. return QDF_STATUS_SUCCESS;
  3621. }
  3622. #endif
  3623. /**
  3624. * dp_ipa_get_wdi_version() - Get WDI version
  3625. * @soc_hdl: data path soc handle
  3626. * @wdi_ver: Out parameter for wdi version
  3627. *
  3628. * Get WDI version based on soc arch
  3629. *
  3630. * Return: None
  3631. */
  3632. void dp_ipa_get_wdi_version(struct cdp_soc_t *soc_hdl, uint8_t *wdi_ver)
  3633. {
  3634. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3635. if (soc->arch_ops.ipa_get_wdi_ver)
  3636. soc->arch_ops.ipa_get_wdi_ver(wdi_ver);
  3637. else
  3638. *wdi_ver = IPA_WDI_3;
  3639. }
  3640. #endif