dp_li_tx.c 16 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "dp_types.h"
  21. #include "dp_tx.h"
  22. #include "dp_li_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include <dp_internal.h>
  25. #include <dp_htt.h>
  26. #include <hal_li_api.h>
  27. #include <hal_li_tx.h>
  28. #include "dp_peer.h"
  29. #ifdef FEATURE_WDS
  30. #include "dp_txrx_wds.h"
  31. #endif
  32. #include "dp_li.h"
  33. extern uint8_t sec_type_map[MAX_CDP_SEC_TYPE];
  34. void dp_tx_comp_get_params_from_hal_desc_li(struct dp_soc *soc,
  35. void *tx_comp_hal_desc,
  36. struct dp_tx_desc_s **r_tx_desc)
  37. {
  38. uint8_t pool_id;
  39. uint32_t tx_desc_id;
  40. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  41. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  42. DP_TX_DESC_ID_POOL_OS;
  43. /* Find Tx descriptor */
  44. *r_tx_desc = dp_tx_desc_find(soc, pool_id,
  45. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  46. DP_TX_DESC_ID_PAGE_OS,
  47. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  48. DP_TX_DESC_ID_OFFSET_OS);
  49. /* Pool id is not matching. Error */
  50. if ((*r_tx_desc)->pool_id != pool_id) {
  51. dp_tx_comp_alert("Tx Comp pool id %d not matched %d",
  52. pool_id, (*r_tx_desc)->pool_id);
  53. qdf_assert_always(0);
  54. }
  55. (*r_tx_desc)->peer_id = hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  56. }
  57. static inline
  58. void dp_tx_process_mec_notify_li(struct dp_soc *soc, uint8_t *status)
  59. {
  60. struct dp_vdev *vdev;
  61. uint8_t vdev_id;
  62. uint32_t *htt_desc = (uint32_t *)status;
  63. /*
  64. * Get vdev id from HTT status word in case of MEC
  65. * notification
  66. */
  67. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  68. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  69. return;
  70. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  71. DP_MOD_ID_HTT_COMP);
  72. if (!vdev)
  73. return;
  74. dp_tx_mec_handler(vdev, status);
  75. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  76. }
  77. void dp_tx_process_htt_completion_li(struct dp_soc *soc,
  78. struct dp_tx_desc_s *tx_desc,
  79. uint8_t *status,
  80. uint8_t ring_id)
  81. {
  82. uint8_t tx_status;
  83. struct dp_pdev *pdev;
  84. struct dp_vdev *vdev = NULL;
  85. struct hal_tx_completion_status ts = {0};
  86. uint32_t *htt_desc = (uint32_t *)status;
  87. struct dp_txrx_peer *txrx_peer;
  88. dp_txrx_ref_handle txrx_ref_handle = NULL;
  89. struct cdp_tid_tx_stats *tid_stats = NULL;
  90. struct htt_soc *htt_handle;
  91. uint8_t vdev_id;
  92. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  93. htt_handle = (struct htt_soc *)soc->htt_handle;
  94. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  95. /*
  96. * There can be scenario where WBM consuming descriptor enqueued
  97. * from TQM2WBM first and TQM completion can happen before MEC
  98. * notification comes from FW2WBM. Avoid access any field of tx
  99. * descriptor in case of MEC notify.
  100. */
  101. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY)
  102. return dp_tx_process_mec_notify_li(soc, status);
  103. /*
  104. * If the descriptor is already freed in vdev_detach,
  105. * continue to next descriptor
  106. */
  107. if (qdf_unlikely(!tx_desc->flags)) {
  108. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  109. tx_desc->id);
  110. return;
  111. }
  112. if (qdf_unlikely(tx_desc->vdev_id == DP_INVALID_VDEV_ID)) {
  113. dp_tx_comp_info_rl("Invalid vdev_id %d", tx_desc->id);
  114. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  115. goto release_tx_desc;
  116. }
  117. pdev = tx_desc->pdev;
  118. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  119. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  120. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  121. goto release_tx_desc;
  122. }
  123. qdf_assert(tx_desc->pdev);
  124. vdev_id = tx_desc->vdev_id;
  125. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  126. DP_MOD_ID_HTT_COMP);
  127. if (qdf_unlikely(!vdev)) {
  128. dp_tx_comp_info_rl("Unable to get vdev ref %d", tx_desc->id);
  129. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  130. goto release_tx_desc;
  131. }
  132. switch (tx_status) {
  133. case HTT_TX_FW2WBM_TX_STATUS_OK:
  134. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  135. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  136. {
  137. uint8_t tid;
  138. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  139. ts.peer_id =
  140. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  141. htt_desc[2]);
  142. ts.tid =
  143. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  144. htt_desc[2]);
  145. } else {
  146. ts.peer_id = HTT_INVALID_PEER;
  147. ts.tid = HTT_INVALID_TID;
  148. }
  149. ts.release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
  150. ts.ppdu_id =
  151. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  152. htt_desc[1]);
  153. ts.ack_frame_rssi =
  154. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  155. htt_desc[1]);
  156. ts.tsf = htt_desc[3];
  157. ts.first_msdu = 1;
  158. ts.last_msdu = 1;
  159. tid = ts.tid;
  160. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  161. tid = CDP_MAX_DATA_TIDS - 1;
  162. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  163. if (qdf_unlikely(pdev->delay_stats_flag) ||
  164. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(vdev)))
  165. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  166. if (tx_status < CDP_MAX_TX_HTT_STATUS)
  167. tid_stats->htt_status_cnt[tx_status]++;
  168. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, ts.peer_id,
  169. &txrx_ref_handle,
  170. DP_MOD_ID_HTT_COMP);
  171. if (qdf_likely(txrx_peer)) {
  172. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1,
  173. qdf_nbuf_len(tx_desc->nbuf));
  174. if (tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)
  175. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  176. }
  177. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, txrx_peer,
  178. ring_id);
  179. dp_tx_comp_process_desc(soc, tx_desc, &ts, txrx_peer);
  180. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  181. if (qdf_likely(txrx_peer))
  182. dp_txrx_peer_unref_delete(txrx_ref_handle,
  183. DP_MOD_ID_HTT_COMP);
  184. break;
  185. }
  186. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  187. {
  188. uint8_t reinject_reason;
  189. reinject_reason =
  190. HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_GET(
  191. htt_desc[0]);
  192. dp_tx_reinject_handler(soc, vdev, tx_desc,
  193. status, reinject_reason);
  194. break;
  195. }
  196. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  197. {
  198. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  199. break;
  200. }
  201. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  202. {
  203. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  204. goto release_tx_desc;
  205. }
  206. default:
  207. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  208. tx_status);
  209. goto release_tx_desc;
  210. }
  211. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  212. return;
  213. release_tx_desc:
  214. dp_tx_comp_free_buf(soc, tx_desc);
  215. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  216. if (vdev)
  217. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  218. }
  219. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  220. /*
  221. * dp_tx_get_rbm_id()- Get the RBM ID for data transmission completion.
  222. * @dp_soc - DP soc structure pointer
  223. * @ring_id - Transmit Queue/ring_id to be used when XPS is enabled
  224. *
  225. * Return - HAL ring handle
  226. */
  227. #ifdef IPA_OFFLOAD
  228. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  229. uint8_t ring_id)
  230. {
  231. return (ring_id + soc->wbm_sw0_bm_id);
  232. }
  233. #else
  234. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  235. uint8_t ring_id)
  236. {
  237. if (ring_id == soc->num_tcl_data_rings)
  238. return HAL_WBM_SW4_BM_ID(soc->wbm_sw0_bm_id);
  239. return (ring_id + HAL_WBM_SW0_BM_ID(soc->wbm_sw0_bm_id));
  240. }
  241. #endif
  242. #else
  243. #ifdef TX_MULTI_TCL
  244. #ifdef IPA_OFFLOAD
  245. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  246. uint8_t ring_id)
  247. {
  248. if (soc->wlan_cfg_ctx->ipa_enabled)
  249. return (ring_id + soc->wbm_sw0_bm_id);
  250. return soc->wlan_cfg_ctx->tcl_wbm_map_array[ring_id].wbm_rbm_id;
  251. }
  252. #else
  253. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  254. uint8_t ring_id)
  255. {
  256. return soc->wlan_cfg_ctx->tcl_wbm_map_array[ring_id].wbm_rbm_id;
  257. }
  258. #endif
  259. #else
  260. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  261. uint8_t ring_id)
  262. {
  263. return (ring_id + soc->wbm_sw0_bm_id);
  264. }
  265. #endif
  266. #endif
  267. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  268. /**
  269. * dp_tx_clear_consumed_hw_descs - Reset all the consumed Tx ring descs to 0
  270. *
  271. * @soc: DP soc handle
  272. * @hal_ring_hdl: Source ring pointer
  273. *
  274. * Return: void
  275. */
  276. static inline
  277. void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
  278. hal_ring_handle_t hal_ring_hdl)
  279. {
  280. void *desc = hal_srng_src_get_next_consumed(soc->hal_soc, hal_ring_hdl);
  281. while (desc) {
  282. hal_tx_desc_clear(desc);
  283. desc = hal_srng_src_get_next_consumed(soc->hal_soc,
  284. hal_ring_hdl);
  285. }
  286. }
  287. #else
  288. static inline
  289. void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
  290. hal_ring_handle_t hal_ring_hdl)
  291. {
  292. }
  293. #endif /* CLEAR_SW2TCL_CONSUMED_DESC */
  294. #ifdef CONFIG_SAWF
  295. /**
  296. * dp_sawf_config_li - Configure sawf specific fields in tcl
  297. *
  298. * @soc: DP soc handle
  299. * @hhal_tx_desc_cached: tx descriptor
  300. * @vdev_id: vdev id
  301. * @nbuf: skb buffer
  302. *
  303. * Return: void
  304. */
  305. static inline
  306. void dp_sawf_config_li(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  307. uint16_t *fw_metadata, uint16_t vdev_id,
  308. qdf_nbuf_t nbuf)
  309. {
  310. uint8_t q_id = 0;
  311. uint32_t search_index;
  312. if (!wlan_cfg_get_sawf_config(soc->wlan_cfg_ctx))
  313. return;
  314. q_id = dp_sawf_queue_id_get(nbuf);
  315. if (q_id == DP_SAWF_DEFAULT_Q_INVALID)
  316. return;
  317. dp_sawf_tcl_cmd(fw_metadata, nbuf);
  318. search_index = dp_sawf_get_search_index(soc, nbuf, vdev_id,
  319. q_id);
  320. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, (q_id & 0x7));
  321. hal_tx_desc_set_search_type_li(soc->hal_soc, hal_tx_desc_cached,
  322. HAL_TX_ADDR_INDEX_SEARCH);
  323. hal_tx_desc_set_search_index_li(soc->hal_soc, hal_tx_desc_cached,
  324. search_index);
  325. }
  326. #else
  327. static inline
  328. void dp_sawf_config_li(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  329. uint16_t *fw_metadata, uint16_t vdev_id,
  330. qdf_nbuf_t nbuf)
  331. {
  332. }
  333. #define dp_sawf_tx_enqueue_peer_stats(soc, tx_desc)
  334. #define dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc)
  335. #endif
  336. QDF_STATUS
  337. dp_tx_hw_enqueue_li(struct dp_soc *soc, struct dp_vdev *vdev,
  338. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  339. struct cdp_tx_exception_metadata *tx_exc_metadata,
  340. struct dp_tx_msdu_info_s *msdu_info)
  341. {
  342. void *hal_tx_desc;
  343. uint32_t *hal_tx_desc_cached;
  344. int coalesce = 0;
  345. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  346. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  347. uint8_t tid = msdu_info->tid;
  348. /*
  349. * Setting it initialization statically here to avoid
  350. * a memset call jump with qdf_mem_set call
  351. */
  352. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  353. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  354. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  355. tx_exc_metadata->sec_type : vdev->sec_type);
  356. /* Return Buffer Manager ID */
  357. uint8_t bm_id = dp_tx_get_rbm_id_li(soc, ring_id);
  358. hal_ring_handle_t hal_ring_hdl = NULL;
  359. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  360. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  361. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  362. return QDF_STATUS_E_RESOURCES;
  363. }
  364. hal_tx_desc_cached = (void *)cached_desc;
  365. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  366. tx_desc->dma_addr, bm_id, tx_desc->id,
  367. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  368. hal_tx_desc_set_lmac_id_li(soc->hal_soc, hal_tx_desc_cached,
  369. vdev->lmac_id);
  370. hal_tx_desc_set_search_type_li(soc->hal_soc, hal_tx_desc_cached,
  371. vdev->search_type);
  372. hal_tx_desc_set_search_index_li(soc->hal_soc, hal_tx_desc_cached,
  373. vdev->bss_ast_idx);
  374. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  375. vdev->dscp_tid_map_id);
  376. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  377. sec_type_map[sec_type]);
  378. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  379. (vdev->bss_ast_hash & 0xF));
  380. if (dp_sawf_tag_valid_get(tx_desc->nbuf)) {
  381. dp_sawf_config_li(soc, hal_tx_desc_cached, &fw_metadata,
  382. vdev->vdev_id, tx_desc->nbuf);
  383. dp_sawf_tx_enqueue_peer_stats(soc, tx_desc);
  384. }
  385. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  386. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  387. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  388. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  389. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  390. vdev->hal_desc_addr_search_flags);
  391. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  392. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  393. /* verify checksum offload configuration*/
  394. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) ==
  395. QDF_NBUF_TX_CKSUM_TCP_UDP) ||
  396. qdf_nbuf_is_tso(tx_desc->nbuf)) {
  397. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  398. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  399. }
  400. if (tid != HTT_TX_EXT_TID_INVALID)
  401. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  402. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  403. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  404. if (!dp_tx_desc_set_ktimestamp(vdev, tx_desc))
  405. dp_tx_desc_set_timestamp(tx_desc);
  406. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  407. tx_desc->length,
  408. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
  409. (uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
  410. tx_desc->id);
  411. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  412. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  413. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  414. "%s %d : HAL RING Access Failed -- %pK",
  415. __func__, __LINE__, hal_ring_hdl);
  416. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  417. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  418. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  419. return status;
  420. }
  421. dp_tx_clear_consumed_hw_descs(soc, hal_ring_hdl);
  422. /* Sync cached descriptor with HW */
  423. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  424. if (qdf_unlikely(!hal_tx_desc)) {
  425. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  426. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  427. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  428. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  429. goto ring_access_fail;
  430. }
  431. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  432. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  433. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  434. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid,
  435. msdu_info, ring_id);
  436. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  437. DP_STATS_INC(soc, tx.tcl_enq[ring_id], 1);
  438. dp_tx_update_stats(soc, tx_desc, ring_id);
  439. status = QDF_STATUS_SUCCESS;
  440. dp_tx_hw_desc_update_evt((uint8_t *)hal_tx_desc_cached,
  441. hal_ring_hdl, soc);
  442. ring_access_fail:
  443. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
  444. dp_pkt_add_timestamp(vdev, QDF_PKT_TX_DRIVER_EXIT,
  445. qdf_get_log_timestamp(), tx_desc->nbuf);
  446. return status;
  447. }
  448. QDF_STATUS dp_tx_desc_pool_init_li(struct dp_soc *soc,
  449. uint32_t num_elem,
  450. uint8_t pool_id)
  451. {
  452. uint32_t id, count, page_id, offset, pool_id_32;
  453. struct dp_tx_desc_s *tx_desc;
  454. struct dp_tx_desc_pool_s *tx_desc_pool;
  455. uint16_t num_desc_per_page;
  456. tx_desc_pool = &soc->tx_desc[pool_id];
  457. tx_desc = tx_desc_pool->freelist;
  458. count = 0;
  459. pool_id_32 = (uint32_t)pool_id;
  460. num_desc_per_page = tx_desc_pool->desc_pages.num_element_per_page;
  461. while (tx_desc) {
  462. page_id = count / num_desc_per_page;
  463. offset = count % num_desc_per_page;
  464. id = ((pool_id_32 << DP_TX_DESC_ID_POOL_OS) |
  465. (page_id << DP_TX_DESC_ID_PAGE_OS) | offset);
  466. tx_desc->id = id;
  467. tx_desc->pool_id = pool_id;
  468. dp_tx_desc_set_magic(tx_desc, DP_TX_MAGIC_PATTERN_FREE);
  469. tx_desc = tx_desc->next;
  470. count++;
  471. }
  472. return QDF_STATUS_SUCCESS;
  473. }
  474. void dp_tx_desc_pool_deinit_li(struct dp_soc *soc,
  475. struct dp_tx_desc_pool_s *tx_desc_pool,
  476. uint8_t pool_id)
  477. {
  478. }