dp_be.c 44 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  26. #include "dp_mon_2.0.h"
  27. #endif
  28. #include <hal_be_api.h>
  29. /* Generic AST entry aging timer value */
  30. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  31. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  32. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  33. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  34. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  35. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  36. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  37. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  38. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  39. };
  40. #else
  41. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  42. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  43. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  44. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  45. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  46. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  47. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  48. };
  49. #endif
  50. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  51. {
  52. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  53. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  54. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  55. /* this is used only when dmac mode is enabled */
  56. soc->num_rx_refill_buf_rings = 1;
  57. }
  58. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  59. {
  60. switch (context_type) {
  61. case DP_CONTEXT_TYPE_SOC:
  62. return sizeof(struct dp_soc_be);
  63. case DP_CONTEXT_TYPE_PDEV:
  64. return sizeof(struct dp_pdev_be);
  65. case DP_CONTEXT_TYPE_VDEV:
  66. return sizeof(struct dp_vdev_be);
  67. case DP_CONTEXT_TYPE_PEER:
  68. return sizeof(struct dp_peer_be);
  69. default:
  70. return 0;
  71. }
  72. }
  73. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  74. qdf_size_t dp_mon_get_context_size_be(enum dp_context_type context_type)
  75. {
  76. switch (context_type) {
  77. case DP_CONTEXT_TYPE_MON_SOC:
  78. return sizeof(struct dp_mon_soc_be);
  79. case DP_CONTEXT_TYPE_MON_PDEV:
  80. return sizeof(struct dp_mon_pdev_be);
  81. default:
  82. return 0;
  83. }
  84. }
  85. #else
  86. qdf_size_t dp_mon_get_context_size_be(enum dp_context_type context_type)
  87. {
  88. switch (context_type) {
  89. case DP_CONTEXT_TYPE_MON_SOC:
  90. return sizeof(struct dp_mon_soc);
  91. case DP_CONTEXT_TYPE_MON_PDEV:
  92. return sizeof(struct dp_mon_pdev);
  93. default:
  94. return 0;
  95. }
  96. }
  97. #endif
  98. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  99. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  100. /**
  101. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  102. per wbm2sw ring
  103. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  104. *
  105. * Return: None
  106. */
  107. static inline
  108. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  109. {
  110. cc_cfg->wbm2sw6_cc_en = 1;
  111. cc_cfg->wbm2sw5_cc_en = 1;
  112. cc_cfg->wbm2sw4_cc_en = 1;
  113. cc_cfg->wbm2sw3_cc_en = 1;
  114. cc_cfg->wbm2sw2_cc_en = 1;
  115. /* disable wbm2sw1 hw cc as it's for FW */
  116. cc_cfg->wbm2sw1_cc_en = 0;
  117. cc_cfg->wbm2sw0_cc_en = 1;
  118. cc_cfg->wbm2fw_cc_en = 0;
  119. }
  120. #else
  121. static inline
  122. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  123. {
  124. cc_cfg->wbm2sw6_cc_en = 1;
  125. cc_cfg->wbm2sw5_cc_en = 1;
  126. cc_cfg->wbm2sw4_cc_en = 1;
  127. cc_cfg->wbm2sw3_cc_en = 1;
  128. cc_cfg->wbm2sw2_cc_en = 1;
  129. cc_cfg->wbm2sw1_cc_en = 1;
  130. cc_cfg->wbm2sw0_cc_en = 1;
  131. cc_cfg->wbm2fw_cc_en = 0;
  132. }
  133. #endif
  134. /**
  135. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  136. conversion register
  137. * @soc: SOC handle
  138. * @is_4k_align: page address 4k alignd
  139. *
  140. * Return: None
  141. */
  142. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  143. bool is_4k_align)
  144. {
  145. struct hal_hw_cc_config cc_cfg = { 0 };
  146. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  147. if (soc->cdp_soc.ol_ops->get_con_mode &&
  148. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  149. return;
  150. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  151. dp_info("INI skip HW CC register setting");
  152. return;
  153. }
  154. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  155. cc_cfg.cc_global_en = true;
  156. cc_cfg.page_4k_align = is_4k_align;
  157. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  158. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  159. /* 36th bit should be 1 then HW know this is CMEM address */
  160. cc_cfg.lut_base_addr_39_32 = 0x10;
  161. cc_cfg.error_path_cookie_conv_en = true;
  162. cc_cfg.release_path_cookie_conv_en = true;
  163. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  164. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  165. }
  166. /**
  167. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  168. * @hal_soc_hdl: HAL SOC handle
  169. * @offset: CMEM address
  170. * @value: value to write
  171. *
  172. * Return: None.
  173. */
  174. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  175. uint32_t offset,
  176. uint32_t value)
  177. {
  178. hal_cmem_write(hal_soc_hdl, offset, value);
  179. }
  180. /**
  181. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  182. HW cookie conversion
  183. * @soc: SOC handle
  184. * @cc_ctx: cookie conversion context pointer
  185. *
  186. * Return: 0 in case of success, else error value
  187. */
  188. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  189. {
  190. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  191. dp_info("cmem base 0x%llx, size 0x%llx",
  192. soc->cmem_base, soc->cmem_size);
  193. /* get CMEM for cookie conversion */
  194. if (soc->cmem_size < DP_CC_PPT_MEM_SIZE) {
  195. dp_err("cmem_size %llu bytes < 4K", soc->cmem_size);
  196. return QDF_STATUS_E_RESOURCES;
  197. }
  198. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  199. DP_CC_MEM_OFFSET_IN_CMEM);
  200. return QDF_STATUS_SUCCESS;
  201. }
  202. #else
  203. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  204. bool is_4k_align) {}
  205. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  206. uint32_t offset,
  207. uint32_t value)
  208. { }
  209. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  210. {
  211. return QDF_STATUS_SUCCESS;
  212. }
  213. #endif
  214. QDF_STATUS
  215. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  216. struct dp_hw_cookie_conversion_t *cc_ctx,
  217. uint32_t num_descs,
  218. enum dp_desc_type desc_type,
  219. uint8_t desc_pool_id)
  220. {
  221. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  222. uint32_t num_spt_pages, i = 0;
  223. struct dp_spt_page_desc *spt_desc;
  224. struct qdf_mem_dma_page_t *dma_page;
  225. uint8_t chip_id;
  226. /* estimate how many SPT DDR pages needed */
  227. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  228. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  229. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  230. dp_info("num_spt_pages needed %d", num_spt_pages);
  231. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  232. &cc_ctx->page_pool, qdf_page_size,
  233. num_spt_pages, 0, false);
  234. if (!cc_ctx->page_pool.dma_pages) {
  235. dp_err("spt ddr pages allocation failed");
  236. return QDF_STATUS_E_RESOURCES;
  237. }
  238. cc_ctx->page_desc_base = qdf_mem_malloc(
  239. num_spt_pages * sizeof(struct dp_spt_page_desc));
  240. if (!cc_ctx->page_desc_base) {
  241. dp_err("spt page descs allocation failed");
  242. goto fail_0;
  243. }
  244. chip_id = dp_mlo_get_chip_id(soc);
  245. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  246. desc_type);
  247. /* initial page desc */
  248. spt_desc = cc_ctx->page_desc_base;
  249. dma_page = cc_ctx->page_pool.dma_pages;
  250. while (i < num_spt_pages) {
  251. /* check if page address 4K aligned */
  252. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  253. dp_err("non-4k aligned pages addr %pK",
  254. (void *)dma_page[i].page_p_addr);
  255. goto fail_1;
  256. }
  257. spt_desc[i].page_v_addr =
  258. dma_page[i].page_v_addr_start;
  259. spt_desc[i].page_p_addr =
  260. dma_page[i].page_p_addr;
  261. i++;
  262. }
  263. cc_ctx->total_page_num = num_spt_pages;
  264. qdf_spinlock_create(&cc_ctx->cc_lock);
  265. return QDF_STATUS_SUCCESS;
  266. fail_1:
  267. qdf_mem_free(cc_ctx->page_desc_base);
  268. fail_0:
  269. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  270. &cc_ctx->page_pool, 0, false);
  271. return QDF_STATUS_E_FAILURE;
  272. }
  273. QDF_STATUS
  274. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  275. struct dp_hw_cookie_conversion_t *cc_ctx)
  276. {
  277. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  278. qdf_mem_free(cc_ctx->page_desc_base);
  279. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  280. &cc_ctx->page_pool, 0, false);
  281. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  282. return QDF_STATUS_SUCCESS;
  283. }
  284. QDF_STATUS
  285. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  286. struct dp_hw_cookie_conversion_t *cc_ctx)
  287. {
  288. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  289. uint32_t i = 0;
  290. struct dp_spt_page_desc *spt_desc;
  291. uint32_t ppt_index;
  292. uint32_t ppt_id_start;
  293. if (!cc_ctx->total_page_num) {
  294. dp_err("total page num is 0");
  295. return QDF_STATUS_E_INVAL;
  296. }
  297. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  298. spt_desc = cc_ctx->page_desc_base;
  299. while (i < cc_ctx->total_page_num) {
  300. /* write page PA to CMEM */
  301. dp_hw_cc_cmem_write(soc->hal_soc,
  302. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  303. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  304. (spt_desc[i].page_p_addr >>
  305. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  306. ppt_index = ppt_id_start + i;
  307. spt_desc[i].ppt_index = ppt_index;
  308. be_soc->page_desc_base[ppt_index].page_v_addr =
  309. spt_desc[i].page_v_addr;
  310. i++;
  311. }
  312. return QDF_STATUS_SUCCESS;
  313. }
  314. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  315. QDF_STATUS
  316. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  317. struct dp_hw_cookie_conversion_t *cc_ctx)
  318. {
  319. uint32_t ppt_index;
  320. struct dp_spt_page_desc *spt_desc;
  321. int i = 0;
  322. spt_desc = cc_ctx->page_desc_base;
  323. while (i < cc_ctx->total_page_num) {
  324. ppt_index = spt_desc[i].ppt_index;
  325. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  326. i++;
  327. }
  328. return QDF_STATUS_SUCCESS;
  329. }
  330. #else
  331. QDF_STATUS
  332. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  333. struct dp_hw_cookie_conversion_t *cc_ctx)
  334. {
  335. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  336. uint32_t ppt_index;
  337. struct dp_spt_page_desc *spt_desc;
  338. int i = 0;
  339. spt_desc = cc_ctx->page_desc_base;
  340. while (i < cc_ctx->total_page_num) {
  341. /* reset PA in CMEM to NULL */
  342. dp_hw_cc_cmem_write(soc->hal_soc,
  343. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  344. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  345. 0);
  346. ppt_index = spt_desc[i].ppt_index;
  347. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  348. i++;
  349. }
  350. return QDF_STATUS_SUCCESS;
  351. }
  352. #endif
  353. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  354. {
  355. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  356. int i = 0;
  357. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  358. dp_hw_cookie_conversion_detach(be_soc,
  359. &be_soc->tx_cc_ctx[i]);
  360. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  361. dp_hw_cookie_conversion_detach(be_soc,
  362. &be_soc->rx_cc_ctx[i]);
  363. qdf_mem_free(be_soc->page_desc_base);
  364. be_soc->page_desc_base = NULL;
  365. return QDF_STATUS_SUCCESS;
  366. }
  367. #ifdef WLAN_MLO_MULTI_CHIP
  368. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  369. {
  370. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  371. qdf_mem_set(be_vdev->partner_vdev_list,
  372. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  373. CDP_INVALID_VDEV_ID);
  374. }
  375. #else
  376. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  377. {
  378. }
  379. #endif
  380. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  381. struct cdp_soc_attach_params *params)
  382. {
  383. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  384. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  385. uint32_t max_tx_rx_desc_num, num_spt_pages;
  386. uint32_t num_entries;
  387. int i = 0;
  388. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  389. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
  390. /* estimate how many SPT DDR pages needed */
  391. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  392. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  393. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  394. be_soc->page_desc_base = qdf_mem_malloc(
  395. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  396. if (!be_soc->page_desc_base) {
  397. dp_err("spt page descs allocation failed");
  398. return QDF_STATUS_E_NOMEM;
  399. }
  400. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  401. qdf_status = dp_hw_cc_cmem_addr_init(soc);
  402. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  403. goto fail;
  404. dp_soc_mlo_fill_params(soc, params);
  405. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  406. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  407. qdf_status =
  408. dp_hw_cookie_conversion_attach(be_soc,
  409. &be_soc->tx_cc_ctx[i],
  410. num_entries,
  411. DP_TX_DESC_TYPE, i);
  412. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  413. goto fail;
  414. }
  415. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  416. num_entries =
  417. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  418. qdf_status =
  419. dp_hw_cookie_conversion_attach(be_soc,
  420. &be_soc->rx_cc_ctx[i],
  421. num_entries,
  422. DP_RX_DESC_BUF_TYPE, i);
  423. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  424. goto fail;
  425. }
  426. return qdf_status;
  427. fail:
  428. dp_soc_detach_be(soc);
  429. return qdf_status;
  430. }
  431. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  432. {
  433. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  434. int i = 0;
  435. dp_tx_deinit_bank_profiles(be_soc);
  436. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  437. dp_hw_cookie_conversion_deinit(be_soc,
  438. &be_soc->tx_cc_ctx[i]);
  439. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  440. dp_hw_cookie_conversion_deinit(be_soc,
  441. &be_soc->rx_cc_ctx[i]);
  442. return QDF_STATUS_SUCCESS;
  443. }
  444. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  445. {
  446. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  447. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  448. int i = 0;
  449. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  450. qdf_status =
  451. dp_hw_cookie_conversion_init(be_soc,
  452. &be_soc->tx_cc_ctx[i]);
  453. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  454. goto fail;
  455. }
  456. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  457. qdf_status =
  458. dp_hw_cookie_conversion_init(be_soc,
  459. &be_soc->rx_cc_ctx[i]);
  460. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  461. goto fail;
  462. }
  463. /* route vdev_id mismatch notification via FW completion */
  464. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  465. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  466. qdf_status = dp_tx_init_bank_profiles(be_soc);
  467. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  468. goto fail;
  469. /* write WBM/REO cookie conversion CFG register */
  470. dp_cc_reg_cfg_init(soc, true);
  471. return qdf_status;
  472. fail:
  473. dp_soc_deinit_be(soc);
  474. return qdf_status;
  475. }
  476. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  477. struct cdp_pdev_attach_params *params)
  478. {
  479. dp_pdev_mlo_fill_params(pdev, params);
  480. return QDF_STATUS_SUCCESS;
  481. }
  482. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  483. {
  484. return QDF_STATUS_SUCCESS;
  485. }
  486. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  487. {
  488. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  489. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  490. struct dp_pdev *pdev = vdev->pdev;
  491. if (vdev->opmode == wlan_op_mode_monitor)
  492. return QDF_STATUS_SUCCESS;
  493. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  494. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  495. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  496. QDF_BUG(0);
  497. return QDF_STATUS_E_FAULT;
  498. }
  499. if (vdev->opmode == wlan_op_mode_sta) {
  500. if (soc->cdp_soc.ol_ops->set_mec_timer)
  501. soc->cdp_soc.ol_ops->set_mec_timer(
  502. soc->ctrl_psoc,
  503. vdev->vdev_id,
  504. DP_AST_AGING_TIMER_DEFAULT_MS);
  505. if (pdev->isolation)
  506. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  507. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  508. else
  509. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  510. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  511. }
  512. dp_mlo_init_ptnr_list(vdev);
  513. return QDF_STATUS_SUCCESS;
  514. }
  515. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  516. {
  517. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  518. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  519. if (vdev->opmode == wlan_op_mode_monitor)
  520. return QDF_STATUS_SUCCESS;
  521. dp_tx_put_bank_profile(be_soc, be_vdev);
  522. dp_clr_mlo_ptnr_list(soc, vdev);
  523. return QDF_STATUS_SUCCESS;
  524. }
  525. qdf_size_t dp_get_soc_context_size_be(void)
  526. {
  527. return sizeof(struct dp_soc_be);
  528. }
  529. #ifdef NO_RX_PKT_HDR_TLV
  530. /**
  531. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  532. * @soc: Common DP soc handle
  533. *
  534. * Return: QDF_STATUS
  535. */
  536. static QDF_STATUS
  537. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  538. {
  539. int i;
  540. int mac_id;
  541. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  542. struct dp_srng *rx_mac_srng;
  543. QDF_STATUS status = QDF_STATUS_SUCCESS;
  544. /*
  545. * In Beryllium chipset msdu_start, mpdu_end
  546. * and rx_attn are part of msdu_end/mpdu_start
  547. */
  548. htt_tlv_filter.msdu_start = 0;
  549. htt_tlv_filter.mpdu_end = 0;
  550. htt_tlv_filter.attention = 0;
  551. htt_tlv_filter.mpdu_start = 1;
  552. htt_tlv_filter.msdu_end = 1;
  553. htt_tlv_filter.packet = 1;
  554. htt_tlv_filter.packet_header = 1;
  555. htt_tlv_filter.ppdu_start = 0;
  556. htt_tlv_filter.ppdu_end = 0;
  557. htt_tlv_filter.ppdu_end_user_stats = 0;
  558. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  559. htt_tlv_filter.ppdu_end_status_done = 0;
  560. htt_tlv_filter.enable_fp = 1;
  561. htt_tlv_filter.enable_md = 0;
  562. htt_tlv_filter.enable_md = 0;
  563. htt_tlv_filter.enable_mo = 0;
  564. htt_tlv_filter.fp_mgmt_filter = 0;
  565. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  566. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  567. FILTER_DATA_MCAST |
  568. FILTER_DATA_DATA);
  569. htt_tlv_filter.mo_mgmt_filter = 0;
  570. htt_tlv_filter.mo_ctrl_filter = 0;
  571. htt_tlv_filter.mo_data_filter = 0;
  572. htt_tlv_filter.md_data_filter = 0;
  573. htt_tlv_filter.offset_valid = true;
  574. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  575. htt_tlv_filter.rx_mpdu_end_offset = 0;
  576. htt_tlv_filter.rx_msdu_start_offset = 0;
  577. htt_tlv_filter.rx_attn_offset = 0;
  578. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  579. /*Not subscribing rx_pkt_header*/
  580. htt_tlv_filter.rx_header_offset = 0;
  581. htt_tlv_filter.rx_mpdu_start_offset =
  582. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  583. htt_tlv_filter.rx_msdu_end_offset =
  584. hal_rx_msdu_end_offset_get(soc->hal_soc);
  585. for (i = 0; i < MAX_PDEV_CNT; i++) {
  586. struct dp_pdev *pdev = soc->pdev_list[i];
  587. if (!pdev)
  588. continue;
  589. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  590. int mac_for_pdev =
  591. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  592. /*
  593. * Obtain lmac id from pdev to access the LMAC ring
  594. * in soc context
  595. */
  596. int lmac_id =
  597. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  598. pdev->pdev_id);
  599. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  600. if (!rx_mac_srng->hal_srng)
  601. continue;
  602. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  603. rx_mac_srng->hal_srng,
  604. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  605. &htt_tlv_filter);
  606. }
  607. }
  608. return status;
  609. }
  610. #else
  611. /**
  612. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  613. * @soc: Common DP soc handle
  614. *
  615. * Return: QDF_STATUS
  616. */
  617. static QDF_STATUS
  618. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  619. {
  620. int i;
  621. int mac_id;
  622. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  623. struct dp_srng *rx_mac_srng;
  624. QDF_STATUS status = QDF_STATUS_SUCCESS;
  625. /*
  626. * In Beryllium chipset msdu_start, mpdu_end
  627. * and rx_attn are part of msdu_end/mpdu_start
  628. */
  629. htt_tlv_filter.msdu_start = 0;
  630. htt_tlv_filter.mpdu_end = 0;
  631. htt_tlv_filter.attention = 0;
  632. htt_tlv_filter.mpdu_start = 1;
  633. htt_tlv_filter.msdu_end = 1;
  634. htt_tlv_filter.packet = 1;
  635. htt_tlv_filter.packet_header = 1;
  636. htt_tlv_filter.ppdu_start = 0;
  637. htt_tlv_filter.ppdu_end = 0;
  638. htt_tlv_filter.ppdu_end_user_stats = 0;
  639. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  640. htt_tlv_filter.ppdu_end_status_done = 0;
  641. htt_tlv_filter.enable_fp = 1;
  642. htt_tlv_filter.enable_md = 0;
  643. htt_tlv_filter.enable_md = 0;
  644. htt_tlv_filter.enable_mo = 0;
  645. htt_tlv_filter.fp_mgmt_filter = 0;
  646. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  647. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  648. FILTER_DATA_MCAST |
  649. FILTER_DATA_DATA);
  650. htt_tlv_filter.mo_mgmt_filter = 0;
  651. htt_tlv_filter.mo_ctrl_filter = 0;
  652. htt_tlv_filter.mo_data_filter = 0;
  653. htt_tlv_filter.md_data_filter = 0;
  654. htt_tlv_filter.offset_valid = true;
  655. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  656. htt_tlv_filter.rx_mpdu_end_offset = 0;
  657. htt_tlv_filter.rx_msdu_start_offset = 0;
  658. htt_tlv_filter.rx_attn_offset = 0;
  659. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  660. htt_tlv_filter.rx_header_offset =
  661. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  662. htt_tlv_filter.rx_mpdu_start_offset =
  663. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  664. htt_tlv_filter.rx_msdu_end_offset =
  665. hal_rx_msdu_end_offset_get(soc->hal_soc);
  666. dp_info("TLV subscription\n"
  667. "msdu_start %d, mpdu_end %d, attention %d"
  668. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  669. "TLV offsets\n"
  670. "msdu_start %d, mpdu_end %d, attention %d"
  671. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  672. htt_tlv_filter.msdu_start,
  673. htt_tlv_filter.mpdu_end,
  674. htt_tlv_filter.attention,
  675. htt_tlv_filter.mpdu_start,
  676. htt_tlv_filter.msdu_end,
  677. htt_tlv_filter.packet_header,
  678. htt_tlv_filter.packet,
  679. htt_tlv_filter.rx_msdu_start_offset,
  680. htt_tlv_filter.rx_mpdu_end_offset,
  681. htt_tlv_filter.rx_attn_offset,
  682. htt_tlv_filter.rx_mpdu_start_offset,
  683. htt_tlv_filter.rx_msdu_end_offset,
  684. htt_tlv_filter.rx_header_offset,
  685. htt_tlv_filter.rx_packet_offset);
  686. for (i = 0; i < MAX_PDEV_CNT; i++) {
  687. struct dp_pdev *pdev = soc->pdev_list[i];
  688. if (!pdev)
  689. continue;
  690. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  691. int mac_for_pdev =
  692. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  693. /*
  694. * Obtain lmac id from pdev to access the LMAC ring
  695. * in soc context
  696. */
  697. int lmac_id =
  698. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  699. pdev->pdev_id);
  700. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  701. if (!rx_mac_srng->hal_srng)
  702. continue;
  703. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  704. rx_mac_srng->hal_srng,
  705. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  706. &htt_tlv_filter);
  707. }
  708. }
  709. return status;
  710. }
  711. #endif
  712. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  713. /**
  714. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  715. * near-full IRQs.
  716. * @soc: Datapath SoC handle
  717. * @int_ctx: Interrupt context
  718. * @dp_budget: Budget of the work that can be done in the bottom half
  719. *
  720. * Return: work done in the handler
  721. */
  722. static uint32_t
  723. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  724. uint32_t dp_budget)
  725. {
  726. int ring = 0;
  727. int budget = dp_budget;
  728. uint32_t work_done = 0;
  729. uint32_t remaining_quota = dp_budget;
  730. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  731. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  732. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  733. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  734. int rx_near_full_mask = rx_near_full_grp_1_mask |
  735. rx_near_full_grp_2_mask;
  736. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  737. rx_near_full_mask,
  738. tx_ring_near_full_mask);
  739. if (rx_near_full_mask) {
  740. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  741. if (!(rx_near_full_mask & (1 << ring)))
  742. continue;
  743. work_done = dp_rx_nf_process(int_ctx,
  744. soc->reo_dest_ring[ring].hal_srng,
  745. ring, remaining_quota);
  746. if (work_done) {
  747. intr_stats->num_rx_ring_near_full_masks[ring]++;
  748. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  749. rx_near_full_mask, ring,
  750. work_done,
  751. budget);
  752. budget -= work_done;
  753. if (budget <= 0)
  754. goto budget_done;
  755. remaining_quota = budget;
  756. }
  757. }
  758. }
  759. if (tx_ring_near_full_mask) {
  760. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  761. if (!(tx_ring_near_full_mask & (1 << ring)))
  762. continue;
  763. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  764. soc->tx_comp_ring[ring].hal_srng,
  765. ring, remaining_quota);
  766. if (work_done) {
  767. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  768. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  769. tx_ring_near_full_mask, ring,
  770. work_done, budget);
  771. budget -= work_done;
  772. if (budget <= 0)
  773. break;
  774. remaining_quota = budget;
  775. }
  776. }
  777. }
  778. intr_stats->num_near_full_masks++;
  779. budget_done:
  780. return dp_budget - budget;
  781. }
  782. /**
  783. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  784. * state and set the reap_limit appropriately
  785. * as per the near full state
  786. * @soc: Datapath soc handle
  787. * @dp_srng: Datapath handle for SRNG
  788. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  789. * the srng near-full state
  790. *
  791. * Return: 1, if the srng is in near-full state
  792. * 0, if the srng is not in near-full state
  793. */
  794. static int
  795. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  796. struct dp_srng *dp_srng,
  797. int *max_reap_limit)
  798. {
  799. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  800. }
  801. /**
  802. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  803. * near full IRQ handling operations.
  804. * @arch_ops: arch ops handle
  805. *
  806. * Return: none
  807. */
  808. static inline void
  809. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  810. {
  811. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  812. arch_ops->dp_srng_test_and_update_nf_params =
  813. dp_srng_test_and_update_nf_params_be;
  814. }
  815. #else
  816. static inline void
  817. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  818. {
  819. }
  820. #endif
  821. #ifdef WLAN_SUPPORT_PPEDS
  822. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  823. {
  824. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  825. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  826. soc_cfg_ctx = soc->wlan_cfg_ctx;
  827. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  828. return;
  829. dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
  830. wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
  831. be_soc->ppe_release_ring.alloc_size,
  832. soc->ctrl_psoc,
  833. WLAN_MD_DP_SRNG_PPE_RELEASE,
  834. "ppe_release_ring");
  835. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  836. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  837. be_soc->ppe2tcl_ring.alloc_size,
  838. soc->ctrl_psoc,
  839. WLAN_MD_DP_SRNG_PPE2TCL,
  840. "ppe2tcl_ring");
  841. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  842. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  843. be_soc->reo2ppe_ring.alloc_size,
  844. soc->ctrl_psoc,
  845. WLAN_MD_DP_SRNG_REO2PPE,
  846. "reo2ppe_ring");
  847. }
  848. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  849. {
  850. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  851. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  852. soc_cfg_ctx = soc->wlan_cfg_ctx;
  853. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  854. return;
  855. dp_srng_free(soc, &be_soc->ppe_release_ring);
  856. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  857. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  858. }
  859. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  860. {
  861. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  862. uint32_t entries;
  863. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  864. soc_cfg_ctx = soc->wlan_cfg_ctx;
  865. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  866. return QDF_STATUS_SUCCESS;
  867. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  868. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  869. entries, 0)) {
  870. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  871. goto fail;
  872. }
  873. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  874. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  875. entries, 0)) {
  876. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  877. goto fail;
  878. }
  879. entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
  880. if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
  881. entries, 0)) {
  882. dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
  883. goto fail;
  884. }
  885. return QDF_STATUS_SUCCESS;
  886. fail:
  887. dp_soc_ppe_srng_free(soc);
  888. return QDF_STATUS_E_NOMEM;
  889. }
  890. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  891. {
  892. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  893. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  894. soc_cfg_ctx = soc->wlan_cfg_ctx;
  895. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  896. return QDF_STATUS_SUCCESS;
  897. if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
  898. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  899. goto fail;
  900. }
  901. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  902. be_soc->reo2ppe_ring.alloc_size,
  903. soc->ctrl_psoc,
  904. WLAN_MD_DP_SRNG_REO2PPE,
  905. "reo2ppe_ring");
  906. if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
  907. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  908. goto fail;
  909. }
  910. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  911. be_soc->ppe2tcl_ring.alloc_size,
  912. soc->ctrl_psoc,
  913. WLAN_MD_DP_SRNG_PPE2TCL,
  914. "ppe2tcl_ring");
  915. if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
  916. dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
  917. goto fail;
  918. }
  919. wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
  920. be_soc->ppe_release_ring.alloc_size,
  921. soc->ctrl_psoc,
  922. WLAN_MD_DP_SRNG_PPE_RELEASE,
  923. "ppe_release_ring");
  924. return QDF_STATUS_SUCCESS;
  925. fail:
  926. dp_soc_ppe_srng_deinit(soc);
  927. return QDF_STATUS_E_NOMEM;
  928. }
  929. #else
  930. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  931. {
  932. }
  933. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  934. {
  935. }
  936. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  937. {
  938. return QDF_STATUS_SUCCESS;
  939. }
  940. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  941. {
  942. return QDF_STATUS_SUCCESS;
  943. }
  944. #endif
  945. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  946. {
  947. uint32_t i;
  948. dp_soc_ppe_srng_deinit(soc);
  949. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  950. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  951. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  952. RXDMA_BUF, 0);
  953. }
  954. }
  955. }
  956. static void dp_soc_srng_free_be(struct dp_soc *soc)
  957. {
  958. uint32_t i;
  959. dp_soc_ppe_srng_free(soc);
  960. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  961. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  962. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  963. }
  964. }
  965. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  966. {
  967. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  968. uint32_t ring_size;
  969. uint32_t i;
  970. soc_cfg_ctx = soc->wlan_cfg_ctx;
  971. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  972. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  973. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  974. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  975. RXDMA_BUF, ring_size, 0)) {
  976. dp_err("%pK: dp_srng_alloc failed refill ring",
  977. soc);
  978. goto fail;
  979. }
  980. }
  981. }
  982. if (dp_soc_ppe_srng_alloc(soc)) {
  983. dp_err("%pK: ppe rings alloc failed",
  984. soc);
  985. goto fail;
  986. }
  987. return QDF_STATUS_SUCCESS;
  988. fail:
  989. dp_soc_srng_free_be(soc);
  990. return QDF_STATUS_E_NOMEM;
  991. }
  992. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  993. {
  994. int i = 0;
  995. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  996. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  997. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  998. RXDMA_BUF, 0, 0)) {
  999. dp_err("%pK: dp_srng_init failed refill ring",
  1000. soc);
  1001. goto fail;
  1002. }
  1003. }
  1004. }
  1005. if (dp_soc_ppe_srng_init(soc)) {
  1006. dp_err("%pK: ppe rings init failed",
  1007. soc);
  1008. goto fail;
  1009. }
  1010. return QDF_STATUS_SUCCESS;
  1011. fail:
  1012. dp_soc_srng_deinit_be(soc);
  1013. return QDF_STATUS_E_NOMEM;
  1014. }
  1015. #ifdef WLAN_FEATURE_11BE_MLO
  1016. static inline unsigned
  1017. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1018. union dp_align_mac_addr *mac_addr)
  1019. {
  1020. uint32_t index;
  1021. index =
  1022. mac_addr->align2.bytes_ab ^
  1023. mac_addr->align2.bytes_cd ^
  1024. mac_addr->align2.bytes_ef;
  1025. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1026. index &= mld_hash_obj->mld_peer_hash.mask;
  1027. return index;
  1028. }
  1029. QDF_STATUS
  1030. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1031. int hash_elems)
  1032. {
  1033. int i, log2;
  1034. if (!mld_hash_obj)
  1035. return QDF_STATUS_E_FAILURE;
  1036. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1037. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1038. log2 = dp_log2_ceil(hash_elems);
  1039. hash_elems = 1 << log2;
  1040. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1041. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1042. /* allocate an array of TAILQ peer object lists */
  1043. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1044. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1045. if (!mld_hash_obj->mld_peer_hash.bins)
  1046. return QDF_STATUS_E_NOMEM;
  1047. for (i = 0; i < hash_elems; i++)
  1048. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1049. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1050. return QDF_STATUS_SUCCESS;
  1051. }
  1052. void
  1053. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1054. {
  1055. if (!mld_hash_obj)
  1056. return;
  1057. if (mld_hash_obj->mld_peer_hash.bins) {
  1058. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1059. mld_hash_obj->mld_peer_hash.bins = NULL;
  1060. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1061. }
  1062. }
  1063. #ifdef WLAN_MLO_MULTI_CHIP
  1064. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1065. {
  1066. /* In case of MULTI chip MLO peer hash table when MLO global object
  1067. * is created, avoid from SOC attach path
  1068. */
  1069. return QDF_STATUS_SUCCESS;
  1070. }
  1071. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1072. {
  1073. }
  1074. #else
  1075. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1076. {
  1077. dp_mld_peer_hash_obj_t mld_hash_obj;
  1078. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1079. if (!mld_hash_obj)
  1080. return QDF_STATUS_E_FAILURE;
  1081. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1082. }
  1083. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1084. {
  1085. dp_mld_peer_hash_obj_t mld_hash_obj;
  1086. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1087. if (!mld_hash_obj)
  1088. return;
  1089. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1090. }
  1091. #endif
  1092. static struct dp_peer *
  1093. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1094. uint8_t *peer_mac_addr,
  1095. int mac_addr_is_aligned,
  1096. enum dp_mod_id mod_id)
  1097. {
  1098. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1099. uint32_t index;
  1100. struct dp_peer *peer;
  1101. dp_mld_peer_hash_obj_t mld_hash_obj;
  1102. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1103. if (!mld_hash_obj)
  1104. return NULL;
  1105. if (!mld_hash_obj->mld_peer_hash.bins)
  1106. return NULL;
  1107. if (mac_addr_is_aligned) {
  1108. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1109. } else {
  1110. qdf_mem_copy(
  1111. &local_mac_addr_aligned.raw[0],
  1112. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1113. mac_addr = &local_mac_addr_aligned;
  1114. }
  1115. /* search mld peer table if no link peer for given mac address */
  1116. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1117. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1118. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1119. hash_list_elem) {
  1120. /* do not check vdev ID for MLD peer */
  1121. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1122. /* take peer reference before returning */
  1123. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1124. QDF_STATUS_SUCCESS)
  1125. peer = NULL;
  1126. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1127. return peer;
  1128. }
  1129. }
  1130. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1131. return NULL; /* failure */
  1132. }
  1133. static void
  1134. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1135. {
  1136. uint32_t index;
  1137. struct dp_peer *tmppeer = NULL;
  1138. int found = 0;
  1139. dp_mld_peer_hash_obj_t mld_hash_obj;
  1140. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1141. if (!mld_hash_obj)
  1142. return;
  1143. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1144. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1145. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1146. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1147. hash_list_elem) {
  1148. if (tmppeer == peer) {
  1149. found = 1;
  1150. break;
  1151. }
  1152. }
  1153. QDF_ASSERT(found);
  1154. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1155. hash_list_elem);
  1156. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1157. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1158. }
  1159. static void
  1160. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1161. {
  1162. uint32_t index;
  1163. dp_mld_peer_hash_obj_t mld_hash_obj;
  1164. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1165. if (!mld_hash_obj)
  1166. return;
  1167. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1168. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1169. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1170. DP_MOD_ID_CONFIG))) {
  1171. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1172. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1173. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1174. return;
  1175. }
  1176. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1177. hash_list_elem);
  1178. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1179. }
  1180. #endif
  1181. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1182. defined(WLAN_MCAST_MLO)
  1183. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1184. struct dp_vdev_be *be_vdev,
  1185. cdp_config_param_type val)
  1186. {
  1187. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1188. }
  1189. #else
  1190. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1191. struct dp_vdev_be *be_vdev,
  1192. cdp_config_param_type val)
  1193. {
  1194. }
  1195. #endif
  1196. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1197. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1198. uint8_t tx_ring_id,
  1199. uint8_t bm_id)
  1200. {
  1201. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1202. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1203. bm_id);
  1204. }
  1205. #else
  1206. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1207. uint8_t tx_ring_id,
  1208. uint8_t bm_id)
  1209. {
  1210. }
  1211. #endif
  1212. #ifdef WLAN_MLO_MULTI_CHIP
  1213. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1214. struct cdp_peer_setup_info *setup_info,
  1215. enum cdp_host_reo_dest_ring *reo_dest,
  1216. bool *hash_based,
  1217. uint8_t *lmac_peer_id_msb)
  1218. {
  1219. struct dp_soc *soc = vdev->pdev->soc;
  1220. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1221. uint8_t default_rx_ring_id;
  1222. uint8_t chip_id;
  1223. if (!be_soc->mlo_enabled)
  1224. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  1225. hash_based);
  1226. chip_id = be_soc->mlo_chip_id;
  1227. default_rx_ring_id =
  1228. wlan_cfg_mlo_default_rx_ring_get_by_chip_id(soc->wlan_cfg_ctx,
  1229. chip_id);
  1230. *reo_dest = hal_reo_ring_remap_value_get_be(default_rx_ring_id);
  1231. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1232. *lmac_peer_id_msb =
  1233. wlan_cfg_mlo_lmac_peer_id_msb_get_by_chip_id(soc->wlan_cfg_ctx,
  1234. chip_id);
  1235. }
  1236. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1237. uint32_t *remap0,
  1238. uint32_t *remap1,
  1239. uint32_t *remap2)
  1240. {
  1241. uint8_t rx_ring_mask;
  1242. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1243. if (!be_soc->mlo_enabled)
  1244. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1245. rx_ring_mask =
  1246. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 0);
  1247. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1248. rx_ring_mask =
  1249. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 1);
  1250. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1251. rx_ring_mask =
  1252. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 2);
  1253. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1254. return true;
  1255. }
  1256. #else
  1257. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1258. struct cdp_peer_setup_info *setup_info,
  1259. enum cdp_host_reo_dest_ring *reo_dest,
  1260. bool *hash_based,
  1261. uint8_t *lmac_peer_id_msb)
  1262. {
  1263. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  1264. }
  1265. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1266. uint32_t *remap0,
  1267. uint32_t *remap1,
  1268. uint32_t *remap2)
  1269. {
  1270. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1271. }
  1272. #endif
  1273. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1274. struct dp_vdev *vdev,
  1275. enum cdp_vdev_param_type param,
  1276. cdp_config_param_type val)
  1277. {
  1278. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1279. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1280. switch (param) {
  1281. case CDP_TX_ENCAP_TYPE:
  1282. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1283. case CDP_UPDATE_TDLS_FLAGS:
  1284. dp_tx_update_bank_profile(be_soc, be_vdev);
  1285. break;
  1286. case CDP_ENABLE_CIPHER:
  1287. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1288. dp_tx_update_bank_profile(be_soc, be_vdev);
  1289. break;
  1290. case CDP_SET_MCAST_VDEV:
  1291. dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val);
  1292. break;
  1293. default:
  1294. dp_warn("invalid param %d", param);
  1295. break;
  1296. }
  1297. return QDF_STATUS_SUCCESS;
  1298. }
  1299. #ifdef WLAN_FEATURE_11BE_MLO
  1300. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1301. static inline void
  1302. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1303. {
  1304. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1305. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1306. /*
  1307. * Double the peers since we use ML indication bit
  1308. * alongwith peer_id to find peers.
  1309. */
  1310. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1311. }
  1312. #else
  1313. static inline void
  1314. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1315. {
  1316. soc->max_peer_id =
  1317. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1318. }
  1319. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1320. #else
  1321. static inline void
  1322. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1323. {
  1324. soc->max_peer_id = soc->max_peers;
  1325. }
  1326. #endif /* WLAN_FEATURE_11BE_MLO */
  1327. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1328. {
  1329. }
  1330. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1331. {
  1332. dp_soc_max_peer_id_set(soc);
  1333. return QDF_STATUS_SUCCESS;
  1334. }
  1335. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  1336. {
  1337. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1338. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  1339. arch_ops->dp_rx_process = dp_rx_process_be;
  1340. arch_ops->tx_comp_get_params_from_hal_desc =
  1341. dp_tx_comp_get_params_from_hal_desc_be;
  1342. arch_ops->dp_tx_process_htt_completion =
  1343. dp_tx_process_htt_completion_be;
  1344. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  1345. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  1346. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  1347. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  1348. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  1349. dp_wbm_get_rx_desc_from_hal_desc_be;
  1350. #endif
  1351. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  1352. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  1353. arch_ops->dp_rx_desc_cookie_2_va =
  1354. dp_rx_desc_cookie_2_va_be;
  1355. arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
  1356. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  1357. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  1358. arch_ops->txrx_soc_init = dp_soc_init_be;
  1359. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  1360. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  1361. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  1362. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  1363. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  1364. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  1365. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  1366. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  1367. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  1368. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  1369. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  1370. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  1371. arch_ops->dp_rx_peer_metadata_peer_id_get =
  1372. dp_rx_peer_metadata_peer_id_get_be;
  1373. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  1374. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  1375. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  1376. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  1377. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  1378. #ifdef WLAN_FEATURE_11BE_MLO
  1379. #ifdef WLAN_MCAST_MLO
  1380. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  1381. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  1382. #endif
  1383. arch_ops->mlo_peer_find_hash_detach =
  1384. dp_mlo_peer_find_hash_detach_wrapper;
  1385. arch_ops->mlo_peer_find_hash_attach =
  1386. dp_mlo_peer_find_hash_attach_wrapper;
  1387. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  1388. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  1389. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  1390. #endif
  1391. arch_ops->dp_peer_rx_reorder_queue_setup =
  1392. dp_peer_rx_reorder_queue_setup_be;
  1393. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  1394. dp_init_near_full_arch_ops_be(arch_ops);
  1395. }