sde_encoder_phys_wb.c 51 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  6. #include <linux/debugfs.h>
  7. #include <uapi/drm/sde_drm.h>
  8. #include "sde_encoder_phys.h"
  9. #include "sde_formats.h"
  10. #include "sde_hw_top.h"
  11. #include "sde_hw_interrupts.h"
  12. #include "sde_core_irq.h"
  13. #include "sde_wb.h"
  14. #include "sde_vbif.h"
  15. #include "sde_crtc.h"
  16. #define to_sde_encoder_phys_wb(x) \
  17. container_of(x, struct sde_encoder_phys_wb, base)
  18. #define WBID(wb_enc) \
  19. ((wb_enc && wb_enc->wb_dev) ? wb_enc->wb_dev->wb_idx - WB_0 : -1)
  20. #define TO_S15D16(_x_) ((_x_) << 7)
  21. static const u32 cwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, INTR_IDX_PP1_OVFL,
  22. INTR_IDX_PP2_OVFL, INTR_IDX_PP3_OVFL, INTR_IDX_PP4_OVFL,
  23. INTR_IDX_PP5_OVFL, SDE_NONE, SDE_NONE};
  24. /**
  25. * sde_rgb2yuv_601l - rgb to yuv color space conversion matrix
  26. *
  27. */
  28. static struct sde_csc_cfg sde_encoder_phys_wb_rgb2yuv_601l = {
  29. {
  30. TO_S15D16(0x0083), TO_S15D16(0x0102), TO_S15D16(0x0032),
  31. TO_S15D16(0x1fb5), TO_S15D16(0x1f6c), TO_S15D16(0x00e1),
  32. TO_S15D16(0x00e1), TO_S15D16(0x1f45), TO_S15D16(0x1fdc)
  33. },
  34. { 0x00, 0x00, 0x00 },
  35. { 0x0040, 0x0200, 0x0200 },
  36. { 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff },
  37. { 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 },
  38. };
  39. /**
  40. * sde_encoder_phys_wb_is_master - report wb always as master encoder
  41. */
  42. static bool sde_encoder_phys_wb_is_master(struct sde_encoder_phys *phys_enc)
  43. {
  44. return true;
  45. }
  46. /**
  47. * sde_encoder_phys_wb_get_intr_type - get interrupt type based on block mode
  48. * @hw_wb: Pointer to h/w writeback driver
  49. */
  50. static enum sde_intr_type sde_encoder_phys_wb_get_intr_type(
  51. struct sde_hw_wb *hw_wb)
  52. {
  53. return (hw_wb->caps->features & BIT(SDE_WB_BLOCK_MODE)) ?
  54. SDE_IRQ_TYPE_WB_ROT_COMP : SDE_IRQ_TYPE_WB_WFD_COMP;
  55. }
  56. /**
  57. * sde_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
  58. * @phys_enc: Pointer to physical encoder
  59. */
  60. static void sde_encoder_phys_wb_set_ot_limit(
  61. struct sde_encoder_phys *phys_enc)
  62. {
  63. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  64. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  65. struct sde_vbif_set_ot_params ot_params;
  66. memset(&ot_params, 0, sizeof(ot_params));
  67. ot_params.xin_id = hw_wb->caps->xin_id;
  68. ot_params.num = hw_wb->idx - WB_0;
  69. ot_params.width = wb_enc->wb_roi.w;
  70. ot_params.height = wb_enc->wb_roi.h;
  71. ot_params.is_wfd = true;
  72. ot_params.frame_rate = phys_enc->cached_mode.vrefresh;
  73. ot_params.vbif_idx = hw_wb->caps->vbif_idx;
  74. ot_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  75. ot_params.rd = false;
  76. sde_vbif_set_ot_limit(phys_enc->sde_kms, &ot_params);
  77. }
  78. /**
  79. * sde_encoder_phys_wb_set_traffic_shaper - set traffic shaper for writeback
  80. * @phys_enc: Pointer to physical encoder
  81. */
  82. static void sde_encoder_phys_wb_set_traffic_shaper(
  83. struct sde_encoder_phys *phys_enc)
  84. {
  85. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  86. struct sde_hw_wb_cfg *wb_cfg = &wb_enc->wb_cfg;
  87. /* traffic shaper is only enabled for rotator */
  88. wb_cfg->ts_cfg.en = false;
  89. }
  90. /**
  91. * sde_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
  92. * @phys_enc: Pointer to physical encoder
  93. */
  94. static void sde_encoder_phys_wb_set_qos_remap(
  95. struct sde_encoder_phys *phys_enc)
  96. {
  97. struct sde_encoder_phys_wb *wb_enc;
  98. struct sde_hw_wb *hw_wb;
  99. struct drm_crtc *crtc;
  100. struct sde_vbif_set_qos_params qos_params;
  101. if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
  102. SDE_ERROR("invalid arguments\n");
  103. return;
  104. }
  105. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  106. if (!wb_enc->crtc) {
  107. SDE_ERROR("invalid crtc");
  108. return;
  109. }
  110. crtc = wb_enc->crtc;
  111. if (!wb_enc->hw_wb || !wb_enc->hw_wb->caps) {
  112. SDE_ERROR("invalid writeback hardware\n");
  113. return;
  114. }
  115. hw_wb = wb_enc->hw_wb;
  116. memset(&qos_params, 0, sizeof(qos_params));
  117. qos_params.vbif_idx = hw_wb->caps->vbif_idx;
  118. qos_params.xin_id = hw_wb->caps->xin_id;
  119. qos_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  120. qos_params.num = hw_wb->idx - WB_0;
  121. qos_params.client_type = phys_enc->in_clone_mode ?
  122. VBIF_CWB_CLIENT : VBIF_NRT_CLIENT;
  123. SDE_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d clone:%d\n",
  124. qos_params.num,
  125. qos_params.vbif_idx,
  126. qos_params.xin_id, qos_params.client_type);
  127. sde_vbif_set_qos_remap(phys_enc->sde_kms, &qos_params);
  128. }
  129. static u64 _sde_encoder_phys_wb_get_qos_lut(const struct sde_qos_lut_tbl *tbl,
  130. u32 total_fl)
  131. {
  132. int i;
  133. if (!tbl || !tbl->nentry || !tbl->entries)
  134. return 0;
  135. for (i = 0; i < tbl->nentry; i++)
  136. if (total_fl <= tbl->entries[i].fl)
  137. return tbl->entries[i].lut;
  138. /* if last fl is zero, use as default */
  139. if (!tbl->entries[i-1].fl)
  140. return tbl->entries[i-1].lut;
  141. return 0;
  142. }
  143. /**
  144. * sde_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
  145. * @phys_enc: Pointer to physical encoder
  146. */
  147. static void sde_encoder_phys_wb_set_qos(struct sde_encoder_phys *phys_enc)
  148. {
  149. struct sde_encoder_phys_wb *wb_enc;
  150. struct sde_hw_wb *hw_wb;
  151. struct sde_hw_wb_qos_cfg qos_cfg;
  152. struct sde_mdss_cfg *catalog;
  153. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->sde_kms->catalog) {
  154. SDE_ERROR("invalid parameter(s)\n");
  155. return;
  156. }
  157. catalog = phys_enc->sde_kms->catalog;
  158. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  159. if (!wb_enc->hw_wb) {
  160. SDE_ERROR("invalid writeback hardware\n");
  161. return;
  162. }
  163. hw_wb = wb_enc->hw_wb;
  164. memset(&qos_cfg, 0, sizeof(struct sde_hw_wb_qos_cfg));
  165. qos_cfg.danger_safe_en = true;
  166. qos_cfg.danger_lut =
  167. catalog->perf.danger_lut_tbl[SDE_QOS_LUT_USAGE_NRT];
  168. if (phys_enc->in_clone_mode)
  169. qos_cfg.safe_lut = (u32) _sde_encoder_phys_wb_get_qos_lut(
  170. &catalog->perf.sfe_lut_tbl[SDE_QOS_LUT_USAGE_CWB], 0);
  171. else
  172. qos_cfg.safe_lut = (u32) _sde_encoder_phys_wb_get_qos_lut(
  173. &catalog->perf.sfe_lut_tbl[SDE_QOS_LUT_USAGE_NRT], 0);
  174. if (phys_enc->in_clone_mode)
  175. qos_cfg.creq_lut = _sde_encoder_phys_wb_get_qos_lut(
  176. &catalog->perf.qos_lut_tbl[SDE_QOS_LUT_USAGE_CWB], 0);
  177. else
  178. qos_cfg.creq_lut = _sde_encoder_phys_wb_get_qos_lut(
  179. &catalog->perf.qos_lut_tbl[SDE_QOS_LUT_USAGE_NRT], 0);
  180. if (hw_wb->ops.setup_danger_safe_lut)
  181. hw_wb->ops.setup_danger_safe_lut(hw_wb, &qos_cfg);
  182. if (hw_wb->ops.setup_creq_lut)
  183. hw_wb->ops.setup_creq_lut(hw_wb, &qos_cfg);
  184. if (hw_wb->ops.setup_qos_ctrl)
  185. hw_wb->ops.setup_qos_ctrl(hw_wb, &qos_cfg);
  186. }
  187. /**
  188. * sde_encoder_phys_setup_cdm - setup chroma down block
  189. * @phys_enc: Pointer to physical encoder
  190. * @fb: Pointer to output framebuffer
  191. * @format: Output format
  192. */
  193. void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc,
  194. struct drm_framebuffer *fb, const struct sde_format *format,
  195. struct sde_rect *wb_roi)
  196. {
  197. struct sde_hw_cdm *hw_cdm;
  198. struct sde_hw_cdm_cfg *cdm_cfg;
  199. struct sde_hw_pingpong *hw_pp;
  200. int ret;
  201. if (!phys_enc || !format)
  202. return;
  203. cdm_cfg = &phys_enc->cdm_cfg;
  204. hw_pp = phys_enc->hw_pp;
  205. hw_cdm = phys_enc->hw_cdm;
  206. if (!hw_cdm)
  207. return;
  208. if (!SDE_FORMAT_IS_YUV(format)) {
  209. SDE_DEBUG("[cdm_disable fmt:%x]\n",
  210. format->base.pixel_format);
  211. if (hw_cdm && hw_cdm->ops.disable)
  212. hw_cdm->ops.disable(hw_cdm);
  213. return;
  214. }
  215. memset(cdm_cfg, 0, sizeof(struct sde_hw_cdm_cfg));
  216. if (!wb_roi)
  217. return;
  218. cdm_cfg->output_width = wb_roi->w;
  219. cdm_cfg->output_height = wb_roi->h;
  220. cdm_cfg->output_fmt = format;
  221. cdm_cfg->output_type = CDM_CDWN_OUTPUT_WB;
  222. cdm_cfg->output_bit_depth = SDE_FORMAT_IS_DX(format) ?
  223. CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
  224. /* enable 10 bit logic */
  225. switch (cdm_cfg->output_fmt->chroma_sample) {
  226. case SDE_CHROMA_RGB:
  227. cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
  228. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  229. break;
  230. case SDE_CHROMA_H2V1:
  231. cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
  232. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  233. break;
  234. case SDE_CHROMA_420:
  235. cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
  236. cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
  237. break;
  238. case SDE_CHROMA_H1V2:
  239. default:
  240. SDE_ERROR("unsupported chroma sampling type\n");
  241. cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
  242. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  243. break;
  244. }
  245. SDE_DEBUG("[cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
  246. cdm_cfg->output_width,
  247. cdm_cfg->output_height,
  248. cdm_cfg->output_fmt->base.pixel_format,
  249. cdm_cfg->output_type,
  250. cdm_cfg->output_bit_depth,
  251. cdm_cfg->h_cdwn_type,
  252. cdm_cfg->v_cdwn_type);
  253. if (hw_cdm && hw_cdm->ops.setup_csc_data) {
  254. ret = hw_cdm->ops.setup_csc_data(hw_cdm,
  255. &sde_encoder_phys_wb_rgb2yuv_601l);
  256. if (ret < 0) {
  257. SDE_ERROR("failed to setup CSC %d\n", ret);
  258. return;
  259. }
  260. }
  261. if (hw_cdm && hw_cdm->ops.setup_cdwn) {
  262. ret = hw_cdm->ops.setup_cdwn(hw_cdm, cdm_cfg);
  263. if (ret < 0) {
  264. SDE_ERROR("failed to setup CDM %d\n", ret);
  265. return;
  266. }
  267. }
  268. if (hw_cdm && hw_pp && hw_cdm->ops.enable) {
  269. cdm_cfg->pp_id = hw_pp->idx;
  270. ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
  271. if (ret < 0) {
  272. SDE_ERROR("failed to enable CDM %d\n", ret);
  273. return;
  274. }
  275. }
  276. }
  277. /**
  278. * sde_encoder_phys_wb_setup_fb - setup output framebuffer
  279. * @phys_enc: Pointer to physical encoder
  280. * @fb: Pointer to output framebuffer
  281. * @wb_roi: Pointer to output region of interest
  282. */
  283. static void sde_encoder_phys_wb_setup_fb(struct sde_encoder_phys *phys_enc,
  284. struct drm_framebuffer *fb, struct sde_rect *wb_roi)
  285. {
  286. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  287. struct sde_hw_wb *hw_wb;
  288. struct sde_hw_wb_cfg *wb_cfg;
  289. struct sde_hw_wb_cdp_cfg *cdp_cfg;
  290. const struct msm_format *format;
  291. int ret;
  292. struct msm_gem_address_space *aspace;
  293. u32 fb_mode;
  294. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->sde_kms->catalog ||
  295. !phys_enc->connector) {
  296. SDE_ERROR("invalid encoder\n");
  297. return;
  298. }
  299. hw_wb = wb_enc->hw_wb;
  300. wb_cfg = &wb_enc->wb_cfg;
  301. cdp_cfg = &wb_enc->cdp_cfg;
  302. memset(wb_cfg, 0, sizeof(struct sde_hw_wb_cfg));
  303. wb_cfg->intf_mode = phys_enc->intf_mode;
  304. fb_mode = sde_connector_get_property(phys_enc->connector->state,
  305. CONNECTOR_PROP_FB_TRANSLATION_MODE);
  306. if (phys_enc->enable_state == SDE_ENC_DISABLING)
  307. wb_cfg->is_secure = false;
  308. else if (fb_mode == SDE_DRM_FB_SEC)
  309. wb_cfg->is_secure = true;
  310. else
  311. wb_cfg->is_secure = false;
  312. aspace = (wb_cfg->is_secure) ?
  313. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] :
  314. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE];
  315. SDE_DEBUG("[fb_secure:%d]\n", wb_cfg->is_secure);
  316. ret = msm_framebuffer_prepare(fb, aspace);
  317. if (ret) {
  318. SDE_ERROR("prep fb failed, %d\n", ret);
  319. return;
  320. }
  321. /* cache framebuffer for cleanup in writeback done */
  322. wb_enc->wb_fb = fb;
  323. wb_enc->wb_aspace = aspace;
  324. format = msm_framebuffer_format(fb);
  325. if (!format) {
  326. SDE_DEBUG("invalid format for fb\n");
  327. return;
  328. }
  329. wb_cfg->dest.format = sde_get_sde_format_ext(
  330. format->pixel_format,
  331. fb->modifier);
  332. if (!wb_cfg->dest.format) {
  333. /* this error should be detected during atomic_check */
  334. SDE_ERROR("failed to get format %x\n", format->pixel_format);
  335. return;
  336. }
  337. wb_cfg->roi = *wb_roi;
  338. if (hw_wb->caps->features & BIT(SDE_WB_XY_ROI_OFFSET)) {
  339. ret = sde_format_populate_layout(aspace, fb, &wb_cfg->dest);
  340. if (ret) {
  341. SDE_DEBUG("failed to populate layout %d\n", ret);
  342. return;
  343. }
  344. wb_cfg->dest.width = fb->width;
  345. wb_cfg->dest.height = fb->height;
  346. wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
  347. } else {
  348. ret = sde_format_populate_layout_with_roi(aspace, fb, wb_roi,
  349. &wb_cfg->dest);
  350. if (ret) {
  351. /* this error should be detected during atomic_check */
  352. SDE_DEBUG("failed to populate layout %d\n", ret);
  353. return;
  354. }
  355. }
  356. if ((wb_cfg->dest.format->fetch_planes == SDE_PLANE_PLANAR) &&
  357. (wb_cfg->dest.format->element[0] == C1_B_Cb))
  358. swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
  359. SDE_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
  360. wb_cfg->dest.plane_addr[0],
  361. wb_cfg->dest.plane_addr[1],
  362. wb_cfg->dest.plane_addr[2],
  363. wb_cfg->dest.plane_addr[3]);
  364. SDE_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
  365. wb_cfg->dest.plane_pitch[0],
  366. wb_cfg->dest.plane_pitch[1],
  367. wb_cfg->dest.plane_pitch[2],
  368. wb_cfg->dest.plane_pitch[3]);
  369. if (hw_wb->ops.setup_roi)
  370. hw_wb->ops.setup_roi(hw_wb, wb_cfg);
  371. if (hw_wb->ops.setup_outformat)
  372. hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
  373. if (hw_wb->ops.setup_cdp) {
  374. memset(cdp_cfg, 0, sizeof(struct sde_hw_wb_cdp_cfg));
  375. cdp_cfg->enable = phys_enc->sde_kms->catalog->perf.cdp_cfg
  376. [SDE_PERF_CDP_USAGE_NRT].wr_enable;
  377. cdp_cfg->ubwc_meta_enable =
  378. SDE_FORMAT_IS_UBWC(wb_cfg->dest.format);
  379. cdp_cfg->tile_amortize_enable =
  380. SDE_FORMAT_IS_UBWC(wb_cfg->dest.format) ||
  381. SDE_FORMAT_IS_TILE(wb_cfg->dest.format);
  382. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  383. hw_wb->ops.setup_cdp(hw_wb, cdp_cfg);
  384. }
  385. if (hw_wb->ops.setup_outaddress) {
  386. SDE_EVT32(hw_wb->idx,
  387. wb_cfg->dest.width,
  388. wb_cfg->dest.height,
  389. wb_cfg->dest.plane_addr[0],
  390. wb_cfg->dest.plane_size[0],
  391. wb_cfg->dest.plane_addr[1],
  392. wb_cfg->dest.plane_size[1],
  393. wb_cfg->dest.plane_addr[2],
  394. wb_cfg->dest.plane_size[2],
  395. wb_cfg->dest.plane_addr[3],
  396. wb_cfg->dest.plane_size[3]);
  397. hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
  398. }
  399. }
  400. static void _sde_encoder_phys_wb_setup_cwb(struct sde_encoder_phys *phys_enc,
  401. bool enable)
  402. {
  403. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  404. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  405. struct sde_hw_ctl *hw_ctl = phys_enc->hw_ctl;
  406. struct sde_crtc *crtc = to_sde_crtc(wb_enc->crtc);
  407. struct sde_hw_pingpong *hw_pp = phys_enc->hw_pp;
  408. bool need_merge = (crtc->num_mixers > 1);
  409. int i = 0;
  410. if (!phys_enc->in_clone_mode) {
  411. SDE_DEBUG("not in CWB mode. early return\n");
  412. return;
  413. }
  414. if (!hw_pp || !hw_ctl || !hw_wb || hw_pp->idx >= PINGPONG_MAX) {
  415. SDE_ERROR("invalid hw resources - return\n");
  416. return;
  417. }
  418. hw_ctl = crtc->mixers[0].hw_ctl;
  419. if (hw_ctl && hw_ctl->ops.setup_intf_cfg_v1 &&
  420. test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features)) {
  421. struct sde_hw_intf_cfg_v1 intf_cfg = { 0, };
  422. for (i = 0; i < crtc->num_mixers; i++)
  423. intf_cfg.cwb[intf_cfg.cwb_count++] =
  424. (enum sde_cwb)(hw_pp->idx + i);
  425. if (enable && hw_pp->merge_3d && (intf_cfg.merge_3d_count <
  426. MAX_MERGE_3D_PER_CTL_V1) && need_merge)
  427. intf_cfg.merge_3d[intf_cfg.merge_3d_count++] =
  428. hw_pp->merge_3d->idx;
  429. if (hw_pp->ops.setup_3d_mode)
  430. hw_pp->ops.setup_3d_mode(hw_pp, (enable && need_merge) ?
  431. BLEND_3D_H_ROW_INT : 0);
  432. if (hw_wb->ops.bind_pingpong_blk)
  433. hw_wb->ops.bind_pingpong_blk(hw_wb, enable, hw_pp->idx);
  434. if (hw_ctl->ops.update_cwb_cfg) {
  435. hw_ctl->ops.update_cwb_cfg(hw_ctl, &intf_cfg);
  436. SDE_DEBUG("in CWB mode on CTL_%d PP-%d merge3d:%d\n",
  437. hw_ctl->idx - CTL_0,
  438. hw_pp->idx - PINGPONG_0,
  439. hw_pp->merge_3d ?
  440. hw_pp->merge_3d->idx - MERGE_3D_0 : -1);
  441. }
  442. } else {
  443. struct sde_hw_intf_cfg *intf_cfg = &phys_enc->intf_cfg;
  444. memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
  445. intf_cfg->intf = SDE_NONE;
  446. intf_cfg->wb = hw_wb->idx;
  447. if (hw_ctl && hw_ctl->ops.update_wb_cfg) {
  448. hw_ctl->ops.update_wb_cfg(hw_ctl, intf_cfg, enable);
  449. SDE_DEBUG("in CWB mode adding WB for CTL_%d\n",
  450. hw_ctl->idx - CTL_0);
  451. }
  452. }
  453. }
  454. /**
  455. * sde_encoder_phys_wb_setup_cdp - setup chroma down prefetch block
  456. * @phys_enc: Pointer to physical encoder
  457. */
  458. static void sde_encoder_phys_wb_setup_cdp(struct sde_encoder_phys *phys_enc,
  459. const struct sde_format *format)
  460. {
  461. struct sde_encoder_phys_wb *wb_enc;
  462. struct sde_hw_wb *hw_wb;
  463. struct sde_hw_cdm *hw_cdm;
  464. struct sde_hw_ctl *ctl;
  465. const int num_wb = 1;
  466. if (!phys_enc) {
  467. SDE_ERROR("invalid encoder\n");
  468. return;
  469. }
  470. if (phys_enc->in_clone_mode) {
  471. SDE_DEBUG("in CWB mode. early return\n");
  472. return;
  473. }
  474. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  475. hw_wb = wb_enc->hw_wb;
  476. hw_cdm = phys_enc->hw_cdm;
  477. ctl = phys_enc->hw_ctl;
  478. if (test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&
  479. (phys_enc->hw_ctl &&
  480. phys_enc->hw_ctl->ops.setup_intf_cfg_v1)) {
  481. struct sde_hw_intf_cfg_v1 *intf_cfg_v1 = &phys_enc->intf_cfg_v1;
  482. struct sde_hw_pingpong *hw_pp = phys_enc->hw_pp;
  483. enum sde_3d_blend_mode mode_3d;
  484. memset(intf_cfg_v1, 0, sizeof(struct sde_hw_intf_cfg_v1));
  485. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  486. intf_cfg_v1->intf_count = SDE_NONE;
  487. intf_cfg_v1->wb_count = num_wb;
  488. intf_cfg_v1->wb[0] = hw_wb->idx;
  489. if (SDE_FORMAT_IS_YUV(format)) {
  490. intf_cfg_v1->cdm_count = num_wb;
  491. intf_cfg_v1->cdm[0] = hw_cdm->idx;
  492. }
  493. if (mode_3d && hw_pp && hw_pp->merge_3d &&
  494. intf_cfg_v1->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  495. intf_cfg_v1->merge_3d[intf_cfg_v1->merge_3d_count++] =
  496. hw_pp->merge_3d->idx;
  497. if (hw_pp && hw_pp->ops.setup_3d_mode)
  498. hw_pp->ops.setup_3d_mode(hw_pp, mode_3d);
  499. /* setup which pp blk will connect to this wb */
  500. if (hw_pp && hw_wb->ops.bind_pingpong_blk)
  501. hw_wb->ops.bind_pingpong_blk(hw_wb, true,
  502. hw_pp->idx);
  503. phys_enc->hw_ctl->ops.setup_intf_cfg_v1(phys_enc->hw_ctl,
  504. intf_cfg_v1);
  505. } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
  506. struct sde_hw_intf_cfg *intf_cfg = &phys_enc->intf_cfg;
  507. memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
  508. intf_cfg->intf = SDE_NONE;
  509. intf_cfg->wb = hw_wb->idx;
  510. intf_cfg->mode_3d =
  511. sde_encoder_helper_get_3d_blend_mode(phys_enc);
  512. phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl,
  513. intf_cfg);
  514. }
  515. }
  516. static void _sde_enc_phys_wb_detect_cwb(struct sde_encoder_phys *phys_enc,
  517. struct drm_crtc_state *crtc_state)
  518. {
  519. struct drm_encoder *encoder;
  520. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  521. const struct sde_wb_cfg *wb_cfg = wb_enc->hw_wb->caps;
  522. phys_enc->in_clone_mode = false;
  523. /* Check if WB has CWB support */
  524. if (!(wb_cfg->features & BIT(SDE_WB_HAS_CWB)))
  525. return;
  526. /* if any other encoder is connected to same crtc enable clone mode*/
  527. drm_for_each_encoder(encoder, crtc_state->crtc->dev) {
  528. if (encoder->crtc != crtc_state->crtc)
  529. continue;
  530. if (phys_enc->parent != encoder) {
  531. phys_enc->in_clone_mode = true;
  532. break;
  533. }
  534. }
  535. SDE_DEBUG("detect CWB - status:%d\n", phys_enc->in_clone_mode);
  536. }
  537. static int _sde_enc_phys_wb_validate_cwb(struct sde_encoder_phys *phys_enc,
  538. struct drm_crtc_state *crtc_state,
  539. struct drm_connector_state *conn_state)
  540. {
  541. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc_state);
  542. struct sde_rect wb_roi = {0,};
  543. struct sde_rect pu_roi = {0,};
  544. int data_pt;
  545. int ds_outw = 0;
  546. int ds_outh = 0;
  547. int ds_in_use = false;
  548. int i = 0;
  549. int ret = 0;
  550. if (!phys_enc->in_clone_mode) {
  551. SDE_DEBUG("not in CWB mode. early return\n");
  552. goto exit;
  553. }
  554. ret = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
  555. if (ret) {
  556. SDE_ERROR("failed to get roi %d\n", ret);
  557. goto exit;
  558. }
  559. data_pt = sde_crtc_get_property(cstate, CRTC_PROP_CAPTURE_OUTPUT);
  560. /* compute cumulative ds output dimensions if in use */
  561. for (i = 0; i < cstate->num_ds; i++)
  562. if (cstate->ds_cfg[i].scl3_cfg.enable) {
  563. ds_in_use = true;
  564. ds_outw += cstate->ds_cfg[i].scl3_cfg.dst_width;
  565. ds_outh = cstate->ds_cfg[i].scl3_cfg.dst_height;
  566. }
  567. /* if ds in use check wb roi against ds output dimensions */
  568. if ((data_pt == CAPTURE_DSPP_OUT) && ds_in_use &&
  569. ((wb_roi.w != ds_outw) || (wb_roi.h != ds_outh))) {
  570. SDE_ERROR("invalid wb roi with dest scalar [%dx%d vs %dx%d]\n",
  571. wb_roi.w, wb_roi.h, ds_outw, ds_outh);
  572. ret = -EINVAL;
  573. goto exit;
  574. }
  575. /* validate conn roi against pu rect */
  576. if (cstate->user_roi_list.num_rects) {
  577. sde_kms_rect_merge_rectangles(&cstate->user_roi_list, &pu_roi);
  578. if (wb_roi.w != pu_roi.w || wb_roi.h != pu_roi.h) {
  579. SDE_ERROR("invalid wb roi with pu [%dx%d vs %dx%d]\n",
  580. wb_roi.w, wb_roi.h, pu_roi.w, pu_roi.h);
  581. ret = -EINVAL;
  582. goto exit;
  583. }
  584. }
  585. exit:
  586. return ret;
  587. }
  588. /**
  589. * sde_encoder_phys_wb_atomic_check - verify and fixup given atomic states
  590. * @phys_enc: Pointer to physical encoder
  591. * @crtc_state: Pointer to CRTC atomic state
  592. * @conn_state: Pointer to connector atomic state
  593. */
  594. static int sde_encoder_phys_wb_atomic_check(
  595. struct sde_encoder_phys *phys_enc,
  596. struct drm_crtc_state *crtc_state,
  597. struct drm_connector_state *conn_state)
  598. {
  599. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  600. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  601. const struct sde_wb_cfg *wb_cfg = hw_wb->caps;
  602. struct drm_framebuffer *fb;
  603. const struct sde_format *fmt;
  604. struct sde_rect wb_roi;
  605. const struct drm_display_mode *mode = &crtc_state->mode;
  606. int rc;
  607. SDE_DEBUG("[atomic_check:%d,%d,\"%s\",%d,%d]\n",
  608. hw_wb->idx - WB_0, mode->base.id, mode->name,
  609. mode->hdisplay, mode->vdisplay);
  610. if (!conn_state || !conn_state->connector) {
  611. SDE_ERROR("invalid connector state\n");
  612. return -EINVAL;
  613. } else if (conn_state->connector->status !=
  614. connector_status_connected) {
  615. SDE_ERROR("connector not connected %d\n",
  616. conn_state->connector->status);
  617. return -EINVAL;
  618. }
  619. _sde_enc_phys_wb_detect_cwb(phys_enc, crtc_state);
  620. memset(&wb_roi, 0, sizeof(struct sde_rect));
  621. rc = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
  622. if (rc) {
  623. SDE_ERROR("failed to get roi %d\n", rc);
  624. return rc;
  625. }
  626. SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi.x, wb_roi.y,
  627. wb_roi.w, wb_roi.h);
  628. /* bypass check if commit with no framebuffer */
  629. fb = sde_wb_connector_state_get_output_fb(conn_state);
  630. if (!fb) {
  631. SDE_DEBUG("no output framebuffer\n");
  632. return 0;
  633. }
  634. SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
  635. fb->width, fb->height);
  636. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  637. if (!fmt) {
  638. SDE_ERROR("unsupported output pixel format:%x\n",
  639. fb->format->format);
  640. return -EINVAL;
  641. }
  642. SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->format->format,
  643. fb->modifier);
  644. if (SDE_FORMAT_IS_YUV(fmt) &&
  645. !(wb_cfg->features & BIT(SDE_WB_YUV_CONFIG))) {
  646. SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
  647. return -EINVAL;
  648. }
  649. if (SDE_FORMAT_IS_UBWC(fmt) &&
  650. !(wb_cfg->features & BIT(SDE_WB_UBWC))) {
  651. SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
  652. return -EINVAL;
  653. }
  654. if (SDE_FORMAT_IS_YUV(fmt) != !!phys_enc->hw_cdm)
  655. crtc_state->mode_changed = true;
  656. if (wb_roi.w && wb_roi.h) {
  657. if (wb_roi.w != mode->hdisplay) {
  658. SDE_ERROR("invalid roi w=%d, mode w=%d\n", wb_roi.w,
  659. mode->hdisplay);
  660. return -EINVAL;
  661. } else if (wb_roi.h != mode->vdisplay) {
  662. SDE_ERROR("invalid roi h=%d, mode h=%d\n", wb_roi.h,
  663. mode->vdisplay);
  664. return -EINVAL;
  665. } else if (wb_roi.x + wb_roi.w > fb->width) {
  666. SDE_ERROR("invalid roi x=%d, w=%d, fb w=%d\n",
  667. wb_roi.x, wb_roi.w, fb->width);
  668. return -EINVAL;
  669. } else if (wb_roi.y + wb_roi.h > fb->height) {
  670. SDE_ERROR("invalid roi y=%d, h=%d, fb h=%d\n",
  671. wb_roi.y, wb_roi.h, fb->height);
  672. return -EINVAL;
  673. } else if (wb_roi.w > wb_cfg->sblk->maxlinewidth) {
  674. SDE_ERROR("invalid roi w=%d, maxlinewidth=%u\n",
  675. wb_roi.w, wb_cfg->sblk->maxlinewidth);
  676. return -EINVAL;
  677. }
  678. } else {
  679. if (wb_roi.x || wb_roi.y) {
  680. SDE_ERROR("invalid roi x=%d, y=%d\n",
  681. wb_roi.x, wb_roi.y);
  682. return -EINVAL;
  683. } else if (fb->width != mode->hdisplay) {
  684. SDE_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
  685. mode->hdisplay);
  686. return -EINVAL;
  687. } else if (fb->height != mode->vdisplay) {
  688. SDE_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
  689. mode->vdisplay);
  690. return -EINVAL;
  691. } else if (fb->width > wb_cfg->sblk->maxlinewidth) {
  692. SDE_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
  693. fb->width, wb_cfg->sblk->maxlinewidth);
  694. return -EINVAL;
  695. }
  696. }
  697. rc = _sde_enc_phys_wb_validate_cwb(phys_enc, crtc_state, conn_state);
  698. if (rc) {
  699. SDE_ERROR("failed in cwb validation %d\n", rc);
  700. return rc;
  701. }
  702. return rc;
  703. }
  704. static void _sde_encoder_phys_wb_update_cwb_flush(
  705. struct sde_encoder_phys *phys_enc)
  706. {
  707. struct sde_encoder_phys_wb *wb_enc;
  708. struct sde_hw_wb *hw_wb;
  709. struct sde_hw_ctl *hw_ctl;
  710. struct sde_hw_cdm *hw_cdm;
  711. struct sde_hw_pingpong *hw_pp;
  712. struct sde_crtc *crtc;
  713. struct sde_crtc_state *crtc_state;
  714. int i = 0;
  715. int cwb_capture_mode = 0;
  716. enum sde_cwb cwb_idx = 0;
  717. enum sde_cwb src_pp_idx = 0;
  718. bool dspp_out = false;
  719. bool need_merge = false;
  720. if (!phys_enc->in_clone_mode) {
  721. SDE_DEBUG("not in CWB mode. early return\n");
  722. return;
  723. }
  724. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  725. crtc = to_sde_crtc(wb_enc->crtc);
  726. crtc_state = to_sde_crtc_state(wb_enc->crtc->state);
  727. cwb_capture_mode = sde_crtc_get_property(crtc_state,
  728. CRTC_PROP_CAPTURE_OUTPUT);
  729. hw_pp = phys_enc->hw_pp;
  730. hw_wb = wb_enc->hw_wb;
  731. hw_cdm = phys_enc->hw_cdm;
  732. /* In CWB mode, program actual source master sde_hw_ctl from crtc */
  733. hw_ctl = crtc->mixers[0].hw_ctl;
  734. if (!hw_ctl || !hw_wb || !hw_pp) {
  735. SDE_ERROR("[wb] HW resource not available for CWB\n");
  736. return;
  737. }
  738. /* treating LM idx of primary display ctl path as source ping-pong idx*/
  739. src_pp_idx = (enum sde_cwb)crtc->mixers[0].hw_lm->idx;
  740. cwb_idx = (enum sde_cwb)hw_pp->idx;
  741. dspp_out = (cwb_capture_mode == CAPTURE_DSPP_OUT);
  742. need_merge = (crtc->num_mixers > 1) ? true : false;
  743. if (src_pp_idx > CWB_0 || ((cwb_idx + crtc->num_mixers) > CWB_MAX)) {
  744. SDE_ERROR("invalid hw config for CWB\n");
  745. return;
  746. }
  747. if (hw_ctl->ops.update_bitmask_wb)
  748. hw_ctl->ops.update_bitmask_wb(hw_ctl, hw_wb->idx, 1);
  749. if (hw_ctl->ops.update_bitmask_cdm && hw_cdm)
  750. hw_ctl->ops.update_bitmask_cdm(hw_ctl, hw_cdm->idx, 1);
  751. if (test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features)) {
  752. for (i = 0; i < crtc->num_mixers; i++) {
  753. cwb_idx = (enum sde_cwb) (hw_pp->idx + i);
  754. src_pp_idx = (enum sde_cwb) (src_pp_idx + i);
  755. if (hw_wb->ops.program_cwb_ctrl)
  756. hw_wb->ops.program_cwb_ctrl(hw_wb, cwb_idx,
  757. src_pp_idx, dspp_out);
  758. if (hw_ctl->ops.update_bitmask_cwb)
  759. hw_ctl->ops.update_bitmask_cwb(hw_ctl,
  760. cwb_idx, 1);
  761. }
  762. if (need_merge && hw_ctl->ops.update_bitmask_merge3d
  763. && hw_pp && hw_pp->merge_3d)
  764. hw_ctl->ops.update_bitmask_merge3d(hw_ctl,
  765. hw_pp->merge_3d->idx, 1);
  766. } else {
  767. phys_enc->hw_mdptop->ops.set_cwb_ppb_cntl(phys_enc->hw_mdptop,
  768. need_merge, dspp_out);
  769. }
  770. }
  771. /**
  772. * _sde_encoder_phys_wb_update_flush - flush hardware update
  773. * @phys_enc: Pointer to physical encoder
  774. */
  775. static void _sde_encoder_phys_wb_update_flush(struct sde_encoder_phys *phys_enc)
  776. {
  777. struct sde_encoder_phys_wb *wb_enc;
  778. struct sde_hw_wb *hw_wb;
  779. struct sde_hw_ctl *hw_ctl;
  780. struct sde_hw_cdm *hw_cdm;
  781. struct sde_hw_pingpong *hw_pp;
  782. struct sde_ctl_flush_cfg pending_flush = {0,};
  783. if (!phys_enc)
  784. return;
  785. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  786. hw_wb = wb_enc->hw_wb;
  787. hw_cdm = phys_enc->hw_cdm;
  788. hw_pp = phys_enc->hw_pp;
  789. hw_ctl = phys_enc->hw_ctl;
  790. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  791. if (phys_enc->in_clone_mode) {
  792. SDE_DEBUG("in CWB mode. early return\n");
  793. return;
  794. }
  795. if (!hw_ctl) {
  796. SDE_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
  797. return;
  798. }
  799. if (hw_ctl->ops.update_bitmask_wb)
  800. hw_ctl->ops.update_bitmask_wb(hw_ctl, hw_wb->idx, 1);
  801. if (hw_ctl->ops.update_bitmask_cdm && hw_cdm)
  802. hw_ctl->ops.update_bitmask_cdm(hw_ctl, hw_cdm->idx, 1);
  803. if (hw_ctl->ops.update_bitmask_merge3d && hw_pp && hw_pp->merge_3d)
  804. hw_ctl->ops.update_bitmask_merge3d(hw_ctl,
  805. hw_pp->merge_3d->idx, 1);
  806. if (hw_ctl->ops.get_pending_flush)
  807. hw_ctl->ops.get_pending_flush(hw_ctl,
  808. &pending_flush);
  809. SDE_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
  810. hw_ctl->idx - CTL_0, pending_flush.pending_flush_mask,
  811. hw_wb->idx - WB_0);
  812. }
  813. /**
  814. * sde_encoder_phys_wb_setup - setup writeback encoder
  815. * @phys_enc: Pointer to physical encoder
  816. */
  817. static void sde_encoder_phys_wb_setup(
  818. struct sde_encoder_phys *phys_enc)
  819. {
  820. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  821. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  822. struct drm_display_mode mode = phys_enc->cached_mode;
  823. struct drm_framebuffer *fb;
  824. struct sde_rect *wb_roi = &wb_enc->wb_roi;
  825. SDE_DEBUG("[mode_set:%d,%d,\"%s\",%d,%d]\n",
  826. hw_wb->idx - WB_0, mode.base.id, mode.name,
  827. mode.hdisplay, mode.vdisplay);
  828. memset(wb_roi, 0, sizeof(struct sde_rect));
  829. /* clear writeback framebuffer - will be updated in setup_fb */
  830. wb_enc->wb_fb = NULL;
  831. wb_enc->wb_aspace = NULL;
  832. if (phys_enc->enable_state == SDE_ENC_DISABLING) {
  833. fb = wb_enc->fb_disable;
  834. wb_roi->w = 0;
  835. wb_roi->h = 0;
  836. } else {
  837. fb = sde_wb_get_output_fb(wb_enc->wb_dev);
  838. sde_wb_get_output_roi(wb_enc->wb_dev, wb_roi);
  839. }
  840. if (!fb) {
  841. SDE_DEBUG("no output framebuffer\n");
  842. return;
  843. }
  844. SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
  845. fb->width, fb->height);
  846. if (wb_roi->w == 0 || wb_roi->h == 0) {
  847. wb_roi->x = 0;
  848. wb_roi->y = 0;
  849. wb_roi->w = fb->width;
  850. wb_roi->h = fb->height;
  851. }
  852. SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi->x, wb_roi->y,
  853. wb_roi->w, wb_roi->h);
  854. wb_enc->wb_fmt = sde_get_sde_format_ext(fb->format->format,
  855. fb->modifier);
  856. if (!wb_enc->wb_fmt) {
  857. SDE_ERROR("unsupported output pixel format: %d\n",
  858. fb->format->format);
  859. return;
  860. }
  861. SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->format->format,
  862. fb->modifier);
  863. sde_encoder_phys_wb_set_ot_limit(phys_enc);
  864. sde_encoder_phys_wb_set_traffic_shaper(phys_enc);
  865. sde_encoder_phys_wb_set_qos_remap(phys_enc);
  866. sde_encoder_phys_wb_set_qos(phys_enc);
  867. sde_encoder_phys_setup_cdm(phys_enc, fb, wb_enc->wb_fmt, wb_roi);
  868. sde_encoder_phys_wb_setup_fb(phys_enc, fb, wb_roi);
  869. sde_encoder_phys_wb_setup_cdp(phys_enc, wb_enc->wb_fmt);
  870. _sde_encoder_phys_wb_setup_cwb(phys_enc, true);
  871. }
  872. static void _sde_encoder_phys_wb_frame_done_helper(void *arg, bool frame_error)
  873. {
  874. struct sde_encoder_phys_wb *wb_enc = arg;
  875. struct sde_encoder_phys *phys_enc = &wb_enc->base;
  876. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  877. u32 event = frame_error ? SDE_ENCODER_FRAME_EVENT_ERROR : 0;
  878. event |= SDE_ENCODER_FRAME_EVENT_DONE |
  879. SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE;
  880. SDE_DEBUG("[wb:%d,%u]\n", hw_wb->idx - WB_0, wb_enc->frame_count);
  881. /* don't notify upper layer for internal commit */
  882. if (phys_enc->enable_state == SDE_ENC_DISABLING)
  883. goto complete;
  884. if (!phys_enc->in_clone_mode)
  885. event |= SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  886. atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0);
  887. if (phys_enc->parent_ops.handle_frame_done)
  888. phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
  889. phys_enc, event);
  890. if (phys_enc->parent_ops.handle_vblank_virt)
  891. phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
  892. phys_enc);
  893. SDE_EVT32_IRQ(DRMID(phys_enc->parent), hw_wb->idx - WB_0, event);
  894. complete:
  895. complete_all(&wb_enc->wbdone_complete);
  896. }
  897. /**
  898. * sde_encoder_phys_wb_done_irq - Pingpong overflow interrupt handler for CWB
  899. * @arg: Pointer to writeback encoder
  900. * @irq_idx: interrupt index
  901. */
  902. static void sde_encoder_phys_cwb_ovflow(void *arg, int irq_idx)
  903. {
  904. _sde_encoder_phys_wb_frame_done_helper(arg, true);
  905. }
  906. /**
  907. * sde_encoder_phys_wb_done_irq - writeback interrupt handler
  908. * @arg: Pointer to writeback encoder
  909. * @irq_idx: interrupt index
  910. */
  911. static void sde_encoder_phys_wb_done_irq(void *arg, int irq_idx)
  912. {
  913. _sde_encoder_phys_wb_frame_done_helper(arg, false);
  914. }
  915. /**
  916. * sde_encoder_phys_wb_irq_ctrl - irq control of WB
  917. * @phys: Pointer to physical encoder
  918. * @enable: indicates enable or disable interrupts
  919. */
  920. static void sde_encoder_phys_wb_irq_ctrl(
  921. struct sde_encoder_phys *phys, bool enable)
  922. {
  923. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys);
  924. int index = 0, refcount;
  925. int ret = 0, pp = 0;
  926. if (!wb_enc)
  927. return;
  928. if (wb_enc->bypass_irqreg)
  929. return;
  930. pp = phys->hw_pp->idx - PINGPONG_0;
  931. if ((pp + CRTC_DUAL_MIXERS) >= PINGPONG_MAX) {
  932. SDE_ERROR("invalid pingpong index for WB or CWB\n");
  933. return;
  934. }
  935. refcount = atomic_read(&phys->wbirq_refcount);
  936. if (enable && atomic_inc_return(&phys->wbirq_refcount) == 1) {
  937. sde_encoder_helper_register_irq(phys, INTR_IDX_WB_DONE);
  938. if (ret)
  939. atomic_dec_return(&phys->wbirq_refcount);
  940. for (index = 0; index < CRTC_DUAL_MIXERS; index++)
  941. if (cwb_irq_tbl[index + pp] != SDE_NONE)
  942. sde_encoder_helper_register_irq(phys,
  943. cwb_irq_tbl[index + pp]);
  944. } else if (!enable &&
  945. atomic_dec_return(&phys->wbirq_refcount) == 0) {
  946. sde_encoder_helper_unregister_irq(phys, INTR_IDX_WB_DONE);
  947. if (ret)
  948. atomic_inc_return(&phys->wbirq_refcount);
  949. for (index = 0; index < CRTC_DUAL_MIXERS; index++)
  950. if (cwb_irq_tbl[index + pp] != SDE_NONE)
  951. sde_encoder_helper_unregister_irq(phys,
  952. cwb_irq_tbl[index + pp]);
  953. }
  954. }
  955. /**
  956. * sde_encoder_phys_wb_mode_set - set display mode
  957. * @phys_enc: Pointer to physical encoder
  958. * @mode: Pointer to requested display mode
  959. * @adj_mode: Pointer to adjusted display mode
  960. */
  961. static void sde_encoder_phys_wb_mode_set(
  962. struct sde_encoder_phys *phys_enc,
  963. struct drm_display_mode *mode,
  964. struct drm_display_mode *adj_mode)
  965. {
  966. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  967. struct sde_rm *rm = &phys_enc->sde_kms->rm;
  968. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  969. struct sde_rm_hw_iter iter;
  970. int i, instance;
  971. phys_enc->cached_mode = *adj_mode;
  972. instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
  973. SDE_DEBUG("[mode_set_cache:%d,%d,\"%s\",%d,%d]\n",
  974. hw_wb->idx - WB_0, mode->base.id,
  975. mode->name, mode->hdisplay, mode->vdisplay);
  976. phys_enc->hw_ctl = NULL;
  977. phys_enc->hw_cdm = NULL;
  978. /* Retrieve previously allocated HW Resources. CTL shouldn't fail */
  979. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
  980. for (i = 0; i <= instance; i++) {
  981. sde_rm_get_hw(rm, &iter);
  982. if (i == instance)
  983. phys_enc->hw_ctl = (struct sde_hw_ctl *) iter.hw;
  984. }
  985. if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
  986. SDE_ERROR("failed init ctl: %ld\n",
  987. (!phys_enc->hw_ctl) ?
  988. -EINVAL : PTR_ERR(phys_enc->hw_ctl));
  989. phys_enc->hw_ctl = NULL;
  990. return;
  991. }
  992. /* CDM is optional */
  993. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CDM);
  994. for (i = 0; i <= instance; i++) {
  995. sde_rm_get_hw(rm, &iter);
  996. if (i == instance)
  997. phys_enc->hw_cdm = (struct sde_hw_cdm *) iter.hw;
  998. }
  999. if (IS_ERR(phys_enc->hw_cdm)) {
  1000. SDE_ERROR("CDM required but not allocated: %ld\n",
  1001. PTR_ERR(phys_enc->hw_cdm));
  1002. phys_enc->hw_cdm = NULL;
  1003. }
  1004. }
  1005. /**
  1006. * sde_encoder_phys_wb_wait_for_commit_done - wait until request is committed
  1007. * @phys_enc: Pointer to physical encoder
  1008. */
  1009. static int sde_encoder_phys_wb_wait_for_commit_done(
  1010. struct sde_encoder_phys *phys_enc)
  1011. {
  1012. unsigned long ret;
  1013. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1014. u32 irq_status, event = 0;
  1015. u64 wb_time = 0;
  1016. int rc = 0;
  1017. int irq_idx = phys_enc->irq[INTR_IDX_WB_DONE].irq_idx;
  1018. u32 timeout = max_t(u32, wb_enc->wbdone_timeout, KICKOFF_TIMEOUT_MS);
  1019. /* Return EWOULDBLOCK since we know the wait isn't necessary */
  1020. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  1021. SDE_ERROR("encoder already disabled\n");
  1022. return -EWOULDBLOCK;
  1023. }
  1024. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
  1025. !!wb_enc->wb_fb);
  1026. /* signal completion if commit with no framebuffer */
  1027. if (!wb_enc->wb_fb) {
  1028. SDE_DEBUG("no output framebuffer\n");
  1029. _sde_encoder_phys_wb_frame_done_helper(wb_enc, false);
  1030. }
  1031. ret = wait_for_completion_timeout(&wb_enc->wbdone_complete,
  1032. msecs_to_jiffies(timeout));
  1033. if (!ret) {
  1034. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1035. wb_enc->frame_count);
  1036. irq_status = sde_core_irq_read(phys_enc->sde_kms,
  1037. irq_idx, true);
  1038. if (irq_status) {
  1039. SDE_DEBUG("wb:%d done but irq not triggered\n",
  1040. WBID(wb_enc));
  1041. _sde_encoder_phys_wb_frame_done_helper(wb_enc, false);
  1042. } else {
  1043. SDE_ERROR("wb:%d kickoff timed out\n",
  1044. WBID(wb_enc));
  1045. atomic_add_unless(
  1046. &phys_enc->pending_retire_fence_cnt, -1, 0);
  1047. event = SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE
  1048. | SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE
  1049. | SDE_ENCODER_FRAME_EVENT_ERROR;
  1050. if (phys_enc->parent_ops.handle_frame_done)
  1051. phys_enc->parent_ops.handle_frame_done(
  1052. phys_enc->parent, phys_enc, event);
  1053. rc = -ETIMEDOUT;
  1054. }
  1055. }
  1056. if (!rc)
  1057. wb_enc->end_time = ktime_get();
  1058. /* once operation is done, disable traffic shaper */
  1059. if (wb_enc->wb_cfg.ts_cfg.en && wb_enc->hw_wb &&
  1060. wb_enc->hw_wb->ops.setup_trafficshaper) {
  1061. wb_enc->wb_cfg.ts_cfg.en = false;
  1062. wb_enc->hw_wb->ops.setup_trafficshaper(
  1063. wb_enc->hw_wb, &wb_enc->wb_cfg);
  1064. }
  1065. /* remove vote for iommu/clk/bus */
  1066. wb_enc->frame_count++;
  1067. if (!rc) {
  1068. wb_time = (u64)ktime_to_us(wb_enc->end_time) -
  1069. (u64)ktime_to_us(wb_enc->start_time);
  1070. SDE_DEBUG("wb:%d took %llu us\n", WBID(wb_enc), wb_time);
  1071. }
  1072. /* cleanup writeback framebuffer */
  1073. if (wb_enc->wb_fb && wb_enc->wb_aspace) {
  1074. msm_framebuffer_cleanup(wb_enc->wb_fb, wb_enc->wb_aspace);
  1075. wb_enc->wb_fb = NULL;
  1076. wb_enc->wb_aspace = NULL;
  1077. }
  1078. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
  1079. wb_time, event, rc);
  1080. return rc;
  1081. }
  1082. /**
  1083. * sde_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
  1084. * @phys_enc: Pointer to physical encoder
  1085. * @params: kickoff parameters
  1086. * Returns: Zero on success
  1087. */
  1088. static int sde_encoder_phys_wb_prepare_for_kickoff(
  1089. struct sde_encoder_phys *phys_enc,
  1090. struct sde_encoder_kickoff_params *params)
  1091. {
  1092. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1093. SDE_DEBUG("[wb:%d,%u]\n", wb_enc->hw_wb->idx - WB_0,
  1094. wb_enc->kickoff_count);
  1095. reinit_completion(&wb_enc->wbdone_complete);
  1096. wb_enc->kickoff_count++;
  1097. /* set OT limit & enable traffic shaper */
  1098. sde_encoder_phys_wb_setup(phys_enc);
  1099. _sde_encoder_phys_wb_update_flush(phys_enc);
  1100. _sde_encoder_phys_wb_update_cwb_flush(phys_enc);
  1101. /* vote for iommu/clk/bus */
  1102. wb_enc->start_time = ktime_get();
  1103. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->kickoff_count);
  1104. return 0;
  1105. }
  1106. /**
  1107. * sde_encoder_phys_wb_trigger_flush - trigger flush processing
  1108. * @phys_enc: Pointer to physical encoder
  1109. */
  1110. static void sde_encoder_phys_wb_trigger_flush(struct sde_encoder_phys *phys_enc)
  1111. {
  1112. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1113. if (!phys_enc || !wb_enc->hw_wb) {
  1114. SDE_ERROR("invalid encoder\n");
  1115. return;
  1116. }
  1117. /*
  1118. * Bail out iff in CWB mode. In case of CWB, primary control-path
  1119. * which is actually driving would trigger the flush
  1120. */
  1121. if (phys_enc->in_clone_mode) {
  1122. SDE_DEBUG("in CWB mode. early return\n");
  1123. return;
  1124. }
  1125. SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
  1126. /* clear pending flush if commit with no framebuffer */
  1127. if (!wb_enc->wb_fb) {
  1128. SDE_DEBUG("no output framebuffer\n");
  1129. return;
  1130. }
  1131. sde_encoder_helper_trigger_flush(phys_enc);
  1132. }
  1133. /**
  1134. * sde_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
  1135. * @phys_enc: Pointer to physical encoder
  1136. */
  1137. static void sde_encoder_phys_wb_handle_post_kickoff(
  1138. struct sde_encoder_phys *phys_enc)
  1139. {
  1140. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1141. SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
  1142. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc));
  1143. }
  1144. /**
  1145. * _sde_encoder_phys_wb_init_internal_fb - create fb for internal commit
  1146. * @wb_enc: Pointer to writeback encoder
  1147. * @pixel_format: DRM pixel format
  1148. * @width: Desired fb width
  1149. * @height: Desired fb height
  1150. * @pitch: Desired fb pitch
  1151. */
  1152. static int _sde_encoder_phys_wb_init_internal_fb(
  1153. struct sde_encoder_phys_wb *wb_enc,
  1154. uint32_t pixel_format, uint32_t width,
  1155. uint32_t height, uint32_t pitch)
  1156. {
  1157. struct drm_device *dev;
  1158. struct drm_framebuffer *fb;
  1159. struct drm_mode_fb_cmd2 mode_cmd;
  1160. uint32_t size;
  1161. int nplanes, i, ret;
  1162. struct msm_gem_address_space *aspace;
  1163. if (!wb_enc || !wb_enc->base.parent || !wb_enc->base.sde_kms) {
  1164. SDE_ERROR("invalid params\n");
  1165. return -EINVAL;
  1166. }
  1167. aspace = wb_enc->base.sde_kms->aspace[SDE_IOMMU_DOMAIN_UNSECURE];
  1168. if (!aspace) {
  1169. SDE_ERROR("invalid address space\n");
  1170. return -EINVAL;
  1171. }
  1172. dev = wb_enc->base.sde_kms->dev;
  1173. if (!dev) {
  1174. SDE_ERROR("invalid dev\n");
  1175. return -EINVAL;
  1176. }
  1177. memset(&mode_cmd, 0, sizeof(mode_cmd));
  1178. mode_cmd.pixel_format = pixel_format;
  1179. mode_cmd.width = width;
  1180. mode_cmd.height = height;
  1181. mode_cmd.pitches[0] = pitch;
  1182. size = sde_format_get_framebuffer_size(pixel_format,
  1183. mode_cmd.width, mode_cmd.height,
  1184. mode_cmd.pitches, 0);
  1185. if (!size) {
  1186. SDE_DEBUG("not creating zero size buffer\n");
  1187. return -EINVAL;
  1188. }
  1189. /* allocate gem tracking object */
  1190. nplanes = drm_format_num_planes(pixel_format);
  1191. if (nplanes >= SDE_MAX_PLANES) {
  1192. SDE_ERROR("requested format has too many planes\n");
  1193. return -EINVAL;
  1194. }
  1195. wb_enc->bo_disable[0] = msm_gem_new(dev, size,
  1196. MSM_BO_SCANOUT | MSM_BO_WC);
  1197. if (IS_ERR_OR_NULL(wb_enc->bo_disable[0])) {
  1198. ret = PTR_ERR(wb_enc->bo_disable[0]);
  1199. wb_enc->bo_disable[0] = NULL;
  1200. SDE_ERROR("failed to create bo, %d\n", ret);
  1201. return ret;
  1202. }
  1203. for (i = 0; i < nplanes; ++i) {
  1204. wb_enc->bo_disable[i] = wb_enc->bo_disable[0];
  1205. mode_cmd.pitches[i] = width *
  1206. drm_format_plane_cpp(pixel_format, i);
  1207. }
  1208. fb = msm_framebuffer_init(dev, &mode_cmd, wb_enc->bo_disable);
  1209. if (IS_ERR_OR_NULL(fb)) {
  1210. ret = PTR_ERR(fb);
  1211. drm_gem_object_put(wb_enc->bo_disable[0]);
  1212. wb_enc->bo_disable[0] = NULL;
  1213. SDE_ERROR("failed to init fb, %d\n", ret);
  1214. return ret;
  1215. }
  1216. /* prepare the backing buffer now so that it's available later */
  1217. ret = msm_framebuffer_prepare(fb, aspace);
  1218. if (!ret)
  1219. wb_enc->fb_disable = fb;
  1220. return ret;
  1221. }
  1222. /**
  1223. * _sde_encoder_phys_wb_destroy_internal_fb - deconstruct internal fb
  1224. * @wb_enc: Pointer to writeback encoder
  1225. */
  1226. static void _sde_encoder_phys_wb_destroy_internal_fb(
  1227. struct sde_encoder_phys_wb *wb_enc)
  1228. {
  1229. if (!wb_enc)
  1230. return;
  1231. if (wb_enc->fb_disable) {
  1232. drm_framebuffer_unregister_private(wb_enc->fb_disable);
  1233. drm_framebuffer_remove(wb_enc->fb_disable);
  1234. wb_enc->fb_disable = NULL;
  1235. }
  1236. if (wb_enc->bo_disable[0]) {
  1237. drm_gem_object_put(wb_enc->bo_disable[0]);
  1238. wb_enc->bo_disable[0] = NULL;
  1239. }
  1240. }
  1241. /**
  1242. * sde_encoder_phys_wb_enable - enable writeback encoder
  1243. * @phys_enc: Pointer to physical encoder
  1244. */
  1245. static void sde_encoder_phys_wb_enable(struct sde_encoder_phys *phys_enc)
  1246. {
  1247. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1248. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1249. struct drm_device *dev;
  1250. struct drm_connector *connector;
  1251. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1252. if (!wb_enc->base.parent || !wb_enc->base.parent->dev) {
  1253. SDE_ERROR("invalid drm device\n");
  1254. return;
  1255. }
  1256. dev = wb_enc->base.parent->dev;
  1257. /* find associated writeback connector */
  1258. connector = phys_enc->connector;
  1259. if (!connector || connector->encoder != phys_enc->parent) {
  1260. SDE_ERROR("failed to find writeback connector\n");
  1261. return;
  1262. }
  1263. wb_enc->wb_dev = sde_wb_connector_get_wb(connector);
  1264. phys_enc->enable_state = SDE_ENC_ENABLED;
  1265. /*
  1266. * cache the crtc in wb_enc on enable for duration of use case
  1267. * for correctly servicing asynchronous irq events and timers
  1268. */
  1269. wb_enc->crtc = phys_enc->parent->crtc;
  1270. }
  1271. /**
  1272. * sde_encoder_phys_wb_disable - disable writeback encoder
  1273. * @phys_enc: Pointer to physical encoder
  1274. */
  1275. static void sde_encoder_phys_wb_disable(struct sde_encoder_phys *phys_enc)
  1276. {
  1277. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1278. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1279. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1280. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  1281. SDE_ERROR("encoder is already disabled\n");
  1282. return;
  1283. }
  1284. if (wb_enc->frame_count != wb_enc->kickoff_count) {
  1285. SDE_DEBUG("[wait_for_done: wb:%d, frame:%u, kickoff:%u]\n",
  1286. hw_wb->idx - WB_0, wb_enc->frame_count,
  1287. wb_enc->kickoff_count);
  1288. sde_encoder_phys_wb_wait_for_commit_done(phys_enc);
  1289. }
  1290. if (!phys_enc->hw_ctl || !phys_enc->parent ||
  1291. !phys_enc->sde_kms || !wb_enc->fb_disable) {
  1292. SDE_DEBUG("invalid enc, skipping extra commit\n");
  1293. goto exit;
  1294. }
  1295. /* avoid reset frame for CWB */
  1296. if (phys_enc->in_clone_mode) {
  1297. _sde_encoder_phys_wb_setup_cwb(phys_enc, false);
  1298. phys_enc->in_clone_mode = false;
  1299. goto exit;
  1300. }
  1301. /* reset h/w before final flush */
  1302. if (phys_enc->hw_ctl->ops.clear_pending_flush)
  1303. phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
  1304. /*
  1305. * New CTL reset sequence from 5.0 MDP onwards.
  1306. * If has_3d_merge_reset is not set, legacy reset
  1307. * sequence is executed.
  1308. */
  1309. if (hw_wb->catalog->has_3d_merge_reset) {
  1310. sde_encoder_helper_phys_disable(phys_enc, wb_enc);
  1311. goto exit;
  1312. }
  1313. if (sde_encoder_helper_reset_mixers(phys_enc, NULL))
  1314. goto exit;
  1315. phys_enc->enable_state = SDE_ENC_DISABLING;
  1316. sde_encoder_phys_wb_prepare_for_kickoff(phys_enc, NULL);
  1317. sde_encoder_phys_wb_irq_ctrl(phys_enc, true);
  1318. if (phys_enc->hw_ctl->ops.trigger_flush)
  1319. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  1320. sde_encoder_helper_trigger_start(phys_enc);
  1321. sde_encoder_phys_wb_wait_for_commit_done(phys_enc);
  1322. sde_encoder_phys_wb_irq_ctrl(phys_enc, false);
  1323. exit:
  1324. phys_enc->enable_state = SDE_ENC_DISABLED;
  1325. wb_enc->crtc = NULL;
  1326. }
  1327. /**
  1328. * sde_encoder_phys_wb_get_hw_resources - get hardware resources
  1329. * @phys_enc: Pointer to physical encoder
  1330. * @hw_res: Pointer to encoder resources
  1331. */
  1332. static void sde_encoder_phys_wb_get_hw_resources(
  1333. struct sde_encoder_phys *phys_enc,
  1334. struct sde_encoder_hw_resources *hw_res,
  1335. struct drm_connector_state *conn_state)
  1336. {
  1337. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1338. struct sde_hw_wb *hw_wb;
  1339. struct drm_framebuffer *fb;
  1340. const struct sde_format *fmt = NULL;
  1341. if (!phys_enc) {
  1342. SDE_ERROR("invalid encoder\n");
  1343. return;
  1344. }
  1345. fb = sde_wb_connector_state_get_output_fb(conn_state);
  1346. if (fb) {
  1347. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  1348. if (!fmt) {
  1349. SDE_ERROR("unsupported output pixel format:%d\n",
  1350. fb->format->format);
  1351. return;
  1352. }
  1353. }
  1354. hw_wb = wb_enc->hw_wb;
  1355. hw_res->wbs[hw_wb->idx - WB_0] = phys_enc->intf_mode;
  1356. hw_res->needs_cdm = fmt ? SDE_FORMAT_IS_YUV(fmt) : false;
  1357. SDE_DEBUG("[wb:%d] intf_mode=%d needs_cdm=%d\n", hw_wb->idx - WB_0,
  1358. hw_res->wbs[hw_wb->idx - WB_0],
  1359. hw_res->needs_cdm);
  1360. }
  1361. #ifdef CONFIG_DEBUG_FS
  1362. /**
  1363. * sde_encoder_phys_wb_init_debugfs - initialize writeback encoder debugfs
  1364. * @phys_enc: Pointer to physical encoder
  1365. * @debugfs_root: Pointer to virtual encoder's debugfs_root dir
  1366. */
  1367. static int sde_encoder_phys_wb_init_debugfs(
  1368. struct sde_encoder_phys *phys_enc, struct dentry *debugfs_root)
  1369. {
  1370. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1371. if (!phys_enc || !wb_enc->hw_wb || !debugfs_root)
  1372. return -EINVAL;
  1373. if (!debugfs_create_u32("wbdone_timeout", 0600,
  1374. debugfs_root, &wb_enc->wbdone_timeout)) {
  1375. SDE_ERROR("failed to create debugfs/wbdone_timeout\n");
  1376. return -ENOMEM;
  1377. }
  1378. return 0;
  1379. }
  1380. #else
  1381. static int sde_encoder_phys_wb_init_debugfs(
  1382. struct sde_encoder_phys *phys_enc, struct dentry *debugfs_root)
  1383. {
  1384. return 0;
  1385. }
  1386. #endif
  1387. static int sde_encoder_phys_wb_late_register(struct sde_encoder_phys *phys_enc,
  1388. struct dentry *debugfs_root)
  1389. {
  1390. return sde_encoder_phys_wb_init_debugfs(phys_enc, debugfs_root);
  1391. }
  1392. /**
  1393. * sde_encoder_phys_wb_destroy - destroy writeback encoder
  1394. * @phys_enc: Pointer to physical encoder
  1395. */
  1396. static void sde_encoder_phys_wb_destroy(struct sde_encoder_phys *phys_enc)
  1397. {
  1398. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1399. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1400. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1401. if (!phys_enc)
  1402. return;
  1403. _sde_encoder_phys_wb_destroy_internal_fb(wb_enc);
  1404. kfree(wb_enc);
  1405. }
  1406. /**
  1407. * sde_encoder_phys_wb_init_ops - initialize writeback operations
  1408. * @ops: Pointer to encoder operation table
  1409. */
  1410. static void sde_encoder_phys_wb_init_ops(struct sde_encoder_phys_ops *ops)
  1411. {
  1412. ops->late_register = sde_encoder_phys_wb_late_register;
  1413. ops->is_master = sde_encoder_phys_wb_is_master;
  1414. ops->mode_set = sde_encoder_phys_wb_mode_set;
  1415. ops->enable = sde_encoder_phys_wb_enable;
  1416. ops->disable = sde_encoder_phys_wb_disable;
  1417. ops->destroy = sde_encoder_phys_wb_destroy;
  1418. ops->atomic_check = sde_encoder_phys_wb_atomic_check;
  1419. ops->get_hw_resources = sde_encoder_phys_wb_get_hw_resources;
  1420. ops->wait_for_commit_done = sde_encoder_phys_wb_wait_for_commit_done;
  1421. ops->prepare_for_kickoff = sde_encoder_phys_wb_prepare_for_kickoff;
  1422. ops->handle_post_kickoff = sde_encoder_phys_wb_handle_post_kickoff;
  1423. ops->trigger_flush = sde_encoder_phys_wb_trigger_flush;
  1424. ops->trigger_start = sde_encoder_helper_trigger_start;
  1425. ops->hw_reset = sde_encoder_helper_hw_reset;
  1426. ops->irq_control = sde_encoder_phys_wb_irq_ctrl;
  1427. }
  1428. /**
  1429. * sde_encoder_phys_wb_init - initialize writeback encoder
  1430. * @init: Pointer to init info structure with initialization params
  1431. */
  1432. struct sde_encoder_phys *sde_encoder_phys_wb_init(
  1433. struct sde_enc_phys_init_params *p)
  1434. {
  1435. struct sde_encoder_phys *phys_enc;
  1436. struct sde_encoder_phys_wb *wb_enc;
  1437. struct sde_hw_mdp *hw_mdp;
  1438. struct sde_encoder_irq *irq;
  1439. int ret = 0;
  1440. SDE_DEBUG("\n");
  1441. if (!p || !p->parent) {
  1442. SDE_ERROR("invalid params\n");
  1443. ret = -EINVAL;
  1444. goto fail_alloc;
  1445. }
  1446. wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL);
  1447. if (!wb_enc) {
  1448. SDE_ERROR("failed to allocate wb enc\n");
  1449. ret = -ENOMEM;
  1450. goto fail_alloc;
  1451. }
  1452. wb_enc->wbdone_timeout = KICKOFF_TIMEOUT_MS;
  1453. init_completion(&wb_enc->wbdone_complete);
  1454. phys_enc = &wb_enc->base;
  1455. if (p->sde_kms->vbif[VBIF_NRT]) {
  1456. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE] =
  1457. p->sde_kms->aspace[MSM_SMMU_DOMAIN_NRT_UNSECURE];
  1458. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] =
  1459. p->sde_kms->aspace[MSM_SMMU_DOMAIN_NRT_SECURE];
  1460. } else {
  1461. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE] =
  1462. p->sde_kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  1463. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] =
  1464. p->sde_kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  1465. }
  1466. hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
  1467. if (IS_ERR_OR_NULL(hw_mdp)) {
  1468. ret = PTR_ERR(hw_mdp);
  1469. SDE_ERROR("failed to init hw_top: %d\n", ret);
  1470. goto fail_mdp_init;
  1471. }
  1472. phys_enc->hw_mdptop = hw_mdp;
  1473. /**
  1474. * hw_wb resource permanently assigned to this encoder
  1475. * Other resources allocated at atomic commit time by use case
  1476. */
  1477. if (p->wb_idx != SDE_NONE) {
  1478. struct sde_rm_hw_iter iter;
  1479. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_WB);
  1480. while (sde_rm_get_hw(&p->sde_kms->rm, &iter)) {
  1481. struct sde_hw_wb *hw_wb = (struct sde_hw_wb *)iter.hw;
  1482. if (hw_wb->idx == p->wb_idx) {
  1483. wb_enc->hw_wb = hw_wb;
  1484. break;
  1485. }
  1486. }
  1487. if (!wb_enc->hw_wb) {
  1488. ret = -EINVAL;
  1489. SDE_ERROR("failed to init hw_wb%d\n", p->wb_idx - WB_0);
  1490. goto fail_wb_init;
  1491. }
  1492. } else {
  1493. ret = -EINVAL;
  1494. SDE_ERROR("invalid wb_idx\n");
  1495. goto fail_wb_check;
  1496. }
  1497. sde_encoder_phys_wb_init_ops(&phys_enc->ops);
  1498. phys_enc->parent = p->parent;
  1499. phys_enc->parent_ops = p->parent_ops;
  1500. phys_enc->sde_kms = p->sde_kms;
  1501. phys_enc->split_role = p->split_role;
  1502. phys_enc->intf_mode = INTF_MODE_WB_LINE;
  1503. phys_enc->intf_idx = p->intf_idx;
  1504. phys_enc->enc_spinlock = p->enc_spinlock;
  1505. phys_enc->vblank_ctl_lock = p->vblank_ctl_lock;
  1506. atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
  1507. atomic_set(&phys_enc->wbirq_refcount, 0);
  1508. irq = &phys_enc->irq[INTR_IDX_WB_DONE];
  1509. INIT_LIST_HEAD(&irq->cb.list);
  1510. irq->name = "wb_done";
  1511. irq->hw_idx = wb_enc->hw_wb->idx;
  1512. irq->irq_idx = -1;
  1513. irq->intr_type = sde_encoder_phys_wb_get_intr_type(wb_enc->hw_wb);
  1514. irq->intr_idx = INTR_IDX_WB_DONE;
  1515. irq->cb.arg = wb_enc;
  1516. irq->cb.func = sde_encoder_phys_wb_done_irq;
  1517. irq = &phys_enc->irq[INTR_IDX_PP1_OVFL];
  1518. INIT_LIST_HEAD(&irq->cb.list);
  1519. irq->name = "pp1_overflow";
  1520. irq->hw_idx = CWB_1;
  1521. irq->irq_idx = -1;
  1522. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1523. irq->intr_idx = INTR_IDX_PP1_OVFL;
  1524. irq->cb.arg = wb_enc;
  1525. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1526. irq = &phys_enc->irq[INTR_IDX_PP2_OVFL];
  1527. INIT_LIST_HEAD(&irq->cb.list);
  1528. irq->name = "pp2_overflow";
  1529. irq->hw_idx = CWB_2;
  1530. irq->irq_idx = -1;
  1531. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1532. irq->intr_idx = INTR_IDX_PP2_OVFL;
  1533. irq->cb.arg = wb_enc;
  1534. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1535. irq = &phys_enc->irq[INTR_IDX_PP3_OVFL];
  1536. INIT_LIST_HEAD(&irq->cb.list);
  1537. irq->name = "pp3_overflow";
  1538. irq->hw_idx = CWB_3;
  1539. irq->irq_idx = -1;
  1540. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1541. irq->intr_idx = INTR_IDX_PP3_OVFL;
  1542. irq->cb.arg = wb_enc;
  1543. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1544. irq = &phys_enc->irq[INTR_IDX_PP4_OVFL];
  1545. INIT_LIST_HEAD(&irq->cb.list);
  1546. irq->name = "pp4_overflow";
  1547. irq->hw_idx = CWB_4;
  1548. irq->irq_idx = -1;
  1549. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1550. irq->intr_idx = INTR_IDX_PP4_OVFL;
  1551. irq->cb.arg = wb_enc;
  1552. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1553. irq = &phys_enc->irq[INTR_IDX_PP5_OVFL];
  1554. INIT_LIST_HEAD(&irq->cb.list);
  1555. irq->name = "pp5_overflow";
  1556. irq->hw_idx = CWB_5;
  1557. irq->irq_idx = -1;
  1558. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1559. irq->intr_idx = INTR_IDX_PP5_OVFL;
  1560. irq->cb.arg = wb_enc;
  1561. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1562. /* create internal buffer for disable logic */
  1563. if (_sde_encoder_phys_wb_init_internal_fb(wb_enc,
  1564. DRM_FORMAT_RGB888, 2, 1, 6)) {
  1565. SDE_ERROR("failed to init internal fb\n");
  1566. goto fail_wb_init;
  1567. }
  1568. SDE_DEBUG("Created sde_encoder_phys_wb for wb %d\n",
  1569. wb_enc->hw_wb->idx - WB_0);
  1570. return phys_enc;
  1571. fail_wb_init:
  1572. fail_wb_check:
  1573. fail_mdp_init:
  1574. kfree(wb_enc);
  1575. fail_alloc:
  1576. return ERR_PTR(ret);
  1577. }