kona.c 187 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "asoc/msm-cdc-pinctrl.h"
  30. #include "asoc/wcd-mbhc-v2.h"
  31. #include "codecs/wcd938x/wcd938x-mbhc.h"
  32. #include "codecs/wsa881x.h"
  33. #include "codecs/wcd938x/wcd938x.h"
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include <dt-bindings/sound/audio-codec-port-types.h>
  36. #include "codecs/bolero/wsa-macro.h"
  37. #include "kona-port-config.h"
  38. #define DRV_NAME "kona-asoc-snd"
  39. #define __CHIPSET__ "KONA "
  40. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define WCD9XXX_MBHC_DEF_RLOADS 5
  55. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  56. #define CODEC_EXT_CLK_RATE 9600000
  57. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  58. #define DEV_NAME_STR_LEN 32
  59. #define WCD_MBHC_HS_V_MAX 1600
  60. #define TDM_CHANNEL_MAX 8
  61. #define DEV_NAME_STR_LEN 32
  62. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define WSA8810_NAME_1 "wsa881x.20170211"
  65. #define WSA8810_NAME_2 "wsa881x.20170212"
  66. #define WCN_CDC_SLIM_RX_CH_MAX 2
  67. #define WCN_CDC_SLIM_TX_CH_MAX 2
  68. #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3
  69. enum {
  70. TDM_0 = 0,
  71. TDM_1,
  72. TDM_2,
  73. TDM_3,
  74. TDM_4,
  75. TDM_5,
  76. TDM_6,
  77. TDM_7,
  78. TDM_PORT_MAX,
  79. };
  80. enum {
  81. TDM_PRI = 0,
  82. TDM_SEC,
  83. TDM_TERT,
  84. TDM_INTERFACE_MAX,
  85. };
  86. enum {
  87. PRIM_AUX_PCM = 0,
  88. SEC_AUX_PCM,
  89. TERT_AUX_PCM,
  90. AUX_PCM_MAX,
  91. };
  92. enum {
  93. PRIM_MI2S = 0,
  94. SEC_MI2S,
  95. TERT_MI2S,
  96. MI2S_MAX,
  97. };
  98. enum {
  99. WSA_CDC_DMA_RX_0 = 0,
  100. WSA_CDC_DMA_RX_1,
  101. RX_CDC_DMA_RX_0,
  102. RX_CDC_DMA_RX_1,
  103. RX_CDC_DMA_RX_2,
  104. RX_CDC_DMA_RX_3,
  105. RX_CDC_DMA_RX_5,
  106. CDC_DMA_RX_MAX,
  107. };
  108. enum {
  109. WSA_CDC_DMA_TX_0 = 0,
  110. WSA_CDC_DMA_TX_1,
  111. WSA_CDC_DMA_TX_2,
  112. TX_CDC_DMA_TX_0,
  113. TX_CDC_DMA_TX_3,
  114. TX_CDC_DMA_TX_4,
  115. VA_CDC_DMA_TX_0,
  116. VA_CDC_DMA_TX_1,
  117. VA_CDC_DMA_TX_2,
  118. CDC_DMA_TX_MAX,
  119. };
  120. enum {
  121. SLIM_RX_7 = 0,
  122. SLIM_RX_MAX,
  123. };
  124. enum {
  125. SLIM_TX_7 = 0,
  126. SLIM_TX_8,
  127. SLIM_TX_MAX,
  128. };
  129. enum {
  130. AFE_LOOPBACK_TX_IDX = 0,
  131. AFE_LOOPBACK_TX_IDX_MAX,
  132. };
  133. struct msm_asoc_mach_data {
  134. struct snd_info_entry *codec_root;
  135. int usbc_en2_gpio; /* used by gpio driver API */
  136. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  137. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  138. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  139. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  140. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  141. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  142. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  143. bool is_afe_config_done;
  144. struct device_node *fsa_handle;
  145. };
  146. struct tdm_port {
  147. u32 mode;
  148. u32 channel;
  149. };
  150. enum {
  151. EXT_DISP_RX_IDX_DP = 0,
  152. EXT_DISP_RX_IDX_MAX,
  153. };
  154. struct msm_wsa881x_dev_info {
  155. struct device_node *of_node;
  156. u32 index;
  157. };
  158. struct aux_codec_dev_info {
  159. struct device_node *of_node;
  160. u32 index;
  161. };
  162. struct dev_config {
  163. u32 sample_rate;
  164. u32 bit_format;
  165. u32 channels;
  166. };
  167. /* Default configuration of slimbus channels */
  168. static struct dev_config slim_rx_cfg[] = {
  169. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  170. };
  171. static struct dev_config slim_tx_cfg[] = {
  172. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  173. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  174. };
  175. /* Default configuration of external display BE */
  176. static struct dev_config ext_disp_rx_cfg[] = {
  177. [EXT_DISP_RX_IDX_DP] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  178. };
  179. static struct dev_config usb_rx_cfg = {
  180. .sample_rate = SAMPLING_RATE_48KHZ,
  181. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  182. .channels = 2,
  183. };
  184. static struct dev_config usb_tx_cfg = {
  185. .sample_rate = SAMPLING_RATE_48KHZ,
  186. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  187. .channels = 1,
  188. };
  189. static struct dev_config proxy_rx_cfg = {
  190. .sample_rate = SAMPLING_RATE_48KHZ,
  191. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  192. .channels = 2,
  193. };
  194. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  195. {
  196. AFE_API_VERSION_I2S_CONFIG,
  197. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  198. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  199. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  200. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  201. 0,
  202. },
  203. {
  204. AFE_API_VERSION_I2S_CONFIG,
  205. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  206. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  207. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  208. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  209. 0,
  210. },
  211. {
  212. AFE_API_VERSION_I2S_CONFIG,
  213. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  214. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  215. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  216. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  217. 0,
  218. },
  219. };
  220. struct mi2s_conf {
  221. struct mutex lock;
  222. u32 ref_cnt;
  223. u32 msm_is_mi2s_master;
  224. };
  225. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  226. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  227. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  228. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  229. };
  230. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  231. /* Default configuration of TDM channels */
  232. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  233. { /* PRI TDM */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  242. },
  243. { /* SEC TDM */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  252. },
  253. { /* TERT TDM */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  262. },
  263. };
  264. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  265. { /* PRI TDM */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  274. },
  275. { /* SEC TDM */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  284. },
  285. { /* TERT TDM */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  294. },
  295. };
  296. /* Default configuration of AUX PCM channels */
  297. static struct dev_config aux_pcm_rx_cfg[] = {
  298. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  299. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  300. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  301. };
  302. static struct dev_config aux_pcm_tx_cfg[] = {
  303. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  304. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  305. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  306. };
  307. /* Default configuration of MI2S channels */
  308. static struct dev_config mi2s_rx_cfg[] = {
  309. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  310. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  311. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  312. };
  313. static struct dev_config mi2s_tx_cfg[] = {
  314. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. };
  318. /* Default configuration of Codec DMA Interface RX */
  319. static struct dev_config cdc_dma_rx_cfg[] = {
  320. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  321. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  322. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  323. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  324. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  325. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  326. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  327. };
  328. /* Default configuration of Codec DMA Interface TX */
  329. static struct dev_config cdc_dma_tx_cfg[] = {
  330. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  331. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  332. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  334. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  335. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  336. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  337. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  338. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  339. };
  340. static struct dev_config afe_loopback_tx_cfg[] = {
  341. [AFE_LOOPBACK_TX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  342. };
  343. static int msm_vi_feed_tx_ch = 2;
  344. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  345. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  346. "S32_LE"};
  347. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  348. "Six", "Seven", "Eight"};
  349. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  350. "KHZ_16", "KHZ_22P05",
  351. "KHZ_32", "KHZ_44P1", "KHZ_48",
  352. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  353. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  354. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  355. "Five", "Six", "Seven",
  356. "Eight"};
  357. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  358. "KHZ_48", "KHZ_176P4",
  359. "KHZ_352P8"};
  360. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  361. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  362. "Five", "Six", "Seven", "Eight"};
  363. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  364. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  365. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  366. "KHZ_48", "KHZ_96", "KHZ_192"};
  367. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  368. "Five", "Six", "Seven",
  369. "Eight"};
  370. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  371. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  372. "Five", "Six", "Seven",
  373. "Eight"};
  374. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  375. "KHZ_16", "KHZ_22P05",
  376. "KHZ_32", "KHZ_44P1", "KHZ_48",
  377. "KHZ_88P2", "KHZ_96",
  378. "KHZ_176P4", "KHZ_192",
  379. "KHZ_352P8", "KHZ_384"};
  380. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
  381. "S24_3LE"};
  382. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  383. "KHZ_192", "KHZ_32", "KHZ_44P1",
  384. "KHZ_88P2", "KHZ_176P4"};
  385. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  386. "KHZ_44P1", "KHZ_48",
  387. "KHZ_88P2", "KHZ_96"};
  388. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  389. "KHZ_44P1", "KHZ_48",
  390. "KHZ_88P2", "KHZ_96"};
  391. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  392. "KHZ_44P1", "KHZ_48",
  393. "KHZ_88P2", "KHZ_96"};
  394. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  395. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  396. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  397. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  398. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  399. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  400. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  401. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  402. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  403. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  404. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  405. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  406. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  407. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  408. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  409. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  410. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  411. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  412. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  413. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  414. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  415. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  416. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  417. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  418. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  419. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  420. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  421. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  422. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  423. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  424. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  425. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  426. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  427. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  428. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  429. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  430. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_format, bit_format_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_format, bit_format_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_format, bit_format_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_format, bit_format_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_format, bit_format_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  463. cdc_dma_sample_rate_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  465. cdc_dma_sample_rate_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_sample_rate,
  467. cdc_dma_sample_rate_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_sample_rate,
  469. cdc_dma_sample_rate_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_sample_rate,
  471. cdc_dma_sample_rate_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_sample_rate,
  473. cdc_dma_sample_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_sample_rate,
  475. cdc_dma_sample_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  477. cdc_dma_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  479. cdc_dma_sample_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  481. cdc_dma_sample_rate_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  483. cdc_dma_sample_rate_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  485. cdc_dma_sample_rate_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  487. cdc_dma_sample_rate_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  489. cdc_dma_sample_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  491. cdc_dma_sample_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  493. cdc_dma_sample_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  497. ext_disp_sample_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  502. static bool is_initial_boot;
  503. static bool codec_reg_done;
  504. static struct snd_soc_aux_dev *msm_aux_dev;
  505. static struct snd_soc_codec_conf *msm_codec_conf;
  506. static struct snd_soc_card snd_soc_card_kona_msm;
  507. static int dmic_0_1_gpio_cnt;
  508. static int dmic_2_3_gpio_cnt;
  509. static int dmic_4_5_gpio_cnt;
  510. static void *def_wcd_mbhc_cal(void);
  511. /*
  512. * Need to report LINEIN
  513. * if R/L channel impedance is larger than 5K ohm
  514. */
  515. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  516. .read_fw_bin = false,
  517. .calibration = NULL,
  518. .detect_extn_cable = true,
  519. .mono_stero_detection = false,
  520. .swap_gnd_mic = NULL,
  521. .hs_ext_micbias = true,
  522. .key_code[0] = KEY_MEDIA,
  523. .key_code[1] = KEY_VOICECOMMAND,
  524. .key_code[2] = KEY_VOLUMEUP,
  525. .key_code[3] = KEY_VOLUMEDOWN,
  526. .key_code[4] = 0,
  527. .key_code[5] = 0,
  528. .key_code[6] = 0,
  529. .key_code[7] = 0,
  530. .linein_th = 5000,
  531. .moisture_en = true,
  532. .mbhc_micbias = MIC_BIAS_2,
  533. .anc_micbias = MIC_BIAS_2,
  534. .enable_anc_mic_detect = false,
  535. };
  536. static inline int param_is_mask(int p)
  537. {
  538. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  539. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  540. }
  541. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  542. int n)
  543. {
  544. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  545. }
  546. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  547. unsigned int bit)
  548. {
  549. if (bit >= SNDRV_MASK_MAX)
  550. return;
  551. if (param_is_mask(n)) {
  552. struct snd_mask *m = param_to_mask(p, n);
  553. m->bits[0] = 0;
  554. m->bits[1] = 0;
  555. m->bits[bit >> 5] |= (1 << (bit & 31));
  556. }
  557. }
  558. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  559. struct snd_ctl_elem_value *ucontrol)
  560. {
  561. int sample_rate_val = 0;
  562. switch (usb_rx_cfg.sample_rate) {
  563. case SAMPLING_RATE_384KHZ:
  564. sample_rate_val = 12;
  565. break;
  566. case SAMPLING_RATE_352P8KHZ:
  567. sample_rate_val = 11;
  568. break;
  569. case SAMPLING_RATE_192KHZ:
  570. sample_rate_val = 10;
  571. break;
  572. case SAMPLING_RATE_176P4KHZ:
  573. sample_rate_val = 9;
  574. break;
  575. case SAMPLING_RATE_96KHZ:
  576. sample_rate_val = 8;
  577. break;
  578. case SAMPLING_RATE_88P2KHZ:
  579. sample_rate_val = 7;
  580. break;
  581. case SAMPLING_RATE_48KHZ:
  582. sample_rate_val = 6;
  583. break;
  584. case SAMPLING_RATE_44P1KHZ:
  585. sample_rate_val = 5;
  586. break;
  587. case SAMPLING_RATE_32KHZ:
  588. sample_rate_val = 4;
  589. break;
  590. case SAMPLING_RATE_22P05KHZ:
  591. sample_rate_val = 3;
  592. break;
  593. case SAMPLING_RATE_16KHZ:
  594. sample_rate_val = 2;
  595. break;
  596. case SAMPLING_RATE_11P025KHZ:
  597. sample_rate_val = 1;
  598. break;
  599. case SAMPLING_RATE_8KHZ:
  600. default:
  601. sample_rate_val = 0;
  602. break;
  603. }
  604. ucontrol->value.integer.value[0] = sample_rate_val;
  605. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  606. usb_rx_cfg.sample_rate);
  607. return 0;
  608. }
  609. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  610. struct snd_ctl_elem_value *ucontrol)
  611. {
  612. switch (ucontrol->value.integer.value[0]) {
  613. case 12:
  614. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  615. break;
  616. case 11:
  617. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  618. break;
  619. case 10:
  620. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  621. break;
  622. case 9:
  623. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  624. break;
  625. case 8:
  626. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  627. break;
  628. case 7:
  629. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  630. break;
  631. case 6:
  632. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  633. break;
  634. case 5:
  635. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  636. break;
  637. case 4:
  638. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  639. break;
  640. case 3:
  641. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  642. break;
  643. case 2:
  644. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  645. break;
  646. case 1:
  647. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  648. break;
  649. case 0:
  650. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  651. break;
  652. default:
  653. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  654. break;
  655. }
  656. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  657. __func__, ucontrol->value.integer.value[0],
  658. usb_rx_cfg.sample_rate);
  659. return 0;
  660. }
  661. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  662. struct snd_ctl_elem_value *ucontrol)
  663. {
  664. int sample_rate_val = 0;
  665. switch (usb_tx_cfg.sample_rate) {
  666. case SAMPLING_RATE_384KHZ:
  667. sample_rate_val = 12;
  668. break;
  669. case SAMPLING_RATE_352P8KHZ:
  670. sample_rate_val = 11;
  671. break;
  672. case SAMPLING_RATE_192KHZ:
  673. sample_rate_val = 10;
  674. break;
  675. case SAMPLING_RATE_176P4KHZ:
  676. sample_rate_val = 9;
  677. break;
  678. case SAMPLING_RATE_96KHZ:
  679. sample_rate_val = 8;
  680. break;
  681. case SAMPLING_RATE_88P2KHZ:
  682. sample_rate_val = 7;
  683. break;
  684. case SAMPLING_RATE_48KHZ:
  685. sample_rate_val = 6;
  686. break;
  687. case SAMPLING_RATE_44P1KHZ:
  688. sample_rate_val = 5;
  689. break;
  690. case SAMPLING_RATE_32KHZ:
  691. sample_rate_val = 4;
  692. break;
  693. case SAMPLING_RATE_22P05KHZ:
  694. sample_rate_val = 3;
  695. break;
  696. case SAMPLING_RATE_16KHZ:
  697. sample_rate_val = 2;
  698. break;
  699. case SAMPLING_RATE_11P025KHZ:
  700. sample_rate_val = 1;
  701. break;
  702. case SAMPLING_RATE_8KHZ:
  703. sample_rate_val = 0;
  704. break;
  705. default:
  706. sample_rate_val = 6;
  707. break;
  708. }
  709. ucontrol->value.integer.value[0] = sample_rate_val;
  710. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  711. usb_tx_cfg.sample_rate);
  712. return 0;
  713. }
  714. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  715. struct snd_ctl_elem_value *ucontrol)
  716. {
  717. switch (ucontrol->value.integer.value[0]) {
  718. case 12:
  719. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  720. break;
  721. case 11:
  722. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  723. break;
  724. case 10:
  725. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  726. break;
  727. case 9:
  728. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  729. break;
  730. case 8:
  731. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  732. break;
  733. case 7:
  734. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  735. break;
  736. case 6:
  737. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  738. break;
  739. case 5:
  740. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  741. break;
  742. case 4:
  743. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  744. break;
  745. case 3:
  746. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  747. break;
  748. case 2:
  749. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  750. break;
  751. case 1:
  752. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  753. break;
  754. case 0:
  755. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  756. break;
  757. default:
  758. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  759. break;
  760. }
  761. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  762. __func__, ucontrol->value.integer.value[0],
  763. usb_tx_cfg.sample_rate);
  764. return 0;
  765. }
  766. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  767. struct snd_ctl_elem_value *ucontrol)
  768. {
  769. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  770. afe_loopback_tx_cfg[0].channels);
  771. ucontrol->value.enumerated.item[0] =
  772. afe_loopback_tx_cfg[0].channels - 1;
  773. return 0;
  774. }
  775. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  776. struct snd_ctl_elem_value *ucontrol)
  777. {
  778. afe_loopback_tx_cfg[0].channels =
  779. ucontrol->value.enumerated.item[0] + 1;
  780. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  781. afe_loopback_tx_cfg[0].channels);
  782. return 1;
  783. }
  784. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  785. struct snd_ctl_elem_value *ucontrol)
  786. {
  787. switch (usb_rx_cfg.bit_format) {
  788. case SNDRV_PCM_FORMAT_S32_LE:
  789. ucontrol->value.integer.value[0] = 3;
  790. break;
  791. case SNDRV_PCM_FORMAT_S24_3LE:
  792. ucontrol->value.integer.value[0] = 2;
  793. break;
  794. case SNDRV_PCM_FORMAT_S24_LE:
  795. ucontrol->value.integer.value[0] = 1;
  796. break;
  797. case SNDRV_PCM_FORMAT_S16_LE:
  798. default:
  799. ucontrol->value.integer.value[0] = 0;
  800. break;
  801. }
  802. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  803. __func__, usb_rx_cfg.bit_format,
  804. ucontrol->value.integer.value[0]);
  805. return 0;
  806. }
  807. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  808. struct snd_ctl_elem_value *ucontrol)
  809. {
  810. int rc = 0;
  811. switch (ucontrol->value.integer.value[0]) {
  812. case 3:
  813. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  814. break;
  815. case 2:
  816. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  817. break;
  818. case 1:
  819. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  820. break;
  821. case 0:
  822. default:
  823. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  824. break;
  825. }
  826. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  827. __func__, usb_rx_cfg.bit_format,
  828. ucontrol->value.integer.value[0]);
  829. return rc;
  830. }
  831. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  832. struct snd_ctl_elem_value *ucontrol)
  833. {
  834. switch (usb_tx_cfg.bit_format) {
  835. case SNDRV_PCM_FORMAT_S32_LE:
  836. ucontrol->value.integer.value[0] = 3;
  837. break;
  838. case SNDRV_PCM_FORMAT_S24_3LE:
  839. ucontrol->value.integer.value[0] = 2;
  840. break;
  841. case SNDRV_PCM_FORMAT_S24_LE:
  842. ucontrol->value.integer.value[0] = 1;
  843. break;
  844. case SNDRV_PCM_FORMAT_S16_LE:
  845. default:
  846. ucontrol->value.integer.value[0] = 0;
  847. break;
  848. }
  849. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  850. __func__, usb_tx_cfg.bit_format,
  851. ucontrol->value.integer.value[0]);
  852. return 0;
  853. }
  854. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  855. struct snd_ctl_elem_value *ucontrol)
  856. {
  857. int rc = 0;
  858. switch (ucontrol->value.integer.value[0]) {
  859. case 3:
  860. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  861. break;
  862. case 2:
  863. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  864. break;
  865. case 1:
  866. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  867. break;
  868. case 0:
  869. default:
  870. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  871. break;
  872. }
  873. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  874. __func__, usb_tx_cfg.bit_format,
  875. ucontrol->value.integer.value[0]);
  876. return rc;
  877. }
  878. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  879. struct snd_ctl_elem_value *ucontrol)
  880. {
  881. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  882. usb_rx_cfg.channels);
  883. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  884. return 0;
  885. }
  886. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  887. struct snd_ctl_elem_value *ucontrol)
  888. {
  889. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  890. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  891. return 1;
  892. }
  893. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  894. struct snd_ctl_elem_value *ucontrol)
  895. {
  896. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  897. usb_tx_cfg.channels);
  898. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  899. return 0;
  900. }
  901. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  902. struct snd_ctl_elem_value *ucontrol)
  903. {
  904. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  905. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  906. return 1;
  907. }
  908. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  909. struct snd_ctl_elem_value *ucontrol)
  910. {
  911. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  912. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  913. ucontrol->value.integer.value[0]);
  914. return 0;
  915. }
  916. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  917. struct snd_ctl_elem_value *ucontrol)
  918. {
  919. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  920. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  921. return 1;
  922. }
  923. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  924. {
  925. int idx = 0;
  926. if (strnstr(kcontrol->id.name, "Display Port RX",
  927. sizeof("Display Port RX"))) {
  928. idx = EXT_DISP_RX_IDX_DP;
  929. } else {
  930. pr_err("%s: unsupported BE: %s\n",
  931. __func__, kcontrol->id.name);
  932. idx = -EINVAL;
  933. }
  934. return idx;
  935. }
  936. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  937. struct snd_ctl_elem_value *ucontrol)
  938. {
  939. int idx = ext_disp_get_port_idx(kcontrol);
  940. if (idx < 0)
  941. return idx;
  942. switch (ext_disp_rx_cfg[idx].bit_format) {
  943. case SNDRV_PCM_FORMAT_S24_3LE:
  944. ucontrol->value.integer.value[0] = 2;
  945. break;
  946. case SNDRV_PCM_FORMAT_S24_LE:
  947. ucontrol->value.integer.value[0] = 1;
  948. break;
  949. case SNDRV_PCM_FORMAT_S16_LE:
  950. default:
  951. ucontrol->value.integer.value[0] = 0;
  952. break;
  953. }
  954. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  955. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  956. ucontrol->value.integer.value[0]);
  957. return 0;
  958. }
  959. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  960. struct snd_ctl_elem_value *ucontrol)
  961. {
  962. int idx = ext_disp_get_port_idx(kcontrol);
  963. if (idx < 0)
  964. return idx;
  965. switch (ucontrol->value.integer.value[0]) {
  966. case 2:
  967. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  968. break;
  969. case 1:
  970. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  971. break;
  972. case 0:
  973. default:
  974. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  975. break;
  976. }
  977. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  978. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  979. ucontrol->value.integer.value[0]);
  980. return 0;
  981. }
  982. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  983. struct snd_ctl_elem_value *ucontrol)
  984. {
  985. int idx = ext_disp_get_port_idx(kcontrol);
  986. if (idx < 0)
  987. return idx;
  988. ucontrol->value.integer.value[0] =
  989. ext_disp_rx_cfg[idx].channels - 2;
  990. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  991. idx, ext_disp_rx_cfg[idx].channels);
  992. return 0;
  993. }
  994. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  995. struct snd_ctl_elem_value *ucontrol)
  996. {
  997. int idx = ext_disp_get_port_idx(kcontrol);
  998. if (idx < 0)
  999. return idx;
  1000. ext_disp_rx_cfg[idx].channels =
  1001. ucontrol->value.integer.value[0] + 2;
  1002. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1003. idx, ext_disp_rx_cfg[idx].channels);
  1004. return 1;
  1005. }
  1006. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1007. struct snd_ctl_elem_value *ucontrol)
  1008. {
  1009. int sample_rate_val;
  1010. int idx = ext_disp_get_port_idx(kcontrol);
  1011. if (idx < 0)
  1012. return idx;
  1013. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1014. case SAMPLING_RATE_176P4KHZ:
  1015. sample_rate_val = 6;
  1016. break;
  1017. case SAMPLING_RATE_88P2KHZ:
  1018. sample_rate_val = 5;
  1019. break;
  1020. case SAMPLING_RATE_44P1KHZ:
  1021. sample_rate_val = 4;
  1022. break;
  1023. case SAMPLING_RATE_32KHZ:
  1024. sample_rate_val = 3;
  1025. break;
  1026. case SAMPLING_RATE_192KHZ:
  1027. sample_rate_val = 2;
  1028. break;
  1029. case SAMPLING_RATE_96KHZ:
  1030. sample_rate_val = 1;
  1031. break;
  1032. case SAMPLING_RATE_48KHZ:
  1033. default:
  1034. sample_rate_val = 0;
  1035. break;
  1036. }
  1037. ucontrol->value.integer.value[0] = sample_rate_val;
  1038. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1039. idx, ext_disp_rx_cfg[idx].sample_rate);
  1040. return 0;
  1041. }
  1042. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1043. struct snd_ctl_elem_value *ucontrol)
  1044. {
  1045. int idx = ext_disp_get_port_idx(kcontrol);
  1046. if (idx < 0)
  1047. return idx;
  1048. switch (ucontrol->value.integer.value[0]) {
  1049. case 6:
  1050. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
  1051. break;
  1052. case 5:
  1053. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
  1054. break;
  1055. case 4:
  1056. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
  1057. break;
  1058. case 3:
  1059. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
  1060. break;
  1061. case 2:
  1062. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1063. break;
  1064. case 1:
  1065. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1066. break;
  1067. case 0:
  1068. default:
  1069. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1070. break;
  1071. }
  1072. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1073. __func__, ucontrol->value.integer.value[0], idx,
  1074. ext_disp_rx_cfg[idx].sample_rate);
  1075. return 0;
  1076. }
  1077. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1078. struct snd_ctl_elem_value *ucontrol)
  1079. {
  1080. pr_debug("%s: proxy_rx channels = %d\n",
  1081. __func__, proxy_rx_cfg.channels);
  1082. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1083. return 0;
  1084. }
  1085. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1086. struct snd_ctl_elem_value *ucontrol)
  1087. {
  1088. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1089. pr_debug("%s: proxy_rx channels = %d\n",
  1090. __func__, proxy_rx_cfg.channels);
  1091. return 1;
  1092. }
  1093. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1094. struct tdm_port *port)
  1095. {
  1096. if (port) {
  1097. if (strnstr(kcontrol->id.name, "PRI",
  1098. sizeof(kcontrol->id.name))) {
  1099. port->mode = TDM_PRI;
  1100. } else if (strnstr(kcontrol->id.name, "SEC",
  1101. sizeof(kcontrol->id.name))) {
  1102. port->mode = TDM_SEC;
  1103. } else if (strnstr(kcontrol->id.name, "TERT",
  1104. sizeof(kcontrol->id.name))) {
  1105. port->mode = TDM_TERT;
  1106. } else {
  1107. pr_err("%s: unsupported mode in: %s\n",
  1108. __func__, kcontrol->id.name);
  1109. return -EINVAL;
  1110. }
  1111. if (strnstr(kcontrol->id.name, "RX_0",
  1112. sizeof(kcontrol->id.name)) ||
  1113. strnstr(kcontrol->id.name, "TX_0",
  1114. sizeof(kcontrol->id.name))) {
  1115. port->channel = TDM_0;
  1116. } else if (strnstr(kcontrol->id.name, "RX_1",
  1117. sizeof(kcontrol->id.name)) ||
  1118. strnstr(kcontrol->id.name, "TX_1",
  1119. sizeof(kcontrol->id.name))) {
  1120. port->channel = TDM_1;
  1121. } else if (strnstr(kcontrol->id.name, "RX_2",
  1122. sizeof(kcontrol->id.name)) ||
  1123. strnstr(kcontrol->id.name, "TX_2",
  1124. sizeof(kcontrol->id.name))) {
  1125. port->channel = TDM_2;
  1126. } else if (strnstr(kcontrol->id.name, "RX_3",
  1127. sizeof(kcontrol->id.name)) ||
  1128. strnstr(kcontrol->id.name, "TX_3",
  1129. sizeof(kcontrol->id.name))) {
  1130. port->channel = TDM_3;
  1131. } else if (strnstr(kcontrol->id.name, "RX_4",
  1132. sizeof(kcontrol->id.name)) ||
  1133. strnstr(kcontrol->id.name, "TX_4",
  1134. sizeof(kcontrol->id.name))) {
  1135. port->channel = TDM_4;
  1136. } else if (strnstr(kcontrol->id.name, "RX_5",
  1137. sizeof(kcontrol->id.name)) ||
  1138. strnstr(kcontrol->id.name, "TX_5",
  1139. sizeof(kcontrol->id.name))) {
  1140. port->channel = TDM_5;
  1141. } else if (strnstr(kcontrol->id.name, "RX_6",
  1142. sizeof(kcontrol->id.name)) ||
  1143. strnstr(kcontrol->id.name, "TX_6",
  1144. sizeof(kcontrol->id.name))) {
  1145. port->channel = TDM_6;
  1146. } else if (strnstr(kcontrol->id.name, "RX_7",
  1147. sizeof(kcontrol->id.name)) ||
  1148. strnstr(kcontrol->id.name, "TX_7",
  1149. sizeof(kcontrol->id.name))) {
  1150. port->channel = TDM_7;
  1151. } else {
  1152. pr_err("%s: unsupported channel in: %s\n",
  1153. __func__, kcontrol->id.name);
  1154. return -EINVAL;
  1155. }
  1156. } else {
  1157. return -EINVAL;
  1158. }
  1159. return 0;
  1160. }
  1161. static int tdm_get_sample_rate(int value)
  1162. {
  1163. int sample_rate = 0;
  1164. switch (value) {
  1165. case 0:
  1166. sample_rate = SAMPLING_RATE_8KHZ;
  1167. break;
  1168. case 1:
  1169. sample_rate = SAMPLING_RATE_16KHZ;
  1170. break;
  1171. case 2:
  1172. sample_rate = SAMPLING_RATE_32KHZ;
  1173. break;
  1174. case 3:
  1175. sample_rate = SAMPLING_RATE_48KHZ;
  1176. break;
  1177. case 4:
  1178. sample_rate = SAMPLING_RATE_176P4KHZ;
  1179. break;
  1180. case 5:
  1181. sample_rate = SAMPLING_RATE_352P8KHZ;
  1182. break;
  1183. default:
  1184. sample_rate = SAMPLING_RATE_48KHZ;
  1185. break;
  1186. }
  1187. return sample_rate;
  1188. }
  1189. static int tdm_get_sample_rate_val(int sample_rate)
  1190. {
  1191. int sample_rate_val = 0;
  1192. switch (sample_rate) {
  1193. case SAMPLING_RATE_8KHZ:
  1194. sample_rate_val = 0;
  1195. break;
  1196. case SAMPLING_RATE_16KHZ:
  1197. sample_rate_val = 1;
  1198. break;
  1199. case SAMPLING_RATE_32KHZ:
  1200. sample_rate_val = 2;
  1201. break;
  1202. case SAMPLING_RATE_48KHZ:
  1203. sample_rate_val = 3;
  1204. break;
  1205. case SAMPLING_RATE_176P4KHZ:
  1206. sample_rate_val = 4;
  1207. break;
  1208. case SAMPLING_RATE_352P8KHZ:
  1209. sample_rate_val = 5;
  1210. break;
  1211. default:
  1212. sample_rate_val = 3;
  1213. break;
  1214. }
  1215. return sample_rate_val;
  1216. }
  1217. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1218. struct snd_ctl_elem_value *ucontrol)
  1219. {
  1220. struct tdm_port port;
  1221. int ret = tdm_get_port_idx(kcontrol, &port);
  1222. if (ret) {
  1223. pr_err("%s: unsupported control: %s\n",
  1224. __func__, kcontrol->id.name);
  1225. } else {
  1226. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1227. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1228. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1229. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1230. ucontrol->value.enumerated.item[0]);
  1231. }
  1232. return ret;
  1233. }
  1234. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1235. struct snd_ctl_elem_value *ucontrol)
  1236. {
  1237. struct tdm_port port;
  1238. int ret = tdm_get_port_idx(kcontrol, &port);
  1239. if (ret) {
  1240. pr_err("%s: unsupported control: %s\n",
  1241. __func__, kcontrol->id.name);
  1242. } else {
  1243. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1244. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1245. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1246. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1247. ucontrol->value.enumerated.item[0]);
  1248. }
  1249. return ret;
  1250. }
  1251. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1252. struct snd_ctl_elem_value *ucontrol)
  1253. {
  1254. struct tdm_port port;
  1255. int ret = tdm_get_port_idx(kcontrol, &port);
  1256. if (ret) {
  1257. pr_err("%s: unsupported control: %s\n",
  1258. __func__, kcontrol->id.name);
  1259. } else {
  1260. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1261. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1262. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1263. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1264. ucontrol->value.enumerated.item[0]);
  1265. }
  1266. return ret;
  1267. }
  1268. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1269. struct snd_ctl_elem_value *ucontrol)
  1270. {
  1271. struct tdm_port port;
  1272. int ret = tdm_get_port_idx(kcontrol, &port);
  1273. if (ret) {
  1274. pr_err("%s: unsupported control: %s\n",
  1275. __func__, kcontrol->id.name);
  1276. } else {
  1277. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1278. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1279. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1280. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1281. ucontrol->value.enumerated.item[0]);
  1282. }
  1283. return ret;
  1284. }
  1285. static int tdm_get_format(int value)
  1286. {
  1287. int format = 0;
  1288. switch (value) {
  1289. case 0:
  1290. format = SNDRV_PCM_FORMAT_S16_LE;
  1291. break;
  1292. case 1:
  1293. format = SNDRV_PCM_FORMAT_S24_LE;
  1294. break;
  1295. case 2:
  1296. format = SNDRV_PCM_FORMAT_S32_LE;
  1297. break;
  1298. default:
  1299. format = SNDRV_PCM_FORMAT_S16_LE;
  1300. break;
  1301. }
  1302. return format;
  1303. }
  1304. static int tdm_get_format_val(int format)
  1305. {
  1306. int value = 0;
  1307. switch (format) {
  1308. case SNDRV_PCM_FORMAT_S16_LE:
  1309. value = 0;
  1310. break;
  1311. case SNDRV_PCM_FORMAT_S24_LE:
  1312. value = 1;
  1313. break;
  1314. case SNDRV_PCM_FORMAT_S32_LE:
  1315. value = 2;
  1316. break;
  1317. default:
  1318. value = 0;
  1319. break;
  1320. }
  1321. return value;
  1322. }
  1323. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1324. struct snd_ctl_elem_value *ucontrol)
  1325. {
  1326. struct tdm_port port;
  1327. int ret = tdm_get_port_idx(kcontrol, &port);
  1328. if (ret) {
  1329. pr_err("%s: unsupported control: %s\n",
  1330. __func__, kcontrol->id.name);
  1331. } else {
  1332. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1333. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1334. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1335. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1336. ucontrol->value.enumerated.item[0]);
  1337. }
  1338. return ret;
  1339. }
  1340. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1341. struct snd_ctl_elem_value *ucontrol)
  1342. {
  1343. struct tdm_port port;
  1344. int ret = tdm_get_port_idx(kcontrol, &port);
  1345. if (ret) {
  1346. pr_err("%s: unsupported control: %s\n",
  1347. __func__, kcontrol->id.name);
  1348. } else {
  1349. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1350. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1351. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1352. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1353. ucontrol->value.enumerated.item[0]);
  1354. }
  1355. return ret;
  1356. }
  1357. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1358. struct snd_ctl_elem_value *ucontrol)
  1359. {
  1360. struct tdm_port port;
  1361. int ret = tdm_get_port_idx(kcontrol, &port);
  1362. if (ret) {
  1363. pr_err("%s: unsupported control: %s\n",
  1364. __func__, kcontrol->id.name);
  1365. } else {
  1366. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1367. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1368. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1369. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1370. ucontrol->value.enumerated.item[0]);
  1371. }
  1372. return ret;
  1373. }
  1374. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1375. struct snd_ctl_elem_value *ucontrol)
  1376. {
  1377. struct tdm_port port;
  1378. int ret = tdm_get_port_idx(kcontrol, &port);
  1379. if (ret) {
  1380. pr_err("%s: unsupported control: %s\n",
  1381. __func__, kcontrol->id.name);
  1382. } else {
  1383. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1384. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1385. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1386. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1387. ucontrol->value.enumerated.item[0]);
  1388. }
  1389. return ret;
  1390. }
  1391. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1392. struct snd_ctl_elem_value *ucontrol)
  1393. {
  1394. struct tdm_port port;
  1395. int ret = tdm_get_port_idx(kcontrol, &port);
  1396. if (ret) {
  1397. pr_err("%s: unsupported control: %s\n",
  1398. __func__, kcontrol->id.name);
  1399. } else {
  1400. ucontrol->value.enumerated.item[0] =
  1401. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1402. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1403. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1404. ucontrol->value.enumerated.item[0]);
  1405. }
  1406. return ret;
  1407. }
  1408. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1409. struct snd_ctl_elem_value *ucontrol)
  1410. {
  1411. struct tdm_port port;
  1412. int ret = tdm_get_port_idx(kcontrol, &port);
  1413. if (ret) {
  1414. pr_err("%s: unsupported control: %s\n",
  1415. __func__, kcontrol->id.name);
  1416. } else {
  1417. tdm_rx_cfg[port.mode][port.channel].channels =
  1418. ucontrol->value.enumerated.item[0] + 1;
  1419. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1420. tdm_rx_cfg[port.mode][port.channel].channels,
  1421. ucontrol->value.enumerated.item[0] + 1);
  1422. }
  1423. return ret;
  1424. }
  1425. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1426. struct snd_ctl_elem_value *ucontrol)
  1427. {
  1428. struct tdm_port port;
  1429. int ret = tdm_get_port_idx(kcontrol, &port);
  1430. if (ret) {
  1431. pr_err("%s: unsupported control: %s\n",
  1432. __func__, kcontrol->id.name);
  1433. } else {
  1434. ucontrol->value.enumerated.item[0] =
  1435. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1436. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1437. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1438. ucontrol->value.enumerated.item[0]);
  1439. }
  1440. return ret;
  1441. }
  1442. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1443. struct snd_ctl_elem_value *ucontrol)
  1444. {
  1445. struct tdm_port port;
  1446. int ret = tdm_get_port_idx(kcontrol, &port);
  1447. if (ret) {
  1448. pr_err("%s: unsupported control: %s\n",
  1449. __func__, kcontrol->id.name);
  1450. } else {
  1451. tdm_tx_cfg[port.mode][port.channel].channels =
  1452. ucontrol->value.enumerated.item[0] + 1;
  1453. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1454. tdm_tx_cfg[port.mode][port.channel].channels,
  1455. ucontrol->value.enumerated.item[0] + 1);
  1456. }
  1457. return ret;
  1458. }
  1459. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1460. {
  1461. int idx = 0;
  1462. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1463. sizeof("PRIM_AUX_PCM"))) {
  1464. idx = PRIM_AUX_PCM;
  1465. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1466. sizeof("SEC_AUX_PCM"))) {
  1467. idx = SEC_AUX_PCM;
  1468. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1469. sizeof("TERT_AUX_PCM"))) {
  1470. idx = TERT_AUX_PCM;
  1471. } else {
  1472. pr_err("%s: unsupported port: %s\n",
  1473. __func__, kcontrol->id.name);
  1474. idx = -EINVAL;
  1475. }
  1476. return idx;
  1477. }
  1478. static int aux_pcm_get_sample_rate(int value)
  1479. {
  1480. int sample_rate = 0;
  1481. switch (value) {
  1482. case 1:
  1483. sample_rate = SAMPLING_RATE_16KHZ;
  1484. break;
  1485. case 0:
  1486. default:
  1487. sample_rate = SAMPLING_RATE_8KHZ;
  1488. break;
  1489. }
  1490. return sample_rate;
  1491. }
  1492. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1493. {
  1494. int sample_rate_val = 0;
  1495. switch (sample_rate) {
  1496. case SAMPLING_RATE_16KHZ:
  1497. sample_rate_val = 1;
  1498. break;
  1499. case SAMPLING_RATE_8KHZ:
  1500. default:
  1501. sample_rate_val = 0;
  1502. break;
  1503. }
  1504. return sample_rate_val;
  1505. }
  1506. static int mi2s_auxpcm_get_format(int value)
  1507. {
  1508. int format = 0;
  1509. switch (value) {
  1510. case 0:
  1511. format = SNDRV_PCM_FORMAT_S16_LE;
  1512. break;
  1513. case 1:
  1514. format = SNDRV_PCM_FORMAT_S24_LE;
  1515. break;
  1516. case 2:
  1517. format = SNDRV_PCM_FORMAT_S24_3LE;
  1518. break;
  1519. case 3:
  1520. format = SNDRV_PCM_FORMAT_S32_LE;
  1521. break;
  1522. default:
  1523. format = SNDRV_PCM_FORMAT_S16_LE;
  1524. break;
  1525. }
  1526. return format;
  1527. }
  1528. static int mi2s_auxpcm_get_format_value(int format)
  1529. {
  1530. int value = 0;
  1531. switch (format) {
  1532. case SNDRV_PCM_FORMAT_S16_LE:
  1533. value = 0;
  1534. break;
  1535. case SNDRV_PCM_FORMAT_S24_LE:
  1536. value = 1;
  1537. break;
  1538. case SNDRV_PCM_FORMAT_S24_3LE:
  1539. value = 2;
  1540. break;
  1541. case SNDRV_PCM_FORMAT_S32_LE:
  1542. value = 3;
  1543. break;
  1544. default:
  1545. value = 0;
  1546. break;
  1547. }
  1548. return value;
  1549. }
  1550. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1551. struct snd_ctl_elem_value *ucontrol)
  1552. {
  1553. int idx = aux_pcm_get_port_idx(kcontrol);
  1554. if (idx < 0)
  1555. return idx;
  1556. ucontrol->value.enumerated.item[0] =
  1557. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1558. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1559. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1560. ucontrol->value.enumerated.item[0]);
  1561. return 0;
  1562. }
  1563. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1564. struct snd_ctl_elem_value *ucontrol)
  1565. {
  1566. int idx = aux_pcm_get_port_idx(kcontrol);
  1567. if (idx < 0)
  1568. return idx;
  1569. aux_pcm_rx_cfg[idx].sample_rate =
  1570. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1571. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1572. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1573. ucontrol->value.enumerated.item[0]);
  1574. return 0;
  1575. }
  1576. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1577. struct snd_ctl_elem_value *ucontrol)
  1578. {
  1579. int idx = aux_pcm_get_port_idx(kcontrol);
  1580. if (idx < 0)
  1581. return idx;
  1582. ucontrol->value.enumerated.item[0] =
  1583. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1584. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1585. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1586. ucontrol->value.enumerated.item[0]);
  1587. return 0;
  1588. }
  1589. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1590. struct snd_ctl_elem_value *ucontrol)
  1591. {
  1592. int idx = aux_pcm_get_port_idx(kcontrol);
  1593. if (idx < 0)
  1594. return idx;
  1595. aux_pcm_tx_cfg[idx].sample_rate =
  1596. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1597. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1598. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1599. ucontrol->value.enumerated.item[0]);
  1600. return 0;
  1601. }
  1602. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1603. struct snd_ctl_elem_value *ucontrol)
  1604. {
  1605. int idx = aux_pcm_get_port_idx(kcontrol);
  1606. if (idx < 0)
  1607. return idx;
  1608. ucontrol->value.enumerated.item[0] =
  1609. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1610. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1611. idx, aux_pcm_rx_cfg[idx].bit_format,
  1612. ucontrol->value.enumerated.item[0]);
  1613. return 0;
  1614. }
  1615. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1616. struct snd_ctl_elem_value *ucontrol)
  1617. {
  1618. int idx = aux_pcm_get_port_idx(kcontrol);
  1619. if (idx < 0)
  1620. return idx;
  1621. aux_pcm_rx_cfg[idx].bit_format =
  1622. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1623. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1624. idx, aux_pcm_rx_cfg[idx].bit_format,
  1625. ucontrol->value.enumerated.item[0]);
  1626. return 0;
  1627. }
  1628. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1629. struct snd_ctl_elem_value *ucontrol)
  1630. {
  1631. int idx = aux_pcm_get_port_idx(kcontrol);
  1632. if (idx < 0)
  1633. return idx;
  1634. ucontrol->value.enumerated.item[0] =
  1635. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1636. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1637. idx, aux_pcm_tx_cfg[idx].bit_format,
  1638. ucontrol->value.enumerated.item[0]);
  1639. return 0;
  1640. }
  1641. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1642. struct snd_ctl_elem_value *ucontrol)
  1643. {
  1644. int idx = aux_pcm_get_port_idx(kcontrol);
  1645. if (idx < 0)
  1646. return idx;
  1647. aux_pcm_tx_cfg[idx].bit_format =
  1648. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1649. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1650. idx, aux_pcm_tx_cfg[idx].bit_format,
  1651. ucontrol->value.enumerated.item[0]);
  1652. return 0;
  1653. }
  1654. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  1655. {
  1656. int idx = 0;
  1657. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  1658. sizeof("PRIM_MI2S_RX"))) {
  1659. idx = PRIM_MI2S;
  1660. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  1661. sizeof("SEC_MI2S_RX"))) {
  1662. idx = SEC_MI2S;
  1663. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  1664. sizeof("TERT_MI2S_RX"))) {
  1665. idx = TERT_MI2S;
  1666. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1667. sizeof("PRIM_MI2S_TX"))) {
  1668. idx = PRIM_MI2S;
  1669. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1670. sizeof("SEC_MI2S_TX"))) {
  1671. idx = SEC_MI2S;
  1672. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1673. sizeof("TERT_MI2S_TX"))) {
  1674. idx = TERT_MI2S;
  1675. } else {
  1676. pr_err("%s: unsupported channel: %s\n",
  1677. __func__, kcontrol->id.name);
  1678. idx = -EINVAL;
  1679. }
  1680. return idx;
  1681. }
  1682. static int mi2s_get_sample_rate(int value)
  1683. {
  1684. int sample_rate = 0;
  1685. switch (value) {
  1686. case 0:
  1687. sample_rate = SAMPLING_RATE_8KHZ;
  1688. break;
  1689. case 1:
  1690. sample_rate = SAMPLING_RATE_11P025KHZ;
  1691. break;
  1692. case 2:
  1693. sample_rate = SAMPLING_RATE_16KHZ;
  1694. break;
  1695. case 3:
  1696. sample_rate = SAMPLING_RATE_22P05KHZ;
  1697. break;
  1698. case 4:
  1699. sample_rate = SAMPLING_RATE_32KHZ;
  1700. break;
  1701. case 5:
  1702. sample_rate = SAMPLING_RATE_44P1KHZ;
  1703. break;
  1704. case 6:
  1705. sample_rate = SAMPLING_RATE_48KHZ;
  1706. break;
  1707. case 7:
  1708. sample_rate = SAMPLING_RATE_96KHZ;
  1709. break;
  1710. case 8:
  1711. sample_rate = SAMPLING_RATE_192KHZ;
  1712. break;
  1713. default:
  1714. sample_rate = SAMPLING_RATE_48KHZ;
  1715. break;
  1716. }
  1717. return sample_rate;
  1718. }
  1719. static int mi2s_get_sample_rate_val(int sample_rate)
  1720. {
  1721. int sample_rate_val = 0;
  1722. switch (sample_rate) {
  1723. case SAMPLING_RATE_8KHZ:
  1724. sample_rate_val = 0;
  1725. break;
  1726. case SAMPLING_RATE_11P025KHZ:
  1727. sample_rate_val = 1;
  1728. break;
  1729. case SAMPLING_RATE_16KHZ:
  1730. sample_rate_val = 2;
  1731. break;
  1732. case SAMPLING_RATE_22P05KHZ:
  1733. sample_rate_val = 3;
  1734. break;
  1735. case SAMPLING_RATE_32KHZ:
  1736. sample_rate_val = 4;
  1737. break;
  1738. case SAMPLING_RATE_44P1KHZ:
  1739. sample_rate_val = 5;
  1740. break;
  1741. case SAMPLING_RATE_48KHZ:
  1742. sample_rate_val = 6;
  1743. break;
  1744. case SAMPLING_RATE_96KHZ:
  1745. sample_rate_val = 7;
  1746. break;
  1747. case SAMPLING_RATE_192KHZ:
  1748. sample_rate_val = 8;
  1749. break;
  1750. default:
  1751. sample_rate_val = 6;
  1752. break;
  1753. }
  1754. return sample_rate_val;
  1755. }
  1756. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1757. struct snd_ctl_elem_value *ucontrol)
  1758. {
  1759. int idx = mi2s_get_port_idx(kcontrol);
  1760. if (idx < 0)
  1761. return idx;
  1762. ucontrol->value.enumerated.item[0] =
  1763. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1764. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1765. idx, mi2s_rx_cfg[idx].sample_rate,
  1766. ucontrol->value.enumerated.item[0]);
  1767. return 0;
  1768. }
  1769. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1770. struct snd_ctl_elem_value *ucontrol)
  1771. {
  1772. int idx = mi2s_get_port_idx(kcontrol);
  1773. if (idx < 0)
  1774. return idx;
  1775. mi2s_rx_cfg[idx].sample_rate =
  1776. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1777. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1778. idx, mi2s_rx_cfg[idx].sample_rate,
  1779. ucontrol->value.enumerated.item[0]);
  1780. return 0;
  1781. }
  1782. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1783. struct snd_ctl_elem_value *ucontrol)
  1784. {
  1785. int idx = mi2s_get_port_idx(kcontrol);
  1786. if (idx < 0)
  1787. return idx;
  1788. ucontrol->value.enumerated.item[0] =
  1789. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1790. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1791. idx, mi2s_tx_cfg[idx].sample_rate,
  1792. ucontrol->value.enumerated.item[0]);
  1793. return 0;
  1794. }
  1795. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1796. struct snd_ctl_elem_value *ucontrol)
  1797. {
  1798. int idx = mi2s_get_port_idx(kcontrol);
  1799. if (idx < 0)
  1800. return idx;
  1801. mi2s_tx_cfg[idx].sample_rate =
  1802. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1803. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1804. idx, mi2s_tx_cfg[idx].sample_rate,
  1805. ucontrol->value.enumerated.item[0]);
  1806. return 0;
  1807. }
  1808. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1809. struct snd_ctl_elem_value *ucontrol)
  1810. {
  1811. int idx = mi2s_get_port_idx(kcontrol);
  1812. if (idx < 0)
  1813. return idx;
  1814. ucontrol->value.enumerated.item[0] =
  1815. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1816. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1817. idx, mi2s_rx_cfg[idx].bit_format,
  1818. ucontrol->value.enumerated.item[0]);
  1819. return 0;
  1820. }
  1821. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1822. struct snd_ctl_elem_value *ucontrol)
  1823. {
  1824. int idx = mi2s_get_port_idx(kcontrol);
  1825. if (idx < 0)
  1826. return idx;
  1827. mi2s_rx_cfg[idx].bit_format =
  1828. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1829. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1830. idx, mi2s_rx_cfg[idx].bit_format,
  1831. ucontrol->value.enumerated.item[0]);
  1832. return 0;
  1833. }
  1834. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1835. struct snd_ctl_elem_value *ucontrol)
  1836. {
  1837. int idx = mi2s_get_port_idx(kcontrol);
  1838. if (idx < 0)
  1839. return idx;
  1840. ucontrol->value.enumerated.item[0] =
  1841. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1842. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1843. idx, mi2s_tx_cfg[idx].bit_format,
  1844. ucontrol->value.enumerated.item[0]);
  1845. return 0;
  1846. }
  1847. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1848. struct snd_ctl_elem_value *ucontrol)
  1849. {
  1850. int idx = mi2s_get_port_idx(kcontrol);
  1851. if (idx < 0)
  1852. return idx;
  1853. mi2s_tx_cfg[idx].bit_format =
  1854. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1855. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1856. idx, mi2s_tx_cfg[idx].bit_format,
  1857. ucontrol->value.enumerated.item[0]);
  1858. return 0;
  1859. }
  1860. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1861. struct snd_ctl_elem_value *ucontrol)
  1862. {
  1863. int idx = mi2s_get_port_idx(kcontrol);
  1864. if (idx < 0)
  1865. return idx;
  1866. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1867. idx, mi2s_rx_cfg[idx].channels);
  1868. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1869. return 0;
  1870. }
  1871. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1872. struct snd_ctl_elem_value *ucontrol)
  1873. {
  1874. int idx = mi2s_get_port_idx(kcontrol);
  1875. if (idx < 0)
  1876. return idx;
  1877. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1878. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1879. idx, mi2s_rx_cfg[idx].channels);
  1880. return 1;
  1881. }
  1882. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  1883. struct snd_ctl_elem_value *ucontrol)
  1884. {
  1885. int idx = mi2s_get_port_idx(kcontrol);
  1886. if (idx < 0)
  1887. return idx;
  1888. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1889. idx, mi2s_tx_cfg[idx].channels);
  1890. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  1891. return 0;
  1892. }
  1893. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  1894. struct snd_ctl_elem_value *ucontrol)
  1895. {
  1896. int idx = mi2s_get_port_idx(kcontrol);
  1897. if (idx < 0)
  1898. return idx;
  1899. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1900. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1901. idx, mi2s_tx_cfg[idx].channels);
  1902. return 1;
  1903. }
  1904. static int msm_get_port_id(int be_id)
  1905. {
  1906. int afe_port_id = 0;
  1907. switch (be_id) {
  1908. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  1909. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  1910. break;
  1911. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  1912. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  1913. break;
  1914. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  1915. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  1916. break;
  1917. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  1918. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  1919. break;
  1920. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  1921. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  1922. break;
  1923. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  1924. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  1925. break;
  1926. default:
  1927. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  1928. afe_port_id = -EINVAL;
  1929. }
  1930. return afe_port_id;
  1931. }
  1932. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  1933. {
  1934. u32 bit_per_sample = 0;
  1935. switch (bit_format) {
  1936. case SNDRV_PCM_FORMAT_S32_LE:
  1937. case SNDRV_PCM_FORMAT_S24_3LE:
  1938. case SNDRV_PCM_FORMAT_S24_LE:
  1939. bit_per_sample = 32;
  1940. break;
  1941. case SNDRV_PCM_FORMAT_S16_LE:
  1942. default:
  1943. bit_per_sample = 16;
  1944. break;
  1945. }
  1946. return bit_per_sample;
  1947. }
  1948. static void update_mi2s_clk_val(int dai_id, int stream)
  1949. {
  1950. u32 bit_per_sample = 0;
  1951. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  1952. bit_per_sample =
  1953. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  1954. mi2s_clk[dai_id].clk_freq_in_hz =
  1955. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  1956. } else {
  1957. bit_per_sample =
  1958. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  1959. mi2s_clk[dai_id].clk_freq_in_hz =
  1960. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  1961. }
  1962. }
  1963. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  1964. {
  1965. int ret = 0;
  1966. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1967. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  1968. int port_id = 0;
  1969. int index = cpu_dai->id;
  1970. port_id = msm_get_port_id(rtd->dai_link->id);
  1971. if (port_id < 0) {
  1972. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  1973. ret = port_id;
  1974. goto err;
  1975. }
  1976. if (enable) {
  1977. update_mi2s_clk_val(index, substream->stream);
  1978. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  1979. mi2s_clk[index].clk_freq_in_hz);
  1980. }
  1981. mi2s_clk[index].enable = enable;
  1982. ret = afe_set_lpass_clock_v2(port_id,
  1983. &mi2s_clk[index]);
  1984. if (ret < 0) {
  1985. dev_err(rtd->card->dev,
  1986. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  1987. __func__, port_id, ret);
  1988. goto err;
  1989. }
  1990. err:
  1991. return ret;
  1992. }
  1993. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1994. {
  1995. int idx = 0;
  1996. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1997. sizeof("WSA_CDC_DMA_RX_0")))
  1998. idx = WSA_CDC_DMA_RX_0;
  1999. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  2000. sizeof("WSA_CDC_DMA_RX_0")))
  2001. idx = WSA_CDC_DMA_RX_1;
  2002. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2003. sizeof("RX_CDC_DMA_RX_0")))
  2004. idx = RX_CDC_DMA_RX_0;
  2005. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2006. sizeof("RX_CDC_DMA_RX_1")))
  2007. idx = RX_CDC_DMA_RX_1;
  2008. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2009. sizeof("RX_CDC_DMA_RX_2")))
  2010. idx = RX_CDC_DMA_RX_2;
  2011. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2012. sizeof("RX_CDC_DMA_RX_3")))
  2013. idx = RX_CDC_DMA_RX_3;
  2014. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2015. sizeof("RX_CDC_DMA_RX_5")))
  2016. idx = RX_CDC_DMA_RX_5;
  2017. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  2018. sizeof("WSA_CDC_DMA_TX_0")))
  2019. idx = WSA_CDC_DMA_TX_0;
  2020. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  2021. sizeof("WSA_CDC_DMA_TX_1")))
  2022. idx = WSA_CDC_DMA_TX_1;
  2023. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  2024. sizeof("WSA_CDC_DMA_TX_2")))
  2025. idx = WSA_CDC_DMA_TX_2;
  2026. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2027. sizeof("TX_CDC_DMA_TX_0")))
  2028. idx = TX_CDC_DMA_TX_0;
  2029. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2030. sizeof("TX_CDC_DMA_TX_3")))
  2031. idx = TX_CDC_DMA_TX_3;
  2032. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2033. sizeof("TX_CDC_DMA_TX_4")))
  2034. idx = TX_CDC_DMA_TX_4;
  2035. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2036. sizeof("VA_CDC_DMA_TX_0")))
  2037. idx = VA_CDC_DMA_TX_0;
  2038. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2039. sizeof("VA_CDC_DMA_TX_1")))
  2040. idx = VA_CDC_DMA_TX_1;
  2041. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2042. sizeof("VA_CDC_DMA_TX_2")))
  2043. idx = VA_CDC_DMA_TX_2;
  2044. else {
  2045. pr_err("%s: unsupported channel: %s\n",
  2046. __func__, kcontrol->id.name);
  2047. return -EINVAL;
  2048. }
  2049. return idx;
  2050. }
  2051. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2052. struct snd_ctl_elem_value *ucontrol)
  2053. {
  2054. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2055. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2056. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2057. return ch_num;
  2058. }
  2059. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2060. cdc_dma_rx_cfg[ch_num].channels - 1);
  2061. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2062. return 0;
  2063. }
  2064. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2065. struct snd_ctl_elem_value *ucontrol)
  2066. {
  2067. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2068. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2069. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2070. return ch_num;
  2071. }
  2072. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2073. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2074. cdc_dma_rx_cfg[ch_num].channels);
  2075. return 1;
  2076. }
  2077. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2078. struct snd_ctl_elem_value *ucontrol)
  2079. {
  2080. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2081. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2082. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2083. return ch_num;
  2084. }
  2085. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2086. case SNDRV_PCM_FORMAT_S32_LE:
  2087. ucontrol->value.integer.value[0] = 3;
  2088. break;
  2089. case SNDRV_PCM_FORMAT_S24_3LE:
  2090. ucontrol->value.integer.value[0] = 2;
  2091. break;
  2092. case SNDRV_PCM_FORMAT_S24_LE:
  2093. ucontrol->value.integer.value[0] = 1;
  2094. break;
  2095. case SNDRV_PCM_FORMAT_S16_LE:
  2096. default:
  2097. ucontrol->value.integer.value[0] = 0;
  2098. break;
  2099. }
  2100. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2101. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2102. ucontrol->value.integer.value[0]);
  2103. return 0;
  2104. }
  2105. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2106. struct snd_ctl_elem_value *ucontrol)
  2107. {
  2108. int rc = 0;
  2109. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2110. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2111. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2112. return ch_num;
  2113. }
  2114. switch (ucontrol->value.integer.value[0]) {
  2115. case 3:
  2116. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2117. break;
  2118. case 2:
  2119. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2120. break;
  2121. case 1:
  2122. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2123. break;
  2124. case 0:
  2125. default:
  2126. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2127. break;
  2128. }
  2129. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2130. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2131. ucontrol->value.integer.value[0]);
  2132. return rc;
  2133. }
  2134. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2135. {
  2136. int sample_rate_val = 0;
  2137. switch (sample_rate) {
  2138. case SAMPLING_RATE_8KHZ:
  2139. sample_rate_val = 0;
  2140. break;
  2141. case SAMPLING_RATE_11P025KHZ:
  2142. sample_rate_val = 1;
  2143. break;
  2144. case SAMPLING_RATE_16KHZ:
  2145. sample_rate_val = 2;
  2146. break;
  2147. case SAMPLING_RATE_22P05KHZ:
  2148. sample_rate_val = 3;
  2149. break;
  2150. case SAMPLING_RATE_32KHZ:
  2151. sample_rate_val = 4;
  2152. break;
  2153. case SAMPLING_RATE_44P1KHZ:
  2154. sample_rate_val = 5;
  2155. break;
  2156. case SAMPLING_RATE_48KHZ:
  2157. sample_rate_val = 6;
  2158. break;
  2159. case SAMPLING_RATE_88P2KHZ:
  2160. sample_rate_val = 7;
  2161. break;
  2162. case SAMPLING_RATE_96KHZ:
  2163. sample_rate_val = 8;
  2164. break;
  2165. case SAMPLING_RATE_176P4KHZ:
  2166. sample_rate_val = 9;
  2167. break;
  2168. case SAMPLING_RATE_192KHZ:
  2169. sample_rate_val = 10;
  2170. break;
  2171. case SAMPLING_RATE_352P8KHZ:
  2172. sample_rate_val = 11;
  2173. break;
  2174. case SAMPLING_RATE_384KHZ:
  2175. sample_rate_val = 12;
  2176. break;
  2177. default:
  2178. sample_rate_val = 6;
  2179. break;
  2180. }
  2181. return sample_rate_val;
  2182. }
  2183. static int cdc_dma_get_sample_rate(int value)
  2184. {
  2185. int sample_rate = 0;
  2186. switch (value) {
  2187. case 0:
  2188. sample_rate = SAMPLING_RATE_8KHZ;
  2189. break;
  2190. case 1:
  2191. sample_rate = SAMPLING_RATE_11P025KHZ;
  2192. break;
  2193. case 2:
  2194. sample_rate = SAMPLING_RATE_16KHZ;
  2195. break;
  2196. case 3:
  2197. sample_rate = SAMPLING_RATE_22P05KHZ;
  2198. break;
  2199. case 4:
  2200. sample_rate = SAMPLING_RATE_32KHZ;
  2201. break;
  2202. case 5:
  2203. sample_rate = SAMPLING_RATE_44P1KHZ;
  2204. break;
  2205. case 6:
  2206. sample_rate = SAMPLING_RATE_48KHZ;
  2207. break;
  2208. case 7:
  2209. sample_rate = SAMPLING_RATE_88P2KHZ;
  2210. break;
  2211. case 8:
  2212. sample_rate = SAMPLING_RATE_96KHZ;
  2213. break;
  2214. case 9:
  2215. sample_rate = SAMPLING_RATE_176P4KHZ;
  2216. break;
  2217. case 10:
  2218. sample_rate = SAMPLING_RATE_192KHZ;
  2219. break;
  2220. case 11:
  2221. sample_rate = SAMPLING_RATE_352P8KHZ;
  2222. break;
  2223. case 12:
  2224. sample_rate = SAMPLING_RATE_384KHZ;
  2225. break;
  2226. default:
  2227. sample_rate = SAMPLING_RATE_48KHZ;
  2228. break;
  2229. }
  2230. return sample_rate;
  2231. }
  2232. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2233. struct snd_ctl_elem_value *ucontrol)
  2234. {
  2235. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2236. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2237. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2238. return ch_num;
  2239. }
  2240. ucontrol->value.enumerated.item[0] =
  2241. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2242. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2243. cdc_dma_rx_cfg[ch_num].sample_rate);
  2244. return 0;
  2245. }
  2246. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2247. struct snd_ctl_elem_value *ucontrol)
  2248. {
  2249. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2250. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2251. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2252. return ch_num;
  2253. }
  2254. cdc_dma_rx_cfg[ch_num].sample_rate =
  2255. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2256. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2257. __func__, ucontrol->value.enumerated.item[0],
  2258. cdc_dma_rx_cfg[ch_num].sample_rate);
  2259. return 0;
  2260. }
  2261. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2262. struct snd_ctl_elem_value *ucontrol)
  2263. {
  2264. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2265. if (ch_num < 0) {
  2266. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2267. return ch_num;
  2268. }
  2269. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2270. cdc_dma_tx_cfg[ch_num].channels);
  2271. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2272. return 0;
  2273. }
  2274. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2275. struct snd_ctl_elem_value *ucontrol)
  2276. {
  2277. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2278. if (ch_num < 0) {
  2279. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2280. return ch_num;
  2281. }
  2282. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2283. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2284. cdc_dma_tx_cfg[ch_num].channels);
  2285. return 1;
  2286. }
  2287. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2288. struct snd_ctl_elem_value *ucontrol)
  2289. {
  2290. int sample_rate_val;
  2291. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2292. if (ch_num < 0) {
  2293. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2294. return ch_num;
  2295. }
  2296. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2297. case SAMPLING_RATE_384KHZ:
  2298. sample_rate_val = 12;
  2299. break;
  2300. case SAMPLING_RATE_352P8KHZ:
  2301. sample_rate_val = 11;
  2302. break;
  2303. case SAMPLING_RATE_192KHZ:
  2304. sample_rate_val = 10;
  2305. break;
  2306. case SAMPLING_RATE_176P4KHZ:
  2307. sample_rate_val = 9;
  2308. break;
  2309. case SAMPLING_RATE_96KHZ:
  2310. sample_rate_val = 8;
  2311. break;
  2312. case SAMPLING_RATE_88P2KHZ:
  2313. sample_rate_val = 7;
  2314. break;
  2315. case SAMPLING_RATE_48KHZ:
  2316. sample_rate_val = 6;
  2317. break;
  2318. case SAMPLING_RATE_44P1KHZ:
  2319. sample_rate_val = 5;
  2320. break;
  2321. case SAMPLING_RATE_32KHZ:
  2322. sample_rate_val = 4;
  2323. break;
  2324. case SAMPLING_RATE_22P05KHZ:
  2325. sample_rate_val = 3;
  2326. break;
  2327. case SAMPLING_RATE_16KHZ:
  2328. sample_rate_val = 2;
  2329. break;
  2330. case SAMPLING_RATE_11P025KHZ:
  2331. sample_rate_val = 1;
  2332. break;
  2333. case SAMPLING_RATE_8KHZ:
  2334. sample_rate_val = 0;
  2335. break;
  2336. default:
  2337. sample_rate_val = 6;
  2338. break;
  2339. }
  2340. ucontrol->value.integer.value[0] = sample_rate_val;
  2341. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2342. cdc_dma_tx_cfg[ch_num].sample_rate);
  2343. return 0;
  2344. }
  2345. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2346. struct snd_ctl_elem_value *ucontrol)
  2347. {
  2348. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2349. if (ch_num < 0) {
  2350. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2351. return ch_num;
  2352. }
  2353. switch (ucontrol->value.integer.value[0]) {
  2354. case 12:
  2355. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2356. break;
  2357. case 11:
  2358. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2359. break;
  2360. case 10:
  2361. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2362. break;
  2363. case 9:
  2364. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2365. break;
  2366. case 8:
  2367. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2368. break;
  2369. case 7:
  2370. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2371. break;
  2372. case 6:
  2373. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2374. break;
  2375. case 5:
  2376. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2377. break;
  2378. case 4:
  2379. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2380. break;
  2381. case 3:
  2382. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2383. break;
  2384. case 2:
  2385. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2386. break;
  2387. case 1:
  2388. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2389. break;
  2390. case 0:
  2391. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2392. break;
  2393. default:
  2394. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2395. break;
  2396. }
  2397. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2398. __func__, ucontrol->value.integer.value[0],
  2399. cdc_dma_tx_cfg[ch_num].sample_rate);
  2400. return 0;
  2401. }
  2402. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2403. struct snd_ctl_elem_value *ucontrol)
  2404. {
  2405. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2406. if (ch_num < 0) {
  2407. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2408. return ch_num;
  2409. }
  2410. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2411. case SNDRV_PCM_FORMAT_S32_LE:
  2412. ucontrol->value.integer.value[0] = 3;
  2413. break;
  2414. case SNDRV_PCM_FORMAT_S24_3LE:
  2415. ucontrol->value.integer.value[0] = 2;
  2416. break;
  2417. case SNDRV_PCM_FORMAT_S24_LE:
  2418. ucontrol->value.integer.value[0] = 1;
  2419. break;
  2420. case SNDRV_PCM_FORMAT_S16_LE:
  2421. default:
  2422. ucontrol->value.integer.value[0] = 0;
  2423. break;
  2424. }
  2425. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2426. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2427. ucontrol->value.integer.value[0]);
  2428. return 0;
  2429. }
  2430. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2431. struct snd_ctl_elem_value *ucontrol)
  2432. {
  2433. int rc = 0;
  2434. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2435. if (ch_num < 0) {
  2436. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2437. return ch_num;
  2438. }
  2439. switch (ucontrol->value.integer.value[0]) {
  2440. case 3:
  2441. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2442. break;
  2443. case 2:
  2444. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2445. break;
  2446. case 1:
  2447. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2448. break;
  2449. case 0:
  2450. default:
  2451. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2452. break;
  2453. }
  2454. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2455. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2456. ucontrol->value.integer.value[0]);
  2457. return rc;
  2458. }
  2459. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2460. {
  2461. int idx = 0;
  2462. switch (be_id) {
  2463. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  2464. idx = WSA_CDC_DMA_RX_0;
  2465. break;
  2466. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  2467. idx = WSA_CDC_DMA_TX_0;
  2468. break;
  2469. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  2470. idx = WSA_CDC_DMA_RX_1;
  2471. break;
  2472. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  2473. idx = WSA_CDC_DMA_TX_1;
  2474. break;
  2475. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  2476. idx = WSA_CDC_DMA_TX_2;
  2477. break;
  2478. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2479. idx = RX_CDC_DMA_RX_0;
  2480. break;
  2481. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2482. idx = RX_CDC_DMA_RX_1;
  2483. break;
  2484. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2485. idx = RX_CDC_DMA_RX_2;
  2486. break;
  2487. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2488. idx = RX_CDC_DMA_RX_3;
  2489. break;
  2490. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2491. idx = RX_CDC_DMA_RX_5;
  2492. break;
  2493. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2494. idx = TX_CDC_DMA_TX_0;
  2495. break;
  2496. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2497. idx = TX_CDC_DMA_TX_3;
  2498. break;
  2499. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2500. idx = TX_CDC_DMA_TX_4;
  2501. break;
  2502. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2503. idx = VA_CDC_DMA_TX_0;
  2504. break;
  2505. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2506. idx = VA_CDC_DMA_TX_1;
  2507. break;
  2508. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2509. idx = VA_CDC_DMA_TX_2;
  2510. break;
  2511. default:
  2512. idx = RX_CDC_DMA_RX_0;
  2513. break;
  2514. }
  2515. return idx;
  2516. }
  2517. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2518. struct snd_ctl_elem_value *ucontrol)
  2519. {
  2520. /*
  2521. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2522. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2523. * value.
  2524. */
  2525. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2526. case SAMPLING_RATE_96KHZ:
  2527. ucontrol->value.integer.value[0] = 5;
  2528. break;
  2529. case SAMPLING_RATE_88P2KHZ:
  2530. ucontrol->value.integer.value[0] = 4;
  2531. break;
  2532. case SAMPLING_RATE_48KHZ:
  2533. ucontrol->value.integer.value[0] = 3;
  2534. break;
  2535. case SAMPLING_RATE_44P1KHZ:
  2536. ucontrol->value.integer.value[0] = 2;
  2537. break;
  2538. case SAMPLING_RATE_16KHZ:
  2539. ucontrol->value.integer.value[0] = 1;
  2540. break;
  2541. case SAMPLING_RATE_8KHZ:
  2542. default:
  2543. ucontrol->value.integer.value[0] = 0;
  2544. break;
  2545. }
  2546. pr_debug("%s: sample rate = %d\n", __func__,
  2547. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2548. return 0;
  2549. }
  2550. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2551. struct snd_ctl_elem_value *ucontrol)
  2552. {
  2553. switch (ucontrol->value.integer.value[0]) {
  2554. case 1:
  2555. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2556. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2557. break;
  2558. case 2:
  2559. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2560. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2561. break;
  2562. case 3:
  2563. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2564. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2565. break;
  2566. case 4:
  2567. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2568. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2569. break;
  2570. case 5:
  2571. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2572. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2573. break;
  2574. case 0:
  2575. default:
  2576. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2577. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2578. break;
  2579. }
  2580. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2581. __func__,
  2582. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2583. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2584. ucontrol->value.enumerated.item[0]);
  2585. return 0;
  2586. }
  2587. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2588. struct snd_ctl_elem_value *ucontrol)
  2589. {
  2590. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2591. case SAMPLING_RATE_96KHZ:
  2592. ucontrol->value.integer.value[0] = 5;
  2593. break;
  2594. case SAMPLING_RATE_88P2KHZ:
  2595. ucontrol->value.integer.value[0] = 4;
  2596. break;
  2597. case SAMPLING_RATE_48KHZ:
  2598. ucontrol->value.integer.value[0] = 3;
  2599. break;
  2600. case SAMPLING_RATE_44P1KHZ:
  2601. ucontrol->value.integer.value[0] = 2;
  2602. break;
  2603. case SAMPLING_RATE_16KHZ:
  2604. ucontrol->value.integer.value[0] = 1;
  2605. break;
  2606. case SAMPLING_RATE_8KHZ:
  2607. default:
  2608. ucontrol->value.integer.value[0] = 0;
  2609. break;
  2610. }
  2611. pr_debug("%s: sample rate rx = %d\n", __func__,
  2612. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2613. return 0;
  2614. }
  2615. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  2616. struct snd_ctl_elem_value *ucontrol)
  2617. {
  2618. switch (ucontrol->value.integer.value[0]) {
  2619. case 1:
  2620. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2621. break;
  2622. case 2:
  2623. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2624. break;
  2625. case 3:
  2626. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2627. break;
  2628. case 4:
  2629. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2630. break;
  2631. case 5:
  2632. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2633. break;
  2634. case 0:
  2635. default:
  2636. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2637. break;
  2638. }
  2639. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  2640. __func__,
  2641. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2642. ucontrol->value.enumerated.item[0]);
  2643. return 0;
  2644. }
  2645. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  2646. struct snd_ctl_elem_value *ucontrol)
  2647. {
  2648. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  2649. case SAMPLING_RATE_96KHZ:
  2650. ucontrol->value.integer.value[0] = 5;
  2651. break;
  2652. case SAMPLING_RATE_88P2KHZ:
  2653. ucontrol->value.integer.value[0] = 4;
  2654. break;
  2655. case SAMPLING_RATE_48KHZ:
  2656. ucontrol->value.integer.value[0] = 3;
  2657. break;
  2658. case SAMPLING_RATE_44P1KHZ:
  2659. ucontrol->value.integer.value[0] = 2;
  2660. break;
  2661. case SAMPLING_RATE_16KHZ:
  2662. ucontrol->value.integer.value[0] = 1;
  2663. break;
  2664. case SAMPLING_RATE_8KHZ:
  2665. default:
  2666. ucontrol->value.integer.value[0] = 0;
  2667. break;
  2668. }
  2669. pr_debug("%s: sample rate tx = %d\n", __func__,
  2670. slim_tx_cfg[SLIM_TX_7].sample_rate);
  2671. return 0;
  2672. }
  2673. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  2674. struct snd_ctl_elem_value *ucontrol)
  2675. {
  2676. switch (ucontrol->value.integer.value[0]) {
  2677. case 1:
  2678. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2679. break;
  2680. case 2:
  2681. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2682. break;
  2683. case 3:
  2684. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2685. break;
  2686. case 4:
  2687. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2688. break;
  2689. case 5:
  2690. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2691. break;
  2692. case 0:
  2693. default:
  2694. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2695. break;
  2696. }
  2697. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  2698. __func__,
  2699. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2700. ucontrol->value.enumerated.item[0]);
  2701. return 0;
  2702. }
  2703. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  2704. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2705. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2706. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2707. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2708. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  2709. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2710. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  2711. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2712. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  2713. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2714. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  2715. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2716. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  2717. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2718. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2719. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2720. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2721. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2722. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2723. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2724. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  2725. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2726. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  2727. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2728. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  2729. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2730. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2731. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2732. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2733. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2734. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  2735. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2736. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2737. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2738. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2739. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2740. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc_dma_rx_0_format,
  2741. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2742. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc_dma_rx_1_format,
  2743. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2744. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc_dma_rx_2_format,
  2745. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2746. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc_dma_rx_3_format,
  2747. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2748. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc_dma_rx_5_format,
  2749. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2750. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2751. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2752. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2753. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2754. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  2755. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2756. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  2757. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2758. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  2759. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2760. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2761. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2762. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2763. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2764. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  2765. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2766. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2767. wsa_cdc_dma_rx_0_sample_rate,
  2768. cdc_dma_rx_sample_rate_get,
  2769. cdc_dma_rx_sample_rate_put),
  2770. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2771. wsa_cdc_dma_rx_1_sample_rate,
  2772. cdc_dma_rx_sample_rate_get,
  2773. cdc_dma_rx_sample_rate_put),
  2774. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2775. rx_cdc_dma_rx_0_sample_rate,
  2776. cdc_dma_rx_sample_rate_get,
  2777. cdc_dma_rx_sample_rate_put),
  2778. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2779. rx_cdc_dma_rx_1_sample_rate,
  2780. cdc_dma_rx_sample_rate_get,
  2781. cdc_dma_rx_sample_rate_put),
  2782. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2783. rx_cdc_dma_rx_2_sample_rate,
  2784. cdc_dma_rx_sample_rate_get,
  2785. cdc_dma_rx_sample_rate_put),
  2786. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2787. rx_cdc_dma_rx_3_sample_rate,
  2788. cdc_dma_rx_sample_rate_get,
  2789. cdc_dma_rx_sample_rate_put),
  2790. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2791. rx_cdc_dma_rx_5_sample_rate,
  2792. cdc_dma_rx_sample_rate_get,
  2793. cdc_dma_rx_sample_rate_put),
  2794. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2795. wsa_cdc_dma_tx_0_sample_rate,
  2796. cdc_dma_tx_sample_rate_get,
  2797. cdc_dma_tx_sample_rate_put),
  2798. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2799. wsa_cdc_dma_tx_1_sample_rate,
  2800. cdc_dma_tx_sample_rate_get,
  2801. cdc_dma_tx_sample_rate_put),
  2802. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2803. wsa_cdc_dma_tx_2_sample_rate,
  2804. cdc_dma_tx_sample_rate_get,
  2805. cdc_dma_tx_sample_rate_put),
  2806. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  2807. tx_cdc_dma_tx_0_sample_rate,
  2808. cdc_dma_tx_sample_rate_get,
  2809. cdc_dma_tx_sample_rate_put),
  2810. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  2811. tx_cdc_dma_tx_3_sample_rate,
  2812. cdc_dma_tx_sample_rate_get,
  2813. cdc_dma_tx_sample_rate_put),
  2814. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  2815. tx_cdc_dma_tx_4_sample_rate,
  2816. cdc_dma_tx_sample_rate_get,
  2817. cdc_dma_tx_sample_rate_put),
  2818. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2819. va_cdc_dma_tx_0_sample_rate,
  2820. cdc_dma_tx_sample_rate_get,
  2821. cdc_dma_tx_sample_rate_put),
  2822. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2823. va_cdc_dma_tx_1_sample_rate,
  2824. cdc_dma_tx_sample_rate_get,
  2825. cdc_dma_tx_sample_rate_put),
  2826. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  2827. va_cdc_dma_tx_2_sample_rate,
  2828. cdc_dma_tx_sample_rate_get,
  2829. cdc_dma_tx_sample_rate_put),
  2830. };
  2831. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  2832. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2833. usb_audio_rx_sample_rate_get,
  2834. usb_audio_rx_sample_rate_put),
  2835. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2836. usb_audio_tx_sample_rate_get,
  2837. usb_audio_tx_sample_rate_put),
  2838. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2839. tdm_rx_sample_rate_get,
  2840. tdm_rx_sample_rate_put),
  2841. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2842. tdm_rx_sample_rate_get,
  2843. tdm_rx_sample_rate_put),
  2844. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2845. tdm_rx_sample_rate_get,
  2846. tdm_rx_sample_rate_put),
  2847. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2848. tdm_tx_sample_rate_get,
  2849. tdm_tx_sample_rate_put),
  2850. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2851. tdm_tx_sample_rate_get,
  2852. tdm_tx_sample_rate_put),
  2853. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2854. tdm_tx_sample_rate_get,
  2855. tdm_tx_sample_rate_put),
  2856. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2857. aux_pcm_rx_sample_rate_get,
  2858. aux_pcm_rx_sample_rate_put),
  2859. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2860. aux_pcm_rx_sample_rate_get,
  2861. aux_pcm_rx_sample_rate_put),
  2862. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2863. aux_pcm_rx_sample_rate_get,
  2864. aux_pcm_rx_sample_rate_put),
  2865. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2866. aux_pcm_tx_sample_rate_get,
  2867. aux_pcm_tx_sample_rate_put),
  2868. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2869. aux_pcm_tx_sample_rate_get,
  2870. aux_pcm_tx_sample_rate_put),
  2871. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2872. aux_pcm_tx_sample_rate_get,
  2873. aux_pcm_tx_sample_rate_put),
  2874. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2875. mi2s_rx_sample_rate_get,
  2876. mi2s_rx_sample_rate_put),
  2877. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2878. mi2s_rx_sample_rate_get,
  2879. mi2s_rx_sample_rate_put),
  2880. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2881. mi2s_rx_sample_rate_get,
  2882. mi2s_rx_sample_rate_put),
  2883. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  2884. mi2s_tx_sample_rate_get,
  2885. mi2s_tx_sample_rate_put),
  2886. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2887. mi2s_tx_sample_rate_get,
  2888. mi2s_tx_sample_rate_put),
  2889. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2890. mi2s_tx_sample_rate_get,
  2891. mi2s_tx_sample_rate_put),
  2892. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2893. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2894. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2895. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2896. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2897. tdm_rx_format_get,
  2898. tdm_rx_format_put),
  2899. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2900. tdm_rx_format_get,
  2901. tdm_rx_format_put),
  2902. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2903. tdm_rx_format_get,
  2904. tdm_rx_format_put),
  2905. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2906. tdm_tx_format_get,
  2907. tdm_tx_format_put),
  2908. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2909. tdm_tx_format_get,
  2910. tdm_tx_format_put),
  2911. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2912. tdm_tx_format_get,
  2913. tdm_tx_format_put),
  2914. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2915. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2916. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2917. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2918. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2919. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2920. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2921. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2922. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2923. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2924. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2925. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2926. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2927. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2928. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2929. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2930. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2931. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2932. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2933. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2934. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2935. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2936. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2937. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2938. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2939. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2940. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2941. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2942. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2943. proxy_rx_ch_get, proxy_rx_ch_put),
  2944. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2945. tdm_rx_ch_get,
  2946. tdm_rx_ch_put),
  2947. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2948. tdm_rx_ch_get,
  2949. tdm_rx_ch_put),
  2950. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2951. tdm_rx_ch_get,
  2952. tdm_rx_ch_put),
  2953. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2954. tdm_tx_ch_get,
  2955. tdm_tx_ch_put),
  2956. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2957. tdm_tx_ch_get,
  2958. tdm_tx_ch_put),
  2959. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2960. tdm_tx_ch_get,
  2961. tdm_tx_ch_put),
  2962. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2963. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2964. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2965. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2966. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2967. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2968. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2969. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2970. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2971. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2972. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2973. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2974. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  2975. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  2976. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  2977. ext_disp_rx_format_get, ext_disp_rx_format_put),
  2978. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  2979. ext_disp_rx_sample_rate_get,
  2980. ext_disp_rx_sample_rate_put),
  2981. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2982. msm_bt_sample_rate_get,
  2983. msm_bt_sample_rate_put),
  2984. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  2985. msm_bt_sample_rate_rx_get,
  2986. msm_bt_sample_rate_rx_put),
  2987. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  2988. msm_bt_sample_rate_tx_get,
  2989. msm_bt_sample_rate_tx_put),
  2990. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  2991. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  2992. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2993. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2994. };
  2995. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2996. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2997. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2998. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2999. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3000. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3001. aux_pcm_rx_sample_rate_get,
  3002. aux_pcm_rx_sample_rate_put),
  3003. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3004. aux_pcm_tx_sample_rate_get,
  3005. aux_pcm_tx_sample_rate_put),
  3006. };
  3007. static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
  3008. {
  3009. int idx;
  3010. switch (be_id) {
  3011. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3012. idx = EXT_DISP_RX_IDX_DP;
  3013. break;
  3014. default:
  3015. pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
  3016. idx = -EINVAL;
  3017. break;
  3018. }
  3019. return idx;
  3020. }
  3021. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3022. struct snd_pcm_hw_params *params)
  3023. {
  3024. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3025. struct snd_interval *rate = hw_param_interval(params,
  3026. SNDRV_PCM_HW_PARAM_RATE);
  3027. struct snd_interval *channels = hw_param_interval(params,
  3028. SNDRV_PCM_HW_PARAM_CHANNELS);
  3029. int idx = 0, rc = 0;
  3030. pr_debug("%s: format = %d, rate = %d\n",
  3031. __func__, params_format(params), params_rate(params));
  3032. switch (dai_link->id) {
  3033. case MSM_BACKEND_DAI_USB_RX:
  3034. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3035. usb_rx_cfg.bit_format);
  3036. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3037. channels->min = channels->max = usb_rx_cfg.channels;
  3038. break;
  3039. case MSM_BACKEND_DAI_USB_TX:
  3040. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3041. usb_tx_cfg.bit_format);
  3042. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3043. channels->min = channels->max = usb_tx_cfg.channels;
  3044. break;
  3045. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3046. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  3047. if (idx < 0) {
  3048. pr_err("%s: Incorrect ext disp idx %d\n",
  3049. __func__, idx);
  3050. rc = idx;
  3051. goto done;
  3052. }
  3053. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3054. ext_disp_rx_cfg[idx].bit_format);
  3055. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  3056. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  3057. break;
  3058. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3059. channels->min = channels->max = proxy_rx_cfg.channels;
  3060. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3061. break;
  3062. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3063. channels->min = channels->max =
  3064. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3065. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3066. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3067. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3068. break;
  3069. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3070. channels->min = channels->max =
  3071. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3072. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3073. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3074. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3075. break;
  3076. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3077. channels->min = channels->max =
  3078. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3079. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3080. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3081. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3082. break;
  3083. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3084. channels->min = channels->max =
  3085. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3086. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3087. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3088. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3089. break;
  3090. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3091. channels->min = channels->max =
  3092. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3093. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3094. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3095. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3096. break;
  3097. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3098. channels->min = channels->max =
  3099. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3100. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3101. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3102. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3103. break;
  3104. case MSM_BACKEND_DAI_AUXPCM_RX:
  3105. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3106. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3107. rate->min = rate->max =
  3108. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3109. channels->min = channels->max =
  3110. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3111. break;
  3112. case MSM_BACKEND_DAI_AUXPCM_TX:
  3113. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3114. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3115. rate->min = rate->max =
  3116. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3117. channels->min = channels->max =
  3118. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3119. break;
  3120. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3121. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3122. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3123. rate->min = rate->max =
  3124. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3125. channels->min = channels->max =
  3126. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3127. break;
  3128. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3129. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3130. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3131. rate->min = rate->max =
  3132. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3133. channels->min = channels->max =
  3134. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3135. break;
  3136. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3137. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3138. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3139. rate->min = rate->max =
  3140. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3141. channels->min = channels->max =
  3142. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3143. break;
  3144. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3145. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3146. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3147. rate->min = rate->max =
  3148. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3149. channels->min = channels->max =
  3150. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3151. break;
  3152. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3153. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3154. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3155. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3156. channels->min = channels->max =
  3157. mi2s_rx_cfg[PRIM_MI2S].channels;
  3158. break;
  3159. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3160. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3161. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3162. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3163. channels->min = channels->max =
  3164. mi2s_tx_cfg[PRIM_MI2S].channels;
  3165. break;
  3166. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3167. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3168. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3169. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3170. channels->min = channels->max =
  3171. mi2s_rx_cfg[SEC_MI2S].channels;
  3172. break;
  3173. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3174. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3175. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3176. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3177. channels->min = channels->max =
  3178. mi2s_tx_cfg[SEC_MI2S].channels;
  3179. break;
  3180. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3181. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3182. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3183. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3184. channels->min = channels->max =
  3185. mi2s_rx_cfg[TERT_MI2S].channels;
  3186. break;
  3187. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3188. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3189. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3190. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3191. channels->min = channels->max =
  3192. mi2s_tx_cfg[TERT_MI2S].channels;
  3193. break;
  3194. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3195. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3196. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3197. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3198. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3199. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3200. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3201. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3202. cdc_dma_rx_cfg[idx].bit_format);
  3203. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3204. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3205. break;
  3206. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3207. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3208. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3209. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3210. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3211. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3212. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3213. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3214. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3215. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3216. cdc_dma_tx_cfg[idx].bit_format);
  3217. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3218. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3219. break;
  3220. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3221. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3222. SNDRV_PCM_FORMAT_S32_LE);
  3223. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3224. channels->min = channels->max = msm_vi_feed_tx_ch;
  3225. break;
  3226. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3227. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3228. slim_rx_cfg[SLIM_RX_7].bit_format);
  3229. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3230. channels->min = channels->max =
  3231. slim_rx_cfg[SLIM_RX_7].channels;
  3232. break;
  3233. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3234. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3235. channels->min = channels->max =
  3236. slim_tx_cfg[SLIM_TX_7].channels;
  3237. break;
  3238. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3239. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3240. channels->min = channels->max =
  3241. slim_tx_cfg[SLIM_TX_8].channels;
  3242. break;
  3243. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3244. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3245. afe_loopback_tx_cfg[idx].bit_format);
  3246. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3247. channels->min = channels->max =
  3248. afe_loopback_tx_cfg[idx].channels;
  3249. break;
  3250. default:
  3251. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3252. break;
  3253. }
  3254. done:
  3255. return rc;
  3256. }
  3257. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3258. {
  3259. struct snd_soc_card *card = component->card;
  3260. struct msm_asoc_mach_data *pdata =
  3261. snd_soc_card_get_drvdata(card);
  3262. if (!pdata->fsa_handle)
  3263. return false;
  3264. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3265. }
  3266. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3267. {
  3268. int value = 0;
  3269. bool ret = false;
  3270. struct snd_soc_card *card;
  3271. struct msm_asoc_mach_data *pdata;
  3272. if (!component) {
  3273. pr_err("%s component is NULL\n", __func__);
  3274. return false;
  3275. }
  3276. card = component->card;
  3277. pdata = snd_soc_card_get_drvdata(card);
  3278. if (!pdata)
  3279. return false;
  3280. if (wcd_mbhc_cfg.enable_usbc_analog)
  3281. return msm_usbc_swap_gnd_mic(component, active);
  3282. /* if usbc is not defined, swap using us_euro_gpio_p */
  3283. if (pdata->us_euro_gpio_p) {
  3284. value = msm_cdc_pinctrl_get_state(
  3285. pdata->us_euro_gpio_p);
  3286. if (value)
  3287. msm_cdc_pinctrl_select_sleep_state(
  3288. pdata->us_euro_gpio_p);
  3289. else
  3290. msm_cdc_pinctrl_select_active_state(
  3291. pdata->us_euro_gpio_p);
  3292. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  3293. __func__, value, !value);
  3294. ret = true;
  3295. }
  3296. return ret;
  3297. }
  3298. static int kona_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  3299. struct snd_pcm_hw_params *params)
  3300. {
  3301. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3302. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3303. int ret = 0;
  3304. int slot_width = 32;
  3305. int channels, slots;
  3306. unsigned int slot_mask, rate, clk_freq;
  3307. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  3308. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  3309. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  3310. switch (cpu_dai->id) {
  3311. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3312. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3313. break;
  3314. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3315. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3316. break;
  3317. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3318. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3319. break;
  3320. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3321. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3322. break;
  3323. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3324. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3325. break;
  3326. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3327. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3328. break;
  3329. default:
  3330. pr_err("%s: dai id 0x%x not supported\n",
  3331. __func__, cpu_dai->id);
  3332. return -EINVAL;
  3333. }
  3334. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3335. /*2 slot config - bits 0 and 1 set for the first two slots */
  3336. slot_mask = 0x0000FFFF >> (16 - slots);
  3337. channels = slots;
  3338. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  3339. __func__, slot_width, slots);
  3340. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  3341. slots, slot_width);
  3342. if (ret < 0) {
  3343. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  3344. __func__, ret);
  3345. goto end;
  3346. }
  3347. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3348. 0, NULL, channels, slot_offset);
  3349. if (ret < 0) {
  3350. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  3351. __func__, ret);
  3352. goto end;
  3353. }
  3354. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3355. /*2 slot config - bits 0 and 1 set for the first two slots */
  3356. slot_mask = 0x0000FFFF >> (16 - slots);
  3357. channels = slots;
  3358. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  3359. __func__, slot_width, slots);
  3360. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  3361. slots, slot_width);
  3362. if (ret < 0) {
  3363. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  3364. __func__, ret);
  3365. goto end;
  3366. }
  3367. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3368. channels, slot_offset, 0, NULL);
  3369. if (ret < 0) {
  3370. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  3371. __func__, ret);
  3372. goto end;
  3373. }
  3374. } else {
  3375. ret = -EINVAL;
  3376. pr_err("%s: invalid use case, err:%d\n",
  3377. __func__, ret);
  3378. goto end;
  3379. }
  3380. rate = params_rate(params);
  3381. clk_freq = rate * slot_width * slots;
  3382. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  3383. if (ret < 0)
  3384. pr_err("%s: failed to set tdm clk, err:%d\n",
  3385. __func__, ret);
  3386. end:
  3387. return ret;
  3388. }
  3389. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3390. struct snd_pcm_hw_params *params)
  3391. {
  3392. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3393. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3394. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3395. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3396. int ret = 0;
  3397. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3398. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3399. u32 user_set_tx_ch = 0;
  3400. u32 user_set_rx_ch = 0;
  3401. u32 ch_id;
  3402. ret = snd_soc_dai_get_channel_map(codec_dai,
  3403. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3404. &rx_ch_cdc_dma);
  3405. if (ret < 0) {
  3406. pr_err("%s: failed to get codec chan map, err:%d\n",
  3407. __func__, ret);
  3408. goto err;
  3409. }
  3410. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3411. switch (dai_link->id) {
  3412. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3413. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3414. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3415. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3416. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3417. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3418. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  3419. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  3420. {
  3421. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3422. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3423. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3424. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3425. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3426. user_set_rx_ch, &rx_ch_cdc_dma);
  3427. if (ret < 0) {
  3428. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3429. __func__, ret);
  3430. goto err;
  3431. }
  3432. }
  3433. break;
  3434. }
  3435. } else {
  3436. switch (dai_link->id) {
  3437. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3438. {
  3439. user_set_tx_ch = msm_vi_feed_tx_ch;
  3440. }
  3441. break;
  3442. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3443. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3444. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3445. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3446. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3447. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3448. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3449. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3450. {
  3451. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3452. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3453. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3454. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3455. }
  3456. break;
  3457. }
  3458. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3459. &tx_ch_cdc_dma, 0, 0);
  3460. if (ret < 0) {
  3461. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3462. __func__, ret);
  3463. goto err;
  3464. }
  3465. }
  3466. err:
  3467. return ret;
  3468. }
  3469. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  3470. {
  3471. cpumask_t mask;
  3472. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  3473. pm_qos_remove_request(&substream->latency_pm_qos_req);
  3474. cpumask_clear(&mask);
  3475. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  3476. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  3477. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  3478. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  3479. pm_qos_add_request(&substream->latency_pm_qos_req,
  3480. PM_QOS_CPU_DMA_LATENCY,
  3481. MSM_LL_QOS_VALUE);
  3482. return 0;
  3483. }
  3484. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  3485. {
  3486. int ret = 0;
  3487. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3488. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3489. int index = cpu_dai->id;
  3490. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  3491. dev_dbg(rtd->card->dev,
  3492. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  3493. __func__, substream->name, substream->stream,
  3494. cpu_dai->name, cpu_dai->id);
  3495. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3496. ret = -EINVAL;
  3497. dev_err(rtd->card->dev,
  3498. "%s: CPU DAI id (%d) out of range\n",
  3499. __func__, cpu_dai->id);
  3500. goto err;
  3501. }
  3502. /*
  3503. * Mutex protection in case the same MI2S
  3504. * interface using for both TX and RX so
  3505. * that the same clock won't be enable twice.
  3506. */
  3507. mutex_lock(&mi2s_intf_conf[index].lock);
  3508. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  3509. /* Check if msm needs to provide the clock to the interface */
  3510. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  3511. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  3512. fmt = SND_SOC_DAIFMT_CBM_CFM;
  3513. }
  3514. ret = msm_mi2s_set_sclk(substream, true);
  3515. if (ret < 0) {
  3516. dev_err(rtd->card->dev,
  3517. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  3518. __func__, ret);
  3519. goto clean_up;
  3520. }
  3521. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  3522. if (ret < 0) {
  3523. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  3524. __func__, index, ret);
  3525. goto clk_off;
  3526. }
  3527. }
  3528. clk_off:
  3529. if (ret < 0)
  3530. msm_mi2s_set_sclk(substream, false);
  3531. clean_up:
  3532. if (ret < 0)
  3533. mi2s_intf_conf[index].ref_cnt--;
  3534. mutex_unlock(&mi2s_intf_conf[index].lock);
  3535. err:
  3536. return ret;
  3537. }
  3538. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  3539. {
  3540. int ret = 0;
  3541. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3542. int index = rtd->cpu_dai->id;
  3543. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  3544. substream->name, substream->stream);
  3545. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3546. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  3547. return;
  3548. }
  3549. mutex_lock(&mi2s_intf_conf[index].lock);
  3550. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  3551. ret = msm_mi2s_set_sclk(substream, false);
  3552. if (ret < 0)
  3553. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  3554. __func__, index, ret);
  3555. }
  3556. mutex_unlock(&mi2s_intf_conf[index].lock);
  3557. }
  3558. static int msm_wcn_hw_params_lito(struct snd_pcm_substream *substream,
  3559. struct snd_pcm_hw_params *params)
  3560. {
  3561. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3562. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3563. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3564. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3565. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO];
  3566. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3567. int ret = 0;
  3568. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3569. codec_dai->name, codec_dai->id);
  3570. ret = snd_soc_dai_get_channel_map(codec_dai,
  3571. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3572. if (ret) {
  3573. dev_err(rtd->dev,
  3574. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3575. __func__, ret);
  3576. goto err;
  3577. }
  3578. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3579. __func__, tx_ch_cnt, dai_link->id);
  3580. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3581. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3582. if (ret)
  3583. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3584. __func__, ret);
  3585. err:
  3586. return ret;
  3587. }
  3588. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3589. struct snd_pcm_hw_params *params)
  3590. {
  3591. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3592. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3593. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3594. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3595. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3596. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3597. int ret = 0;
  3598. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3599. codec_dai->name, codec_dai->id);
  3600. ret = snd_soc_dai_get_channel_map(codec_dai,
  3601. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3602. if (ret) {
  3603. dev_err(rtd->dev,
  3604. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3605. __func__, ret);
  3606. goto err;
  3607. }
  3608. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3609. __func__, tx_ch_cnt, dai_link->id);
  3610. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3611. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3612. if (ret)
  3613. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3614. __func__, ret);
  3615. err:
  3616. return ret;
  3617. }
  3618. static struct snd_soc_ops kona_tdm_be_ops = {
  3619. .hw_params = kona_tdm_snd_hw_params,
  3620. };
  3621. static struct snd_soc_ops msm_mi2s_be_ops = {
  3622. .startup = msm_mi2s_snd_startup,
  3623. .shutdown = msm_mi2s_snd_shutdown,
  3624. };
  3625. static struct snd_soc_ops msm_fe_qos_ops = {
  3626. .prepare = msm_fe_qos_prepare,
  3627. };
  3628. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  3629. .hw_params = msm_snd_cdc_dma_hw_params,
  3630. };
  3631. static struct snd_soc_ops msm_wcn_ops = {
  3632. .hw_params = msm_wcn_hw_params,
  3633. };
  3634. static struct snd_soc_ops msm_wcn_ops_lito = {
  3635. .hw_params = msm_wcn_hw_params_lito,
  3636. };
  3637. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3638. struct snd_kcontrol *kcontrol, int event)
  3639. {
  3640. struct msm_asoc_mach_data *pdata = NULL;
  3641. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  3642. int ret = 0;
  3643. u32 dmic_idx;
  3644. int *dmic_gpio_cnt;
  3645. struct device_node *dmic_gpio;
  3646. char *wname;
  3647. wname = strpbrk(w->name, "012345");
  3648. if (!wname) {
  3649. dev_err(component->dev, "%s: widget not found\n", __func__);
  3650. return -EINVAL;
  3651. }
  3652. ret = kstrtouint(wname, 10, &dmic_idx);
  3653. if (ret < 0) {
  3654. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  3655. __func__);
  3656. return -EINVAL;
  3657. }
  3658. pdata = snd_soc_card_get_drvdata(component->card);
  3659. switch (dmic_idx) {
  3660. case 0:
  3661. case 1:
  3662. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  3663. dmic_gpio = pdata->dmic01_gpio_p;
  3664. break;
  3665. case 2:
  3666. case 3:
  3667. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  3668. dmic_gpio = pdata->dmic23_gpio_p;
  3669. break;
  3670. case 4:
  3671. case 5:
  3672. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  3673. dmic_gpio = pdata->dmic45_gpio_p;
  3674. break;
  3675. default:
  3676. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  3677. __func__);
  3678. return -EINVAL;
  3679. }
  3680. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3681. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3682. switch (event) {
  3683. case SND_SOC_DAPM_PRE_PMU:
  3684. (*dmic_gpio_cnt)++;
  3685. if (*dmic_gpio_cnt == 1) {
  3686. ret = msm_cdc_pinctrl_select_active_state(
  3687. dmic_gpio);
  3688. if (ret < 0) {
  3689. pr_err("%s: gpio set cannot be activated %sd",
  3690. __func__, "dmic_gpio");
  3691. return ret;
  3692. }
  3693. }
  3694. break;
  3695. case SND_SOC_DAPM_POST_PMD:
  3696. (*dmic_gpio_cnt)--;
  3697. if (*dmic_gpio_cnt == 0) {
  3698. ret = msm_cdc_pinctrl_select_sleep_state(
  3699. dmic_gpio);
  3700. if (ret < 0) {
  3701. pr_err("%s: gpio set cannot be de-activated %sd",
  3702. __func__, "dmic_gpio");
  3703. return ret;
  3704. }
  3705. }
  3706. break;
  3707. default:
  3708. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  3709. return -EINVAL;
  3710. }
  3711. return 0;
  3712. }
  3713. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  3714. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  3715. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  3716. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3717. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3718. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  3719. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3720. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3721. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3722. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3723. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3724. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3725. };
  3726. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3727. {
  3728. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3729. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160};
  3730. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3731. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3732. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3733. }
  3734. static int msm_wcn_init_lito(struct snd_soc_pcm_runtime *rtd)
  3735. {
  3736. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3737. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO] = {159, 160, 161};
  3738. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3739. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3740. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3741. }
  3742. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3743. {
  3744. int ret = -EINVAL;
  3745. struct snd_soc_component *component;
  3746. struct snd_soc_dapm_context *dapm;
  3747. struct snd_card *card;
  3748. struct snd_info_entry *entry;
  3749. struct snd_soc_component *aux_comp;
  3750. struct msm_asoc_mach_data *pdata =
  3751. snd_soc_card_get_drvdata(rtd->card);
  3752. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  3753. if (!component) {
  3754. pr_err("%s: could not find component for bolero_codec\n",
  3755. __func__);
  3756. return ret;
  3757. }
  3758. dapm = snd_soc_component_get_dapm(component);
  3759. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  3760. ARRAY_SIZE(msm_int_snd_controls));
  3761. if (ret < 0) {
  3762. pr_err("%s: add_component_controls failed: %d\n",
  3763. __func__, ret);
  3764. return ret;
  3765. }
  3766. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  3767. ARRAY_SIZE(msm_common_snd_controls));
  3768. if (ret < 0) {
  3769. pr_err("%s: add common snd controls failed: %d\n",
  3770. __func__, ret);
  3771. return ret;
  3772. }
  3773. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  3774. ARRAY_SIZE(msm_int_dapm_widgets));
  3775. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3776. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3777. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3778. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3779. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  3780. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  3781. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3782. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3783. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  3784. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  3785. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  3786. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  3787. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  3788. snd_soc_dapm_sync(dapm);
  3789. /*
  3790. * Send speaker configuration only for WSA8810.
  3791. * Default configuration is for WSA8815.
  3792. */
  3793. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  3794. __func__, rtd->card->num_aux_devs);
  3795. if (rtd->card->num_aux_devs &&
  3796. !list_empty(&rtd->card->component_dev_list)) {
  3797. aux_comp = list_first_entry(
  3798. &rtd->card->component_dev_list,
  3799. struct snd_soc_component,
  3800. card_aux_list);
  3801. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  3802. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  3803. wsa_macro_set_spkr_mode(component,
  3804. WSA_MACRO_SPKR_MODE_1);
  3805. wsa_macro_set_spkr_gain_offset(component,
  3806. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  3807. }
  3808. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map),
  3809. sm_port_map);
  3810. }
  3811. card = rtd->card->snd_card;
  3812. if (!pdata->codec_root) {
  3813. entry = snd_info_create_subdir(card->module, "codecs",
  3814. card->proc_root);
  3815. if (!entry) {
  3816. pr_debug("%s: Cannot create codecs module entry\n",
  3817. __func__);
  3818. ret = 0;
  3819. goto err;
  3820. }
  3821. pdata->codec_root = entry;
  3822. }
  3823. bolero_info_create_codec_entry(pdata->codec_root, component);
  3824. bolero_register_wake_irq(component, false);
  3825. codec_reg_done = true;
  3826. return 0;
  3827. err:
  3828. return ret;
  3829. }
  3830. static void *def_wcd_mbhc_cal(void)
  3831. {
  3832. void *wcd_mbhc_cal;
  3833. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  3834. u16 *btn_high;
  3835. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  3836. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  3837. if (!wcd_mbhc_cal)
  3838. return NULL;
  3839. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  3840. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  3841. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  3842. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  3843. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  3844. btn_high[0] = 75;
  3845. btn_high[1] = 150;
  3846. btn_high[2] = 237;
  3847. btn_high[3] = 500;
  3848. btn_high[4] = 500;
  3849. btn_high[5] = 500;
  3850. btn_high[6] = 500;
  3851. btn_high[7] = 500;
  3852. return wcd_mbhc_cal;
  3853. }
  3854. /* Digital audio interface glue - connects codec <---> CPU */
  3855. static struct snd_soc_dai_link msm_common_dai_links[] = {
  3856. /* FrontEnd DAI Links */
  3857. {/* hw:x,0 */
  3858. .name = MSM_DAILINK_NAME(Media1),
  3859. .stream_name = "MultiMedia1",
  3860. .cpu_dai_name = "MultiMedia1",
  3861. .platform_name = "msm-pcm-dsp.0",
  3862. .dynamic = 1,
  3863. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  3864. .dpcm_playback = 1,
  3865. .dpcm_capture = 1,
  3866. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3867. SND_SOC_DPCM_TRIGGER_POST},
  3868. .codec_dai_name = "snd-soc-dummy-dai",
  3869. .codec_name = "snd-soc-dummy",
  3870. .ignore_suspend = 1,
  3871. /* this dainlink has playback support */
  3872. .ignore_pmdown_time = 1,
  3873. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  3874. },
  3875. {/* hw:x,1 */
  3876. .name = MSM_DAILINK_NAME(Media2),
  3877. .stream_name = "MultiMedia2",
  3878. .cpu_dai_name = "MultiMedia2",
  3879. .platform_name = "msm-pcm-dsp.0",
  3880. .dynamic = 1,
  3881. .dpcm_playback = 1,
  3882. .dpcm_capture = 1,
  3883. .codec_dai_name = "snd-soc-dummy-dai",
  3884. .codec_name = "snd-soc-dummy",
  3885. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3886. SND_SOC_DPCM_TRIGGER_POST},
  3887. .ignore_suspend = 1,
  3888. /* this dainlink has playback support */
  3889. .ignore_pmdown_time = 1,
  3890. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  3891. },
  3892. {/* hw:x,2 */
  3893. .name = "VoiceMMode1",
  3894. .stream_name = "VoiceMMode1",
  3895. .cpu_dai_name = "VoiceMMode1",
  3896. .platform_name = "msm-pcm-voice",
  3897. .dynamic = 1,
  3898. .dpcm_playback = 1,
  3899. .dpcm_capture = 1,
  3900. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3901. SND_SOC_DPCM_TRIGGER_POST},
  3902. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  3903. .ignore_suspend = 1,
  3904. .ignore_pmdown_time = 1,
  3905. .codec_dai_name = "snd-soc-dummy-dai",
  3906. .codec_name = "snd-soc-dummy",
  3907. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  3908. },
  3909. {/* hw:x,3 */
  3910. .name = "MSM VoIP",
  3911. .stream_name = "VoIP",
  3912. .cpu_dai_name = "VoIP",
  3913. .platform_name = "msm-voip-dsp",
  3914. .dynamic = 1,
  3915. .dpcm_playback = 1,
  3916. .dpcm_capture = 1,
  3917. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3918. SND_SOC_DPCM_TRIGGER_POST},
  3919. .codec_dai_name = "snd-soc-dummy-dai",
  3920. .codec_name = "snd-soc-dummy",
  3921. .ignore_suspend = 1,
  3922. /* this dainlink has playback support */
  3923. .ignore_pmdown_time = 1,
  3924. .id = MSM_FRONTEND_DAI_VOIP,
  3925. },
  3926. {/* hw:x,4 */
  3927. .name = MSM_DAILINK_NAME(ULL),
  3928. .stream_name = "MultiMedia3",
  3929. .cpu_dai_name = "MultiMedia3",
  3930. .platform_name = "msm-pcm-dsp.2",
  3931. .dynamic = 1,
  3932. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  3933. .dpcm_playback = 1,
  3934. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3935. SND_SOC_DPCM_TRIGGER_POST},
  3936. .codec_dai_name = "snd-soc-dummy-dai",
  3937. .codec_name = "snd-soc-dummy",
  3938. .ignore_suspend = 1,
  3939. /* this dainlink has playback support */
  3940. .ignore_pmdown_time = 1,
  3941. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  3942. },
  3943. {/* hw:x,5 */
  3944. .name = "MSM AFE-PCM RX",
  3945. .stream_name = "AFE-PROXY RX",
  3946. .cpu_dai_name = "msm-dai-q6-dev.241",
  3947. .codec_name = "msm-stub-codec.1",
  3948. .codec_dai_name = "msm-stub-rx",
  3949. .platform_name = "msm-pcm-afe",
  3950. .dpcm_playback = 1,
  3951. .ignore_suspend = 1,
  3952. /* this dainlink has playback support */
  3953. .ignore_pmdown_time = 1,
  3954. },
  3955. {/* hw:x,6 */
  3956. .name = "MSM AFE-PCM TX",
  3957. .stream_name = "AFE-PROXY TX",
  3958. .cpu_dai_name = "msm-dai-q6-dev.240",
  3959. .codec_name = "msm-stub-codec.1",
  3960. .codec_dai_name = "msm-stub-tx",
  3961. .platform_name = "msm-pcm-afe",
  3962. .dpcm_capture = 1,
  3963. .ignore_suspend = 1,
  3964. },
  3965. {/* hw:x,7 */
  3966. .name = MSM_DAILINK_NAME(Compress1),
  3967. .stream_name = "Compress1",
  3968. .cpu_dai_name = "MultiMedia4",
  3969. .platform_name = "msm-compress-dsp",
  3970. .dynamic = 1,
  3971. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  3972. .dpcm_playback = 1,
  3973. .dpcm_capture = 1,
  3974. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3975. SND_SOC_DPCM_TRIGGER_POST},
  3976. .codec_dai_name = "snd-soc-dummy-dai",
  3977. .codec_name = "snd-soc-dummy",
  3978. .ignore_suspend = 1,
  3979. .ignore_pmdown_time = 1,
  3980. /* this dainlink has playback support */
  3981. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  3982. },
  3983. /* Hostless PCM purpose */
  3984. {/* hw:x,8 */
  3985. .name = "AUXPCM Hostless",
  3986. .stream_name = "AUXPCM Hostless",
  3987. .cpu_dai_name = "AUXPCM_HOSTLESS",
  3988. .platform_name = "msm-pcm-hostless",
  3989. .dynamic = 1,
  3990. .dpcm_playback = 1,
  3991. .dpcm_capture = 1,
  3992. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3993. SND_SOC_DPCM_TRIGGER_POST},
  3994. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  3995. .ignore_suspend = 1,
  3996. /* this dainlink has playback support */
  3997. .ignore_pmdown_time = 1,
  3998. .codec_dai_name = "snd-soc-dummy-dai",
  3999. .codec_name = "snd-soc-dummy",
  4000. },
  4001. {/* hw:x,9 */
  4002. .name = MSM_DAILINK_NAME(LowLatency),
  4003. .stream_name = "MultiMedia5",
  4004. .cpu_dai_name = "MultiMedia5",
  4005. .platform_name = "msm-pcm-dsp.1",
  4006. .dynamic = 1,
  4007. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4008. .dpcm_playback = 1,
  4009. .dpcm_capture = 1,
  4010. .codec_dai_name = "snd-soc-dummy-dai",
  4011. .codec_name = "snd-soc-dummy",
  4012. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4013. SND_SOC_DPCM_TRIGGER_POST},
  4014. .ignore_suspend = 1,
  4015. /* this dainlink has playback support */
  4016. .ignore_pmdown_time = 1,
  4017. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4018. .ops = &msm_fe_qos_ops,
  4019. },
  4020. {/* hw:x,10 */
  4021. .name = "Listen 1 Audio Service",
  4022. .stream_name = "Listen 1 Audio Service",
  4023. .cpu_dai_name = "LSM1",
  4024. .platform_name = "msm-lsm-client",
  4025. .dynamic = 1,
  4026. .dpcm_capture = 1,
  4027. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4028. SND_SOC_DPCM_TRIGGER_POST },
  4029. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4030. .ignore_suspend = 1,
  4031. .codec_dai_name = "snd-soc-dummy-dai",
  4032. .codec_name = "snd-soc-dummy",
  4033. .id = MSM_FRONTEND_DAI_LSM1,
  4034. },
  4035. /* Multiple Tunnel instances */
  4036. {/* hw:x,11 */
  4037. .name = MSM_DAILINK_NAME(Compress2),
  4038. .stream_name = "Compress2",
  4039. .cpu_dai_name = "MultiMedia7",
  4040. .platform_name = "msm-compress-dsp",
  4041. .dynamic = 1,
  4042. .dpcm_playback = 1,
  4043. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4044. SND_SOC_DPCM_TRIGGER_POST},
  4045. .codec_dai_name = "snd-soc-dummy-dai",
  4046. .codec_name = "snd-soc-dummy",
  4047. .ignore_suspend = 1,
  4048. .ignore_pmdown_time = 1,
  4049. /* this dainlink has playback support */
  4050. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4051. },
  4052. {/* hw:x,12 */
  4053. .name = MSM_DAILINK_NAME(MultiMedia10),
  4054. .stream_name = "MultiMedia10",
  4055. .cpu_dai_name = "MultiMedia10",
  4056. .platform_name = "msm-pcm-dsp.1",
  4057. .dynamic = 1,
  4058. .dpcm_playback = 1,
  4059. .dpcm_capture = 1,
  4060. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4061. SND_SOC_DPCM_TRIGGER_POST},
  4062. .codec_dai_name = "snd-soc-dummy-dai",
  4063. .codec_name = "snd-soc-dummy",
  4064. .ignore_suspend = 1,
  4065. .ignore_pmdown_time = 1,
  4066. /* this dainlink has playback support */
  4067. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4068. },
  4069. {/* hw:x,13 */
  4070. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4071. .stream_name = "MM_NOIRQ",
  4072. .cpu_dai_name = "MultiMedia8",
  4073. .platform_name = "msm-pcm-dsp-noirq",
  4074. .dynamic = 1,
  4075. .dpcm_playback = 1,
  4076. .dpcm_capture = 1,
  4077. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4078. SND_SOC_DPCM_TRIGGER_POST},
  4079. .codec_dai_name = "snd-soc-dummy-dai",
  4080. .codec_name = "snd-soc-dummy",
  4081. .ignore_suspend = 1,
  4082. .ignore_pmdown_time = 1,
  4083. /* this dainlink has playback support */
  4084. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4085. .ops = &msm_fe_qos_ops,
  4086. },
  4087. /* HDMI Hostless */
  4088. {/* hw:x,14 */
  4089. .name = "HDMI_RX_HOSTLESS",
  4090. .stream_name = "HDMI_RX_HOSTLESS",
  4091. .cpu_dai_name = "HDMI_HOSTLESS",
  4092. .platform_name = "msm-pcm-hostless",
  4093. .dynamic = 1,
  4094. .dpcm_playback = 1,
  4095. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4096. SND_SOC_DPCM_TRIGGER_POST},
  4097. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4098. .ignore_suspend = 1,
  4099. .ignore_pmdown_time = 1,
  4100. .codec_dai_name = "snd-soc-dummy-dai",
  4101. .codec_name = "snd-soc-dummy",
  4102. },
  4103. {/* hw:x,15 */
  4104. .name = "VoiceMMode2",
  4105. .stream_name = "VoiceMMode2",
  4106. .cpu_dai_name = "VoiceMMode2",
  4107. .platform_name = "msm-pcm-voice",
  4108. .dynamic = 1,
  4109. .dpcm_playback = 1,
  4110. .dpcm_capture = 1,
  4111. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4112. SND_SOC_DPCM_TRIGGER_POST},
  4113. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4114. .ignore_suspend = 1,
  4115. .ignore_pmdown_time = 1,
  4116. .codec_dai_name = "snd-soc-dummy-dai",
  4117. .codec_name = "snd-soc-dummy",
  4118. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4119. },
  4120. /* LSM FE */
  4121. {/* hw:x,16 */
  4122. .name = "Listen 2 Audio Service",
  4123. .stream_name = "Listen 2 Audio Service",
  4124. .cpu_dai_name = "LSM2",
  4125. .platform_name = "msm-lsm-client",
  4126. .dynamic = 1,
  4127. .dpcm_capture = 1,
  4128. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4129. SND_SOC_DPCM_TRIGGER_POST },
  4130. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4131. .ignore_suspend = 1,
  4132. .codec_dai_name = "snd-soc-dummy-dai",
  4133. .codec_name = "snd-soc-dummy",
  4134. .id = MSM_FRONTEND_DAI_LSM2,
  4135. },
  4136. {/* hw:x,17 */
  4137. .name = "Listen 3 Audio Service",
  4138. .stream_name = "Listen 3 Audio Service",
  4139. .cpu_dai_name = "LSM3",
  4140. .platform_name = "msm-lsm-client",
  4141. .dynamic = 1,
  4142. .dpcm_capture = 1,
  4143. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4144. SND_SOC_DPCM_TRIGGER_POST },
  4145. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4146. .ignore_suspend = 1,
  4147. .codec_dai_name = "snd-soc-dummy-dai",
  4148. .codec_name = "snd-soc-dummy",
  4149. .id = MSM_FRONTEND_DAI_LSM3,
  4150. },
  4151. {/* hw:x,18 */
  4152. .name = "Listen 4 Audio Service",
  4153. .stream_name = "Listen 4 Audio Service",
  4154. .cpu_dai_name = "LSM4",
  4155. .platform_name = "msm-lsm-client",
  4156. .dynamic = 1,
  4157. .dpcm_capture = 1,
  4158. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4159. SND_SOC_DPCM_TRIGGER_POST },
  4160. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4161. .ignore_suspend = 1,
  4162. .codec_dai_name = "snd-soc-dummy-dai",
  4163. .codec_name = "snd-soc-dummy",
  4164. .id = MSM_FRONTEND_DAI_LSM4,
  4165. },
  4166. {/* hw:x,19 */
  4167. .name = "Listen 5 Audio Service",
  4168. .stream_name = "Listen 5 Audio Service",
  4169. .cpu_dai_name = "LSM5",
  4170. .platform_name = "msm-lsm-client",
  4171. .dynamic = 1,
  4172. .dpcm_capture = 1,
  4173. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4174. SND_SOC_DPCM_TRIGGER_POST },
  4175. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4176. .ignore_suspend = 1,
  4177. .codec_dai_name = "snd-soc-dummy-dai",
  4178. .codec_name = "snd-soc-dummy",
  4179. .id = MSM_FRONTEND_DAI_LSM5,
  4180. },
  4181. {/* hw:x,20 */
  4182. .name = "Listen 6 Audio Service",
  4183. .stream_name = "Listen 6 Audio Service",
  4184. .cpu_dai_name = "LSM6",
  4185. .platform_name = "msm-lsm-client",
  4186. .dynamic = 1,
  4187. .dpcm_capture = 1,
  4188. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4189. SND_SOC_DPCM_TRIGGER_POST },
  4190. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4191. .ignore_suspend = 1,
  4192. .codec_dai_name = "snd-soc-dummy-dai",
  4193. .codec_name = "snd-soc-dummy",
  4194. .id = MSM_FRONTEND_DAI_LSM6,
  4195. },
  4196. {/* hw:x,21 */
  4197. .name = "Listen 7 Audio Service",
  4198. .stream_name = "Listen 7 Audio Service",
  4199. .cpu_dai_name = "LSM7",
  4200. .platform_name = "msm-lsm-client",
  4201. .dynamic = 1,
  4202. .dpcm_capture = 1,
  4203. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4204. SND_SOC_DPCM_TRIGGER_POST },
  4205. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4206. .ignore_suspend = 1,
  4207. .codec_dai_name = "snd-soc-dummy-dai",
  4208. .codec_name = "snd-soc-dummy",
  4209. .id = MSM_FRONTEND_DAI_LSM7,
  4210. },
  4211. {/* hw:x,22 */
  4212. .name = "Listen 8 Audio Service",
  4213. .stream_name = "Listen 8 Audio Service",
  4214. .cpu_dai_name = "LSM8",
  4215. .platform_name = "msm-lsm-client",
  4216. .dynamic = 1,
  4217. .dpcm_capture = 1,
  4218. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4219. SND_SOC_DPCM_TRIGGER_POST },
  4220. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4221. .ignore_suspend = 1,
  4222. .codec_dai_name = "snd-soc-dummy-dai",
  4223. .codec_name = "snd-soc-dummy",
  4224. .id = MSM_FRONTEND_DAI_LSM8,
  4225. },
  4226. {/* hw:x,23 */
  4227. .name = MSM_DAILINK_NAME(Media9),
  4228. .stream_name = "MultiMedia9",
  4229. .cpu_dai_name = "MultiMedia9",
  4230. .platform_name = "msm-pcm-dsp.0",
  4231. .dynamic = 1,
  4232. .dpcm_playback = 1,
  4233. .dpcm_capture = 1,
  4234. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4235. SND_SOC_DPCM_TRIGGER_POST},
  4236. .codec_dai_name = "snd-soc-dummy-dai",
  4237. .codec_name = "snd-soc-dummy",
  4238. .ignore_suspend = 1,
  4239. /* this dainlink has playback support */
  4240. .ignore_pmdown_time = 1,
  4241. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4242. },
  4243. {/* hw:x,24 */
  4244. .name = MSM_DAILINK_NAME(Compress4),
  4245. .stream_name = "Compress4",
  4246. .cpu_dai_name = "MultiMedia11",
  4247. .platform_name = "msm-compress-dsp",
  4248. .dynamic = 1,
  4249. .dpcm_playback = 1,
  4250. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4251. SND_SOC_DPCM_TRIGGER_POST},
  4252. .codec_dai_name = "snd-soc-dummy-dai",
  4253. .codec_name = "snd-soc-dummy",
  4254. .ignore_suspend = 1,
  4255. .ignore_pmdown_time = 1,
  4256. /* this dainlink has playback support */
  4257. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4258. },
  4259. {/* hw:x,25 */
  4260. .name = MSM_DAILINK_NAME(Compress5),
  4261. .stream_name = "Compress5",
  4262. .cpu_dai_name = "MultiMedia12",
  4263. .platform_name = "msm-compress-dsp",
  4264. .dynamic = 1,
  4265. .dpcm_playback = 1,
  4266. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4267. SND_SOC_DPCM_TRIGGER_POST},
  4268. .codec_dai_name = "snd-soc-dummy-dai",
  4269. .codec_name = "snd-soc-dummy",
  4270. .ignore_suspend = 1,
  4271. .ignore_pmdown_time = 1,
  4272. /* this dainlink has playback support */
  4273. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4274. },
  4275. {/* hw:x,26 */
  4276. .name = MSM_DAILINK_NAME(Compress6),
  4277. .stream_name = "Compress6",
  4278. .cpu_dai_name = "MultiMedia13",
  4279. .platform_name = "msm-compress-dsp",
  4280. .dynamic = 1,
  4281. .dpcm_playback = 1,
  4282. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4283. SND_SOC_DPCM_TRIGGER_POST},
  4284. .codec_dai_name = "snd-soc-dummy-dai",
  4285. .codec_name = "snd-soc-dummy",
  4286. .ignore_suspend = 1,
  4287. .ignore_pmdown_time = 1,
  4288. /* this dainlink has playback support */
  4289. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  4290. },
  4291. {/* hw:x,27 */
  4292. .name = MSM_DAILINK_NAME(Compress7),
  4293. .stream_name = "Compress7",
  4294. .cpu_dai_name = "MultiMedia14",
  4295. .platform_name = "msm-compress-dsp",
  4296. .dynamic = 1,
  4297. .dpcm_playback = 1,
  4298. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4299. SND_SOC_DPCM_TRIGGER_POST},
  4300. .codec_dai_name = "snd-soc-dummy-dai",
  4301. .codec_name = "snd-soc-dummy",
  4302. .ignore_suspend = 1,
  4303. .ignore_pmdown_time = 1,
  4304. /* this dainlink has playback support */
  4305. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  4306. },
  4307. {/* hw:x,28 */
  4308. .name = MSM_DAILINK_NAME(Compress8),
  4309. .stream_name = "Compress8",
  4310. .cpu_dai_name = "MultiMedia15",
  4311. .platform_name = "msm-compress-dsp",
  4312. .dynamic = 1,
  4313. .dpcm_playback = 1,
  4314. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4315. SND_SOC_DPCM_TRIGGER_POST},
  4316. .codec_dai_name = "snd-soc-dummy-dai",
  4317. .codec_name = "snd-soc-dummy",
  4318. .ignore_suspend = 1,
  4319. .ignore_pmdown_time = 1,
  4320. /* this dainlink has playback support */
  4321. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  4322. },
  4323. {/* hw:x,29 */
  4324. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  4325. .stream_name = "MM_NOIRQ_2",
  4326. .cpu_dai_name = "MultiMedia16",
  4327. .platform_name = "msm-pcm-dsp-noirq",
  4328. .dynamic = 1,
  4329. .dpcm_playback = 1,
  4330. .dpcm_capture = 1,
  4331. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4332. SND_SOC_DPCM_TRIGGER_POST},
  4333. .codec_dai_name = "snd-soc-dummy-dai",
  4334. .codec_name = "snd-soc-dummy",
  4335. .ignore_suspend = 1,
  4336. .ignore_pmdown_time = 1,
  4337. /* this dainlink has playback support */
  4338. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  4339. },
  4340. {/* hw:x,30 */
  4341. .name = "CDC_DMA Hostless",
  4342. .stream_name = "CDC_DMA Hostless",
  4343. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  4344. .platform_name = "msm-pcm-hostless",
  4345. .dynamic = 1,
  4346. .dpcm_playback = 1,
  4347. .dpcm_capture = 1,
  4348. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4349. SND_SOC_DPCM_TRIGGER_POST},
  4350. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4351. .ignore_suspend = 1,
  4352. /* this dailink has playback support */
  4353. .ignore_pmdown_time = 1,
  4354. .codec_dai_name = "snd-soc-dummy-dai",
  4355. .codec_name = "snd-soc-dummy",
  4356. },
  4357. {/* hw:x,31 */
  4358. .name = "TX3_CDC_DMA Hostless",
  4359. .stream_name = "TX3_CDC_DMA Hostless",
  4360. .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
  4361. .platform_name = "msm-pcm-hostless",
  4362. .dynamic = 1,
  4363. .dpcm_capture = 1,
  4364. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4365. SND_SOC_DPCM_TRIGGER_POST},
  4366. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4367. .ignore_suspend = 1,
  4368. .codec_dai_name = "snd-soc-dummy-dai",
  4369. .codec_name = "snd-soc-dummy",
  4370. },
  4371. {/* hw:x,32 */
  4372. .name = "Tertiary MI2S TX_Hostless",
  4373. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  4374. .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
  4375. .platform_name = "msm-pcm-hostless",
  4376. .dynamic = 1,
  4377. .dpcm_capture = 1,
  4378. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4379. SND_SOC_DPCM_TRIGGER_POST},
  4380. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4381. .ignore_suspend = 1,
  4382. .ignore_pmdown_time = 1,
  4383. .codec_dai_name = "snd-soc-dummy-dai",
  4384. .codec_name = "snd-soc-dummy",
  4385. },
  4386. };
  4387. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  4388. {/* hw:x,33 */
  4389. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  4390. .stream_name = "WSA CDC DMA0 Capture",
  4391. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  4392. .platform_name = "msm-pcm-hostless",
  4393. .codec_name = "bolero_codec",
  4394. .codec_dai_name = "wsa_macro_vifeedback",
  4395. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  4396. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4397. .ignore_suspend = 1,
  4398. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4399. .ops = &msm_cdc_dma_be_ops,
  4400. },
  4401. };
  4402. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  4403. {/* hw:x,34 */
  4404. .name = MSM_DAILINK_NAME(ASM Loopback),
  4405. .stream_name = "MultiMedia6",
  4406. .cpu_dai_name = "MultiMedia6",
  4407. .platform_name = "msm-pcm-loopback",
  4408. .dynamic = 1,
  4409. .dpcm_playback = 1,
  4410. .dpcm_capture = 1,
  4411. .codec_dai_name = "snd-soc-dummy-dai",
  4412. .codec_name = "snd-soc-dummy",
  4413. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4414. SND_SOC_DPCM_TRIGGER_POST},
  4415. .ignore_suspend = 1,
  4416. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4417. .ignore_pmdown_time = 1,
  4418. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  4419. },
  4420. {/* hw:x,35 */
  4421. .name = "USB Audio Hostless",
  4422. .stream_name = "USB Audio Hostless",
  4423. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  4424. .platform_name = "msm-pcm-hostless",
  4425. .dynamic = 1,
  4426. .dpcm_playback = 1,
  4427. .dpcm_capture = 1,
  4428. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4429. SND_SOC_DPCM_TRIGGER_POST},
  4430. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4431. .ignore_suspend = 1,
  4432. .ignore_pmdown_time = 1,
  4433. .codec_dai_name = "snd-soc-dummy-dai",
  4434. .codec_name = "snd-soc-dummy",
  4435. },
  4436. {/* hw:x,36 */
  4437. .name = "SLIMBUS_7 Hostless",
  4438. .stream_name = "SLIMBUS_7 Hostless",
  4439. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  4440. .platform_name = "msm-pcm-hostless",
  4441. .dynamic = 1,
  4442. .dpcm_capture = 1,
  4443. .dpcm_playback = 1,
  4444. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4445. SND_SOC_DPCM_TRIGGER_POST},
  4446. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4447. .ignore_suspend = 1,
  4448. .ignore_pmdown_time = 1,
  4449. .codec_dai_name = "snd-soc-dummy-dai",
  4450. .codec_name = "snd-soc-dummy",
  4451. },
  4452. {/* hw:x,37 */
  4453. .name = "Compress Capture",
  4454. .stream_name = "Compress9",
  4455. .cpu_dai_name = "MultiMedia17",
  4456. .platform_name = "msm-compress-dsp",
  4457. .dynamic = 1,
  4458. .dpcm_capture = 1,
  4459. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4460. SND_SOC_DPCM_TRIGGER_POST},
  4461. .codec_dai_name = "snd-soc-dummy-dai",
  4462. .codec_name = "snd-soc-dummy",
  4463. .ignore_suspend = 1,
  4464. .ignore_pmdown_time = 1,
  4465. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  4466. },
  4467. {/* hw:x,38 */
  4468. .name = "SLIMBUS_8 Hostless",
  4469. .stream_name = "SLIMBUS_8 Hostless",
  4470. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  4471. .platform_name = "msm-pcm-hostless",
  4472. .dynamic = 1,
  4473. .dpcm_capture = 1,
  4474. .dpcm_playback = 1,
  4475. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4476. SND_SOC_DPCM_TRIGGER_POST},
  4477. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4478. .ignore_suspend = 1,
  4479. .ignore_pmdown_time = 1,
  4480. .codec_dai_name = "snd-soc-dummy-dai",
  4481. .codec_name = "snd-soc-dummy",
  4482. },
  4483. };
  4484. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  4485. /* Backend AFE DAI Links */
  4486. {
  4487. .name = LPASS_BE_AFE_PCM_RX,
  4488. .stream_name = "AFE Playback",
  4489. .cpu_dai_name = "msm-dai-q6-dev.224",
  4490. .platform_name = "msm-pcm-routing",
  4491. .codec_name = "msm-stub-codec.1",
  4492. .codec_dai_name = "msm-stub-rx",
  4493. .no_pcm = 1,
  4494. .dpcm_playback = 1,
  4495. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  4496. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4497. /* this dainlink has playback support */
  4498. .ignore_pmdown_time = 1,
  4499. .ignore_suspend = 1,
  4500. },
  4501. {
  4502. .name = LPASS_BE_AFE_PCM_TX,
  4503. .stream_name = "AFE Capture",
  4504. .cpu_dai_name = "msm-dai-q6-dev.225",
  4505. .platform_name = "msm-pcm-routing",
  4506. .codec_name = "msm-stub-codec.1",
  4507. .codec_dai_name = "msm-stub-tx",
  4508. .no_pcm = 1,
  4509. .dpcm_capture = 1,
  4510. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  4511. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4512. .ignore_suspend = 1,
  4513. },
  4514. /* Incall Record Uplink BACK END DAI Link */
  4515. {
  4516. .name = LPASS_BE_INCALL_RECORD_TX,
  4517. .stream_name = "Voice Uplink Capture",
  4518. .cpu_dai_name = "msm-dai-q6-dev.32772",
  4519. .platform_name = "msm-pcm-routing",
  4520. .codec_name = "msm-stub-codec.1",
  4521. .codec_dai_name = "msm-stub-tx",
  4522. .no_pcm = 1,
  4523. .dpcm_capture = 1,
  4524. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  4525. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4526. .ignore_suspend = 1,
  4527. },
  4528. /* Incall Record Downlink BACK END DAI Link */
  4529. {
  4530. .name = LPASS_BE_INCALL_RECORD_RX,
  4531. .stream_name = "Voice Downlink Capture",
  4532. .cpu_dai_name = "msm-dai-q6-dev.32771",
  4533. .platform_name = "msm-pcm-routing",
  4534. .codec_name = "msm-stub-codec.1",
  4535. .codec_dai_name = "msm-stub-tx",
  4536. .no_pcm = 1,
  4537. .dpcm_capture = 1,
  4538. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  4539. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4540. .ignore_suspend = 1,
  4541. },
  4542. /* Incall Music BACK END DAI Link */
  4543. {
  4544. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  4545. .stream_name = "Voice Farend Playback",
  4546. .cpu_dai_name = "msm-dai-q6-dev.32773",
  4547. .platform_name = "msm-pcm-routing",
  4548. .codec_name = "msm-stub-codec.1",
  4549. .codec_dai_name = "msm-stub-rx",
  4550. .no_pcm = 1,
  4551. .dpcm_playback = 1,
  4552. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  4553. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4554. .ignore_suspend = 1,
  4555. .ignore_pmdown_time = 1,
  4556. },
  4557. /* Incall Music 2 BACK END DAI Link */
  4558. {
  4559. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  4560. .stream_name = "Voice2 Farend Playback",
  4561. .cpu_dai_name = "msm-dai-q6-dev.32770",
  4562. .platform_name = "msm-pcm-routing",
  4563. .codec_name = "msm-stub-codec.1",
  4564. .codec_dai_name = "msm-stub-rx",
  4565. .no_pcm = 1,
  4566. .dpcm_playback = 1,
  4567. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  4568. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4569. .ignore_suspend = 1,
  4570. .ignore_pmdown_time = 1,
  4571. },
  4572. {
  4573. .name = LPASS_BE_USB_AUDIO_RX,
  4574. .stream_name = "USB Audio Playback",
  4575. .cpu_dai_name = "msm-dai-q6-dev.28672",
  4576. .platform_name = "msm-pcm-routing",
  4577. .codec_name = "msm-stub-codec.1",
  4578. .codec_dai_name = "msm-stub-rx",
  4579. .no_pcm = 1,
  4580. .dpcm_playback = 1,
  4581. .id = MSM_BACKEND_DAI_USB_RX,
  4582. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4583. .ignore_pmdown_time = 1,
  4584. .ignore_suspend = 1,
  4585. },
  4586. {
  4587. .name = LPASS_BE_USB_AUDIO_TX,
  4588. .stream_name = "USB Audio Capture",
  4589. .cpu_dai_name = "msm-dai-q6-dev.28673",
  4590. .platform_name = "msm-pcm-routing",
  4591. .codec_name = "msm-stub-codec.1",
  4592. .codec_dai_name = "msm-stub-tx",
  4593. .no_pcm = 1,
  4594. .dpcm_capture = 1,
  4595. .id = MSM_BACKEND_DAI_USB_TX,
  4596. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4597. .ignore_suspend = 1,
  4598. },
  4599. {
  4600. .name = LPASS_BE_PRI_TDM_RX_0,
  4601. .stream_name = "Primary TDM0 Playback",
  4602. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  4603. .platform_name = "msm-pcm-routing",
  4604. .codec_name = "msm-stub-codec.1",
  4605. .codec_dai_name = "msm-stub-rx",
  4606. .no_pcm = 1,
  4607. .dpcm_playback = 1,
  4608. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  4609. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4610. .ops = &kona_tdm_be_ops,
  4611. .ignore_suspend = 1,
  4612. .ignore_pmdown_time = 1,
  4613. },
  4614. {
  4615. .name = LPASS_BE_PRI_TDM_TX_0,
  4616. .stream_name = "Primary TDM0 Capture",
  4617. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  4618. .platform_name = "msm-pcm-routing",
  4619. .codec_name = "msm-stub-codec.1",
  4620. .codec_dai_name = "msm-stub-tx",
  4621. .no_pcm = 1,
  4622. .dpcm_capture = 1,
  4623. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  4624. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4625. .ops = &kona_tdm_be_ops,
  4626. .ignore_suspend = 1,
  4627. },
  4628. {
  4629. .name = LPASS_BE_SEC_TDM_RX_0,
  4630. .stream_name = "Secondary TDM0 Playback",
  4631. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  4632. .platform_name = "msm-pcm-routing",
  4633. .codec_name = "msm-stub-codec.1",
  4634. .codec_dai_name = "msm-stub-rx",
  4635. .no_pcm = 1,
  4636. .dpcm_playback = 1,
  4637. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  4638. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4639. .ops = &kona_tdm_be_ops,
  4640. .ignore_suspend = 1,
  4641. .ignore_pmdown_time = 1,
  4642. },
  4643. {
  4644. .name = LPASS_BE_SEC_TDM_TX_0,
  4645. .stream_name = "Secondary TDM0 Capture",
  4646. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  4647. .platform_name = "msm-pcm-routing",
  4648. .codec_name = "msm-stub-codec.1",
  4649. .codec_dai_name = "msm-stub-tx",
  4650. .no_pcm = 1,
  4651. .dpcm_capture = 1,
  4652. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  4653. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4654. .ops = &kona_tdm_be_ops,
  4655. .ignore_suspend = 1,
  4656. },
  4657. {
  4658. .name = LPASS_BE_TERT_TDM_RX_0,
  4659. .stream_name = "Tertiary TDM0 Playback",
  4660. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  4661. .platform_name = "msm-pcm-routing",
  4662. .codec_name = "msm-stub-codec.1",
  4663. .codec_dai_name = "msm-stub-rx",
  4664. .no_pcm = 1,
  4665. .dpcm_playback = 1,
  4666. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  4667. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4668. .ops = &kona_tdm_be_ops,
  4669. .ignore_suspend = 1,
  4670. .ignore_pmdown_time = 1,
  4671. },
  4672. {
  4673. .name = LPASS_BE_TERT_TDM_TX_0,
  4674. .stream_name = "Tertiary TDM0 Capture",
  4675. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  4676. .platform_name = "msm-pcm-routing",
  4677. .codec_name = "msm-stub-codec.1",
  4678. .codec_dai_name = "msm-stub-tx",
  4679. .no_pcm = 1,
  4680. .dpcm_capture = 1,
  4681. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  4682. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4683. .ops = &kona_tdm_be_ops,
  4684. .ignore_suspend = 1,
  4685. },
  4686. };
  4687. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  4688. {
  4689. .name = LPASS_BE_SLIMBUS_7_RX,
  4690. .stream_name = "Slimbus7 Playback",
  4691. .cpu_dai_name = "msm-dai-q6-dev.16398",
  4692. .platform_name = "msm-pcm-routing",
  4693. .codec_name = "btfmslim_slave",
  4694. /* BT codec driver determines capabilities based on
  4695. * dai name, bt codecdai name should always contains
  4696. * supported usecase information
  4697. */
  4698. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  4699. .no_pcm = 1,
  4700. .dpcm_playback = 1,
  4701. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  4702. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4703. .init = &msm_wcn_init,
  4704. .ops = &msm_wcn_ops,
  4705. /* dai link has playback support */
  4706. .ignore_pmdown_time = 1,
  4707. .ignore_suspend = 1,
  4708. },
  4709. {
  4710. .name = LPASS_BE_SLIMBUS_7_TX,
  4711. .stream_name = "Slimbus7 Capture",
  4712. .cpu_dai_name = "msm-dai-q6-dev.16399",
  4713. .platform_name = "msm-pcm-routing",
  4714. .codec_name = "btfmslim_slave",
  4715. .codec_dai_name = "btfm_bt_sco_slim_tx",
  4716. .no_pcm = 1,
  4717. .dpcm_capture = 1,
  4718. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  4719. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4720. .ops = &msm_wcn_ops,
  4721. .ignore_suspend = 1,
  4722. },
  4723. };
  4724. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  4725. {
  4726. .name = LPASS_BE_SLIMBUS_7_RX,
  4727. .stream_name = "Slimbus7 Playback",
  4728. .cpu_dai_name = "msm-dai-q6-dev.16398",
  4729. .platform_name = "msm-pcm-routing",
  4730. .codec_name = "btfmslim_slave",
  4731. /* BT codec driver determines capabilities based on
  4732. * dai name, bt codecdai name should always contains
  4733. * supported usecase information
  4734. */
  4735. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  4736. .no_pcm = 1,
  4737. .dpcm_playback = 1,
  4738. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  4739. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4740. .init = &msm_wcn_init_lito,
  4741. .ops = &msm_wcn_ops_lito,
  4742. /* dai link has playback support */
  4743. .ignore_pmdown_time = 1,
  4744. .ignore_suspend = 1,
  4745. },
  4746. {
  4747. .name = LPASS_BE_SLIMBUS_7_TX,
  4748. .stream_name = "Slimbus7 Capture",
  4749. .cpu_dai_name = "msm-dai-q6-dev.16399",
  4750. .platform_name = "msm-pcm-routing",
  4751. .codec_name = "btfmslim_slave",
  4752. .codec_dai_name = "btfm_bt_sco_slim_tx",
  4753. .no_pcm = 1,
  4754. .dpcm_capture = 1,
  4755. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  4756. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4757. .ops = &msm_wcn_ops_lito,
  4758. .ignore_suspend = 1,
  4759. },
  4760. {
  4761. .name = LPASS_BE_SLIMBUS_8_TX,
  4762. .stream_name = "Slimbus8 Capture",
  4763. .cpu_dai_name = "msm-dai-q6-dev.16401",
  4764. .platform_name = "msm-pcm-routing",
  4765. .codec_name = "btfmslim_slave",
  4766. .codec_dai_name = "btfm_fm_slim_tx",
  4767. .no_pcm = 1,
  4768. .dpcm_capture = 1,
  4769. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  4770. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4771. .ops = &msm_wcn_ops_lito,
  4772. .ignore_suspend = 1,
  4773. },
  4774. };
  4775. static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
  4776. /* DISP PORT BACK END DAI Link */
  4777. {
  4778. .name = LPASS_BE_DISPLAY_PORT,
  4779. .stream_name = "Display Port Playback",
  4780. .cpu_dai_name = "msm-dai-q6-dp.24608",
  4781. .platform_name = "msm-pcm-routing",
  4782. .codec_name = "msm-ext-disp-audio-codec-rx",
  4783. .codec_dai_name = "msm_dp_audio_codec_rx_dai",
  4784. .no_pcm = 1,
  4785. .dpcm_playback = 1,
  4786. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
  4787. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4788. .ignore_pmdown_time = 1,
  4789. .ignore_suspend = 1,
  4790. },
  4791. /* DISP PORT 1 BACK END DAI Link */
  4792. {
  4793. .name = LPASS_BE_DISPLAY_PORT1,
  4794. .stream_name = "Display Port1 Playback",
  4795. .cpu_dai_name = "msm-dai-q6-dp.24608",
  4796. .platform_name = "msm-pcm-routing",
  4797. .codec_name = "msm-ext-disp-audio-codec-rx",
  4798. .codec_dai_name = "msm_dp_audio_codec_rx1_dai",
  4799. .no_pcm = 1,
  4800. .dpcm_playback = 1,
  4801. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX_1,
  4802. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4803. .ignore_pmdown_time = 1,
  4804. .ignore_suspend = 1,
  4805. },
  4806. };
  4807. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  4808. {
  4809. .name = LPASS_BE_PRI_MI2S_RX,
  4810. .stream_name = "Primary MI2S Playback",
  4811. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  4812. .platform_name = "msm-pcm-routing",
  4813. .codec_name = "msm-stub-codec.1",
  4814. .codec_dai_name = "msm-stub-rx",
  4815. .no_pcm = 1,
  4816. .dpcm_playback = 1,
  4817. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  4818. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4819. .ops = &msm_mi2s_be_ops,
  4820. .ignore_suspend = 1,
  4821. .ignore_pmdown_time = 1,
  4822. },
  4823. {
  4824. .name = LPASS_BE_PRI_MI2S_TX,
  4825. .stream_name = "Primary MI2S Capture",
  4826. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  4827. .platform_name = "msm-pcm-routing",
  4828. .codec_name = "msm-stub-codec.1",
  4829. .codec_dai_name = "msm-stub-tx",
  4830. .no_pcm = 1,
  4831. .dpcm_capture = 1,
  4832. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  4833. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4834. .ops = &msm_mi2s_be_ops,
  4835. .ignore_suspend = 1,
  4836. },
  4837. {
  4838. .name = LPASS_BE_SEC_MI2S_RX,
  4839. .stream_name = "Secondary MI2S Playback",
  4840. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  4841. .platform_name = "msm-pcm-routing",
  4842. .codec_name = "msm-stub-codec.1",
  4843. .codec_dai_name = "msm-stub-rx",
  4844. .no_pcm = 1,
  4845. .dpcm_playback = 1,
  4846. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  4847. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4848. .ops = &msm_mi2s_be_ops,
  4849. .ignore_suspend = 1,
  4850. .ignore_pmdown_time = 1,
  4851. },
  4852. {
  4853. .name = LPASS_BE_SEC_MI2S_TX,
  4854. .stream_name = "Secondary MI2S Capture",
  4855. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  4856. .platform_name = "msm-pcm-routing",
  4857. .codec_name = "msm-stub-codec.1",
  4858. .codec_dai_name = "msm-stub-tx",
  4859. .no_pcm = 1,
  4860. .dpcm_capture = 1,
  4861. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  4862. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4863. .ops = &msm_mi2s_be_ops,
  4864. .ignore_suspend = 1,
  4865. },
  4866. {
  4867. .name = LPASS_BE_TERT_MI2S_RX,
  4868. .stream_name = "Tertiary MI2S Playback",
  4869. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  4870. .platform_name = "msm-pcm-routing",
  4871. .codec_name = "msm-stub-codec.1",
  4872. .codec_dai_name = "msm-stub-rx",
  4873. .no_pcm = 1,
  4874. .dpcm_playback = 1,
  4875. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  4876. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4877. .ops = &msm_mi2s_be_ops,
  4878. .ignore_suspend = 1,
  4879. .ignore_pmdown_time = 1,
  4880. },
  4881. {
  4882. .name = LPASS_BE_TERT_MI2S_TX,
  4883. .stream_name = "Tertiary MI2S Capture",
  4884. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  4885. .platform_name = "msm-pcm-routing",
  4886. .codec_name = "msm-stub-codec.1",
  4887. .codec_dai_name = "msm-stub-tx",
  4888. .no_pcm = 1,
  4889. .dpcm_capture = 1,
  4890. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  4891. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4892. .ops = &msm_mi2s_be_ops,
  4893. .ignore_suspend = 1,
  4894. },
  4895. };
  4896. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  4897. /* Primary AUX PCM Backend DAI Links */
  4898. {
  4899. .name = LPASS_BE_AUXPCM_RX,
  4900. .stream_name = "AUX PCM Playback",
  4901. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  4902. .platform_name = "msm-pcm-routing",
  4903. .codec_name = "msm-stub-codec.1",
  4904. .codec_dai_name = "msm-stub-rx",
  4905. .no_pcm = 1,
  4906. .dpcm_playback = 1,
  4907. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  4908. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4909. .ignore_pmdown_time = 1,
  4910. .ignore_suspend = 1,
  4911. },
  4912. {
  4913. .name = LPASS_BE_AUXPCM_TX,
  4914. .stream_name = "AUX PCM Capture",
  4915. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  4916. .platform_name = "msm-pcm-routing",
  4917. .codec_name = "msm-stub-codec.1",
  4918. .codec_dai_name = "msm-stub-tx",
  4919. .no_pcm = 1,
  4920. .dpcm_capture = 1,
  4921. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  4922. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4923. .ignore_suspend = 1,
  4924. },
  4925. /* Secondary AUX PCM Backend DAI Links */
  4926. {
  4927. .name = LPASS_BE_SEC_AUXPCM_RX,
  4928. .stream_name = "Sec AUX PCM Playback",
  4929. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  4930. .platform_name = "msm-pcm-routing",
  4931. .codec_name = "msm-stub-codec.1",
  4932. .codec_dai_name = "msm-stub-rx",
  4933. .no_pcm = 1,
  4934. .dpcm_playback = 1,
  4935. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  4936. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4937. .ignore_pmdown_time = 1,
  4938. .ignore_suspend = 1,
  4939. },
  4940. {
  4941. .name = LPASS_BE_SEC_AUXPCM_TX,
  4942. .stream_name = "Sec AUX PCM Capture",
  4943. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  4944. .platform_name = "msm-pcm-routing",
  4945. .codec_name = "msm-stub-codec.1",
  4946. .codec_dai_name = "msm-stub-tx",
  4947. .no_pcm = 1,
  4948. .dpcm_capture = 1,
  4949. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  4950. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4951. .ignore_suspend = 1,
  4952. },
  4953. /* Tertiary AUX PCM Backend DAI Links */
  4954. {
  4955. .name = LPASS_BE_TERT_AUXPCM_RX,
  4956. .stream_name = "Tert AUX PCM Playback",
  4957. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  4958. .platform_name = "msm-pcm-routing",
  4959. .codec_name = "msm-stub-codec.1",
  4960. .codec_dai_name = "msm-stub-rx",
  4961. .no_pcm = 1,
  4962. .dpcm_playback = 1,
  4963. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  4964. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4965. .ignore_suspend = 1,
  4966. },
  4967. {
  4968. .name = LPASS_BE_TERT_AUXPCM_TX,
  4969. .stream_name = "Tert AUX PCM Capture",
  4970. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  4971. .platform_name = "msm-pcm-routing",
  4972. .codec_name = "msm-stub-codec.1",
  4973. .codec_dai_name = "msm-stub-tx",
  4974. .no_pcm = 1,
  4975. .dpcm_capture = 1,
  4976. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  4977. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4978. .ignore_suspend = 1,
  4979. },
  4980. };
  4981. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  4982. /* WSA CDC DMA Backend DAI Links */
  4983. {
  4984. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  4985. .stream_name = "WSA CDC DMA0 Playback",
  4986. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  4987. .platform_name = "msm-pcm-routing",
  4988. .codec_name = "bolero_codec",
  4989. .codec_dai_name = "wsa_macro_rx1",
  4990. .no_pcm = 1,
  4991. .dpcm_playback = 1,
  4992. .init = &msm_int_audrx_init,
  4993. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  4994. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4995. .ignore_pmdown_time = 1,
  4996. .ignore_suspend = 1,
  4997. .ops = &msm_cdc_dma_be_ops,
  4998. },
  4999. {
  5000. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  5001. .stream_name = "WSA CDC DMA1 Playback",
  5002. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  5003. .platform_name = "msm-pcm-routing",
  5004. .codec_name = "bolero_codec",
  5005. .codec_dai_name = "wsa_macro_rx_mix",
  5006. .no_pcm = 1,
  5007. .dpcm_playback = 1,
  5008. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  5009. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5010. .ignore_pmdown_time = 1,
  5011. .ignore_suspend = 1,
  5012. .ops = &msm_cdc_dma_be_ops,
  5013. },
  5014. {
  5015. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  5016. .stream_name = "WSA CDC DMA1 Capture",
  5017. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  5018. .platform_name = "msm-pcm-routing",
  5019. .codec_name = "bolero_codec",
  5020. .codec_dai_name = "wsa_macro_echo",
  5021. .no_pcm = 1,
  5022. .dpcm_capture = 1,
  5023. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  5024. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5025. .ignore_suspend = 1,
  5026. .ops = &msm_cdc_dma_be_ops,
  5027. },
  5028. };
  5029. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  5030. /* RX CDC DMA Backend DAI Links */
  5031. {
  5032. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  5033. .stream_name = "RX CDC DMA0 Playback",
  5034. .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
  5035. .platform_name = "msm-pcm-routing",
  5036. .codec_name = "bolero_codec",
  5037. .codec_dai_name = "rx_macro_rx1",
  5038. .no_pcm = 1,
  5039. .dpcm_playback = 1,
  5040. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  5041. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5042. .ignore_pmdown_time = 1,
  5043. .ignore_suspend = 1,
  5044. .ops = &msm_cdc_dma_be_ops,
  5045. },
  5046. {
  5047. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  5048. .stream_name = "RX CDC DMA1 Playback",
  5049. .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
  5050. .platform_name = "msm-pcm-routing",
  5051. .codec_name = "bolero_codec",
  5052. .codec_dai_name = "rx_macro_rx2",
  5053. .no_pcm = 1,
  5054. .dpcm_playback = 1,
  5055. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  5056. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5057. .ignore_pmdown_time = 1,
  5058. .ignore_suspend = 1,
  5059. .ops = &msm_cdc_dma_be_ops,
  5060. },
  5061. {
  5062. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  5063. .stream_name = "RX CDC DMA2 Playback",
  5064. .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
  5065. .platform_name = "msm-pcm-routing",
  5066. .codec_name = "bolero_codec",
  5067. .codec_dai_name = "rx_macro_rx3",
  5068. .no_pcm = 1,
  5069. .dpcm_playback = 1,
  5070. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  5071. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5072. .ignore_pmdown_time = 1,
  5073. .ignore_suspend = 1,
  5074. .ops = &msm_cdc_dma_be_ops,
  5075. },
  5076. {
  5077. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  5078. .stream_name = "RX CDC DMA3 Playback",
  5079. .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
  5080. .platform_name = "msm-pcm-routing",
  5081. .codec_name = "bolero_codec",
  5082. .codec_dai_name = "rx_macro_rx4",
  5083. .no_pcm = 1,
  5084. .dpcm_playback = 1,
  5085. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  5086. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5087. .ignore_pmdown_time = 1,
  5088. .ignore_suspend = 1,
  5089. .ops = &msm_cdc_dma_be_ops,
  5090. },
  5091. /* TX CDC DMA Backend DAI Links */
  5092. {
  5093. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  5094. .stream_name = "TX CDC DMA3 Capture",
  5095. .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
  5096. .platform_name = "msm-pcm-routing",
  5097. .codec_name = "bolero_codec",
  5098. .codec_dai_name = "tx_macro_tx1",
  5099. .no_pcm = 1,
  5100. .dpcm_capture = 1,
  5101. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  5102. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5103. .ignore_suspend = 1,
  5104. .ops = &msm_cdc_dma_be_ops,
  5105. },
  5106. {
  5107. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  5108. .stream_name = "TX CDC DMA4 Capture",
  5109. .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
  5110. .platform_name = "msm-pcm-routing",
  5111. .codec_name = "bolero_codec",
  5112. .codec_dai_name = "tx_macro_tx2",
  5113. .no_pcm = 1,
  5114. .dpcm_capture = 1,
  5115. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  5116. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5117. .ignore_suspend = 1,
  5118. .ops = &msm_cdc_dma_be_ops,
  5119. },
  5120. };
  5121. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  5122. {
  5123. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  5124. .stream_name = "VA CDC DMA0 Capture",
  5125. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  5126. .platform_name = "msm-pcm-routing",
  5127. .codec_name = "bolero_codec",
  5128. .codec_dai_name = "va_macro_tx1",
  5129. .no_pcm = 1,
  5130. .dpcm_capture = 1,
  5131. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  5132. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5133. .ignore_suspend = 1,
  5134. .ops = &msm_cdc_dma_be_ops,
  5135. },
  5136. {
  5137. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  5138. .stream_name = "VA CDC DMA1 Capture",
  5139. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  5140. .platform_name = "msm-pcm-routing",
  5141. .codec_name = "bolero_codec",
  5142. .codec_dai_name = "va_macro_tx2",
  5143. .no_pcm = 1,
  5144. .dpcm_capture = 1,
  5145. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  5146. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5147. .ignore_suspend = 1,
  5148. .ops = &msm_cdc_dma_be_ops,
  5149. },
  5150. {
  5151. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  5152. .stream_name = "VA CDC DMA2 Capture",
  5153. .cpu_dai_name = "msm-dai-cdc-dma-dev.45093",
  5154. .platform_name = "msm-pcm-routing",
  5155. .codec_name = "bolero_codec",
  5156. .codec_dai_name = "va_macro_tx3",
  5157. .no_pcm = 1,
  5158. .dpcm_capture = 1,
  5159. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  5160. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5161. .ignore_suspend = 1,
  5162. .ops = &msm_cdc_dma_be_ops,
  5163. },
  5164. };
  5165. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  5166. {
  5167. .name = LPASS_BE_AFE_LOOPBACK_TX,
  5168. .stream_name = "AFE Loopback Capture",
  5169. .cpu_dai_name = "msm-dai-q6-dev.24577",
  5170. .platform_name = "msm-pcm-routing",
  5171. .codec_name = "msm-stub-codec.1",
  5172. .codec_dai_name = "msm-stub-tx",
  5173. .no_pcm = 1,
  5174. .dpcm_capture = 1,
  5175. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  5176. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5177. .ignore_pmdown_time = 1,
  5178. .ignore_suspend = 1,
  5179. },
  5180. };
  5181. static struct snd_soc_dai_link msm_kona_dai_links[
  5182. ARRAY_SIZE(msm_common_dai_links) +
  5183. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  5184. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  5185. ARRAY_SIZE(msm_common_be_dai_links) +
  5186. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  5187. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  5188. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  5189. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  5190. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  5191. ARRAY_SIZE(ext_disp_be_dai_link) +
  5192. ARRAY_SIZE(msm_wcn_be_dai_links) +
  5193. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  5194. ARRAY_SIZE(msm_wcn_btfm_be_dai_links)];
  5195. static int msm_populate_dai_link_component_of_node(
  5196. struct snd_soc_card *card)
  5197. {
  5198. int i, index, ret = 0;
  5199. struct device *cdev = card->dev;
  5200. struct snd_soc_dai_link *dai_link = card->dai_link;
  5201. struct device_node *np;
  5202. if (!cdev) {
  5203. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  5204. return -ENODEV;
  5205. }
  5206. for (i = 0; i < card->num_links; i++) {
  5207. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  5208. continue;
  5209. /* populate platform_of_node for snd card dai links */
  5210. if (dai_link[i].platform_name &&
  5211. !dai_link[i].platform_of_node) {
  5212. index = of_property_match_string(cdev->of_node,
  5213. "asoc-platform-names",
  5214. dai_link[i].platform_name);
  5215. if (index < 0) {
  5216. dev_err(cdev, "%s: No match found for platform name: %s\n",
  5217. __func__, dai_link[i].platform_name);
  5218. ret = index;
  5219. goto err;
  5220. }
  5221. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  5222. index);
  5223. if (!np) {
  5224. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  5225. __func__, dai_link[i].platform_name,
  5226. index);
  5227. ret = -ENODEV;
  5228. goto err;
  5229. }
  5230. dai_link[i].platform_of_node = np;
  5231. dai_link[i].platform_name = NULL;
  5232. }
  5233. /* populate cpu_of_node for snd card dai links */
  5234. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  5235. index = of_property_match_string(cdev->of_node,
  5236. "asoc-cpu-names",
  5237. dai_link[i].cpu_dai_name);
  5238. if (index >= 0) {
  5239. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  5240. index);
  5241. if (!np) {
  5242. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  5243. __func__,
  5244. dai_link[i].cpu_dai_name);
  5245. ret = -ENODEV;
  5246. goto err;
  5247. }
  5248. dai_link[i].cpu_of_node = np;
  5249. dai_link[i].cpu_dai_name = NULL;
  5250. }
  5251. }
  5252. /* populate codec_of_node for snd card dai links */
  5253. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  5254. index = of_property_match_string(cdev->of_node,
  5255. "asoc-codec-names",
  5256. dai_link[i].codec_name);
  5257. if (index < 0)
  5258. continue;
  5259. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  5260. index);
  5261. if (!np) {
  5262. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  5263. __func__, dai_link[i].codec_name);
  5264. ret = -ENODEV;
  5265. goto err;
  5266. }
  5267. dai_link[i].codec_of_node = np;
  5268. dai_link[i].codec_name = NULL;
  5269. }
  5270. }
  5271. err:
  5272. return ret;
  5273. }
  5274. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  5275. {
  5276. int ret = -EINVAL;
  5277. struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  5278. if (!component) {
  5279. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  5280. return ret;
  5281. }
  5282. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  5283. ARRAY_SIZE(msm_snd_controls));
  5284. if (ret < 0) {
  5285. dev_err(component->dev,
  5286. "%s: add_codec_controls failed, err = %d\n",
  5287. __func__, ret);
  5288. return ret;
  5289. }
  5290. return ret;
  5291. }
  5292. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  5293. struct snd_pcm_hw_params *params)
  5294. {
  5295. return 0;
  5296. }
  5297. static struct snd_soc_ops msm_stub_be_ops = {
  5298. .hw_params = msm_snd_stub_hw_params,
  5299. };
  5300. struct snd_soc_card snd_soc_card_stub_msm = {
  5301. .name = "kona-stub-snd-card",
  5302. };
  5303. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  5304. /* FrontEnd DAI Links */
  5305. {
  5306. .name = "MSMSTUB Media1",
  5307. .stream_name = "MultiMedia1",
  5308. .cpu_dai_name = "MultiMedia1",
  5309. .platform_name = "msm-pcm-dsp.0",
  5310. .dynamic = 1,
  5311. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5312. .dpcm_playback = 1,
  5313. .dpcm_capture = 1,
  5314. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5315. SND_SOC_DPCM_TRIGGER_POST},
  5316. .codec_dai_name = "snd-soc-dummy-dai",
  5317. .codec_name = "snd-soc-dummy",
  5318. .ignore_suspend = 1,
  5319. /* this dainlink has playback support */
  5320. .ignore_pmdown_time = 1,
  5321. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5322. },
  5323. };
  5324. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  5325. /* Backend DAI Links */
  5326. {
  5327. .name = LPASS_BE_AUXPCM_RX,
  5328. .stream_name = "AUX PCM Playback",
  5329. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5330. .platform_name = "msm-pcm-routing",
  5331. .codec_name = "msm-stub-codec.1",
  5332. .codec_dai_name = "msm-stub-rx",
  5333. .no_pcm = 1,
  5334. .dpcm_playback = 1,
  5335. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5336. .init = &msm_audrx_stub_init,
  5337. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5338. .ignore_pmdown_time = 1,
  5339. .ignore_suspend = 1,
  5340. .ops = &msm_stub_be_ops,
  5341. },
  5342. {
  5343. .name = LPASS_BE_AUXPCM_TX,
  5344. .stream_name = "AUX PCM Capture",
  5345. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5346. .platform_name = "msm-pcm-routing",
  5347. .codec_name = "msm-stub-codec.1",
  5348. .codec_dai_name = "msm-stub-tx",
  5349. .no_pcm = 1,
  5350. .dpcm_capture = 1,
  5351. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5352. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5353. .ignore_suspend = 1,
  5354. .ops = &msm_stub_be_ops,
  5355. },
  5356. };
  5357. static struct snd_soc_dai_link msm_stub_dai_links[
  5358. ARRAY_SIZE(msm_stub_fe_dai_links) +
  5359. ARRAY_SIZE(msm_stub_be_dai_links)];
  5360. static const struct of_device_id kona_asoc_machine_of_match[] = {
  5361. { .compatible = "qcom,kona-asoc-snd",
  5362. .data = "codec"},
  5363. { .compatible = "qcom,kona-asoc-snd-stub",
  5364. .data = "stub_codec"},
  5365. {},
  5366. };
  5367. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  5368. {
  5369. struct snd_soc_card *card = NULL;
  5370. struct snd_soc_dai_link *dailink = NULL;
  5371. int len_1 = 0;
  5372. int len_2 = 0;
  5373. int total_links = 0;
  5374. int rc = 0;
  5375. u32 mi2s_audio_intf = 0;
  5376. u32 auxpcm_audio_intf = 0;
  5377. u32 val = 0;
  5378. u32 wcn_btfm_intf = 0;
  5379. const struct of_device_id *match;
  5380. match = of_match_node(kona_asoc_machine_of_match, dev->of_node);
  5381. if (!match) {
  5382. dev_err(dev, "%s: No DT match found for sound card\n",
  5383. __func__);
  5384. return NULL;
  5385. }
  5386. if (!strcmp(match->data, "codec")) {
  5387. card = &snd_soc_card_kona_msm;
  5388. memcpy(msm_kona_dai_links + total_links,
  5389. msm_common_dai_links,
  5390. sizeof(msm_common_dai_links));
  5391. total_links += ARRAY_SIZE(msm_common_dai_links);
  5392. memcpy(msm_kona_dai_links + total_links,
  5393. msm_bolero_fe_dai_links,
  5394. sizeof(msm_bolero_fe_dai_links));
  5395. total_links +=
  5396. ARRAY_SIZE(msm_bolero_fe_dai_links);
  5397. memcpy(msm_kona_dai_links + total_links,
  5398. msm_common_misc_fe_dai_links,
  5399. sizeof(msm_common_misc_fe_dai_links));
  5400. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  5401. memcpy(msm_kona_dai_links + total_links,
  5402. msm_common_be_dai_links,
  5403. sizeof(msm_common_be_dai_links));
  5404. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  5405. memcpy(msm_kona_dai_links + total_links,
  5406. msm_wsa_cdc_dma_be_dai_links,
  5407. sizeof(msm_wsa_cdc_dma_be_dai_links));
  5408. total_links +=
  5409. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  5410. memcpy(msm_kona_dai_links + total_links,
  5411. msm_rx_tx_cdc_dma_be_dai_links,
  5412. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  5413. total_links +=
  5414. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  5415. memcpy(msm_kona_dai_links + total_links,
  5416. msm_va_cdc_dma_be_dai_links,
  5417. sizeof(msm_va_cdc_dma_be_dai_links));
  5418. total_links +=
  5419. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  5420. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  5421. &mi2s_audio_intf);
  5422. if (rc) {
  5423. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  5424. __func__);
  5425. } else {
  5426. if (mi2s_audio_intf) {
  5427. memcpy(msm_kona_dai_links + total_links,
  5428. msm_mi2s_be_dai_links,
  5429. sizeof(msm_mi2s_be_dai_links));
  5430. total_links +=
  5431. ARRAY_SIZE(msm_mi2s_be_dai_links);
  5432. }
  5433. }
  5434. rc = of_property_read_u32(dev->of_node,
  5435. "qcom,auxpcm-audio-intf",
  5436. &auxpcm_audio_intf);
  5437. if (rc) {
  5438. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  5439. __func__);
  5440. } else {
  5441. if (auxpcm_audio_intf) {
  5442. memcpy(msm_kona_dai_links + total_links,
  5443. msm_auxpcm_be_dai_links,
  5444. sizeof(msm_auxpcm_be_dai_links));
  5445. total_links +=
  5446. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  5447. }
  5448. }
  5449. rc = of_property_read_u32(dev->of_node,
  5450. "qcom,ext-disp-audio-rx", &val);
  5451. if (!rc && val) {
  5452. dev_dbg(dev, "%s(): ext disp audio support present\n",
  5453. __func__);
  5454. memcpy(msm_kona_dai_links + total_links,
  5455. ext_disp_be_dai_link,
  5456. sizeof(ext_disp_be_dai_link));
  5457. total_links += ARRAY_SIZE(ext_disp_be_dai_link);
  5458. }
  5459. rc = of_property_read_u32(dev->of_node, "qcom,wcn-bt", &val);
  5460. if (!rc && val) {
  5461. dev_dbg(dev, "%s(): WCN BT support present\n",
  5462. __func__);
  5463. memcpy(msm_kona_dai_links + total_links,
  5464. msm_wcn_be_dai_links,
  5465. sizeof(msm_wcn_be_dai_links));
  5466. total_links += ARRAY_SIZE(msm_wcn_be_dai_links);
  5467. }
  5468. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  5469. &val);
  5470. if (!rc && val) {
  5471. memcpy(msm_kona_dai_links + total_links,
  5472. msm_afe_rxtx_lb_be_dai_link,
  5473. sizeof(msm_afe_rxtx_lb_be_dai_link));
  5474. total_links +=
  5475. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  5476. }
  5477. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  5478. &wcn_btfm_intf);
  5479. if (rc) {
  5480. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  5481. __func__);
  5482. } else {
  5483. if (wcn_btfm_intf) {
  5484. memcpy(msm_kona_dai_links + total_links,
  5485. msm_wcn_btfm_be_dai_links,
  5486. sizeof(msm_wcn_btfm_be_dai_links));
  5487. total_links +=
  5488. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  5489. }
  5490. }
  5491. dailink = msm_kona_dai_links;
  5492. } else if(!strcmp(match->data, "stub_codec")) {
  5493. card = &snd_soc_card_stub_msm;
  5494. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  5495. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  5496. memcpy(msm_stub_dai_links,
  5497. msm_stub_fe_dai_links,
  5498. sizeof(msm_stub_fe_dai_links));
  5499. memcpy(msm_stub_dai_links + len_1,
  5500. msm_stub_be_dai_links,
  5501. sizeof(msm_stub_be_dai_links));
  5502. dailink = msm_stub_dai_links;
  5503. total_links = len_2;
  5504. }
  5505. if (card) {
  5506. card->dai_link = dailink;
  5507. card->num_links = total_links;
  5508. }
  5509. return card;
  5510. }
  5511. static int msm_wsa881x_init(struct snd_soc_component *component)
  5512. {
  5513. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  5514. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  5515. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  5516. SPKR_L_BOOST, SPKR_L_VI};
  5517. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  5518. SPKR_R_BOOST, SPKR_R_VI};
  5519. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  5520. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  5521. struct msm_asoc_mach_data *pdata;
  5522. struct snd_soc_dapm_context *dapm;
  5523. struct snd_card *card;
  5524. struct snd_info_entry *entry;
  5525. int ret = 0;
  5526. if (!component) {
  5527. pr_err("%s component is NULL\n", __func__);
  5528. return -EINVAL;
  5529. }
  5530. card = component->card->snd_card;
  5531. dapm = snd_soc_component_get_dapm(component);
  5532. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  5533. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  5534. __func__, component->name);
  5535. wsa881x_set_channel_map(component, &spkleft_ports[0],
  5536. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  5537. &ch_rate[0], &spkleft_port_types[0]);
  5538. if (dapm->component) {
  5539. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  5540. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  5541. }
  5542. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  5543. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  5544. __func__, component->name);
  5545. wsa881x_set_channel_map(component, &spkright_ports[0],
  5546. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  5547. &ch_rate[0], &spkright_port_types[0]);
  5548. if (dapm->component) {
  5549. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  5550. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  5551. }
  5552. } else {
  5553. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  5554. component->name);
  5555. ret = -EINVAL;
  5556. goto err;
  5557. }
  5558. pdata = snd_soc_card_get_drvdata(component->card);
  5559. if (!pdata->codec_root) {
  5560. entry = snd_info_create_subdir(card->module, "codecs",
  5561. card->proc_root);
  5562. if (!entry) {
  5563. pr_err("%s: Cannot create codecs module entry\n",
  5564. __func__);
  5565. ret = 0;
  5566. goto err;
  5567. }
  5568. pdata->codec_root = entry;
  5569. }
  5570. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  5571. component);
  5572. err:
  5573. return ret;
  5574. }
  5575. static int msm_aux_codec_init(struct snd_soc_component *component)
  5576. {
  5577. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  5578. int ret = 0;
  5579. void *mbhc_calibration;
  5580. struct snd_info_entry *entry;
  5581. struct snd_card *card = component->card->snd_card;
  5582. struct msm_asoc_mach_data *pdata;
  5583. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  5584. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  5585. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  5586. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  5587. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  5588. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  5589. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  5590. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  5591. snd_soc_dapm_sync(dapm);
  5592. pdata = snd_soc_card_get_drvdata(component->card);
  5593. if (!pdata->codec_root) {
  5594. entry = snd_info_create_subdir(card->module, "codecs",
  5595. card->proc_root);
  5596. if (!entry) {
  5597. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  5598. __func__);
  5599. ret = 0;
  5600. goto mbhc_cfg_cal;
  5601. }
  5602. pdata->codec_root = entry;
  5603. }
  5604. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  5605. mbhc_cfg_cal:
  5606. mbhc_calibration = def_wcd_mbhc_cal();
  5607. if (!mbhc_calibration)
  5608. return -ENOMEM;
  5609. wcd_mbhc_cfg.calibration = mbhc_calibration;
  5610. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  5611. if (ret) {
  5612. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  5613. __func__, ret);
  5614. goto err_hs_detect;
  5615. }
  5616. return 0;
  5617. err_hs_detect:
  5618. kfree(mbhc_calibration);
  5619. return ret;
  5620. }
  5621. static int msm_init_aux_dev(struct platform_device *pdev,
  5622. struct snd_soc_card *card)
  5623. {
  5624. struct device_node *wsa_of_node;
  5625. struct device_node *aux_codec_of_node;
  5626. u32 wsa_max_devs;
  5627. u32 wsa_dev_cnt;
  5628. u32 codec_aux_dev_cnt = 0;
  5629. int i;
  5630. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  5631. struct aux_codec_dev_info *aux_cdc_dev_info;
  5632. const char *auxdev_name_prefix[1];
  5633. char *dev_name_str = NULL;
  5634. int found = 0;
  5635. int codecs_found = 0;
  5636. int ret = 0;
  5637. /* Get maximum WSA device count for this platform */
  5638. ret = of_property_read_u32(pdev->dev.of_node,
  5639. "qcom,wsa-max-devs", &wsa_max_devs);
  5640. if (ret) {
  5641. dev_info(&pdev->dev,
  5642. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  5643. __func__, pdev->dev.of_node->full_name, ret);
  5644. wsa_max_devs = 0;
  5645. goto codec_aux_dev;
  5646. }
  5647. if (wsa_max_devs == 0) {
  5648. dev_warn(&pdev->dev,
  5649. "%s: Max WSA devices is 0 for this target?\n",
  5650. __func__);
  5651. goto codec_aux_dev;
  5652. }
  5653. /* Get count of WSA device phandles for this platform */
  5654. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  5655. "qcom,wsa-devs", NULL);
  5656. if (wsa_dev_cnt == -ENOENT) {
  5657. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  5658. __func__);
  5659. goto err;
  5660. } else if (wsa_dev_cnt <= 0) {
  5661. dev_err(&pdev->dev,
  5662. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  5663. __func__, wsa_dev_cnt);
  5664. ret = -EINVAL;
  5665. goto err;
  5666. }
  5667. /*
  5668. * Expect total phandles count to be NOT less than maximum possible
  5669. * WSA count. However, if it is less, then assign same value to
  5670. * max count as well.
  5671. */
  5672. if (wsa_dev_cnt < wsa_max_devs) {
  5673. dev_dbg(&pdev->dev,
  5674. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  5675. __func__, wsa_max_devs, wsa_dev_cnt);
  5676. wsa_max_devs = wsa_dev_cnt;
  5677. }
  5678. /* Make sure prefix string passed for each WSA device */
  5679. ret = of_property_count_strings(pdev->dev.of_node,
  5680. "qcom,wsa-aux-dev-prefix");
  5681. if (ret != wsa_dev_cnt) {
  5682. dev_err(&pdev->dev,
  5683. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  5684. __func__, wsa_dev_cnt, ret);
  5685. ret = -EINVAL;
  5686. goto err;
  5687. }
  5688. /*
  5689. * Alloc mem to store phandle and index info of WSA device, if already
  5690. * registered with ALSA core
  5691. */
  5692. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  5693. sizeof(struct msm_wsa881x_dev_info),
  5694. GFP_KERNEL);
  5695. if (!wsa881x_dev_info) {
  5696. ret = -ENOMEM;
  5697. goto err;
  5698. }
  5699. /*
  5700. * search and check whether all WSA devices are already
  5701. * registered with ALSA core or not. If found a node, store
  5702. * the node and the index in a local array of struct for later
  5703. * use.
  5704. */
  5705. for (i = 0; i < wsa_dev_cnt; i++) {
  5706. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  5707. "qcom,wsa-devs", i);
  5708. if (unlikely(!wsa_of_node)) {
  5709. /* we should not be here */
  5710. dev_err(&pdev->dev,
  5711. "%s: wsa dev node is not present\n",
  5712. __func__);
  5713. ret = -EINVAL;
  5714. goto err;
  5715. }
  5716. if (soc_find_component(wsa_of_node, NULL)) {
  5717. /* WSA device registered with ALSA core */
  5718. wsa881x_dev_info[found].of_node = wsa_of_node;
  5719. wsa881x_dev_info[found].index = i;
  5720. found++;
  5721. if (found == wsa_max_devs)
  5722. break;
  5723. }
  5724. }
  5725. if (found < wsa_max_devs) {
  5726. dev_dbg(&pdev->dev,
  5727. "%s: failed to find %d components. Found only %d\n",
  5728. __func__, wsa_max_devs, found);
  5729. return -EPROBE_DEFER;
  5730. }
  5731. dev_info(&pdev->dev,
  5732. "%s: found %d wsa881x devices registered with ALSA core\n",
  5733. __func__, found);
  5734. codec_aux_dev:
  5735. /* Get count of aux codec device phandles for this platform */
  5736. codec_aux_dev_cnt = of_count_phandle_with_args(
  5737. pdev->dev.of_node,
  5738. "qcom,codec-aux-devs", NULL);
  5739. if (codec_aux_dev_cnt == -ENOENT) {
  5740. dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
  5741. __func__);
  5742. goto err;
  5743. } else if (codec_aux_dev_cnt <= 0) {
  5744. dev_err(&pdev->dev,
  5745. "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
  5746. __func__, codec_aux_dev_cnt);
  5747. ret = -EINVAL;
  5748. goto err;
  5749. }
  5750. /*
  5751. * Alloc mem to store phandle and index info of aux codec
  5752. * if already registered with ALSA core
  5753. */
  5754. aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_aux_dev_cnt,
  5755. sizeof(struct aux_codec_dev_info),
  5756. GFP_KERNEL);
  5757. if (!aux_cdc_dev_info) {
  5758. ret = -ENOMEM;
  5759. goto err;
  5760. }
  5761. /*
  5762. * search and check whether all aux codecs are already
  5763. * registered with ALSA core or not. If found a node, store
  5764. * the node and the index in a local array of struct for later
  5765. * use.
  5766. */
  5767. for (i = 0; i < codec_aux_dev_cnt; i++) {
  5768. aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
  5769. "qcom,codec-aux-devs", i);
  5770. if (unlikely(!aux_codec_of_node)) {
  5771. /* we should not be here */
  5772. dev_err(&pdev->dev,
  5773. "%s: aux codec dev node is not present\n",
  5774. __func__);
  5775. ret = -EINVAL;
  5776. goto err;
  5777. }
  5778. if (soc_find_component(aux_codec_of_node, NULL)) {
  5779. /* AUX codec registered with ALSA core */
  5780. aux_cdc_dev_info[codecs_found].of_node =
  5781. aux_codec_of_node;
  5782. aux_cdc_dev_info[codecs_found].index = i;
  5783. codecs_found++;
  5784. }
  5785. }
  5786. if (codecs_found < codec_aux_dev_cnt) {
  5787. dev_dbg(&pdev->dev,
  5788. "%s: failed to find %d components. Found only %d\n",
  5789. __func__, codec_aux_dev_cnt, codecs_found);
  5790. return -EPROBE_DEFER;
  5791. }
  5792. dev_info(&pdev->dev,
  5793. "%s: found %d AUX codecs registered with ALSA core\n",
  5794. __func__, codecs_found);
  5795. card->num_aux_devs = wsa_max_devs + codec_aux_dev_cnt;
  5796. card->num_configs = wsa_max_devs + codec_aux_dev_cnt;
  5797. /* Alloc array of AUX devs struct */
  5798. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  5799. sizeof(struct snd_soc_aux_dev),
  5800. GFP_KERNEL);
  5801. if (!msm_aux_dev) {
  5802. ret = -ENOMEM;
  5803. goto err;
  5804. }
  5805. /* Alloc array of codec conf struct */
  5806. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
  5807. sizeof(struct snd_soc_codec_conf),
  5808. GFP_KERNEL);
  5809. if (!msm_codec_conf) {
  5810. ret = -ENOMEM;
  5811. goto err;
  5812. }
  5813. for (i = 0; i < wsa_max_devs; i++) {
  5814. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  5815. GFP_KERNEL);
  5816. if (!dev_name_str) {
  5817. ret = -ENOMEM;
  5818. goto err;
  5819. }
  5820. ret = of_property_read_string_index(pdev->dev.of_node,
  5821. "qcom,wsa-aux-dev-prefix",
  5822. wsa881x_dev_info[i].index,
  5823. auxdev_name_prefix);
  5824. if (ret) {
  5825. dev_err(&pdev->dev,
  5826. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  5827. __func__, ret);
  5828. ret = -EINVAL;
  5829. goto err;
  5830. }
  5831. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  5832. msm_aux_dev[i].name = dev_name_str;
  5833. msm_aux_dev[i].codec_name = NULL;
  5834. msm_aux_dev[i].codec_of_node =
  5835. wsa881x_dev_info[i].of_node;
  5836. msm_aux_dev[i].init = msm_wsa881x_init;
  5837. msm_codec_conf[i].dev_name = NULL;
  5838. msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
  5839. msm_codec_conf[i].of_node =
  5840. wsa881x_dev_info[i].of_node;
  5841. }
  5842. for (i = 0; i < codec_aux_dev_cnt; i++) {
  5843. msm_aux_dev[wsa_max_devs + i].name = NULL;
  5844. msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
  5845. msm_aux_dev[wsa_max_devs + i].codec_of_node =
  5846. aux_cdc_dev_info[i].of_node;
  5847. msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
  5848. msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
  5849. msm_codec_conf[wsa_max_devs + i].name_prefix =
  5850. NULL;
  5851. msm_codec_conf[wsa_max_devs + i].of_node =
  5852. aux_cdc_dev_info[i].of_node;
  5853. }
  5854. card->codec_conf = msm_codec_conf;
  5855. card->aux_dev = msm_aux_dev;
  5856. err:
  5857. return ret;
  5858. }
  5859. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  5860. {
  5861. int count = 0;
  5862. u32 mi2s_master_slave[MI2S_MAX];
  5863. int ret = 0;
  5864. for (count = 0; count < MI2S_MAX; count++) {
  5865. mutex_init(&mi2s_intf_conf[count].lock);
  5866. mi2s_intf_conf[count].ref_cnt = 0;
  5867. }
  5868. ret = of_property_read_u32_array(pdev->dev.of_node,
  5869. "qcom,msm-mi2s-master",
  5870. mi2s_master_slave, MI2S_MAX);
  5871. if (ret) {
  5872. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  5873. __func__);
  5874. } else {
  5875. for (count = 0; count < MI2S_MAX; count++) {
  5876. mi2s_intf_conf[count].msm_is_mi2s_master =
  5877. mi2s_master_slave[count];
  5878. }
  5879. }
  5880. }
  5881. static void msm_i2s_auxpcm_deinit(void)
  5882. {
  5883. int count = 0;
  5884. for (count = 0; count < MI2S_MAX; count++) {
  5885. mutex_destroy(&mi2s_intf_conf[count].lock);
  5886. mi2s_intf_conf[count].ref_cnt = 0;
  5887. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  5888. }
  5889. }
  5890. static int kona_ssr_enable(struct device *dev, void *data)
  5891. {
  5892. struct platform_device *pdev = to_platform_device(dev);
  5893. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5894. int ret = 0;
  5895. if (!card) {
  5896. dev_err(dev, "%s: card is NULL\n", __func__);
  5897. ret = -EINVAL;
  5898. goto err;
  5899. }
  5900. if (!strcmp(card->name, "kona-stub-snd-card")) {
  5901. /* TODO */
  5902. dev_dbg(dev, "%s: TODO \n", __func__);
  5903. }
  5904. snd_soc_card_change_online_state(card, 1);
  5905. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  5906. err:
  5907. return ret;
  5908. }
  5909. static void kona_ssr_disable(struct device *dev, void *data)
  5910. {
  5911. struct platform_device *pdev = to_platform_device(dev);
  5912. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5913. if (!card) {
  5914. dev_err(dev, "%s: card is NULL\n", __func__);
  5915. return;
  5916. }
  5917. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  5918. snd_soc_card_change_online_state(card, 0);
  5919. if (!strcmp(card->name, "kona-stub-snd-card")) {
  5920. /* TODO */
  5921. dev_dbg(dev, "%s: TODO \n", __func__);
  5922. }
  5923. }
  5924. static const struct snd_event_ops kona_ssr_ops = {
  5925. .enable = kona_ssr_enable,
  5926. .disable = kona_ssr_disable,
  5927. };
  5928. static int msm_audio_ssr_compare(struct device *dev, void *data)
  5929. {
  5930. struct device_node *node = data;
  5931. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  5932. __func__, dev->of_node, node);
  5933. return (dev->of_node && dev->of_node == node);
  5934. }
  5935. static int msm_audio_ssr_register(struct device *dev)
  5936. {
  5937. struct device_node *np = dev->of_node;
  5938. struct snd_event_clients *ssr_clients = NULL;
  5939. struct device_node *node = NULL;
  5940. int ret = 0;
  5941. int i = 0;
  5942. for (i = 0; ; i++) {
  5943. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  5944. if (!node)
  5945. break;
  5946. snd_event_mstr_add_client(&ssr_clients,
  5947. msm_audio_ssr_compare, node);
  5948. }
  5949. ret = snd_event_master_register(dev, &kona_ssr_ops,
  5950. ssr_clients, NULL);
  5951. if (!ret)
  5952. snd_event_notify(dev, SND_EVENT_UP);
  5953. return ret;
  5954. }
  5955. static int msm_asoc_machine_probe(struct platform_device *pdev)
  5956. {
  5957. struct snd_soc_card *card = NULL;
  5958. struct msm_asoc_mach_data *pdata = NULL;
  5959. const char *mbhc_audio_jack_type = NULL;
  5960. int ret = 0;
  5961. if (!pdev->dev.of_node) {
  5962. dev_err(&pdev->dev, "%s: No platform supplied from device tree\n", __func__);
  5963. return -EINVAL;
  5964. }
  5965. pdata = devm_kzalloc(&pdev->dev,
  5966. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  5967. if (!pdata)
  5968. return -ENOMEM;
  5969. card = populate_snd_card_dailinks(&pdev->dev);
  5970. if (!card) {
  5971. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  5972. ret = -EINVAL;
  5973. goto err;
  5974. }
  5975. card->dev = &pdev->dev;
  5976. platform_set_drvdata(pdev, card);
  5977. snd_soc_card_set_drvdata(card, pdata);
  5978. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  5979. if (ret) {
  5980. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  5981. __func__, ret);
  5982. goto err;
  5983. }
  5984. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  5985. if (ret) {
  5986. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  5987. __func__, ret);
  5988. goto err;
  5989. }
  5990. ret = msm_populate_dai_link_component_of_node(card);
  5991. if (ret) {
  5992. ret = -EPROBE_DEFER;
  5993. goto err;
  5994. }
  5995. ret = msm_init_aux_dev(pdev, card);
  5996. if (ret)
  5997. goto err;
  5998. ret = devm_snd_soc_register_card(&pdev->dev, card);
  5999. if (ret == -EPROBE_DEFER) {
  6000. if (codec_reg_done)
  6001. ret = -EINVAL;
  6002. goto err;
  6003. } else if (ret) {
  6004. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  6005. __func__, ret);
  6006. goto err;
  6007. }
  6008. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  6009. __func__, card->name);
  6010. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6011. "qcom,hph-en1-gpio", 0);
  6012. if (!pdata->hph_en1_gpio_p) {
  6013. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6014. __func__, "qcom,hph-en1-gpio",
  6015. pdev->dev.of_node->full_name);
  6016. }
  6017. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6018. "qcom,hph-en0-gpio", 0);
  6019. if (!pdata->hph_en0_gpio_p) {
  6020. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6021. __func__, "qcom,hph-en0-gpio",
  6022. pdev->dev.of_node->full_name);
  6023. }
  6024. ret = of_property_read_string(pdev->dev.of_node,
  6025. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  6026. if (ret) {
  6027. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  6028. __func__, "qcom,mbhc-audio-jack-type",
  6029. pdev->dev.of_node->full_name);
  6030. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  6031. } else {
  6032. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  6033. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6034. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  6035. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  6036. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6037. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  6038. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  6039. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6040. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  6041. } else {
  6042. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6043. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  6044. }
  6045. }
  6046. /*
  6047. * Parse US-Euro gpio info from DT. Report no error if us-euro
  6048. * entry is not found in DT file as some targets do not support
  6049. * US-Euro detection
  6050. */
  6051. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6052. "qcom,us-euro-gpios", 0);
  6053. if (!pdata->us_euro_gpio_p) {
  6054. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  6055. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  6056. } else {
  6057. dev_dbg(&pdev->dev, "%s detected\n",
  6058. "qcom,us-euro-gpios");
  6059. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  6060. }
  6061. if (wcd_mbhc_cfg.enable_usbc_analog)
  6062. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  6063. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  6064. "fsa4480-i2c-handle", 0);
  6065. if (!pdata->fsa_handle)
  6066. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  6067. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  6068. msm_i2s_auxpcm_init(pdev);
  6069. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6070. "qcom,cdc-dmic01-gpios",
  6071. 0);
  6072. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6073. "qcom,cdc-dmic23-gpios",
  6074. 0);
  6075. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6076. "qcom,cdc-dmic45-gpios",
  6077. 0);
  6078. ret = msm_audio_ssr_register(&pdev->dev);
  6079. if (ret)
  6080. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  6081. __func__, ret);
  6082. is_initial_boot = true;
  6083. return 0;
  6084. err:
  6085. devm_kfree(&pdev->dev, pdata);
  6086. return ret;
  6087. }
  6088. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6089. {
  6090. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6091. snd_event_master_deregister(&pdev->dev);
  6092. snd_soc_unregister_card(card);
  6093. msm_i2s_auxpcm_deinit();
  6094. return 0;
  6095. }
  6096. static struct platform_driver kona_asoc_machine_driver = {
  6097. .driver = {
  6098. .name = DRV_NAME,
  6099. .owner = THIS_MODULE,
  6100. .pm = &snd_soc_pm_ops,
  6101. .of_match_table = kona_asoc_machine_of_match,
  6102. },
  6103. .probe = msm_asoc_machine_probe,
  6104. .remove = msm_asoc_machine_remove,
  6105. };
  6106. module_platform_driver(kona_asoc_machine_driver);
  6107. MODULE_DESCRIPTION("ALSA SoC msm");
  6108. MODULE_LICENSE("GPL v2");
  6109. MODULE_ALIAS("platform:" DRV_NAME);
  6110. MODULE_DEVICE_TABLE(of, kona_asoc_machine_of_match);