internal.h 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  3. */
  4. #ifndef _WCD937X_INTERNAL_H
  5. #define _WCD937X_INTERNAL_H
  6. #include <asoc/wcd-clsh.h>
  7. #include <asoc/wcd-mbhc-v2.h>
  8. #include <asoc/wcd-irq.h>
  9. #include "wcd937x-mbhc.h"
  10. #define WCD937X_MAX_MICBIAS 3
  11. /* Convert from vout ctl to micbias voltage in mV */
  12. #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
  13. #define MAX_PORT 8
  14. #define MAX_CH_PER_PORT 8
  15. extern struct regmap_config wcd937x_regmap_config;
  16. struct codec_port_info {
  17. u32 slave_port_type;
  18. u32 master_port_type;
  19. u32 ch_mask;
  20. u32 num_ch;
  21. u32 ch_rate;
  22. };
  23. struct wcd937x_priv {
  24. struct device *dev;
  25. int variant;
  26. struct snd_soc_component *component;
  27. struct device_node *rst_np;
  28. struct regmap *regmap;
  29. struct swr_device *rx_swr_dev;
  30. struct swr_device *tx_swr_dev;
  31. s32 micb_ref[WCD937X_MAX_MICBIAS];
  32. s32 pullup_ref[WCD937X_MAX_MICBIAS];
  33. struct fw_info *fw_data;
  34. struct device_node *wcd_rst_np;
  35. struct mutex micb_lock;
  36. s32 dmic_0_1_clk_cnt;
  37. s32 dmic_2_3_clk_cnt;
  38. s32 dmic_4_5_clk_cnt;
  39. /* class h specific info */
  40. struct wcd_clsh_cdc_info clsh_info;
  41. /* mbhc module */
  42. struct wcd937x_mbhc *mbhc;
  43. u32 hph_mode;
  44. bool comp1_enable;
  45. bool comp2_enable;
  46. struct irq_domain *virq;
  47. struct wcd_irq_info irq_info;
  48. u32 rx_clk_cnt;
  49. int num_irq_regs;
  50. /* to track the status */
  51. unsigned long status_mask;
  52. u8 num_tx_ports;
  53. u8 num_rx_ports;
  54. struct codec_port_info
  55. tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  56. struct codec_port_info
  57. rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  58. struct regulator_bulk_data *supplies;
  59. struct notifier_block nblock;
  60. /* wcd callback to bolero */
  61. void *handle;
  62. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  63. int (*register_notifier)(void *handle,
  64. struct notifier_block *nblock,
  65. bool enable);
  66. int (*wakeup)(void *handle, bool enable);
  67. u32 version;
  68. /* Entry for version info */
  69. struct snd_info_entry *entry;
  70. struct snd_info_entry *version_entry;
  71. int ear_rx_path;
  72. int ana_clk_count;
  73. struct mutex ana_tx_clk_lock;
  74. };
  75. struct wcd937x_micbias_setting {
  76. u8 ldoh_v;
  77. u32 cfilt1_mv;
  78. u32 micb1_mv;
  79. u32 micb2_mv;
  80. u32 micb3_mv;
  81. u8 bias1_cfilt_sel;
  82. };
  83. struct wcd937x_pdata {
  84. struct device_node *rst_np;
  85. struct device_node *rx_slave;
  86. struct device_node *tx_slave;
  87. struct wcd937x_micbias_setting micbias;
  88. struct cdc_regulator *regulator;
  89. int num_supplies;
  90. };
  91. struct wcd_ctrl_platform_data {
  92. void *handle;
  93. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  94. int (*register_notifier)(void *handle,
  95. struct notifier_block *nblock,
  96. bool enable);
  97. };
  98. enum {
  99. WCD_RX1,
  100. WCD_RX2,
  101. WCD_RX3
  102. };
  103. enum {
  104. BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR = 1,
  105. BOLERO_WCD_EVT_PA_OFF_PRE_SSR,
  106. BOLERO_WCD_EVT_SSR_DOWN,
  107. BOLERO_WCD_EVT_SSR_UP,
  108. };
  109. enum {
  110. WCD_BOLERO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
  111. WCD_BOLERO_EVT_IMPED_TRUE, /* for imped true */
  112. WCD_BOLERO_EVT_IMPED_FALSE, /* for imped false */
  113. };
  114. enum {
  115. /* INTR_CTRL_INT_MASK_0 */
  116. WCD937X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
  117. WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET,
  118. WCD937X_IRQ_MBHC_ELECT_INS_REM_DET,
  119. WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
  120. WCD937X_IRQ_MBHC_SW_DET,
  121. WCD937X_IRQ_HPHR_OCP_INT,
  122. WCD937X_IRQ_HPHR_CNP_INT,
  123. WCD937X_IRQ_HPHL_OCP_INT,
  124. /* INTR_CTRL_INT_MASK_1 */
  125. WCD937X_IRQ_HPHL_CNP_INT,
  126. WCD937X_IRQ_EAR_CNP_INT,
  127. WCD937X_IRQ_EAR_SCD_INT,
  128. WCD937X_IRQ_AUX_CNP_INT,
  129. WCD937X_IRQ_AUX_SCD_INT,
  130. WCD937X_IRQ_HPHL_PDM_WD_INT,
  131. WCD937X_IRQ_HPHR_PDM_WD_INT,
  132. WCD937X_IRQ_AUX_PDM_WD_INT,
  133. /* INTR_CTRL_INT_MASK_2 */
  134. WCD937X_IRQ_LDORT_SCD_INT,
  135. WCD937X_IRQ_MBHC_MOISTURE_INT,
  136. WCD937X_IRQ_HPHL_SURGE_DET_INT,
  137. WCD937X_IRQ_HPHR_SURGE_DET_INT,
  138. WCD937X_NUM_IRQS,
  139. };
  140. extern struct wcd937x_mbhc *wcd937x_soc_get_mbhc(
  141. struct snd_soc_component *component);
  142. extern int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  143. int volt, int micb_num);
  144. extern int wcd937x_get_micb_vout_ctl_val(u32 micb_mv);
  145. extern int wcd937x_micbias_control(struct snd_soc_component *component,
  146. int micb_num, int req, bool is_dapm);
  147. #endif