wsa884x.c 67 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/device.h>
  11. #include <linux/printk.h>
  12. #include <linux/bitops.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/delay.h>
  16. #include <linux/kernel.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/regmap.h>
  21. #include <linux/debugfs.h>
  22. #include <soc/soundwire.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/tlv.h>
  28. #include <asoc/msm-cdc-pinctrl.h>
  29. #include <asoc/msm-cdc-supply.h>
  30. #include "wsa884x.h"
  31. #include "internal.h"
  32. #include "asoc/bolero-slave-internal.h"
  33. #include <linux/qti-regmap-debugfs.h>
  34. #define T1_TEMP -10
  35. #define T2_TEMP 150
  36. #define LOW_TEMP_THRESHOLD 5
  37. #define HIGH_TEMP_THRESHOLD 45
  38. #define TEMP_INVALID 0xFFFF
  39. #define WSA884X_TEMP_RETRY 3
  40. #define PBR_MAX_VOLTAGE 20
  41. #define PBR_MAX_CODE 255
  42. #define WSA884X_IDLE_DETECT_NG_BLOCK_MASK 0x38
  43. #define MAX_NAME_LEN 40
  44. #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  45. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  46. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  47. SNDRV_PCM_RATE_384000)
  48. /* Fractional Rates */
  49. #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  50. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  51. #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  52. SNDRV_PCM_FMTBIT_S24_LE |\
  53. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  54. #define REG_FIELD_VALUE(register_name, field_name, value) \
  55. WSA884X_##register_name, FIELD_MASK(register_name, field_name), \
  56. value << FIELD_SHIFT(register_name, field_name)
  57. enum {
  58. IDLE_DETECT,
  59. NG1,
  60. NG2,
  61. NG3,
  62. };
  63. struct wsa_temp_register {
  64. u8 d1_msb;
  65. u8 d1_lsb;
  66. u8 d2_msb;
  67. u8 d2_lsb;
  68. u8 dmeas_msb;
  69. u8 dmeas_lsb;
  70. };
  71. enum {
  72. COMP_OFFSET0,
  73. COMP_OFFSET1,
  74. COMP_OFFSET2,
  75. COMP_OFFSET3,
  76. COMP_OFFSET4,
  77. };
  78. #define WSA884X_VTH_TO_REG(vth) \
  79. ((vth) != 0 ? (((vth) - 150 / PBR_MAX_VOLTAGE) * PBR_MAX_CODE / 100) : 0)
  80. struct wsa_reg_mask_val {
  81. u16 reg;
  82. u8 mask;
  83. u8 val;
  84. };
  85. static const struct wsa_reg_mask_val reg_init[] = {
  86. {REG_FIELD_VALUE(CKWD_CTL_1, VPP_SW_CTL, 0x00)},
  87. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
  88. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)},
  89. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)},
  90. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)},
  91. {REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)},
  92. {REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)},
  93. {REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)},
  94. {REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)},
  95. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)},
  96. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)},
  97. {REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)},
  98. {REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)},
  99. {REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)},
  100. {REG_FIELD_VALUE(CDC_SPK_DSM_R2, SAT_LIMIT_R2, 0x7F)},
  101. {REG_FIELD_VALUE(CDC_SPK_DSM_R3, SAT_LIMIT_R3, 0x9D)},
  102. {REG_FIELD_VALUE(CDC_SPK_DSM_R4, SAT_LIMIT_R4, 0x82)},
  103. {REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)},
  104. {REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)},
  105. {REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)},
  106. {REG_FIELD_VALUE(BOP_DEGLITCH_CTL, BOP_DEGLITCH_SETTING, 0x08)},
  107. {REG_FIELD_VALUE(VBAT_THRM_FLT_CTL, VBAT_COEF_SEL, 0x04)},
  108. {REG_FIELD_VALUE(CLSH_CTL_0, DLY_CODE, 0x06)},
  109. {REG_FIELD_VALUE(CLSH_SOFT_MAX, SOFT_MAX, 0xFF)},
  110. {REG_FIELD_VALUE(OTP_REG_38, BOOST_ILIM_TUNE, 0x00)},
  111. {REG_FIELD_VALUE(OTP_REG_40, ISENSE_RESCAL, 0x08)},
  112. {REG_FIELD_VALUE(STB_CTRL1, SLOPE_COMP_CURRENT, 0x0D)},
  113. {REG_FIELD_VALUE(ILIM_CTRL1, ILIM_OFFSET_PB, 0x03)},
  114. {REG_FIELD_VALUE(CURRENT_LIMIT, CURRENT_LIMIT, 0x09)},
  115. {REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
  116. {REG_FIELD_VALUE(BOP2_PROG, BOP2_VTH, 0x06)},
  117. {REG_FIELD_VALUE(BOP2_PROG, BOP2_HYST, 0x06)},
  118. };
  119. static int wsa884x_handle_post_irq(void *data);
  120. static int wsa884x_get_temperature(struct snd_soc_component *component,
  121. int *temp);
  122. enum {
  123. WSA8840 = 0,
  124. WSA8845 = 5,
  125. WSA8845H = 0xC,
  126. };
  127. enum {
  128. SPKR_STATUS = 0,
  129. WSA_SUPPLIES_LPM_MODE,
  130. SPKR_ADIE_LB,
  131. };
  132. enum {
  133. WSA884X_IRQ_INT_SAF2WAR = 0,
  134. WSA884X_IRQ_INT_WAR2SAF,
  135. WSA884X_IRQ_INT_DISABLE,
  136. WSA884X_IRQ_INT_OCP,
  137. WSA884X_IRQ_INT_CLIP,
  138. WSA884X_IRQ_INT_PDM_WD,
  139. WSA884X_IRQ_INT_CLK_WD,
  140. WSA884X_IRQ_INT_INTR_PIN,
  141. WSA884X_IRQ_INT_UVLO,
  142. WSA884X_IRQ_INT_PA_ON_ERR,
  143. WSA884X_NUM_IRQS,
  144. };
  145. static const struct regmap_irq wsa884x_irqs[WSA884X_NUM_IRQS] = {
  146. REGMAP_IRQ_REG(WSA884X_IRQ_INT_SAF2WAR, 0, 0x01),
  147. REGMAP_IRQ_REG(WSA884X_IRQ_INT_WAR2SAF, 0, 0x02),
  148. REGMAP_IRQ_REG(WSA884X_IRQ_INT_DISABLE, 0, 0x04),
  149. REGMAP_IRQ_REG(WSA884X_IRQ_INT_OCP, 0, 0x08),
  150. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLIP, 0, 0x10),
  151. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PDM_WD, 0, 0x20),
  152. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLK_WD, 0, 0x40),
  153. REGMAP_IRQ_REG(WSA884X_IRQ_INT_INTR_PIN, 0, 0x80),
  154. REGMAP_IRQ_REG(WSA884X_IRQ_INT_UVLO, 1, 0x01),
  155. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PA_ON_ERR, 1, 0x02),
  156. };
  157. static struct regmap_irq_chip wsa884x_regmap_irq_chip = {
  158. .name = "wsa884x",
  159. .irqs = wsa884x_irqs,
  160. .num_irqs = ARRAY_SIZE(wsa884x_irqs),
  161. .num_regs = 2,
  162. .status_base = WSA884X_INTR_STATUS0,
  163. .mask_base = WSA884X_INTR_MASK0,
  164. .type_base = WSA884X_INTR_LEVEL0,
  165. .ack_base = WSA884X_INTR_CLEAR0,
  166. .use_ack = 1,
  167. .runtime_pm = false,
  168. .handle_post_irq = wsa884x_handle_post_irq,
  169. .irq_drv_data = NULL,
  170. };
  171. static int wsa884x_handle_post_irq(void *data)
  172. {
  173. struct wsa884x_priv *wsa884x = data;
  174. u32 sts1 = 0, sts2 = 0;
  175. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS0, &sts1);
  176. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS1, &sts2);
  177. wsa884x->swr_slave->slave_irq_pending =
  178. ((sts1 || sts2) ? true : false);
  179. return IRQ_HANDLED;
  180. }
  181. #ifdef CONFIG_DEBUG_FS
  182. static int codec_debug_open(struct inode *inode, struct file *file)
  183. {
  184. file->private_data = inode->i_private;
  185. return 0;
  186. }
  187. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  188. {
  189. char *token;
  190. int base, cnt;
  191. token = strsep(&buf, " ");
  192. for (cnt = 0; cnt < num_of_par; cnt++) {
  193. if (token) {
  194. if ((token[1] == 'x') || (token[1] == 'X'))
  195. base = 16;
  196. else
  197. base = 10;
  198. if (kstrtou32(token, base, &param1[cnt]) != 0)
  199. return -EINVAL;
  200. token = strsep(&buf, " ");
  201. } else {
  202. return -EINVAL;
  203. }
  204. }
  205. return 0;
  206. }
  207. static bool is_swr_slave_reg_readable(int reg)
  208. {
  209. int ret = true;
  210. if (((reg > 0x46) && (reg < 0x4A)) ||
  211. ((reg > 0x4A) && (reg < 0x50)) ||
  212. ((reg > 0x55) && (reg < 0xD0)) ||
  213. ((reg > 0xD0) && (reg < 0xE0)) ||
  214. ((reg > 0xE0) && (reg < 0xF0)) ||
  215. ((reg > 0xF0) && (reg < 0x100)) ||
  216. ((reg > 0x105) && (reg < 0x120)) ||
  217. ((reg > 0x205) && (reg < 0x220)) ||
  218. ((reg > 0x305) && (reg < 0x320)) ||
  219. ((reg > 0x405) && (reg < 0x420)) ||
  220. ((reg > 0x505) && (reg < 0x520)) ||
  221. ((reg > 0x605) && (reg < 0x620)) ||
  222. ((reg > 0x127) && (reg < 0x130)) ||
  223. ((reg > 0x227) && (reg < 0x230)) ||
  224. ((reg > 0x327) && (reg < 0x330)) ||
  225. ((reg > 0x427) && (reg < 0x430)) ||
  226. ((reg > 0x527) && (reg < 0x530)) ||
  227. ((reg > 0x627) && (reg < 0x630)) ||
  228. ((reg > 0x137) && (reg < 0x200)) ||
  229. ((reg > 0x237) && (reg < 0x300)) ||
  230. ((reg > 0x337) && (reg < 0x400)) ||
  231. ((reg > 0x437) && (reg < 0x500)) ||
  232. ((reg > 0x537) && (reg < 0x600)) ||
  233. ((reg > 0x637) && (reg < 0xF00)) ||
  234. ((reg > 0xF05) && (reg < 0xF20)) ||
  235. ((reg > 0xF25) && (reg < 0xF30)) ||
  236. ((reg > 0xF35) && (reg < 0x2000)))
  237. ret = false;
  238. return ret;
  239. }
  240. static ssize_t swr_slave_reg_show(struct swr_device *pdev, char __user *ubuf,
  241. size_t count, loff_t *ppos)
  242. {
  243. int i, reg_val, len;
  244. ssize_t total = 0;
  245. char tmp_buf[SWR_SLV_MAX_BUF_LEN];
  246. if (!ubuf || !ppos)
  247. return 0;
  248. for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
  249. i <= SWR_SLV_MAX_REG_ADDR; i++) {
  250. if (!is_swr_slave_reg_readable(i))
  251. continue;
  252. swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
  253. len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
  254. (reg_val & 0xFF));
  255. if (len < 0) {
  256. pr_err("%s: fail to fill the buffer\n", __func__);
  257. total = -EFAULT;
  258. goto copy_err;
  259. }
  260. if ((total + len) >= count - 1)
  261. break;
  262. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  263. pr_err("%s: fail to copy reg dump\n", __func__);
  264. total = -EFAULT;
  265. goto copy_err;
  266. }
  267. total += len;
  268. *ppos += len;
  269. }
  270. copy_err:
  271. *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
  272. return total;
  273. }
  274. static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
  275. size_t count, loff_t *ppos)
  276. {
  277. struct swr_device *pdev;
  278. if (!count || !file || !ppos || !ubuf)
  279. return -EINVAL;
  280. pdev = file->private_data;
  281. if (!pdev)
  282. return -EINVAL;
  283. if (*ppos < 0)
  284. return -EINVAL;
  285. return swr_slave_reg_show(pdev, ubuf, count, ppos);
  286. }
  287. static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
  288. size_t count, loff_t *ppos)
  289. {
  290. char lbuf[SWR_SLV_RD_BUF_LEN];
  291. struct swr_device *pdev = NULL;
  292. struct wsa884x_priv *wsa884x = NULL;
  293. if (!count || !file || !ppos || !ubuf)
  294. return -EINVAL;
  295. pdev = file->private_data;
  296. if (!pdev)
  297. return -EINVAL;
  298. wsa884x = swr_get_dev_data(pdev);
  299. if (!wsa884x)
  300. return -EINVAL;
  301. if (*ppos < 0)
  302. return -EINVAL;
  303. snprintf(lbuf, sizeof(lbuf), "0x%x\n",
  304. (wsa884x->read_data & 0xFF));
  305. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  306. strnlen(lbuf, 7));
  307. }
  308. static ssize_t codec_debug_peek_write(struct file *file,
  309. const char __user *ubuf, size_t cnt, loff_t *ppos)
  310. {
  311. char lbuf[SWR_SLV_WR_BUF_LEN];
  312. int rc = 0;
  313. u32 param[5];
  314. struct swr_device *pdev = NULL;
  315. struct wsa884x_priv *wsa884x = NULL;
  316. if (!cnt || !file || !ppos || !ubuf)
  317. return -EINVAL;
  318. pdev = file->private_data;
  319. if (!pdev)
  320. return -EINVAL;
  321. wsa884x = swr_get_dev_data(pdev);
  322. if (!wsa884x)
  323. return -EINVAL;
  324. if (*ppos < 0)
  325. return -EINVAL;
  326. if (cnt > sizeof(lbuf) - 1)
  327. return -EINVAL;
  328. rc = copy_from_user(lbuf, ubuf, cnt);
  329. if (rc)
  330. return -EFAULT;
  331. lbuf[cnt] = '\0';
  332. rc = get_parameters(lbuf, param, 1);
  333. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
  334. return -EINVAL;
  335. swr_read(pdev, pdev->dev_num, param[0], &wsa884x->read_data, 1);
  336. if (rc == 0)
  337. rc = cnt;
  338. else
  339. pr_err("%s: rc = %d\n", __func__, rc);
  340. return rc;
  341. }
  342. static ssize_t codec_debug_write(struct file *file,
  343. const char __user *ubuf, size_t cnt, loff_t *ppos)
  344. {
  345. char lbuf[SWR_SLV_WR_BUF_LEN];
  346. int rc = 0;
  347. u32 param[5];
  348. struct swr_device *pdev;
  349. if (!file || !ppos || !ubuf)
  350. return -EINVAL;
  351. pdev = file->private_data;
  352. if (!pdev)
  353. return -EINVAL;
  354. if (cnt > sizeof(lbuf) - 1)
  355. return -EINVAL;
  356. rc = copy_from_user(lbuf, ubuf, cnt);
  357. if (rc)
  358. return -EFAULT;
  359. lbuf[cnt] = '\0';
  360. rc = get_parameters(lbuf, param, 2);
  361. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
  362. (param[1] <= 0xFF) && (rc == 0)))
  363. return -EINVAL;
  364. swr_write(pdev, pdev->dev_num, param[0], &param[1]);
  365. if (rc == 0)
  366. rc = cnt;
  367. else
  368. pr_err("%s: rc = %d\n", __func__, rc);
  369. return rc;
  370. }
  371. static const struct file_operations codec_debug_write_ops = {
  372. .open = codec_debug_open,
  373. .write = codec_debug_write,
  374. };
  375. static const struct file_operations codec_debug_read_ops = {
  376. .open = codec_debug_open,
  377. .read = codec_debug_read,
  378. .write = codec_debug_peek_write,
  379. };
  380. static const struct file_operations codec_debug_dump_ops = {
  381. .open = codec_debug_open,
  382. .read = codec_debug_dump,
  383. };
  384. #endif
  385. static void wsa884x_regcache_sync(struct wsa884x_priv *wsa884x)
  386. {
  387. mutex_lock(&wsa884x->res_lock);
  388. regcache_mark_dirty(wsa884x->regmap);
  389. regcache_sync(wsa884x->regmap);
  390. mutex_unlock(&wsa884x->res_lock);
  391. }
  392. static irqreturn_t wsa884x_saf2war_handle_irq(int irq, void *data)
  393. {
  394. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  395. __func__, irq);
  396. return IRQ_HANDLED;
  397. }
  398. static irqreturn_t wsa884x_war2saf_handle_irq(int irq, void *data)
  399. {
  400. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  401. __func__, irq);
  402. return IRQ_HANDLED;
  403. }
  404. static irqreturn_t wsa884x_otp_handle_irq(int irq, void *data)
  405. {
  406. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  407. __func__, irq);
  408. return IRQ_HANDLED;
  409. }
  410. static irqreturn_t wsa884x_ocp_handle_irq(int irq, void *data)
  411. {
  412. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  413. __func__, irq);
  414. return IRQ_HANDLED;
  415. }
  416. static irqreturn_t wsa884x_clip_handle_irq(int irq, void *data)
  417. {
  418. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  419. __func__, irq);
  420. return IRQ_HANDLED;
  421. }
  422. static irqreturn_t wsa884x_pdm_wd_handle_irq(int irq, void *data)
  423. {
  424. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  425. __func__, irq);
  426. return IRQ_HANDLED;
  427. }
  428. static irqreturn_t wsa884x_clk_wd_handle_irq(int irq, void *data)
  429. {
  430. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  431. __func__, irq);
  432. return IRQ_HANDLED;
  433. }
  434. static irqreturn_t wsa884x_ext_int_handle_irq(int irq, void *data)
  435. {
  436. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  437. __func__, irq);
  438. return IRQ_HANDLED;
  439. }
  440. static irqreturn_t wsa884x_uvlo_handle_irq(int irq, void *data)
  441. {
  442. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  443. __func__, irq);
  444. return IRQ_HANDLED;
  445. }
  446. static irqreturn_t wsa884x_pa_on_err_handle_irq(int irq, void *data)
  447. {
  448. u8 pa_fsm_sta = 0, pa_fsm_err = 0;
  449. struct wsa884x_priv *wsa884x = data;
  450. struct snd_soc_component *component = NULL;
  451. if (!wsa884x)
  452. return IRQ_NONE;
  453. component = wsa884x->component;
  454. if (!component)
  455. return IRQ_NONE;
  456. pa_fsm_sta = (snd_soc_component_read(component, WSA884X_PA_FSM_STA1)
  457. & 0x1F);
  458. if (pa_fsm_sta)
  459. pa_fsm_err = snd_soc_component_read(component,
  460. WSA884X_PA_FSM_ERR_COND0);
  461. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  462. __func__, irq);
  463. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  464. 0x10, 0x00);
  465. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  466. 0x10, 0x10);
  467. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  468. 0x10, 0x00);
  469. return IRQ_HANDLED;
  470. }
  471. static int wsa884x_set_gain_parameters(struct snd_soc_component *component)
  472. {
  473. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  474. u8 igain;
  475. u8 vgain;
  476. switch (wsa884x->bat_cfg) {
  477. case CONFIG_1S:
  478. case EXT_1S:
  479. switch (wsa884x->system_gain) {
  480. case G_21_DB:
  481. wsa884x->comp_offset = COMP_OFFSET0;
  482. wsa884x->min_gain = G_0_DB;
  483. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  484. break;
  485. case G_19P5_DB:
  486. wsa884x->comp_offset = COMP_OFFSET1;
  487. wsa884x->min_gain = G_M1P5_DB;
  488. wsa884x->pa_aux_gain = PA_AUX_M1P5_DB;
  489. break;
  490. case G_18_DB:
  491. wsa884x->comp_offset = COMP_OFFSET2;
  492. wsa884x->min_gain = G_M3_DB;
  493. wsa884x->pa_aux_gain = PA_AUX_M3_DB;
  494. break;
  495. case G_16P5_DB:
  496. wsa884x->comp_offset = COMP_OFFSET3;
  497. wsa884x->min_gain = G_M4P5_DB;
  498. wsa884x->pa_aux_gain = PA_AUX_M4P5_DB;
  499. break;
  500. default:
  501. wsa884x->comp_offset = COMP_OFFSET4;
  502. wsa884x->min_gain = G_M6_DB;
  503. wsa884x->pa_aux_gain = PA_AUX_M6_DB;
  504. break;
  505. }
  506. break;
  507. case CONFIG_3S:
  508. case EXT_3S:
  509. wsa884x->comp_offset = COMP_OFFSET0;
  510. wsa884x->min_gain = G_7P5_DB;
  511. wsa884x->pa_aux_gain = PA_AUX_7P5_DB;
  512. break;
  513. case EXT_ABOVE_3S:
  514. wsa884x->comp_offset = COMP_OFFSET0;
  515. wsa884x->min_gain = G_12_DB;
  516. wsa884x->pa_aux_gain = PA_AUX_12_DB;
  517. break;
  518. default:
  519. wsa884x->comp_offset = COMP_OFFSET0;
  520. wsa884x->min_gain = G_0_DB;
  521. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  522. break;
  523. }
  524. igain = isense_gain_data[wsa884x->system_gain][wsa884x->rload];
  525. vgain = vsense_gain_data[wsa884x->system_gain];
  526. snd_soc_component_update_bits(component,
  527. REG_FIELD_VALUE(ISENSE2, ISENSE_GAIN_CTL, igain));
  528. snd_soc_component_update_bits(component,
  529. REG_FIELD_VALUE(VSENSE1, GAIN_VSENSE_FE, vgain));
  530. snd_soc_component_update_bits(component,
  531. REG_FIELD_VALUE(GAIN_RAMPING_MIN, MIN_GAIN, wsa884x->min_gain));
  532. if (wsa884x->comp_enable) {
  533. snd_soc_component_update_bits(component,
  534. REG_FIELD_VALUE(DRE_CTL_0, OFFSET,
  535. wsa884x->comp_offset));
  536. snd_soc_component_update_bits(component,
  537. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x00));
  538. } else {
  539. wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->system_gain];
  540. snd_soc_component_update_bits(component,
  541. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  542. snd_soc_component_update_bits(component,
  543. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN, wsa884x->pa_gain));
  544. }
  545. return 0;
  546. }
  547. static int wsa884x_set_pbr_parameters(struct snd_soc_component *component)
  548. {
  549. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  550. int vth1_reg_val;
  551. int vth2_reg_val;
  552. int vth3_reg_val;
  553. int vth4_reg_val;
  554. int vth5_reg_val;
  555. int vth6_reg_val;
  556. int vth7_reg_val;
  557. int vth8_reg_val;
  558. int vth9_reg_val;
  559. int vth10_reg_val;
  560. int vth11_reg_val;
  561. int vth12_reg_val;
  562. int vth13_reg_val;
  563. int vth14_reg_val;
  564. int vth15_reg_val;
  565. int vth1_val = pbr_vth1_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  566. int vth2_val = pbr_vth2_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  567. int vth3_val = pbr_vth3_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  568. int vth4_val = pbr_vth4_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  569. int vth5_val = pbr_vth5_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  570. int vth6_val = pbr_vth6_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  571. int vth7_val = pbr_vth7_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  572. int vth8_val = pbr_vth8_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  573. int vth9_val = pbr_vth9_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  574. int vth10_val = pbr_vth10_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  575. int vth11_val = pbr_vth11_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  576. int vth12_val = pbr_vth12_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  577. int vth13_val = pbr_vth13_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  578. int vth14_val = pbr_vth14_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  579. int vth15_val = pbr_vth15_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  580. vth1_reg_val = WSA884X_VTH_TO_REG(vth1_val);
  581. vth2_reg_val = WSA884X_VTH_TO_REG(vth2_val);
  582. vth3_reg_val = WSA884X_VTH_TO_REG(vth3_val);
  583. vth4_reg_val = WSA884X_VTH_TO_REG(vth4_val);
  584. vth5_reg_val = WSA884X_VTH_TO_REG(vth5_val);
  585. vth6_reg_val = WSA884X_VTH_TO_REG(vth6_val);
  586. vth7_reg_val = WSA884X_VTH_TO_REG(vth7_val);
  587. vth8_reg_val = WSA884X_VTH_TO_REG(vth8_val);
  588. vth9_reg_val = WSA884X_VTH_TO_REG(vth9_val);
  589. vth10_reg_val = WSA884X_VTH_TO_REG(vth10_val);
  590. vth11_reg_val = WSA884X_VTH_TO_REG(vth11_val);
  591. vth12_reg_val = WSA884X_VTH_TO_REG(vth12_val);
  592. vth13_reg_val = WSA884X_VTH_TO_REG(vth13_val);
  593. vth14_reg_val = WSA884X_VTH_TO_REG(vth14_val);
  594. vth15_reg_val = WSA884X_VTH_TO_REG(vth15_val);
  595. snd_soc_component_write(component, WSA884X_CLSH_VTH1, vth1_reg_val);
  596. snd_soc_component_write(component, WSA884X_CLSH_VTH2, vth2_reg_val);
  597. snd_soc_component_write(component, WSA884X_CLSH_VTH3, vth3_reg_val);
  598. snd_soc_component_write(component, WSA884X_CLSH_VTH4, vth4_reg_val);
  599. snd_soc_component_write(component, WSA884X_CLSH_VTH5, vth5_reg_val);
  600. snd_soc_component_write(component, WSA884X_CLSH_VTH6, vth6_reg_val);
  601. snd_soc_component_write(component, WSA884X_CLSH_VTH7, vth7_reg_val);
  602. snd_soc_component_write(component, WSA884X_CLSH_VTH8, vth8_reg_val);
  603. snd_soc_component_write(component, WSA884X_CLSH_VTH9, vth9_reg_val);
  604. snd_soc_component_write(component, WSA884X_CLSH_VTH10, vth10_reg_val);
  605. snd_soc_component_write(component, WSA884X_CLSH_VTH11, vth11_reg_val);
  606. snd_soc_component_write(component, WSA884X_CLSH_VTH12, vth12_reg_val);
  607. snd_soc_component_write(component, WSA884X_CLSH_VTH13, vth13_reg_val);
  608. snd_soc_component_write(component, WSA884X_CLSH_VTH14, vth14_reg_val);
  609. snd_soc_component_write(component, WSA884X_CLSH_VTH15, vth15_reg_val);
  610. return 0;
  611. }
  612. static void wsa_noise_gate_write(struct snd_soc_component *component,
  613. int imode)
  614. {
  615. switch (imode) {
  616. case NG1:
  617. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  618. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x30);
  619. break;
  620. case NG2:
  621. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  622. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x28);
  623. break;
  624. case NG3:
  625. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  626. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x18);
  627. break;
  628. default:
  629. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  630. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x8);
  631. break;
  632. }
  633. }
  634. static const char * const wsa_dev_mode_text[] = {
  635. "speaker", "receiver"
  636. };
  637. static const struct soc_enum wsa_dev_mode_enum =
  638. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_dev_mode_text), wsa_dev_mode_text);
  639. static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
  640. struct snd_ctl_elem_value *ucontrol)
  641. {
  642. struct snd_soc_component *component =
  643. snd_soc_kcontrol_component(kcontrol);
  644. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  645. ucontrol->value.integer.value[0] = wsa884x->dev_mode;
  646. dev_dbg(component->dev, "%s: mode = 0x%x\n", __func__,
  647. wsa884x->dev_mode);
  648. return 0;
  649. }
  650. static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
  651. struct snd_ctl_elem_value *ucontrol)
  652. {
  653. struct snd_soc_component *component =
  654. snd_soc_kcontrol_component(kcontrol);
  655. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  656. int dev_mode;
  657. dev_mode = ucontrol->value.integer.value[0];
  658. dev_dbg(component->dev, "%s: Dev Mode current: %d, new: %d = %ld\n",
  659. __func__, wsa884x->dev_mode, dev_mode);
  660. if (dev_mode >= SPEAKER && dev_mode <= RECEIVER) {
  661. wsa884x->dev_mode = dev_mode;
  662. wsa884x->system_gain = wsa884x->sys_gains[
  663. wsa884x->dev_mode + (wsa884x->dev_index - 1) * 2];
  664. } else {
  665. return -EINVAL;
  666. }
  667. return 0;
  668. }
  669. static const char * const wsa_pa_gain_text[] = {
  670. "G_21_DB", "G_19P5_DB" "G_18_DB", "G_16P5_DB", "G_15_DB", "G_13P5_DB",
  671. "G_12_DB", "G_10P5_DB", "G_9_DB", "G_7P5_DB", "G_6_DB", "G_4P5_DB",
  672. "G_3_DB", "G_1P5_DB", "G_0_DB", "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB"
  673. "G_M6_DB", "G_M7P5_DB", "G_M9_DB"
  674. };
  675. static const struct soc_enum wsa_pa_gain_enum =
  676. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_pa_gain_text), wsa_pa_gain_text);
  677. static int wsa_pa_gain_get(struct snd_kcontrol *kcontrol,
  678. struct snd_ctl_elem_value *ucontrol)
  679. {
  680. struct snd_soc_component *component =
  681. snd_soc_kcontrol_component(kcontrol);
  682. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  683. ucontrol->value.integer.value[0] = wsa884x->pa_gain;
  684. dev_dbg(component->dev, "%s: PA gain = 0x%x\n", __func__,
  685. wsa884x->pa_gain);
  686. return 0;
  687. }
  688. static int wsa_pa_gain_put(struct snd_kcontrol *kcontrol,
  689. struct snd_ctl_elem_value *ucontrol)
  690. {
  691. struct snd_soc_component *component =
  692. snd_soc_kcontrol_component(kcontrol);
  693. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  694. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  695. __func__, ucontrol->value.integer.value[0]);
  696. wsa884x->pa_gain = ucontrol->value.integer.value[0];
  697. return 0;
  698. }
  699. static int wsa_get_temp(struct snd_kcontrol *kcontrol,
  700. struct snd_ctl_elem_value *ucontrol)
  701. {
  702. struct snd_soc_component *component =
  703. snd_soc_kcontrol_component(kcontrol);
  704. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  705. int temp = 0;
  706. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  707. temp = wsa884x->curr_temp;
  708. else
  709. wsa884x_get_temperature(component, &temp);
  710. ucontrol->value.integer.value[0] = temp;
  711. return 0;
  712. }
  713. static ssize_t wsa884x_codec_version_read(struct snd_info_entry *entry,
  714. void *file_private_data, struct file *file,
  715. char __user *buf, size_t count, loff_t pos)
  716. {
  717. struct wsa884x_priv *wsa884x;
  718. char buffer[WSA884X_VERSION_ENTRY_SIZE];
  719. int len = 0;
  720. wsa884x = (struct wsa884x_priv *) entry->private_data;
  721. if (!wsa884x) {
  722. pr_err("%s: wsa884x priv is null\n", __func__);
  723. return -EINVAL;
  724. }
  725. switch (wsa884x->version) {
  726. case WSA884X_VERSION_1_0:
  727. len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n");
  728. break;
  729. default:
  730. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  731. break;
  732. }
  733. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  734. }
  735. static struct snd_info_entry_ops wsa884x_codec_info_ops = {
  736. .read = wsa884x_codec_version_read,
  737. };
  738. static ssize_t wsa884x_variant_read(struct snd_info_entry *entry,
  739. void *file_private_data,
  740. struct file *file,
  741. char __user *buf, size_t count,
  742. loff_t pos)
  743. {
  744. struct wsa884x_priv *wsa884x;
  745. char buffer[WSA884X_VARIANT_ENTRY_SIZE];
  746. int len = 0;
  747. wsa884x = (struct wsa884x_priv *) entry->private_data;
  748. if (!wsa884x) {
  749. pr_err("%s: wsa884x priv is null\n", __func__);
  750. return -EINVAL;
  751. }
  752. switch (wsa884x->variant) {
  753. case WSA8840:
  754. len = snprintf(buffer, sizeof(buffer), "WSA8840\n");
  755. break;
  756. case WSA8845:
  757. len = snprintf(buffer, sizeof(buffer), "WSA8845\n");
  758. break;
  759. case WSA8845H:
  760. len = snprintf(buffer, sizeof(buffer), "WSA8845H\n");
  761. break;
  762. default:
  763. len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n");
  764. break;
  765. }
  766. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  767. }
  768. static struct snd_info_entry_ops wsa884x_variant_ops = {
  769. .read = wsa884x_variant_read,
  770. };
  771. /*
  772. * wsa884x_codec_info_create_codec_entry - creates wsa884x module
  773. * @codec_root: The parent directory
  774. * @component: Codec instance
  775. *
  776. * Creates wsa884x module and version entry under the given
  777. * parent directory.
  778. *
  779. * Return: 0 on success or negative error code on failure.
  780. */
  781. int wsa884x_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
  782. struct snd_soc_component *component)
  783. {
  784. struct snd_info_entry *version_entry;
  785. struct snd_info_entry *variant_entry;
  786. struct wsa884x_priv *wsa884x;
  787. struct snd_soc_card *card;
  788. char name[80];
  789. if (!codec_root || !component)
  790. return -EINVAL;
  791. wsa884x = snd_soc_component_get_drvdata(component);
  792. if (wsa884x->entry) {
  793. dev_dbg(wsa884x->dev,
  794. "%s:wsa884x module already created\n", __func__);
  795. return 0;
  796. }
  797. card = component->card;
  798. snprintf(name, sizeof(name), "%s.%llx", "wsa884x",
  799. wsa884x->swr_slave->addr);
  800. wsa884x->entry = snd_info_create_module_entry(codec_root->module,
  801. (const char *)name,
  802. codec_root);
  803. if (!wsa884x->entry) {
  804. dev_dbg(component->dev, "%s: failed to create wsa884x entry\n",
  805. __func__);
  806. return -ENOMEM;
  807. }
  808. wsa884x->entry->mode = S_IFDIR | 0555;
  809. if (snd_info_register(wsa884x->entry) < 0) {
  810. snd_info_free_entry(wsa884x->entry);
  811. return -ENOMEM;
  812. }
  813. version_entry = snd_info_create_card_entry(card->snd_card,
  814. "version",
  815. wsa884x->entry);
  816. if (!version_entry) {
  817. dev_dbg(component->dev, "%s: failed to create wsa884x version entry\n",
  818. __func__);
  819. snd_info_free_entry(wsa884x->entry);
  820. return -ENOMEM;
  821. }
  822. version_entry->private_data = wsa884x;
  823. version_entry->size = WSA884X_VERSION_ENTRY_SIZE;
  824. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  825. version_entry->c.ops = &wsa884x_codec_info_ops;
  826. if (snd_info_register(version_entry) < 0) {
  827. snd_info_free_entry(version_entry);
  828. snd_info_free_entry(wsa884x->entry);
  829. return -ENOMEM;
  830. }
  831. wsa884x->version_entry = version_entry;
  832. variant_entry = snd_info_create_card_entry(card->snd_card,
  833. "variant",
  834. wsa884x->entry);
  835. if (!variant_entry) {
  836. dev_dbg(component->dev,
  837. "%s: failed to create wsa884x variant entry\n",
  838. __func__);
  839. snd_info_free_entry(version_entry);
  840. snd_info_free_entry(wsa884x->entry);
  841. return -ENOMEM;
  842. }
  843. variant_entry->private_data = wsa884x;
  844. variant_entry->size = WSA884X_VARIANT_ENTRY_SIZE;
  845. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  846. variant_entry->c.ops = &wsa884x_variant_ops;
  847. if (snd_info_register(variant_entry) < 0) {
  848. snd_info_free_entry(variant_entry);
  849. snd_info_free_entry(version_entry);
  850. snd_info_free_entry(wsa884x->entry);
  851. return -ENOMEM;
  852. }
  853. wsa884x->variant_entry = variant_entry;
  854. return 0;
  855. }
  856. EXPORT_SYMBOL(wsa884x_codec_info_create_codec_entry);
  857. /*
  858. * wsa884x_codec_get_dev_num - returns swr device number
  859. * @component: Codec instance
  860. *
  861. * Return: swr device number on success or negative error
  862. * code on failure.
  863. */
  864. int wsa884x_codec_get_dev_num(struct snd_soc_component *component)
  865. {
  866. struct wsa884x_priv *wsa884x;
  867. if (!component)
  868. return -EINVAL;
  869. wsa884x = snd_soc_component_get_drvdata(component);
  870. if (!wsa884x) {
  871. pr_err("%s: wsa884x component is NULL\n", __func__);
  872. return -EINVAL;
  873. }
  874. return wsa884x->swr_slave->dev_num;
  875. }
  876. EXPORT_SYMBOL(wsa884x_codec_get_dev_num);
  877. static int wsa884x_get_dev_num(struct snd_kcontrol *kcontrol,
  878. struct snd_ctl_elem_value *ucontrol)
  879. {
  880. struct snd_soc_component *component =
  881. snd_soc_kcontrol_component(kcontrol);
  882. struct wsa884x_priv *wsa884x;
  883. if (!component)
  884. return -EINVAL;
  885. wsa884x = snd_soc_component_get_drvdata(component);
  886. if (!wsa884x) {
  887. pr_err("%s: wsa884x component is NULL\n", __func__);
  888. return -EINVAL;
  889. }
  890. ucontrol->value.integer.value[0] = wsa884x->swr_slave->dev_num;
  891. return 0;
  892. }
  893. static int wsa884x_get_compander(struct snd_kcontrol *kcontrol,
  894. struct snd_ctl_elem_value *ucontrol)
  895. {
  896. struct snd_soc_component *component =
  897. snd_soc_kcontrol_component(kcontrol);
  898. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  899. ucontrol->value.integer.value[0] = wsa884x->comp_enable;
  900. return 0;
  901. }
  902. /*
  903. * wsa884x_validate_dt_configuration_params - returns 1 or 0
  904. * Return: 0 Valid configuration, 1 Invalid configuration
  905. */
  906. static bool wsa884x_validate_dt_configuration_params(u8 irload, u8 ibat_cfg,
  907. u8 isystem_gain)
  908. {
  909. bool is_invalid_flag = true;
  910. if ((WSA_4_OHMS <= irload && irload < WSA_MAX_OHMS) &&
  911. (G_21_DB <= isystem_gain && isystem_gain < G_MAX_DB) &&
  912. (EXT_ABOVE_3S <= ibat_cfg && ibat_cfg < CONFIG_MAX))
  913. is_invalid_flag = false;
  914. return is_invalid_flag;
  915. }
  916. static int wsa884x_set_compander(struct snd_kcontrol *kcontrol,
  917. struct snd_ctl_elem_value *ucontrol)
  918. {
  919. struct snd_soc_component *component =
  920. snd_soc_kcontrol_component(kcontrol);
  921. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  922. int value = ucontrol->value.integer.value[0];
  923. dev_dbg(component->dev, "%s: Compander enable current %d, new %d\n",
  924. __func__, wsa884x->comp_enable, value);
  925. wsa884x->comp_enable = value;
  926. return 0;
  927. }
  928. static int wsa884x_get_visense(struct snd_kcontrol *kcontrol,
  929. struct snd_ctl_elem_value *ucontrol)
  930. {
  931. struct snd_soc_component *component =
  932. snd_soc_kcontrol_component(kcontrol);
  933. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  934. ucontrol->value.integer.value[0] = wsa884x->visense_enable;
  935. return 0;
  936. }
  937. static int wsa884x_set_visense(struct snd_kcontrol *kcontrol,
  938. struct snd_ctl_elem_value *ucontrol)
  939. {
  940. struct snd_soc_component *component =
  941. snd_soc_kcontrol_component(kcontrol);
  942. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  943. int value = ucontrol->value.integer.value[0];
  944. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  945. __func__, wsa884x->visense_enable, value);
  946. wsa884x->visense_enable = value;
  947. return 0;
  948. }
  949. static int wsa884x_get_pbr(struct snd_kcontrol *kcontrol,
  950. struct snd_ctl_elem_value *ucontrol)
  951. {
  952. struct snd_soc_component *component =
  953. snd_soc_kcontrol_component(kcontrol);
  954. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  955. ucontrol->value.integer.value[0] = wsa884x->pbr_enable;
  956. return 0;
  957. }
  958. static int wsa884x_set_pbr(struct snd_kcontrol *kcontrol,
  959. struct snd_ctl_elem_value *ucontrol)
  960. {
  961. struct snd_soc_component *component =
  962. snd_soc_kcontrol_component(kcontrol);
  963. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  964. int value = ucontrol->value.integer.value[0];
  965. dev_dbg(component->dev, "%s: PBR enable current %d, new %d\n",
  966. __func__, wsa884x->pbr_enable, value);
  967. wsa884x->pbr_enable = value;
  968. return 0;
  969. }
  970. static int wsa884x_get_cps(struct snd_kcontrol *kcontrol,
  971. struct snd_ctl_elem_value *ucontrol)
  972. {
  973. struct snd_soc_component *component =
  974. snd_soc_kcontrol_component(kcontrol);
  975. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  976. ucontrol->value.integer.value[0] = wsa884x->cps_enable;
  977. return 0;
  978. }
  979. static int wsa884x_set_cps(struct snd_kcontrol *kcontrol,
  980. struct snd_ctl_elem_value *ucontrol)
  981. {
  982. struct snd_soc_component *component =
  983. snd_soc_kcontrol_component(kcontrol);
  984. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  985. int value = ucontrol->value.integer.value[0];
  986. dev_dbg(component->dev, "%s: CPS enable current %d, new %d\n",
  987. __func__, wsa884x->cps_enable, value);
  988. wsa884x->cps_enable = value;
  989. return 0;
  990. }
  991. static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
  992. SOC_ENUM_EXT("WSA PA Gain", wsa_pa_gain_enum,
  993. wsa_pa_gain_get, wsa_pa_gain_put),
  994. SOC_SINGLE_EXT("WSA Temp", SND_SOC_NOPM, 0, UINT_MAX, 0,
  995. wsa_get_temp, NULL),
  996. SOC_SINGLE_EXT("WSA Get DevNum", SND_SOC_NOPM, 0, UINT_MAX, 0,
  997. wsa884x_get_dev_num, NULL),
  998. SOC_ENUM_EXT("WSA MODE", wsa_dev_mode_enum,
  999. wsa_dev_mode_get, wsa_dev_mode_put),
  1000. SOC_SINGLE_EXT("COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1001. wsa884x_get_compander, wsa884x_set_compander),
  1002. SOC_SINGLE_EXT("VISENSE Switch", SND_SOC_NOPM, 0, 1, 0,
  1003. wsa884x_get_visense, wsa884x_set_visense),
  1004. SOC_SINGLE_EXT("PBR Switch", SND_SOC_NOPM, 0, 1, 0,
  1005. wsa884x_get_pbr, wsa884x_set_pbr),
  1006. SOC_SINGLE_EXT("CPS Switch", SND_SOC_NOPM, 0, 1, 0,
  1007. wsa884x_get_cps, wsa884x_set_cps),
  1008. };
  1009. static const struct snd_kcontrol_new swr_dac_port[] = {
  1010. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1011. };
  1012. static int wsa884x_set_port(struct snd_soc_component *component, int port_idx,
  1013. u8 *port_id, u8 *num_ch, u8 *ch_mask, u32 *ch_rate,
  1014. u8 *port_type)
  1015. {
  1016. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1017. *port_id = wsa884x->port[port_idx].port_id;
  1018. *num_ch = wsa884x->port[port_idx].num_ch;
  1019. *ch_mask = wsa884x->port[port_idx].ch_mask;
  1020. *ch_rate = wsa884x->port[port_idx].ch_rate;
  1021. *port_type = wsa884x->port[port_idx].port_type;
  1022. return 0;
  1023. }
  1024. static int wsa884x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
  1025. struct snd_kcontrol *kcontrol, int event)
  1026. {
  1027. struct snd_soc_component *component =
  1028. snd_soc_dapm_to_component(w->dapm);
  1029. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1030. u8 port_id[WSA884X_MAX_SWR_PORTS];
  1031. u8 num_ch[WSA884X_MAX_SWR_PORTS];
  1032. u8 ch_mask[WSA884X_MAX_SWR_PORTS];
  1033. u32 ch_rate[WSA884X_MAX_SWR_PORTS];
  1034. u8 port_type[WSA884X_MAX_SWR_PORTS];
  1035. u8 num_port = 0;
  1036. dev_dbg(component->dev, "%s: event %d name %s\n", __func__,
  1037. event, w->name);
  1038. if (wsa884x == NULL)
  1039. return -EINVAL;
  1040. switch (event) {
  1041. case SND_SOC_DAPM_PRE_PMU:
  1042. wsa884x_set_port(component, SWR_DAC_PORT,
  1043. &port_id[num_port], &num_ch[num_port],
  1044. &ch_mask[num_port], &ch_rate[num_port],
  1045. &port_type[num_port]);
  1046. if (wsa884x->dev_mode == RECEIVER)
  1047. ch_rate[num_port] = SWR_CLK_RATE_4P8MHZ;
  1048. ++num_port;
  1049. if (wsa884x->comp_enable) {
  1050. wsa884x_set_port(component, SWR_COMP_PORT,
  1051. &port_id[num_port], &num_ch[num_port],
  1052. &ch_mask[num_port], &ch_rate[num_port],
  1053. &port_type[num_port]);
  1054. ++num_port;
  1055. }
  1056. if (wsa884x->pbr_enable) {
  1057. wsa884x_set_port(component, SWR_PBR_PORT,
  1058. &port_id[num_port], &num_ch[num_port],
  1059. &ch_mask[num_port], &ch_rate[num_port],
  1060. &port_type[num_port]);
  1061. ++num_port;
  1062. }
  1063. if (wsa884x->visense_enable) {
  1064. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1065. &port_id[num_port], &num_ch[num_port],
  1066. &ch_mask[num_port], &ch_rate[num_port],
  1067. &port_type[num_port]);
  1068. ++num_port;
  1069. }
  1070. if (wsa884x->cps_enable) {
  1071. wsa884x_set_port(component, SWR_CPS_PORT,
  1072. &port_id[num_port], &num_ch[num_port],
  1073. &ch_mask[num_port], &ch_rate[num_port],
  1074. &port_type[num_port]);
  1075. ++num_port;
  1076. }
  1077. swr_connect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1078. &ch_mask[0], &ch_rate[0], &num_ch[0],
  1079. &port_type[0]);
  1080. break;
  1081. case SND_SOC_DAPM_POST_PMU:
  1082. set_bit(SPKR_STATUS, &wsa884x->status_mask);
  1083. break;
  1084. case SND_SOC_DAPM_PRE_PMD:
  1085. wsa884x_set_port(component, SWR_DAC_PORT,
  1086. &port_id[num_port], &num_ch[num_port],
  1087. &ch_mask[num_port], &ch_rate[num_port],
  1088. &port_type[num_port]);
  1089. ++num_port;
  1090. if (wsa884x->comp_enable) {
  1091. wsa884x_set_port(component, SWR_COMP_PORT,
  1092. &port_id[num_port], &num_ch[num_port],
  1093. &ch_mask[num_port], &ch_rate[num_port],
  1094. &port_type[num_port]);
  1095. ++num_port;
  1096. }
  1097. if (wsa884x->pbr_enable) {
  1098. wsa884x_set_port(component, SWR_PBR_PORT,
  1099. &port_id[num_port], &num_ch[num_port],
  1100. &ch_mask[num_port], &ch_rate[num_port],
  1101. &port_type[num_port]);
  1102. ++num_port;
  1103. }
  1104. if (wsa884x->visense_enable) {
  1105. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1106. &port_id[num_port], &num_ch[num_port],
  1107. &ch_mask[num_port], &ch_rate[num_port],
  1108. &port_type[num_port]);
  1109. ++num_port;
  1110. }
  1111. if (wsa884x->cps_enable) {
  1112. wsa884x_set_port(component, SWR_CPS_PORT,
  1113. &port_id[num_port], &num_ch[num_port],
  1114. &ch_mask[num_port], &ch_rate[num_port],
  1115. &port_type[num_port]);
  1116. ++num_port;
  1117. }
  1118. swr_disconnect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1119. &ch_mask[0], &port_type[0]);
  1120. break;
  1121. case SND_SOC_DAPM_POST_PMD:
  1122. if (swr_set_device_group(wsa884x->swr_slave, SWR_GROUP_NONE))
  1123. dev_err(component->dev,
  1124. "%s: set num ch failed\n", __func__);
  1125. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1126. wsa884x->swr_slave->dev_num,
  1127. false);
  1128. break;
  1129. default:
  1130. break;
  1131. }
  1132. return 0;
  1133. }
  1134. static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
  1135. struct snd_kcontrol *kcontrol, int event)
  1136. {
  1137. struct snd_soc_component *component =
  1138. snd_soc_dapm_to_component(w->dapm);
  1139. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1140. dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
  1141. switch (event) {
  1142. case SND_SOC_DAPM_POST_PMU:
  1143. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1144. wsa884x->swr_slave->dev_num,
  1145. true);
  1146. wsa884x_set_gain_parameters(component);
  1147. if (wsa884x->dev_mode == SPEAKER) {
  1148. snd_soc_component_update_bits(component,
  1149. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1150. } else {
  1151. snd_soc_component_update_bits(component,
  1152. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1153. snd_soc_component_update_bits(component,
  1154. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1155. snd_soc_component_update_bits(component,
  1156. REG_FIELD_VALUE(PWM_CLK_CTL,
  1157. PWM_CLK_FREQ_SEL, 0x01));
  1158. }
  1159. if (wsa884x->pbr_enable) {
  1160. snd_soc_component_update_bits(component,
  1161. REG_FIELD_VALUE(CURRENT_LIMIT,
  1162. CURRENT_LIMIT_OVRD_EN, 0x00));
  1163. switch (wsa884x->bat_cfg) {
  1164. case CONFIG_1S:
  1165. snd_soc_component_update_bits(component,
  1166. REG_FIELD_VALUE(CURRENT_LIMIT,
  1167. CURRENT_LIMIT, 0x15));
  1168. break;
  1169. case CONFIG_2S:
  1170. snd_soc_component_update_bits(component,
  1171. REG_FIELD_VALUE(CURRENT_LIMIT,
  1172. CURRENT_LIMIT, 0x11));
  1173. break;
  1174. case CONFIG_3S:
  1175. snd_soc_component_update_bits(component,
  1176. REG_FIELD_VALUE(CURRENT_LIMIT,
  1177. CURRENT_LIMIT, 0x0D));
  1178. break;
  1179. }
  1180. } else {
  1181. snd_soc_component_update_bits(component,
  1182. REG_FIELD_VALUE(CURRENT_LIMIT,
  1183. CURRENT_LIMIT_OVRD_EN, 0x01));
  1184. if (wsa884x->system_gain >= G_12_DB)
  1185. snd_soc_component_update_bits(component,
  1186. REG_FIELD_VALUE(CURRENT_LIMIT,
  1187. CURRENT_LIMIT, 0x15));
  1188. else
  1189. snd_soc_component_update_bits(component,
  1190. REG_FIELD_VALUE(CURRENT_LIMIT,
  1191. CURRENT_LIMIT, 0x09));
  1192. }
  1193. /* Force remove group */
  1194. swr_remove_from_group(wsa884x->swr_slave,
  1195. wsa884x->swr_slave->dev_num);
  1196. if (test_bit(SPKR_ADIE_LB, &wsa884x->status_mask))
  1197. snd_soc_component_update_bits(component,
  1198. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1199. break;
  1200. case SND_SOC_DAPM_PRE_PMD:
  1201. snd_soc_component_update_bits(component,
  1202. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1203. snd_soc_component_update_bits(component,
  1204. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  1205. clear_bit(SPKR_STATUS, &wsa884x->status_mask);
  1206. clear_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1207. break;
  1208. }
  1209. return 0;
  1210. }
  1211. static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
  1212. SND_SOC_DAPM_INPUT("IN"),
  1213. SND_SOC_DAPM_MIXER_E("SWR DAC_Port", SND_SOC_NOPM, 0, 0, swr_dac_port,
  1214. ARRAY_SIZE(swr_dac_port), wsa884x_enable_swr_dac_port,
  1215. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1216. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1217. SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
  1218. };
  1219. static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
  1220. {"SWR DAC_Port", "Switch", "IN"},
  1221. {"SPKR", NULL, "SWR DAC_Port"},
  1222. };
  1223. int wsa884x_set_channel_map(struct snd_soc_component *component, u8 *port,
  1224. u8 num_port, unsigned int *ch_mask,
  1225. unsigned int *ch_rate, u8 *port_type)
  1226. {
  1227. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1228. int i;
  1229. if (!port || !ch_mask || !ch_rate ||
  1230. (num_port > WSA884X_MAX_SWR_PORTS)) {
  1231. dev_err(component->dev,
  1232. "%s: Invalid port=%pK, ch_mask=%pK, ch_rate=%pK\n",
  1233. __func__, port, ch_mask, ch_rate);
  1234. return -EINVAL;
  1235. }
  1236. for (i = 0; i < num_port; i++) {
  1237. wsa884x->port[i].port_id = port[i];
  1238. wsa884x->port[i].ch_mask = ch_mask[i];
  1239. wsa884x->port[i].ch_rate = ch_rate[i];
  1240. wsa884x->port[i].num_ch = __sw_hweight8(ch_mask[i]);
  1241. if (port_type)
  1242. wsa884x->port[i].port_type = port_type[i];
  1243. }
  1244. return 0;
  1245. }
  1246. EXPORT_SYMBOL(wsa884x_set_channel_map);
  1247. static void wsa884x_codec_init(struct snd_soc_component *component)
  1248. {
  1249. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1250. int i;
  1251. if (!wsa884x)
  1252. return;
  1253. for (i = 0; i < ARRAY_SIZE(reg_init); i++)
  1254. snd_soc_component_update_bits(component, reg_init[i].reg,
  1255. reg_init[i].mask, reg_init[i].val);
  1256. if (wsa884x->variant == WSA8845H)
  1257. snd_soc_component_update_bits(wsa884x->component,
  1258. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  1259. wsa_noise_gate_write(component, wsa884x->noise_gate_mode);
  1260. }
  1261. static int32_t wsa884x_temp_reg_read(struct snd_soc_component *component,
  1262. struct wsa_temp_register *wsa_temp_reg)
  1263. {
  1264. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1265. if (!wsa884x) {
  1266. dev_err(component->dev, "%s: wsa884x is NULL\n", __func__);
  1267. return -EINVAL;
  1268. }
  1269. mutex_lock(&wsa884x->res_lock);
  1270. snd_soc_component_update_bits(component,
  1271. REG_FIELD_VALUE(PA_FSM_BYP0, DC_CAL_EN, 0x01));
  1272. snd_soc_component_update_bits(component,
  1273. REG_FIELD_VALUE(PA_FSM_BYP0, BG_EN, 0x01));
  1274. snd_soc_component_update_bits(component,
  1275. REG_FIELD_VALUE(PA_FSM_BYP0, CLK_WD_EN, 0x01));
  1276. snd_soc_component_update_bits(component,
  1277. REG_FIELD_VALUE(PA_FSM_BYP0, TSADC_EN, 0x01));
  1278. snd_soc_component_update_bits(component,
  1279. REG_FIELD_VALUE(PA_FSM_BYP0, D_UNMUTE, 0x01));
  1280. snd_soc_component_update_bits(component,
  1281. REG_FIELD_VALUE(PA_FSM_BYP0, SPKR_PROT_EN, 0x01));
  1282. snd_soc_component_update_bits(component,
  1283. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x00));
  1284. wsa_temp_reg->dmeas_msb = snd_soc_component_read(component,
  1285. WSA884X_TEMP_DIN_MSB);
  1286. wsa_temp_reg->dmeas_lsb = snd_soc_component_read(component,
  1287. WSA884X_TEMP_DIN_LSB);
  1288. snd_soc_component_update_bits(component,
  1289. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x01));
  1290. wsa_temp_reg->d1_msb = snd_soc_component_read(component,
  1291. WSA884X_OTP_REG_1);
  1292. wsa_temp_reg->d1_lsb = snd_soc_component_read(component,
  1293. WSA884X_OTP_REG_2);
  1294. wsa_temp_reg->d2_msb = snd_soc_component_read(component,
  1295. WSA884X_OTP_REG_3);
  1296. wsa_temp_reg->d2_lsb = snd_soc_component_read(component,
  1297. WSA884X_OTP_REG_4);
  1298. snd_soc_component_update_bits(component,
  1299. WSA884X_PA_FSM_BYP0, 0xE7, 0x00);
  1300. mutex_unlock(&wsa884x->res_lock);
  1301. return 0;
  1302. }
  1303. static int wsa884x_get_temperature(struct snd_soc_component *component,
  1304. int *temp)
  1305. {
  1306. struct wsa_temp_register reg;
  1307. int dmeas, d1, d2;
  1308. int ret = 0;
  1309. int temp_val = 0;
  1310. int t1 = T1_TEMP;
  1311. int t2 = T2_TEMP;
  1312. u8 retry = WSA884X_TEMP_RETRY;
  1313. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1314. if (!wsa884x)
  1315. return -EINVAL;
  1316. do {
  1317. ret = wsa884x_temp_reg_read(component, &reg);
  1318. if (ret) {
  1319. pr_err("%s: temp read failed: %d, current temp: %d\n",
  1320. __func__, ret, wsa884x->curr_temp);
  1321. if (temp)
  1322. *temp = wsa884x->curr_temp;
  1323. return 0;
  1324. }
  1325. /*
  1326. * Temperature register values are expected to be in the
  1327. * following range.
  1328. * d1_msb = 68 - 92 and d1_lsb = 0, 64, 128, 192
  1329. * d2_msb = 185 -218 and d2_lsb = 0, 64, 128, 192
  1330. */
  1331. if ((reg.d1_msb < 68 || reg.d1_msb > 92) ||
  1332. (!(reg.d1_lsb == 0 || reg.d1_lsb == 64 || reg.d1_lsb == 128 ||
  1333. reg.d1_lsb == 192)) ||
  1334. (reg.d2_msb < 185 || reg.d2_msb > 218) ||
  1335. (!(reg.d2_lsb == 0 || reg.d2_lsb == 64 || reg.d2_lsb == 128 ||
  1336. reg.d2_lsb == 192))) {
  1337. printk_ratelimited("%s: Temperature registers[%d %d %d %d] are out of range\n",
  1338. __func__, reg.d1_msb, reg.d1_lsb, reg.d2_msb,
  1339. reg.d2_lsb);
  1340. }
  1341. dmeas = ((reg.dmeas_msb << 0x8) | reg.dmeas_lsb) >> 0x6;
  1342. d1 = ((reg.d1_msb << 0x8) | reg.d1_lsb) >> 0x6;
  1343. d2 = ((reg.d2_msb << 0x8) | reg.d2_lsb) >> 0x6;
  1344. if (d1 == d2)
  1345. temp_val = TEMP_INVALID;
  1346. else
  1347. temp_val = t1 + (((dmeas - d1) * (t2 - t1))/(d2 - d1));
  1348. if (temp_val <= LOW_TEMP_THRESHOLD ||
  1349. temp_val >= HIGH_TEMP_THRESHOLD) {
  1350. pr_debug("%s: T0: %d is out of range[%d, %d]\n", __func__,
  1351. temp_val, LOW_TEMP_THRESHOLD, HIGH_TEMP_THRESHOLD);
  1352. if (retry--)
  1353. msleep(10);
  1354. } else {
  1355. break;
  1356. }
  1357. } while (retry);
  1358. wsa884x->curr_temp = temp_val;
  1359. if (temp)
  1360. *temp = temp_val;
  1361. pr_debug("%s: t0 measured: %d dmeas = %d, d1 = %d, d2 = %d\n",
  1362. __func__, temp_val, dmeas, d1, d2);
  1363. return ret;
  1364. }
  1365. static int wsa884x_codec_probe(struct snd_soc_component *component)
  1366. {
  1367. char w_name[MAX_NAME_LEN];
  1368. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1369. struct swr_device *dev;
  1370. int variant = 0, version = 0;
  1371. struct snd_soc_dapm_context *dapm =
  1372. snd_soc_component_get_dapm(component);
  1373. if (!wsa884x)
  1374. return -EINVAL;
  1375. if (!component->name_prefix)
  1376. return -EINVAL;
  1377. snd_soc_component_init_regmap(component, wsa884x->regmap);
  1378. dev = wsa884x->swr_slave;
  1379. wsa884x->component = component;
  1380. variant = (snd_soc_component_read(component, WSA884X_OTP_REG_0)
  1381. & FIELD_MASK(OTP_REG_0, WSA884X_ID));
  1382. wsa884x->variant = variant;
  1383. version = (snd_soc_component_read(component, WSA884X_CHIP_ID0)
  1384. & FIELD_MASK(CHIP_ID0, BYTE_0));
  1385. wsa884x->version = version;
  1386. wsa884x->comp_offset = COMP_OFFSET2;
  1387. wsa884x_codec_init(component);
  1388. wsa884x->global_pa_cnt = 0;
  1389. memset(w_name, 0, sizeof(w_name));
  1390. strlcpy(w_name, wsa884x->dai_driver->playback.stream_name,
  1391. sizeof(w_name));
  1392. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1393. memset(w_name, 0, sizeof(w_name));
  1394. strlcpy(w_name, "IN", sizeof(w_name));
  1395. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1396. memset(w_name, 0, sizeof(w_name));
  1397. strlcpy(w_name, "SWR DAC_Port", sizeof(w_name));
  1398. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1399. memset(w_name, 0, sizeof(w_name));
  1400. strlcpy(w_name, "SPKR", sizeof(w_name));
  1401. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1402. snd_soc_dapm_sync(dapm);
  1403. return 0;
  1404. }
  1405. static void wsa884x_codec_remove(struct snd_soc_component *component)
  1406. {
  1407. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1408. if (!wsa884x)
  1409. return;
  1410. snd_soc_component_exit_regmap(component);
  1411. return;
  1412. }
  1413. static int wsa884x_soc_codec_suspend(struct snd_soc_component *component)
  1414. {
  1415. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1416. if (!wsa884x)
  1417. return 0;
  1418. wsa884x->dapm_bias_off = true;
  1419. return 0;
  1420. }
  1421. static int wsa884x_soc_codec_resume(struct snd_soc_component *component)
  1422. {
  1423. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1424. if (!wsa884x)
  1425. return 0;
  1426. wsa884x->dapm_bias_off = false;
  1427. return 0;
  1428. }
  1429. static const struct snd_soc_component_driver soc_codec_dev_wsa884x_wsa = {
  1430. .name = "",
  1431. .probe = wsa884x_codec_probe,
  1432. .remove = wsa884x_codec_remove,
  1433. .controls = wsa884x_snd_controls,
  1434. .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
  1435. .dapm_widgets = wsa884x_dapm_widgets,
  1436. .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
  1437. .dapm_routes = wsa884x_audio_map,
  1438. .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
  1439. .suspend = wsa884x_soc_codec_suspend,
  1440. .resume = wsa884x_soc_codec_resume,
  1441. };
  1442. static int wsa884x_gpio_ctrl(struct wsa884x_priv *wsa884x, bool enable)
  1443. {
  1444. int ret = 0;
  1445. if (enable)
  1446. ret = msm_cdc_pinctrl_select_active_state(
  1447. wsa884x->wsa_rst_np);
  1448. else
  1449. ret = msm_cdc_pinctrl_select_sleep_state(
  1450. wsa884x->wsa_rst_np);
  1451. if (ret != 0)
  1452. dev_err(wsa884x->dev,
  1453. "%s: Failed to turn state %d; ret=%d\n",
  1454. __func__, enable, ret);
  1455. return ret;
  1456. }
  1457. static int wsa884x_swr_up(struct wsa884x_priv *wsa884x)
  1458. {
  1459. int ret;
  1460. ret = wsa884x_gpio_ctrl(wsa884x, true);
  1461. if (ret)
  1462. dev_err(wsa884x->dev, "%s: Failed to enable gpio\n", __func__);
  1463. return ret;
  1464. }
  1465. static int wsa884x_swr_down(struct wsa884x_priv *wsa884x)
  1466. {
  1467. int ret;
  1468. ret = wsa884x_gpio_ctrl(wsa884x, false);
  1469. if (ret)
  1470. dev_err(wsa884x->dev, "%s: Failed to disable gpio\n", __func__);
  1471. return ret;
  1472. }
  1473. static int wsa884x_swr_reset(struct wsa884x_priv *wsa884x)
  1474. {
  1475. u8 retry = WSA884X_NUM_RETRY;
  1476. u8 devnum = 0;
  1477. struct swr_device *pdev;
  1478. pdev = wsa884x->swr_slave;
  1479. while (swr_get_logical_dev_num(pdev, pdev->addr, &devnum) && retry--) {
  1480. /* Retry after 1 msec delay */
  1481. usleep_range(1000, 1100);
  1482. }
  1483. pdev->dev_num = devnum;
  1484. wsa884x_regcache_sync(wsa884x);
  1485. return 0;
  1486. }
  1487. static int wsa884x_event_notify(struct notifier_block *nb,
  1488. unsigned long val, void *ptr)
  1489. {
  1490. u16 event = (val & 0xffff);
  1491. struct wsa884x_priv *wsa884x = container_of(nb, struct wsa884x_priv,
  1492. parent_nblock);
  1493. if (!wsa884x)
  1494. return -EINVAL;
  1495. switch (event) {
  1496. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1497. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1498. snd_soc_component_update_bits(wsa884x->component,
  1499. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1500. wsa884x_swr_down(wsa884x);
  1501. break;
  1502. case BOLERO_SLV_EVT_SSR_UP:
  1503. wsa884x_swr_up(wsa884x);
  1504. /* Add delay to allow enumerate */
  1505. usleep_range(20000, 20010);
  1506. wsa884x_swr_reset(wsa884x);
  1507. break;
  1508. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK:
  1509. if (test_bit(SPKR_STATUS, &wsa884x->status_mask)) {
  1510. snd_soc_component_update_bits(wsa884x->component,
  1511. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  1512. snd_soc_component_update_bits(wsa884x->component,
  1513. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1514. }
  1515. break;
  1516. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB:
  1517. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1518. set_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1519. break;
  1520. default:
  1521. dev_dbg(wsa884x->dev, "%s: unknown event %d\n",
  1522. __func__, event);
  1523. break;
  1524. }
  1525. return 0;
  1526. }
  1527. static int wsa884x_parse_port_params(struct device *dev, char *prop)
  1528. {
  1529. u32 *dt_array, map_size, max_uc;
  1530. int ret = 0;
  1531. u32 cnt = 0;
  1532. u32 i, j;
  1533. struct swr_port_params (*map)[SWR_UC_MAX][WSA884X_MAX_SWR_PORTS];
  1534. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  1535. struct wsa884x_priv *wsa884x = dev_get_drvdata(dev);
  1536. map = &wsa884x->wsa_port_params;
  1537. map_uc = &wsa884x->swr_wsa_port_params;
  1538. if (!of_find_property(dev->of_node, prop,
  1539. &map_size)) {
  1540. dev_err(dev, "missing port mapping prop %s\n", prop);
  1541. ret = -EINVAL;
  1542. goto err_port_map;
  1543. }
  1544. max_uc = map_size / (WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  1545. if (max_uc != SWR_UC_MAX) {
  1546. dev_err(dev, "%s: port params not provided for all usecases\n",
  1547. __func__);
  1548. ret = -EINVAL;
  1549. goto err_port_map;
  1550. }
  1551. dt_array = kzalloc(map_size, GFP_KERNEL);
  1552. if (!dt_array) {
  1553. ret = -ENOMEM;
  1554. goto err_port_map;
  1555. }
  1556. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  1557. WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * max_uc);
  1558. if (ret) {
  1559. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  1560. __func__, prop);
  1561. goto err_pdata_fail;
  1562. }
  1563. for (i = 0; i < max_uc; i++) {
  1564. for (j = 0; j < WSA884X_MAX_SWR_PORTS; j++) {
  1565. cnt = (i * WSA884X_MAX_SWR_PORTS + j) * SWR_PORT_PARAMS;
  1566. (*map)[i][j].offset1 = dt_array[cnt];
  1567. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  1568. }
  1569. (*map_uc)[i].pp = &(*map)[i][0];
  1570. }
  1571. kfree(dt_array);
  1572. return 0;
  1573. err_pdata_fail:
  1574. kfree(dt_array);
  1575. err_port_map:
  1576. return ret;
  1577. }
  1578. static int wsa884x_enable_supplies(struct device *dev,
  1579. struct wsa884x_priv *priv)
  1580. {
  1581. int ret = 0;
  1582. /* Parse power supplies */
  1583. msm_cdc_get_power_supplies(dev, &priv->regulator,
  1584. &priv->num_supplies);
  1585. if (!priv->regulator || (priv->num_supplies <= 0)) {
  1586. dev_err(dev, "%s: no power supplies defined\n", __func__);
  1587. return -EINVAL;
  1588. }
  1589. ret = msm_cdc_init_supplies(dev, &priv->supplies,
  1590. priv->regulator, priv->num_supplies);
  1591. if (!priv->supplies) {
  1592. dev_err(dev, "%s: Cannot init wsa supplies\n",
  1593. __func__);
  1594. return ret;
  1595. }
  1596. ret = msm_cdc_enable_static_supplies(dev, priv->supplies,
  1597. priv->regulator,
  1598. priv->num_supplies);
  1599. if (ret)
  1600. dev_err(dev, "%s: wsa static supply enable failed!\n",
  1601. __func__);
  1602. return ret;
  1603. }
  1604. static struct snd_soc_dai_driver wsa_dai[] = {
  1605. {
  1606. .name = "",
  1607. .playback = {
  1608. .stream_name = "",
  1609. .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
  1610. .formats = WSA884X_FORMATS,
  1611. .rate_max = 192000,
  1612. .rate_min = 8000,
  1613. .channels_min = 1,
  1614. .channels_max = 2,
  1615. },
  1616. },
  1617. };
  1618. static int wsa884x_swr_probe(struct swr_device *pdev)
  1619. {
  1620. int ret = 0;
  1621. struct wsa884x_priv *wsa884x;
  1622. u8 devnum = 0;
  1623. bool pin_state_current = false;
  1624. struct wsa_ctrl_platform_data *plat_data = NULL;
  1625. struct snd_soc_component *component;
  1626. u32 noise_gate_mode;
  1627. char buffer[MAX_NAME_LEN];
  1628. int dev_index = 0;
  1629. struct regmap_irq_chip *wsa884x_sub_regmap_irq_chip = NULL;
  1630. u8 wo0_val;
  1631. int sys_gain_size, sys_gain_length;
  1632. wsa884x = devm_kzalloc(&pdev->dev, sizeof(struct wsa884x_priv),
  1633. GFP_KERNEL);
  1634. if (!wsa884x)
  1635. return -ENOMEM;
  1636. wsa884x_sub_regmap_irq_chip = devm_kzalloc(&pdev->dev, sizeof(struct regmap_irq_chip),
  1637. GFP_KERNEL);
  1638. if (!wsa884x_sub_regmap_irq_chip)
  1639. return -ENOMEM;
  1640. memcpy(wsa884x_sub_regmap_irq_chip, &wsa884x_regmap_irq_chip,
  1641. sizeof(struct regmap_irq_chip));
  1642. ret = wsa884x_enable_supplies(&pdev->dev, wsa884x);
  1643. if (ret) {
  1644. ret = -EPROBE_DEFER;
  1645. goto err;
  1646. }
  1647. wsa884x->wsa_rst_np = of_parse_phandle(pdev->dev.of_node,
  1648. "qcom,spkr-sd-n-node", 0);
  1649. if (!wsa884x->wsa_rst_np) {
  1650. dev_dbg(&pdev->dev, "%s: pinctrl not defined\n", __func__);
  1651. goto err_supply;
  1652. }
  1653. swr_set_dev_data(pdev, wsa884x);
  1654. wsa884x->swr_slave = pdev;
  1655. wsa884x->dev = &pdev->dev;
  1656. pin_state_current = msm_cdc_pinctrl_get_state(wsa884x->wsa_rst_np);
  1657. wsa884x_gpio_ctrl(wsa884x, true);
  1658. /*
  1659. * Add 5msec delay to provide sufficient time for
  1660. * soundwire auto enumeration of slave devices as
  1661. * per HW requirement.
  1662. */
  1663. usleep_range(5000, 5010);
  1664. ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
  1665. if (ret) {
  1666. dev_dbg(&pdev->dev,
  1667. "%s get devnum %d for dev addr %lx failed\n",
  1668. __func__, devnum, pdev->addr);
  1669. ret = -EPROBE_DEFER;
  1670. goto err_supply;
  1671. }
  1672. pdev->dev_num = devnum;
  1673. wsa884x->regmap = devm_regmap_init_swr(pdev,
  1674. &wsa884x_regmap_config);
  1675. if (IS_ERR(wsa884x->regmap)) {
  1676. ret = PTR_ERR(wsa884x->regmap);
  1677. dev_err(&pdev->dev, "%s: regmap_init failed %d\n",
  1678. __func__, ret);
  1679. goto dev_err;
  1680. }
  1681. devm_regmap_qti_debugfs_register(&pdev->dev, wsa884x->regmap);
  1682. wsa884x_sub_regmap_irq_chip->irq_drv_data = wsa884x;
  1683. wsa884x->irq_info.wcd_regmap_irq_chip = wsa884x_sub_regmap_irq_chip;
  1684. wsa884x->irq_info.codec_name = "WSA884X";
  1685. wsa884x->irq_info.regmap = wsa884x->regmap;
  1686. wsa884x->irq_info.dev = &pdev->dev;
  1687. ret = wcd_irq_init(&wsa884x->irq_info, &wsa884x->virq);
  1688. if (ret) {
  1689. dev_err(wsa884x->dev, "%s: IRQ init failed: %d\n",
  1690. __func__, ret);
  1691. goto dev_err;
  1692. }
  1693. wsa884x->swr_slave->slave_irq = wsa884x->virq;
  1694. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR,
  1695. "WSA SAF2WAR", wsa884x_saf2war_handle_irq, wsa884x);
  1696. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF,
  1697. "WSA WAR2SAF", wsa884x_war2saf_handle_irq, wsa884x);
  1698. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE,
  1699. "WSA OTP", wsa884x_otp_handle_irq, wsa884x);
  1700. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP,
  1701. "WSA OCP", wsa884x_ocp_handle_irq, wsa884x);
  1702. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP,
  1703. "WSA CLIP", wsa884x_clip_handle_irq, wsa884x);
  1704. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP);
  1705. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD,
  1706. "WSA PDM WD", wsa884x_pdm_wd_handle_irq, wsa884x);
  1707. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD,
  1708. "WSA CLK WD", wsa884x_clk_wd_handle_irq, wsa884x);
  1709. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN,
  1710. "WSA EXT INT", wsa884x_ext_int_handle_irq, wsa884x);
  1711. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN);
  1712. /* Under Voltage Lock out (UVLO) interrupt handle */
  1713. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO,
  1714. "WSA UVLO", wsa884x_uvlo_handle_irq, wsa884x);
  1715. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR,
  1716. "WSA PA ERR", wsa884x_pa_on_err_handle_irq, wsa884x);
  1717. wsa884x->driver = devm_kzalloc(&pdev->dev,
  1718. sizeof(struct snd_soc_component_driver), GFP_KERNEL);
  1719. if (!wsa884x->driver) {
  1720. ret = -ENOMEM;
  1721. goto err_irq;
  1722. }
  1723. memcpy(wsa884x->driver, &soc_codec_dev_wsa884x_wsa,
  1724. sizeof(struct snd_soc_component_driver));
  1725. wsa884x->dai_driver = devm_kzalloc(&pdev->dev,
  1726. sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
  1727. if (!wsa884x->dai_driver) {
  1728. ret = -ENOMEM;
  1729. goto err_mem;
  1730. }
  1731. memcpy(wsa884x->dai_driver, wsa_dai, sizeof(struct snd_soc_dai_driver));
  1732. /* Get last digit from HEX format */
  1733. dev_index = (int)((char)(pdev->addr & 0xF));
  1734. dev_index += 1;
  1735. if (of_device_is_compatible(pdev->dev.of_node, "qcom,wsa884x_2"))
  1736. dev_index += 2;
  1737. snprintf(buffer, sizeof(buffer), "wsa-codec.%d", dev_index);
  1738. wsa884x->driver->name = kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1739. snprintf(buffer, sizeof(buffer), "wsa_rx%d", dev_index);
  1740. wsa884x->dai_driver->name =
  1741. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1742. snprintf(buffer, sizeof(buffer), "WSA884X_AIF%d Playback", dev_index);
  1743. wsa884x->dai_driver->playback.stream_name =
  1744. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1745. /* Number of DAI's used is 1 */
  1746. ret = snd_soc_register_component(&pdev->dev,
  1747. wsa884x->driver, wsa884x->dai_driver, 1);
  1748. component = snd_soc_lookup_component(&pdev->dev, wsa884x->driver->name);
  1749. if (!component) {
  1750. dev_err(&pdev->dev, "%s: component is NULL\n", __func__);
  1751. ret = -EINVAL;
  1752. goto err_mem;
  1753. }
  1754. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1755. "qcom,bolero-handle", 0);
  1756. if (!wsa884x->parent_np)
  1757. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1758. "qcom,lpass-cdc-handle", 0);
  1759. if (wsa884x->parent_np) {
  1760. wsa884x->parent_dev =
  1761. of_find_device_by_node(wsa884x->parent_np);
  1762. if (wsa884x->parent_dev) {
  1763. plat_data = dev_get_platdata(&wsa884x->parent_dev->dev);
  1764. if (plat_data) {
  1765. wsa884x->parent_nblock.notifier_call =
  1766. wsa884x_event_notify;
  1767. if (plat_data->register_notifier)
  1768. plat_data->register_notifier(
  1769. plat_data->handle,
  1770. &wsa884x->parent_nblock,
  1771. true);
  1772. wsa884x->register_notifier =
  1773. plat_data->register_notifier;
  1774. wsa884x->handle = plat_data->handle;
  1775. } else {
  1776. dev_err(&pdev->dev, "%s: plat data not found\n",
  1777. __func__);
  1778. }
  1779. } else {
  1780. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1781. __func__);
  1782. }
  1783. } else {
  1784. dev_info(&pdev->dev, "%s: parent node not found\n", __func__);
  1785. }
  1786. /* Start in speaker mode by default */
  1787. wsa884x->dev_mode = SPEAKER;
  1788. wsa884x->dev_index = dev_index;
  1789. wsa884x->macro_np = of_parse_phandle(pdev->dev.of_node,
  1790. "qcom,wsa-macro-handle", 0);
  1791. if (wsa884x->macro_np) {
  1792. wsa884x->macro_dev =
  1793. of_find_device_by_node(wsa884x->macro_np);
  1794. if (wsa884x->macro_dev) {
  1795. ret = of_property_read_u32_index(
  1796. wsa884x->macro_dev->dev.of_node,
  1797. "qcom,wsa-rloads",
  1798. dev_index - 1,
  1799. &wsa884x->rload);
  1800. if (ret) {
  1801. dev_err(&pdev->dev,
  1802. "%s: Failed to read wsa rloads\n",
  1803. __func__);
  1804. goto err_mem;
  1805. }
  1806. ret = of_property_read_u32(wsa884x->macro_dev->dev.of_node,
  1807. "qcom,noise-gate-mode", &noise_gate_mode);
  1808. if (ret) {
  1809. dev_info(&pdev->dev,
  1810. "%s: Failed to read wsa noise gate mode\n",
  1811. __func__);
  1812. wsa884x->noise_gate_mode = IDLE_DETECT;
  1813. } else {
  1814. if(IDLE_DETECT <= noise_gate_mode && noise_gate_mode <= NG3)
  1815. wsa884x->noise_gate_mode = noise_gate_mode;
  1816. else
  1817. wsa884x->noise_gate_mode = IDLE_DETECT;
  1818. }
  1819. if (!of_find_property(wsa884x->macro_dev->dev.of_node,
  1820. "qcom,wsa-system-gains", &sys_gain_size)) {
  1821. dev_err(&pdev->dev,
  1822. "%s: missing wsa-system-gains\n",
  1823. __func__);
  1824. goto err_mem;
  1825. }
  1826. sys_gain_length = sys_gain_size / (2 * sizeof(u32));
  1827. ret = of_property_read_u32_array(
  1828. wsa884x->macro_dev->dev.of_node,
  1829. "qcom,wsa-system-gains", wsa884x->sys_gains,
  1830. sys_gain_length);
  1831. if (ret) {
  1832. dev_err(&pdev->dev,
  1833. "%s: Failed to read wsa system gains\n",
  1834. __func__);
  1835. goto err_mem;
  1836. }
  1837. wsa884x->system_gain = wsa884x->sys_gains[
  1838. wsa884x->dev_mode + (dev_index - 1) * 2];
  1839. } else {
  1840. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1841. __func__);
  1842. goto err_mem;
  1843. }
  1844. } else {
  1845. dev_err(&pdev->dev, "%s: parent node not found\n", __func__);
  1846. goto err_mem;
  1847. }
  1848. wsa884x->bat_cfg = snd_soc_component_read(component,
  1849. WSA884X_VPHX_SYS_EN_STATUS);
  1850. dev_dbg(component->dev,
  1851. "%s: Bat_cfg: 0x%x, Rload: 0x%x, Sys_gain: 0x%x\n", __func__,
  1852. wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1853. ret = wsa884x_validate_dt_configuration_params(wsa884x->rload,
  1854. wsa884x->bat_cfg, wsa884x->system_gain);
  1855. if (ret) {
  1856. dev_err(&pdev->dev, "%s: invalid dt parameter\n", __func__);
  1857. ret = -EINVAL;
  1858. goto err_mem;
  1859. }
  1860. wsa884x_set_gain_parameters(component);
  1861. wsa884x_set_pbr_parameters(component);
  1862. /* Must write WO registers in a single write */
  1863. wo0_val = (0xC | (wsa884x->pa_aux_gain << 0x02) | !wsa884x->dev_mode);
  1864. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_0, wo0_val);
  1865. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_1, 0x0);
  1866. if (wsa884x->rload == WSA_4_OHMS || wsa884x->rload == WSA_6_OHMS)
  1867. snd_soc_component_update_bits(component,
  1868. REG_FIELD_VALUE(OCP_CTL, OCP_CURR_LIMIT, 0x07));
  1869. if (wsa884x->dev_mode == SPEAKER) {
  1870. snd_soc_component_update_bits(component,
  1871. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1872. } else {
  1873. snd_soc_component_update_bits(component,
  1874. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1875. snd_soc_component_update_bits(component,
  1876. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1877. snd_soc_component_update_bits(component,
  1878. REG_FIELD_VALUE(PWM_CLK_CTL,
  1879. PWM_CLK_FREQ_SEL, 0x01));
  1880. }
  1881. if (wsa884x->bat_cfg != CONFIG_1S && wsa884x->bat_cfg != EXT_1S)
  1882. snd_soc_component_update_bits(component,
  1883. REG_FIELD_VALUE(TOP_CTRL1,
  1884. OCP_LOWVBAT_ITH_SEL_EN, 0x00));
  1885. ret = wsa884x_parse_port_params(&pdev->dev, "qcom,swr-wsa-port-params");
  1886. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1887. wsa884x->swr_wsa_port_params);
  1888. if (ret) {
  1889. dev_err(&pdev->dev, "Failed to read port params\n");
  1890. goto err;
  1891. }
  1892. mutex_init(&wsa884x->res_lock);
  1893. #ifdef CONFIG_DEBUG_FS
  1894. if (!wsa884x->debugfs_dent) {
  1895. wsa884x->debugfs_dent = debugfs_create_dir(
  1896. dev_name(&pdev->dev), 0);
  1897. if (!IS_ERR(wsa884x->debugfs_dent)) {
  1898. wsa884x->debugfs_peek =
  1899. debugfs_create_file("swrslave_peek",
  1900. S_IFREG | 0444,
  1901. wsa884x->debugfs_dent,
  1902. (void *) pdev,
  1903. &codec_debug_read_ops);
  1904. wsa884x->debugfs_poke =
  1905. debugfs_create_file("swrslave_poke",
  1906. S_IFREG | 0444,
  1907. wsa884x->debugfs_dent,
  1908. (void *) pdev,
  1909. &codec_debug_write_ops);
  1910. wsa884x->debugfs_reg_dump =
  1911. debugfs_create_file(
  1912. "swrslave_reg_dump",
  1913. S_IFREG | 0444,
  1914. wsa884x->debugfs_dent,
  1915. (void *) pdev,
  1916. &codec_debug_dump_ops);
  1917. }
  1918. }
  1919. #endif
  1920. return 0;
  1921. err_mem:
  1922. if (wsa884x->dai_driver) {
  1923. kfree(wsa884x->dai_driver->name);
  1924. kfree(wsa884x->dai_driver->playback.stream_name);
  1925. kfree(wsa884x->dai_driver);
  1926. }
  1927. if (wsa884x->driver) {
  1928. kfree(wsa884x->driver->name);
  1929. kfree(wsa884x->driver);
  1930. }
  1931. err_irq:
  1932. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  1933. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  1934. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  1935. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  1936. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  1937. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  1938. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  1939. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  1940. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  1941. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  1942. wcd_irq_exit(&wsa884x->irq_info, wsa884x->virq);
  1943. dev_err:
  1944. if (pin_state_current == false)
  1945. wsa884x_gpio_ctrl(wsa884x, false);
  1946. swr_remove_device(pdev);
  1947. err_supply:
  1948. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  1949. wsa884x->regulator,
  1950. wsa884x->num_supplies);
  1951. err:
  1952. swr_set_dev_data(pdev, NULL);
  1953. return ret;
  1954. }
  1955. static int wsa884x_swr_remove(struct swr_device *pdev)
  1956. {
  1957. struct wsa884x_priv *wsa884x;
  1958. wsa884x = swr_get_dev_data(pdev);
  1959. if (!wsa884x) {
  1960. dev_err(&pdev->dev, "%s: wsa884x is NULL\n", __func__);
  1961. return -EINVAL;
  1962. }
  1963. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  1964. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  1965. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  1966. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  1967. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  1968. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  1969. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  1970. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  1971. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  1972. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  1973. if (wsa884x->register_notifier)
  1974. wsa884x->register_notifier(wsa884x->handle,
  1975. &wsa884x->parent_nblock, false);
  1976. #ifdef CONFIG_DEBUG_FS
  1977. debugfs_remove_recursive(wsa884x->debugfs_dent);
  1978. wsa884x->debugfs_dent = NULL;
  1979. #endif
  1980. mutex_destroy(&wsa884x->res_lock);
  1981. snd_soc_unregister_component(&pdev->dev);
  1982. if (wsa884x->dai_driver) {
  1983. kfree(wsa884x->dai_driver->name);
  1984. kfree(wsa884x->dai_driver->playback.stream_name);
  1985. kfree(wsa884x->dai_driver);
  1986. }
  1987. if (wsa884x->driver) {
  1988. kfree(wsa884x->driver->name);
  1989. kfree(wsa884x->driver);
  1990. }
  1991. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  1992. wsa884x->regulator,
  1993. wsa884x->num_supplies);
  1994. swr_set_dev_data(pdev, NULL);
  1995. return 0;
  1996. }
  1997. #ifdef CONFIG_PM_SLEEP
  1998. static int wsa884x_swr_suspend(struct device *dev)
  1999. {
  2000. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2001. if (!wsa884x) {
  2002. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  2003. return -EINVAL;
  2004. }
  2005. dev_dbg(dev, "%s: system suspend\n", __func__);
  2006. if (wsa884x->dapm_bias_off) {
  2007. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2008. wsa884x->regulator,
  2009. wsa884x->num_supplies,
  2010. true);
  2011. set_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2012. }
  2013. return 0;
  2014. }
  2015. static int wsa884x_swr_resume(struct device *dev)
  2016. {
  2017. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2018. if (!wsa884x) {
  2019. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  2020. return -EINVAL;
  2021. }
  2022. if (test_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask)) {
  2023. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2024. wsa884x->regulator,
  2025. wsa884x->num_supplies,
  2026. false);
  2027. clear_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2028. }
  2029. dev_dbg(dev, "%s: system resume\n", __func__);
  2030. return 0;
  2031. }
  2032. #endif /* CONFIG_PM_SLEEP */
  2033. static const struct dev_pm_ops wsa884x_swr_pm_ops = {
  2034. .suspend_late = wsa884x_swr_suspend,
  2035. .resume_early = wsa884x_swr_resume,
  2036. };
  2037. static const struct swr_device_id wsa884x_swr_id[] = {
  2038. {"wsa884x", 0},
  2039. {"wsa884x_2", 0},
  2040. {}
  2041. };
  2042. static const struct of_device_id wsa884x_swr_dt_match[] = {
  2043. {
  2044. .compatible = "qcom,wsa884x",
  2045. },
  2046. {
  2047. .compatible = "qcom,wsa884x_2",
  2048. },
  2049. {}
  2050. };
  2051. static struct swr_driver wsa884x_swr_driver = {
  2052. .driver = {
  2053. .name = "wsa884x",
  2054. .owner = THIS_MODULE,
  2055. .pm = &wsa884x_swr_pm_ops,
  2056. .of_match_table = wsa884x_swr_dt_match,
  2057. },
  2058. .probe = wsa884x_swr_probe,
  2059. .remove = wsa884x_swr_remove,
  2060. .id_table = wsa884x_swr_id,
  2061. };
  2062. static int __init wsa884x_swr_init(void)
  2063. {
  2064. return swr_driver_register(&wsa884x_swr_driver);
  2065. }
  2066. static void __exit wsa884x_swr_exit(void)
  2067. {
  2068. swr_driver_unregister(&wsa884x_swr_driver);
  2069. }
  2070. module_init(wsa884x_swr_init);
  2071. module_exit(wsa884x_swr_exit);
  2072. MODULE_DESCRIPTION("WSA884x codec driver");
  2073. MODULE_LICENSE("GPL v2");