43bbb87652
Update file header to GPL-2.0-only. Change-Id: Ic1542a3209a5fe73c937a5b36491ede4a451936d Signed-off-by: Meng Wang <mengw@codeaurora.org>
163 行
4.0 KiB
C
163 行
4.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _AQT1000_INTERNAL_H
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#define _AQT1000_INTERNAL_H
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#include <linux/types.h>
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#include <linux/regmap.h>
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#include <sound/soc.h>
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#define AQT1000_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
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SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
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SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
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SNDRV_PCM_RATE_384000)
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/* Fractional Rates */
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#define AQT1000_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
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SNDRV_PCM_RATE_176400)
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#define AQT1000_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S24_LE)
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#define AQT1000_FORMATS_S16_S24_S32_LE (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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#define AQT1000_FORMATS_S16_LE (SNDRV_PCM_FMTBIT_S16_LE)
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/* Macros for packing register writes into a U32 */
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#define AQT1000_PACKED_REG_SIZE sizeof(u32)
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#define AQT1000_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \
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do { \
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((reg) = ((packed >> 16) & (0xffff))); \
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((mask) = ((packed >> 8) & (0xff))); \
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((val) = ((packed) & (0xff))); \
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} while (0)
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#define STRING(name) #name
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#define AQT_DAPM_ENUM(name, reg, offset, text) \
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static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
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static const struct snd_kcontrol_new name##_mux = \
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SOC_DAPM_ENUM(STRING(name), name##_enum)
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#define AQT_DAPM_ENUM_EXT(name, reg, offset, text, getname, putname) \
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static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
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static const struct snd_kcontrol_new name##_mux = \
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SOC_DAPM_ENUM_EXT(STRING(name), name##_enum, getname, putname)
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#define AQT_DAPM_MUX(name, shift, kctl) \
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SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, shift, 0, &kctl##_mux)
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#define AQT1000_INTERP_MUX_NUM_INPUTS 3
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#define AQT1000_RX_PATH_CTL_OFFSET 20
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#define BYTE_BIT_MASK(nr) (1 << ((nr) % BITS_PER_BYTE))
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#define AQT1000_REG_BITS 8
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#define AQT1000_MAX_VALID_ADC_MUX 3
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#define AQT1000_AMIC_PWR_LEVEL_LP 0
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#define AQT1000_AMIC_PWR_LEVEL_DEFAULT 1
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#define AQT1000_AMIC_PWR_LEVEL_HP 2
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#define AQT1000_AMIC_PWR_LVL_MASK 0x60
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#define AQT1000_AMIC_PWR_LVL_SHIFT 0x5
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#define AQT1000_DEC_PWR_LVL_MASK 0x06
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#define AQT1000_DEC_PWR_LVL_DF 0x00
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#define AQT1000_DEC_PWR_LVL_LP 0x02
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#define AQT1000_DEC_PWR_LVL_HP 0x04
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#define AQT1000_STRING_LEN 100
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#define AQT1000_CDC_SIDETONE_IIR_COEFF_MAX 5
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#define AQT1000_MAX_MICBIAS 1
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#define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
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#define TX_HPF_CUT_OFF_FREQ_MASK 0x60
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#define CF_MIN_3DB_4HZ 0x0
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#define CF_MIN_3DB_75HZ 0x1
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#define CF_MIN_3DB_150HZ 0x2
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enum {
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AUDIO_NOMINAL,
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HPH_PA_DELAY,
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CLSH_Z_CONFIG,
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ANC_MIC_AMIC1,
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ANC_MIC_AMIC2,
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ANC_MIC_AMIC3,
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};
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enum {
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INTn_1_INP_SEL_ZERO = 0,
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INTn_1_INP_SEL_DEC0,
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INTn_1_INP_SEL_DEC1,
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INTn_1_INP_SEL_IIR0,
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INTn_1_INP_SEL_IIR1,
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INTn_1_INP_SEL_RX0,
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INTn_1_INP_SEL_RX1,
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};
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enum {
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INTn_2_INP_SEL_ZERO = 0,
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INTn_2_INP_SEL_RX0,
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INTn_2_INP_SEL_RX1,
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INTn_2_INP_SEL_PROXIMITY,
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};
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/* Codec supports 2 IIR filters */
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enum {
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IIR0 = 0,
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IIR1,
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IIR_MAX,
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};
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enum {
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ASRC_IN_HPHL,
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ASRC_IN_HPHR,
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ASRC_INVALID,
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};
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enum {
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CONV_88P2K_TO_384K,
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CONV_96K_TO_352P8K,
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CONV_352P8K_TO_384K,
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CONV_384K_TO_352P8K,
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CONV_384K_TO_384K,
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CONV_96K_TO_384K,
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};
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enum aqt_notify_event {
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AQT_EVENT_INVALID,
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/* events for micbias ON and OFF */
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AQT_EVENT_PRE_MICBIAS_1_OFF,
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AQT_EVENT_POST_MICBIAS_1_OFF,
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AQT_EVENT_PRE_MICBIAS_1_ON,
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AQT_EVENT_POST_MICBIAS_1_ON,
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AQT_EVENT_PRE_DAPM_MICBIAS_1_OFF,
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AQT_EVENT_POST_DAPM_MICBIAS_1_OFF,
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AQT_EVENT_PRE_DAPM_MICBIAS_1_ON,
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AQT_EVENT_POST_DAPM_MICBIAS_1_ON,
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/* events for PA ON and OFF */
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AQT_EVENT_PRE_HPHL_PA_ON,
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AQT_EVENT_POST_HPHL_PA_OFF,
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AQT_EVENT_PRE_HPHR_PA_ON,
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AQT_EVENT_POST_HPHR_PA_OFF,
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AQT_EVENT_PRE_HPHL_PA_OFF,
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AQT_EVENT_PRE_HPHR_PA_OFF,
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AQT_EVENT_OCP_OFF,
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AQT_EVENT_OCP_ON,
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AQT_EVENT_LAST,
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};
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struct interp_sample_rate {
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int sample_rate;
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int rate_val;
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};
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extern struct regmap_config aqt1000_regmap_config;
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extern int aqt_register_codec(struct device *dev);
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#endif /* _AQT1000_INTERNAL_H */
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