bfe03e92a3
Currently, we are assigning 9 MSI Vector to DP. But in some target available MSI Vector are less because of which they are unable to assign 9 MSI Vector to DP. So, to fix the issue reduces MSI requirement for DP from 9 to 7 and mux DP interrupts. Change-Id: I48da2d0e8921db3298903a398f981e5b45a60987 CRs-Fixed: 3111170
83 linhas
2.4 KiB
C
83 linhas
2.4 KiB
C
/*
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* Copyright (c) 2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __WLAN_INIT_CFG_H
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#define __WLAN_INIT_CFG_H
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/*
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* Temporary place holders. These should come either from target config
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* or platform configuration
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*/
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#if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
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#define WLAN_CFG_DST_RING_CACHED_DESC 0
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#define MAX_PDEV_CNT 1
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#ifdef CONFIG_BERYLLIUM
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/* (8 REOs + 5 WBMs + 2 Near Full + 1 Error handling) */
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#define WLAN_CFG_INT_NUM_CONTEXTS 18
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#define WLAN_CFG_INT_NUM_CONTEXTS_MAX 18
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#else
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#define WLAN_CFG_INT_NUM_CONTEXTS 7
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#define WLAN_CFG_INT_NUM_CONTEXTS_MAX 14
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#endif
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#define WLAN_CFG_RXDMA1_ENABLE 1
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/*
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* This mask defines how many transmit frames account for 1 NAPI work unit
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* 0 means each tx completion is 1 unit
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*/
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#define DP_TX_NAPI_BUDGET_DIV_MASK 0
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/* PPDU Stats Configuration - Configure bitmask for enabling tx ppdu tlv's */
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#define DP_PPDU_TXLITE_STATS_BITMASK_CFG 0x3FFF
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#define NUM_RXDMA_RINGS_PER_PDEV 2
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#define DP_NUM_MACS_PER_PDEV 2
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/*Maximum Number of LMAC instances*/
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#define MAX_NUM_LMAC_HW 2
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#else
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#ifdef DP_NO_CACHE_DESC_SUPPORT
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#define WLAN_CFG_DST_RING_CACHED_DESC 0
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#else
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#define WLAN_CFG_DST_RING_CACHED_DESC 1
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#endif
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#define MAX_PDEV_CNT 3
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#define WLAN_CFG_INT_NUM_CONTEXTS 11
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#define WLAN_CFG_INT_NUM_CONTEXTS_MAX 11
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#define NUM_RXDMA_RINGS_PER_PDEV 1
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#define MAX_NUM_LMAC_HW 3
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#define DP_NUM_MACS_PER_PDEV 1
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#endif
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/* Tx configuration */
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#define MAX_LINK_DESC_BANKS 8
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#define MAX_TXDESC_POOLS 4
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/* Rx configuration */
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#define MAX_RXDESC_POOLS 4
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#define MAX_REO_DEST_RINGS 8
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#define MAX_TCL_DATA_RINGS 5
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#define MAX_RX_MAC_RINGS 2
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#endif /* __WLAN_INIT_CFG_H */
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