hal_api_mon.h 37 KB

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  1. /*
  2. * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_API_MON_H_
  19. #define _HAL_API_MON_H_
  20. #include "qdf_types.h"
  21. #include "hal_internal.h"
  22. #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET
  23. #define HAL_RX_LSB(block, field) block##_##field##_LSB
  24. #define HAL_RX_MASk(block, field) block##_##field##_MASK
  25. #define HAL_RX_GET(_ptr, block, field) \
  26. (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \
  27. HAL_RX_MASk(block, field)) >> \
  28. HAL_RX_LSB(block, field))
  29. #define HAL_RX_PHY_DATA_RADAR 0x01
  30. #define HAL_SU_MU_CODING_LDPC 0x01
  31. #define HAL_RX_FCS_LEN (4)
  32. #define KEY_EXTIV 0x20
  33. #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000
  34. #define HAL_RX_USER_TLV32_TYPE_LSB 1
  35. #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE
  36. #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000
  37. #define HAL_RX_USER_TLV32_LEN_LSB 10
  38. #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00
  39. #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000
  40. #define HAL_RX_USER_TLV32_USERID_LSB 26
  41. #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000
  42. #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1)
  43. #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask))
  44. #define HAL_RX_TLV32_HDR_SIZE 4
  45. #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \
  46. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  47. HAL_RX_USER_TLV32_TYPE_MASK) >> \
  48. HAL_RX_USER_TLV32_TYPE_LSB)
  49. #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \
  50. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  51. HAL_RX_USER_TLV32_LEN_MASK) >> \
  52. HAL_RX_USER_TLV32_LEN_LSB)
  53. #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \
  54. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  55. HAL_RX_USER_TLV32_USERID_MASK) >> \
  56. HAL_RX_USER_TLV32_USERID_LSB)
  57. #define HAL_TLV_STATUS_PPDU_NOT_DONE 0
  58. #define HAL_TLV_STATUS_PPDU_DONE 1
  59. #define HAL_TLV_STATUS_BUF_DONE 2
  60. #define HAL_MAX_UL_MU_USERS 8
  61. #define HAL_RX_PKT_TYPE_11A 0
  62. #define HAL_RX_PKT_TYPE_11B 1
  63. #define HAL_RX_PKT_TYPE_11N 2
  64. #define HAL_RX_PKT_TYPE_11AC 3
  65. #define HAL_RX_PKT_TYPE_11AX 4
  66. #define HAL_RX_RECEPTION_TYPE_SU 0
  67. #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1
  68. #define HAL_RX_RECEPTION_TYPE_OFDMA 2
  69. #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3
  70. /* Multiply rate by 2 to avoid float point
  71. * and get rate in units of 500kbps
  72. */
  73. #define HAL_11B_RATE_0MCS 11*2
  74. #define HAL_11B_RATE_1MCS 5.5*2
  75. #define HAL_11B_RATE_2MCS 2*2
  76. #define HAL_11B_RATE_3MCS 1*2
  77. #define HAL_11B_RATE_4MCS 11*2
  78. #define HAL_11B_RATE_5MCS 5.5*2
  79. #define HAL_11B_RATE_6MCS 2*2
  80. #define HAL_11A_RATE_0MCS 48*2
  81. #define HAL_11A_RATE_1MCS 24*2
  82. #define HAL_11A_RATE_2MCS 12*2
  83. #define HAL_11A_RATE_3MCS 6*2
  84. #define HAL_11A_RATE_4MCS 54*2
  85. #define HAL_11A_RATE_5MCS 36*2
  86. #define HAL_11A_RATE_6MCS 18*2
  87. #define HAL_11A_RATE_7MCS 9*2
  88. #define HE_GI_0_8 0
  89. #define HE_GI_1_6 1
  90. #define HE_GI_3_2 2
  91. #define HT_SGI_PRESENT 0x80
  92. #define HE_LTF_1_X 0
  93. #define HE_LTF_2_X 1
  94. #define HE_LTF_4_X 2
  95. #define VHT_SIG_SU_NSS_MASK 0x7
  96. #define HAL_TID_INVALID 31
  97. #define HAL_AST_IDX_INVALID 0xFFFF
  98. #ifdef GET_MSDU_AGGREGATION
  99. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\
  100. {\
  101. struct rx_msdu_end *rx_msdu_end;\
  102. bool first_msdu, last_msdu; \
  103. rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\
  104. first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\
  105. last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\
  106. if (first_msdu && last_msdu)\
  107. rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\
  108. else\
  109. rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \
  110. } \
  111. #else
  112. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)
  113. #endif
  114. enum {
  115. HAL_HW_RX_DECAP_FORMAT_RAW = 0,
  116. HAL_HW_RX_DECAP_FORMAT_NWIFI,
  117. HAL_HW_RX_DECAP_FORMAT_ETH2,
  118. HAL_HW_RX_DECAP_FORMAT_8023,
  119. };
  120. enum {
  121. DP_PPDU_STATUS_START,
  122. DP_PPDU_STATUS_DONE,
  123. };
  124. static inline
  125. uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void)
  126. {
  127. /* return the HW_RX_DESC size */
  128. return sizeof(struct rx_pkt_tlvs);
  129. }
  130. static inline
  131. uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data)
  132. {
  133. return data;
  134. }
  135. static inline
  136. uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr)
  137. {
  138. struct rx_attention *rx_attn;
  139. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  140. rx_attn = &rx_desc->attn_tlv.rx_attn;
  141. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
  142. }
  143. static inline
  144. uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr)
  145. {
  146. struct rx_attention *rx_attn;
  147. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  148. rx_attn = &rx_desc->attn_tlv.rx_attn;
  149. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
  150. }
  151. static inline
  152. uint32_t
  153. HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) {
  154. struct rx_msdu_start *rx_msdu_start;
  155. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  156. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  157. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  158. }
  159. static inline
  160. uint8_t *
  161. HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) {
  162. uint8_t *rx_pkt_hdr;
  163. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  164. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  165. return rx_pkt_hdr;
  166. }
  167. static inline
  168. uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr)
  169. {
  170. struct rx_mpdu_info *rx_mpdu_info;
  171. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  172. rx_mpdu_info =
  173. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  174. return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
  175. }
  176. /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */
  177. static inline
  178. uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr)
  179. {
  180. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  181. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  182. return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
  183. }
  184. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  185. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  186. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \
  187. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \
  188. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB))
  189. #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \
  190. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  191. (((struct reo_entrance_ring *)reo_ent_desc) \
  192. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  193. #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \
  194. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  195. (((struct reo_entrance_ring *)reo_ent_desc) \
  196. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  197. #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \
  198. (HAL_RX_BUF_COOKIE_GET(& \
  199. (((struct reo_entrance_ring *)reo_ent_desc) \
  200. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  201. /**
  202. * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and
  203. * cookie from the REO entrance ring element
  204. *
  205. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  206. * the current descriptor
  207. * @ buf_info: structure to return the buffer information
  208. * @ msdu_cnt: pointer to msdu count in MPDU
  209. * Return: void
  210. */
  211. static inline
  212. void hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
  213. struct hal_buf_info *buf_info,
  214. void **pp_buf_addr_info,
  215. uint32_t *msdu_cnt
  216. )
  217. {
  218. struct reo_entrance_ring *reo_ent_ring =
  219. (struct reo_entrance_ring *)rx_desc;
  220. struct buffer_addr_info *buf_addr_info;
  221. struct rx_mpdu_desc_info *rx_mpdu_desc_info_details;
  222. uint32_t loop_cnt;
  223. rx_mpdu_desc_info_details =
  224. &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
  225. *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details,
  226. RX_MPDU_DESC_INFO_0, MSDU_COUNT);
  227. loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT);
  228. buf_addr_info =
  229. &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
  230. buf_info->paddr =
  231. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  232. ((uint64_t)
  233. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  234. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  235. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  236. "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d\n",
  237. __func__, __LINE__, reo_ent_ring, buf_addr_info,
  238. (unsigned long long)buf_info->paddr, loop_cnt);
  239. *pp_buf_addr_info = (void *)buf_addr_info;
  240. }
  241. static inline
  242. void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
  243. struct hal_buf_info *buf_info, void **pp_buf_addr_info)
  244. {
  245. struct rx_msdu_link *msdu_link =
  246. (struct rx_msdu_link *)rx_msdu_link_desc;
  247. struct buffer_addr_info *buf_addr_info;
  248. buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info;
  249. buf_info->paddr =
  250. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  251. ((uint64_t)
  252. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  253. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  254. *pp_buf_addr_info = (void *)buf_addr_info;
  255. }
  256. /**
  257. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  258. *
  259. * @ soc : HAL version of the SOC pointer
  260. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  261. * @ buf_addr_info : void pointer to the buffer_addr_info
  262. *
  263. * Return: void
  264. */
  265. static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc,
  266. void *src_srng_desc, void *buf_addr_info)
  267. {
  268. struct buffer_addr_info *wbm_srng_buffer_addr_info =
  269. (struct buffer_addr_info *)src_srng_desc;
  270. uint64_t paddr;
  271. struct buffer_addr_info *p_buffer_addr_info =
  272. (struct buffer_addr_info *)buf_addr_info;
  273. paddr =
  274. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  275. ((uint64_t)
  276. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  277. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  278. "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx\n",
  279. __func__, __LINE__, src_srng_desc, (unsigned long long)paddr,
  280. (unsigned long long)p_buffer_addr_info->sw_buffer_cookie);
  281. /* Structure copy !!! */
  282. *wbm_srng_buffer_addr_info =
  283. *((struct buffer_addr_info *)buf_addr_info);
  284. }
  285. static inline
  286. uint32 hal_get_rx_msdu_link_desc_size(void)
  287. {
  288. return sizeof(struct rx_msdu_link);
  289. }
  290. enum {
  291. HAL_PKT_TYPE_OFDM = 0,
  292. HAL_PKT_TYPE_CCK,
  293. HAL_PKT_TYPE_HT,
  294. HAL_PKT_TYPE_VHT,
  295. HAL_PKT_TYPE_HE,
  296. };
  297. enum {
  298. HAL_SGI_0_8_US,
  299. HAL_SGI_0_4_US,
  300. HAL_SGI_1_6_US,
  301. HAL_SGI_3_2_US,
  302. };
  303. enum {
  304. HAL_FULL_RX_BW_20,
  305. HAL_FULL_RX_BW_40,
  306. HAL_FULL_RX_BW_80,
  307. HAL_FULL_RX_BW_160,
  308. };
  309. enum {
  310. HAL_RX_TYPE_SU,
  311. HAL_RX_TYPE_MU_MIMO,
  312. HAL_RX_TYPE_MU_OFDMA,
  313. HAL_RX_TYPE_MU_OFDMA_MIMO,
  314. };
  315. /**
  316. * enum
  317. * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL
  318. * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL
  319. */
  320. enum {
  321. HAL_RX_MON_PPDU_START = 0,
  322. HAL_RX_MON_PPDU_END,
  323. };
  324. /**
  325. * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status
  326. *
  327. * @ hw_desc_addr: Start address of Rx HW TLVs
  328. * @ rs: Status for monitor mode
  329. *
  330. * Return: void
  331. */
  332. static inline
  333. void hal_rx_mon_hw_desc_get_mpdu_status(void *hw_desc_addr,
  334. struct mon_rx_status *rs)
  335. {
  336. struct rx_msdu_start *rx_msdu_start;
  337. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  338. uint32_t reg_value;
  339. static uint32_t sgi_hw_to_cdp[] = {
  340. CDP_SGI_0_8_US,
  341. CDP_SGI_0_4_US,
  342. CDP_SGI_1_6_US,
  343. CDP_SGI_3_2_US,
  344. };
  345. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  346. HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
  347. rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
  348. RX_MSDU_START_5, USER_RSSI);
  349. rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
  350. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
  351. rs->sgi = sgi_hw_to_cdp[reg_value];
  352. #if !defined(QCA_WIFI_QCA6290_11AX)
  353. rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS);
  354. #endif
  355. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
  356. rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
  357. /* TODO: rs->beamformed should be set for SU beamforming also */
  358. }
  359. struct hal_rx_ppdu_user_info {
  360. };
  361. struct hal_rx_ppdu_common_info {
  362. uint32_t ppdu_id;
  363. uint32_t last_ppdu_id;
  364. uint32_t ppdu_timestamp;
  365. uint32_t mpdu_cnt_fcs_ok;
  366. uint32_t mpdu_cnt_fcs_err;
  367. };
  368. struct hal_rx_msdu_payload_info {
  369. uint8_t *first_msdu_payload;
  370. uint32_t payload_len;
  371. };
  372. struct hal_rx_ppdu_info {
  373. struct hal_rx_ppdu_common_info com_info;
  374. struct hal_rx_ppdu_user_info user_info[HAL_MAX_UL_MU_USERS];
  375. struct mon_rx_status rx_status;
  376. struct hal_rx_msdu_payload_info msdu_info;
  377. /* status ring PPDU start and end state */
  378. uint32_t rx_state;
  379. };
  380. static inline uint32_t
  381. hal_get_rx_status_buf_size(void) {
  382. /* RX status buffer size is hard coded for now */
  383. return 2048;
  384. }
  385. static inline uint8_t*
  386. hal_rx_status_get_next_tlv(uint8_t *rx_tlv) {
  387. uint32_t tlv_len, tlv_tag;
  388. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
  389. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  390. /* The actual length of PPDU_END is the combined lenght of many PHY
  391. * TLVs that follow. Skip the TLV header and
  392. * rx_rxpcu_classification_overview that follows the header to get to
  393. * next TLV.
  394. */
  395. if (tlv_tag == WIFIRX_PPDU_END_E)
  396. tlv_len = sizeof(struct rx_rxpcu_classification_overview);
  397. return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len +
  398. HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3)));
  399. }
  400. static inline uint32_t
  401. hal_rx_status_get_tlv_info(void *rx_tlv, struct hal_rx_ppdu_info *ppdu_info)
  402. {
  403. uint32_t tlv_tag, user_id, tlv_len, value;
  404. uint8_t group_id = 0;
  405. uint8_t he_dcm = 0;
  406. uint8_t he_stbc = 0;
  407. uint16_t he_gi = 0;
  408. uint16_t he_ltf = 0;
  409. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  410. user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv);
  411. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
  412. rx_tlv = (uint8_t *) rx_tlv + HAL_RX_TLV32_HDR_SIZE;
  413. switch (tlv_tag) {
  414. case WIFIRX_PPDU_START_E:
  415. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  416. "[%s][%d] ppdu_start_e len=%d",
  417. __func__, __LINE__, tlv_len);
  418. ppdu_info->com_info.ppdu_id =
  419. HAL_RX_GET(rx_tlv, RX_PPDU_START_0,
  420. PHY_PPDU_ID);
  421. /* channel number is set in PHY meta data */
  422. ppdu_info->rx_status.chan_num =
  423. HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
  424. SW_PHY_META_DATA);
  425. ppdu_info->com_info.ppdu_timestamp =
  426. HAL_RX_GET(rx_tlv, RX_PPDU_START_2,
  427. PPDU_START_TIMESTAMP);
  428. ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
  429. break;
  430. case WIFIRX_PPDU_START_USER_INFO_E:
  431. break;
  432. case WIFIRX_PPDU_END_E:
  433. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  434. "[%s][%d] ppdu_end_e len=%d",
  435. __func__, __LINE__, tlv_len);
  436. /* This is followed by sub-TLVs of PPDU_END */
  437. ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
  438. break;
  439. case WIFIRXPCU_PPDU_END_INFO_E:
  440. ppdu_info->rx_status.tsft =
  441. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1,
  442. WB_TIMESTAMP_UPPER_32);
  443. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  444. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0,
  445. WB_TIMESTAMP_LOWER_32);
  446. ppdu_info->rx_status.duration =
  447. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_8,
  448. RX_PPDU_DURATION);
  449. break;
  450. case WIFIRX_PPDU_END_USER_STATS_E:
  451. {
  452. unsigned long tid = 0;
  453. uint16_t seq = 0;
  454. ppdu_info->rx_status.ast_index =
  455. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4,
  456. AST_INDEX);
  457. tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12,
  458. RECEIVED_QOS_DATA_TID_BITMAP);
  459. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8);
  460. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  461. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  462. ppdu_info->rx_status.tcp_msdu_count =
  463. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  464. TCP_MSDU_COUNT) +
  465. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  466. TCP_ACK_MSDU_COUNT);
  467. ppdu_info->rx_status.udp_msdu_count =
  468. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  469. UDP_MSDU_COUNT);
  470. ppdu_info->rx_status.other_msdu_count =
  471. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  472. OTHER_MSDU_COUNT);
  473. ppdu_info->rx_status.frame_control_info_valid =
  474. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  475. DATA_SEQUENCE_CONTROL_INFO_VALID);
  476. seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5,
  477. FIRST_DATA_SEQ_CTRL);
  478. if (ppdu_info->rx_status.frame_control_info_valid)
  479. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  480. ppdu_info->rx_status.preamble_type =
  481. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  482. HT_CONTROL_FIELD_PKT_TYPE);
  483. switch (ppdu_info->rx_status.preamble_type) {
  484. case HAL_RX_PKT_TYPE_11N:
  485. ppdu_info->rx_status.ht_flags = 1;
  486. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  487. break;
  488. case HAL_RX_PKT_TYPE_11AC:
  489. ppdu_info->rx_status.vht_flags = 1;
  490. break;
  491. case HAL_RX_PKT_TYPE_11AX:
  492. ppdu_info->rx_status.he_flags = 1;
  493. break;
  494. default:
  495. break;
  496. }
  497. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  498. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  499. MPDU_CNT_FCS_OK);
  500. ppdu_info->com_info.mpdu_cnt_fcs_err =
  501. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2,
  502. MPDU_CNT_FCS_ERR);
  503. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  504. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  505. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  506. else
  507. ppdu_info->rx_status.rs_flags &=
  508. (~IEEE80211_AMPDU_FLAG);
  509. break;
  510. }
  511. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  512. break;
  513. case WIFIRX_PPDU_END_STATUS_DONE_E:
  514. return HAL_TLV_STATUS_PPDU_DONE;
  515. case WIFIDUMMY_E:
  516. return HAL_TLV_STATUS_BUF_DONE;
  517. case WIFIPHYRX_HT_SIG_E:
  518. {
  519. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  520. HAL_RX_OFFSET(PHYRX_HT_SIG_0,
  521. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  522. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1,
  523. FEC_CODING);
  524. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  525. 1 : 0;
  526. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  527. HT_SIG_INFO_0, MCS);
  528. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  529. HT_SIG_INFO_0, CBW);
  530. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  531. HT_SIG_INFO_1, SHORT_GI);
  532. break;
  533. }
  534. case WIFIPHYRX_L_SIG_B_E:
  535. {
  536. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  537. HAL_RX_OFFSET(PHYRX_L_SIG_B_0,
  538. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  539. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE);
  540. switch (value) {
  541. case 1:
  542. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  543. break;
  544. case 2:
  545. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  546. break;
  547. case 3:
  548. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  549. break;
  550. case 4:
  551. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  552. break;
  553. case 5:
  554. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  555. break;
  556. case 6:
  557. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  558. break;
  559. case 7:
  560. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  561. break;
  562. default:
  563. break;
  564. }
  565. ppdu_info->rx_status.cck_flag = 1;
  566. break;
  567. }
  568. case WIFIPHYRX_L_SIG_A_E:
  569. {
  570. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  571. HAL_RX_OFFSET(PHYRX_L_SIG_A_0,
  572. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  573. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE);
  574. switch (value) {
  575. case 8:
  576. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  577. break;
  578. case 9:
  579. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  580. break;
  581. case 10:
  582. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  583. break;
  584. case 11:
  585. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  586. break;
  587. case 12:
  588. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  589. break;
  590. case 13:
  591. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  592. break;
  593. case 14:
  594. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  595. break;
  596. case 15:
  597. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  598. break;
  599. default:
  600. break;
  601. }
  602. ppdu_info->rx_status.ofdm_flag = 1;
  603. break;
  604. }
  605. case WIFIPHYRX_VHT_SIG_A_E:
  606. {
  607. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  608. HAL_RX_OFFSET(PHYRX_VHT_SIG_A_0,
  609. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  610. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1,
  611. SU_MU_CODING);
  612. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  613. 1 : 0;
  614. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID);
  615. ppdu_info->rx_status.vht_flag_values5 = group_id;
  616. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  617. VHT_SIG_A_INFO_1, MCS);
  618. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  619. VHT_SIG_A_INFO_1, GI_SETTING);
  620. #if !defined(QCA_WIFI_QCA6290_11AX)
  621. value = HAL_RX_GET(vht_sig_a_info,
  622. VHT_SIG_A_INFO_0, N_STS);
  623. ppdu_info->rx_status.nss = ((value & VHT_SIG_SU_NSS_MASK) + 1);
  624. #else
  625. ppdu_info->rx_status.nss = 0;
  626. #endif
  627. ppdu_info->rx_status.vht_flag_values3[0] =
  628. (((ppdu_info->rx_status.mcs) << 4)
  629. | ppdu_info->rx_status.nss);
  630. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  631. VHT_SIG_A_INFO_0, BANDWIDTH);
  632. ppdu_info->rx_status.vht_flag_values2 =
  633. ppdu_info->rx_status.bw;
  634. ppdu_info->rx_status.vht_flag_values4 =
  635. HAL_RX_GET(vht_sig_a_info,
  636. VHT_SIG_A_INFO_1, SU_MU_CODING);
  637. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  638. VHT_SIG_A_INFO_1, BEAMFORMED);
  639. break;
  640. }
  641. case WIFIPHYRX_HE_SIG_A_SU_E:
  642. {
  643. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  644. HAL_RX_OFFSET(PHYRX_HE_SIG_A_SU_0,
  645. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  646. ppdu_info->rx_status.he_flags = 1;
  647. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  648. FORMAT_INDICATION);
  649. if (value == 0) {
  650. ppdu_info->rx_status.he_data1 =
  651. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  652. } else {
  653. ppdu_info->rx_status.he_data1 =
  654. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  655. }
  656. /* data1 */
  657. ppdu_info->rx_status.he_data1 |=
  658. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  659. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  660. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  661. QDF_MON_STATUS_HE_MCS_KNOWN |
  662. QDF_MON_STATUS_HE_DCM_KNOWN |
  663. QDF_MON_STATUS_HE_CODING_KNOWN |
  664. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  665. QDF_MON_STATUS_HE_STBC_KNOWN |
  666. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  667. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  668. /* data2 */
  669. ppdu_info->rx_status.he_data2 =
  670. QDF_MON_STATUS_HE_GI_KNOWN;
  671. ppdu_info->rx_status.he_data2 |=
  672. QDF_MON_STATUS_TXBF_KNOWN |
  673. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  674. QDF_MON_STATUS_TXOP_KNOWN |
  675. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  676. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  677. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  678. /* data3 */
  679. value = HAL_RX_GET(he_sig_a_su_info,
  680. HE_SIG_A_SU_INFO_0, BSS_COLOR_ID);
  681. ppdu_info->rx_status.he_data3 = value;
  682. value = HAL_RX_GET(he_sig_a_su_info,
  683. HE_SIG_A_SU_INFO_0, BEAM_CHANGE);
  684. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  685. ppdu_info->rx_status.he_data3 |= value;
  686. value = HAL_RX_GET(he_sig_a_su_info,
  687. HE_SIG_A_SU_INFO_0, DL_UL_FLAG);
  688. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  689. ppdu_info->rx_status.he_data3 |= value;
  690. value = HAL_RX_GET(he_sig_a_su_info,
  691. HE_SIG_A_SU_INFO_0, TRANSMIT_MCS);
  692. ppdu_info->rx_status.mcs = value;
  693. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  694. ppdu_info->rx_status.he_data3 |= value;
  695. value = HAL_RX_GET(he_sig_a_su_info,
  696. HE_SIG_A_SU_INFO_0, DCM);
  697. he_dcm = value;
  698. value = value << QDF_MON_STATUS_DCM_SHIFT;
  699. ppdu_info->rx_status.he_data3 |= value;
  700. value = HAL_RX_GET(he_sig_a_su_info,
  701. HE_SIG_A_SU_INFO_1, CODING);
  702. value = value << QDF_MON_STATUS_CODING_SHIFT;
  703. ppdu_info->rx_status.he_data3 |= value;
  704. value = HAL_RX_GET(he_sig_a_su_info,
  705. HE_SIG_A_SU_INFO_1,
  706. LDPC_EXTRA_SYMBOL);
  707. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  708. ppdu_info->rx_status.he_data3 |= value;
  709. value = HAL_RX_GET(he_sig_a_su_info,
  710. HE_SIG_A_SU_INFO_1, STBC);
  711. he_stbc = value;
  712. value = value << QDF_MON_STATUS_STBC_SHIFT;
  713. ppdu_info->rx_status.he_data3 |= value;
  714. /* data4 */
  715. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  716. SPATIAL_REUSE);
  717. ppdu_info->rx_status.he_data4 = value;
  718. /* data5 */
  719. value = HAL_RX_GET(he_sig_a_su_info,
  720. HE_SIG_A_SU_INFO_0, TRANSMIT_BW);
  721. ppdu_info->rx_status.he_data5 = value;
  722. ppdu_info->rx_status.bw = value;
  723. value = HAL_RX_GET(he_sig_a_su_info,
  724. HE_SIG_A_SU_INFO_0, CP_LTF_SIZE);
  725. switch (value) {
  726. case 0:
  727. he_gi = HE_GI_0_8;
  728. he_ltf = HE_LTF_1_X;
  729. break;
  730. case 1:
  731. he_gi = HE_GI_0_8;
  732. he_ltf = HE_LTF_2_X;
  733. break;
  734. case 2:
  735. he_gi = HE_GI_1_6;
  736. he_ltf = HE_LTF_2_X;
  737. break;
  738. case 3:
  739. if (he_dcm && he_stbc) {
  740. he_gi = HE_GI_0_8;
  741. he_ltf = HE_LTF_4_X;
  742. } else {
  743. he_gi = HE_GI_3_2;
  744. he_ltf = HE_LTF_4_X;
  745. }
  746. break;
  747. }
  748. ppdu_info->rx_status.sgi = he_gi;
  749. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  750. ppdu_info->rx_status.he_data5 |= value;
  751. value = he_ltf << QDF_MON_STATUS_HE_LTF_SHIFT;
  752. ppdu_info->rx_status.he_data5 |= value;
  753. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  754. PACKET_EXTENSION_A_FACTOR);
  755. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  756. ppdu_info->rx_status.he_data5 |= value;
  757. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF);
  758. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  759. ppdu_info->rx_status.he_data5 |= value;
  760. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  761. PACKET_EXTENSION_PE_DISAMBIGUITY);
  762. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  763. ppdu_info->rx_status.he_data5 |= value;
  764. /* data6 */
  765. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
  766. value++;
  767. ppdu_info->rx_status.nss = value;
  768. ppdu_info->rx_status.he_data6 = value;
  769. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  770. DOPPLER_INDICATION);
  771. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  772. ppdu_info->rx_status.he_data6 |= value;
  773. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  774. TXOP_DURATION);
  775. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  776. ppdu_info->rx_status.he_data6 |= value;
  777. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  778. HE_SIG_A_SU_INFO_1, TXBF);
  779. break;
  780. }
  781. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  782. {
  783. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  784. HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_DL_0,
  785. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  786. ppdu_info->rx_status.he_mu_flags = 1;
  787. /* HE Flags */
  788. /*data1*/
  789. ppdu_info->rx_status.he_data1 =
  790. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  791. ppdu_info->rx_status.he_data1 |=
  792. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  793. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  794. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  795. QDF_MON_STATUS_HE_STBC_KNOWN |
  796. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  797. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  798. /* data2 */
  799. ppdu_info->rx_status.he_data2 =
  800. QDF_MON_STATUS_HE_GI_KNOWN;
  801. ppdu_info->rx_status.he_data2 |=
  802. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  803. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  804. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  805. QDF_MON_STATUS_TXOP_KNOWN |
  806. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  807. /*data3*/
  808. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  809. HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID);
  810. ppdu_info->rx_status.he_data3 = value;
  811. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  812. HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG);
  813. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  814. ppdu_info->rx_status.he_data3 |= value;
  815. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  816. HE_SIG_A_MU_DL_INFO_1,
  817. LDPC_EXTRA_SYMBOL);
  818. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  819. ppdu_info->rx_status.he_data3 |= value;
  820. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  821. HE_SIG_A_MU_DL_INFO_1, STBC);
  822. he_stbc = value;
  823. value = value << QDF_MON_STATUS_STBC_SHIFT;
  824. ppdu_info->rx_status.he_data3 |= value;
  825. /*data4*/
  826. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  827. SPATIAL_REUSE);
  828. ppdu_info->rx_status.he_data4 = value;
  829. /*data5*/
  830. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  831. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  832. ppdu_info->rx_status.he_data5 = value;
  833. ppdu_info->rx_status.bw = value;
  834. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  835. HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE);
  836. switch (value) {
  837. case 0:
  838. he_gi = HE_GI_0_8;
  839. he_ltf = HE_LTF_4_X;
  840. break;
  841. case 1:
  842. he_gi = HE_GI_0_8;
  843. he_ltf = HE_LTF_2_X;
  844. break;
  845. case 2:
  846. he_gi = HE_GI_1_6;
  847. he_ltf = HE_LTF_2_X;
  848. break;
  849. case 3:
  850. he_gi = HE_GI_3_2;
  851. he_ltf = HE_LTF_4_X;
  852. break;
  853. }
  854. ppdu_info->rx_status.sgi = he_gi;
  855. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  856. ppdu_info->rx_status.he_data5 |= value;
  857. value = he_ltf << QDF_MON_STATUS_HE_LTF_SHIFT;
  858. ppdu_info->rx_status.he_data5 |= value;
  859. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  860. PACKET_EXTENSION_A_FACTOR);
  861. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  862. ppdu_info->rx_status.he_data5 |= value;
  863. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  864. PACKET_EXTENSION_PE_DISAMBIGUITY);
  865. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  866. ppdu_info->rx_status.he_data5 |= value;
  867. /*data6*/
  868. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  869. DOPPLER_INDICATION);
  870. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  871. ppdu_info->rx_status.he_data6 |= value;
  872. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  873. TXOP_DURATION);
  874. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  875. ppdu_info->rx_status.he_data6 |= value;
  876. /* HE-MU Flags */
  877. /* HE-MU-flags1 */
  878. ppdu_info->rx_status.he_flags1 =
  879. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  880. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  881. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  882. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  883. QDF_MON_STATUS_RU_0_KNOWN;
  884. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  885. HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B);
  886. ppdu_info->rx_status.he_flags1 |= value;
  887. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  888. HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B);
  889. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  890. ppdu_info->rx_status.he_flags1 |= value;
  891. /* HE-MU-flags2 */
  892. ppdu_info->rx_status.he_flags2 =
  893. QDF_MON_STATUS_BW_KNOWN;
  894. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  895. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  896. ppdu_info->rx_status.he_flags2 |= value;
  897. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  898. HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B);
  899. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  900. ppdu_info->rx_status.he_flags2 |= value;
  901. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  902. HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS);
  903. value = value - 1;
  904. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  905. ppdu_info->rx_status.he_flags2 |= value;
  906. break;
  907. }
  908. case WIFIPHYRX_HE_SIG_B1_MU_E:
  909. {
  910. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  911. HAL_RX_OFFSET(PHYRX_HE_SIG_B1_MU_0,
  912. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  913. ppdu_info->rx_status.he_sig_b_common_known |=
  914. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  915. /* TODO: Check on the availability of other fields in
  916. * sig_b_common
  917. */
  918. value = HAL_RX_GET(he_sig_b1_mu_info,
  919. HE_SIG_B1_MU_INFO_0, RU_ALLOCATION);
  920. ppdu_info->rx_status.he_RU[0] = value;
  921. break;
  922. }
  923. case WIFIPHYRX_HE_SIG_B2_MU_E:
  924. {
  925. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  926. HAL_RX_OFFSET(PHYRX_HE_SIG_B2_MU_0,
  927. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  928. /*
  929. * Not all "HE" fields can be updated from
  930. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  931. * to populate rest of the "HE" fields for MU scenarios.
  932. */
  933. /* HE-data1 */
  934. ppdu_info->rx_status.he_data1 |=
  935. QDF_MON_STATUS_HE_MCS_KNOWN |
  936. QDF_MON_STATUS_HE_CODING_KNOWN;
  937. /* HE-data2 */
  938. /* HE-data3 */
  939. value = HAL_RX_GET(he_sig_b2_mu_info,
  940. HE_SIG_B2_MU_INFO_0, STA_MCS);
  941. ppdu_info->rx_status.mcs = value;
  942. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  943. ppdu_info->rx_status.he_data3 |= value;
  944. value = HAL_RX_GET(he_sig_b2_mu_info,
  945. HE_SIG_B2_MU_INFO_0, STA_CODING);
  946. value = value << QDF_MON_STATUS_CODING_SHIFT;
  947. ppdu_info->rx_status.he_data3 |= value;
  948. /* HE-data4 */
  949. value = HAL_RX_GET(he_sig_b2_mu_info,
  950. HE_SIG_B2_MU_INFO_0, STA_ID);
  951. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  952. ppdu_info->rx_status.he_data4 |= value;
  953. /* HE-data5 */
  954. /* HE-data6 */
  955. value = HAL_RX_GET(he_sig_b2_mu_info,
  956. HE_SIG_B2_MU_INFO_0, NSTS);
  957. /* value n indicates n+1 spatial streams */
  958. value++;
  959. ppdu_info->rx_status.nss = value;
  960. ppdu_info->rx_status.he_data6 |= value;
  961. break;
  962. }
  963. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  964. {
  965. uint8_t *he_sig_b2_ofdma_info =
  966. (uint8_t *)rx_tlv +
  967. HAL_RX_OFFSET(PHYRX_HE_SIG_B2_OFDMA_0,
  968. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  969. /*
  970. * Not all "HE" fields can be updated from
  971. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  972. * to populate rest of "HE" fields for MU OFDMA scenarios.
  973. */
  974. /* HE-data1 */
  975. ppdu_info->rx_status.he_data1 |=
  976. QDF_MON_STATUS_HE_MCS_KNOWN |
  977. QDF_MON_STATUS_HE_DCM_KNOWN |
  978. QDF_MON_STATUS_HE_CODING_KNOWN;
  979. /* HE-data2 */
  980. ppdu_info->rx_status.he_data2 |=
  981. QDF_MON_STATUS_TXBF_KNOWN;
  982. /* HE-data3 */
  983. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  984. HE_SIG_B2_OFDMA_INFO_0, STA_MCS);
  985. ppdu_info->rx_status.mcs = value;
  986. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  987. ppdu_info->rx_status.he_data3 |= value;
  988. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  989. HE_SIG_B2_OFDMA_INFO_0, STA_DCM);
  990. he_dcm = value;
  991. value = value << QDF_MON_STATUS_DCM_SHIFT;
  992. ppdu_info->rx_status.he_data3 |= value;
  993. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  994. HE_SIG_B2_OFDMA_INFO_0, STA_CODING);
  995. value = value << QDF_MON_STATUS_CODING_SHIFT;
  996. ppdu_info->rx_status.he_data3 |= value;
  997. /* HE-data4 */
  998. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  999. HE_SIG_B2_OFDMA_INFO_0, STA_ID);
  1000. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1001. ppdu_info->rx_status.he_data4 |= value;
  1002. /* HE-data5 */
  1003. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1004. HE_SIG_B2_OFDMA_INFO_0, TXBF);
  1005. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  1006. ppdu_info->rx_status.he_data5 |= value;
  1007. /* HE-data6 */
  1008. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1009. HE_SIG_B2_OFDMA_INFO_0, NSTS);
  1010. /* value n indicates n+1 spatial streams */
  1011. value++;
  1012. ppdu_info->rx_status.nss = value;
  1013. ppdu_info->rx_status.he_data6 |= value;
  1014. break;
  1015. }
  1016. case WIFIPHYRX_RSSI_LEGACY_E:
  1017. {
  1018. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  1019. HAL_RX_OFFSET(PHYRX_RSSI_LEGACY_3,
  1020. RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS);
  1021. ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
  1022. PHYRX_RSSI_LEGACY_35, RSSI_COMB);
  1023. ppdu_info->rx_status.bw = HAL_RX_GET(rx_tlv,
  1024. #if !defined(QCA_WIFI_QCA6290_11AX)
  1025. PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH);
  1026. #else
  1027. PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
  1028. #endif
  1029. ppdu_info->rx_status.he_re = 0;
  1030. ppdu_info->rx_status.reception_type = HAL_RX_GET(rx_tlv,
  1031. PHYRX_RSSI_LEGACY_0, RECEPTION_TYPE);
  1032. value = HAL_RX_GET(rssi_info_tlv,
  1033. RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0);
  1034. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1035. "RSSI_PRI20_CHAIN0: %d\n", value);
  1036. value = HAL_RX_GET(rssi_info_tlv,
  1037. RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0);
  1038. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1039. "RSSI_EXT20_CHAIN0: %d\n", value);
  1040. value = HAL_RX_GET(rssi_info_tlv,
  1041. RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0);
  1042. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1043. "RSSI_EXT40_LOW20_CHAIN0: %d\n", value);
  1044. value = HAL_RX_GET(rssi_info_tlv,
  1045. RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0);
  1046. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1047. "RSSI_EXT40_HIGH20_CHAIN0: %d\n", value);
  1048. value = HAL_RX_GET(rssi_info_tlv,
  1049. RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0);
  1050. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1051. "RSSI_EXT80_LOW20_CHAIN0: %d\n", value);
  1052. value = HAL_RX_GET(rssi_info_tlv,
  1053. RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0);
  1054. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1055. "RSSI_EXT80_LOW_HIGH20_CHAIN0: %d\n", value);
  1056. value = HAL_RX_GET(rssi_info_tlv,
  1057. RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0);
  1058. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1059. "RSSI_EXT80_HIGH_LOW20_CHAIN0: %d\n", value);
  1060. value = HAL_RX_GET(rssi_info_tlv,
  1061. RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH20_CHAIN0);
  1062. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1063. "RSSI_EXT80_HIGH20_CHAIN0: %d\n", value);
  1064. break;
  1065. }
  1066. case WIFIRX_HEADER_E:
  1067. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  1068. ppdu_info->msdu_info.payload_len = tlv_len;
  1069. break;
  1070. case WIFIRX_MPDU_START_E:
  1071. {
  1072. uint8_t *rx_mpdu_start =
  1073. (uint8_t *)rx_tlv + HAL_RX_OFFSET(RX_MPDU_START_0,
  1074. RX_MPDU_INFO_RX_MPDU_INFO_DETAILS);
  1075. uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0,
  1076. PHY_PPDU_ID);
  1077. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  1078. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  1079. ppdu_info->rx_status.ppdu_len =
  1080. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1081. MPDU_LENGTH);
  1082. } else {
  1083. ppdu_info->rx_status.ppdu_len +=
  1084. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1085. MPDU_LENGTH);
  1086. }
  1087. break;
  1088. }
  1089. case 0:
  1090. return HAL_TLV_STATUS_PPDU_DONE;
  1091. default:
  1092. break;
  1093. }
  1094. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1095. "%s TLV type: %d, TLV len:%d",
  1096. __func__, tlv_tag, tlv_len);
  1097. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1098. }
  1099. static inline
  1100. uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc)
  1101. {
  1102. return HAL_RX_TLV32_HDR_SIZE;
  1103. }
  1104. static inline QDF_STATUS
  1105. hal_get_rx_status_done(uint8_t *rx_tlv)
  1106. {
  1107. uint32_t tlv_tag;
  1108. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  1109. if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E)
  1110. return QDF_STATUS_SUCCESS;
  1111. else
  1112. return QDF_STATUS_E_EMPTY;
  1113. }
  1114. static inline QDF_STATUS
  1115. hal_clear_rx_status_done(uint8_t *rx_tlv)
  1116. {
  1117. *(uint32_t *)rx_tlv = 0;
  1118. return QDF_STATUS_SUCCESS;
  1119. }
  1120. #endif