dp_rings_main.c 139 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_ipa_obj_mgmt_api.h>
  20. #include <qdf_types.h>
  21. #include <qdf_lock.h>
  22. #include <qdf_net_types.h>
  23. #include <qdf_lro.h>
  24. #include <qdf_module.h>
  25. #include <hal_hw_headers.h>
  26. #include <hal_api.h>
  27. #include <hif.h>
  28. #include <htt.h>
  29. #include <wdi_event.h>
  30. #include <queue.h>
  31. #include "dp_types.h"
  32. #include "dp_rings.h"
  33. #include "dp_internal.h"
  34. #include "dp_tx.h"
  35. #include "dp_tx_desc.h"
  36. #include "dp_rx.h"
  37. #ifdef DP_RATETABLE_SUPPORT
  38. #include "dp_ratetable.h"
  39. #endif
  40. #include <cdp_txrx_handle.h>
  41. #include <wlan_cfg.h>
  42. #include <wlan_utility.h>
  43. #include "cdp_txrx_cmn_struct.h"
  44. #include "cdp_txrx_stats_struct.h"
  45. #include "cdp_txrx_cmn_reg.h"
  46. #include <qdf_util.h>
  47. #include "dp_peer.h"
  48. #include "htt_stats.h"
  49. #include "dp_htt.h"
  50. #include "htt_ppdu_stats.h"
  51. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  52. #include "cfg_ucfg_api.h"
  53. #include <wlan_module_ids.h>
  54. #ifdef WIFI_MONITOR_SUPPORT
  55. #include <dp_mon.h>
  56. #endif
  57. #ifdef WLAN_FEATURE_STATS_EXT
  58. #define INIT_RX_HW_STATS_LOCK(_soc) \
  59. qdf_spinlock_create(&(_soc)->rx_hw_stats_lock)
  60. #define DEINIT_RX_HW_STATS_LOCK(_soc) \
  61. qdf_spinlock_destroy(&(_soc)->rx_hw_stats_lock)
  62. #else
  63. #define INIT_RX_HW_STATS_LOCK(_soc) /* no op */
  64. #define DEINIT_RX_HW_STATS_LOCK(_soc) /* no op */
  65. #endif
  66. #ifdef QCA_DP_ENABLE_TX_COMP_RING4
  67. #define TXCOMP_RING4_NUM 3
  68. #else
  69. #define TXCOMP_RING4_NUM WBM2SW_TXCOMP_RING4_NUM
  70. #endif
  71. static QDF_STATUS dp_init_tx_ring_pair_by_index(struct dp_soc *soc,
  72. uint8_t index);
  73. static void dp_deinit_tx_pair_by_index(struct dp_soc *soc, int index);
  74. static void dp_free_tx_ring_pair_by_index(struct dp_soc *soc, uint8_t index);
  75. static QDF_STATUS dp_alloc_tx_ring_pair_by_index(struct dp_soc *soc,
  76. uint8_t index);
  77. /* default_dscp_tid_map - Default DSCP-TID mapping
  78. *
  79. * DSCP TID
  80. * 000000 0
  81. * 001000 1
  82. * 010000 2
  83. * 011000 3
  84. * 100000 4
  85. * 101000 5
  86. * 110000 6
  87. * 111000 7
  88. */
  89. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 1, 1, 1, 1, 1, 1, 1, 1,
  92. 2, 2, 2, 2, 2, 2, 2, 2,
  93. 3, 3, 3, 3, 3, 3, 3, 3,
  94. 4, 4, 4, 4, 4, 4, 4, 4,
  95. 5, 5, 5, 5, 5, 5, 5, 5,
  96. 6, 6, 6, 6, 6, 6, 6, 6,
  97. 7, 7, 7, 7, 7, 7, 7, 7,
  98. };
  99. /* default_pcp_tid_map - Default PCP-TID mapping
  100. *
  101. * PCP TID
  102. * 000 0
  103. * 001 1
  104. * 010 2
  105. * 011 3
  106. * 100 4
  107. * 101 5
  108. * 110 6
  109. * 111 7
  110. */
  111. static uint8_t default_pcp_tid_map[PCP_TID_MAP_MAX] = {
  112. 0, 1, 2, 3, 4, 5, 6, 7,
  113. };
  114. uint8_t
  115. dp_cpu_ring_map[DP_NSS_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS_MAX] = {
  116. {0x0, 0x1, 0x2, 0x0, 0x0, 0x1, 0x2, 0x0, 0x0, 0x1, 0x2},
  117. {0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1},
  118. {0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0},
  119. {0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2},
  120. {0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3},
  121. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  122. {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1}
  123. #endif
  124. };
  125. qdf_export_symbol(dp_cpu_ring_map);
  126. /**
  127. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  128. * @soc: DP soc handle
  129. * @ring_type: ring type
  130. * @ring_num: ring_num
  131. *
  132. * Return: 0 if the ring is not offloaded, non-0 if it is offloaded
  133. */
  134. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc,
  135. enum hal_ring_type ring_type,
  136. int ring_num)
  137. {
  138. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  139. uint8_t status = 0;
  140. switch (ring_type) {
  141. case WBM2SW_RELEASE:
  142. case REO_DST:
  143. case RXDMA_BUF:
  144. case REO_EXCEPTION:
  145. status = ((nss_config) & (1 << ring_num));
  146. break;
  147. default:
  148. break;
  149. }
  150. return status;
  151. }
  152. /* MCL specific functions */
  153. #if defined(DP_CON_MON)
  154. #ifdef DP_CON_MON_MSI_ENABLED
  155. /**
  156. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  157. * @soc: pointer to dp_soc handle
  158. * @intr_ctx_num: interrupt context number for which mon mask is needed
  159. *
  160. * For MCL, monitor mode rings are being processed in timer contexts (polled).
  161. * This function is returning 0, since in interrupt mode(softirq based RX),
  162. * we donot want to process monitor mode rings in a softirq.
  163. *
  164. * So, in case packet log is enabled for SAP/STA/P2P modes,
  165. * regular interrupt processing will not process monitor mode rings. It would be
  166. * done in a separate timer context.
  167. *
  168. * Return: 0
  169. */
  170. static inline uint32_t
  171. dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc, int intr_ctx_num)
  172. {
  173. return wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  174. }
  175. #else
  176. /**
  177. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  178. * @soc: pointer to dp_soc handle
  179. * @intr_ctx_num: interrupt context number for which mon mask is needed
  180. *
  181. * For MCL, monitor mode rings are being processed in timer contexts (polled).
  182. * This function is returning 0, since in interrupt mode(softirq based RX),
  183. * we donot want to process monitor mode rings in a softirq.
  184. *
  185. * So, in case packet log is enabled for SAP/STA/P2P modes,
  186. * regular interrupt processing will not process monitor mode rings. It would be
  187. * done in a separate timer context.
  188. *
  189. * Return: 0
  190. */
  191. static inline uint32_t
  192. dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc, int intr_ctx_num)
  193. {
  194. return 0;
  195. }
  196. #endif
  197. #else
  198. /**
  199. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  200. * @soc: pointer to dp_soc handle
  201. * @intr_ctx_num: interrupt context number for which mon mask is needed
  202. *
  203. * Return: mon mask value
  204. */
  205. static inline
  206. uint32_t dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc,
  207. int intr_ctx_num)
  208. {
  209. return wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  210. }
  211. void dp_soc_reset_mon_intr_mask(struct dp_soc *soc)
  212. {
  213. int i;
  214. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  215. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  216. soc->intr_ctx[i].host2rxdma_mon_ring_mask = 0;
  217. }
  218. }
  219. qdf_export_symbol(dp_soc_reset_mon_intr_mask);
  220. void dp_service_lmac_rings(void *arg)
  221. {
  222. struct dp_soc *soc = (struct dp_soc *)arg;
  223. int ring = 0, i;
  224. struct dp_pdev *pdev = NULL;
  225. union dp_rx_desc_list_elem_t *desc_list = NULL;
  226. union dp_rx_desc_list_elem_t *tail = NULL;
  227. /* Process LMAC interrupts */
  228. for (ring = 0 ; ring < MAX_NUM_LMAC_HW; ring++) {
  229. int mac_for_pdev = ring;
  230. struct dp_srng *rx_refill_buf_ring;
  231. pdev = dp_get_pdev_for_lmac_id(soc, mac_for_pdev);
  232. if (!pdev)
  233. continue;
  234. rx_refill_buf_ring = &soc->rx_refill_buf_ring[mac_for_pdev];
  235. dp_monitor_process(soc, NULL, mac_for_pdev,
  236. QCA_NAPI_BUDGET);
  237. for (i = 0;
  238. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  239. dp_rxdma_err_process(&soc->intr_ctx[i], soc,
  240. mac_for_pdev,
  241. QCA_NAPI_BUDGET);
  242. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF,
  243. mac_for_pdev))
  244. dp_rx_buffers_replenish(soc, mac_for_pdev,
  245. rx_refill_buf_ring,
  246. &soc->rx_desc_buf[mac_for_pdev],
  247. 0, &desc_list, &tail, false);
  248. }
  249. qdf_timer_mod(&soc->lmac_reap_timer, DP_INTR_POLL_TIMER_MS);
  250. }
  251. #endif
  252. /**
  253. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  254. * @ring_num: ring num of the ring being queried
  255. * @grp_mask: the grp_mask array for the ring type in question.
  256. *
  257. * The grp_mask array is indexed by group number and the bit fields correspond
  258. * to ring numbers. We are finding which interrupt group a ring belongs to.
  259. *
  260. * Return: the index in the grp_mask array with the ring number.
  261. * -QDF_STATUS_E_NOENT if no entry is found
  262. */
  263. static int dp_srng_find_ring_in_mask(int ring_num, uint8_t *grp_mask)
  264. {
  265. int ext_group_num;
  266. uint8_t mask = 1 << ring_num;
  267. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  268. ext_group_num++) {
  269. if (mask & grp_mask[ext_group_num])
  270. return ext_group_num;
  271. }
  272. return -QDF_STATUS_E_NOENT;
  273. }
  274. /**
  275. * dp_is_msi_group_number_invalid() - check msi_group_number valid or not
  276. * @soc: dp_soc
  277. * @msi_group_number: MSI group number.
  278. * @msi_data_count: MSI data count.
  279. *
  280. * Return: true if msi_group_number is invalid.
  281. */
  282. static bool dp_is_msi_group_number_invalid(struct dp_soc *soc,
  283. int msi_group_number,
  284. int msi_data_count)
  285. {
  286. if (soc && soc->osdev && soc->osdev->dev &&
  287. pld_is_one_msi(soc->osdev->dev))
  288. return false;
  289. return msi_group_number > msi_data_count;
  290. }
  291. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  292. /**
  293. * dp_is_reo_ring_num_in_nf_grp1() - Check if the current reo ring is part of
  294. * rx_near_full_grp1 mask
  295. * @soc: Datapath SoC Handle
  296. * @ring_num: REO ring number
  297. *
  298. * Return: 1 if the ring_num belongs to reo_nf_grp1,
  299. * 0, otherwise.
  300. */
  301. static inline int
  302. dp_is_reo_ring_num_in_nf_grp1(struct dp_soc *soc, int ring_num)
  303. {
  304. return (WLAN_CFG_RX_NEAR_FULL_IRQ_MASK_1 & (1 << ring_num));
  305. }
  306. /**
  307. * dp_is_reo_ring_num_in_nf_grp2() - Check if the current reo ring is part of
  308. * rx_near_full_grp2 mask
  309. * @soc: Datapath SoC Handle
  310. * @ring_num: REO ring number
  311. *
  312. * Return: 1 if the ring_num belongs to reo_nf_grp2,
  313. * 0, otherwise.
  314. */
  315. static inline int
  316. dp_is_reo_ring_num_in_nf_grp2(struct dp_soc *soc, int ring_num)
  317. {
  318. return (WLAN_CFG_RX_NEAR_FULL_IRQ_MASK_2 & (1 << ring_num));
  319. }
  320. /**
  321. * dp_srng_get_near_full_irq_mask() - Get near-full irq mask for a particular
  322. * ring type and number
  323. * @soc: Datapath SoC handle
  324. * @ring_type: SRNG type
  325. * @ring_num: ring num
  326. *
  327. * Return: near-full irq mask pointer
  328. */
  329. static inline
  330. uint8_t *dp_srng_get_near_full_irq_mask(struct dp_soc *soc,
  331. enum hal_ring_type ring_type,
  332. int ring_num)
  333. {
  334. struct wlan_cfg_dp_soc_ctxt *cfg_ctx = soc->wlan_cfg_ctx;
  335. uint8_t wbm2_sw_rx_rel_ring_id;
  336. uint8_t *nf_irq_mask = NULL;
  337. switch (ring_type) {
  338. case WBM2SW_RELEASE:
  339. wbm2_sw_rx_rel_ring_id =
  340. wlan_cfg_get_rx_rel_ring_id(cfg_ctx);
  341. if (ring_num != wbm2_sw_rx_rel_ring_id) {
  342. nf_irq_mask = &soc->wlan_cfg_ctx->
  343. int_tx_ring_near_full_irq_mask[0];
  344. }
  345. break;
  346. case REO_DST:
  347. if (dp_is_reo_ring_num_in_nf_grp1(soc, ring_num))
  348. nf_irq_mask =
  349. &soc->wlan_cfg_ctx->int_rx_ring_near_full_irq_1_mask[0];
  350. else if (dp_is_reo_ring_num_in_nf_grp2(soc, ring_num))
  351. nf_irq_mask =
  352. &soc->wlan_cfg_ctx->int_rx_ring_near_full_irq_2_mask[0];
  353. else
  354. qdf_assert(0);
  355. break;
  356. default:
  357. break;
  358. }
  359. return nf_irq_mask;
  360. }
  361. /**
  362. * dp_srng_set_msi2_ring_params() - Set the msi2 addr/data in the ring params
  363. * @soc: Datapath SoC handle
  364. * @ring_params: srng params handle
  365. * @msi2_addr: MSI2 addr to be set for the SRNG
  366. * @msi2_data: MSI2 data to be set for the SRNG
  367. *
  368. * Return: None
  369. */
  370. static inline
  371. void dp_srng_set_msi2_ring_params(struct dp_soc *soc,
  372. struct hal_srng_params *ring_params,
  373. qdf_dma_addr_t msi2_addr,
  374. uint32_t msi2_data)
  375. {
  376. ring_params->msi2_addr = msi2_addr;
  377. ring_params->msi2_data = msi2_data;
  378. }
  379. /**
  380. * dp_srng_msi2_setup() - Setup MSI2 details for near full IRQ of an SRNG
  381. * @soc: Datapath SoC handle
  382. * @ring_params: ring_params for SRNG
  383. * @ring_type: SENG type
  384. * @ring_num: ring number for the SRNG
  385. * @nf_msi_grp_num: near full msi group number
  386. *
  387. * Return: None
  388. */
  389. static inline void
  390. dp_srng_msi2_setup(struct dp_soc *soc,
  391. struct hal_srng_params *ring_params,
  392. int ring_type, int ring_num, int nf_msi_grp_num)
  393. {
  394. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  395. int msi_data_count, ret;
  396. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  397. &msi_data_count, &msi_data_start,
  398. &msi_irq_start);
  399. if (ret)
  400. return;
  401. if (nf_msi_grp_num < 0) {
  402. dp_init_info("%pK: ring near full IRQ not part of an ext_group; ring_type: %d,ring_num %d",
  403. soc, ring_type, ring_num);
  404. ring_params->msi2_addr = 0;
  405. ring_params->msi2_data = 0;
  406. return;
  407. }
  408. if (dp_is_msi_group_number_invalid(soc, nf_msi_grp_num,
  409. msi_data_count)) {
  410. dp_init_warn("%pK: 2 msi_groups will share an msi for near full IRQ; msi_group_num %d",
  411. soc, nf_msi_grp_num);
  412. QDF_ASSERT(0);
  413. }
  414. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  415. ring_params->nf_irq_support = 1;
  416. ring_params->msi2_addr = addr_low;
  417. ring_params->msi2_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  418. ring_params->msi2_data = (nf_msi_grp_num % msi_data_count)
  419. + msi_data_start;
  420. ring_params->flags |= HAL_SRNG_MSI_INTR;
  421. }
  422. /* Percentage of ring entries considered as nearly full */
  423. #define DP_NF_HIGH_THRESH_PERCENTAGE 75
  424. /* Percentage of ring entries considered as critically full */
  425. #define DP_NF_CRIT_THRESH_PERCENTAGE 90
  426. /* Percentage of ring entries considered as safe threshold */
  427. #define DP_NF_SAFE_THRESH_PERCENTAGE 50
  428. /**
  429. * dp_srng_configure_nf_interrupt_thresholds() - Configure the thresholds for
  430. * near full irq
  431. * @soc: Datapath SoC handle
  432. * @ring_params: ring params for SRNG
  433. * @ring_type: ring type
  434. */
  435. static inline void
  436. dp_srng_configure_nf_interrupt_thresholds(struct dp_soc *soc,
  437. struct hal_srng_params *ring_params,
  438. int ring_type)
  439. {
  440. if (ring_params->nf_irq_support) {
  441. ring_params->high_thresh = (ring_params->num_entries *
  442. DP_NF_HIGH_THRESH_PERCENTAGE) / 100;
  443. ring_params->crit_thresh = (ring_params->num_entries *
  444. DP_NF_CRIT_THRESH_PERCENTAGE) / 100;
  445. ring_params->safe_thresh = (ring_params->num_entries *
  446. DP_NF_SAFE_THRESH_PERCENTAGE) /100;
  447. }
  448. }
  449. /**
  450. * dp_srng_set_nf_thresholds() - Set the near full thresholds to srng data
  451. * structure from the ring params
  452. * @soc: Datapath SoC handle
  453. * @srng: SRNG handle
  454. * @ring_params: ring params for a SRNG
  455. *
  456. * Return: None
  457. */
  458. static inline void
  459. dp_srng_set_nf_thresholds(struct dp_soc *soc, struct dp_srng *srng,
  460. struct hal_srng_params *ring_params)
  461. {
  462. srng->crit_thresh = ring_params->crit_thresh;
  463. srng->safe_thresh = ring_params->safe_thresh;
  464. }
  465. #else
  466. static inline
  467. uint8_t *dp_srng_get_near_full_irq_mask(struct dp_soc *soc,
  468. enum hal_ring_type ring_type,
  469. int ring_num)
  470. {
  471. return NULL;
  472. }
  473. static inline
  474. void dp_srng_set_msi2_ring_params(struct dp_soc *soc,
  475. struct hal_srng_params *ring_params,
  476. qdf_dma_addr_t msi2_addr,
  477. uint32_t msi2_data)
  478. {
  479. }
  480. static inline void
  481. dp_srng_msi2_setup(struct dp_soc *soc,
  482. struct hal_srng_params *ring_params,
  483. int ring_type, int ring_num, int nf_msi_grp_num)
  484. {
  485. }
  486. static inline void
  487. dp_srng_configure_nf_interrupt_thresholds(struct dp_soc *soc,
  488. struct hal_srng_params *ring_params,
  489. int ring_type)
  490. {
  491. }
  492. static inline void
  493. dp_srng_set_nf_thresholds(struct dp_soc *soc, struct dp_srng *srng,
  494. struct hal_srng_params *ring_params)
  495. {
  496. }
  497. #endif
  498. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  499. enum hal_ring_type ring_type,
  500. int ring_num,
  501. int *reg_msi_grp_num,
  502. bool nf_irq_support,
  503. int *nf_msi_grp_num)
  504. {
  505. struct wlan_cfg_dp_soc_ctxt *cfg_ctx = soc->wlan_cfg_ctx;
  506. uint8_t *grp_mask, *nf_irq_mask = NULL;
  507. bool nf_irq_enabled = false;
  508. uint8_t wbm2_sw_rx_rel_ring_id;
  509. switch (ring_type) {
  510. case WBM2SW_RELEASE:
  511. wbm2_sw_rx_rel_ring_id =
  512. wlan_cfg_get_rx_rel_ring_id(cfg_ctx);
  513. if (ring_num == wbm2_sw_rx_rel_ring_id) {
  514. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  515. grp_mask = &cfg_ctx->int_rx_wbm_rel_ring_mask[0];
  516. ring_num = 0;
  517. } else if (ring_num == WBM2_SW_PPE_REL_RING_ID) {
  518. grp_mask = &cfg_ctx->int_ppeds_wbm_release_ring_mask[0];
  519. ring_num = 0;
  520. } else { /* dp_tx_comp_handler - soc->tx_comp_ring */
  521. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  522. nf_irq_mask = dp_srng_get_near_full_irq_mask(soc,
  523. ring_type,
  524. ring_num);
  525. if (nf_irq_mask)
  526. nf_irq_enabled = true;
  527. /*
  528. * Using ring 4 as 4th tx completion ring since ring 3
  529. * is Rx error ring
  530. */
  531. if (ring_num == WBM2SW_TXCOMP_RING4_NUM)
  532. ring_num = TXCOMP_RING4_NUM;
  533. }
  534. break;
  535. case REO_EXCEPTION:
  536. /* dp_rx_err_process - &soc->reo_exception_ring */
  537. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  538. break;
  539. case REO_DST:
  540. /* dp_rx_process - soc->reo_dest_ring */
  541. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  542. nf_irq_mask = dp_srng_get_near_full_irq_mask(soc, ring_type,
  543. ring_num);
  544. if (nf_irq_mask)
  545. nf_irq_enabled = true;
  546. break;
  547. case REO_STATUS:
  548. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  549. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  550. break;
  551. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  552. case RXDMA_MONITOR_STATUS:
  553. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  554. case RXDMA_MONITOR_DST:
  555. /* dp_mon_process */
  556. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  557. break;
  558. case TX_MONITOR_DST:
  559. /* dp_tx_mon_process */
  560. grp_mask = &soc->wlan_cfg_ctx->int_tx_mon_ring_mask[0];
  561. break;
  562. case RXDMA_DST:
  563. /* dp_rxdma_err_process */
  564. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  565. break;
  566. case RXDMA_BUF:
  567. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  568. break;
  569. case RXDMA_MONITOR_BUF:
  570. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_mon_ring_mask[0];
  571. break;
  572. case TX_MONITOR_BUF:
  573. grp_mask = &soc->wlan_cfg_ctx->int_host2txmon_ring_mask[0];
  574. break;
  575. case REO2PPE:
  576. grp_mask = &soc->wlan_cfg_ctx->int_reo2ppe_ring_mask[0];
  577. break;
  578. case PPE2TCL:
  579. grp_mask = &soc->wlan_cfg_ctx->int_ppe2tcl_ring_mask[0];
  580. break;
  581. case TCL_DATA:
  582. /* CMD_CREDIT_RING is used as command in 8074 and credit in 9000 */
  583. case TCL_CMD_CREDIT:
  584. case REO_CMD:
  585. case SW2WBM_RELEASE:
  586. case WBM_IDLE_LINK:
  587. /* normally empty SW_TO_HW rings */
  588. return -QDF_STATUS_E_NOENT;
  589. break;
  590. case TCL_STATUS:
  591. case REO_REINJECT:
  592. /* misc unused rings */
  593. return -QDF_STATUS_E_NOENT;
  594. break;
  595. case CE_SRC:
  596. case CE_DST:
  597. case CE_DST_STATUS:
  598. /* CE_rings - currently handled by hif */
  599. default:
  600. return -QDF_STATUS_E_NOENT;
  601. break;
  602. }
  603. *reg_msi_grp_num = dp_srng_find_ring_in_mask(ring_num, grp_mask);
  604. if (nf_irq_support && nf_irq_enabled) {
  605. *nf_msi_grp_num = dp_srng_find_ring_in_mask(ring_num,
  606. nf_irq_mask);
  607. }
  608. return QDF_STATUS_SUCCESS;
  609. }
  610. /**
  611. * dp_get_num_msi_available()- API to get number of MSIs available
  612. * @soc: DP soc Handle
  613. * @interrupt_mode: Mode of interrupts
  614. *
  615. * Return: Number of MSIs available or 0 in case of integrated
  616. */
  617. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  618. static int dp_get_num_msi_available(struct dp_soc *soc, int interrupt_mode)
  619. {
  620. return 0;
  621. }
  622. #else
  623. static int dp_get_num_msi_available(struct dp_soc *soc, int interrupt_mode)
  624. {
  625. int msi_data_count;
  626. int msi_data_start;
  627. int msi_irq_start;
  628. int ret;
  629. if (interrupt_mode == DP_INTR_INTEGRATED) {
  630. return 0;
  631. } else if (interrupt_mode == DP_INTR_MSI || interrupt_mode ==
  632. DP_INTR_POLL) {
  633. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  634. &msi_data_count,
  635. &msi_data_start,
  636. &msi_irq_start);
  637. if (ret) {
  638. qdf_err("Unable to get DP MSI assignment %d",
  639. interrupt_mode);
  640. return -EINVAL;
  641. }
  642. return msi_data_count;
  643. }
  644. qdf_err("Interrupt mode invalid %d", interrupt_mode);
  645. return -EINVAL;
  646. }
  647. #endif
  648. #if defined(IPA_OFFLOAD) && defined(IPA_WDI3_VLAN_SUPPORT)
  649. static void
  650. dp_ipa_vlan_srng_msi_setup(struct hal_srng_params *ring_params, int ring_type,
  651. int ring_num)
  652. {
  653. if (wlan_ipa_is_vlan_enabled()) {
  654. if ((ring_type == REO_DST) &&
  655. (ring_num == IPA_ALT_REO_DEST_RING_IDX)) {
  656. ring_params->msi_addr = 0;
  657. ring_params->msi_data = 0;
  658. ring_params->flags &= ~HAL_SRNG_MSI_INTR;
  659. }
  660. }
  661. }
  662. #else
  663. static inline void
  664. dp_ipa_vlan_srng_msi_setup(struct hal_srng_params *ring_params, int ring_type,
  665. int ring_num)
  666. {
  667. }
  668. #endif
  669. static void dp_srng_msi_setup(struct dp_soc *soc, struct dp_srng *srng,
  670. struct hal_srng_params *ring_params,
  671. int ring_type, int ring_num)
  672. {
  673. int reg_msi_grp_num;
  674. /*
  675. * nf_msi_grp_num needs to be initialized with negative value,
  676. * to avoid configuring near-full msi for WBM2SW3 ring
  677. */
  678. int nf_msi_grp_num = -1;
  679. int msi_data_count;
  680. int ret;
  681. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  682. bool nf_irq_support;
  683. int vector;
  684. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  685. &msi_data_count, &msi_data_start,
  686. &msi_irq_start);
  687. if (ret)
  688. return;
  689. nf_irq_support = hal_srng_is_near_full_irq_supported(soc->hal_soc,
  690. ring_type,
  691. ring_num);
  692. ret = dp_srng_calculate_msi_group(soc, ring_type, ring_num,
  693. &reg_msi_grp_num,
  694. nf_irq_support,
  695. &nf_msi_grp_num);
  696. if (ret < 0) {
  697. dp_init_info("%pK: ring not part of an ext_group; ring_type: %d,ring_num %d",
  698. soc, ring_type, ring_num);
  699. ring_params->msi_addr = 0;
  700. ring_params->msi_data = 0;
  701. dp_srng_set_msi2_ring_params(soc, ring_params, 0, 0);
  702. return;
  703. }
  704. if (reg_msi_grp_num < 0) {
  705. dp_init_info("%pK: ring not part of an ext_group; ring_type: %d,ring_num %d",
  706. soc, ring_type, ring_num);
  707. ring_params->msi_addr = 0;
  708. ring_params->msi_data = 0;
  709. goto configure_msi2;
  710. }
  711. if (dp_is_msi_group_number_invalid(soc, reg_msi_grp_num,
  712. msi_data_count)) {
  713. dp_init_warn("%pK: 2 msi_groups will share an msi; msi_group_num %d",
  714. soc, reg_msi_grp_num);
  715. QDF_ASSERT(0);
  716. }
  717. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  718. ring_params->msi_addr = addr_low;
  719. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  720. ring_params->msi_data = (reg_msi_grp_num % msi_data_count)
  721. + msi_data_start;
  722. ring_params->flags |= HAL_SRNG_MSI_INTR;
  723. dp_ipa_vlan_srng_msi_setup(ring_params, ring_type, ring_num);
  724. dp_debug("ring type %u ring_num %u msi->data %u msi_addr %llx",
  725. ring_type, ring_num, ring_params->msi_data,
  726. (uint64_t)ring_params->msi_addr);
  727. vector = msi_irq_start + (reg_msi_grp_num % msi_data_count);
  728. /*
  729. * During umac reset ppeds interrupts free is not called.
  730. * Avoid registering interrupts again.
  731. *
  732. */
  733. if (dp_check_umac_reset_in_progress(soc))
  734. goto configure_msi2;
  735. if (soc->arch_ops.dp_register_ppeds_interrupts)
  736. if (soc->arch_ops.dp_register_ppeds_interrupts(soc, srng,
  737. vector,
  738. ring_type,
  739. ring_num))
  740. return;
  741. configure_msi2:
  742. if (!nf_irq_support) {
  743. dp_srng_set_msi2_ring_params(soc, ring_params, 0, 0);
  744. return;
  745. }
  746. dp_srng_msi2_setup(soc, ring_params, ring_type, ring_num,
  747. nf_msi_grp_num);
  748. }
  749. /**
  750. * dp_srng_configure_pointer_update_thresholds() - Retrieve pointer
  751. * update threshold value from wlan_cfg_ctx
  752. * @soc: device handle
  753. * @ring_params: per ring specific parameters
  754. * @ring_type: Ring type
  755. * @ring_num: Ring number for a given ring type
  756. * @num_entries: number of entries to fill
  757. *
  758. * Fill the ring params with the pointer update threshold
  759. * configuration parameters available in wlan_cfg_ctx
  760. *
  761. * Return: None
  762. */
  763. static void
  764. dp_srng_configure_pointer_update_thresholds(
  765. struct dp_soc *soc,
  766. struct hal_srng_params *ring_params,
  767. int ring_type, int ring_num,
  768. int num_entries)
  769. {
  770. if (ring_type == REO_DST) {
  771. ring_params->pointer_timer_threshold =
  772. wlan_cfg_get_pointer_timer_threshold_rx(
  773. soc->wlan_cfg_ctx);
  774. ring_params->pointer_num_threshold =
  775. wlan_cfg_get_pointer_num_threshold_rx(
  776. soc->wlan_cfg_ctx);
  777. }
  778. }
  779. #ifdef WLAN_DP_PER_RING_TYPE_CONFIG
  780. /**
  781. * dp_srng_configure_interrupt_thresholds() - Retrieve interrupt
  782. * threshold values from the wlan_srng_cfg table for each ring type
  783. * @soc: device handle
  784. * @ring_params: per ring specific parameters
  785. * @ring_type: Ring type
  786. * @ring_num: Ring number for a given ring type
  787. * @num_entries: number of entries to fill
  788. *
  789. * Fill the ring params with the interrupt threshold
  790. * configuration parameters available in the per ring type wlan_srng_cfg
  791. * table.
  792. *
  793. * Return: None
  794. */
  795. static void
  796. dp_srng_configure_interrupt_thresholds(struct dp_soc *soc,
  797. struct hal_srng_params *ring_params,
  798. int ring_type, int ring_num,
  799. int num_entries)
  800. {
  801. uint8_t wbm2_sw_rx_rel_ring_id;
  802. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc->wlan_cfg_ctx);
  803. if (ring_type == REO_DST) {
  804. ring_params->intr_timer_thres_us =
  805. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  806. ring_params->intr_batch_cntr_thres_entries =
  807. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  808. } else if (ring_type == WBM2SW_RELEASE &&
  809. (ring_num == wbm2_sw_rx_rel_ring_id)) {
  810. ring_params->intr_timer_thres_us =
  811. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  812. ring_params->intr_batch_cntr_thres_entries =
  813. wlan_cfg_get_int_batch_threshold_other(soc->wlan_cfg_ctx);
  814. } else {
  815. ring_params->intr_timer_thres_us =
  816. soc->wlan_srng_cfg[ring_type].timer_threshold;
  817. ring_params->intr_batch_cntr_thres_entries =
  818. soc->wlan_srng_cfg[ring_type].batch_count_threshold;
  819. }
  820. ring_params->low_threshold =
  821. soc->wlan_srng_cfg[ring_type].low_threshold;
  822. if (ring_params->low_threshold)
  823. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  824. dp_srng_configure_nf_interrupt_thresholds(soc, ring_params, ring_type);
  825. }
  826. #else
  827. static void
  828. dp_srng_configure_interrupt_thresholds(struct dp_soc *soc,
  829. struct hal_srng_params *ring_params,
  830. int ring_type, int ring_num,
  831. int num_entries)
  832. {
  833. uint8_t wbm2_sw_rx_rel_ring_id;
  834. bool rx_refill_lt_disable;
  835. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc->wlan_cfg_ctx);
  836. if (ring_type == REO_DST || ring_type == REO2PPE) {
  837. ring_params->intr_timer_thres_us =
  838. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  839. ring_params->intr_batch_cntr_thres_entries =
  840. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  841. } else if (ring_type == WBM2SW_RELEASE &&
  842. (ring_num < wbm2_sw_rx_rel_ring_id ||
  843. ring_num == WBM2SW_TXCOMP_RING4_NUM ||
  844. ring_num == WBM2_SW_PPE_REL_RING_ID)) {
  845. ring_params->intr_timer_thres_us =
  846. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  847. ring_params->intr_batch_cntr_thres_entries =
  848. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  849. } else if (ring_type == RXDMA_BUF) {
  850. rx_refill_lt_disable =
  851. wlan_cfg_get_dp_soc_rxdma_refill_lt_disable
  852. (soc->wlan_cfg_ctx);
  853. ring_params->intr_timer_thres_us =
  854. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  855. if (!rx_refill_lt_disable) {
  856. ring_params->low_threshold = num_entries >> 3;
  857. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  858. ring_params->intr_batch_cntr_thres_entries = 0;
  859. }
  860. } else {
  861. ring_params->intr_timer_thres_us =
  862. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  863. ring_params->intr_batch_cntr_thres_entries =
  864. wlan_cfg_get_int_batch_threshold_other(soc->wlan_cfg_ctx);
  865. }
  866. /* These rings donot require interrupt to host. Make them zero */
  867. switch (ring_type) {
  868. case REO_REINJECT:
  869. case REO_CMD:
  870. case TCL_DATA:
  871. case TCL_CMD_CREDIT:
  872. case TCL_STATUS:
  873. case WBM_IDLE_LINK:
  874. case SW2WBM_RELEASE:
  875. case SW2RXDMA_NEW:
  876. ring_params->intr_timer_thres_us = 0;
  877. ring_params->intr_batch_cntr_thres_entries = 0;
  878. break;
  879. case PPE2TCL:
  880. ring_params->intr_timer_thres_us =
  881. wlan_cfg_get_int_timer_threshold_ppe2tcl(soc->wlan_cfg_ctx);
  882. ring_params->intr_batch_cntr_thres_entries =
  883. wlan_cfg_get_int_batch_threshold_ppe2tcl(soc->wlan_cfg_ctx);
  884. break;
  885. }
  886. /* Enable low threshold interrupts for rx buffer rings (regular and
  887. * monitor buffer rings.
  888. * TODO: See if this is required for any other ring
  889. */
  890. if ((ring_type == RXDMA_MONITOR_BUF) ||
  891. (ring_type == RXDMA_MONITOR_STATUS ||
  892. (ring_type == TX_MONITOR_BUF))) {
  893. /* TODO: Setting low threshold to 1/8th of ring size
  894. * see if this needs to be configurable
  895. */
  896. ring_params->low_threshold = num_entries >> 3;
  897. ring_params->intr_timer_thres_us =
  898. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  899. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  900. ring_params->intr_batch_cntr_thres_entries = 0;
  901. }
  902. /* During initialisation monitor rings are only filled with
  903. * MON_BUF_MIN_ENTRIES entries. So low threshold needs to be set to
  904. * a value less than that. Low threshold value is reconfigured again
  905. * to 1/8th of the ring size when monitor vap is created.
  906. */
  907. if (ring_type == RXDMA_MONITOR_BUF)
  908. ring_params->low_threshold = MON_BUF_MIN_ENTRIES >> 1;
  909. /* In case of PCI chipsets, we dont have PPDU end interrupts,
  910. * so MONITOR STATUS ring is reaped by receiving MSI from srng.
  911. * Keep batch threshold as 8 so that interrupt is received for
  912. * every 4 packets in MONITOR_STATUS ring
  913. */
  914. if ((ring_type == RXDMA_MONITOR_STATUS) &&
  915. (soc->intr_mode == DP_INTR_MSI))
  916. ring_params->intr_batch_cntr_thres_entries = 4;
  917. }
  918. #endif
  919. #ifdef DISABLE_MON_RING_MSI_CFG
  920. /**
  921. * dp_skip_msi_cfg() - Check if msi cfg has to be skipped for ring_type
  922. * @soc: DP SoC context
  923. * @ring_type: sring type
  924. *
  925. * Return: True if msi cfg should be skipped for srng type else false
  926. */
  927. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  928. {
  929. if (ring_type == RXDMA_MONITOR_STATUS)
  930. return true;
  931. return false;
  932. }
  933. #else
  934. #ifdef DP_CON_MON_MSI_ENABLED
  935. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  936. {
  937. if (soc->cdp_soc.ol_ops->get_con_mode &&
  938. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE) {
  939. if (ring_type == REO_DST || ring_type == RXDMA_DST)
  940. return true;
  941. } else if (ring_type == RXDMA_MONITOR_STATUS &&
  942. !wlan_cfg_get_local_pkt_capture(soc->wlan_cfg_ctx)) {
  943. return true;
  944. }
  945. return false;
  946. }
  947. #else
  948. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  949. {
  950. return false;
  951. }
  952. #endif /* DP_CON_MON_MSI_ENABLED */
  953. #endif /* DISABLE_MON_RING_MSI_CFG */
  954. QDF_STATUS dp_srng_init_idx(struct dp_soc *soc, struct dp_srng *srng,
  955. int ring_type, int ring_num, int mac_id,
  956. uint32_t idx)
  957. {
  958. bool idle_check;
  959. hal_soc_handle_t hal_soc = soc->hal_soc;
  960. struct hal_srng_params ring_params;
  961. if (srng->hal_srng) {
  962. dp_init_err("%pK: Ring type: %d, num:%d is already initialized",
  963. soc, ring_type, ring_num);
  964. return QDF_STATUS_SUCCESS;
  965. }
  966. /* memset the srng ring to zero */
  967. qdf_mem_zero(srng->base_vaddr_unaligned, srng->alloc_size);
  968. qdf_mem_zero(&ring_params, sizeof(struct hal_srng_params));
  969. ring_params.ring_base_paddr = srng->base_paddr_aligned;
  970. ring_params.ring_base_vaddr = srng->base_vaddr_aligned;
  971. ring_params.num_entries = srng->num_entries;
  972. dp_info("Ring type: %d, num:%d vaddr %pK paddr %pK entries %u",
  973. ring_type, ring_num,
  974. (void *)ring_params.ring_base_vaddr,
  975. (void *)ring_params.ring_base_paddr,
  976. ring_params.num_entries);
  977. if (soc->intr_mode == DP_INTR_MSI && !dp_skip_msi_cfg(soc, ring_type)) {
  978. dp_srng_msi_setup(soc, srng, &ring_params, ring_type, ring_num);
  979. dp_verbose_debug("Using MSI for ring_type: %d, ring_num %d",
  980. ring_type, ring_num);
  981. } else {
  982. ring_params.msi_data = 0;
  983. ring_params.msi_addr = 0;
  984. dp_srng_set_msi2_ring_params(soc, &ring_params, 0, 0);
  985. dp_verbose_debug("Skipping MSI for ring_type: %d, ring_num %d",
  986. ring_type, ring_num);
  987. }
  988. dp_srng_configure_interrupt_thresholds(soc, &ring_params,
  989. ring_type, ring_num,
  990. srng->num_entries);
  991. dp_srng_set_nf_thresholds(soc, srng, &ring_params);
  992. dp_srng_configure_pointer_update_thresholds(soc, &ring_params,
  993. ring_type, ring_num,
  994. srng->num_entries);
  995. if (srng->cached)
  996. ring_params.flags |= HAL_SRNG_CACHED_DESC;
  997. idle_check = dp_check_umac_reset_in_progress(soc);
  998. srng->hal_srng = hal_srng_setup_idx(hal_soc, ring_type, ring_num,
  999. mac_id, &ring_params, idle_check,
  1000. idx);
  1001. if (!srng->hal_srng) {
  1002. dp_srng_free(soc, srng);
  1003. return QDF_STATUS_E_FAILURE;
  1004. }
  1005. return QDF_STATUS_SUCCESS;
  1006. }
  1007. qdf_export_symbol(dp_srng_init_idx);
  1008. static int dp_process_rxdma_dst_ring(struct dp_soc *soc,
  1009. struct dp_intr *int_ctx,
  1010. int mac_for_pdev,
  1011. int total_budget)
  1012. {
  1013. uint32_t target_type;
  1014. target_type = hal_get_target_type(soc->hal_soc);
  1015. if (target_type == TARGET_TYPE_QCN9160)
  1016. return dp_monitor_process(soc, int_ctx,
  1017. mac_for_pdev, total_budget);
  1018. else
  1019. return dp_rxdma_err_process(int_ctx, soc, mac_for_pdev,
  1020. total_budget);
  1021. }
  1022. /**
  1023. * dp_process_lmac_rings() - Process LMAC rings
  1024. * @int_ctx: interrupt context
  1025. * @total_budget: budget of work which can be done
  1026. *
  1027. * Return: work done
  1028. */
  1029. static int dp_process_lmac_rings(struct dp_intr *int_ctx, int total_budget)
  1030. {
  1031. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1032. struct dp_soc *soc = int_ctx->soc;
  1033. uint32_t remaining_quota = total_budget;
  1034. struct dp_pdev *pdev = NULL;
  1035. uint32_t work_done = 0;
  1036. int budget = total_budget;
  1037. int ring = 0;
  1038. bool rx_refill_lt_disable;
  1039. rx_refill_lt_disable =
  1040. wlan_cfg_get_dp_soc_rxdma_refill_lt_disable(soc->wlan_cfg_ctx);
  1041. /* Process LMAC interrupts */
  1042. for (ring = 0 ; ring < MAX_NUM_LMAC_HW; ring++) {
  1043. int mac_for_pdev = ring;
  1044. pdev = dp_get_pdev_for_lmac_id(soc, mac_for_pdev);
  1045. if (!pdev)
  1046. continue;
  1047. if (int_ctx->rx_mon_ring_mask & (1 << mac_for_pdev)) {
  1048. work_done = dp_monitor_process(soc, int_ctx,
  1049. mac_for_pdev,
  1050. remaining_quota);
  1051. if (work_done)
  1052. intr_stats->num_rx_mon_ring_masks++;
  1053. budget -= work_done;
  1054. if (budget <= 0)
  1055. goto budget_done;
  1056. remaining_quota = budget;
  1057. }
  1058. if (int_ctx->tx_mon_ring_mask & (1 << mac_for_pdev)) {
  1059. work_done = dp_tx_mon_process(soc, int_ctx,
  1060. mac_for_pdev,
  1061. remaining_quota);
  1062. if (work_done)
  1063. intr_stats->num_tx_mon_ring_masks++;
  1064. budget -= work_done;
  1065. if (budget <= 0)
  1066. goto budget_done;
  1067. remaining_quota = budget;
  1068. }
  1069. if (int_ctx->rxdma2host_ring_mask &
  1070. (1 << mac_for_pdev)) {
  1071. work_done = dp_process_rxdma_dst_ring(soc, int_ctx,
  1072. mac_for_pdev,
  1073. remaining_quota);
  1074. if (work_done)
  1075. intr_stats->num_rxdma2host_ring_masks++;
  1076. budget -= work_done;
  1077. if (budget <= 0)
  1078. goto budget_done;
  1079. remaining_quota = budget;
  1080. }
  1081. if (int_ctx->host2rxdma_ring_mask & (1 << mac_for_pdev)) {
  1082. union dp_rx_desc_list_elem_t *desc_list = NULL;
  1083. union dp_rx_desc_list_elem_t *tail = NULL;
  1084. struct dp_srng *rx_refill_buf_ring;
  1085. struct rx_desc_pool *rx_desc_pool;
  1086. rx_desc_pool = &soc->rx_desc_buf[mac_for_pdev];
  1087. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx))
  1088. rx_refill_buf_ring =
  1089. &soc->rx_refill_buf_ring[mac_for_pdev];
  1090. else
  1091. rx_refill_buf_ring =
  1092. &soc->rx_refill_buf_ring[pdev->lmac_id];
  1093. intr_stats->num_host2rxdma_ring_masks++;
  1094. if (!rx_refill_lt_disable)
  1095. dp_rx_buffers_lt_replenish_simple(soc,
  1096. mac_for_pdev,
  1097. rx_refill_buf_ring,
  1098. rx_desc_pool,
  1099. 0,
  1100. &desc_list,
  1101. &tail);
  1102. }
  1103. }
  1104. if (int_ctx->host2rxdma_mon_ring_mask)
  1105. dp_rx_mon_buf_refill(int_ctx);
  1106. if (int_ctx->host2txmon_ring_mask)
  1107. dp_tx_mon_buf_refill(int_ctx);
  1108. budget_done:
  1109. return total_budget - budget;
  1110. }
  1111. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1112. /**
  1113. * dp_service_near_full_srngs() - Bottom half handler to process the near
  1114. * full IRQ on a SRNG
  1115. * @dp_ctx: Datapath SoC handle
  1116. * @dp_budget: Number of SRNGs which can be processed in a single attempt
  1117. * without rescheduling
  1118. * @cpu: cpu id
  1119. *
  1120. * Return: remaining budget/quota for the soc device
  1121. */
  1122. static
  1123. uint32_t dp_service_near_full_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1124. {
  1125. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1126. struct dp_soc *soc = int_ctx->soc;
  1127. /*
  1128. * dp_service_near_full_srngs arch ops should be initialized always
  1129. * if the NEAR FULL IRQ feature is enabled.
  1130. */
  1131. return soc->arch_ops.dp_service_near_full_srngs(soc, int_ctx,
  1132. dp_budget);
  1133. }
  1134. #endif
  1135. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1136. uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1137. {
  1138. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1139. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1140. struct dp_soc *soc = int_ctx->soc;
  1141. int ring = 0;
  1142. int index;
  1143. uint32_t work_done = 0;
  1144. int budget = dp_budget;
  1145. uint32_t remaining_quota = dp_budget;
  1146. uint8_t tx_mask = 0;
  1147. uint8_t rx_mask = 0;
  1148. uint8_t rx_err_mask = 0;
  1149. uint8_t rx_wbm_rel_mask = 0;
  1150. uint8_t reo_status_mask = 0;
  1151. qdf_atomic_set_bit(cpu, &soc->service_rings_running);
  1152. tx_mask = int_ctx->tx_ring_mask;
  1153. rx_mask = int_ctx->rx_ring_mask;
  1154. rx_err_mask = int_ctx->rx_err_ring_mask;
  1155. rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  1156. reo_status_mask = int_ctx->reo_status_ring_mask;
  1157. dp_verbose_debug("tx %x rx %x rx_err %x rx_wbm_rel %x reo_status %x rx_mon_ring %x host2rxdma %x rxdma2host %x",
  1158. tx_mask, rx_mask, rx_err_mask, rx_wbm_rel_mask,
  1159. reo_status_mask,
  1160. int_ctx->rx_mon_ring_mask,
  1161. int_ctx->host2rxdma_ring_mask,
  1162. int_ctx->rxdma2host_ring_mask);
  1163. /* Process Tx completion interrupts first to return back buffers */
  1164. for (index = 0; index < soc->num_tx_comp_rings; index++) {
  1165. if (!(1 << wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, index) & tx_mask))
  1166. continue;
  1167. work_done = dp_tx_comp_handler(int_ctx,
  1168. soc,
  1169. soc->tx_comp_ring[index].hal_srng,
  1170. index, remaining_quota);
  1171. if (work_done) {
  1172. intr_stats->num_tx_ring_masks[index]++;
  1173. dp_verbose_debug("tx mask 0x%x index %d, budget %d, work_done %d",
  1174. tx_mask, index, budget,
  1175. work_done);
  1176. }
  1177. budget -= work_done;
  1178. if (budget <= 0)
  1179. goto budget_done;
  1180. remaining_quota = budget;
  1181. }
  1182. /* Process REO Exception ring interrupt */
  1183. if (rx_err_mask) {
  1184. work_done = dp_rx_err_process(int_ctx, soc,
  1185. soc->reo_exception_ring.hal_srng,
  1186. remaining_quota);
  1187. if (work_done) {
  1188. intr_stats->num_rx_err_ring_masks++;
  1189. dp_verbose_debug("REO Exception Ring: work_done %d budget %d",
  1190. work_done, budget);
  1191. }
  1192. budget -= work_done;
  1193. if (budget <= 0) {
  1194. goto budget_done;
  1195. }
  1196. remaining_quota = budget;
  1197. }
  1198. /* Process Rx WBM release ring interrupt */
  1199. if (rx_wbm_rel_mask) {
  1200. work_done = dp_rx_wbm_err_process(int_ctx, soc,
  1201. soc->rx_rel_ring.hal_srng,
  1202. remaining_quota);
  1203. if (work_done) {
  1204. intr_stats->num_rx_wbm_rel_ring_masks++;
  1205. dp_verbose_debug("WBM Release Ring: work_done %d budget %d",
  1206. work_done, budget);
  1207. }
  1208. budget -= work_done;
  1209. if (budget <= 0) {
  1210. goto budget_done;
  1211. }
  1212. remaining_quota = budget;
  1213. }
  1214. /* Process Rx interrupts */
  1215. if (rx_mask) {
  1216. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1217. if (!(rx_mask & (1 << ring)))
  1218. continue;
  1219. work_done = soc->arch_ops.dp_rx_process(int_ctx,
  1220. soc->reo_dest_ring[ring].hal_srng,
  1221. ring,
  1222. remaining_quota);
  1223. if (work_done) {
  1224. intr_stats->num_rx_ring_masks[ring]++;
  1225. dp_verbose_debug("rx mask 0x%x ring %d, work_done %d budget %d",
  1226. rx_mask, ring,
  1227. work_done, budget);
  1228. budget -= work_done;
  1229. if (budget <= 0)
  1230. goto budget_done;
  1231. remaining_quota = budget;
  1232. }
  1233. }
  1234. }
  1235. if (reo_status_mask) {
  1236. if (dp_reo_status_ring_handler(int_ctx, soc))
  1237. int_ctx->intr_stats.num_reo_status_ring_masks++;
  1238. }
  1239. if (qdf_unlikely(!dp_monitor_is_vdev_timer_running(soc))) {
  1240. work_done = dp_process_lmac_rings(int_ctx, remaining_quota);
  1241. if (work_done) {
  1242. budget -= work_done;
  1243. if (budget <= 0)
  1244. goto budget_done;
  1245. remaining_quota = budget;
  1246. }
  1247. }
  1248. qdf_lro_flush(int_ctx->lro_ctx);
  1249. intr_stats->num_masks++;
  1250. budget_done:
  1251. qdf_atomic_clear_bit(cpu, &soc->service_rings_running);
  1252. if (soc->notify_fw_callback)
  1253. soc->notify_fw_callback(soc);
  1254. return dp_budget - budget;
  1255. }
  1256. #else /* QCA_HOST_MODE_WIFI_DISABLED */
  1257. uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1258. {
  1259. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1260. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1261. struct dp_soc *soc = int_ctx->soc;
  1262. uint32_t remaining_quota = dp_budget;
  1263. uint32_t work_done = 0;
  1264. int budget = dp_budget;
  1265. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  1266. if (reo_status_mask) {
  1267. if (dp_reo_status_ring_handler(int_ctx, soc))
  1268. int_ctx->intr_stats.num_reo_status_ring_masks++;
  1269. }
  1270. if (qdf_unlikely(!dp_monitor_is_vdev_timer_running(soc))) {
  1271. work_done = dp_process_lmac_rings(int_ctx, remaining_quota);
  1272. if (work_done) {
  1273. budget -= work_done;
  1274. if (budget <= 0)
  1275. goto budget_done;
  1276. remaining_quota = budget;
  1277. }
  1278. }
  1279. qdf_lro_flush(int_ctx->lro_ctx);
  1280. intr_stats->num_masks++;
  1281. budget_done:
  1282. return dp_budget - budget;
  1283. }
  1284. #endif /* QCA_HOST_MODE_WIFI_DISABLED */
  1285. QDF_STATUS dp_soc_attach_poll(struct cdp_soc_t *txrx_soc)
  1286. {
  1287. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1288. int i;
  1289. int lmac_id = 0;
  1290. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1291. sizeof(soc->mon_intr_id_lmac_map), DP_MON_INVALID_LMAC_ID);
  1292. soc->intr_mode = DP_INTR_POLL;
  1293. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1294. soc->intr_ctx[i].dp_intr_id = i;
  1295. soc->intr_ctx[i].tx_ring_mask =
  1296. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1297. soc->intr_ctx[i].rx_ring_mask =
  1298. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1299. soc->intr_ctx[i].rx_mon_ring_mask =
  1300. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1301. soc->intr_ctx[i].rx_err_ring_mask =
  1302. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1303. soc->intr_ctx[i].rx_wbm_rel_ring_mask =
  1304. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1305. soc->intr_ctx[i].reo_status_ring_mask =
  1306. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1307. soc->intr_ctx[i].rxdma2host_ring_mask =
  1308. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1309. soc->intr_ctx[i].soc = soc;
  1310. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1311. if (dp_is_mon_mask_valid(soc, &soc->intr_ctx[i])) {
  1312. hif_event_history_init(soc->hif_handle, i);
  1313. soc->mon_intr_id_lmac_map[lmac_id] = i;
  1314. lmac_id++;
  1315. }
  1316. }
  1317. qdf_timer_init(soc->osdev, &soc->int_timer,
  1318. dp_interrupt_timer, (void *)soc,
  1319. QDF_TIMER_TYPE_WAKE_APPS);
  1320. return QDF_STATUS_SUCCESS;
  1321. }
  1322. void dp_soc_set_interrupt_mode(struct dp_soc *soc)
  1323. {
  1324. uint32_t msi_base_data, msi_vector_start;
  1325. int msi_vector_count, ret;
  1326. soc->intr_mode = DP_INTR_INTEGRATED;
  1327. if (!(soc->wlan_cfg_ctx->napi_enabled) ||
  1328. (dp_is_monitor_mode_using_poll(soc) &&
  1329. soc->cdp_soc.ol_ops->get_con_mode &&
  1330. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)) {
  1331. soc->intr_mode = DP_INTR_POLL;
  1332. } else {
  1333. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  1334. &msi_vector_count,
  1335. &msi_base_data,
  1336. &msi_vector_start);
  1337. if (ret)
  1338. return;
  1339. soc->intr_mode = DP_INTR_MSI;
  1340. }
  1341. }
  1342. #ifdef QCA_SUPPORT_LEGACY_INTERRUPTS
  1343. /**
  1344. * dp_soc_interrupt_map_calculate_wifi3_pci_legacy() -
  1345. * Calculate interrupt map for legacy interrupts
  1346. * @soc: DP soc handle
  1347. * @intr_ctx_num: Interrupt context number
  1348. * @irq_id_map: IRQ map
  1349. * @num_irq_r: Number of interrupts assigned for this context
  1350. *
  1351. * Return: void
  1352. */
  1353. static void dp_soc_interrupt_map_calculate_wifi3_pci_legacy(struct dp_soc *soc,
  1354. int intr_ctx_num,
  1355. int *irq_id_map,
  1356. int *num_irq_r)
  1357. {
  1358. int j;
  1359. int num_irq = 0;
  1360. int tx_mask = wlan_cfg_get_tx_ring_mask(
  1361. soc->wlan_cfg_ctx, intr_ctx_num);
  1362. int rx_mask = wlan_cfg_get_rx_ring_mask(
  1363. soc->wlan_cfg_ctx, intr_ctx_num);
  1364. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  1365. soc->wlan_cfg_ctx, intr_ctx_num);
  1366. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1367. soc->wlan_cfg_ctx, intr_ctx_num);
  1368. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1369. soc->wlan_cfg_ctx, intr_ctx_num);
  1370. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1371. soc->wlan_cfg_ctx, intr_ctx_num);
  1372. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1373. soc->wlan_cfg_ctx, intr_ctx_num);
  1374. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1375. soc->wlan_cfg_ctx, intr_ctx_num);
  1376. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1377. soc->wlan_cfg_ctx, intr_ctx_num);
  1378. int host2txmon_ring_mask = wlan_cfg_get_host2txmon_ring_mask(
  1379. soc->wlan_cfg_ctx, intr_ctx_num);
  1380. int txmon2host_mon_ring_mask = wlan_cfg_get_tx_mon_ring_mask(
  1381. soc->wlan_cfg_ctx, intr_ctx_num);
  1382. soc->intr_mode = DP_INTR_LEGACY_VIRTUAL_IRQ;
  1383. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  1384. if (tx_mask & (1 << j))
  1385. irq_id_map[num_irq++] = (wbm2sw0_release - j);
  1386. if (rx_mask & (1 << j))
  1387. irq_id_map[num_irq++] = (reo2sw1_intr - j);
  1388. if (rx_mon_mask & (1 << j))
  1389. irq_id_map[num_irq++] = (rxmon2sw_p0_dest0 - j);
  1390. if (rx_err_ring_mask & (1 << j))
  1391. irq_id_map[num_irq++] = (reo2sw0_intr - j);
  1392. if (rx_wbm_rel_ring_mask & (1 << j))
  1393. irq_id_map[num_irq++] = (wbm2sw5_release - j);
  1394. if (reo_status_ring_mask & (1 << j))
  1395. irq_id_map[num_irq++] = (reo_status - j);
  1396. if (rxdma2host_ring_mask & (1 << j))
  1397. irq_id_map[num_irq++] = (rxdma2sw_dst_ring0 - j);
  1398. if (host2rxdma_ring_mask & (1 << j))
  1399. irq_id_map[num_irq++] = (sw2rxdma_0 - j);
  1400. if (host2rxdma_mon_ring_mask & (1 << j))
  1401. irq_id_map[num_irq++] = (sw2rxmon_src_ring - j);
  1402. if (host2txmon_ring_mask & (1 << j))
  1403. irq_id_map[num_irq++] = sw2txmon_src_ring;
  1404. if (txmon2host_mon_ring_mask & (1 << j))
  1405. irq_id_map[num_irq++] = (txmon2sw_p0_dest0 - j);
  1406. }
  1407. *num_irq_r = num_irq;
  1408. }
  1409. #else
  1410. static void dp_soc_interrupt_map_calculate_wifi3_pci_legacy(struct dp_soc *soc,
  1411. int intr_ctx_num,
  1412. int *irq_id_map,
  1413. int *num_irq_r)
  1414. {
  1415. }
  1416. #endif
  1417. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  1418. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  1419. {
  1420. int j;
  1421. int num_irq = 0;
  1422. int tx_mask =
  1423. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1424. int rx_mask =
  1425. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1426. int rx_mon_mask =
  1427. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1428. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1429. soc->wlan_cfg_ctx, intr_ctx_num);
  1430. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1431. soc->wlan_cfg_ctx, intr_ctx_num);
  1432. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1433. soc->wlan_cfg_ctx, intr_ctx_num);
  1434. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1435. soc->wlan_cfg_ctx, intr_ctx_num);
  1436. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1437. soc->wlan_cfg_ctx, intr_ctx_num);
  1438. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1439. soc->wlan_cfg_ctx, intr_ctx_num);
  1440. int host2txmon_ring_mask = wlan_cfg_get_host2txmon_ring_mask(
  1441. soc->wlan_cfg_ctx, intr_ctx_num);
  1442. int txmon2host_mon_ring_mask = wlan_cfg_get_tx_mon_ring_mask(
  1443. soc->wlan_cfg_ctx, intr_ctx_num);
  1444. soc->intr_mode = DP_INTR_INTEGRATED;
  1445. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  1446. if (tx_mask & (1 << j)) {
  1447. irq_id_map[num_irq++] =
  1448. (wbm2host_tx_completions_ring1 - j);
  1449. }
  1450. if (rx_mask & (1 << j)) {
  1451. irq_id_map[num_irq++] =
  1452. (reo2host_destination_ring1 - j);
  1453. }
  1454. if (rxdma2host_ring_mask & (1 << j)) {
  1455. irq_id_map[num_irq++] =
  1456. rxdma2host_destination_ring_mac1 - j;
  1457. }
  1458. if (host2rxdma_ring_mask & (1 << j)) {
  1459. irq_id_map[num_irq++] =
  1460. host2rxdma_host_buf_ring_mac1 - j;
  1461. }
  1462. if (host2rxdma_mon_ring_mask & (1 << j)) {
  1463. irq_id_map[num_irq++] =
  1464. host2rxdma_monitor_ring1 - j;
  1465. }
  1466. if (rx_mon_mask & (1 << j)) {
  1467. irq_id_map[num_irq++] =
  1468. ppdu_end_interrupts_mac1 - j;
  1469. irq_id_map[num_irq++] =
  1470. rxdma2host_monitor_status_ring_mac1 - j;
  1471. irq_id_map[num_irq++] =
  1472. rxdma2host_monitor_destination_mac1 - j;
  1473. }
  1474. if (rx_wbm_rel_ring_mask & (1 << j))
  1475. irq_id_map[num_irq++] = wbm2host_rx_release;
  1476. if (rx_err_ring_mask & (1 << j))
  1477. irq_id_map[num_irq++] = reo2host_exception;
  1478. if (reo_status_ring_mask & (1 << j))
  1479. irq_id_map[num_irq++] = reo2host_status;
  1480. if (host2txmon_ring_mask & (1 << j))
  1481. irq_id_map[num_irq++] = host2tx_monitor_ring1;
  1482. if (txmon2host_mon_ring_mask & (1 << j)) {
  1483. irq_id_map[num_irq++] =
  1484. (txmon2host_monitor_destination_mac1 - j);
  1485. }
  1486. }
  1487. *num_irq_r = num_irq;
  1488. }
  1489. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  1490. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  1491. int msi_vector_count, int msi_vector_start)
  1492. {
  1493. int tx_mask = wlan_cfg_get_tx_ring_mask(
  1494. soc->wlan_cfg_ctx, intr_ctx_num);
  1495. int rx_mask = wlan_cfg_get_rx_ring_mask(
  1496. soc->wlan_cfg_ctx, intr_ctx_num);
  1497. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  1498. soc->wlan_cfg_ctx, intr_ctx_num);
  1499. int tx_mon_mask = wlan_cfg_get_tx_mon_ring_mask(
  1500. soc->wlan_cfg_ctx, intr_ctx_num);
  1501. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1502. soc->wlan_cfg_ctx, intr_ctx_num);
  1503. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1504. soc->wlan_cfg_ctx, intr_ctx_num);
  1505. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1506. soc->wlan_cfg_ctx, intr_ctx_num);
  1507. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1508. soc->wlan_cfg_ctx, intr_ctx_num);
  1509. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1510. soc->wlan_cfg_ctx, intr_ctx_num);
  1511. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1512. soc->wlan_cfg_ctx, intr_ctx_num);
  1513. int rx_near_full_grp_1_mask =
  1514. wlan_cfg_get_rx_near_full_grp_1_mask(soc->wlan_cfg_ctx,
  1515. intr_ctx_num);
  1516. int rx_near_full_grp_2_mask =
  1517. wlan_cfg_get_rx_near_full_grp_2_mask(soc->wlan_cfg_ctx,
  1518. intr_ctx_num);
  1519. int tx_ring_near_full_mask =
  1520. wlan_cfg_get_tx_ring_near_full_mask(soc->wlan_cfg_ctx,
  1521. intr_ctx_num);
  1522. int host2txmon_ring_mask =
  1523. wlan_cfg_get_host2txmon_ring_mask(soc->wlan_cfg_ctx,
  1524. intr_ctx_num);
  1525. unsigned int vector =
  1526. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  1527. int num_irq = 0;
  1528. soc->intr_mode = DP_INTR_MSI;
  1529. if (tx_mask | rx_mask | rx_mon_mask | tx_mon_mask | rx_err_ring_mask |
  1530. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask |
  1531. host2rxdma_ring_mask | host2rxdma_mon_ring_mask |
  1532. rx_near_full_grp_1_mask | rx_near_full_grp_2_mask |
  1533. tx_ring_near_full_mask | host2txmon_ring_mask)
  1534. irq_id_map[num_irq++] =
  1535. pld_get_msi_irq(soc->osdev->dev, vector);
  1536. *num_irq_r = num_irq;
  1537. }
  1538. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  1539. int *irq_id_map, int *num_irq)
  1540. {
  1541. int msi_vector_count, ret;
  1542. uint32_t msi_base_data, msi_vector_start;
  1543. if (pld_get_enable_intx(soc->osdev->dev)) {
  1544. return dp_soc_interrupt_map_calculate_wifi3_pci_legacy(soc,
  1545. intr_ctx_num, irq_id_map, num_irq);
  1546. }
  1547. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  1548. &msi_vector_count,
  1549. &msi_base_data,
  1550. &msi_vector_start);
  1551. if (ret)
  1552. return dp_soc_interrupt_map_calculate_integrated(soc,
  1553. intr_ctx_num, irq_id_map, num_irq);
  1554. else
  1555. dp_soc_interrupt_map_calculate_msi(soc,
  1556. intr_ctx_num, irq_id_map, num_irq,
  1557. msi_vector_count, msi_vector_start);
  1558. }
  1559. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1560. /**
  1561. * dp_soc_near_full_interrupt_attach() - Register handler for DP near fill irq
  1562. * @soc: DP soc handle
  1563. * @num_irq: IRQ number
  1564. * @irq_id_map: IRQ map
  1565. * @intr_id: interrupt context ID
  1566. *
  1567. * Return: 0 for success. nonzero for failure.
  1568. */
  1569. static inline int
  1570. dp_soc_near_full_interrupt_attach(struct dp_soc *soc, int num_irq,
  1571. int irq_id_map[], int intr_id)
  1572. {
  1573. return hif_register_ext_group(soc->hif_handle,
  1574. num_irq, irq_id_map,
  1575. dp_service_near_full_srngs,
  1576. &soc->intr_ctx[intr_id], "dp_nf_intr",
  1577. HIF_EXEC_NAPI_TYPE,
  1578. QCA_NAPI_DEF_SCALE_BIN_SHIFT);
  1579. }
  1580. #else
  1581. static inline int
  1582. dp_soc_near_full_interrupt_attach(struct dp_soc *soc, int num_irq,
  1583. int *irq_id_map, int intr_id)
  1584. {
  1585. return 0;
  1586. }
  1587. #endif
  1588. #ifdef DP_CON_MON_MSI_SKIP_SET
  1589. static inline bool dp_skip_rx_mon_ring_mask_set(struct dp_soc *soc)
  1590. {
  1591. return !!(soc->cdp_soc.ol_ops->get_con_mode() !=
  1592. QDF_GLOBAL_MONITOR_MODE &&
  1593. !wlan_cfg_get_local_pkt_capture(soc->wlan_cfg_ctx));
  1594. }
  1595. #else
  1596. static inline bool dp_skip_rx_mon_ring_mask_set(struct dp_soc *soc)
  1597. {
  1598. return false;
  1599. }
  1600. #endif
  1601. void dp_soc_interrupt_detach(struct cdp_soc_t *txrx_soc)
  1602. {
  1603. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1604. int i;
  1605. if (soc->intr_mode == DP_INTR_POLL) {
  1606. qdf_timer_free(&soc->int_timer);
  1607. } else {
  1608. hif_deconfigure_ext_group_interrupts(soc->hif_handle);
  1609. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1610. hif_deregister_exec_group(soc->hif_handle, "dp_nf_intr");
  1611. }
  1612. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1613. soc->intr_ctx[i].tx_ring_mask = 0;
  1614. soc->intr_ctx[i].rx_ring_mask = 0;
  1615. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1616. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1617. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1618. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1619. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  1620. soc->intr_ctx[i].host2rxdma_ring_mask = 0;
  1621. soc->intr_ctx[i].host2rxdma_mon_ring_mask = 0;
  1622. soc->intr_ctx[i].rx_near_full_grp_1_mask = 0;
  1623. soc->intr_ctx[i].rx_near_full_grp_2_mask = 0;
  1624. soc->intr_ctx[i].tx_ring_near_full_mask = 0;
  1625. soc->intr_ctx[i].tx_mon_ring_mask = 0;
  1626. soc->intr_ctx[i].host2txmon_ring_mask = 0;
  1627. soc->intr_ctx[i].umac_reset_intr_mask = 0;
  1628. hif_event_history_deinit(soc->hif_handle, i);
  1629. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1630. }
  1631. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1632. sizeof(soc->mon_intr_id_lmac_map),
  1633. DP_MON_INVALID_LMAC_ID);
  1634. }
  1635. QDF_STATUS dp_soc_interrupt_attach(struct cdp_soc_t *txrx_soc)
  1636. {
  1637. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1638. int i = 0;
  1639. int num_irq = 0;
  1640. int rx_err_ring_intr_ctxt_id = HIF_MAX_GROUP;
  1641. int lmac_id = 0;
  1642. int napi_scale;
  1643. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1644. sizeof(soc->mon_intr_id_lmac_map), DP_MON_INVALID_LMAC_ID);
  1645. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1646. int ret = 0;
  1647. /* Map of IRQ ids registered with one interrupt context */
  1648. int irq_id_map[HIF_MAX_GRP_IRQ];
  1649. int tx_mask =
  1650. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1651. int rx_mask =
  1652. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1653. int rx_mon_mask =
  1654. dp_soc_get_mon_mask_for_interrupt_mode(soc, i);
  1655. int tx_mon_ring_mask =
  1656. wlan_cfg_get_tx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1657. int rx_err_ring_mask =
  1658. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1659. int rx_wbm_rel_ring_mask =
  1660. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1661. int reo_status_ring_mask =
  1662. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1663. int rxdma2host_ring_mask =
  1664. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1665. int host2rxdma_ring_mask =
  1666. wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx, i);
  1667. int host2rxdma_mon_ring_mask =
  1668. wlan_cfg_get_host2rxdma_mon_ring_mask(
  1669. soc->wlan_cfg_ctx, i);
  1670. int rx_near_full_grp_1_mask =
  1671. wlan_cfg_get_rx_near_full_grp_1_mask(soc->wlan_cfg_ctx,
  1672. i);
  1673. int rx_near_full_grp_2_mask =
  1674. wlan_cfg_get_rx_near_full_grp_2_mask(soc->wlan_cfg_ctx,
  1675. i);
  1676. int tx_ring_near_full_mask =
  1677. wlan_cfg_get_tx_ring_near_full_mask(soc->wlan_cfg_ctx,
  1678. i);
  1679. int host2txmon_ring_mask =
  1680. wlan_cfg_get_host2txmon_ring_mask(soc->wlan_cfg_ctx, i);
  1681. int umac_reset_intr_mask =
  1682. wlan_cfg_get_umac_reset_intr_mask(soc->wlan_cfg_ctx, i);
  1683. if (dp_skip_rx_mon_ring_mask_set(soc))
  1684. rx_mon_mask = 0;
  1685. soc->intr_ctx[i].dp_intr_id = i;
  1686. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1687. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1688. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1689. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1690. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1691. soc->intr_ctx[i].host2rxdma_ring_mask = host2rxdma_ring_mask;
  1692. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1693. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1694. soc->intr_ctx[i].host2rxdma_mon_ring_mask =
  1695. host2rxdma_mon_ring_mask;
  1696. soc->intr_ctx[i].rx_near_full_grp_1_mask =
  1697. rx_near_full_grp_1_mask;
  1698. soc->intr_ctx[i].rx_near_full_grp_2_mask =
  1699. rx_near_full_grp_2_mask;
  1700. soc->intr_ctx[i].tx_ring_near_full_mask =
  1701. tx_ring_near_full_mask;
  1702. soc->intr_ctx[i].tx_mon_ring_mask = tx_mon_ring_mask;
  1703. soc->intr_ctx[i].host2txmon_ring_mask = host2txmon_ring_mask;
  1704. soc->intr_ctx[i].umac_reset_intr_mask = umac_reset_intr_mask;
  1705. soc->intr_ctx[i].soc = soc;
  1706. num_irq = 0;
  1707. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1708. &num_irq);
  1709. if (rx_near_full_grp_1_mask | rx_near_full_grp_2_mask |
  1710. tx_ring_near_full_mask) {
  1711. dp_soc_near_full_interrupt_attach(soc, num_irq,
  1712. irq_id_map, i);
  1713. } else {
  1714. napi_scale = wlan_cfg_get_napi_scale_factor(
  1715. soc->wlan_cfg_ctx);
  1716. if (!napi_scale)
  1717. napi_scale = QCA_NAPI_DEF_SCALE_BIN_SHIFT;
  1718. ret = hif_register_ext_group(soc->hif_handle,
  1719. num_irq, irq_id_map, dp_service_srngs,
  1720. &soc->intr_ctx[i], "dp_intr",
  1721. HIF_EXEC_NAPI_TYPE, napi_scale);
  1722. }
  1723. dp_debug(" int ctx %u num_irq %u irq_id_map %u %u",
  1724. i, num_irq, irq_id_map[0], irq_id_map[1]);
  1725. if (ret) {
  1726. dp_init_err("%pK: failed, ret = %d", soc, ret);
  1727. dp_soc_interrupt_detach(txrx_soc);
  1728. return QDF_STATUS_E_FAILURE;
  1729. }
  1730. hif_event_history_init(soc->hif_handle, i);
  1731. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1732. if (rx_err_ring_mask)
  1733. rx_err_ring_intr_ctxt_id = i;
  1734. if (dp_is_mon_mask_valid(soc, &soc->intr_ctx[i])) {
  1735. soc->mon_intr_id_lmac_map[lmac_id] = i;
  1736. lmac_id++;
  1737. }
  1738. }
  1739. hif_configure_ext_group_interrupts(soc->hif_handle);
  1740. if (rx_err_ring_intr_ctxt_id != HIF_MAX_GROUP)
  1741. hif_config_irq_clear_cpu_affinity(soc->hif_handle,
  1742. rx_err_ring_intr_ctxt_id, 0);
  1743. return QDF_STATUS_SUCCESS;
  1744. }
  1745. #define AVG_MAX_MPDUS_PER_TID 128
  1746. #define AVG_TIDS_PER_CLIENT 2
  1747. #define AVG_FLOWS_PER_TID 2
  1748. #define AVG_MSDUS_PER_FLOW 128
  1749. #define AVG_MSDUS_PER_MPDU 4
  1750. void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, uint32_t mac_id)
  1751. {
  1752. struct qdf_mem_multi_page_t *pages;
  1753. if (mac_id != WLAN_INVALID_PDEV_ID) {
  1754. pages = dp_monitor_get_link_desc_pages(soc, mac_id);
  1755. } else {
  1756. pages = &soc->link_desc_pages;
  1757. }
  1758. if (!pages) {
  1759. dp_err("can not get link desc pages");
  1760. QDF_ASSERT(0);
  1761. return;
  1762. }
  1763. if (pages->dma_pages) {
  1764. wlan_minidump_remove((void *)
  1765. pages->dma_pages->page_v_addr_start,
  1766. pages->num_pages * pages->page_size,
  1767. soc->ctrl_psoc,
  1768. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1769. "hw_link_desc_bank");
  1770. dp_desc_multi_pages_mem_free(soc, QDF_DP_HW_LINK_DESC_TYPE,
  1771. pages, 0, false);
  1772. }
  1773. }
  1774. qdf_export_symbol(dp_hw_link_desc_pool_banks_free);
  1775. QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, uint32_t mac_id)
  1776. {
  1777. hal_soc_handle_t hal_soc = soc->hal_soc;
  1778. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1779. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1780. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1781. uint32_t num_mpdus_per_link_desc = hal_num_mpdus_per_link_desc(hal_soc);
  1782. uint32_t num_msdus_per_link_desc = hal_num_msdus_per_link_desc(hal_soc);
  1783. uint32_t num_mpdu_links_per_queue_desc =
  1784. hal_num_mpdu_links_per_queue_desc(hal_soc);
  1785. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1786. uint32_t *total_link_descs, total_mem_size;
  1787. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1788. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1789. uint32_t num_entries;
  1790. struct qdf_mem_multi_page_t *pages;
  1791. struct dp_srng *dp_srng;
  1792. uint8_t minidump_str[MINIDUMP_STR_SIZE];
  1793. /* Only Tx queue descriptors are allocated from common link descriptor
  1794. * pool Rx queue descriptors are not included in this because (REO queue
  1795. * extension descriptors) they are expected to be allocated contiguously
  1796. * with REO queue descriptors
  1797. */
  1798. if (mac_id != WLAN_INVALID_PDEV_ID) {
  1799. pages = dp_monitor_get_link_desc_pages(soc, mac_id);
  1800. /* dp_monitor_get_link_desc_pages returns NULL only
  1801. * if monitor SOC is NULL
  1802. */
  1803. if (!pages) {
  1804. dp_err("can not get link desc pages");
  1805. QDF_ASSERT(0);
  1806. return QDF_STATUS_E_FAULT;
  1807. }
  1808. dp_srng = &soc->rxdma_mon_desc_ring[mac_id];
  1809. num_entries = dp_srng->alloc_size /
  1810. hal_srng_get_entrysize(soc->hal_soc,
  1811. RXDMA_MONITOR_DESC);
  1812. total_link_descs = dp_monitor_get_total_link_descs(soc, mac_id);
  1813. qdf_str_lcopy(minidump_str, "mon_link_desc_bank",
  1814. MINIDUMP_STR_SIZE);
  1815. } else {
  1816. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1817. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1818. num_mpdu_queue_descs = num_mpdu_link_descs /
  1819. num_mpdu_links_per_queue_desc;
  1820. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1821. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1822. num_msdus_per_link_desc;
  1823. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1824. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1825. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1826. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1827. pages = &soc->link_desc_pages;
  1828. total_link_descs = &soc->total_link_descs;
  1829. qdf_str_lcopy(minidump_str, "link_desc_bank",
  1830. MINIDUMP_STR_SIZE);
  1831. }
  1832. /* If link descriptor banks are allocated, return from here */
  1833. if (pages->num_pages)
  1834. return QDF_STATUS_SUCCESS;
  1835. /* Round up to power of 2 */
  1836. *total_link_descs = 1;
  1837. while (*total_link_descs < num_entries)
  1838. *total_link_descs <<= 1;
  1839. dp_init_info("%pK: total_link_descs: %u, link_desc_size: %d",
  1840. soc, *total_link_descs, link_desc_size);
  1841. total_mem_size = *total_link_descs * link_desc_size;
  1842. total_mem_size += link_desc_align;
  1843. dp_init_info("%pK: total_mem_size: %d",
  1844. soc, total_mem_size);
  1845. dp_set_max_page_size(pages, max_alloc_size);
  1846. dp_desc_multi_pages_mem_alloc(soc, QDF_DP_HW_LINK_DESC_TYPE,
  1847. pages,
  1848. link_desc_size,
  1849. *total_link_descs,
  1850. 0, false);
  1851. if (!pages->num_pages) {
  1852. dp_err("Multi page alloc fail for hw link desc pool");
  1853. return QDF_STATUS_E_FAULT;
  1854. }
  1855. wlan_minidump_log(pages->dma_pages->page_v_addr_start,
  1856. pages->num_pages * pages->page_size,
  1857. soc->ctrl_psoc,
  1858. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1859. "hw_link_desc_bank");
  1860. return QDF_STATUS_SUCCESS;
  1861. }
  1862. void dp_hw_link_desc_ring_free(struct dp_soc *soc)
  1863. {
  1864. uint32_t i;
  1865. uint32_t size = soc->wbm_idle_scatter_buf_size;
  1866. void *vaddr = soc->wbm_idle_link_ring.base_vaddr_unaligned;
  1867. qdf_dma_addr_t paddr;
  1868. if (soc->wbm_idle_scatter_buf_base_vaddr[0]) {
  1869. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1870. vaddr = soc->wbm_idle_scatter_buf_base_vaddr[i];
  1871. paddr = soc->wbm_idle_scatter_buf_base_paddr[i];
  1872. if (vaddr) {
  1873. qdf_mem_free_consistent(soc->osdev,
  1874. soc->osdev->dev,
  1875. size,
  1876. vaddr,
  1877. paddr,
  1878. 0);
  1879. vaddr = NULL;
  1880. }
  1881. }
  1882. } else {
  1883. wlan_minidump_remove(soc->wbm_idle_link_ring.base_vaddr_unaligned,
  1884. soc->wbm_idle_link_ring.alloc_size,
  1885. soc->ctrl_psoc,
  1886. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1887. "wbm_idle_link_ring");
  1888. dp_srng_free(soc, &soc->wbm_idle_link_ring);
  1889. }
  1890. }
  1891. QDF_STATUS dp_hw_link_desc_ring_alloc(struct dp_soc *soc)
  1892. {
  1893. uint32_t entry_size, i;
  1894. uint32_t total_mem_size;
  1895. qdf_dma_addr_t *baseaddr = NULL;
  1896. struct dp_srng *dp_srng;
  1897. uint32_t ring_type;
  1898. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1899. uint32_t tlds;
  1900. ring_type = WBM_IDLE_LINK;
  1901. dp_srng = &soc->wbm_idle_link_ring;
  1902. tlds = soc->total_link_descs;
  1903. entry_size = hal_srng_get_entrysize(soc->hal_soc, ring_type);
  1904. total_mem_size = entry_size * tlds;
  1905. if (total_mem_size <= max_alloc_size) {
  1906. if (dp_srng_alloc(soc, dp_srng, ring_type, tlds, 0)) {
  1907. dp_init_err("%pK: Link desc idle ring setup failed",
  1908. soc);
  1909. goto fail;
  1910. }
  1911. wlan_minidump_log(soc->wbm_idle_link_ring.base_vaddr_unaligned,
  1912. soc->wbm_idle_link_ring.alloc_size,
  1913. soc->ctrl_psoc,
  1914. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1915. "wbm_idle_link_ring");
  1916. } else {
  1917. uint32_t num_scatter_bufs;
  1918. uint32_t buf_size = 0;
  1919. soc->wbm_idle_scatter_buf_size =
  1920. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1921. hal_idle_scatter_buf_num_entries(
  1922. soc->hal_soc,
  1923. soc->wbm_idle_scatter_buf_size);
  1924. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1925. soc->hal_soc, total_mem_size,
  1926. soc->wbm_idle_scatter_buf_size);
  1927. if (num_scatter_bufs > MAX_IDLE_SCATTER_BUFS) {
  1928. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1929. FL("scatter bufs size out of bounds"));
  1930. goto fail;
  1931. }
  1932. for (i = 0; i < num_scatter_bufs; i++) {
  1933. baseaddr = &soc->wbm_idle_scatter_buf_base_paddr[i];
  1934. buf_size = soc->wbm_idle_scatter_buf_size;
  1935. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1936. qdf_mem_alloc_consistent(soc->osdev,
  1937. soc->osdev->dev,
  1938. buf_size,
  1939. baseaddr);
  1940. if (!soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1941. QDF_TRACE(QDF_MODULE_ID_DP,
  1942. QDF_TRACE_LEVEL_ERROR,
  1943. FL("Scatter lst memory alloc fail"));
  1944. goto fail;
  1945. }
  1946. }
  1947. soc->num_scatter_bufs = num_scatter_bufs;
  1948. }
  1949. return QDF_STATUS_SUCCESS;
  1950. fail:
  1951. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1952. void *vaddr = soc->wbm_idle_scatter_buf_base_vaddr[i];
  1953. qdf_dma_addr_t paddr = soc->wbm_idle_scatter_buf_base_paddr[i];
  1954. if (vaddr) {
  1955. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1956. soc->wbm_idle_scatter_buf_size,
  1957. vaddr,
  1958. paddr, 0);
  1959. vaddr = NULL;
  1960. }
  1961. }
  1962. return QDF_STATUS_E_NOMEM;
  1963. }
  1964. qdf_export_symbol(dp_hw_link_desc_pool_banks_alloc);
  1965. QDF_STATUS dp_hw_link_desc_ring_init(struct dp_soc *soc)
  1966. {
  1967. struct dp_srng *dp_srng = &soc->wbm_idle_link_ring;
  1968. if (dp_srng->base_vaddr_unaligned) {
  1969. if (dp_srng_init(soc, dp_srng, WBM_IDLE_LINK, 0, 0))
  1970. return QDF_STATUS_E_FAILURE;
  1971. }
  1972. return QDF_STATUS_SUCCESS;
  1973. }
  1974. void dp_hw_link_desc_ring_deinit(struct dp_soc *soc)
  1975. {
  1976. dp_srng_deinit(soc, &soc->wbm_idle_link_ring, WBM_IDLE_LINK, 0);
  1977. }
  1978. #ifdef IPA_OFFLOAD
  1979. #define USE_1_IPA_RX_REO_RING 1
  1980. #define USE_2_IPA_RX_REO_RINGS 2
  1981. #define REO_DST_RING_SIZE_QCA6290 1023
  1982. #ifndef CONFIG_WIFI_EMULATION_WIFI_3_0
  1983. #define REO_DST_RING_SIZE_QCA8074 1023
  1984. #define REO_DST_RING_SIZE_QCN9000 2048
  1985. #else
  1986. #define REO_DST_RING_SIZE_QCA8074 8
  1987. #define REO_DST_RING_SIZE_QCN9000 8
  1988. #endif /* CONFIG_WIFI_EMULATION_WIFI_3_0 */
  1989. #ifdef IPA_WDI3_TX_TWO_PIPES
  1990. #ifdef DP_MEMORY_OPT
  1991. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  1992. {
  1993. return dp_init_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  1994. }
  1995. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  1996. {
  1997. dp_deinit_tx_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  1998. }
  1999. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2000. {
  2001. return dp_alloc_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2002. }
  2003. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2004. {
  2005. dp_free_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2006. }
  2007. #else /* !DP_MEMORY_OPT */
  2008. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2009. {
  2010. return 0;
  2011. }
  2012. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2013. {
  2014. }
  2015. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2016. {
  2017. return 0;
  2018. }
  2019. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2020. {
  2021. }
  2022. #endif /* DP_MEMORY_OPT */
  2023. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2024. {
  2025. hal_tx_init_data_ring(soc->hal_soc,
  2026. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng);
  2027. }
  2028. #else /* !IPA_WDI3_TX_TWO_PIPES */
  2029. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2030. {
  2031. return 0;
  2032. }
  2033. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2034. {
  2035. }
  2036. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2037. {
  2038. return 0;
  2039. }
  2040. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2041. {
  2042. }
  2043. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2044. {
  2045. }
  2046. #endif /* IPA_WDI3_TX_TWO_PIPES */
  2047. #else
  2048. #define REO_DST_RING_SIZE_QCA6290 1024
  2049. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2050. {
  2051. return 0;
  2052. }
  2053. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2054. {
  2055. }
  2056. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2057. {
  2058. return 0;
  2059. }
  2060. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2061. {
  2062. }
  2063. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2064. {
  2065. }
  2066. #endif /* IPA_OFFLOAD */
  2067. /**
  2068. * dp_soc_reset_cpu_ring_map() - Reset cpu ring map
  2069. * @soc: Datapath soc handler
  2070. *
  2071. * This api resets the default cpu ring map
  2072. */
  2073. void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  2074. {
  2075. uint8_t i;
  2076. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2077. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  2078. switch (nss_config) {
  2079. case dp_nss_cfg_first_radio:
  2080. /*
  2081. * Setting Tx ring map for one nss offloaded radio
  2082. */
  2083. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  2084. break;
  2085. case dp_nss_cfg_second_radio:
  2086. /*
  2087. * Setting Tx ring for two nss offloaded radios
  2088. */
  2089. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  2090. break;
  2091. case dp_nss_cfg_dbdc:
  2092. /*
  2093. * Setting Tx ring map for 2 nss offloaded radios
  2094. */
  2095. soc->tx_ring_map[i] =
  2096. dp_cpu_ring_map[DP_NSS_DBDC_OFFLOADED_MAP][i];
  2097. break;
  2098. case dp_nss_cfg_dbtc:
  2099. /*
  2100. * Setting Tx ring map for 3 nss offloaded radios
  2101. */
  2102. soc->tx_ring_map[i] =
  2103. dp_cpu_ring_map[DP_NSS_DBTC_OFFLOADED_MAP][i];
  2104. break;
  2105. default:
  2106. dp_err("tx_ring_map failed due to invalid nss cfg");
  2107. break;
  2108. }
  2109. }
  2110. }
  2111. /**
  2112. * dp_soc_disable_unused_mac_intr_mask() - reset interrupt mask for
  2113. * unused WMAC hw rings
  2114. * @soc: DP Soc handle
  2115. * @mac_num: wmac num
  2116. *
  2117. * Return: Return void
  2118. */
  2119. static void dp_soc_disable_unused_mac_intr_mask(struct dp_soc *soc,
  2120. int mac_num)
  2121. {
  2122. uint8_t *grp_mask = NULL;
  2123. int group_number;
  2124. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  2125. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2126. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2127. group_number, 0x0);
  2128. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  2129. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2130. wlan_cfg_set_rx_mon_ring_mask(soc->wlan_cfg_ctx,
  2131. group_number, 0x0);
  2132. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  2133. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2134. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx,
  2135. group_number, 0x0);
  2136. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_mon_ring_mask[0];
  2137. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2138. wlan_cfg_set_host2rxdma_mon_ring_mask(soc->wlan_cfg_ctx,
  2139. group_number, 0x0);
  2140. }
  2141. #ifdef IPA_OFFLOAD
  2142. #ifdef IPA_WDI3_VLAN_SUPPORT
  2143. /**
  2144. * dp_soc_reset_ipa_vlan_intr_mask() - reset interrupt mask for IPA offloaded
  2145. * ring for vlan tagged traffic
  2146. * @soc: DP Soc handle
  2147. *
  2148. * Return: Return void
  2149. */
  2150. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2151. {
  2152. uint8_t *grp_mask = NULL;
  2153. int group_number, mask;
  2154. if (!wlan_ipa_is_vlan_enabled())
  2155. return;
  2156. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  2157. group_number = dp_srng_find_ring_in_mask(IPA_ALT_REO_DEST_RING_IDX, grp_mask);
  2158. if (group_number < 0) {
  2159. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2160. soc, REO_DST, IPA_ALT_REO_DEST_RING_IDX);
  2161. return;
  2162. }
  2163. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2164. /* reset the interrupt mask for offloaded ring */
  2165. mask &= (~(1 << IPA_ALT_REO_DEST_RING_IDX));
  2166. /*
  2167. * set the interrupt mask to zero for rx offloaded radio.
  2168. */
  2169. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2170. }
  2171. #else
  2172. inline
  2173. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2174. { }
  2175. #endif /* IPA_WDI3_VLAN_SUPPORT */
  2176. #else
  2177. inline
  2178. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2179. { }
  2180. #endif /* IPA_OFFLOAD */
  2181. /**
  2182. * dp_soc_reset_intr_mask() - reset interrupt mask
  2183. * @soc: DP Soc handle
  2184. *
  2185. * Return: Return void
  2186. */
  2187. void dp_soc_reset_intr_mask(struct dp_soc *soc)
  2188. {
  2189. uint8_t j;
  2190. uint8_t *grp_mask = NULL;
  2191. int group_number, mask, num_ring;
  2192. /* number of tx ring */
  2193. num_ring = soc->num_tcl_data_rings;
  2194. /*
  2195. * group mask for tx completion ring.
  2196. */
  2197. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  2198. /* loop and reset the mask for only offloaded ring */
  2199. for (j = 0; j < WLAN_CFG_NUM_TCL_DATA_RINGS; j++) {
  2200. /*
  2201. * Group number corresponding to tx offloaded ring.
  2202. */
  2203. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2204. if (group_number < 0) {
  2205. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2206. soc, WBM2SW_RELEASE, j);
  2207. continue;
  2208. }
  2209. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2210. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j) &&
  2211. (!mask)) {
  2212. continue;
  2213. }
  2214. /* reset the tx mask for offloaded ring */
  2215. mask &= (~(1 << j));
  2216. /*
  2217. * reset the interrupt mask for offloaded ring.
  2218. */
  2219. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2220. }
  2221. /* number of rx rings */
  2222. num_ring = soc->num_reo_dest_rings;
  2223. /*
  2224. * group mask for reo destination ring.
  2225. */
  2226. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  2227. /* loop and reset the mask for only offloaded ring */
  2228. for (j = 0; j < WLAN_CFG_NUM_REO_DEST_RING; j++) {
  2229. /*
  2230. * Group number corresponding to rx offloaded ring.
  2231. */
  2232. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2233. if (group_number < 0) {
  2234. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2235. soc, REO_DST, j);
  2236. continue;
  2237. }
  2238. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2239. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j) &&
  2240. (!mask)) {
  2241. continue;
  2242. }
  2243. /* reset the interrupt mask for offloaded ring */
  2244. mask &= (~(1 << j));
  2245. /*
  2246. * set the interrupt mask to zero for rx offloaded radio.
  2247. */
  2248. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2249. }
  2250. /*
  2251. * group mask for Rx buffer refill ring
  2252. */
  2253. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  2254. /* loop and reset the mask for only offloaded ring */
  2255. for (j = 0; j < MAX_PDEV_CNT; j++) {
  2256. int lmac_id = wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  2257. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF, j)) {
  2258. continue;
  2259. }
  2260. /*
  2261. * Group number corresponding to rx offloaded ring.
  2262. */
  2263. group_number = dp_srng_find_ring_in_mask(lmac_id, grp_mask);
  2264. if (group_number < 0) {
  2265. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2266. soc, REO_DST, lmac_id);
  2267. continue;
  2268. }
  2269. /* set the interrupt mask for offloaded ring */
  2270. mask = wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2271. group_number);
  2272. mask &= (~(1 << lmac_id));
  2273. /*
  2274. * set the interrupt mask to zero for rx offloaded radio.
  2275. */
  2276. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2277. group_number, mask);
  2278. }
  2279. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  2280. for (j = 0; j < num_ring; j++) {
  2281. if (!dp_soc_ring_if_nss_offloaded(soc, REO_EXCEPTION, j)) {
  2282. continue;
  2283. }
  2284. /*
  2285. * Group number corresponding to rx err ring.
  2286. */
  2287. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2288. if (group_number < 0) {
  2289. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2290. soc, REO_EXCEPTION, j);
  2291. continue;
  2292. }
  2293. wlan_cfg_set_rx_err_ring_mask(soc->wlan_cfg_ctx,
  2294. group_number, 0);
  2295. }
  2296. }
  2297. #ifdef IPA_OFFLOAD
  2298. bool dp_reo_remap_config(struct dp_soc *soc, uint32_t *remap0,
  2299. uint32_t *remap1, uint32_t *remap2)
  2300. {
  2301. uint32_t ring[WLAN_CFG_NUM_REO_DEST_RING_MAX] = {
  2302. REO_REMAP_SW1, REO_REMAP_SW2, REO_REMAP_SW3,
  2303. REO_REMAP_SW5, REO_REMAP_SW6, REO_REMAP_SW7};
  2304. switch (soc->arch_id) {
  2305. case CDP_ARCH_TYPE_BE:
  2306. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2307. soc->num_reo_dest_rings -
  2308. USE_2_IPA_RX_REO_RINGS, remap1,
  2309. remap2);
  2310. break;
  2311. case CDP_ARCH_TYPE_LI:
  2312. if (wlan_ipa_is_vlan_enabled()) {
  2313. hal_compute_reo_remap_ix2_ix3(
  2314. soc->hal_soc, ring,
  2315. soc->num_reo_dest_rings -
  2316. USE_2_IPA_RX_REO_RINGS, remap1,
  2317. remap2);
  2318. } else {
  2319. hal_compute_reo_remap_ix2_ix3(
  2320. soc->hal_soc, ring,
  2321. soc->num_reo_dest_rings -
  2322. USE_1_IPA_RX_REO_RING, remap1,
  2323. remap2);
  2324. }
  2325. hal_compute_reo_remap_ix0(soc->hal_soc, remap0);
  2326. break;
  2327. default:
  2328. dp_err("unknown arch_id 0x%x", soc->arch_id);
  2329. QDF_BUG(0);
  2330. }
  2331. dp_debug("remap1 %x remap2 %x", *remap1, *remap2);
  2332. return true;
  2333. }
  2334. #ifdef IPA_WDI3_TX_TWO_PIPES
  2335. static bool dp_ipa_is_alt_tx_ring(int index)
  2336. {
  2337. return index == IPA_TX_ALT_RING_IDX;
  2338. }
  2339. static bool dp_ipa_is_alt_tx_comp_ring(int index)
  2340. {
  2341. return index == IPA_TX_ALT_COMP_RING_IDX;
  2342. }
  2343. #else /* !IPA_WDI3_TX_TWO_PIPES */
  2344. static bool dp_ipa_is_alt_tx_ring(int index)
  2345. {
  2346. return false;
  2347. }
  2348. static bool dp_ipa_is_alt_tx_comp_ring(int index)
  2349. {
  2350. return false;
  2351. }
  2352. #endif /* IPA_WDI3_TX_TWO_PIPES */
  2353. /**
  2354. * dp_ipa_get_tx_ring_size() - Get Tx ring size for IPA
  2355. *
  2356. * @tx_ring_num: Tx ring number
  2357. * @tx_ipa_ring_sz: Return param only updated for IPA.
  2358. * @soc_cfg_ctx: dp soc cfg context
  2359. *
  2360. * Return: None
  2361. */
  2362. static void dp_ipa_get_tx_ring_size(int tx_ring_num, int *tx_ipa_ring_sz,
  2363. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2364. {
  2365. if (!soc_cfg_ctx->ipa_enabled)
  2366. return;
  2367. if (tx_ring_num == IPA_TCL_DATA_RING_IDX)
  2368. *tx_ipa_ring_sz = wlan_cfg_ipa_tx_ring_size(soc_cfg_ctx);
  2369. else if (dp_ipa_is_alt_tx_ring(tx_ring_num))
  2370. *tx_ipa_ring_sz = wlan_cfg_ipa_tx_alt_ring_size(soc_cfg_ctx);
  2371. }
  2372. /**
  2373. * dp_ipa_get_tx_comp_ring_size() - Get Tx comp ring size for IPA
  2374. *
  2375. * @tx_comp_ring_num: Tx comp ring number
  2376. * @tx_comp_ipa_ring_sz: Return param only updated for IPA.
  2377. * @soc_cfg_ctx: dp soc cfg context
  2378. *
  2379. * Return: None
  2380. */
  2381. static void dp_ipa_get_tx_comp_ring_size(int tx_comp_ring_num,
  2382. int *tx_comp_ipa_ring_sz,
  2383. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2384. {
  2385. if (!soc_cfg_ctx->ipa_enabled)
  2386. return;
  2387. if (tx_comp_ring_num == IPA_TCL_DATA_RING_IDX)
  2388. *tx_comp_ipa_ring_sz =
  2389. wlan_cfg_ipa_tx_comp_ring_size(soc_cfg_ctx);
  2390. else if (dp_ipa_is_alt_tx_comp_ring(tx_comp_ring_num))
  2391. *tx_comp_ipa_ring_sz =
  2392. wlan_cfg_ipa_tx_alt_comp_ring_size(soc_cfg_ctx);
  2393. }
  2394. #else
  2395. static uint8_t dp_reo_ring_selection(uint32_t value, uint32_t *ring)
  2396. {
  2397. uint8_t num = 0;
  2398. switch (value) {
  2399. /* should we have all the different possible ring configs */
  2400. case 0xFF:
  2401. num = 8;
  2402. ring[0] = REO_REMAP_SW1;
  2403. ring[1] = REO_REMAP_SW2;
  2404. ring[2] = REO_REMAP_SW3;
  2405. ring[3] = REO_REMAP_SW4;
  2406. ring[4] = REO_REMAP_SW5;
  2407. ring[5] = REO_REMAP_SW6;
  2408. ring[6] = REO_REMAP_SW7;
  2409. ring[7] = REO_REMAP_SW8;
  2410. break;
  2411. case 0x3F:
  2412. num = 6;
  2413. ring[0] = REO_REMAP_SW1;
  2414. ring[1] = REO_REMAP_SW2;
  2415. ring[2] = REO_REMAP_SW3;
  2416. ring[3] = REO_REMAP_SW4;
  2417. ring[4] = REO_REMAP_SW5;
  2418. ring[5] = REO_REMAP_SW6;
  2419. break;
  2420. case 0xF:
  2421. num = 4;
  2422. ring[0] = REO_REMAP_SW1;
  2423. ring[1] = REO_REMAP_SW2;
  2424. ring[2] = REO_REMAP_SW3;
  2425. ring[3] = REO_REMAP_SW4;
  2426. break;
  2427. case 0xE:
  2428. num = 3;
  2429. ring[0] = REO_REMAP_SW2;
  2430. ring[1] = REO_REMAP_SW3;
  2431. ring[2] = REO_REMAP_SW4;
  2432. break;
  2433. case 0xD:
  2434. num = 3;
  2435. ring[0] = REO_REMAP_SW1;
  2436. ring[1] = REO_REMAP_SW3;
  2437. ring[2] = REO_REMAP_SW4;
  2438. break;
  2439. case 0xC:
  2440. num = 2;
  2441. ring[0] = REO_REMAP_SW3;
  2442. ring[1] = REO_REMAP_SW4;
  2443. break;
  2444. case 0xB:
  2445. num = 3;
  2446. ring[0] = REO_REMAP_SW1;
  2447. ring[1] = REO_REMAP_SW2;
  2448. ring[2] = REO_REMAP_SW4;
  2449. break;
  2450. case 0xA:
  2451. num = 2;
  2452. ring[0] = REO_REMAP_SW2;
  2453. ring[1] = REO_REMAP_SW4;
  2454. break;
  2455. case 0x9:
  2456. num = 2;
  2457. ring[0] = REO_REMAP_SW1;
  2458. ring[1] = REO_REMAP_SW4;
  2459. break;
  2460. case 0x8:
  2461. num = 1;
  2462. ring[0] = REO_REMAP_SW4;
  2463. break;
  2464. case 0x7:
  2465. num = 3;
  2466. ring[0] = REO_REMAP_SW1;
  2467. ring[1] = REO_REMAP_SW2;
  2468. ring[2] = REO_REMAP_SW3;
  2469. break;
  2470. case 0x6:
  2471. num = 2;
  2472. ring[0] = REO_REMAP_SW2;
  2473. ring[1] = REO_REMAP_SW3;
  2474. break;
  2475. case 0x5:
  2476. num = 2;
  2477. ring[0] = REO_REMAP_SW1;
  2478. ring[1] = REO_REMAP_SW3;
  2479. break;
  2480. case 0x4:
  2481. num = 1;
  2482. ring[0] = REO_REMAP_SW3;
  2483. break;
  2484. case 0x3:
  2485. num = 2;
  2486. ring[0] = REO_REMAP_SW1;
  2487. ring[1] = REO_REMAP_SW2;
  2488. break;
  2489. case 0x2:
  2490. num = 1;
  2491. ring[0] = REO_REMAP_SW2;
  2492. break;
  2493. case 0x1:
  2494. num = 1;
  2495. ring[0] = REO_REMAP_SW1;
  2496. break;
  2497. default:
  2498. dp_err("unknown reo ring map 0x%x", value);
  2499. QDF_BUG(0);
  2500. }
  2501. return num;
  2502. }
  2503. bool dp_reo_remap_config(struct dp_soc *soc,
  2504. uint32_t *remap0,
  2505. uint32_t *remap1,
  2506. uint32_t *remap2)
  2507. {
  2508. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2509. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  2510. uint8_t num;
  2511. uint32_t ring[WLAN_CFG_NUM_REO_DEST_RING_MAX];
  2512. uint32_t value;
  2513. switch (offload_radio) {
  2514. case dp_nss_cfg_default:
  2515. value = reo_config & WLAN_CFG_NUM_REO_RINGS_MAP_MAX;
  2516. num = dp_reo_ring_selection(value, ring);
  2517. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2518. num, remap1, remap2);
  2519. hal_compute_reo_remap_ix0(soc->hal_soc, remap0);
  2520. break;
  2521. case dp_nss_cfg_first_radio:
  2522. value = reo_config & 0xE;
  2523. num = dp_reo_ring_selection(value, ring);
  2524. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2525. num, remap1, remap2);
  2526. break;
  2527. case dp_nss_cfg_second_radio:
  2528. value = reo_config & 0xD;
  2529. num = dp_reo_ring_selection(value, ring);
  2530. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2531. num, remap1, remap2);
  2532. break;
  2533. case dp_nss_cfg_dbdc:
  2534. case dp_nss_cfg_dbtc:
  2535. /* return false if both or all are offloaded to NSS */
  2536. return false;
  2537. }
  2538. dp_debug("remap1 %x remap2 %x offload_radio %u",
  2539. *remap1, *remap2, offload_radio);
  2540. return true;
  2541. }
  2542. static void dp_ipa_get_tx_ring_size(int ring_num, int *tx_ipa_ring_sz,
  2543. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2544. {
  2545. }
  2546. static void dp_ipa_get_tx_comp_ring_size(int tx_comp_ring_num,
  2547. int *tx_comp_ipa_ring_sz,
  2548. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2549. {
  2550. }
  2551. #endif /* IPA_OFFLOAD */
  2552. /**
  2553. * dp_reo_frag_dst_set() - configure reo register to set the
  2554. * fragment destination ring
  2555. * @soc: Datapath soc
  2556. * @frag_dst_ring: output parameter to set fragment destination ring
  2557. *
  2558. * Based on offload_radio below fragment destination rings is selected
  2559. * 0 - TCL
  2560. * 1 - SW1
  2561. * 2 - SW2
  2562. * 3 - SW3
  2563. * 4 - SW4
  2564. * 5 - Release
  2565. * 6 - FW
  2566. * 7 - alternate select
  2567. *
  2568. * Return: void
  2569. */
  2570. void dp_reo_frag_dst_set(struct dp_soc *soc, uint8_t *frag_dst_ring)
  2571. {
  2572. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2573. switch (offload_radio) {
  2574. case dp_nss_cfg_default:
  2575. *frag_dst_ring = REO_REMAP_TCL;
  2576. break;
  2577. case dp_nss_cfg_first_radio:
  2578. /*
  2579. * This configuration is valid for single band radio which
  2580. * is also NSS offload.
  2581. */
  2582. case dp_nss_cfg_dbdc:
  2583. case dp_nss_cfg_dbtc:
  2584. *frag_dst_ring = HAL_SRNG_REO_ALTERNATE_SELECT;
  2585. break;
  2586. default:
  2587. dp_init_err("%pK: dp_reo_frag_dst_set invalid offload radio config", soc);
  2588. break;
  2589. }
  2590. }
  2591. #ifdef WLAN_FEATURE_STATS_EXT
  2592. static inline void dp_create_ext_stats_event(struct dp_soc *soc)
  2593. {
  2594. qdf_event_create(&soc->rx_hw_stats_event);
  2595. }
  2596. #else
  2597. static inline void dp_create_ext_stats_event(struct dp_soc *soc)
  2598. {
  2599. }
  2600. #endif
  2601. static void dp_deinit_tx_pair_by_index(struct dp_soc *soc, int index)
  2602. {
  2603. int tcl_ring_num, wbm_ring_num;
  2604. wlan_cfg_get_tcl_wbm_ring_num_for_index(soc->wlan_cfg_ctx,
  2605. index,
  2606. &tcl_ring_num,
  2607. &wbm_ring_num);
  2608. if (tcl_ring_num == -1) {
  2609. dp_err("incorrect tcl ring num for index %u", index);
  2610. return;
  2611. }
  2612. wlan_minidump_remove(soc->tcl_data_ring[index].base_vaddr_unaligned,
  2613. soc->tcl_data_ring[index].alloc_size,
  2614. soc->ctrl_psoc,
  2615. WLAN_MD_DP_SRNG_TCL_DATA,
  2616. "tcl_data_ring");
  2617. dp_info("index %u tcl %u wbm %u", index, tcl_ring_num, wbm_ring_num);
  2618. dp_srng_deinit(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2619. tcl_ring_num);
  2620. if (wbm_ring_num == INVALID_WBM_RING_NUM)
  2621. return;
  2622. wlan_minidump_remove(soc->tx_comp_ring[index].base_vaddr_unaligned,
  2623. soc->tx_comp_ring[index].alloc_size,
  2624. soc->ctrl_psoc,
  2625. WLAN_MD_DP_SRNG_TX_COMP,
  2626. "tcl_comp_ring");
  2627. dp_srng_deinit(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2628. wbm_ring_num);
  2629. }
  2630. /**
  2631. * dp_init_tx_ring_pair_by_index() - The function inits tcl data/wbm completion
  2632. * ring pair
  2633. * @soc: DP soc pointer
  2634. * @index: index of soc->tcl_data or soc->tx_comp to initialize
  2635. *
  2636. * Return: QDF_STATUS_SUCCESS on success, error code otherwise.
  2637. */
  2638. static QDF_STATUS dp_init_tx_ring_pair_by_index(struct dp_soc *soc,
  2639. uint8_t index)
  2640. {
  2641. int tcl_ring_num, wbm_ring_num;
  2642. uint8_t bm_id;
  2643. if (index >= MAX_TCL_DATA_RINGS) {
  2644. dp_err("unexpected index!");
  2645. QDF_BUG(0);
  2646. goto fail1;
  2647. }
  2648. wlan_cfg_get_tcl_wbm_ring_num_for_index(soc->wlan_cfg_ctx,
  2649. index,
  2650. &tcl_ring_num,
  2651. &wbm_ring_num);
  2652. if (tcl_ring_num == -1) {
  2653. dp_err("incorrect tcl ring num for index %u", index);
  2654. goto fail1;
  2655. }
  2656. dp_info("index %u tcl %u wbm %u", index, tcl_ring_num, wbm_ring_num);
  2657. if (dp_srng_init(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2658. tcl_ring_num, 0)) {
  2659. dp_err("dp_srng_init failed for tcl_data_ring");
  2660. goto fail1;
  2661. }
  2662. wlan_minidump_log(soc->tcl_data_ring[index].base_vaddr_unaligned,
  2663. soc->tcl_data_ring[index].alloc_size,
  2664. soc->ctrl_psoc,
  2665. WLAN_MD_DP_SRNG_TCL_DATA,
  2666. "tcl_data_ring");
  2667. if (wbm_ring_num == INVALID_WBM_RING_NUM)
  2668. goto set_rbm;
  2669. if (dp_srng_init(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2670. wbm_ring_num, 0)) {
  2671. dp_err("dp_srng_init failed for tx_comp_ring");
  2672. goto fail1;
  2673. }
  2674. wlan_minidump_log(soc->tx_comp_ring[index].base_vaddr_unaligned,
  2675. soc->tx_comp_ring[index].alloc_size,
  2676. soc->ctrl_psoc,
  2677. WLAN_MD_DP_SRNG_TX_COMP,
  2678. "tcl_comp_ring");
  2679. set_rbm:
  2680. bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx, tcl_ring_num);
  2681. soc->arch_ops.tx_implicit_rbm_set(soc, tcl_ring_num, bm_id);
  2682. return QDF_STATUS_SUCCESS;
  2683. fail1:
  2684. return QDF_STATUS_E_FAILURE;
  2685. }
  2686. static void dp_free_tx_ring_pair_by_index(struct dp_soc *soc, uint8_t index)
  2687. {
  2688. dp_debug("index %u", index);
  2689. dp_srng_free(soc, &soc->tcl_data_ring[index]);
  2690. dp_srng_free(soc, &soc->tx_comp_ring[index]);
  2691. }
  2692. /**
  2693. * dp_alloc_tx_ring_pair_by_index() - The function allocs tcl data/wbm2sw
  2694. * ring pair for the given "index"
  2695. * @soc: DP soc pointer
  2696. * @index: index of soc->tcl_data or soc->tx_comp to initialize
  2697. *
  2698. * Return: QDF_STATUS_SUCCESS on success, error code otherwise.
  2699. */
  2700. static QDF_STATUS dp_alloc_tx_ring_pair_by_index(struct dp_soc *soc,
  2701. uint8_t index)
  2702. {
  2703. int tx_ring_size;
  2704. int tx_comp_ring_size;
  2705. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  2706. int cached = 0;
  2707. if (index >= MAX_TCL_DATA_RINGS) {
  2708. dp_err("unexpected index!");
  2709. QDF_BUG(0);
  2710. goto fail1;
  2711. }
  2712. dp_debug("index %u", index);
  2713. tx_ring_size = wlan_cfg_tx_ring_size(soc_cfg_ctx);
  2714. dp_ipa_get_tx_ring_size(index, &tx_ring_size, soc_cfg_ctx);
  2715. if (dp_srng_alloc(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2716. tx_ring_size, cached)) {
  2717. dp_err("dp_srng_alloc failed for tcl_data_ring");
  2718. goto fail1;
  2719. }
  2720. tx_comp_ring_size = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
  2721. dp_ipa_get_tx_comp_ring_size(index, &tx_comp_ring_size, soc_cfg_ctx);
  2722. /* Enable cached TCL desc if NSS offload is disabled */
  2723. if (!wlan_cfg_get_dp_soc_nss_cfg(soc_cfg_ctx))
  2724. cached = WLAN_CFG_DST_RING_CACHED_DESC;
  2725. if (wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, index) ==
  2726. INVALID_WBM_RING_NUM)
  2727. return QDF_STATUS_SUCCESS;
  2728. if (dp_srng_alloc(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2729. tx_comp_ring_size, cached)) {
  2730. dp_err("dp_srng_alloc failed for tx_comp_ring");
  2731. goto fail1;
  2732. }
  2733. return QDF_STATUS_SUCCESS;
  2734. fail1:
  2735. return QDF_STATUS_E_FAILURE;
  2736. }
  2737. /**
  2738. * dp_dscp_tid_map_setup() - Initialize the dscp-tid maps
  2739. * @pdev: DP_PDEV handle
  2740. *
  2741. * Return: void
  2742. */
  2743. void
  2744. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  2745. {
  2746. uint8_t map_id;
  2747. struct dp_soc *soc = pdev->soc;
  2748. if (!soc)
  2749. return;
  2750. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  2751. qdf_mem_copy(pdev->dscp_tid_map[map_id],
  2752. default_dscp_tid_map,
  2753. sizeof(default_dscp_tid_map));
  2754. }
  2755. for (map_id = 0; map_id < soc->num_hw_dscp_tid_map; map_id++) {
  2756. hal_tx_set_dscp_tid_map(soc->hal_soc,
  2757. default_dscp_tid_map,
  2758. map_id);
  2759. }
  2760. }
  2761. /**
  2762. * dp_pcp_tid_map_setup() - Initialize the pcp-tid maps
  2763. * @pdev: DP_PDEV handle
  2764. *
  2765. * Return: void
  2766. */
  2767. void
  2768. dp_pcp_tid_map_setup(struct dp_pdev *pdev)
  2769. {
  2770. struct dp_soc *soc = pdev->soc;
  2771. if (!soc)
  2772. return;
  2773. qdf_mem_copy(soc->pcp_tid_map, default_pcp_tid_map,
  2774. sizeof(default_pcp_tid_map));
  2775. hal_tx_set_pcp_tid_map_default(soc->hal_soc, default_pcp_tid_map);
  2776. }
  2777. #ifndef DP_UMAC_HW_RESET_SUPPORT
  2778. static inline
  2779. #endif
  2780. void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2781. {
  2782. struct reo_desc_list_node *desc;
  2783. struct dp_rx_tid *rx_tid;
  2784. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2785. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2786. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2787. rx_tid = &desc->rx_tid;
  2788. qdf_mem_unmap_nbytes_single(soc->osdev,
  2789. rx_tid->hw_qdesc_paddr,
  2790. QDF_DMA_BIDIRECTIONAL,
  2791. rx_tid->hw_qdesc_alloc_size);
  2792. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2793. qdf_mem_free(desc);
  2794. }
  2795. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2796. qdf_list_destroy(&soc->reo_desc_freelist);
  2797. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2798. }
  2799. #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY
  2800. /**
  2801. * dp_reo_desc_deferred_freelist_create() - Initialize the resources used
  2802. * for deferred reo desc list
  2803. * @soc: Datapath soc handle
  2804. *
  2805. * Return: void
  2806. */
  2807. static void dp_reo_desc_deferred_freelist_create(struct dp_soc *soc)
  2808. {
  2809. qdf_spinlock_create(&soc->reo_desc_deferred_freelist_lock);
  2810. qdf_list_create(&soc->reo_desc_deferred_freelist,
  2811. REO_DESC_DEFERRED_FREELIST_SIZE);
  2812. soc->reo_desc_deferred_freelist_init = true;
  2813. }
  2814. /**
  2815. * dp_reo_desc_deferred_freelist_destroy() - loop the deferred free list &
  2816. * free the leftover REO QDESCs
  2817. * @soc: Datapath soc handle
  2818. *
  2819. * Return: void
  2820. */
  2821. static void dp_reo_desc_deferred_freelist_destroy(struct dp_soc *soc)
  2822. {
  2823. struct reo_desc_deferred_freelist_node *desc;
  2824. qdf_spin_lock_bh(&soc->reo_desc_deferred_freelist_lock);
  2825. soc->reo_desc_deferred_freelist_init = false;
  2826. while (qdf_list_remove_front(&soc->reo_desc_deferred_freelist,
  2827. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2828. qdf_mem_unmap_nbytes_single(soc->osdev,
  2829. desc->hw_qdesc_paddr,
  2830. QDF_DMA_BIDIRECTIONAL,
  2831. desc->hw_qdesc_alloc_size);
  2832. qdf_mem_free(desc->hw_qdesc_vaddr_unaligned);
  2833. qdf_mem_free(desc);
  2834. }
  2835. qdf_spin_unlock_bh(&soc->reo_desc_deferred_freelist_lock);
  2836. qdf_list_destroy(&soc->reo_desc_deferred_freelist);
  2837. qdf_spinlock_destroy(&soc->reo_desc_deferred_freelist_lock);
  2838. }
  2839. #else
  2840. static inline void dp_reo_desc_deferred_freelist_create(struct dp_soc *soc)
  2841. {
  2842. }
  2843. static inline void dp_reo_desc_deferred_freelist_destroy(struct dp_soc *soc)
  2844. {
  2845. }
  2846. #endif /* !WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY */
  2847. /**
  2848. * dp_soc_reset_txrx_ring_map() - reset tx ring map
  2849. * @soc: DP SOC handle
  2850. *
  2851. */
  2852. static void dp_soc_reset_txrx_ring_map(struct dp_soc *soc)
  2853. {
  2854. uint32_t i;
  2855. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++)
  2856. soc->tx_ring_map[i] = 0;
  2857. }
  2858. /**
  2859. * dp_soc_deinit() - Deinitialize txrx SOC
  2860. * @txrx_soc: Opaque DP SOC handle
  2861. *
  2862. * Return: None
  2863. */
  2864. void dp_soc_deinit(void *txrx_soc)
  2865. {
  2866. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2867. struct htt_soc *htt_soc = soc->htt_handle;
  2868. dp_monitor_soc_deinit(soc);
  2869. /* free peer tables & AST tables allocated during peer_map_attach */
  2870. if (soc->peer_map_attach_success) {
  2871. dp_peer_find_detach(soc);
  2872. soc->arch_ops.txrx_peer_map_detach(soc);
  2873. soc->peer_map_attach_success = FALSE;
  2874. }
  2875. qdf_flush_work(&soc->htt_stats.work);
  2876. qdf_disable_work(&soc->htt_stats.work);
  2877. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2878. dp_soc_reset_txrx_ring_map(soc);
  2879. dp_reo_desc_freelist_destroy(soc);
  2880. dp_reo_desc_deferred_freelist_destroy(soc);
  2881. DEINIT_RX_HW_STATS_LOCK(soc);
  2882. qdf_spinlock_destroy(&soc->ast_lock);
  2883. dp_peer_mec_spinlock_destroy(soc);
  2884. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2885. qdf_nbuf_queue_free(&soc->invalid_buf_queue);
  2886. qdf_spinlock_destroy(&soc->rx.defrag.defrag_lock);
  2887. qdf_spinlock_destroy(&soc->vdev_map_lock);
  2888. dp_reo_cmdlist_destroy(soc);
  2889. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2890. dp_soc_tx_desc_sw_pools_deinit(soc);
  2891. dp_soc_srng_deinit(soc);
  2892. dp_hw_link_desc_ring_deinit(soc);
  2893. dp_soc_print_inactive_objects(soc);
  2894. qdf_spinlock_destroy(&soc->inactive_peer_list_lock);
  2895. qdf_spinlock_destroy(&soc->inactive_vdev_list_lock);
  2896. htt_soc_htc_dealloc(soc->htt_handle);
  2897. htt_soc_detach(htt_soc);
  2898. /* Free wbm sg list and reset flags in down path */
  2899. dp_rx_wbm_sg_list_deinit(soc);
  2900. wlan_minidump_remove(soc, sizeof(*soc), soc->ctrl_psoc,
  2901. WLAN_MD_DP_SOC, "dp_soc");
  2902. }
  2903. #ifdef QCA_HOST2FW_RXBUF_RING
  2904. void
  2905. dp_htt_setup_rxdma_err_dst_ring(struct dp_soc *soc, int mac_id,
  2906. int lmac_id)
  2907. {
  2908. if (soc->rxdma_err_dst_ring[lmac_id].hal_srng)
  2909. htt_srng_setup(soc->htt_handle, mac_id,
  2910. soc->rxdma_err_dst_ring[lmac_id].hal_srng,
  2911. RXDMA_DST);
  2912. }
  2913. #endif
  2914. void dp_vdev_get_default_reo_hash(struct dp_vdev *vdev,
  2915. enum cdp_host_reo_dest_ring *reo_dest,
  2916. bool *hash_based)
  2917. {
  2918. struct dp_soc *soc;
  2919. struct dp_pdev *pdev;
  2920. pdev = vdev->pdev;
  2921. soc = pdev->soc;
  2922. /*
  2923. * hash based steering is disabled for Radios which are offloaded
  2924. * to NSS
  2925. */
  2926. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2927. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2928. /*
  2929. * Below line of code will ensure the proper reo_dest ring is chosen
  2930. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  2931. */
  2932. *reo_dest = pdev->reo_dest;
  2933. }
  2934. #ifdef IPA_OFFLOAD
  2935. /**
  2936. * dp_is_vdev_subtype_p2p() - Check if the subtype for vdev is P2P
  2937. * @vdev: Virtual device
  2938. *
  2939. * Return: true if the vdev is of subtype P2P
  2940. * false if the vdev is of any other subtype
  2941. */
  2942. static inline bool dp_is_vdev_subtype_p2p(struct dp_vdev *vdev)
  2943. {
  2944. if (vdev->subtype == wlan_op_subtype_p2p_device ||
  2945. vdev->subtype == wlan_op_subtype_p2p_cli ||
  2946. vdev->subtype == wlan_op_subtype_p2p_go)
  2947. return true;
  2948. return false;
  2949. }
  2950. /**
  2951. * dp_peer_setup_get_reo_hash() - get reo dest ring and hash values for a peer
  2952. * @vdev: Datapath VDEV handle
  2953. * @setup_info:
  2954. * @reo_dest: pointer to default reo_dest ring for vdev to be populated
  2955. * @hash_based: pointer to hash value (enabled/disabled) to be populated
  2956. * @lmac_peer_id_msb:
  2957. *
  2958. * If IPA is enabled in ini, for SAP mode, disable hash based
  2959. * steering, use default reo_dst ring for RX. Use config values for other modes.
  2960. *
  2961. * Return: None
  2962. */
  2963. static void dp_peer_setup_get_reo_hash(struct dp_vdev *vdev,
  2964. struct cdp_peer_setup_info *setup_info,
  2965. enum cdp_host_reo_dest_ring *reo_dest,
  2966. bool *hash_based,
  2967. uint8_t *lmac_peer_id_msb)
  2968. {
  2969. struct dp_soc *soc;
  2970. struct dp_pdev *pdev;
  2971. pdev = vdev->pdev;
  2972. soc = pdev->soc;
  2973. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  2974. /* For P2P-GO interfaces we do not need to change the REO
  2975. * configuration even if IPA config is enabled
  2976. */
  2977. if (dp_is_vdev_subtype_p2p(vdev))
  2978. return;
  2979. /*
  2980. * If IPA is enabled, disable hash-based flow steering and set
  2981. * reo_dest_ring_4 as the REO ring to receive packets on.
  2982. * IPA is configured to reap reo_dest_ring_4.
  2983. *
  2984. * Note - REO DST indexes are from 0 - 3, while cdp_host_reo_dest_ring
  2985. * value enum value is from 1 - 4.
  2986. * Hence, *reo_dest = IPA_REO_DEST_RING_IDX + 1
  2987. */
  2988. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  2989. if (dp_ipa_is_mdm_platform()) {
  2990. *reo_dest = IPA_REO_DEST_RING_IDX + 1;
  2991. if (vdev->opmode == wlan_op_mode_ap)
  2992. *hash_based = 0;
  2993. } else {
  2994. dp_debug("opt_dp: default HOST reo ring is set");
  2995. }
  2996. }
  2997. }
  2998. #else
  2999. /**
  3000. * dp_peer_setup_get_reo_hash() - get reo dest ring and hash values for a peer
  3001. * @vdev: Datapath VDEV handle
  3002. * @setup_info:
  3003. * @reo_dest: pointer to default reo_dest ring for vdev to be populated
  3004. * @hash_based: pointer to hash value (enabled/disabled) to be populated
  3005. * @lmac_peer_id_msb:
  3006. *
  3007. * Use system config values for hash based steering.
  3008. * Return: None
  3009. */
  3010. static void dp_peer_setup_get_reo_hash(struct dp_vdev *vdev,
  3011. struct cdp_peer_setup_info *setup_info,
  3012. enum cdp_host_reo_dest_ring *reo_dest,
  3013. bool *hash_based,
  3014. uint8_t *lmac_peer_id_msb)
  3015. {
  3016. struct dp_soc *soc = vdev->pdev->soc;
  3017. soc->arch_ops.peer_get_reo_hash(vdev, setup_info, reo_dest, hash_based,
  3018. lmac_peer_id_msb);
  3019. }
  3020. #endif /* IPA_OFFLOAD */
  3021. /**
  3022. * dp_peer_setup_wifi3() - initialize the peer
  3023. * @soc_hdl: soc handle object
  3024. * @vdev_id: vdev_id of vdev object
  3025. * @peer_mac: Peer's mac address
  3026. * @setup_info: peer setup info for MLO
  3027. *
  3028. * Return: QDF_STATUS
  3029. */
  3030. QDF_STATUS
  3031. dp_peer_setup_wifi3(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3032. uint8_t *peer_mac,
  3033. struct cdp_peer_setup_info *setup_info)
  3034. {
  3035. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3036. struct dp_pdev *pdev;
  3037. bool hash_based = 0;
  3038. enum cdp_host_reo_dest_ring reo_dest;
  3039. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3040. struct dp_vdev *vdev = NULL;
  3041. struct dp_peer *peer =
  3042. dp_peer_find_hash_find(soc, peer_mac, 0, vdev_id,
  3043. DP_MOD_ID_CDP);
  3044. struct dp_peer *mld_peer = NULL;
  3045. enum wlan_op_mode vdev_opmode;
  3046. uint8_t lmac_peer_id_msb = 0;
  3047. if (!peer)
  3048. return QDF_STATUS_E_FAILURE;
  3049. vdev = peer->vdev;
  3050. if (!vdev) {
  3051. status = QDF_STATUS_E_FAILURE;
  3052. goto fail;
  3053. }
  3054. /* save vdev related member in case vdev freed */
  3055. vdev_opmode = vdev->opmode;
  3056. pdev = vdev->pdev;
  3057. dp_peer_setup_get_reo_hash(vdev, setup_info,
  3058. &reo_dest, &hash_based,
  3059. &lmac_peer_id_msb);
  3060. dp_cfg_event_record_peer_setup_evt(soc, DP_CFG_EVENT_PEER_SETUP,
  3061. peer, vdev, vdev->vdev_id,
  3062. setup_info);
  3063. dp_info("pdev: %d vdev :%d opmode:%u peer %pK (" QDF_MAC_ADDR_FMT ") "
  3064. "hash-based-steering:%d default-reo_dest:%u",
  3065. pdev->pdev_id, vdev->vdev_id,
  3066. vdev->opmode, peer,
  3067. QDF_MAC_ADDR_REF(peer->mac_addr.raw), hash_based, reo_dest);
  3068. /*
  3069. * There are corner cases where the AD1 = AD2 = "VAPs address"
  3070. * i.e both the devices have same MAC address. In these
  3071. * cases we want such pkts to be processed in NULL Q handler
  3072. * which is REO2TCL ring. for this reason we should
  3073. * not setup reo_queues and default route for bss_peer.
  3074. */
  3075. if (!IS_MLO_DP_MLD_PEER(peer))
  3076. dp_monitor_peer_tx_init(pdev, peer);
  3077. if (!setup_info)
  3078. if (dp_peer_legacy_setup(soc, peer) !=
  3079. QDF_STATUS_SUCCESS) {
  3080. status = QDF_STATUS_E_RESOURCES;
  3081. goto fail;
  3082. }
  3083. if (peer->bss_peer && vdev->opmode == wlan_op_mode_ap) {
  3084. status = QDF_STATUS_E_FAILURE;
  3085. goto fail;
  3086. }
  3087. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  3088. /* TODO: Check the destination ring number to be passed to FW */
  3089. soc->cdp_soc.ol_ops->peer_set_default_routing(
  3090. soc->ctrl_psoc,
  3091. peer->vdev->pdev->pdev_id,
  3092. peer->mac_addr.raw,
  3093. peer->vdev->vdev_id, hash_based, reo_dest,
  3094. lmac_peer_id_msb);
  3095. }
  3096. qdf_atomic_set(&peer->is_default_route_set, 1);
  3097. status = dp_peer_mlo_setup(soc, peer, vdev->vdev_id, setup_info);
  3098. if (QDF_IS_STATUS_ERROR(status)) {
  3099. dp_peer_err("peer mlo setup failed");
  3100. qdf_assert_always(0);
  3101. }
  3102. if (vdev_opmode != wlan_op_mode_monitor) {
  3103. /* In case of MLD peer, switch peer to mld peer and
  3104. * do peer_rx_init.
  3105. */
  3106. if (hal_reo_shared_qaddr_is_enable(soc->hal_soc) &&
  3107. IS_MLO_DP_LINK_PEER(peer)) {
  3108. if (setup_info && setup_info->is_first_link) {
  3109. mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
  3110. if (mld_peer)
  3111. dp_peer_rx_init(pdev, mld_peer);
  3112. else
  3113. dp_peer_err("MLD peer null. Primary link peer:%pK", peer);
  3114. }
  3115. } else {
  3116. dp_peer_rx_init(pdev, peer);
  3117. }
  3118. }
  3119. if (!IS_MLO_DP_MLD_PEER(peer))
  3120. dp_peer_ppdu_delayed_ba_init(peer);
  3121. fail:
  3122. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  3123. return status;
  3124. }
  3125. /**
  3126. * dp_set_ba_aging_timeout() - set ba aging timeout per AC
  3127. * @txrx_soc: cdp soc handle
  3128. * @ac: Access category
  3129. * @value: timeout value in millisec
  3130. *
  3131. * Return: void
  3132. */
  3133. void dp_set_ba_aging_timeout(struct cdp_soc_t *txrx_soc,
  3134. uint8_t ac, uint32_t value)
  3135. {
  3136. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3137. hal_set_ba_aging_timeout(soc->hal_soc, ac, value);
  3138. }
  3139. /**
  3140. * dp_get_ba_aging_timeout() - get ba aging timeout per AC
  3141. * @txrx_soc: cdp soc handle
  3142. * @ac: access category
  3143. * @value: timeout value in millisec
  3144. *
  3145. * Return: void
  3146. */
  3147. void dp_get_ba_aging_timeout(struct cdp_soc_t *txrx_soc,
  3148. uint8_t ac, uint32_t *value)
  3149. {
  3150. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3151. hal_get_ba_aging_timeout(soc->hal_soc, ac, value);
  3152. }
  3153. /**
  3154. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  3155. * @txrx_soc: cdp soc handle
  3156. * @pdev_id: id of physical device object
  3157. * @val: reo destination ring index (1 - 4)
  3158. *
  3159. * Return: QDF_STATUS
  3160. */
  3161. QDF_STATUS
  3162. dp_set_pdev_reo_dest(struct cdp_soc_t *txrx_soc, uint8_t pdev_id,
  3163. enum cdp_host_reo_dest_ring val)
  3164. {
  3165. struct dp_pdev *pdev =
  3166. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)txrx_soc,
  3167. pdev_id);
  3168. if (pdev) {
  3169. pdev->reo_dest = val;
  3170. return QDF_STATUS_SUCCESS;
  3171. }
  3172. return QDF_STATUS_E_FAILURE;
  3173. }
  3174. /**
  3175. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  3176. * @txrx_soc: cdp soc handle
  3177. * @pdev_id: id of physical device object
  3178. *
  3179. * Return: reo destination ring index
  3180. */
  3181. enum cdp_host_reo_dest_ring
  3182. dp_get_pdev_reo_dest(struct cdp_soc_t *txrx_soc, uint8_t pdev_id)
  3183. {
  3184. struct dp_pdev *pdev =
  3185. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)txrx_soc,
  3186. pdev_id);
  3187. if (pdev)
  3188. return pdev->reo_dest;
  3189. else
  3190. return cdp_host_reo_dest_ring_unknown;
  3191. }
  3192. void dp_rx_bar_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3193. union hal_reo_status *reo_status)
  3194. {
  3195. struct dp_pdev *pdev = (struct dp_pdev *)cb_ctxt;
  3196. struct hal_reo_queue_status *queue_status = &(reo_status->queue_status);
  3197. if (!dp_check_pdev_exists(soc, pdev)) {
  3198. dp_err_rl("pdev doesn't exist");
  3199. return;
  3200. }
  3201. if (!qdf_atomic_read(&soc->cmn_init_done))
  3202. return;
  3203. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3204. DP_PRINT_STATS("REO stats failure %d",
  3205. queue_status->header.status);
  3206. qdf_atomic_set(&(pdev->stats_cmd_complete), 1);
  3207. return;
  3208. }
  3209. pdev->stats.rx.bar_recv_cnt += queue_status->bar_rcvd_cnt;
  3210. qdf_atomic_set(&(pdev->stats_cmd_complete), 1);
  3211. }
  3212. /**
  3213. * dp_dump_wbm_idle_hptp() - dump wbm idle ring, hw hp tp info.
  3214. * @soc: dp soc.
  3215. * @pdev: dp pdev.
  3216. *
  3217. * Return: None.
  3218. */
  3219. void
  3220. dp_dump_wbm_idle_hptp(struct dp_soc *soc, struct dp_pdev *pdev)
  3221. {
  3222. uint32_t hw_head;
  3223. uint32_t hw_tail;
  3224. struct dp_srng *srng;
  3225. if (!soc) {
  3226. dp_err("soc is NULL");
  3227. return;
  3228. }
  3229. if (!pdev) {
  3230. dp_err("pdev is NULL");
  3231. return;
  3232. }
  3233. srng = &pdev->soc->wbm_idle_link_ring;
  3234. if (!srng) {
  3235. dp_err("wbm_idle_link_ring srng is NULL");
  3236. return;
  3237. }
  3238. hal_get_hw_hptp(soc->hal_soc, srng->hal_srng, &hw_head,
  3239. &hw_tail, WBM_IDLE_LINK);
  3240. dp_debug("WBM_IDLE_LINK: HW hp: %d, HW tp: %d",
  3241. hw_head, hw_tail);
  3242. }
  3243. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3244. static void dp_update_soft_irq_limits(struct dp_soc *soc, uint32_t tx_limit,
  3245. uint32_t rx_limit)
  3246. {
  3247. soc->wlan_cfg_ctx->tx_comp_loop_pkt_limit = tx_limit;
  3248. soc->wlan_cfg_ctx->rx_reap_loop_pkt_limit = rx_limit;
  3249. }
  3250. #else
  3251. static inline
  3252. void dp_update_soft_irq_limits(struct dp_soc *soc, uint32_t tx_limit,
  3253. uint32_t rx_limit)
  3254. {
  3255. }
  3256. #endif /* WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT */
  3257. /**
  3258. * dp_display_srng_info() - Dump the srng HP TP info
  3259. * @soc_hdl: CDP Soc handle
  3260. *
  3261. * This function dumps the SW hp/tp values for the important rings.
  3262. * HW hp/tp values are not being dumped, since it can lead to
  3263. * READ NOC error when UMAC is in low power state. MCC does not have
  3264. * device force wake working yet.
  3265. *
  3266. * Return: none
  3267. */
  3268. void dp_display_srng_info(struct cdp_soc_t *soc_hdl)
  3269. {
  3270. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3271. hal_soc_handle_t hal_soc = soc->hal_soc;
  3272. uint32_t hp, tp, i;
  3273. dp_info("SRNG HP-TP data:");
  3274. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3275. hal_get_sw_hptp(hal_soc, soc->tcl_data_ring[i].hal_srng,
  3276. &tp, &hp);
  3277. dp_info("TCL DATA ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3278. if (wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, i) ==
  3279. INVALID_WBM_RING_NUM)
  3280. continue;
  3281. hal_get_sw_hptp(hal_soc, soc->tx_comp_ring[i].hal_srng,
  3282. &tp, &hp);
  3283. dp_info("TX comp ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3284. }
  3285. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  3286. hal_get_sw_hptp(hal_soc, soc->reo_dest_ring[i].hal_srng,
  3287. &tp, &hp);
  3288. dp_info("REO DST ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3289. }
  3290. hal_get_sw_hptp(hal_soc, soc->reo_exception_ring.hal_srng, &tp, &hp);
  3291. dp_info("REO exception ring: hp=0x%x, tp=0x%x", hp, tp);
  3292. hal_get_sw_hptp(hal_soc, soc->rx_rel_ring.hal_srng, &tp, &hp);
  3293. dp_info("WBM RX release ring: hp=0x%x, tp=0x%x", hp, tp);
  3294. hal_get_sw_hptp(hal_soc, soc->wbm_desc_rel_ring.hal_srng, &tp, &hp);
  3295. dp_info("WBM desc release ring: hp=0x%x, tp=0x%x", hp, tp);
  3296. }
  3297. /**
  3298. * dp_set_pdev_pcp_tid_map_wifi3() - update pcp tid map in pdev
  3299. * @psoc: dp soc handle
  3300. * @pdev_id: id of DP_PDEV handle
  3301. * @pcp: pcp value
  3302. * @tid: tid value passed by the user
  3303. *
  3304. * Return: QDF_STATUS_SUCCESS on success
  3305. */
  3306. QDF_STATUS dp_set_pdev_pcp_tid_map_wifi3(ol_txrx_soc_handle psoc,
  3307. uint8_t pdev_id,
  3308. uint8_t pcp, uint8_t tid)
  3309. {
  3310. struct dp_soc *soc = (struct dp_soc *)psoc;
  3311. soc->pcp_tid_map[pcp] = tid;
  3312. hal_tx_update_pcp_tid_map(soc->hal_soc, pcp, tid);
  3313. return QDF_STATUS_SUCCESS;
  3314. }
  3315. /**
  3316. * dp_set_vdev_pcp_tid_map_wifi3() - update pcp tid map in vdev
  3317. * @soc_hdl: DP soc handle
  3318. * @vdev_id: id of DP_VDEV handle
  3319. * @pcp: pcp value
  3320. * @tid: tid value passed by the user
  3321. *
  3322. * Return: QDF_STATUS_SUCCESS on success
  3323. */
  3324. QDF_STATUS dp_set_vdev_pcp_tid_map_wifi3(struct cdp_soc_t *soc_hdl,
  3325. uint8_t vdev_id,
  3326. uint8_t pcp, uint8_t tid)
  3327. {
  3328. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3329. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3330. DP_MOD_ID_CDP);
  3331. if (!vdev)
  3332. return QDF_STATUS_E_FAILURE;
  3333. vdev->pcp_tid_map[pcp] = tid;
  3334. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3335. return QDF_STATUS_SUCCESS;
  3336. }
  3337. #if defined(FEATURE_RUNTIME_PM) || defined(DP_POWER_SAVE)
  3338. void dp_drain_txrx(struct cdp_soc_t *soc_handle)
  3339. {
  3340. struct dp_soc *soc = (struct dp_soc *)soc_handle;
  3341. uint32_t cur_tx_limit, cur_rx_limit;
  3342. uint32_t budget = 0xffff;
  3343. uint32_t val;
  3344. int i;
  3345. int cpu = dp_srng_get_cpu();
  3346. cur_tx_limit = soc->wlan_cfg_ctx->tx_comp_loop_pkt_limit;
  3347. cur_rx_limit = soc->wlan_cfg_ctx->rx_reap_loop_pkt_limit;
  3348. /* Temporarily increase soft irq limits when going to drain
  3349. * the UMAC/LMAC SRNGs and restore them after polling.
  3350. * Though the budget is on higher side, the TX/RX reaping loops
  3351. * will not execute longer as both TX and RX would be suspended
  3352. * by the time this API is called.
  3353. */
  3354. dp_update_soft_irq_limits(soc, budget, budget);
  3355. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  3356. dp_service_srngs(&soc->intr_ctx[i], budget, cpu);
  3357. dp_update_soft_irq_limits(soc, cur_tx_limit, cur_rx_limit);
  3358. /* Do a dummy read at offset 0; this will ensure all
  3359. * pendings writes(HP/TP) are flushed before read returns.
  3360. */
  3361. val = HAL_REG_READ((struct hal_soc *)soc->hal_soc, 0);
  3362. dp_debug("Register value at offset 0: %u", val);
  3363. }
  3364. #endif
  3365. #if defined(DP_POWER_SAVE) || defined(FEATURE_RUNTIME_PM)
  3366. /**
  3367. * dp_flush_ring_hptp() - Update ring shadow
  3368. * register HP/TP address when runtime
  3369. * resume
  3370. * @soc: DP soc context
  3371. * @hal_srng: srng
  3372. *
  3373. * Return: None
  3374. */
  3375. static void dp_flush_ring_hptp(struct dp_soc *soc, hal_ring_handle_t hal_srng)
  3376. {
  3377. if (hal_srng && hal_srng_get_clear_event(hal_srng,
  3378. HAL_SRNG_FLUSH_EVENT)) {
  3379. /* Acquire the lock */
  3380. hal_srng_access_start(soc->hal_soc, hal_srng);
  3381. hal_srng_access_end(soc->hal_soc, hal_srng);
  3382. hal_srng_set_flush_last_ts(hal_srng);
  3383. dp_debug("flushed");
  3384. }
  3385. }
  3386. void dp_update_ring_hptp(struct dp_soc *soc, bool force_flush_tx)
  3387. {
  3388. uint8_t i;
  3389. if (force_flush_tx) {
  3390. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3391. hal_srng_set_event(soc->tcl_data_ring[i].hal_srng,
  3392. HAL_SRNG_FLUSH_EVENT);
  3393. dp_flush_ring_hptp(soc, soc->tcl_data_ring[i].hal_srng);
  3394. }
  3395. return;
  3396. }
  3397. for (i = 0; i < soc->num_tcl_data_rings; i++)
  3398. dp_flush_ring_hptp(soc, soc->tcl_data_ring[i].hal_srng);
  3399. dp_flush_ring_hptp(soc, soc->reo_cmd_ring.hal_srng);
  3400. }
  3401. #endif
  3402. #ifdef WLAN_FEATURE_STATS_EXT
  3403. /* rx hw stats event wait timeout in ms */
  3404. #define DP_REO_STATUS_STATS_TIMEOUT 100
  3405. /**
  3406. * dp_rx_hw_stats_cb() - request rx hw stats response callback
  3407. * @soc: soc handle
  3408. * @cb_ctxt: callback context
  3409. * @reo_status: reo command response status
  3410. *
  3411. * Return: None
  3412. */
  3413. static void dp_rx_hw_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3414. union hal_reo_status *reo_status)
  3415. {
  3416. struct dp_req_rx_hw_stats_t *rx_hw_stats = cb_ctxt;
  3417. struct hal_reo_queue_status *queue_status = &reo_status->queue_status;
  3418. bool is_query_timeout;
  3419. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3420. is_query_timeout = rx_hw_stats->is_query_timeout;
  3421. /* free the cb_ctxt if all pending tid stats query is received */
  3422. if (qdf_atomic_dec_and_test(&rx_hw_stats->pending_tid_stats_cnt)) {
  3423. if (!is_query_timeout) {
  3424. qdf_event_set(&soc->rx_hw_stats_event);
  3425. soc->is_last_stats_ctx_init = false;
  3426. }
  3427. qdf_mem_free(rx_hw_stats);
  3428. }
  3429. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3430. dp_info("REO stats failure %d",
  3431. queue_status->header.status);
  3432. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3433. return;
  3434. }
  3435. if (!is_query_timeout) {
  3436. soc->ext_stats.rx_mpdu_received +=
  3437. queue_status->mpdu_frms_cnt;
  3438. soc->ext_stats.rx_mpdu_missed +=
  3439. queue_status->hole_cnt;
  3440. }
  3441. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3442. }
  3443. /**
  3444. * dp_request_rx_hw_stats() - request rx hardware stats
  3445. * @soc_hdl: soc handle
  3446. * @vdev_id: vdev id
  3447. *
  3448. * Return: None
  3449. */
  3450. QDF_STATUS
  3451. dp_request_rx_hw_stats(struct cdp_soc_t *soc_hdl, uint8_t vdev_id)
  3452. {
  3453. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3454. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3455. DP_MOD_ID_CDP);
  3456. struct dp_peer *peer = NULL;
  3457. QDF_STATUS status;
  3458. struct dp_req_rx_hw_stats_t *rx_hw_stats;
  3459. int rx_stats_sent_cnt = 0;
  3460. uint32_t last_rx_mpdu_received;
  3461. uint32_t last_rx_mpdu_missed;
  3462. if (!vdev) {
  3463. dp_err("vdev is null for vdev_id: %u", vdev_id);
  3464. status = QDF_STATUS_E_INVAL;
  3465. goto out;
  3466. }
  3467. peer = dp_vdev_bss_peer_ref_n_get(soc, vdev, DP_MOD_ID_CDP);
  3468. if (!peer) {
  3469. dp_err("Peer is NULL");
  3470. status = QDF_STATUS_E_INVAL;
  3471. goto out;
  3472. }
  3473. rx_hw_stats = qdf_mem_malloc(sizeof(*rx_hw_stats));
  3474. if (!rx_hw_stats) {
  3475. dp_err("malloc failed for hw stats structure");
  3476. status = QDF_STATUS_E_INVAL;
  3477. goto out;
  3478. }
  3479. qdf_event_reset(&soc->rx_hw_stats_event);
  3480. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3481. /* save the last soc cumulative stats and reset it to 0 */
  3482. last_rx_mpdu_received = soc->ext_stats.rx_mpdu_received;
  3483. last_rx_mpdu_missed = soc->ext_stats.rx_mpdu_missed;
  3484. soc->ext_stats.rx_mpdu_received = 0;
  3485. soc->ext_stats.rx_mpdu_missed = 0;
  3486. dp_debug("HW stats query start");
  3487. rx_stats_sent_cnt =
  3488. dp_peer_rxtid_stats(peer, dp_rx_hw_stats_cb, rx_hw_stats);
  3489. if (!rx_stats_sent_cnt) {
  3490. dp_err("no tid stats sent successfully");
  3491. qdf_mem_free(rx_hw_stats);
  3492. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3493. status = QDF_STATUS_E_INVAL;
  3494. goto out;
  3495. }
  3496. qdf_atomic_set(&rx_hw_stats->pending_tid_stats_cnt,
  3497. rx_stats_sent_cnt);
  3498. rx_hw_stats->is_query_timeout = false;
  3499. soc->is_last_stats_ctx_init = true;
  3500. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3501. status = qdf_wait_single_event(&soc->rx_hw_stats_event,
  3502. DP_REO_STATUS_STATS_TIMEOUT);
  3503. dp_debug("HW stats query end with %d", rx_stats_sent_cnt);
  3504. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3505. if (status != QDF_STATUS_SUCCESS) {
  3506. dp_info("partial rx hw stats event collected with %d",
  3507. qdf_atomic_read(
  3508. &rx_hw_stats->pending_tid_stats_cnt));
  3509. if (soc->is_last_stats_ctx_init)
  3510. rx_hw_stats->is_query_timeout = true;
  3511. /*
  3512. * If query timeout happened, use the last saved stats
  3513. * for this time query.
  3514. */
  3515. soc->ext_stats.rx_mpdu_received = last_rx_mpdu_received;
  3516. soc->ext_stats.rx_mpdu_missed = last_rx_mpdu_missed;
  3517. DP_STATS_INC(soc, rx.rx_hw_stats_timeout, 1);
  3518. }
  3519. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3520. out:
  3521. if (peer)
  3522. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  3523. if (vdev)
  3524. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3525. DP_STATS_INC(soc, rx.rx_hw_stats_requested, 1);
  3526. return status;
  3527. }
  3528. /**
  3529. * dp_reset_rx_hw_ext_stats() - Reset rx hardware ext stats
  3530. * @soc_hdl: soc handle
  3531. *
  3532. * Return: None
  3533. */
  3534. void dp_reset_rx_hw_ext_stats(struct cdp_soc_t *soc_hdl)
  3535. {
  3536. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3537. soc->ext_stats.rx_mpdu_received = 0;
  3538. soc->ext_stats.rx_mpdu_missed = 0;
  3539. }
  3540. #endif /* WLAN_FEATURE_STATS_EXT */
  3541. uint32_t dp_get_tx_rings_grp_bitmap(struct cdp_soc_t *soc_hdl)
  3542. {
  3543. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3544. return soc->wlan_cfg_ctx->tx_rings_grp_bitmap;
  3545. }
  3546. void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  3547. {
  3548. uint32_t i;
  3549. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  3550. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_DEFAULT_MAP][i];
  3551. }
  3552. }
  3553. qdf_export_symbol(dp_soc_set_txrx_ring_map);
  3554. static void dp_soc_cfg_dump(struct dp_soc *soc, uint32_t target_type)
  3555. {
  3556. dp_init_info("DP soc Dump for Target = %d", target_type);
  3557. dp_init_info("ast_override_support = %d da_war_enabled = %d",
  3558. soc->ast_override_support, soc->da_war_enabled);
  3559. wlan_cfg_dp_soc_ctx_dump(soc->wlan_cfg_ctx);
  3560. }
  3561. /**
  3562. * dp_soc_cfg_init() - initialize target specific configuration
  3563. * during dp_soc_init
  3564. * @soc: dp soc handle
  3565. */
  3566. static void dp_soc_cfg_init(struct dp_soc *soc)
  3567. {
  3568. uint32_t target_type;
  3569. target_type = hal_get_target_type(soc->hal_soc);
  3570. switch (target_type) {
  3571. case TARGET_TYPE_QCA6290:
  3572. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  3573. REO_DST_RING_SIZE_QCA6290);
  3574. soc->ast_override_support = 1;
  3575. soc->da_war_enabled = false;
  3576. break;
  3577. case TARGET_TYPE_QCA6390:
  3578. case TARGET_TYPE_QCA6490:
  3579. case TARGET_TYPE_QCA6750:
  3580. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  3581. REO_DST_RING_SIZE_QCA6290);
  3582. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, true);
  3583. soc->ast_override_support = 1;
  3584. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3585. soc->cdp_soc.ol_ops->get_con_mode() ==
  3586. QDF_GLOBAL_MONITOR_MODE) {
  3587. int int_ctx;
  3588. for (int_ctx = 0; int_ctx < WLAN_CFG_INT_NUM_CONTEXTS; int_ctx++) {
  3589. soc->wlan_cfg_ctx->int_rx_ring_mask[int_ctx] = 0;
  3590. soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[int_ctx] = 0;
  3591. }
  3592. }
  3593. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  3594. break;
  3595. case TARGET_TYPE_KIWI:
  3596. case TARGET_TYPE_MANGO:
  3597. case TARGET_TYPE_PEACH:
  3598. soc->ast_override_support = 1;
  3599. soc->per_tid_basize_max_tid = 8;
  3600. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3601. soc->cdp_soc.ol_ops->get_con_mode() ==
  3602. QDF_GLOBAL_MONITOR_MODE) {
  3603. int int_ctx;
  3604. for (int_ctx = 0; int_ctx < WLAN_CFG_INT_NUM_CONTEXTS;
  3605. int_ctx++) {
  3606. soc->wlan_cfg_ctx->int_rx_ring_mask[int_ctx] = 0;
  3607. if (dp_is_monitor_mode_using_poll(soc))
  3608. soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[int_ctx] = 0;
  3609. }
  3610. }
  3611. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  3612. soc->wlan_cfg_ctx->num_rxdma_dst_rings_per_pdev = 1;
  3613. break;
  3614. case TARGET_TYPE_QCA8074:
  3615. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, true);
  3616. soc->da_war_enabled = true;
  3617. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3618. break;
  3619. case TARGET_TYPE_QCA8074V2:
  3620. case TARGET_TYPE_QCA6018:
  3621. case TARGET_TYPE_QCA9574:
  3622. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3623. soc->ast_override_support = 1;
  3624. soc->per_tid_basize_max_tid = 8;
  3625. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3626. soc->da_war_enabled = false;
  3627. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3628. break;
  3629. case TARGET_TYPE_QCN9000:
  3630. soc->ast_override_support = 1;
  3631. soc->da_war_enabled = false;
  3632. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3633. soc->per_tid_basize_max_tid = 8;
  3634. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3635. soc->lmac_polled_mode = 0;
  3636. soc->wbm_release_desc_rx_sg_support = 1;
  3637. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3638. break;
  3639. case TARGET_TYPE_QCA5018:
  3640. case TARGET_TYPE_QCN6122:
  3641. case TARGET_TYPE_QCN9160:
  3642. soc->ast_override_support = 1;
  3643. soc->da_war_enabled = false;
  3644. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3645. soc->per_tid_basize_max_tid = 8;
  3646. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_MAPS_11AX;
  3647. soc->disable_mac1_intr = 1;
  3648. soc->disable_mac2_intr = 1;
  3649. soc->wbm_release_desc_rx_sg_support = 1;
  3650. break;
  3651. case TARGET_TYPE_QCN9224:
  3652. soc->umac_reset_supported = true;
  3653. soc->ast_override_support = 1;
  3654. soc->da_war_enabled = false;
  3655. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3656. soc->per_tid_basize_max_tid = 8;
  3657. soc->wbm_release_desc_rx_sg_support = 1;
  3658. soc->rxdma2sw_rings_not_supported = 1;
  3659. soc->wbm_sg_last_msdu_war = 1;
  3660. soc->ast_offload_support = AST_OFFLOAD_ENABLE_STATUS;
  3661. soc->mec_fw_offload = FW_MEC_FW_OFFLOAD_ENABLED;
  3662. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3663. wlan_cfg_set_txmon_hw_support(soc->wlan_cfg_ctx, true);
  3664. soc->host_ast_db_enable = cfg_get(soc->ctrl_psoc,
  3665. CFG_DP_HOST_AST_DB_ENABLE);
  3666. soc->features.wds_ext_ast_override_enable = true;
  3667. break;
  3668. case TARGET_TYPE_QCA5332:
  3669. case TARGET_TYPE_QCN6432:
  3670. soc->umac_reset_supported = true;
  3671. soc->ast_override_support = 1;
  3672. soc->da_war_enabled = false;
  3673. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3674. soc->per_tid_basize_max_tid = 8;
  3675. soc->wbm_release_desc_rx_sg_support = 1;
  3676. soc->rxdma2sw_rings_not_supported = 1;
  3677. soc->wbm_sg_last_msdu_war = 1;
  3678. soc->ast_offload_support = AST_OFFLOAD_ENABLE_STATUS;
  3679. soc->mec_fw_offload = FW_MEC_FW_OFFLOAD_ENABLED;
  3680. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS_5332;
  3681. wlan_cfg_set_txmon_hw_support(soc->wlan_cfg_ctx, true);
  3682. soc->host_ast_db_enable = cfg_get(soc->ctrl_psoc,
  3683. CFG_DP_HOST_AST_DB_ENABLE);
  3684. soc->features.wds_ext_ast_override_enable = true;
  3685. break;
  3686. default:
  3687. qdf_print("%s: Unknown tgt type %d\n", __func__, target_type);
  3688. qdf_assert_always(0);
  3689. break;
  3690. }
  3691. dp_soc_cfg_dump(soc, target_type);
  3692. }
  3693. /**
  3694. * dp_soc_get_ap_mld_mode() - store ap mld mode from ini
  3695. * @soc: Opaque DP SOC handle
  3696. *
  3697. * Return: none
  3698. */
  3699. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3700. static inline void dp_soc_get_ap_mld_mode(struct dp_soc *soc)
  3701. {
  3702. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  3703. soc->mld_mode_ap =
  3704. soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  3705. CDP_CFG_MLD_NETDEV_MODE_AP);
  3706. }
  3707. qdf_info("DP mld_mode_ap-%u\n", soc->mld_mode_ap);
  3708. }
  3709. #else
  3710. static inline void dp_soc_get_ap_mld_mode(struct dp_soc *soc)
  3711. {
  3712. (void)soc;
  3713. }
  3714. #endif
  3715. /**
  3716. * dp_soc_init() - Initialize txrx SOC
  3717. * @soc: Opaque DP SOC handle
  3718. * @htc_handle: Opaque HTC handle
  3719. * @hif_handle: Opaque HIF handle
  3720. *
  3721. * Return: DP SOC handle on success, NULL on failure
  3722. */
  3723. void *dp_soc_init(struct dp_soc *soc, HTC_HANDLE htc_handle,
  3724. struct hif_opaque_softc *hif_handle)
  3725. {
  3726. struct htt_soc *htt_soc = (struct htt_soc *)soc->htt_handle;
  3727. bool is_monitor_mode = false;
  3728. uint8_t i;
  3729. int num_dp_msi;
  3730. bool ppeds_attached = false;
  3731. htt_soc = htt_soc_attach(soc, htc_handle);
  3732. if (!htt_soc)
  3733. goto fail1;
  3734. soc->htt_handle = htt_soc;
  3735. if (htt_soc_htc_prealloc(htt_soc) != QDF_STATUS_SUCCESS)
  3736. goto fail2;
  3737. htt_set_htc_handle(htt_soc, htc_handle);
  3738. dp_soc_cfg_init(soc);
  3739. dp_monitor_soc_cfg_init(soc);
  3740. /* Reset/Initialize wbm sg list and flags */
  3741. dp_rx_wbm_sg_list_reset(soc);
  3742. /* Note: Any SRNG ring initialization should happen only after
  3743. * Interrupt mode is set and followed by filling up the
  3744. * interrupt mask. IT SHOULD ALWAYS BE IN THIS ORDER.
  3745. */
  3746. dp_soc_set_interrupt_mode(soc);
  3747. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3748. soc->cdp_soc.ol_ops->get_con_mode() ==
  3749. QDF_GLOBAL_MONITOR_MODE) {
  3750. is_monitor_mode = true;
  3751. soc->curr_rx_pkt_tlv_size = soc->rx_mon_pkt_tlv_size;
  3752. } else {
  3753. soc->curr_rx_pkt_tlv_size = soc->rx_pkt_tlv_size;
  3754. }
  3755. num_dp_msi = dp_get_num_msi_available(soc, soc->intr_mode);
  3756. if (num_dp_msi < 0) {
  3757. dp_init_err("%pK: dp_interrupt assignment failed", soc);
  3758. goto fail3;
  3759. }
  3760. if (soc->arch_ops.ppeds_handle_attached)
  3761. ppeds_attached = soc->arch_ops.ppeds_handle_attached(soc);
  3762. wlan_cfg_fill_interrupt_mask(soc->wlan_cfg_ctx, num_dp_msi,
  3763. soc->intr_mode, is_monitor_mode,
  3764. ppeds_attached,
  3765. soc->umac_reset_supported);
  3766. /* initialize WBM_IDLE_LINK ring */
  3767. if (dp_hw_link_desc_ring_init(soc)) {
  3768. dp_init_err("%pK: dp_hw_link_desc_ring_init failed", soc);
  3769. goto fail3;
  3770. }
  3771. dp_link_desc_ring_replenish(soc, WLAN_INVALID_PDEV_ID);
  3772. if (dp_soc_srng_init(soc)) {
  3773. dp_init_err("%pK: dp_soc_srng_init failed", soc);
  3774. goto fail4;
  3775. }
  3776. if (htt_soc_initialize(soc->htt_handle, soc->ctrl_psoc,
  3777. htt_get_htc_handle(htt_soc),
  3778. soc->hal_soc, soc->osdev) == NULL)
  3779. goto fail5;
  3780. /* Initialize descriptors in TCL Rings */
  3781. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3782. hal_tx_init_data_ring(soc->hal_soc,
  3783. soc->tcl_data_ring[i].hal_srng);
  3784. }
  3785. if (dp_soc_tx_desc_sw_pools_init(soc)) {
  3786. dp_init_err("%pK: dp_tx_soc_attach failed", soc);
  3787. goto fail6;
  3788. }
  3789. if (soc->arch_ops.txrx_soc_ppeds_start) {
  3790. if (soc->arch_ops.txrx_soc_ppeds_start(soc)) {
  3791. dp_init_err("%pK: ppeds start failed", soc);
  3792. goto fail7;
  3793. }
  3794. }
  3795. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx,
  3796. cfg_get(soc->ctrl_psoc, CFG_DP_RX_HASH));
  3797. #ifdef WLAN_SUPPORT_RX_FLOW_TAG
  3798. wlan_cfg_set_rx_rr(soc->wlan_cfg_ctx,
  3799. cfg_get(soc->ctrl_psoc, CFG_DP_RX_RR));
  3800. #endif
  3801. soc->cce_disable = false;
  3802. soc->max_ast_ageout_count = MAX_AST_AGEOUT_COUNT;
  3803. soc->sta_mode_search_policy = DP_TX_ADDR_SEARCH_ADDR_POLICY;
  3804. qdf_mem_zero(&soc->vdev_id_map, sizeof(soc->vdev_id_map));
  3805. qdf_spinlock_create(&soc->vdev_map_lock);
  3806. qdf_atomic_init(&soc->num_tx_outstanding);
  3807. qdf_atomic_init(&soc->num_tx_exception);
  3808. soc->num_tx_allowed =
  3809. wlan_cfg_get_dp_soc_tx_device_limit(soc->wlan_cfg_ctx);
  3810. soc->num_tx_spl_allowed =
  3811. wlan_cfg_get_dp_soc_tx_spl_device_limit(soc->wlan_cfg_ctx);
  3812. soc->num_reg_tx_allowed = soc->num_tx_allowed - soc->num_tx_spl_allowed;
  3813. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  3814. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  3815. CDP_CFG_MAX_PEER_ID);
  3816. if (ret != -EINVAL)
  3817. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  3818. ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  3819. CDP_CFG_CCE_DISABLE);
  3820. if (ret == 1)
  3821. soc->cce_disable = true;
  3822. }
  3823. /*
  3824. * Skip registering hw ring interrupts for WMAC2 on IPQ6018
  3825. * and IPQ5018 WMAC2 is not there in these platforms.
  3826. */
  3827. if (hal_get_target_type(soc->hal_soc) == TARGET_TYPE_QCA6018 ||
  3828. soc->disable_mac2_intr)
  3829. dp_soc_disable_unused_mac_intr_mask(soc, 0x2);
  3830. /*
  3831. * Skip registering hw ring interrupts for WMAC1 on IPQ5018
  3832. * WMAC1 is not there in this platform.
  3833. */
  3834. if (soc->disable_mac1_intr)
  3835. dp_soc_disable_unused_mac_intr_mask(soc, 0x1);
  3836. /* setup the global rx defrag waitlist */
  3837. TAILQ_INIT(&soc->rx.defrag.waitlist);
  3838. soc->rx.defrag.timeout_ms =
  3839. wlan_cfg_get_rx_defrag_min_timeout(soc->wlan_cfg_ctx);
  3840. soc->rx.defrag.next_flush_ms = 0;
  3841. soc->rx.flags.defrag_timeout_check =
  3842. wlan_cfg_get_defrag_timeout_check(soc->wlan_cfg_ctx);
  3843. qdf_spinlock_create(&soc->rx.defrag.defrag_lock);
  3844. dp_monitor_soc_init(soc);
  3845. qdf_atomic_set(&soc->cmn_init_done, 1);
  3846. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  3847. qdf_spinlock_create(&soc->ast_lock);
  3848. dp_peer_mec_spinlock_create(soc);
  3849. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  3850. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  3851. INIT_RX_HW_STATS_LOCK(soc);
  3852. qdf_nbuf_queue_init(&soc->invalid_buf_queue);
  3853. /* fill the tx/rx cpu ring map*/
  3854. dp_soc_set_txrx_ring_map(soc);
  3855. TAILQ_INIT(&soc->inactive_peer_list);
  3856. qdf_spinlock_create(&soc->inactive_peer_list_lock);
  3857. TAILQ_INIT(&soc->inactive_vdev_list);
  3858. qdf_spinlock_create(&soc->inactive_vdev_list_lock);
  3859. qdf_spinlock_create(&soc->htt_stats.lock);
  3860. /* initialize work queue for stats processing */
  3861. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  3862. dp_reo_desc_deferred_freelist_create(soc);
  3863. dp_info("Mem stats: DMA = %u HEAP = %u SKB = %u",
  3864. qdf_dma_mem_stats_read(),
  3865. qdf_heap_mem_stats_read(),
  3866. qdf_skb_total_mem_stats_read());
  3867. soc->vdev_stats_id_map = 0;
  3868. dp_soc_get_ap_mld_mode(soc);
  3869. return soc;
  3870. fail7:
  3871. dp_soc_tx_desc_sw_pools_deinit(soc);
  3872. fail6:
  3873. htt_soc_htc_dealloc(soc->htt_handle);
  3874. fail5:
  3875. dp_soc_srng_deinit(soc);
  3876. fail4:
  3877. dp_hw_link_desc_ring_deinit(soc);
  3878. fail3:
  3879. htt_htc_pkt_pool_free(htt_soc);
  3880. fail2:
  3881. htt_soc_detach(htt_soc);
  3882. fail1:
  3883. return NULL;
  3884. }
  3885. #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG
  3886. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_init(struct dp_soc *soc)
  3887. {
  3888. QDF_STATUS status;
  3889. if (soc->init_tcl_cmd_cred_ring) {
  3890. status = dp_srng_init(soc, &soc->tcl_cmd_credit_ring,
  3891. TCL_CMD_CREDIT, 0, 0);
  3892. if (QDF_IS_STATUS_ERROR(status))
  3893. return status;
  3894. wlan_minidump_log(soc->tcl_cmd_credit_ring.base_vaddr_unaligned,
  3895. soc->tcl_cmd_credit_ring.alloc_size,
  3896. soc->ctrl_psoc,
  3897. WLAN_MD_DP_SRNG_TCL_CMD,
  3898. "wbm_desc_rel_ring");
  3899. }
  3900. return QDF_STATUS_SUCCESS;
  3901. }
  3902. static inline void dp_soc_tcl_cmd_cred_srng_deinit(struct dp_soc *soc)
  3903. {
  3904. if (soc->init_tcl_cmd_cred_ring) {
  3905. wlan_minidump_remove(soc->tcl_cmd_credit_ring.base_vaddr_unaligned,
  3906. soc->tcl_cmd_credit_ring.alloc_size,
  3907. soc->ctrl_psoc, WLAN_MD_DP_SRNG_TCL_CMD,
  3908. "wbm_desc_rel_ring");
  3909. dp_srng_deinit(soc, &soc->tcl_cmd_credit_ring,
  3910. TCL_CMD_CREDIT, 0);
  3911. }
  3912. }
  3913. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_alloc(struct dp_soc *soc)
  3914. {
  3915. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  3916. uint32_t entries;
  3917. QDF_STATUS status;
  3918. entries = wlan_cfg_get_dp_soc_tcl_cmd_credit_ring_size(soc_cfg_ctx);
  3919. if (soc->init_tcl_cmd_cred_ring) {
  3920. status = dp_srng_alloc(soc, &soc->tcl_cmd_credit_ring,
  3921. TCL_CMD_CREDIT, entries, 0);
  3922. if (QDF_IS_STATUS_ERROR(status))
  3923. return status;
  3924. }
  3925. return QDF_STATUS_SUCCESS;
  3926. }
  3927. static inline void dp_soc_tcl_cmd_cred_srng_free(struct dp_soc *soc)
  3928. {
  3929. if (soc->init_tcl_cmd_cred_ring)
  3930. dp_srng_free(soc, &soc->tcl_cmd_credit_ring);
  3931. }
  3932. inline void dp_tx_init_cmd_credit_ring(struct dp_soc *soc)
  3933. {
  3934. if (soc->init_tcl_cmd_cred_ring)
  3935. hal_tx_init_cmd_credit_ring(soc->hal_soc,
  3936. soc->tcl_cmd_credit_ring.hal_srng);
  3937. }
  3938. #else
  3939. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_init(struct dp_soc *soc)
  3940. {
  3941. return QDF_STATUS_SUCCESS;
  3942. }
  3943. static inline void dp_soc_tcl_cmd_cred_srng_deinit(struct dp_soc *soc)
  3944. {
  3945. }
  3946. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_alloc(struct dp_soc *soc)
  3947. {
  3948. return QDF_STATUS_SUCCESS;
  3949. }
  3950. static inline void dp_soc_tcl_cmd_cred_srng_free(struct dp_soc *soc)
  3951. {
  3952. }
  3953. inline void dp_tx_init_cmd_credit_ring(struct dp_soc *soc)
  3954. {
  3955. }
  3956. #endif
  3957. #ifndef WLAN_DP_DISABLE_TCL_STATUS_SRNG
  3958. static inline QDF_STATUS dp_soc_tcl_status_srng_init(struct dp_soc *soc)
  3959. {
  3960. QDF_STATUS status;
  3961. status = dp_srng_init(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0);
  3962. if (QDF_IS_STATUS_ERROR(status))
  3963. return status;
  3964. wlan_minidump_log(soc->tcl_status_ring.base_vaddr_unaligned,
  3965. soc->tcl_status_ring.alloc_size,
  3966. soc->ctrl_psoc,
  3967. WLAN_MD_DP_SRNG_TCL_STATUS,
  3968. "wbm_desc_rel_ring");
  3969. return QDF_STATUS_SUCCESS;
  3970. }
  3971. static inline void dp_soc_tcl_status_srng_deinit(struct dp_soc *soc)
  3972. {
  3973. wlan_minidump_remove(soc->tcl_status_ring.base_vaddr_unaligned,
  3974. soc->tcl_status_ring.alloc_size,
  3975. soc->ctrl_psoc, WLAN_MD_DP_SRNG_TCL_STATUS,
  3976. "wbm_desc_rel_ring");
  3977. dp_srng_deinit(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  3978. }
  3979. static inline QDF_STATUS dp_soc_tcl_status_srng_alloc(struct dp_soc *soc)
  3980. {
  3981. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  3982. uint32_t entries;
  3983. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3984. entries = wlan_cfg_get_dp_soc_tcl_status_ring_size(soc_cfg_ctx);
  3985. status = dp_srng_alloc(soc, &soc->tcl_status_ring,
  3986. TCL_STATUS, entries, 0);
  3987. return status;
  3988. }
  3989. static inline void dp_soc_tcl_status_srng_free(struct dp_soc *soc)
  3990. {
  3991. dp_srng_free(soc, &soc->tcl_status_ring);
  3992. }
  3993. #else
  3994. static inline QDF_STATUS dp_soc_tcl_status_srng_init(struct dp_soc *soc)
  3995. {
  3996. return QDF_STATUS_SUCCESS;
  3997. }
  3998. static inline void dp_soc_tcl_status_srng_deinit(struct dp_soc *soc)
  3999. {
  4000. }
  4001. static inline QDF_STATUS dp_soc_tcl_status_srng_alloc(struct dp_soc *soc)
  4002. {
  4003. return QDF_STATUS_SUCCESS;
  4004. }
  4005. static inline void dp_soc_tcl_status_srng_free(struct dp_soc *soc)
  4006. {
  4007. }
  4008. #endif
  4009. /**
  4010. * dp_soc_srng_deinit() - de-initialize soc srng rings
  4011. * @soc: Datapath soc handle
  4012. *
  4013. */
  4014. void dp_soc_srng_deinit(struct dp_soc *soc)
  4015. {
  4016. uint32_t i;
  4017. if (soc->arch_ops.txrx_soc_srng_deinit)
  4018. soc->arch_ops.txrx_soc_srng_deinit(soc);
  4019. /* Free the ring memories */
  4020. /* Common rings */
  4021. wlan_minidump_remove(soc->wbm_desc_rel_ring.base_vaddr_unaligned,
  4022. soc->wbm_desc_rel_ring.alloc_size,
  4023. soc->ctrl_psoc, WLAN_MD_DP_SRNG_WBM_DESC_REL,
  4024. "wbm_desc_rel_ring");
  4025. dp_srng_deinit(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  4026. /* Tx data rings */
  4027. for (i = 0; i < soc->num_tcl_data_rings; i++)
  4028. dp_deinit_tx_pair_by_index(soc, i);
  4029. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4030. dp_deinit_tx_pair_by_index(soc, IPA_TCL_DATA_RING_IDX);
  4031. dp_ipa_deinit_alt_tx_ring(soc);
  4032. }
  4033. /* TCL command and status rings */
  4034. dp_soc_tcl_cmd_cred_srng_deinit(soc);
  4035. dp_soc_tcl_status_srng_deinit(soc);
  4036. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4037. /* TODO: Get number of rings and ring sizes
  4038. * from wlan_cfg
  4039. */
  4040. wlan_minidump_remove(soc->reo_dest_ring[i].base_vaddr_unaligned,
  4041. soc->reo_dest_ring[i].alloc_size,
  4042. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_DEST,
  4043. "reo_dest_ring");
  4044. dp_srng_deinit(soc, &soc->reo_dest_ring[i], REO_DST, i);
  4045. }
  4046. /* REO reinjection ring */
  4047. wlan_minidump_remove(soc->reo_reinject_ring.base_vaddr_unaligned,
  4048. soc->reo_reinject_ring.alloc_size,
  4049. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_REINJECT,
  4050. "reo_reinject_ring");
  4051. dp_srng_deinit(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  4052. /* Rx release ring */
  4053. wlan_minidump_remove(soc->rx_rel_ring.base_vaddr_unaligned,
  4054. soc->rx_rel_ring.alloc_size,
  4055. soc->ctrl_psoc, WLAN_MD_DP_SRNG_RX_REL,
  4056. "reo_release_ring");
  4057. dp_srng_deinit(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  4058. /* Rx exception ring */
  4059. /* TODO: Better to store ring_type and ring_num in
  4060. * dp_srng during setup
  4061. */
  4062. wlan_minidump_remove(soc->reo_exception_ring.base_vaddr_unaligned,
  4063. soc->reo_exception_ring.alloc_size,
  4064. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_EXCEPTION,
  4065. "reo_exception_ring");
  4066. dp_srng_deinit(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  4067. /* REO command and status rings */
  4068. wlan_minidump_remove(soc->reo_cmd_ring.base_vaddr_unaligned,
  4069. soc->reo_cmd_ring.alloc_size,
  4070. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_CMD,
  4071. "reo_cmd_ring");
  4072. dp_srng_deinit(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  4073. wlan_minidump_remove(soc->reo_status_ring.base_vaddr_unaligned,
  4074. soc->reo_status_ring.alloc_size,
  4075. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_STATUS,
  4076. "reo_status_ring");
  4077. dp_srng_deinit(soc, &soc->reo_status_ring, REO_STATUS, 0);
  4078. }
  4079. /**
  4080. * dp_soc_srng_init() - Initialize soc level srng rings
  4081. * @soc: Datapath soc handle
  4082. *
  4083. * Return: QDF_STATUS_SUCCESS on success
  4084. * QDF_STATUS_E_FAILURE on failure
  4085. */
  4086. QDF_STATUS dp_soc_srng_init(struct dp_soc *soc)
  4087. {
  4088. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  4089. uint8_t i;
  4090. uint8_t wbm2_sw_rx_rel_ring_id;
  4091. soc_cfg_ctx = soc->wlan_cfg_ctx;
  4092. dp_enable_verbose_debug(soc);
  4093. /* WBM descriptor release ring */
  4094. if (dp_srng_init(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0)) {
  4095. dp_init_err("%pK: dp_srng_init failed for wbm_desc_rel_ring", soc);
  4096. goto fail1;
  4097. }
  4098. wlan_minidump_log(soc->wbm_desc_rel_ring.base_vaddr_unaligned,
  4099. soc->wbm_desc_rel_ring.alloc_size,
  4100. soc->ctrl_psoc,
  4101. WLAN_MD_DP_SRNG_WBM_DESC_REL,
  4102. "wbm_desc_rel_ring");
  4103. /* TCL command and status rings */
  4104. if (dp_soc_tcl_cmd_cred_srng_init(soc)) {
  4105. dp_init_err("%pK: dp_srng_init failed for tcl_cmd_ring", soc);
  4106. goto fail1;
  4107. }
  4108. if (dp_soc_tcl_status_srng_init(soc)) {
  4109. dp_init_err("%pK: dp_srng_init failed for tcl_status_ring", soc);
  4110. goto fail1;
  4111. }
  4112. /* REO reinjection ring */
  4113. if (dp_srng_init(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0)) {
  4114. dp_init_err("%pK: dp_srng_init failed for reo_reinject_ring", soc);
  4115. goto fail1;
  4116. }
  4117. wlan_minidump_log(soc->reo_reinject_ring.base_vaddr_unaligned,
  4118. soc->reo_reinject_ring.alloc_size,
  4119. soc->ctrl_psoc,
  4120. WLAN_MD_DP_SRNG_REO_REINJECT,
  4121. "reo_reinject_ring");
  4122. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc_cfg_ctx);
  4123. /* Rx release ring */
  4124. if (dp_srng_init(soc, &soc->rx_rel_ring, WBM2SW_RELEASE,
  4125. wbm2_sw_rx_rel_ring_id, 0)) {
  4126. dp_init_err("%pK: dp_srng_init failed for rx_rel_ring", soc);
  4127. goto fail1;
  4128. }
  4129. wlan_minidump_log(soc->rx_rel_ring.base_vaddr_unaligned,
  4130. soc->rx_rel_ring.alloc_size,
  4131. soc->ctrl_psoc,
  4132. WLAN_MD_DP_SRNG_RX_REL,
  4133. "reo_release_ring");
  4134. /* Rx exception ring */
  4135. if (dp_srng_init(soc, &soc->reo_exception_ring,
  4136. REO_EXCEPTION, 0, MAX_REO_DEST_RINGS)) {
  4137. dp_init_err("%pK: dp_srng_init failed - reo_exception", soc);
  4138. goto fail1;
  4139. }
  4140. wlan_minidump_log(soc->reo_exception_ring.base_vaddr_unaligned,
  4141. soc->reo_exception_ring.alloc_size,
  4142. soc->ctrl_psoc,
  4143. WLAN_MD_DP_SRNG_REO_EXCEPTION,
  4144. "reo_exception_ring");
  4145. /* REO command and status rings */
  4146. if (dp_srng_init(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0)) {
  4147. dp_init_err("%pK: dp_srng_init failed for reo_cmd_ring", soc);
  4148. goto fail1;
  4149. }
  4150. wlan_minidump_log(soc->reo_cmd_ring.base_vaddr_unaligned,
  4151. soc->reo_cmd_ring.alloc_size,
  4152. soc->ctrl_psoc,
  4153. WLAN_MD_DP_SRNG_REO_CMD,
  4154. "reo_cmd_ring");
  4155. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  4156. TAILQ_INIT(&soc->rx.reo_cmd_list);
  4157. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  4158. if (dp_srng_init(soc, &soc->reo_status_ring, REO_STATUS, 0, 0)) {
  4159. dp_init_err("%pK: dp_srng_init failed for reo_status_ring", soc);
  4160. goto fail1;
  4161. }
  4162. wlan_minidump_log(soc->reo_status_ring.base_vaddr_unaligned,
  4163. soc->reo_status_ring.alloc_size,
  4164. soc->ctrl_psoc,
  4165. WLAN_MD_DP_SRNG_REO_STATUS,
  4166. "reo_status_ring");
  4167. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  4168. if (dp_init_tx_ring_pair_by_index(soc, i))
  4169. goto fail1;
  4170. }
  4171. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4172. if (dp_init_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX))
  4173. goto fail1;
  4174. if (dp_ipa_init_alt_tx_ring(soc))
  4175. goto fail1;
  4176. }
  4177. dp_create_ext_stats_event(soc);
  4178. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4179. /* Initialize REO destination ring */
  4180. if (dp_srng_init(soc, &soc->reo_dest_ring[i], REO_DST, i, 0)) {
  4181. dp_init_err("%pK: dp_srng_init failed for reo_dest_ringn", soc);
  4182. goto fail1;
  4183. }
  4184. wlan_minidump_log(soc->reo_dest_ring[i].base_vaddr_unaligned,
  4185. soc->reo_dest_ring[i].alloc_size,
  4186. soc->ctrl_psoc,
  4187. WLAN_MD_DP_SRNG_REO_DEST,
  4188. "reo_dest_ring");
  4189. }
  4190. if (soc->arch_ops.txrx_soc_srng_init) {
  4191. if (soc->arch_ops.txrx_soc_srng_init(soc)) {
  4192. dp_init_err("%pK: dp_srng_init failed for arch rings",
  4193. soc);
  4194. goto fail1;
  4195. }
  4196. }
  4197. return QDF_STATUS_SUCCESS;
  4198. fail1:
  4199. /*
  4200. * Cleanup will be done as part of soc_detach, which will
  4201. * be called on pdev attach failure
  4202. */
  4203. dp_soc_srng_deinit(soc);
  4204. return QDF_STATUS_E_FAILURE;
  4205. }
  4206. /**
  4207. * dp_soc_srng_free() - free soc level srng rings
  4208. * @soc: Datapath soc handle
  4209. *
  4210. */
  4211. void dp_soc_srng_free(struct dp_soc *soc)
  4212. {
  4213. uint32_t i;
  4214. if (soc->arch_ops.txrx_soc_srng_free)
  4215. soc->arch_ops.txrx_soc_srng_free(soc);
  4216. dp_srng_free(soc, &soc->wbm_desc_rel_ring);
  4217. for (i = 0; i < soc->num_tcl_data_rings; i++)
  4218. dp_free_tx_ring_pair_by_index(soc, i);
  4219. /* Free IPA rings for TCL_TX and TCL_COMPL ring */
  4220. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4221. dp_free_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX);
  4222. dp_ipa_free_alt_tx_ring(soc);
  4223. }
  4224. dp_soc_tcl_cmd_cred_srng_free(soc);
  4225. dp_soc_tcl_status_srng_free(soc);
  4226. for (i = 0; i < soc->num_reo_dest_rings; i++)
  4227. dp_srng_free(soc, &soc->reo_dest_ring[i]);
  4228. dp_srng_free(soc, &soc->reo_reinject_ring);
  4229. dp_srng_free(soc, &soc->rx_rel_ring);
  4230. dp_srng_free(soc, &soc->reo_exception_ring);
  4231. dp_srng_free(soc, &soc->reo_cmd_ring);
  4232. dp_srng_free(soc, &soc->reo_status_ring);
  4233. }
  4234. /**
  4235. * dp_soc_srng_alloc() - Allocate memory for soc level srng rings
  4236. * @soc: Datapath soc handle
  4237. *
  4238. * Return: QDF_STATUS_SUCCESS on success
  4239. * QDF_STATUS_E_NOMEM on failure
  4240. */
  4241. QDF_STATUS dp_soc_srng_alloc(struct dp_soc *soc)
  4242. {
  4243. uint32_t entries;
  4244. uint32_t i;
  4245. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  4246. uint32_t cached = WLAN_CFG_DST_RING_CACHED_DESC;
  4247. uint32_t reo_dst_ring_size;
  4248. soc_cfg_ctx = soc->wlan_cfg_ctx;
  4249. /* sw2wbm link descriptor release ring */
  4250. entries = wlan_cfg_get_dp_soc_wbm_release_ring_size(soc_cfg_ctx);
  4251. if (dp_srng_alloc(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE,
  4252. entries, 0)) {
  4253. dp_init_err("%pK: dp_srng_alloc failed for wbm_desc_rel_ring", soc);
  4254. goto fail1;
  4255. }
  4256. /* TCL command and status rings */
  4257. if (dp_soc_tcl_cmd_cred_srng_alloc(soc)) {
  4258. dp_init_err("%pK: dp_srng_alloc failed for tcl_cmd_ring", soc);
  4259. goto fail1;
  4260. }
  4261. if (dp_soc_tcl_status_srng_alloc(soc)) {
  4262. dp_init_err("%pK: dp_srng_alloc failed for tcl_status_ring", soc);
  4263. goto fail1;
  4264. }
  4265. /* REO reinjection ring */
  4266. entries = wlan_cfg_get_dp_soc_reo_reinject_ring_size(soc_cfg_ctx);
  4267. if (dp_srng_alloc(soc, &soc->reo_reinject_ring, REO_REINJECT,
  4268. entries, 0)) {
  4269. dp_init_err("%pK: dp_srng_alloc failed for reo_reinject_ring", soc);
  4270. goto fail1;
  4271. }
  4272. /* Rx release ring */
  4273. entries = wlan_cfg_get_dp_soc_rx_release_ring_size(soc_cfg_ctx);
  4274. if (dp_srng_alloc(soc, &soc->rx_rel_ring, WBM2SW_RELEASE,
  4275. entries, 0)) {
  4276. dp_init_err("%pK: dp_srng_alloc failed for rx_rel_ring", soc);
  4277. goto fail1;
  4278. }
  4279. /* Rx exception ring */
  4280. entries = wlan_cfg_get_dp_soc_reo_exception_ring_size(soc_cfg_ctx);
  4281. if (dp_srng_alloc(soc, &soc->reo_exception_ring, REO_EXCEPTION,
  4282. entries, 0)) {
  4283. dp_init_err("%pK: dp_srng_alloc failed - reo_exception", soc);
  4284. goto fail1;
  4285. }
  4286. /* REO command and status rings */
  4287. entries = wlan_cfg_get_dp_soc_reo_cmd_ring_size(soc_cfg_ctx);
  4288. if (dp_srng_alloc(soc, &soc->reo_cmd_ring, REO_CMD, entries, 0)) {
  4289. dp_init_err("%pK: dp_srng_alloc failed for reo_cmd_ring", soc);
  4290. goto fail1;
  4291. }
  4292. entries = wlan_cfg_get_dp_soc_reo_status_ring_size(soc_cfg_ctx);
  4293. if (dp_srng_alloc(soc, &soc->reo_status_ring, REO_STATUS,
  4294. entries, 0)) {
  4295. dp_init_err("%pK: dp_srng_alloc failed for reo_status_ring", soc);
  4296. goto fail1;
  4297. }
  4298. reo_dst_ring_size = wlan_cfg_get_reo_dst_ring_size(soc_cfg_ctx);
  4299. /* Disable cached desc if NSS offload is enabled */
  4300. if (wlan_cfg_get_dp_soc_nss_cfg(soc_cfg_ctx))
  4301. cached = 0;
  4302. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  4303. if (dp_alloc_tx_ring_pair_by_index(soc, i))
  4304. goto fail1;
  4305. }
  4306. /* IPA rings for TCL_TX and TX_COMP will be allocated here */
  4307. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4308. if (dp_alloc_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX))
  4309. goto fail1;
  4310. if (dp_ipa_alloc_alt_tx_ring(soc))
  4311. goto fail1;
  4312. }
  4313. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4314. /* Setup REO destination ring */
  4315. if (dp_srng_alloc(soc, &soc->reo_dest_ring[i], REO_DST,
  4316. reo_dst_ring_size, cached)) {
  4317. dp_init_err("%pK: dp_srng_alloc failed for reo_dest_ring", soc);
  4318. goto fail1;
  4319. }
  4320. }
  4321. if (soc->arch_ops.txrx_soc_srng_alloc) {
  4322. if (soc->arch_ops.txrx_soc_srng_alloc(soc)) {
  4323. dp_init_err("%pK: dp_srng_alloc failed for arch rings",
  4324. soc);
  4325. goto fail1;
  4326. }
  4327. }
  4328. return QDF_STATUS_SUCCESS;
  4329. fail1:
  4330. dp_soc_srng_free(soc);
  4331. return QDF_STATUS_E_NOMEM;
  4332. }
  4333. /**
  4334. * dp_soc_cfg_attach() - set target specific configuration in
  4335. * dp soc cfg.
  4336. * @soc: dp soc handle
  4337. */
  4338. void dp_soc_cfg_attach(struct dp_soc *soc)
  4339. {
  4340. int target_type;
  4341. int nss_cfg = 0;
  4342. target_type = hal_get_target_type(soc->hal_soc);
  4343. switch (target_type) {
  4344. case TARGET_TYPE_QCA6290:
  4345. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  4346. REO_DST_RING_SIZE_QCA6290);
  4347. break;
  4348. case TARGET_TYPE_QCA6390:
  4349. case TARGET_TYPE_QCA6490:
  4350. case TARGET_TYPE_QCA6750:
  4351. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  4352. REO_DST_RING_SIZE_QCA6290);
  4353. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4354. break;
  4355. case TARGET_TYPE_KIWI:
  4356. case TARGET_TYPE_MANGO:
  4357. case TARGET_TYPE_PEACH:
  4358. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4359. break;
  4360. case TARGET_TYPE_QCA8074:
  4361. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4362. break;
  4363. case TARGET_TYPE_QCA8074V2:
  4364. case TARGET_TYPE_QCA6018:
  4365. case TARGET_TYPE_QCA9574:
  4366. case TARGET_TYPE_QCN6122:
  4367. case TARGET_TYPE_QCA5018:
  4368. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4369. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4370. break;
  4371. case TARGET_TYPE_QCN9160:
  4372. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4373. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4374. break;
  4375. case TARGET_TYPE_QCN9000:
  4376. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4377. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4378. break;
  4379. case TARGET_TYPE_QCN9224:
  4380. case TARGET_TYPE_QCA5332:
  4381. case TARGET_TYPE_QCN6432:
  4382. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4383. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4384. break;
  4385. default:
  4386. qdf_print("%s: Unknown tgt type %d\n", __func__, target_type);
  4387. qdf_assert_always(0);
  4388. break;
  4389. }
  4390. if (soc->cdp_soc.ol_ops->get_soc_nss_cfg)
  4391. nss_cfg = soc->cdp_soc.ol_ops->get_soc_nss_cfg(soc->ctrl_psoc);
  4392. wlan_cfg_set_dp_soc_nss_cfg(soc->wlan_cfg_ctx, nss_cfg);
  4393. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  4394. wlan_cfg_set_num_tx_desc_pool(soc->wlan_cfg_ctx, 0);
  4395. wlan_cfg_set_num_tx_ext_desc_pool(soc->wlan_cfg_ctx, 0);
  4396. wlan_cfg_set_num_tx_desc(soc->wlan_cfg_ctx, 0);
  4397. wlan_cfg_set_num_tx_ext_desc(soc->wlan_cfg_ctx, 0);
  4398. soc->init_tcl_cmd_cred_ring = false;
  4399. soc->num_tcl_data_rings =
  4400. wlan_cfg_num_nss_tcl_data_rings(soc->wlan_cfg_ctx);
  4401. soc->num_reo_dest_rings =
  4402. wlan_cfg_num_nss_reo_dest_rings(soc->wlan_cfg_ctx);
  4403. } else {
  4404. soc->init_tcl_cmd_cred_ring = true;
  4405. soc->num_tx_comp_rings =
  4406. wlan_cfg_num_tx_comp_rings(soc->wlan_cfg_ctx);
  4407. soc->num_tcl_data_rings =
  4408. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  4409. soc->num_reo_dest_rings =
  4410. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  4411. }
  4412. }
  4413. void dp_pdev_set_default_reo(struct dp_pdev *pdev)
  4414. {
  4415. struct dp_soc *soc = pdev->soc;
  4416. switch (pdev->pdev_id) {
  4417. case 0:
  4418. pdev->reo_dest =
  4419. wlan_cfg_radio0_default_reo_get(soc->wlan_cfg_ctx);
  4420. break;
  4421. case 1:
  4422. pdev->reo_dest =
  4423. wlan_cfg_radio1_default_reo_get(soc->wlan_cfg_ctx);
  4424. break;
  4425. case 2:
  4426. pdev->reo_dest =
  4427. wlan_cfg_radio2_default_reo_get(soc->wlan_cfg_ctx);
  4428. break;
  4429. default:
  4430. dp_init_err("%pK: Invalid pdev_id %d for reo selection",
  4431. soc, pdev->pdev_id);
  4432. break;
  4433. }
  4434. }