dp_rings_main.c 144 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_ipa_obj_mgmt_api.h>
  20. #include <qdf_types.h>
  21. #include <qdf_lock.h>
  22. #include <qdf_net_types.h>
  23. #include <qdf_lro.h>
  24. #include <qdf_module.h>
  25. #include <hal_hw_headers.h>
  26. #include <hal_api.h>
  27. #include <hif.h>
  28. #include <htt.h>
  29. #include <wdi_event.h>
  30. #include <queue.h>
  31. #include "dp_types.h"
  32. #include "dp_rings.h"
  33. #include "dp_internal.h"
  34. #include "dp_tx.h"
  35. #include "dp_tx_desc.h"
  36. #include "dp_rx.h"
  37. #ifdef DP_RATETABLE_SUPPORT
  38. #include "dp_ratetable.h"
  39. #endif
  40. #include <cdp_txrx_handle.h>
  41. #include <wlan_cfg.h>
  42. #include <wlan_utility.h>
  43. #include "cdp_txrx_cmn_struct.h"
  44. #include "cdp_txrx_stats_struct.h"
  45. #include "cdp_txrx_cmn_reg.h"
  46. #include <qdf_util.h>
  47. #include "dp_peer.h"
  48. #include "htt_stats.h"
  49. #include "dp_htt.h"
  50. #include "htt_ppdu_stats.h"
  51. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  52. #include "cfg_ucfg_api.h"
  53. #include <wlan_module_ids.h>
  54. #ifdef WIFI_MONITOR_SUPPORT
  55. #include <dp_mon.h>
  56. #endif
  57. #ifdef WLAN_FEATURE_STATS_EXT
  58. #define INIT_RX_HW_STATS_LOCK(_soc) \
  59. qdf_spinlock_create(&(_soc)->rx_hw_stats_lock)
  60. #define DEINIT_RX_HW_STATS_LOCK(_soc) \
  61. qdf_spinlock_destroy(&(_soc)->rx_hw_stats_lock)
  62. #else
  63. #define INIT_RX_HW_STATS_LOCK(_soc) /* no op */
  64. #define DEINIT_RX_HW_STATS_LOCK(_soc) /* no op */
  65. #endif
  66. #ifdef QCA_DP_ENABLE_TX_COMP_RING4
  67. #define TXCOMP_RING4_NUM 3
  68. #else
  69. #define TXCOMP_RING4_NUM WBM2SW_TXCOMP_RING4_NUM
  70. #endif
  71. static QDF_STATUS dp_init_tx_ring_pair_by_index(struct dp_soc *soc,
  72. uint8_t index);
  73. static void dp_deinit_tx_pair_by_index(struct dp_soc *soc, int index);
  74. static void dp_free_tx_ring_pair_by_index(struct dp_soc *soc, uint8_t index);
  75. static QDF_STATUS dp_alloc_tx_ring_pair_by_index(struct dp_soc *soc,
  76. uint8_t index);
  77. /* default_dscp_tid_map - Default DSCP-TID mapping
  78. *
  79. * DSCP TID
  80. * 000000 0
  81. * 001000 1
  82. * 010000 2
  83. * 011000 3
  84. * 100000 4
  85. * 101000 5
  86. * 110000 6
  87. * 111000 7
  88. */
  89. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 1, 1, 1, 1, 1, 1, 1, 1,
  92. 2, 2, 2, 2, 2, 2, 2, 2,
  93. 3, 3, 3, 3, 3, 3, 3, 3,
  94. 4, 4, 4, 4, 4, 4, 4, 4,
  95. 5, 5, 5, 5, 5, 5, 5, 5,
  96. 6, 6, 6, 6, 6, 6, 6, 6,
  97. 7, 7, 7, 7, 7, 7, 7, 7,
  98. };
  99. /* default_pcp_tid_map - Default PCP-TID mapping
  100. *
  101. * PCP TID
  102. * 000 0
  103. * 001 1
  104. * 010 2
  105. * 011 3
  106. * 100 4
  107. * 101 5
  108. * 110 6
  109. * 111 7
  110. */
  111. static uint8_t default_pcp_tid_map[PCP_TID_MAP_MAX] = {
  112. 0, 1, 2, 3, 4, 5, 6, 7,
  113. };
  114. uint8_t
  115. dp_cpu_ring_map[DP_NSS_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS_MAX] = {
  116. {0x0, 0x1, 0x2, 0x0, 0x0, 0x1, 0x2, 0x0, 0x0, 0x1, 0x2},
  117. {0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1},
  118. {0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0},
  119. {0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2},
  120. {0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3},
  121. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  122. {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1}
  123. #endif
  124. };
  125. qdf_export_symbol(dp_cpu_ring_map);
  126. /**
  127. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  128. * @soc: DP soc handle
  129. * @ring_type: ring type
  130. * @ring_num: ring_num
  131. *
  132. * Return: 0 if the ring is not offloaded, non-0 if it is offloaded
  133. */
  134. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc,
  135. enum hal_ring_type ring_type,
  136. int ring_num)
  137. {
  138. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  139. uint8_t status = 0;
  140. switch (ring_type) {
  141. case WBM2SW_RELEASE:
  142. case REO_DST:
  143. case RXDMA_BUF:
  144. case REO_EXCEPTION:
  145. status = ((nss_config) & (1 << ring_num));
  146. break;
  147. default:
  148. break;
  149. }
  150. return status;
  151. }
  152. /* MCL specific functions */
  153. #if defined(DP_CON_MON)
  154. #ifdef DP_CON_MON_MSI_ENABLED
  155. /**
  156. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  157. * @soc: pointer to dp_soc handle
  158. * @intr_ctx_num: interrupt context number for which mon mask is needed
  159. *
  160. * For MCL, monitor mode rings are being processed in timer contexts (polled).
  161. * This function is returning 0, since in interrupt mode(softirq based RX),
  162. * we donot want to process monitor mode rings in a softirq.
  163. *
  164. * So, in case packet log is enabled for SAP/STA/P2P modes,
  165. * regular interrupt processing will not process monitor mode rings. It would be
  166. * done in a separate timer context.
  167. *
  168. * Return: 0
  169. */
  170. static inline uint32_t
  171. dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc, int intr_ctx_num)
  172. {
  173. return wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  174. }
  175. #else
  176. /**
  177. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  178. * @soc: pointer to dp_soc handle
  179. * @intr_ctx_num: interrupt context number for which mon mask is needed
  180. *
  181. * For MCL, monitor mode rings are being processed in timer contexts (polled).
  182. * This function is returning 0, since in interrupt mode(softirq based RX),
  183. * we donot want to process monitor mode rings in a softirq.
  184. *
  185. * So, in case packet log is enabled for SAP/STA/P2P modes,
  186. * regular interrupt processing will not process monitor mode rings. It would be
  187. * done in a separate timer context.
  188. *
  189. * Return: 0
  190. */
  191. static inline uint32_t
  192. dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc, int intr_ctx_num)
  193. {
  194. return 0;
  195. }
  196. #endif
  197. #else
  198. /**
  199. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  200. * @soc: pointer to dp_soc handle
  201. * @intr_ctx_num: interrupt context number for which mon mask is needed
  202. *
  203. * Return: mon mask value
  204. */
  205. static inline
  206. uint32_t dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc,
  207. int intr_ctx_num)
  208. {
  209. return wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  210. }
  211. void dp_soc_reset_mon_intr_mask(struct dp_soc *soc)
  212. {
  213. int i;
  214. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  215. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  216. soc->intr_ctx[i].host2rxdma_mon_ring_mask = 0;
  217. }
  218. }
  219. qdf_export_symbol(dp_soc_reset_mon_intr_mask);
  220. void dp_service_lmac_rings(void *arg)
  221. {
  222. struct dp_soc *soc = (struct dp_soc *)arg;
  223. int ring = 0, i;
  224. struct dp_pdev *pdev = NULL;
  225. union dp_rx_desc_list_elem_t *desc_list = NULL;
  226. union dp_rx_desc_list_elem_t *tail = NULL;
  227. /* Process LMAC interrupts */
  228. for (ring = 0 ; ring < MAX_NUM_LMAC_HW; ring++) {
  229. int mac_for_pdev = ring;
  230. struct dp_srng *rx_refill_buf_ring;
  231. pdev = dp_get_pdev_for_lmac_id(soc, mac_for_pdev);
  232. if (!pdev)
  233. continue;
  234. rx_refill_buf_ring = &soc->rx_refill_buf_ring[mac_for_pdev];
  235. dp_monitor_process(soc, NULL, mac_for_pdev,
  236. QCA_NAPI_BUDGET);
  237. for (i = 0;
  238. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  239. dp_rxdma_err_process(&soc->intr_ctx[i], soc,
  240. mac_for_pdev,
  241. QCA_NAPI_BUDGET);
  242. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF,
  243. mac_for_pdev))
  244. dp_rx_buffers_replenish(soc, mac_for_pdev,
  245. rx_refill_buf_ring,
  246. &soc->rx_desc_buf[mac_for_pdev],
  247. 0, &desc_list, &tail, false);
  248. }
  249. qdf_timer_mod(&soc->lmac_reap_timer, DP_INTR_POLL_TIMER_MS);
  250. }
  251. #endif
  252. /**
  253. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  254. * @ring_num: ring num of the ring being queried
  255. * @grp_mask: the grp_mask array for the ring type in question.
  256. *
  257. * The grp_mask array is indexed by group number and the bit fields correspond
  258. * to ring numbers. We are finding which interrupt group a ring belongs to.
  259. *
  260. * Return: the index in the grp_mask array with the ring number.
  261. * -QDF_STATUS_E_NOENT if no entry is found
  262. */
  263. static int dp_srng_find_ring_in_mask(int ring_num, uint8_t *grp_mask)
  264. {
  265. int ext_group_num;
  266. uint8_t mask = 1 << ring_num;
  267. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  268. ext_group_num++) {
  269. if (mask & grp_mask[ext_group_num])
  270. return ext_group_num;
  271. }
  272. return -QDF_STATUS_E_NOENT;
  273. }
  274. /**
  275. * dp_is_msi_group_number_invalid() - check msi_group_number valid or not
  276. * @soc: dp_soc
  277. * @msi_group_number: MSI group number.
  278. * @msi_data_count: MSI data count.
  279. *
  280. * Return: true if msi_group_number is invalid.
  281. */
  282. static bool dp_is_msi_group_number_invalid(struct dp_soc *soc,
  283. int msi_group_number,
  284. int msi_data_count)
  285. {
  286. if (soc && soc->osdev && soc->osdev->dev &&
  287. pld_is_one_msi(soc->osdev->dev))
  288. return false;
  289. return msi_group_number > msi_data_count;
  290. }
  291. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  292. /**
  293. * dp_is_reo_ring_num_in_nf_grp1() - Check if the current reo ring is part of
  294. * rx_near_full_grp1 mask
  295. * @soc: Datapath SoC Handle
  296. * @ring_num: REO ring number
  297. *
  298. * Return: 1 if the ring_num belongs to reo_nf_grp1,
  299. * 0, otherwise.
  300. */
  301. static inline int
  302. dp_is_reo_ring_num_in_nf_grp1(struct dp_soc *soc, int ring_num)
  303. {
  304. return (WLAN_CFG_RX_NEAR_FULL_IRQ_MASK_1 & (1 << ring_num));
  305. }
  306. /**
  307. * dp_is_reo_ring_num_in_nf_grp2() - Check if the current reo ring is part of
  308. * rx_near_full_grp2 mask
  309. * @soc: Datapath SoC Handle
  310. * @ring_num: REO ring number
  311. *
  312. * Return: 1 if the ring_num belongs to reo_nf_grp2,
  313. * 0, otherwise.
  314. */
  315. static inline int
  316. dp_is_reo_ring_num_in_nf_grp2(struct dp_soc *soc, int ring_num)
  317. {
  318. return (WLAN_CFG_RX_NEAR_FULL_IRQ_MASK_2 & (1 << ring_num));
  319. }
  320. /**
  321. * dp_srng_get_near_full_irq_mask() - Get near-full irq mask for a particular
  322. * ring type and number
  323. * @soc: Datapath SoC handle
  324. * @ring_type: SRNG type
  325. * @ring_num: ring num
  326. *
  327. * Return: near-full irq mask pointer
  328. */
  329. static inline
  330. uint8_t *dp_srng_get_near_full_irq_mask(struct dp_soc *soc,
  331. enum hal_ring_type ring_type,
  332. int ring_num)
  333. {
  334. struct wlan_cfg_dp_soc_ctxt *cfg_ctx = soc->wlan_cfg_ctx;
  335. uint8_t wbm2_sw_rx_rel_ring_id;
  336. uint8_t *nf_irq_mask = NULL;
  337. switch (ring_type) {
  338. case WBM2SW_RELEASE:
  339. wbm2_sw_rx_rel_ring_id =
  340. wlan_cfg_get_rx_rel_ring_id(cfg_ctx);
  341. if (ring_num != wbm2_sw_rx_rel_ring_id) {
  342. nf_irq_mask = &soc->wlan_cfg_ctx->
  343. int_tx_ring_near_full_irq_mask[0];
  344. }
  345. break;
  346. case REO_DST:
  347. if (dp_is_reo_ring_num_in_nf_grp1(soc, ring_num))
  348. nf_irq_mask =
  349. &soc->wlan_cfg_ctx->int_rx_ring_near_full_irq_1_mask[0];
  350. else if (dp_is_reo_ring_num_in_nf_grp2(soc, ring_num))
  351. nf_irq_mask =
  352. &soc->wlan_cfg_ctx->int_rx_ring_near_full_irq_2_mask[0];
  353. else
  354. qdf_assert(0);
  355. break;
  356. default:
  357. break;
  358. }
  359. return nf_irq_mask;
  360. }
  361. /**
  362. * dp_srng_set_msi2_ring_params() - Set the msi2 addr/data in the ring params
  363. * @soc: Datapath SoC handle
  364. * @ring_params: srng params handle
  365. * @msi2_addr: MSI2 addr to be set for the SRNG
  366. * @msi2_data: MSI2 data to be set for the SRNG
  367. *
  368. * Return: None
  369. */
  370. static inline
  371. void dp_srng_set_msi2_ring_params(struct dp_soc *soc,
  372. struct hal_srng_params *ring_params,
  373. qdf_dma_addr_t msi2_addr,
  374. uint32_t msi2_data)
  375. {
  376. ring_params->msi2_addr = msi2_addr;
  377. ring_params->msi2_data = msi2_data;
  378. }
  379. /**
  380. * dp_srng_msi2_setup() - Setup MSI2 details for near full IRQ of an SRNG
  381. * @soc: Datapath SoC handle
  382. * @ring_params: ring_params for SRNG
  383. * @ring_type: SENG type
  384. * @ring_num: ring number for the SRNG
  385. * @nf_msi_grp_num: near full msi group number
  386. *
  387. * Return: None
  388. */
  389. static inline void
  390. dp_srng_msi2_setup(struct dp_soc *soc,
  391. struct hal_srng_params *ring_params,
  392. int ring_type, int ring_num, int nf_msi_grp_num)
  393. {
  394. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  395. int msi_data_count, ret;
  396. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  397. &msi_data_count, &msi_data_start,
  398. &msi_irq_start);
  399. if (ret)
  400. return;
  401. if (nf_msi_grp_num < 0) {
  402. dp_init_info("%pK: ring near full IRQ not part of an ext_group; ring_type: %d,ring_num %d",
  403. soc, ring_type, ring_num);
  404. ring_params->msi2_addr = 0;
  405. ring_params->msi2_data = 0;
  406. return;
  407. }
  408. if (dp_is_msi_group_number_invalid(soc, nf_msi_grp_num,
  409. msi_data_count)) {
  410. dp_init_warn("%pK: 2 msi_groups will share an msi for near full IRQ; msi_group_num %d",
  411. soc, nf_msi_grp_num);
  412. QDF_ASSERT(0);
  413. }
  414. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  415. ring_params->nf_irq_support = 1;
  416. ring_params->msi2_addr = addr_low;
  417. ring_params->msi2_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  418. ring_params->msi2_data = (nf_msi_grp_num % msi_data_count)
  419. + msi_data_start;
  420. ring_params->flags |= HAL_SRNG_MSI_INTR;
  421. }
  422. /* Percentage of ring entries considered as nearly full */
  423. #define DP_NF_HIGH_THRESH_PERCENTAGE 75
  424. /* Percentage of ring entries considered as critically full */
  425. #define DP_NF_CRIT_THRESH_PERCENTAGE 90
  426. /* Percentage of ring entries considered as safe threshold */
  427. #define DP_NF_SAFE_THRESH_PERCENTAGE 50
  428. /**
  429. * dp_srng_configure_nf_interrupt_thresholds() - Configure the thresholds for
  430. * near full irq
  431. * @soc: Datapath SoC handle
  432. * @ring_params: ring params for SRNG
  433. * @ring_type: ring type
  434. */
  435. static inline void
  436. dp_srng_configure_nf_interrupt_thresholds(struct dp_soc *soc,
  437. struct hal_srng_params *ring_params,
  438. int ring_type)
  439. {
  440. if (ring_params->nf_irq_support) {
  441. ring_params->high_thresh = (ring_params->num_entries *
  442. DP_NF_HIGH_THRESH_PERCENTAGE) / 100;
  443. ring_params->crit_thresh = (ring_params->num_entries *
  444. DP_NF_CRIT_THRESH_PERCENTAGE) / 100;
  445. ring_params->safe_thresh = (ring_params->num_entries *
  446. DP_NF_SAFE_THRESH_PERCENTAGE) /100;
  447. }
  448. }
  449. /**
  450. * dp_srng_set_nf_thresholds() - Set the near full thresholds to srng data
  451. * structure from the ring params
  452. * @soc: Datapath SoC handle
  453. * @srng: SRNG handle
  454. * @ring_params: ring params for a SRNG
  455. *
  456. * Return: None
  457. */
  458. static inline void
  459. dp_srng_set_nf_thresholds(struct dp_soc *soc, struct dp_srng *srng,
  460. struct hal_srng_params *ring_params)
  461. {
  462. srng->crit_thresh = ring_params->crit_thresh;
  463. srng->safe_thresh = ring_params->safe_thresh;
  464. }
  465. #else
  466. static inline
  467. uint8_t *dp_srng_get_near_full_irq_mask(struct dp_soc *soc,
  468. enum hal_ring_type ring_type,
  469. int ring_num)
  470. {
  471. return NULL;
  472. }
  473. static inline
  474. void dp_srng_set_msi2_ring_params(struct dp_soc *soc,
  475. struct hal_srng_params *ring_params,
  476. qdf_dma_addr_t msi2_addr,
  477. uint32_t msi2_data)
  478. {
  479. }
  480. static inline void
  481. dp_srng_msi2_setup(struct dp_soc *soc,
  482. struct hal_srng_params *ring_params,
  483. int ring_type, int ring_num, int nf_msi_grp_num)
  484. {
  485. }
  486. static inline void
  487. dp_srng_configure_nf_interrupt_thresholds(struct dp_soc *soc,
  488. struct hal_srng_params *ring_params,
  489. int ring_type)
  490. {
  491. }
  492. static inline void
  493. dp_srng_set_nf_thresholds(struct dp_soc *soc, struct dp_srng *srng,
  494. struct hal_srng_params *ring_params)
  495. {
  496. }
  497. #endif
  498. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  499. enum hal_ring_type ring_type,
  500. int ring_num,
  501. int *reg_msi_grp_num,
  502. bool nf_irq_support,
  503. int *nf_msi_grp_num)
  504. {
  505. struct wlan_cfg_dp_soc_ctxt *cfg_ctx = soc->wlan_cfg_ctx;
  506. uint8_t *grp_mask, *nf_irq_mask = NULL;
  507. bool nf_irq_enabled = false;
  508. uint8_t wbm2_sw_rx_rel_ring_id;
  509. switch (ring_type) {
  510. case WBM2SW_RELEASE:
  511. wbm2_sw_rx_rel_ring_id =
  512. wlan_cfg_get_rx_rel_ring_id(cfg_ctx);
  513. if (ring_num == wbm2_sw_rx_rel_ring_id) {
  514. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  515. grp_mask = &cfg_ctx->int_rx_wbm_rel_ring_mask[0];
  516. ring_num = 0;
  517. } else if (ring_num == WBM2_SW_PPE_REL_RING_ID) {
  518. grp_mask = &cfg_ctx->int_ppeds_wbm_release_ring_mask[0];
  519. ring_num = 0;
  520. } else { /* dp_tx_comp_handler - soc->tx_comp_ring */
  521. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  522. nf_irq_mask = dp_srng_get_near_full_irq_mask(soc,
  523. ring_type,
  524. ring_num);
  525. if (nf_irq_mask)
  526. nf_irq_enabled = true;
  527. /*
  528. * Using ring 4 as 4th tx completion ring since ring 3
  529. * is Rx error ring
  530. */
  531. if (ring_num == WBM2SW_TXCOMP_RING4_NUM)
  532. ring_num = TXCOMP_RING4_NUM;
  533. }
  534. break;
  535. case REO_EXCEPTION:
  536. /* dp_rx_err_process - &soc->reo_exception_ring */
  537. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  538. break;
  539. case REO_DST:
  540. /* dp_rx_process - soc->reo_dest_ring */
  541. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  542. nf_irq_mask = dp_srng_get_near_full_irq_mask(soc, ring_type,
  543. ring_num);
  544. if (nf_irq_mask)
  545. nf_irq_enabled = true;
  546. break;
  547. case REO_STATUS:
  548. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  549. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  550. break;
  551. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  552. case RXDMA_MONITOR_STATUS:
  553. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  554. case RXDMA_MONITOR_DST:
  555. /* dp_mon_process */
  556. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  557. break;
  558. case TX_MONITOR_DST:
  559. /* dp_tx_mon_process */
  560. grp_mask = &soc->wlan_cfg_ctx->int_tx_mon_ring_mask[0];
  561. break;
  562. case RXDMA_DST:
  563. /* dp_rxdma_err_process */
  564. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  565. break;
  566. case RXDMA_BUF:
  567. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  568. break;
  569. case RXDMA_MONITOR_BUF:
  570. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_mon_ring_mask[0];
  571. break;
  572. case TX_MONITOR_BUF:
  573. grp_mask = &soc->wlan_cfg_ctx->int_host2txmon_ring_mask[0];
  574. break;
  575. case REO2PPE:
  576. grp_mask = &soc->wlan_cfg_ctx->int_reo2ppe_ring_mask[0];
  577. break;
  578. case PPE2TCL:
  579. grp_mask = &soc->wlan_cfg_ctx->int_ppe2tcl_ring_mask[0];
  580. break;
  581. case TCL_DATA:
  582. /* CMD_CREDIT_RING is used as command in 8074 and credit in 9000 */
  583. case TCL_CMD_CREDIT:
  584. case REO_CMD:
  585. case SW2WBM_RELEASE:
  586. case WBM_IDLE_LINK:
  587. /* normally empty SW_TO_HW rings */
  588. return -QDF_STATUS_E_NOENT;
  589. break;
  590. case TCL_STATUS:
  591. case REO_REINJECT:
  592. /* misc unused rings */
  593. return -QDF_STATUS_E_NOENT;
  594. break;
  595. case CE_SRC:
  596. case CE_DST:
  597. case CE_DST_STATUS:
  598. /* CE_rings - currently handled by hif */
  599. default:
  600. return -QDF_STATUS_E_NOENT;
  601. break;
  602. }
  603. *reg_msi_grp_num = dp_srng_find_ring_in_mask(ring_num, grp_mask);
  604. if (nf_irq_support && nf_irq_enabled) {
  605. *nf_msi_grp_num = dp_srng_find_ring_in_mask(ring_num,
  606. nf_irq_mask);
  607. }
  608. return QDF_STATUS_SUCCESS;
  609. }
  610. /**
  611. * dp_get_num_msi_available()- API to get number of MSIs available
  612. * @soc: DP soc Handle
  613. * @interrupt_mode: Mode of interrupts
  614. *
  615. * Return: Number of MSIs available or 0 in case of integrated
  616. */
  617. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  618. static int dp_get_num_msi_available(struct dp_soc *soc, int interrupt_mode)
  619. {
  620. return 0;
  621. }
  622. #else
  623. static int dp_get_num_msi_available(struct dp_soc *soc, int interrupt_mode)
  624. {
  625. int msi_data_count;
  626. int msi_data_start;
  627. int msi_irq_start;
  628. int ret;
  629. if (interrupt_mode == DP_INTR_INTEGRATED) {
  630. return 0;
  631. } else if (interrupt_mode == DP_INTR_MSI || interrupt_mode ==
  632. DP_INTR_POLL) {
  633. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  634. &msi_data_count,
  635. &msi_data_start,
  636. &msi_irq_start);
  637. if (ret) {
  638. qdf_err("Unable to get DP MSI assignment %d",
  639. interrupt_mode);
  640. return -EINVAL;
  641. }
  642. return msi_data_count;
  643. }
  644. qdf_err("Interrupt mode invalid %d", interrupt_mode);
  645. return -EINVAL;
  646. }
  647. #endif
  648. #if defined(IPA_OFFLOAD) && defined(IPA_WDI3_VLAN_SUPPORT)
  649. static void
  650. dp_ipa_vlan_srng_msi_setup(struct hal_srng_params *ring_params, int ring_type,
  651. int ring_num)
  652. {
  653. if (wlan_ipa_is_vlan_enabled()) {
  654. if ((ring_type == REO_DST) &&
  655. (ring_num == IPA_ALT_REO_DEST_RING_IDX)) {
  656. ring_params->msi_addr = 0;
  657. ring_params->msi_data = 0;
  658. ring_params->flags &= ~HAL_SRNG_MSI_INTR;
  659. }
  660. }
  661. }
  662. #else
  663. static inline void
  664. dp_ipa_vlan_srng_msi_setup(struct hal_srng_params *ring_params, int ring_type,
  665. int ring_num)
  666. {
  667. }
  668. #endif
  669. static void dp_srng_msi_setup(struct dp_soc *soc, struct dp_srng *srng,
  670. struct hal_srng_params *ring_params,
  671. int ring_type, int ring_num)
  672. {
  673. int reg_msi_grp_num;
  674. /*
  675. * nf_msi_grp_num needs to be initialized with negative value,
  676. * to avoid configuring near-full msi for WBM2SW3 ring
  677. */
  678. int nf_msi_grp_num = -1;
  679. int msi_data_count;
  680. int ret;
  681. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  682. bool nf_irq_support;
  683. int vector;
  684. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  685. &msi_data_count, &msi_data_start,
  686. &msi_irq_start);
  687. if (ret)
  688. return;
  689. nf_irq_support = hal_srng_is_near_full_irq_supported(soc->hal_soc,
  690. ring_type,
  691. ring_num);
  692. ret = dp_srng_calculate_msi_group(soc, ring_type, ring_num,
  693. &reg_msi_grp_num,
  694. nf_irq_support,
  695. &nf_msi_grp_num);
  696. if (ret < 0) {
  697. dp_init_info("%pK: ring not part of an ext_group; ring_type: %d,ring_num %d",
  698. soc, ring_type, ring_num);
  699. ring_params->msi_addr = 0;
  700. ring_params->msi_data = 0;
  701. dp_srng_set_msi2_ring_params(soc, ring_params, 0, 0);
  702. return;
  703. }
  704. if (reg_msi_grp_num < 0) {
  705. dp_init_info("%pK: ring not part of an ext_group; ring_type: %d,ring_num %d",
  706. soc, ring_type, ring_num);
  707. ring_params->msi_addr = 0;
  708. ring_params->msi_data = 0;
  709. goto configure_msi2;
  710. }
  711. if (dp_is_msi_group_number_invalid(soc, reg_msi_grp_num,
  712. msi_data_count)) {
  713. dp_init_warn("%pK: 2 msi_groups will share an msi; msi_group_num %d",
  714. soc, reg_msi_grp_num);
  715. QDF_ASSERT(0);
  716. }
  717. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  718. ring_params->msi_addr = addr_low;
  719. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  720. ring_params->msi_data = (reg_msi_grp_num % msi_data_count)
  721. + msi_data_start;
  722. ring_params->flags |= HAL_SRNG_MSI_INTR;
  723. dp_ipa_vlan_srng_msi_setup(ring_params, ring_type, ring_num);
  724. dp_debug("ring type %u ring_num %u msi->data %u msi_addr %llx",
  725. ring_type, ring_num, ring_params->msi_data,
  726. (uint64_t)ring_params->msi_addr);
  727. vector = msi_irq_start + (reg_msi_grp_num % msi_data_count);
  728. if (soc->arch_ops.dp_register_ppeds_interrupts)
  729. if (soc->arch_ops.dp_register_ppeds_interrupts(soc, srng,
  730. vector,
  731. ring_type,
  732. ring_num))
  733. return;
  734. configure_msi2:
  735. if (!nf_irq_support) {
  736. dp_srng_set_msi2_ring_params(soc, ring_params, 0, 0);
  737. return;
  738. }
  739. dp_srng_msi2_setup(soc, ring_params, ring_type, ring_num,
  740. nf_msi_grp_num);
  741. }
  742. /**
  743. * dp_srng_configure_pointer_update_thresholds() - Retrieve pointer
  744. * update threshold value from wlan_cfg_ctx
  745. * @soc: device handle
  746. * @ring_params: per ring specific parameters
  747. * @ring_type: Ring type
  748. * @ring_num: Ring number for a given ring type
  749. * @num_entries: number of entries to fill
  750. *
  751. * Fill the ring params with the pointer update threshold
  752. * configuration parameters available in wlan_cfg_ctx
  753. *
  754. * Return: None
  755. */
  756. static void
  757. dp_srng_configure_pointer_update_thresholds(
  758. struct dp_soc *soc,
  759. struct hal_srng_params *ring_params,
  760. int ring_type, int ring_num,
  761. int num_entries)
  762. {
  763. if (ring_type == REO_DST) {
  764. ring_params->pointer_timer_threshold =
  765. wlan_cfg_get_pointer_timer_threshold_rx(
  766. soc->wlan_cfg_ctx);
  767. ring_params->pointer_num_threshold =
  768. wlan_cfg_get_pointer_num_threshold_rx(
  769. soc->wlan_cfg_ctx);
  770. }
  771. }
  772. #ifdef WLAN_DP_PER_RING_TYPE_CONFIG
  773. /**
  774. * dp_srng_configure_interrupt_thresholds() - Retrieve interrupt
  775. * threshold values from the wlan_srng_cfg table for each ring type
  776. * @soc: device handle
  777. * @ring_params: per ring specific parameters
  778. * @ring_type: Ring type
  779. * @ring_num: Ring number for a given ring type
  780. * @num_entries: number of entries to fill
  781. *
  782. * Fill the ring params with the interrupt threshold
  783. * configuration parameters available in the per ring type wlan_srng_cfg
  784. * table.
  785. *
  786. * Return: None
  787. */
  788. static void
  789. dp_srng_configure_interrupt_thresholds(struct dp_soc *soc,
  790. struct hal_srng_params *ring_params,
  791. int ring_type, int ring_num,
  792. int num_entries)
  793. {
  794. uint8_t wbm2_sw_rx_rel_ring_id;
  795. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc->wlan_cfg_ctx);
  796. if (ring_type == REO_DST) {
  797. ring_params->intr_timer_thres_us =
  798. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  799. ring_params->intr_batch_cntr_thres_entries =
  800. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  801. } else if (ring_type == WBM2SW_RELEASE &&
  802. (ring_num == wbm2_sw_rx_rel_ring_id)) {
  803. ring_params->intr_timer_thres_us =
  804. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  805. ring_params->intr_batch_cntr_thres_entries =
  806. wlan_cfg_get_int_batch_threshold_other(soc->wlan_cfg_ctx);
  807. } else {
  808. ring_params->intr_timer_thres_us =
  809. soc->wlan_srng_cfg[ring_type].timer_threshold;
  810. ring_params->intr_batch_cntr_thres_entries =
  811. soc->wlan_srng_cfg[ring_type].batch_count_threshold;
  812. }
  813. ring_params->low_threshold =
  814. soc->wlan_srng_cfg[ring_type].low_threshold;
  815. if (ring_params->low_threshold)
  816. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  817. dp_srng_configure_nf_interrupt_thresholds(soc, ring_params, ring_type);
  818. }
  819. #else
  820. static void
  821. dp_srng_configure_interrupt_thresholds(struct dp_soc *soc,
  822. struct hal_srng_params *ring_params,
  823. int ring_type, int ring_num,
  824. int num_entries)
  825. {
  826. uint8_t wbm2_sw_rx_rel_ring_id;
  827. bool rx_refill_lt_disable;
  828. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc->wlan_cfg_ctx);
  829. if (ring_type == REO_DST || ring_type == REO2PPE) {
  830. ring_params->intr_timer_thres_us =
  831. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  832. ring_params->intr_batch_cntr_thres_entries =
  833. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  834. } else if (ring_type == WBM2SW_RELEASE &&
  835. (ring_num < wbm2_sw_rx_rel_ring_id ||
  836. ring_num == WBM2SW_TXCOMP_RING4_NUM ||
  837. ring_num == WBM2_SW_PPE_REL_RING_ID)) {
  838. ring_params->intr_timer_thres_us =
  839. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  840. ring_params->intr_batch_cntr_thres_entries =
  841. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  842. } else if (ring_type == RXDMA_BUF) {
  843. rx_refill_lt_disable =
  844. wlan_cfg_get_dp_soc_rxdma_refill_lt_disable
  845. (soc->wlan_cfg_ctx);
  846. ring_params->intr_timer_thres_us =
  847. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  848. if (!rx_refill_lt_disable) {
  849. ring_params->low_threshold = num_entries >> 3;
  850. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  851. ring_params->intr_batch_cntr_thres_entries = 0;
  852. }
  853. } else {
  854. ring_params->intr_timer_thres_us =
  855. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  856. ring_params->intr_batch_cntr_thres_entries =
  857. wlan_cfg_get_int_batch_threshold_other(soc->wlan_cfg_ctx);
  858. }
  859. /* These rings donot require interrupt to host. Make them zero */
  860. switch (ring_type) {
  861. case REO_REINJECT:
  862. case REO_CMD:
  863. case TCL_DATA:
  864. case TCL_CMD_CREDIT:
  865. case TCL_STATUS:
  866. case WBM_IDLE_LINK:
  867. case SW2WBM_RELEASE:
  868. case SW2RXDMA_NEW:
  869. ring_params->intr_timer_thres_us = 0;
  870. ring_params->intr_batch_cntr_thres_entries = 0;
  871. break;
  872. case PPE2TCL:
  873. ring_params->intr_timer_thres_us =
  874. wlan_cfg_get_int_timer_threshold_ppe2tcl(soc->wlan_cfg_ctx);
  875. ring_params->intr_batch_cntr_thres_entries =
  876. wlan_cfg_get_int_batch_threshold_ppe2tcl(soc->wlan_cfg_ctx);
  877. break;
  878. }
  879. /* Enable low threshold interrupts for rx buffer rings (regular and
  880. * monitor buffer rings.
  881. * TODO: See if this is required for any other ring
  882. */
  883. if ((ring_type == RXDMA_MONITOR_BUF) ||
  884. (ring_type == RXDMA_MONITOR_STATUS ||
  885. (ring_type == TX_MONITOR_BUF))) {
  886. /* TODO: Setting low threshold to 1/8th of ring size
  887. * see if this needs to be configurable
  888. */
  889. ring_params->low_threshold = num_entries >> 3;
  890. ring_params->intr_timer_thres_us =
  891. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  892. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  893. ring_params->intr_batch_cntr_thres_entries = 0;
  894. }
  895. /* During initialisation monitor rings are only filled with
  896. * MON_BUF_MIN_ENTRIES entries. So low threshold needs to be set to
  897. * a value less than that. Low threshold value is reconfigured again
  898. * to 1/8th of the ring size when monitor vap is created.
  899. */
  900. if (ring_type == RXDMA_MONITOR_BUF)
  901. ring_params->low_threshold = MON_BUF_MIN_ENTRIES >> 1;
  902. /* In case of PCI chipsets, we dont have PPDU end interrupts,
  903. * so MONITOR STATUS ring is reaped by receiving MSI from srng.
  904. * Keep batch threshold as 8 so that interrupt is received for
  905. * every 4 packets in MONITOR_STATUS ring
  906. */
  907. if ((ring_type == RXDMA_MONITOR_STATUS) &&
  908. (soc->intr_mode == DP_INTR_MSI))
  909. ring_params->intr_batch_cntr_thres_entries = 4;
  910. }
  911. #endif
  912. #ifdef DISABLE_MON_RING_MSI_CFG
  913. /**
  914. * dp_skip_msi_cfg() - Check if msi cfg has to be skipped for ring_type
  915. * @soc: DP SoC context
  916. * @ring_type: sring type
  917. *
  918. * Return: True if msi cfg should be skipped for srng type else false
  919. */
  920. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  921. {
  922. if (ring_type == RXDMA_MONITOR_STATUS)
  923. return true;
  924. return false;
  925. }
  926. #else
  927. #ifdef DP_CON_MON_MSI_ENABLED
  928. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  929. {
  930. if (soc->cdp_soc.ol_ops->get_con_mode &&
  931. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE) {
  932. if (ring_type == REO_DST || ring_type == RXDMA_DST)
  933. return true;
  934. } else if (ring_type == RXDMA_MONITOR_STATUS) {
  935. return true;
  936. }
  937. return false;
  938. }
  939. #else
  940. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  941. {
  942. return false;
  943. }
  944. #endif /* DP_CON_MON_MSI_ENABLED */
  945. #endif /* DISABLE_MON_RING_MSI_CFG */
  946. QDF_STATUS dp_srng_init_idx(struct dp_soc *soc, struct dp_srng *srng,
  947. int ring_type, int ring_num, int mac_id,
  948. uint32_t idx)
  949. {
  950. bool idle_check;
  951. hal_soc_handle_t hal_soc = soc->hal_soc;
  952. struct hal_srng_params ring_params;
  953. if (srng->hal_srng) {
  954. dp_init_err("%pK: Ring type: %d, num:%d is already initialized",
  955. soc, ring_type, ring_num);
  956. return QDF_STATUS_SUCCESS;
  957. }
  958. /* memset the srng ring to zero */
  959. qdf_mem_zero(srng->base_vaddr_unaligned, srng->alloc_size);
  960. qdf_mem_zero(&ring_params, sizeof(struct hal_srng_params));
  961. ring_params.ring_base_paddr = srng->base_paddr_aligned;
  962. ring_params.ring_base_vaddr = srng->base_vaddr_aligned;
  963. ring_params.num_entries = srng->num_entries;
  964. dp_info("Ring type: %d, num:%d vaddr %pK paddr %pK entries %u",
  965. ring_type, ring_num,
  966. (void *)ring_params.ring_base_vaddr,
  967. (void *)ring_params.ring_base_paddr,
  968. ring_params.num_entries);
  969. if (soc->intr_mode == DP_INTR_MSI && !dp_skip_msi_cfg(soc, ring_type)) {
  970. dp_srng_msi_setup(soc, srng, &ring_params, ring_type, ring_num);
  971. dp_verbose_debug("Using MSI for ring_type: %d, ring_num %d",
  972. ring_type, ring_num);
  973. } else {
  974. ring_params.msi_data = 0;
  975. ring_params.msi_addr = 0;
  976. dp_srng_set_msi2_ring_params(soc, &ring_params, 0, 0);
  977. dp_verbose_debug("Skipping MSI for ring_type: %d, ring_num %d",
  978. ring_type, ring_num);
  979. }
  980. dp_srng_configure_interrupt_thresholds(soc, &ring_params,
  981. ring_type, ring_num,
  982. srng->num_entries);
  983. dp_srng_set_nf_thresholds(soc, srng, &ring_params);
  984. dp_srng_configure_pointer_update_thresholds(soc, &ring_params,
  985. ring_type, ring_num,
  986. srng->num_entries);
  987. if (srng->cached)
  988. ring_params.flags |= HAL_SRNG_CACHED_DESC;
  989. idle_check = dp_check_umac_reset_in_progress(soc);
  990. srng->hal_srng = hal_srng_setup_idx(hal_soc, ring_type, ring_num,
  991. mac_id, &ring_params, idle_check,
  992. idx);
  993. if (!srng->hal_srng) {
  994. dp_srng_free(soc, srng);
  995. return QDF_STATUS_E_FAILURE;
  996. }
  997. return QDF_STATUS_SUCCESS;
  998. }
  999. qdf_export_symbol(dp_srng_init_idx);
  1000. static int dp_process_rxdma_dst_ring(struct dp_soc *soc,
  1001. struct dp_intr *int_ctx,
  1002. int mac_for_pdev,
  1003. int total_budget)
  1004. {
  1005. uint32_t target_type;
  1006. target_type = hal_get_target_type(soc->hal_soc);
  1007. if (target_type == TARGET_TYPE_QCN9160)
  1008. return dp_monitor_process(soc, int_ctx,
  1009. mac_for_pdev, total_budget);
  1010. else
  1011. return dp_rxdma_err_process(int_ctx, soc, mac_for_pdev,
  1012. total_budget);
  1013. }
  1014. /**
  1015. * dp_process_lmac_rings() - Process LMAC rings
  1016. * @int_ctx: interrupt context
  1017. * @total_budget: budget of work which can be done
  1018. *
  1019. * Return: work done
  1020. */
  1021. static int dp_process_lmac_rings(struct dp_intr *int_ctx, int total_budget)
  1022. {
  1023. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1024. struct dp_soc *soc = int_ctx->soc;
  1025. uint32_t remaining_quota = total_budget;
  1026. struct dp_pdev *pdev = NULL;
  1027. uint32_t work_done = 0;
  1028. int budget = total_budget;
  1029. int ring = 0;
  1030. /* Process LMAC interrupts */
  1031. for (ring = 0 ; ring < MAX_NUM_LMAC_HW; ring++) {
  1032. int mac_for_pdev = ring;
  1033. pdev = dp_get_pdev_for_lmac_id(soc, mac_for_pdev);
  1034. if (!pdev)
  1035. continue;
  1036. if (int_ctx->rx_mon_ring_mask & (1 << mac_for_pdev)) {
  1037. work_done = dp_monitor_process(soc, int_ctx,
  1038. mac_for_pdev,
  1039. remaining_quota);
  1040. if (work_done)
  1041. intr_stats->num_rx_mon_ring_masks++;
  1042. budget -= work_done;
  1043. if (budget <= 0)
  1044. goto budget_done;
  1045. remaining_quota = budget;
  1046. }
  1047. if (int_ctx->tx_mon_ring_mask & (1 << mac_for_pdev)) {
  1048. work_done = dp_tx_mon_process(soc, int_ctx,
  1049. mac_for_pdev,
  1050. remaining_quota);
  1051. if (work_done)
  1052. intr_stats->num_tx_mon_ring_masks++;
  1053. budget -= work_done;
  1054. if (budget <= 0)
  1055. goto budget_done;
  1056. remaining_quota = budget;
  1057. }
  1058. if (int_ctx->rxdma2host_ring_mask &
  1059. (1 << mac_for_pdev)) {
  1060. work_done = dp_process_rxdma_dst_ring(soc, int_ctx,
  1061. mac_for_pdev,
  1062. remaining_quota);
  1063. if (work_done)
  1064. intr_stats->num_rxdma2host_ring_masks++;
  1065. budget -= work_done;
  1066. if (budget <= 0)
  1067. goto budget_done;
  1068. remaining_quota = budget;
  1069. }
  1070. if (int_ctx->host2rxdma_ring_mask & (1 << mac_for_pdev)) {
  1071. union dp_rx_desc_list_elem_t *desc_list = NULL;
  1072. union dp_rx_desc_list_elem_t *tail = NULL;
  1073. struct dp_srng *rx_refill_buf_ring;
  1074. struct rx_desc_pool *rx_desc_pool;
  1075. rx_desc_pool = &soc->rx_desc_buf[mac_for_pdev];
  1076. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx))
  1077. rx_refill_buf_ring =
  1078. &soc->rx_refill_buf_ring[mac_for_pdev];
  1079. else
  1080. rx_refill_buf_ring =
  1081. &soc->rx_refill_buf_ring[pdev->lmac_id];
  1082. intr_stats->num_host2rxdma_ring_masks++;
  1083. dp_rx_buffers_lt_replenish_simple(soc, mac_for_pdev,
  1084. rx_refill_buf_ring,
  1085. rx_desc_pool,
  1086. 0,
  1087. &desc_list,
  1088. &tail);
  1089. }
  1090. }
  1091. if (int_ctx->host2rxdma_mon_ring_mask)
  1092. dp_rx_mon_buf_refill(int_ctx);
  1093. if (int_ctx->host2txmon_ring_mask)
  1094. dp_tx_mon_buf_refill(int_ctx);
  1095. budget_done:
  1096. return total_budget - budget;
  1097. }
  1098. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1099. /**
  1100. * dp_service_near_full_srngs() - Bottom half handler to process the near
  1101. * full IRQ on a SRNG
  1102. * @dp_ctx: Datapath SoC handle
  1103. * @dp_budget: Number of SRNGs which can be processed in a single attempt
  1104. * without rescheduling
  1105. * @cpu: cpu id
  1106. *
  1107. * Return: remaining budget/quota for the soc device
  1108. */
  1109. static
  1110. uint32_t dp_service_near_full_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1111. {
  1112. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1113. struct dp_soc *soc = int_ctx->soc;
  1114. /*
  1115. * dp_service_near_full_srngs arch ops should be initialized always
  1116. * if the NEAR FULL IRQ feature is enabled.
  1117. */
  1118. return soc->arch_ops.dp_service_near_full_srngs(soc, int_ctx,
  1119. dp_budget);
  1120. }
  1121. #endif
  1122. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1123. uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1124. {
  1125. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1126. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1127. struct dp_soc *soc = int_ctx->soc;
  1128. int ring = 0;
  1129. int index;
  1130. uint32_t work_done = 0;
  1131. int budget = dp_budget;
  1132. uint8_t tx_mask = int_ctx->tx_ring_mask;
  1133. uint8_t rx_mask = int_ctx->rx_ring_mask;
  1134. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  1135. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  1136. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  1137. uint32_t remaining_quota = dp_budget;
  1138. qdf_atomic_set_bit(cpu, &soc->service_rings_running);
  1139. dp_verbose_debug("tx %x rx %x rx_err %x rx_wbm_rel %x reo_status %x rx_mon_ring %x host2rxdma %x rxdma2host %x\n",
  1140. tx_mask, rx_mask, rx_err_mask, rx_wbm_rel_mask,
  1141. reo_status_mask,
  1142. int_ctx->rx_mon_ring_mask,
  1143. int_ctx->host2rxdma_ring_mask,
  1144. int_ctx->rxdma2host_ring_mask);
  1145. /* Process Tx completion interrupts first to return back buffers */
  1146. for (index = 0; index < soc->num_tx_comp_rings; index++) {
  1147. if (!(1 << wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, index) & tx_mask))
  1148. continue;
  1149. work_done = dp_tx_comp_handler(int_ctx,
  1150. soc,
  1151. soc->tx_comp_ring[index].hal_srng,
  1152. index, remaining_quota);
  1153. if (work_done) {
  1154. intr_stats->num_tx_ring_masks[index]++;
  1155. dp_verbose_debug("tx mask 0x%x index %d, budget %d, work_done %d",
  1156. tx_mask, index, budget,
  1157. work_done);
  1158. }
  1159. budget -= work_done;
  1160. if (budget <= 0)
  1161. goto budget_done;
  1162. remaining_quota = budget;
  1163. }
  1164. /* Process REO Exception ring interrupt */
  1165. if (rx_err_mask) {
  1166. work_done = dp_rx_err_process(int_ctx, soc,
  1167. soc->reo_exception_ring.hal_srng,
  1168. remaining_quota);
  1169. if (work_done) {
  1170. intr_stats->num_rx_err_ring_masks++;
  1171. dp_verbose_debug("REO Exception Ring: work_done %d budget %d",
  1172. work_done, budget);
  1173. }
  1174. budget -= work_done;
  1175. if (budget <= 0) {
  1176. goto budget_done;
  1177. }
  1178. remaining_quota = budget;
  1179. }
  1180. /* Process Rx WBM release ring interrupt */
  1181. if (rx_wbm_rel_mask) {
  1182. work_done = dp_rx_wbm_err_process(int_ctx, soc,
  1183. soc->rx_rel_ring.hal_srng,
  1184. remaining_quota);
  1185. if (work_done) {
  1186. intr_stats->num_rx_wbm_rel_ring_masks++;
  1187. dp_verbose_debug("WBM Release Ring: work_done %d budget %d",
  1188. work_done, budget);
  1189. }
  1190. budget -= work_done;
  1191. if (budget <= 0) {
  1192. goto budget_done;
  1193. }
  1194. remaining_quota = budget;
  1195. }
  1196. /* Process Rx interrupts */
  1197. if (rx_mask) {
  1198. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1199. if (!(rx_mask & (1 << ring)))
  1200. continue;
  1201. work_done = soc->arch_ops.dp_rx_process(int_ctx,
  1202. soc->reo_dest_ring[ring].hal_srng,
  1203. ring,
  1204. remaining_quota);
  1205. if (work_done) {
  1206. intr_stats->num_rx_ring_masks[ring]++;
  1207. dp_verbose_debug("rx mask 0x%x ring %d, work_done %d budget %d",
  1208. rx_mask, ring,
  1209. work_done, budget);
  1210. budget -= work_done;
  1211. if (budget <= 0)
  1212. goto budget_done;
  1213. remaining_quota = budget;
  1214. }
  1215. }
  1216. }
  1217. if (reo_status_mask) {
  1218. if (dp_reo_status_ring_handler(int_ctx, soc))
  1219. int_ctx->intr_stats.num_reo_status_ring_masks++;
  1220. }
  1221. if (qdf_unlikely(!dp_monitor_is_vdev_timer_running(soc))) {
  1222. work_done = dp_process_lmac_rings(int_ctx, remaining_quota);
  1223. if (work_done) {
  1224. budget -= work_done;
  1225. if (budget <= 0)
  1226. goto budget_done;
  1227. remaining_quota = budget;
  1228. }
  1229. }
  1230. qdf_lro_flush(int_ctx->lro_ctx);
  1231. intr_stats->num_masks++;
  1232. budget_done:
  1233. qdf_atomic_clear_bit(cpu, &soc->service_rings_running);
  1234. if (soc->notify_fw_callback)
  1235. soc->notify_fw_callback(soc);
  1236. return dp_budget - budget;
  1237. }
  1238. #else /* QCA_HOST_MODE_WIFI_DISABLED */
  1239. uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1240. {
  1241. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1242. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1243. struct dp_soc *soc = int_ctx->soc;
  1244. uint32_t remaining_quota = dp_budget;
  1245. uint32_t work_done = 0;
  1246. int budget = dp_budget;
  1247. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  1248. if (reo_status_mask) {
  1249. if (dp_reo_status_ring_handler(int_ctx, soc))
  1250. int_ctx->intr_stats.num_reo_status_ring_masks++;
  1251. }
  1252. if (qdf_unlikely(!dp_monitor_is_vdev_timer_running(soc))) {
  1253. work_done = dp_process_lmac_rings(int_ctx, remaining_quota);
  1254. if (work_done) {
  1255. budget -= work_done;
  1256. if (budget <= 0)
  1257. goto budget_done;
  1258. remaining_quota = budget;
  1259. }
  1260. }
  1261. qdf_lro_flush(int_ctx->lro_ctx);
  1262. intr_stats->num_masks++;
  1263. budget_done:
  1264. return dp_budget - budget;
  1265. }
  1266. #endif /* QCA_HOST_MODE_WIFI_DISABLED */
  1267. #ifdef WLAN_FEATURE_DP_EVENT_HISTORY
  1268. static inline bool dp_is_mon_mask_valid(struct dp_soc *soc,
  1269. struct dp_intr *intr_ctx)
  1270. {
  1271. if (intr_ctx->rx_mon_ring_mask)
  1272. return true;
  1273. return false;
  1274. }
  1275. #else
  1276. static inline bool dp_is_mon_mask_valid(struct dp_soc *soc,
  1277. struct dp_intr *intr_ctx)
  1278. {
  1279. return false;
  1280. }
  1281. #endif
  1282. QDF_STATUS dp_soc_attach_poll(struct cdp_soc_t *txrx_soc)
  1283. {
  1284. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1285. int i;
  1286. int lmac_id = 0;
  1287. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1288. sizeof(soc->mon_intr_id_lmac_map), DP_MON_INVALID_LMAC_ID);
  1289. soc->intr_mode = DP_INTR_POLL;
  1290. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1291. soc->intr_ctx[i].dp_intr_id = i;
  1292. soc->intr_ctx[i].tx_ring_mask =
  1293. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1294. soc->intr_ctx[i].rx_ring_mask =
  1295. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1296. soc->intr_ctx[i].rx_mon_ring_mask =
  1297. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1298. soc->intr_ctx[i].rx_err_ring_mask =
  1299. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1300. soc->intr_ctx[i].rx_wbm_rel_ring_mask =
  1301. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1302. soc->intr_ctx[i].reo_status_ring_mask =
  1303. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1304. soc->intr_ctx[i].rxdma2host_ring_mask =
  1305. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1306. soc->intr_ctx[i].soc = soc;
  1307. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1308. if (dp_is_mon_mask_valid(soc, &soc->intr_ctx[i])) {
  1309. hif_event_history_init(soc->hif_handle, i);
  1310. soc->mon_intr_id_lmac_map[lmac_id] = i;
  1311. lmac_id++;
  1312. }
  1313. }
  1314. qdf_timer_init(soc->osdev, &soc->int_timer,
  1315. dp_interrupt_timer, (void *)soc,
  1316. QDF_TIMER_TYPE_WAKE_APPS);
  1317. return QDF_STATUS_SUCCESS;
  1318. }
  1319. void dp_soc_set_interrupt_mode(struct dp_soc *soc)
  1320. {
  1321. uint32_t msi_base_data, msi_vector_start;
  1322. int msi_vector_count, ret;
  1323. soc->intr_mode = DP_INTR_INTEGRATED;
  1324. if (!(soc->wlan_cfg_ctx->napi_enabled) ||
  1325. (dp_is_monitor_mode_using_poll(soc) &&
  1326. soc->cdp_soc.ol_ops->get_con_mode &&
  1327. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)) {
  1328. soc->intr_mode = DP_INTR_POLL;
  1329. } else {
  1330. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  1331. &msi_vector_count,
  1332. &msi_base_data,
  1333. &msi_vector_start);
  1334. if (ret)
  1335. return;
  1336. soc->intr_mode = DP_INTR_MSI;
  1337. }
  1338. }
  1339. #ifdef QCA_SUPPORT_LEGACY_INTERRUPTS
  1340. /**
  1341. * dp_soc_interrupt_map_calculate_wifi3_pci_legacy() -
  1342. * Calculate interrupt map for legacy interrupts
  1343. * @soc: DP soc handle
  1344. * @intr_ctx_num: Interrupt context number
  1345. * @irq_id_map: IRQ map
  1346. * @num_irq_r: Number of interrupts assigned for this context
  1347. *
  1348. * Return: void
  1349. */
  1350. static void dp_soc_interrupt_map_calculate_wifi3_pci_legacy(struct dp_soc *soc,
  1351. int intr_ctx_num,
  1352. int *irq_id_map,
  1353. int *num_irq_r)
  1354. {
  1355. int j;
  1356. int num_irq = 0;
  1357. int tx_mask = wlan_cfg_get_tx_ring_mask(
  1358. soc->wlan_cfg_ctx, intr_ctx_num);
  1359. int rx_mask = wlan_cfg_get_rx_ring_mask(
  1360. soc->wlan_cfg_ctx, intr_ctx_num);
  1361. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  1362. soc->wlan_cfg_ctx, intr_ctx_num);
  1363. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1364. soc->wlan_cfg_ctx, intr_ctx_num);
  1365. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1366. soc->wlan_cfg_ctx, intr_ctx_num);
  1367. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1368. soc->wlan_cfg_ctx, intr_ctx_num);
  1369. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1370. soc->wlan_cfg_ctx, intr_ctx_num);
  1371. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1372. soc->wlan_cfg_ctx, intr_ctx_num);
  1373. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1374. soc->wlan_cfg_ctx, intr_ctx_num);
  1375. soc->intr_mode = DP_INTR_LEGACY_VIRTUAL_IRQ;
  1376. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  1377. if (tx_mask & (1 << j))
  1378. irq_id_map[num_irq++] = (wbm2sw0_release - j);
  1379. if (rx_mask & (1 << j))
  1380. irq_id_map[num_irq++] = (reo2sw1_intr - j);
  1381. if (rx_mon_mask & (1 << j))
  1382. irq_id_map[num_irq++] = (rxmon2sw_p0_dest0 - j);
  1383. if (rx_err_ring_mask & (1 << j))
  1384. irq_id_map[num_irq++] = (reo2sw0_intr - j);
  1385. if (rx_wbm_rel_ring_mask & (1 << j))
  1386. irq_id_map[num_irq++] = (wbm2sw5_release - j);
  1387. if (reo_status_ring_mask & (1 << j))
  1388. irq_id_map[num_irq++] = (reo_status - j);
  1389. if (rxdma2host_ring_mask & (1 << j))
  1390. irq_id_map[num_irq++] = (rxdma2sw_dst_ring0 - j);
  1391. if (host2rxdma_ring_mask & (1 << j))
  1392. irq_id_map[num_irq++] = (sw2rxdma_0 - j);
  1393. if (host2rxdma_mon_ring_mask & (1 << j))
  1394. irq_id_map[num_irq++] = (sw2rxmon_src_ring - j);
  1395. }
  1396. *num_irq_r = num_irq;
  1397. }
  1398. #else
  1399. static void dp_soc_interrupt_map_calculate_wifi3_pci_legacy(struct dp_soc *soc,
  1400. int intr_ctx_num,
  1401. int *irq_id_map,
  1402. int *num_irq_r)
  1403. {
  1404. }
  1405. #endif
  1406. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  1407. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  1408. {
  1409. int j;
  1410. int num_irq = 0;
  1411. int tx_mask =
  1412. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1413. int rx_mask =
  1414. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1415. int rx_mon_mask =
  1416. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1417. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1418. soc->wlan_cfg_ctx, intr_ctx_num);
  1419. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1420. soc->wlan_cfg_ctx, intr_ctx_num);
  1421. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1422. soc->wlan_cfg_ctx, intr_ctx_num);
  1423. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1424. soc->wlan_cfg_ctx, intr_ctx_num);
  1425. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1426. soc->wlan_cfg_ctx, intr_ctx_num);
  1427. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1428. soc->wlan_cfg_ctx, intr_ctx_num);
  1429. int host2txmon_ring_mask = wlan_cfg_get_host2txmon_ring_mask(
  1430. soc->wlan_cfg_ctx, intr_ctx_num);
  1431. int txmon2host_mon_ring_mask = wlan_cfg_get_tx_mon_ring_mask(
  1432. soc->wlan_cfg_ctx, intr_ctx_num);
  1433. soc->intr_mode = DP_INTR_INTEGRATED;
  1434. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  1435. if (tx_mask & (1 << j)) {
  1436. irq_id_map[num_irq++] =
  1437. (wbm2host_tx_completions_ring1 - j);
  1438. }
  1439. if (rx_mask & (1 << j)) {
  1440. irq_id_map[num_irq++] =
  1441. (reo2host_destination_ring1 - j);
  1442. }
  1443. if (rxdma2host_ring_mask & (1 << j)) {
  1444. irq_id_map[num_irq++] =
  1445. rxdma2host_destination_ring_mac1 - j;
  1446. }
  1447. if (host2rxdma_ring_mask & (1 << j)) {
  1448. irq_id_map[num_irq++] =
  1449. host2rxdma_host_buf_ring_mac1 - j;
  1450. }
  1451. if (host2rxdma_mon_ring_mask & (1 << j)) {
  1452. irq_id_map[num_irq++] =
  1453. host2rxdma_monitor_ring1 - j;
  1454. }
  1455. if (rx_mon_mask & (1 << j)) {
  1456. irq_id_map[num_irq++] =
  1457. ppdu_end_interrupts_mac1 - j;
  1458. irq_id_map[num_irq++] =
  1459. rxdma2host_monitor_status_ring_mac1 - j;
  1460. irq_id_map[num_irq++] =
  1461. rxdma2host_monitor_destination_mac1 - j;
  1462. }
  1463. if (rx_wbm_rel_ring_mask & (1 << j))
  1464. irq_id_map[num_irq++] = wbm2host_rx_release;
  1465. if (rx_err_ring_mask & (1 << j))
  1466. irq_id_map[num_irq++] = reo2host_exception;
  1467. if (reo_status_ring_mask & (1 << j))
  1468. irq_id_map[num_irq++] = reo2host_status;
  1469. if (host2txmon_ring_mask & (1 << j))
  1470. irq_id_map[num_irq++] = host2tx_monitor_ring1;
  1471. if (txmon2host_mon_ring_mask & (1 << j)) {
  1472. irq_id_map[num_irq++] =
  1473. (txmon2host_monitor_destination_mac1 - j);
  1474. }
  1475. }
  1476. *num_irq_r = num_irq;
  1477. }
  1478. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  1479. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  1480. int msi_vector_count, int msi_vector_start)
  1481. {
  1482. int tx_mask = wlan_cfg_get_tx_ring_mask(
  1483. soc->wlan_cfg_ctx, intr_ctx_num);
  1484. int rx_mask = wlan_cfg_get_rx_ring_mask(
  1485. soc->wlan_cfg_ctx, intr_ctx_num);
  1486. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  1487. soc->wlan_cfg_ctx, intr_ctx_num);
  1488. int tx_mon_mask = wlan_cfg_get_tx_mon_ring_mask(
  1489. soc->wlan_cfg_ctx, intr_ctx_num);
  1490. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1491. soc->wlan_cfg_ctx, intr_ctx_num);
  1492. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1493. soc->wlan_cfg_ctx, intr_ctx_num);
  1494. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1495. soc->wlan_cfg_ctx, intr_ctx_num);
  1496. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1497. soc->wlan_cfg_ctx, intr_ctx_num);
  1498. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1499. soc->wlan_cfg_ctx, intr_ctx_num);
  1500. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1501. soc->wlan_cfg_ctx, intr_ctx_num);
  1502. int rx_near_full_grp_1_mask =
  1503. wlan_cfg_get_rx_near_full_grp_1_mask(soc->wlan_cfg_ctx,
  1504. intr_ctx_num);
  1505. int rx_near_full_grp_2_mask =
  1506. wlan_cfg_get_rx_near_full_grp_2_mask(soc->wlan_cfg_ctx,
  1507. intr_ctx_num);
  1508. int tx_ring_near_full_mask =
  1509. wlan_cfg_get_tx_ring_near_full_mask(soc->wlan_cfg_ctx,
  1510. intr_ctx_num);
  1511. int host2txmon_ring_mask =
  1512. wlan_cfg_get_host2txmon_ring_mask(soc->wlan_cfg_ctx,
  1513. intr_ctx_num);
  1514. unsigned int vector =
  1515. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  1516. int num_irq = 0;
  1517. soc->intr_mode = DP_INTR_MSI;
  1518. if (tx_mask | rx_mask | rx_mon_mask | tx_mon_mask | rx_err_ring_mask |
  1519. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask |
  1520. host2rxdma_ring_mask | host2rxdma_mon_ring_mask |
  1521. rx_near_full_grp_1_mask | rx_near_full_grp_2_mask |
  1522. tx_ring_near_full_mask | host2txmon_ring_mask)
  1523. irq_id_map[num_irq++] =
  1524. pld_get_msi_irq(soc->osdev->dev, vector);
  1525. *num_irq_r = num_irq;
  1526. }
  1527. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  1528. int *irq_id_map, int *num_irq)
  1529. {
  1530. int msi_vector_count, ret;
  1531. uint32_t msi_base_data, msi_vector_start;
  1532. if (pld_get_enable_intx(soc->osdev->dev)) {
  1533. return dp_soc_interrupt_map_calculate_wifi3_pci_legacy(soc,
  1534. intr_ctx_num, irq_id_map, num_irq);
  1535. }
  1536. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  1537. &msi_vector_count,
  1538. &msi_base_data,
  1539. &msi_vector_start);
  1540. if (ret)
  1541. return dp_soc_interrupt_map_calculate_integrated(soc,
  1542. intr_ctx_num, irq_id_map, num_irq);
  1543. else
  1544. dp_soc_interrupt_map_calculate_msi(soc,
  1545. intr_ctx_num, irq_id_map, num_irq,
  1546. msi_vector_count, msi_vector_start);
  1547. }
  1548. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1549. /**
  1550. * dp_soc_near_full_interrupt_attach() - Register handler for DP near fill irq
  1551. * @soc: DP soc handle
  1552. * @num_irq: IRQ number
  1553. * @irq_id_map: IRQ map
  1554. * @intr_id: interrupt context ID
  1555. *
  1556. * Return: 0 for success. nonzero for failure.
  1557. */
  1558. static inline int
  1559. dp_soc_near_full_interrupt_attach(struct dp_soc *soc, int num_irq,
  1560. int irq_id_map[], int intr_id)
  1561. {
  1562. return hif_register_ext_group(soc->hif_handle,
  1563. num_irq, irq_id_map,
  1564. dp_service_near_full_srngs,
  1565. &soc->intr_ctx[intr_id], "dp_nf_intr",
  1566. HIF_EXEC_NAPI_TYPE,
  1567. QCA_NAPI_DEF_SCALE_BIN_SHIFT);
  1568. }
  1569. #else
  1570. static inline int
  1571. dp_soc_near_full_interrupt_attach(struct dp_soc *soc, int num_irq,
  1572. int *irq_id_map, int intr_id)
  1573. {
  1574. return 0;
  1575. }
  1576. #endif
  1577. #ifdef DP_CON_MON_MSI_SKIP_SET
  1578. static inline bool dp_skip_rx_mon_ring_mask_set(struct dp_soc *soc)
  1579. {
  1580. return !!(soc->cdp_soc.ol_ops->get_con_mode() !=
  1581. QDF_GLOBAL_MONITOR_MODE);
  1582. }
  1583. #else
  1584. static inline bool dp_skip_rx_mon_ring_mask_set(struct dp_soc *soc)
  1585. {
  1586. return false;
  1587. }
  1588. #endif
  1589. void dp_soc_interrupt_detach(struct cdp_soc_t *txrx_soc)
  1590. {
  1591. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1592. int i;
  1593. if (soc->intr_mode == DP_INTR_POLL) {
  1594. qdf_timer_free(&soc->int_timer);
  1595. } else {
  1596. hif_deconfigure_ext_group_interrupts(soc->hif_handle);
  1597. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1598. hif_deregister_exec_group(soc->hif_handle, "dp_nf_intr");
  1599. }
  1600. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1601. soc->intr_ctx[i].tx_ring_mask = 0;
  1602. soc->intr_ctx[i].rx_ring_mask = 0;
  1603. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1604. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1605. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1606. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1607. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  1608. soc->intr_ctx[i].host2rxdma_ring_mask = 0;
  1609. soc->intr_ctx[i].host2rxdma_mon_ring_mask = 0;
  1610. soc->intr_ctx[i].rx_near_full_grp_1_mask = 0;
  1611. soc->intr_ctx[i].rx_near_full_grp_2_mask = 0;
  1612. soc->intr_ctx[i].tx_ring_near_full_mask = 0;
  1613. soc->intr_ctx[i].tx_mon_ring_mask = 0;
  1614. soc->intr_ctx[i].host2txmon_ring_mask = 0;
  1615. soc->intr_ctx[i].umac_reset_intr_mask = 0;
  1616. hif_event_history_deinit(soc->hif_handle, i);
  1617. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1618. }
  1619. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1620. sizeof(soc->mon_intr_id_lmac_map),
  1621. DP_MON_INVALID_LMAC_ID);
  1622. }
  1623. QDF_STATUS dp_soc_interrupt_attach(struct cdp_soc_t *txrx_soc)
  1624. {
  1625. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1626. int i = 0;
  1627. int num_irq = 0;
  1628. int rx_err_ring_intr_ctxt_id = HIF_MAX_GROUP;
  1629. int lmac_id = 0;
  1630. int napi_scale;
  1631. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1632. sizeof(soc->mon_intr_id_lmac_map), DP_MON_INVALID_LMAC_ID);
  1633. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1634. int ret = 0;
  1635. /* Map of IRQ ids registered with one interrupt context */
  1636. int irq_id_map[HIF_MAX_GRP_IRQ];
  1637. int tx_mask =
  1638. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1639. int rx_mask =
  1640. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1641. int rx_mon_mask =
  1642. dp_soc_get_mon_mask_for_interrupt_mode(soc, i);
  1643. int tx_mon_ring_mask =
  1644. wlan_cfg_get_tx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1645. int rx_err_ring_mask =
  1646. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1647. int rx_wbm_rel_ring_mask =
  1648. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1649. int reo_status_ring_mask =
  1650. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1651. int rxdma2host_ring_mask =
  1652. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1653. int host2rxdma_ring_mask =
  1654. wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx, i);
  1655. int host2rxdma_mon_ring_mask =
  1656. wlan_cfg_get_host2rxdma_mon_ring_mask(
  1657. soc->wlan_cfg_ctx, i);
  1658. int rx_near_full_grp_1_mask =
  1659. wlan_cfg_get_rx_near_full_grp_1_mask(soc->wlan_cfg_ctx,
  1660. i);
  1661. int rx_near_full_grp_2_mask =
  1662. wlan_cfg_get_rx_near_full_grp_2_mask(soc->wlan_cfg_ctx,
  1663. i);
  1664. int tx_ring_near_full_mask =
  1665. wlan_cfg_get_tx_ring_near_full_mask(soc->wlan_cfg_ctx,
  1666. i);
  1667. int host2txmon_ring_mask =
  1668. wlan_cfg_get_host2txmon_ring_mask(soc->wlan_cfg_ctx, i);
  1669. int umac_reset_intr_mask =
  1670. wlan_cfg_get_umac_reset_intr_mask(soc->wlan_cfg_ctx, i);
  1671. if (dp_skip_rx_mon_ring_mask_set(soc))
  1672. rx_mon_mask = 0;
  1673. soc->intr_ctx[i].dp_intr_id = i;
  1674. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1675. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1676. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1677. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1678. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1679. soc->intr_ctx[i].host2rxdma_ring_mask = host2rxdma_ring_mask;
  1680. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1681. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1682. soc->intr_ctx[i].host2rxdma_mon_ring_mask =
  1683. host2rxdma_mon_ring_mask;
  1684. soc->intr_ctx[i].rx_near_full_grp_1_mask =
  1685. rx_near_full_grp_1_mask;
  1686. soc->intr_ctx[i].rx_near_full_grp_2_mask =
  1687. rx_near_full_grp_2_mask;
  1688. soc->intr_ctx[i].tx_ring_near_full_mask =
  1689. tx_ring_near_full_mask;
  1690. soc->intr_ctx[i].tx_mon_ring_mask = tx_mon_ring_mask;
  1691. soc->intr_ctx[i].host2txmon_ring_mask = host2txmon_ring_mask;
  1692. soc->intr_ctx[i].umac_reset_intr_mask = umac_reset_intr_mask;
  1693. soc->intr_ctx[i].soc = soc;
  1694. num_irq = 0;
  1695. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1696. &num_irq);
  1697. if (rx_near_full_grp_1_mask | rx_near_full_grp_2_mask |
  1698. tx_ring_near_full_mask) {
  1699. dp_soc_near_full_interrupt_attach(soc, num_irq,
  1700. irq_id_map, i);
  1701. } else {
  1702. napi_scale = wlan_cfg_get_napi_scale_factor(
  1703. soc->wlan_cfg_ctx);
  1704. if (!napi_scale)
  1705. napi_scale = QCA_NAPI_DEF_SCALE_BIN_SHIFT;
  1706. ret = hif_register_ext_group(soc->hif_handle,
  1707. num_irq, irq_id_map, dp_service_srngs,
  1708. &soc->intr_ctx[i], "dp_intr",
  1709. HIF_EXEC_NAPI_TYPE, napi_scale);
  1710. }
  1711. dp_debug(" int ctx %u num_irq %u irq_id_map %u %u",
  1712. i, num_irq, irq_id_map[0], irq_id_map[1]);
  1713. if (ret) {
  1714. dp_init_err("%pK: failed, ret = %d", soc, ret);
  1715. dp_soc_interrupt_detach(txrx_soc);
  1716. return QDF_STATUS_E_FAILURE;
  1717. }
  1718. hif_event_history_init(soc->hif_handle, i);
  1719. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1720. if (rx_err_ring_mask)
  1721. rx_err_ring_intr_ctxt_id = i;
  1722. if (dp_is_mon_mask_valid(soc, &soc->intr_ctx[i])) {
  1723. soc->mon_intr_id_lmac_map[lmac_id] = i;
  1724. lmac_id++;
  1725. }
  1726. }
  1727. hif_configure_ext_group_interrupts(soc->hif_handle);
  1728. if (rx_err_ring_intr_ctxt_id != HIF_MAX_GROUP)
  1729. hif_config_irq_clear_cpu_affinity(soc->hif_handle,
  1730. rx_err_ring_intr_ctxt_id, 0);
  1731. return QDF_STATUS_SUCCESS;
  1732. }
  1733. #define AVG_MAX_MPDUS_PER_TID 128
  1734. #define AVG_TIDS_PER_CLIENT 2
  1735. #define AVG_FLOWS_PER_TID 2
  1736. #define AVG_MSDUS_PER_FLOW 128
  1737. #define AVG_MSDUS_PER_MPDU 4
  1738. void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, uint32_t mac_id)
  1739. {
  1740. struct qdf_mem_multi_page_t *pages;
  1741. if (mac_id != WLAN_INVALID_PDEV_ID) {
  1742. pages = dp_monitor_get_link_desc_pages(soc, mac_id);
  1743. } else {
  1744. pages = &soc->link_desc_pages;
  1745. }
  1746. if (!pages) {
  1747. dp_err("can not get link desc pages");
  1748. QDF_ASSERT(0);
  1749. return;
  1750. }
  1751. if (pages->dma_pages) {
  1752. wlan_minidump_remove((void *)
  1753. pages->dma_pages->page_v_addr_start,
  1754. pages->num_pages * pages->page_size,
  1755. soc->ctrl_psoc,
  1756. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1757. "hw_link_desc_bank");
  1758. dp_desc_multi_pages_mem_free(soc, DP_HW_LINK_DESC_TYPE,
  1759. pages, 0, false);
  1760. }
  1761. }
  1762. qdf_export_symbol(dp_hw_link_desc_pool_banks_free);
  1763. QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, uint32_t mac_id)
  1764. {
  1765. hal_soc_handle_t hal_soc = soc->hal_soc;
  1766. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1767. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1768. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1769. uint32_t num_mpdus_per_link_desc = hal_num_mpdus_per_link_desc(hal_soc);
  1770. uint32_t num_msdus_per_link_desc = hal_num_msdus_per_link_desc(hal_soc);
  1771. uint32_t num_mpdu_links_per_queue_desc =
  1772. hal_num_mpdu_links_per_queue_desc(hal_soc);
  1773. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1774. uint32_t *total_link_descs, total_mem_size;
  1775. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1776. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1777. uint32_t num_entries;
  1778. struct qdf_mem_multi_page_t *pages;
  1779. struct dp_srng *dp_srng;
  1780. uint8_t minidump_str[MINIDUMP_STR_SIZE];
  1781. /* Only Tx queue descriptors are allocated from common link descriptor
  1782. * pool Rx queue descriptors are not included in this because (REO queue
  1783. * extension descriptors) they are expected to be allocated contiguously
  1784. * with REO queue descriptors
  1785. */
  1786. if (mac_id != WLAN_INVALID_PDEV_ID) {
  1787. pages = dp_monitor_get_link_desc_pages(soc, mac_id);
  1788. /* dp_monitor_get_link_desc_pages returns NULL only
  1789. * if monitor SOC is NULL
  1790. */
  1791. if (!pages) {
  1792. dp_err("can not get link desc pages");
  1793. QDF_ASSERT(0);
  1794. return QDF_STATUS_E_FAULT;
  1795. }
  1796. dp_srng = &soc->rxdma_mon_desc_ring[mac_id];
  1797. num_entries = dp_srng->alloc_size /
  1798. hal_srng_get_entrysize(soc->hal_soc,
  1799. RXDMA_MONITOR_DESC);
  1800. total_link_descs = dp_monitor_get_total_link_descs(soc, mac_id);
  1801. qdf_str_lcopy(minidump_str, "mon_link_desc_bank",
  1802. MINIDUMP_STR_SIZE);
  1803. } else {
  1804. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1805. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1806. num_mpdu_queue_descs = num_mpdu_link_descs /
  1807. num_mpdu_links_per_queue_desc;
  1808. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1809. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1810. num_msdus_per_link_desc;
  1811. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1812. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1813. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1814. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1815. pages = &soc->link_desc_pages;
  1816. total_link_descs = &soc->total_link_descs;
  1817. qdf_str_lcopy(minidump_str, "link_desc_bank",
  1818. MINIDUMP_STR_SIZE);
  1819. }
  1820. /* If link descriptor banks are allocated, return from here */
  1821. if (pages->num_pages)
  1822. return QDF_STATUS_SUCCESS;
  1823. /* Round up to power of 2 */
  1824. *total_link_descs = 1;
  1825. while (*total_link_descs < num_entries)
  1826. *total_link_descs <<= 1;
  1827. dp_init_info("%pK: total_link_descs: %u, link_desc_size: %d",
  1828. soc, *total_link_descs, link_desc_size);
  1829. total_mem_size = *total_link_descs * link_desc_size;
  1830. total_mem_size += link_desc_align;
  1831. dp_init_info("%pK: total_mem_size: %d",
  1832. soc, total_mem_size);
  1833. dp_set_max_page_size(pages, max_alloc_size);
  1834. dp_desc_multi_pages_mem_alloc(soc, DP_HW_LINK_DESC_TYPE,
  1835. pages,
  1836. link_desc_size,
  1837. *total_link_descs,
  1838. 0, false);
  1839. if (!pages->num_pages) {
  1840. dp_err("Multi page alloc fail for hw link desc pool");
  1841. return QDF_STATUS_E_FAULT;
  1842. }
  1843. wlan_minidump_log(pages->dma_pages->page_v_addr_start,
  1844. pages->num_pages * pages->page_size,
  1845. soc->ctrl_psoc,
  1846. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1847. "hw_link_desc_bank");
  1848. return QDF_STATUS_SUCCESS;
  1849. }
  1850. void dp_hw_link_desc_ring_free(struct dp_soc *soc)
  1851. {
  1852. uint32_t i;
  1853. uint32_t size = soc->wbm_idle_scatter_buf_size;
  1854. void *vaddr = soc->wbm_idle_link_ring.base_vaddr_unaligned;
  1855. qdf_dma_addr_t paddr;
  1856. if (soc->wbm_idle_scatter_buf_base_vaddr[0]) {
  1857. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1858. vaddr = soc->wbm_idle_scatter_buf_base_vaddr[i];
  1859. paddr = soc->wbm_idle_scatter_buf_base_paddr[i];
  1860. if (vaddr) {
  1861. qdf_mem_free_consistent(soc->osdev,
  1862. soc->osdev->dev,
  1863. size,
  1864. vaddr,
  1865. paddr,
  1866. 0);
  1867. vaddr = NULL;
  1868. }
  1869. }
  1870. } else {
  1871. wlan_minidump_remove(soc->wbm_idle_link_ring.base_vaddr_unaligned,
  1872. soc->wbm_idle_link_ring.alloc_size,
  1873. soc->ctrl_psoc,
  1874. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1875. "wbm_idle_link_ring");
  1876. dp_srng_free(soc, &soc->wbm_idle_link_ring);
  1877. }
  1878. }
  1879. QDF_STATUS dp_hw_link_desc_ring_alloc(struct dp_soc *soc)
  1880. {
  1881. uint32_t entry_size, i;
  1882. uint32_t total_mem_size;
  1883. qdf_dma_addr_t *baseaddr = NULL;
  1884. struct dp_srng *dp_srng;
  1885. uint32_t ring_type;
  1886. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1887. uint32_t tlds;
  1888. ring_type = WBM_IDLE_LINK;
  1889. dp_srng = &soc->wbm_idle_link_ring;
  1890. tlds = soc->total_link_descs;
  1891. entry_size = hal_srng_get_entrysize(soc->hal_soc, ring_type);
  1892. total_mem_size = entry_size * tlds;
  1893. if (total_mem_size <= max_alloc_size) {
  1894. if (dp_srng_alloc(soc, dp_srng, ring_type, tlds, 0)) {
  1895. dp_init_err("%pK: Link desc idle ring setup failed",
  1896. soc);
  1897. goto fail;
  1898. }
  1899. wlan_minidump_log(soc->wbm_idle_link_ring.base_vaddr_unaligned,
  1900. soc->wbm_idle_link_ring.alloc_size,
  1901. soc->ctrl_psoc,
  1902. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1903. "wbm_idle_link_ring");
  1904. } else {
  1905. uint32_t num_scatter_bufs;
  1906. uint32_t buf_size = 0;
  1907. soc->wbm_idle_scatter_buf_size =
  1908. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1909. hal_idle_scatter_buf_num_entries(
  1910. soc->hal_soc,
  1911. soc->wbm_idle_scatter_buf_size);
  1912. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1913. soc->hal_soc, total_mem_size,
  1914. soc->wbm_idle_scatter_buf_size);
  1915. if (num_scatter_bufs > MAX_IDLE_SCATTER_BUFS) {
  1916. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1917. FL("scatter bufs size out of bounds"));
  1918. goto fail;
  1919. }
  1920. for (i = 0; i < num_scatter_bufs; i++) {
  1921. baseaddr = &soc->wbm_idle_scatter_buf_base_paddr[i];
  1922. buf_size = soc->wbm_idle_scatter_buf_size;
  1923. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1924. qdf_mem_alloc_consistent(soc->osdev,
  1925. soc->osdev->dev,
  1926. buf_size,
  1927. baseaddr);
  1928. if (!soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1929. QDF_TRACE(QDF_MODULE_ID_DP,
  1930. QDF_TRACE_LEVEL_ERROR,
  1931. FL("Scatter lst memory alloc fail"));
  1932. goto fail;
  1933. }
  1934. }
  1935. soc->num_scatter_bufs = num_scatter_bufs;
  1936. }
  1937. return QDF_STATUS_SUCCESS;
  1938. fail:
  1939. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1940. void *vaddr = soc->wbm_idle_scatter_buf_base_vaddr[i];
  1941. qdf_dma_addr_t paddr = soc->wbm_idle_scatter_buf_base_paddr[i];
  1942. if (vaddr) {
  1943. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1944. soc->wbm_idle_scatter_buf_size,
  1945. vaddr,
  1946. paddr, 0);
  1947. vaddr = NULL;
  1948. }
  1949. }
  1950. return QDF_STATUS_E_NOMEM;
  1951. }
  1952. qdf_export_symbol(dp_hw_link_desc_pool_banks_alloc);
  1953. QDF_STATUS dp_hw_link_desc_ring_init(struct dp_soc *soc)
  1954. {
  1955. struct dp_srng *dp_srng = &soc->wbm_idle_link_ring;
  1956. if (dp_srng->base_vaddr_unaligned) {
  1957. if (dp_srng_init(soc, dp_srng, WBM_IDLE_LINK, 0, 0))
  1958. return QDF_STATUS_E_FAILURE;
  1959. }
  1960. return QDF_STATUS_SUCCESS;
  1961. }
  1962. void dp_hw_link_desc_ring_deinit(struct dp_soc *soc)
  1963. {
  1964. dp_srng_deinit(soc, &soc->wbm_idle_link_ring, WBM_IDLE_LINK, 0);
  1965. }
  1966. void dp_link_desc_ring_replenish(struct dp_soc *soc, uint32_t mac_id)
  1967. {
  1968. uint32_t cookie = 0;
  1969. uint32_t page_idx = 0;
  1970. struct qdf_mem_multi_page_t *pages;
  1971. struct qdf_mem_dma_page_t *dma_pages;
  1972. uint32_t offset = 0;
  1973. uint32_t count = 0;
  1974. uint32_t desc_id = 0;
  1975. void *desc_srng;
  1976. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1977. uint32_t *total_link_descs_addr;
  1978. uint32_t total_link_descs;
  1979. uint32_t scatter_buf_num;
  1980. uint32_t num_entries_per_buf = 0;
  1981. uint32_t rem_entries;
  1982. uint32_t num_descs_per_page;
  1983. uint32_t num_scatter_bufs = 0;
  1984. uint8_t *scatter_buf_ptr;
  1985. void *desc;
  1986. num_scatter_bufs = soc->num_scatter_bufs;
  1987. if (mac_id == WLAN_INVALID_PDEV_ID) {
  1988. pages = &soc->link_desc_pages;
  1989. total_link_descs = soc->total_link_descs;
  1990. desc_srng = soc->wbm_idle_link_ring.hal_srng;
  1991. } else {
  1992. pages = dp_monitor_get_link_desc_pages(soc, mac_id);
  1993. /* dp_monitor_get_link_desc_pages returns NULL only
  1994. * if monitor SOC is NULL
  1995. */
  1996. if (!pages) {
  1997. dp_err("can not get link desc pages");
  1998. QDF_ASSERT(0);
  1999. return;
  2000. }
  2001. total_link_descs_addr =
  2002. dp_monitor_get_total_link_descs(soc, mac_id);
  2003. total_link_descs = *total_link_descs_addr;
  2004. desc_srng = soc->rxdma_mon_desc_ring[mac_id].hal_srng;
  2005. }
  2006. dma_pages = pages->dma_pages;
  2007. do {
  2008. qdf_mem_zero(dma_pages[page_idx].page_v_addr_start,
  2009. pages->page_size);
  2010. page_idx++;
  2011. } while (page_idx < pages->num_pages);
  2012. if (desc_srng) {
  2013. hal_srng_access_start_unlocked(soc->hal_soc, desc_srng);
  2014. page_idx = 0;
  2015. count = 0;
  2016. offset = 0;
  2017. pages = &soc->link_desc_pages;
  2018. while ((desc = hal_srng_src_get_next(soc->hal_soc,
  2019. desc_srng)) &&
  2020. (count < total_link_descs)) {
  2021. page_idx = count / pages->num_element_per_page;
  2022. if (desc_id == pages->num_element_per_page)
  2023. desc_id = 0;
  2024. offset = count % pages->num_element_per_page;
  2025. cookie = LINK_DESC_COOKIE(desc_id, page_idx,
  2026. soc->link_desc_id_start);
  2027. hal_set_link_desc_addr(soc->hal_soc, desc, cookie,
  2028. dma_pages[page_idx].page_p_addr
  2029. + (offset * link_desc_size),
  2030. soc->idle_link_bm_id);
  2031. count++;
  2032. desc_id++;
  2033. }
  2034. hal_srng_access_end_unlocked(soc->hal_soc, desc_srng);
  2035. } else {
  2036. /* Populate idle list scatter buffers with link descriptor
  2037. * pointers
  2038. */
  2039. scatter_buf_num = 0;
  2040. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  2041. soc->hal_soc,
  2042. soc->wbm_idle_scatter_buf_size);
  2043. scatter_buf_ptr = (uint8_t *)(
  2044. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  2045. rem_entries = num_entries_per_buf;
  2046. pages = &soc->link_desc_pages;
  2047. page_idx = 0; count = 0;
  2048. offset = 0;
  2049. num_descs_per_page = pages->num_element_per_page;
  2050. while (count < total_link_descs) {
  2051. page_idx = count / num_descs_per_page;
  2052. offset = count % num_descs_per_page;
  2053. if (desc_id == pages->num_element_per_page)
  2054. desc_id = 0;
  2055. cookie = LINK_DESC_COOKIE(desc_id, page_idx,
  2056. soc->link_desc_id_start);
  2057. hal_set_link_desc_addr(soc->hal_soc,
  2058. (void *)scatter_buf_ptr,
  2059. cookie,
  2060. dma_pages[page_idx].page_p_addr +
  2061. (offset * link_desc_size),
  2062. soc->idle_link_bm_id);
  2063. rem_entries--;
  2064. if (rem_entries) {
  2065. scatter_buf_ptr += link_desc_size;
  2066. } else {
  2067. rem_entries = num_entries_per_buf;
  2068. scatter_buf_num++;
  2069. if (scatter_buf_num >= num_scatter_bufs)
  2070. break;
  2071. scatter_buf_ptr = (uint8_t *)
  2072. (soc->wbm_idle_scatter_buf_base_vaddr[
  2073. scatter_buf_num]);
  2074. }
  2075. count++;
  2076. desc_id++;
  2077. }
  2078. /* Setup link descriptor idle list in HW */
  2079. hal_setup_link_idle_list(soc->hal_soc,
  2080. soc->wbm_idle_scatter_buf_base_paddr,
  2081. soc->wbm_idle_scatter_buf_base_vaddr,
  2082. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  2083. (uint32_t)(scatter_buf_ptr -
  2084. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  2085. scatter_buf_num-1])), total_link_descs);
  2086. }
  2087. }
  2088. qdf_export_symbol(dp_link_desc_ring_replenish);
  2089. #ifdef IPA_OFFLOAD
  2090. #define USE_1_IPA_RX_REO_RING 1
  2091. #define USE_2_IPA_RX_REO_RINGS 2
  2092. #define REO_DST_RING_SIZE_QCA6290 1023
  2093. #ifndef CONFIG_WIFI_EMULATION_WIFI_3_0
  2094. #define REO_DST_RING_SIZE_QCA8074 1023
  2095. #define REO_DST_RING_SIZE_QCN9000 2048
  2096. #else
  2097. #define REO_DST_RING_SIZE_QCA8074 8
  2098. #define REO_DST_RING_SIZE_QCN9000 8
  2099. #endif /* CONFIG_WIFI_EMULATION_WIFI_3_0 */
  2100. #ifdef IPA_WDI3_TX_TWO_PIPES
  2101. #ifdef DP_MEMORY_OPT
  2102. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2103. {
  2104. return dp_init_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2105. }
  2106. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2107. {
  2108. dp_deinit_tx_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2109. }
  2110. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2111. {
  2112. return dp_alloc_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2113. }
  2114. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2115. {
  2116. dp_free_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2117. }
  2118. #else /* !DP_MEMORY_OPT */
  2119. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2120. {
  2121. return 0;
  2122. }
  2123. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2124. {
  2125. }
  2126. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2127. {
  2128. return 0
  2129. }
  2130. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2131. {
  2132. }
  2133. #endif /* DP_MEMORY_OPT */
  2134. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2135. {
  2136. hal_tx_init_data_ring(soc->hal_soc,
  2137. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng);
  2138. }
  2139. #else /* !IPA_WDI3_TX_TWO_PIPES */
  2140. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2141. {
  2142. return 0;
  2143. }
  2144. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2145. {
  2146. }
  2147. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2148. {
  2149. return 0;
  2150. }
  2151. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2152. {
  2153. }
  2154. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2155. {
  2156. }
  2157. #endif /* IPA_WDI3_TX_TWO_PIPES */
  2158. #else
  2159. #define REO_DST_RING_SIZE_QCA6290 1024
  2160. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2161. {
  2162. return 0;
  2163. }
  2164. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2165. {
  2166. }
  2167. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2168. {
  2169. return 0;
  2170. }
  2171. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2172. {
  2173. }
  2174. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2175. {
  2176. }
  2177. #endif /* IPA_OFFLOAD */
  2178. /**
  2179. * dp_soc_reset_cpu_ring_map() - Reset cpu ring map
  2180. * @soc: Datapath soc handler
  2181. *
  2182. * This api resets the default cpu ring map
  2183. */
  2184. void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  2185. {
  2186. uint8_t i;
  2187. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2188. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  2189. switch (nss_config) {
  2190. case dp_nss_cfg_first_radio:
  2191. /*
  2192. * Setting Tx ring map for one nss offloaded radio
  2193. */
  2194. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  2195. break;
  2196. case dp_nss_cfg_second_radio:
  2197. /*
  2198. * Setting Tx ring for two nss offloaded radios
  2199. */
  2200. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  2201. break;
  2202. case dp_nss_cfg_dbdc:
  2203. /*
  2204. * Setting Tx ring map for 2 nss offloaded radios
  2205. */
  2206. soc->tx_ring_map[i] =
  2207. dp_cpu_ring_map[DP_NSS_DBDC_OFFLOADED_MAP][i];
  2208. break;
  2209. case dp_nss_cfg_dbtc:
  2210. /*
  2211. * Setting Tx ring map for 3 nss offloaded radios
  2212. */
  2213. soc->tx_ring_map[i] =
  2214. dp_cpu_ring_map[DP_NSS_DBTC_OFFLOADED_MAP][i];
  2215. break;
  2216. default:
  2217. dp_err("tx_ring_map failed due to invalid nss cfg");
  2218. break;
  2219. }
  2220. }
  2221. }
  2222. /**
  2223. * dp_soc_disable_unused_mac_intr_mask() - reset interrupt mask for
  2224. * unused WMAC hw rings
  2225. * @soc: DP Soc handle
  2226. * @mac_num: wmac num
  2227. *
  2228. * Return: Return void
  2229. */
  2230. static void dp_soc_disable_unused_mac_intr_mask(struct dp_soc *soc,
  2231. int mac_num)
  2232. {
  2233. uint8_t *grp_mask = NULL;
  2234. int group_number;
  2235. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  2236. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2237. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2238. group_number, 0x0);
  2239. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  2240. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2241. wlan_cfg_set_rx_mon_ring_mask(soc->wlan_cfg_ctx,
  2242. group_number, 0x0);
  2243. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  2244. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2245. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx,
  2246. group_number, 0x0);
  2247. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_mon_ring_mask[0];
  2248. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2249. wlan_cfg_set_host2rxdma_mon_ring_mask(soc->wlan_cfg_ctx,
  2250. group_number, 0x0);
  2251. }
  2252. #ifdef IPA_OFFLOAD
  2253. #ifdef IPA_WDI3_VLAN_SUPPORT
  2254. /**
  2255. * dp_soc_reset_ipa_vlan_intr_mask() - reset interrupt mask for IPA offloaded
  2256. * ring for vlan tagged traffic
  2257. * @soc: DP Soc handle
  2258. *
  2259. * Return: Return void
  2260. */
  2261. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2262. {
  2263. uint8_t *grp_mask = NULL;
  2264. int group_number, mask;
  2265. if (!wlan_ipa_is_vlan_enabled())
  2266. return;
  2267. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  2268. group_number = dp_srng_find_ring_in_mask(IPA_ALT_REO_DEST_RING_IDX, grp_mask);
  2269. if (group_number < 0) {
  2270. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2271. soc, REO_DST, IPA_ALT_REO_DEST_RING_IDX);
  2272. return;
  2273. }
  2274. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2275. /* reset the interrupt mask for offloaded ring */
  2276. mask &= (~(1 << IPA_ALT_REO_DEST_RING_IDX));
  2277. /*
  2278. * set the interrupt mask to zero for rx offloaded radio.
  2279. */
  2280. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2281. }
  2282. #else
  2283. inline
  2284. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2285. { }
  2286. #endif /* IPA_WDI3_VLAN_SUPPORT */
  2287. #else
  2288. inline
  2289. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2290. { }
  2291. #endif /* IPA_OFFLOAD */
  2292. /**
  2293. * dp_soc_reset_intr_mask() - reset interrupt mask
  2294. * @soc: DP Soc handle
  2295. *
  2296. * Return: Return void
  2297. */
  2298. void dp_soc_reset_intr_mask(struct dp_soc *soc)
  2299. {
  2300. uint8_t j;
  2301. uint8_t *grp_mask = NULL;
  2302. int group_number, mask, num_ring;
  2303. /* number of tx ring */
  2304. num_ring = soc->num_tcl_data_rings;
  2305. /*
  2306. * group mask for tx completion ring.
  2307. */
  2308. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  2309. /* loop and reset the mask for only offloaded ring */
  2310. for (j = 0; j < WLAN_CFG_NUM_TCL_DATA_RINGS; j++) {
  2311. /*
  2312. * Group number corresponding to tx offloaded ring.
  2313. */
  2314. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2315. if (group_number < 0) {
  2316. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2317. soc, WBM2SW_RELEASE, j);
  2318. continue;
  2319. }
  2320. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2321. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j) &&
  2322. (!mask)) {
  2323. continue;
  2324. }
  2325. /* reset the tx mask for offloaded ring */
  2326. mask &= (~(1 << j));
  2327. /*
  2328. * reset the interrupt mask for offloaded ring.
  2329. */
  2330. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2331. }
  2332. /* number of rx rings */
  2333. num_ring = soc->num_reo_dest_rings;
  2334. /*
  2335. * group mask for reo destination ring.
  2336. */
  2337. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  2338. /* loop and reset the mask for only offloaded ring */
  2339. for (j = 0; j < WLAN_CFG_NUM_REO_DEST_RING; j++) {
  2340. /*
  2341. * Group number corresponding to rx offloaded ring.
  2342. */
  2343. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2344. if (group_number < 0) {
  2345. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2346. soc, REO_DST, j);
  2347. continue;
  2348. }
  2349. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2350. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j) &&
  2351. (!mask)) {
  2352. continue;
  2353. }
  2354. /* reset the interrupt mask for offloaded ring */
  2355. mask &= (~(1 << j));
  2356. /*
  2357. * set the interrupt mask to zero for rx offloaded radio.
  2358. */
  2359. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2360. }
  2361. /*
  2362. * group mask for Rx buffer refill ring
  2363. */
  2364. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  2365. /* loop and reset the mask for only offloaded ring */
  2366. for (j = 0; j < MAX_PDEV_CNT; j++) {
  2367. int lmac_id = wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  2368. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF, j)) {
  2369. continue;
  2370. }
  2371. /*
  2372. * Group number corresponding to rx offloaded ring.
  2373. */
  2374. group_number = dp_srng_find_ring_in_mask(lmac_id, grp_mask);
  2375. if (group_number < 0) {
  2376. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2377. soc, REO_DST, lmac_id);
  2378. continue;
  2379. }
  2380. /* set the interrupt mask for offloaded ring */
  2381. mask = wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2382. group_number);
  2383. mask &= (~(1 << lmac_id));
  2384. /*
  2385. * set the interrupt mask to zero for rx offloaded radio.
  2386. */
  2387. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2388. group_number, mask);
  2389. }
  2390. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  2391. for (j = 0; j < num_ring; j++) {
  2392. if (!dp_soc_ring_if_nss_offloaded(soc, REO_EXCEPTION, j)) {
  2393. continue;
  2394. }
  2395. /*
  2396. * Group number corresponding to rx err ring.
  2397. */
  2398. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2399. if (group_number < 0) {
  2400. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2401. soc, REO_EXCEPTION, j);
  2402. continue;
  2403. }
  2404. wlan_cfg_set_rx_err_ring_mask(soc->wlan_cfg_ctx,
  2405. group_number, 0);
  2406. }
  2407. }
  2408. #ifdef IPA_OFFLOAD
  2409. bool dp_reo_remap_config(struct dp_soc *soc, uint32_t *remap0,
  2410. uint32_t *remap1, uint32_t *remap2)
  2411. {
  2412. uint32_t ring[WLAN_CFG_NUM_REO_DEST_RING_MAX] = {
  2413. REO_REMAP_SW1, REO_REMAP_SW2, REO_REMAP_SW3,
  2414. REO_REMAP_SW5, REO_REMAP_SW6, REO_REMAP_SW7};
  2415. switch (soc->arch_id) {
  2416. case CDP_ARCH_TYPE_BE:
  2417. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2418. soc->num_reo_dest_rings -
  2419. USE_2_IPA_RX_REO_RINGS, remap1,
  2420. remap2);
  2421. break;
  2422. case CDP_ARCH_TYPE_LI:
  2423. if (wlan_ipa_is_vlan_enabled()) {
  2424. hal_compute_reo_remap_ix2_ix3(
  2425. soc->hal_soc, ring,
  2426. soc->num_reo_dest_rings -
  2427. USE_2_IPA_RX_REO_RINGS, remap1,
  2428. remap2);
  2429. } else {
  2430. hal_compute_reo_remap_ix2_ix3(
  2431. soc->hal_soc, ring,
  2432. soc->num_reo_dest_rings -
  2433. USE_1_IPA_RX_REO_RING, remap1,
  2434. remap2);
  2435. }
  2436. hal_compute_reo_remap_ix0(soc->hal_soc, remap0);
  2437. break;
  2438. default:
  2439. dp_err("unknown arch_id 0x%x", soc->arch_id);
  2440. QDF_BUG(0);
  2441. }
  2442. dp_debug("remap1 %x remap2 %x", *remap1, *remap2);
  2443. return true;
  2444. }
  2445. #ifdef IPA_WDI3_TX_TWO_PIPES
  2446. static bool dp_ipa_is_alt_tx_ring(int index)
  2447. {
  2448. return index == IPA_TX_ALT_RING_IDX;
  2449. }
  2450. static bool dp_ipa_is_alt_tx_comp_ring(int index)
  2451. {
  2452. return index == IPA_TX_ALT_COMP_RING_IDX;
  2453. }
  2454. #else /* !IPA_WDI3_TX_TWO_PIPES */
  2455. static bool dp_ipa_is_alt_tx_ring(int index)
  2456. {
  2457. return false;
  2458. }
  2459. static bool dp_ipa_is_alt_tx_comp_ring(int index)
  2460. {
  2461. return false;
  2462. }
  2463. #endif /* IPA_WDI3_TX_TWO_PIPES */
  2464. /**
  2465. * dp_ipa_get_tx_ring_size() - Get Tx ring size for IPA
  2466. *
  2467. * @tx_ring_num: Tx ring number
  2468. * @tx_ipa_ring_sz: Return param only updated for IPA.
  2469. * @soc_cfg_ctx: dp soc cfg context
  2470. *
  2471. * Return: None
  2472. */
  2473. static void dp_ipa_get_tx_ring_size(int tx_ring_num, int *tx_ipa_ring_sz,
  2474. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2475. {
  2476. if (!soc_cfg_ctx->ipa_enabled)
  2477. return;
  2478. if (tx_ring_num == IPA_TCL_DATA_RING_IDX)
  2479. *tx_ipa_ring_sz = wlan_cfg_ipa_tx_ring_size(soc_cfg_ctx);
  2480. else if (dp_ipa_is_alt_tx_ring(tx_ring_num))
  2481. *tx_ipa_ring_sz = wlan_cfg_ipa_tx_alt_ring_size(soc_cfg_ctx);
  2482. }
  2483. /**
  2484. * dp_ipa_get_tx_comp_ring_size() - Get Tx comp ring size for IPA
  2485. *
  2486. * @tx_comp_ring_num: Tx comp ring number
  2487. * @tx_comp_ipa_ring_sz: Return param only updated for IPA.
  2488. * @soc_cfg_ctx: dp soc cfg context
  2489. *
  2490. * Return: None
  2491. */
  2492. static void dp_ipa_get_tx_comp_ring_size(int tx_comp_ring_num,
  2493. int *tx_comp_ipa_ring_sz,
  2494. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2495. {
  2496. if (!soc_cfg_ctx->ipa_enabled)
  2497. return;
  2498. if (tx_comp_ring_num == IPA_TCL_DATA_RING_IDX)
  2499. *tx_comp_ipa_ring_sz =
  2500. wlan_cfg_ipa_tx_comp_ring_size(soc_cfg_ctx);
  2501. else if (dp_ipa_is_alt_tx_comp_ring(tx_comp_ring_num))
  2502. *tx_comp_ipa_ring_sz =
  2503. wlan_cfg_ipa_tx_alt_comp_ring_size(soc_cfg_ctx);
  2504. }
  2505. #else
  2506. static uint8_t dp_reo_ring_selection(uint32_t value, uint32_t *ring)
  2507. {
  2508. uint8_t num = 0;
  2509. switch (value) {
  2510. /* should we have all the different possible ring configs */
  2511. case 0xFF:
  2512. num = 8;
  2513. ring[0] = REO_REMAP_SW1;
  2514. ring[1] = REO_REMAP_SW2;
  2515. ring[2] = REO_REMAP_SW3;
  2516. ring[3] = REO_REMAP_SW4;
  2517. ring[4] = REO_REMAP_SW5;
  2518. ring[5] = REO_REMAP_SW6;
  2519. ring[6] = REO_REMAP_SW7;
  2520. ring[7] = REO_REMAP_SW8;
  2521. break;
  2522. case 0x3F:
  2523. num = 6;
  2524. ring[0] = REO_REMAP_SW1;
  2525. ring[1] = REO_REMAP_SW2;
  2526. ring[2] = REO_REMAP_SW3;
  2527. ring[3] = REO_REMAP_SW4;
  2528. ring[4] = REO_REMAP_SW5;
  2529. ring[5] = REO_REMAP_SW6;
  2530. break;
  2531. case 0xF:
  2532. num = 4;
  2533. ring[0] = REO_REMAP_SW1;
  2534. ring[1] = REO_REMAP_SW2;
  2535. ring[2] = REO_REMAP_SW3;
  2536. ring[3] = REO_REMAP_SW4;
  2537. break;
  2538. case 0xE:
  2539. num = 3;
  2540. ring[0] = REO_REMAP_SW2;
  2541. ring[1] = REO_REMAP_SW3;
  2542. ring[2] = REO_REMAP_SW4;
  2543. break;
  2544. case 0xD:
  2545. num = 3;
  2546. ring[0] = REO_REMAP_SW1;
  2547. ring[1] = REO_REMAP_SW3;
  2548. ring[2] = REO_REMAP_SW4;
  2549. break;
  2550. case 0xC:
  2551. num = 2;
  2552. ring[0] = REO_REMAP_SW3;
  2553. ring[1] = REO_REMAP_SW4;
  2554. break;
  2555. case 0xB:
  2556. num = 3;
  2557. ring[0] = REO_REMAP_SW1;
  2558. ring[1] = REO_REMAP_SW2;
  2559. ring[2] = REO_REMAP_SW4;
  2560. break;
  2561. case 0xA:
  2562. num = 2;
  2563. ring[0] = REO_REMAP_SW2;
  2564. ring[1] = REO_REMAP_SW4;
  2565. break;
  2566. case 0x9:
  2567. num = 2;
  2568. ring[0] = REO_REMAP_SW1;
  2569. ring[1] = REO_REMAP_SW4;
  2570. break;
  2571. case 0x8:
  2572. num = 1;
  2573. ring[0] = REO_REMAP_SW4;
  2574. break;
  2575. case 0x7:
  2576. num = 3;
  2577. ring[0] = REO_REMAP_SW1;
  2578. ring[1] = REO_REMAP_SW2;
  2579. ring[2] = REO_REMAP_SW3;
  2580. break;
  2581. case 0x6:
  2582. num = 2;
  2583. ring[0] = REO_REMAP_SW2;
  2584. ring[1] = REO_REMAP_SW3;
  2585. break;
  2586. case 0x5:
  2587. num = 2;
  2588. ring[0] = REO_REMAP_SW1;
  2589. ring[1] = REO_REMAP_SW3;
  2590. break;
  2591. case 0x4:
  2592. num = 1;
  2593. ring[0] = REO_REMAP_SW3;
  2594. break;
  2595. case 0x3:
  2596. num = 2;
  2597. ring[0] = REO_REMAP_SW1;
  2598. ring[1] = REO_REMAP_SW2;
  2599. break;
  2600. case 0x2:
  2601. num = 1;
  2602. ring[0] = REO_REMAP_SW2;
  2603. break;
  2604. case 0x1:
  2605. num = 1;
  2606. ring[0] = REO_REMAP_SW1;
  2607. break;
  2608. default:
  2609. dp_err("unknown reo ring map 0x%x", value);
  2610. QDF_BUG(0);
  2611. }
  2612. return num;
  2613. }
  2614. bool dp_reo_remap_config(struct dp_soc *soc,
  2615. uint32_t *remap0,
  2616. uint32_t *remap1,
  2617. uint32_t *remap2)
  2618. {
  2619. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2620. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  2621. uint8_t num;
  2622. uint32_t ring[WLAN_CFG_NUM_REO_DEST_RING_MAX];
  2623. uint32_t value;
  2624. switch (offload_radio) {
  2625. case dp_nss_cfg_default:
  2626. value = reo_config & WLAN_CFG_NUM_REO_RINGS_MAP_MAX;
  2627. num = dp_reo_ring_selection(value, ring);
  2628. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2629. num, remap1, remap2);
  2630. hal_compute_reo_remap_ix0(soc->hal_soc, remap0);
  2631. break;
  2632. case dp_nss_cfg_first_radio:
  2633. value = reo_config & 0xE;
  2634. num = dp_reo_ring_selection(value, ring);
  2635. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2636. num, remap1, remap2);
  2637. break;
  2638. case dp_nss_cfg_second_radio:
  2639. value = reo_config & 0xD;
  2640. num = dp_reo_ring_selection(value, ring);
  2641. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2642. num, remap1, remap2);
  2643. break;
  2644. case dp_nss_cfg_dbdc:
  2645. case dp_nss_cfg_dbtc:
  2646. /* return false if both or all are offloaded to NSS */
  2647. return false;
  2648. }
  2649. dp_debug("remap1 %x remap2 %x offload_radio %u",
  2650. *remap1, *remap2, offload_radio);
  2651. return true;
  2652. }
  2653. static void dp_ipa_get_tx_ring_size(int ring_num, int *tx_ipa_ring_sz,
  2654. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2655. {
  2656. }
  2657. static void dp_ipa_get_tx_comp_ring_size(int tx_comp_ring_num,
  2658. int *tx_comp_ipa_ring_sz,
  2659. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2660. {
  2661. }
  2662. #endif /* IPA_OFFLOAD */
  2663. /**
  2664. * dp_reo_frag_dst_set() - configure reo register to set the
  2665. * fragment destination ring
  2666. * @soc: Datapath soc
  2667. * @frag_dst_ring: output parameter to set fragment destination ring
  2668. *
  2669. * Based on offload_radio below fragment destination rings is selected
  2670. * 0 - TCL
  2671. * 1 - SW1
  2672. * 2 - SW2
  2673. * 3 - SW3
  2674. * 4 - SW4
  2675. * 5 - Release
  2676. * 6 - FW
  2677. * 7 - alternate select
  2678. *
  2679. * Return: void
  2680. */
  2681. void dp_reo_frag_dst_set(struct dp_soc *soc, uint8_t *frag_dst_ring)
  2682. {
  2683. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2684. switch (offload_radio) {
  2685. case dp_nss_cfg_default:
  2686. *frag_dst_ring = REO_REMAP_TCL;
  2687. break;
  2688. case dp_nss_cfg_first_radio:
  2689. /*
  2690. * This configuration is valid for single band radio which
  2691. * is also NSS offload.
  2692. */
  2693. case dp_nss_cfg_dbdc:
  2694. case dp_nss_cfg_dbtc:
  2695. *frag_dst_ring = HAL_SRNG_REO_ALTERNATE_SELECT;
  2696. break;
  2697. default:
  2698. dp_init_err("%pK: dp_reo_frag_dst_set invalid offload radio config", soc);
  2699. break;
  2700. }
  2701. }
  2702. #ifdef WLAN_FEATURE_STATS_EXT
  2703. static inline void dp_create_ext_stats_event(struct dp_soc *soc)
  2704. {
  2705. qdf_event_create(&soc->rx_hw_stats_event);
  2706. }
  2707. #else
  2708. static inline void dp_create_ext_stats_event(struct dp_soc *soc)
  2709. {
  2710. }
  2711. #endif
  2712. static void dp_deinit_tx_pair_by_index(struct dp_soc *soc, int index)
  2713. {
  2714. int tcl_ring_num, wbm_ring_num;
  2715. wlan_cfg_get_tcl_wbm_ring_num_for_index(soc->wlan_cfg_ctx,
  2716. index,
  2717. &tcl_ring_num,
  2718. &wbm_ring_num);
  2719. if (tcl_ring_num == -1) {
  2720. dp_err("incorrect tcl ring num for index %u", index);
  2721. return;
  2722. }
  2723. wlan_minidump_remove(soc->tcl_data_ring[index].base_vaddr_unaligned,
  2724. soc->tcl_data_ring[index].alloc_size,
  2725. soc->ctrl_psoc,
  2726. WLAN_MD_DP_SRNG_TCL_DATA,
  2727. "tcl_data_ring");
  2728. dp_info("index %u tcl %u wbm %u", index, tcl_ring_num, wbm_ring_num);
  2729. dp_srng_deinit(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2730. tcl_ring_num);
  2731. if (wbm_ring_num == INVALID_WBM_RING_NUM)
  2732. return;
  2733. wlan_minidump_remove(soc->tx_comp_ring[index].base_vaddr_unaligned,
  2734. soc->tx_comp_ring[index].alloc_size,
  2735. soc->ctrl_psoc,
  2736. WLAN_MD_DP_SRNG_TX_COMP,
  2737. "tcl_comp_ring");
  2738. dp_srng_deinit(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2739. wbm_ring_num);
  2740. }
  2741. /**
  2742. * dp_init_tx_ring_pair_by_index() - The function inits tcl data/wbm completion
  2743. * ring pair
  2744. * @soc: DP soc pointer
  2745. * @index: index of soc->tcl_data or soc->tx_comp to initialize
  2746. *
  2747. * Return: QDF_STATUS_SUCCESS on success, error code otherwise.
  2748. */
  2749. static QDF_STATUS dp_init_tx_ring_pair_by_index(struct dp_soc *soc,
  2750. uint8_t index)
  2751. {
  2752. int tcl_ring_num, wbm_ring_num;
  2753. uint8_t bm_id;
  2754. if (index >= MAX_TCL_DATA_RINGS) {
  2755. dp_err("unexpected index!");
  2756. QDF_BUG(0);
  2757. goto fail1;
  2758. }
  2759. wlan_cfg_get_tcl_wbm_ring_num_for_index(soc->wlan_cfg_ctx,
  2760. index,
  2761. &tcl_ring_num,
  2762. &wbm_ring_num);
  2763. if (tcl_ring_num == -1) {
  2764. dp_err("incorrect tcl ring num for index %u", index);
  2765. goto fail1;
  2766. }
  2767. dp_info("index %u tcl %u wbm %u", index, tcl_ring_num, wbm_ring_num);
  2768. if (dp_srng_init(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2769. tcl_ring_num, 0)) {
  2770. dp_err("dp_srng_init failed for tcl_data_ring");
  2771. goto fail1;
  2772. }
  2773. wlan_minidump_log(soc->tcl_data_ring[index].base_vaddr_unaligned,
  2774. soc->tcl_data_ring[index].alloc_size,
  2775. soc->ctrl_psoc,
  2776. WLAN_MD_DP_SRNG_TCL_DATA,
  2777. "tcl_data_ring");
  2778. if (wbm_ring_num == INVALID_WBM_RING_NUM)
  2779. goto set_rbm;
  2780. if (dp_srng_init(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2781. wbm_ring_num, 0)) {
  2782. dp_err("dp_srng_init failed for tx_comp_ring");
  2783. goto fail1;
  2784. }
  2785. wlan_minidump_log(soc->tx_comp_ring[index].base_vaddr_unaligned,
  2786. soc->tx_comp_ring[index].alloc_size,
  2787. soc->ctrl_psoc,
  2788. WLAN_MD_DP_SRNG_TX_COMP,
  2789. "tcl_comp_ring");
  2790. set_rbm:
  2791. bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx, tcl_ring_num);
  2792. soc->arch_ops.tx_implicit_rbm_set(soc, tcl_ring_num, bm_id);
  2793. return QDF_STATUS_SUCCESS;
  2794. fail1:
  2795. return QDF_STATUS_E_FAILURE;
  2796. }
  2797. static void dp_free_tx_ring_pair_by_index(struct dp_soc *soc, uint8_t index)
  2798. {
  2799. dp_debug("index %u", index);
  2800. dp_srng_free(soc, &soc->tcl_data_ring[index]);
  2801. dp_srng_free(soc, &soc->tx_comp_ring[index]);
  2802. }
  2803. /**
  2804. * dp_alloc_tx_ring_pair_by_index() - The function allocs tcl data/wbm2sw
  2805. * ring pair for the given "index"
  2806. * @soc: DP soc pointer
  2807. * @index: index of soc->tcl_data or soc->tx_comp to initialize
  2808. *
  2809. * Return: QDF_STATUS_SUCCESS on success, error code otherwise.
  2810. */
  2811. static QDF_STATUS dp_alloc_tx_ring_pair_by_index(struct dp_soc *soc,
  2812. uint8_t index)
  2813. {
  2814. int tx_ring_size;
  2815. int tx_comp_ring_size;
  2816. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  2817. int cached = 0;
  2818. if (index >= MAX_TCL_DATA_RINGS) {
  2819. dp_err("unexpected index!");
  2820. QDF_BUG(0);
  2821. goto fail1;
  2822. }
  2823. dp_debug("index %u", index);
  2824. tx_ring_size = wlan_cfg_tx_ring_size(soc_cfg_ctx);
  2825. dp_ipa_get_tx_ring_size(index, &tx_ring_size, soc_cfg_ctx);
  2826. if (dp_srng_alloc(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2827. tx_ring_size, cached)) {
  2828. dp_err("dp_srng_alloc failed for tcl_data_ring");
  2829. goto fail1;
  2830. }
  2831. tx_comp_ring_size = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
  2832. dp_ipa_get_tx_comp_ring_size(index, &tx_comp_ring_size, soc_cfg_ctx);
  2833. /* Enable cached TCL desc if NSS offload is disabled */
  2834. if (!wlan_cfg_get_dp_soc_nss_cfg(soc_cfg_ctx))
  2835. cached = WLAN_CFG_DST_RING_CACHED_DESC;
  2836. if (wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, index) ==
  2837. INVALID_WBM_RING_NUM)
  2838. return QDF_STATUS_SUCCESS;
  2839. if (dp_srng_alloc(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2840. tx_comp_ring_size, cached)) {
  2841. dp_err("dp_srng_alloc failed for tx_comp_ring");
  2842. goto fail1;
  2843. }
  2844. return QDF_STATUS_SUCCESS;
  2845. fail1:
  2846. return QDF_STATUS_E_FAILURE;
  2847. }
  2848. /**
  2849. * dp_dscp_tid_map_setup() - Initialize the dscp-tid maps
  2850. * @pdev: DP_PDEV handle
  2851. *
  2852. * Return: void
  2853. */
  2854. void
  2855. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  2856. {
  2857. uint8_t map_id;
  2858. struct dp_soc *soc = pdev->soc;
  2859. if (!soc)
  2860. return;
  2861. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  2862. qdf_mem_copy(pdev->dscp_tid_map[map_id],
  2863. default_dscp_tid_map,
  2864. sizeof(default_dscp_tid_map));
  2865. }
  2866. for (map_id = 0; map_id < soc->num_hw_dscp_tid_map; map_id++) {
  2867. hal_tx_set_dscp_tid_map(soc->hal_soc,
  2868. default_dscp_tid_map,
  2869. map_id);
  2870. }
  2871. }
  2872. /**
  2873. * dp_pcp_tid_map_setup() - Initialize the pcp-tid maps
  2874. * @pdev: DP_PDEV handle
  2875. *
  2876. * Return: void
  2877. */
  2878. void
  2879. dp_pcp_tid_map_setup(struct dp_pdev *pdev)
  2880. {
  2881. struct dp_soc *soc = pdev->soc;
  2882. if (!soc)
  2883. return;
  2884. qdf_mem_copy(soc->pcp_tid_map, default_pcp_tid_map,
  2885. sizeof(default_pcp_tid_map));
  2886. hal_tx_set_pcp_tid_map_default(soc->hal_soc, default_pcp_tid_map);
  2887. }
  2888. #ifndef DP_UMAC_HW_RESET_SUPPORT
  2889. static inline
  2890. #endif
  2891. void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2892. {
  2893. struct reo_desc_list_node *desc;
  2894. struct dp_rx_tid *rx_tid;
  2895. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2896. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2897. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2898. rx_tid = &desc->rx_tid;
  2899. qdf_mem_unmap_nbytes_single(soc->osdev,
  2900. rx_tid->hw_qdesc_paddr,
  2901. QDF_DMA_BIDIRECTIONAL,
  2902. rx_tid->hw_qdesc_alloc_size);
  2903. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2904. qdf_mem_free(desc);
  2905. }
  2906. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2907. qdf_list_destroy(&soc->reo_desc_freelist);
  2908. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2909. }
  2910. #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY
  2911. /**
  2912. * dp_reo_desc_deferred_freelist_create() - Initialize the resources used
  2913. * for deferred reo desc list
  2914. * @soc: Datapath soc handle
  2915. *
  2916. * Return: void
  2917. */
  2918. static void dp_reo_desc_deferred_freelist_create(struct dp_soc *soc)
  2919. {
  2920. qdf_spinlock_create(&soc->reo_desc_deferred_freelist_lock);
  2921. qdf_list_create(&soc->reo_desc_deferred_freelist,
  2922. REO_DESC_DEFERRED_FREELIST_SIZE);
  2923. soc->reo_desc_deferred_freelist_init = true;
  2924. }
  2925. /**
  2926. * dp_reo_desc_deferred_freelist_destroy() - loop the deferred free list &
  2927. * free the leftover REO QDESCs
  2928. * @soc: Datapath soc handle
  2929. *
  2930. * Return: void
  2931. */
  2932. static void dp_reo_desc_deferred_freelist_destroy(struct dp_soc *soc)
  2933. {
  2934. struct reo_desc_deferred_freelist_node *desc;
  2935. qdf_spin_lock_bh(&soc->reo_desc_deferred_freelist_lock);
  2936. soc->reo_desc_deferred_freelist_init = false;
  2937. while (qdf_list_remove_front(&soc->reo_desc_deferred_freelist,
  2938. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2939. qdf_mem_unmap_nbytes_single(soc->osdev,
  2940. desc->hw_qdesc_paddr,
  2941. QDF_DMA_BIDIRECTIONAL,
  2942. desc->hw_qdesc_alloc_size);
  2943. qdf_mem_free(desc->hw_qdesc_vaddr_unaligned);
  2944. qdf_mem_free(desc);
  2945. }
  2946. qdf_spin_unlock_bh(&soc->reo_desc_deferred_freelist_lock);
  2947. qdf_list_destroy(&soc->reo_desc_deferred_freelist);
  2948. qdf_spinlock_destroy(&soc->reo_desc_deferred_freelist_lock);
  2949. }
  2950. #else
  2951. static inline void dp_reo_desc_deferred_freelist_create(struct dp_soc *soc)
  2952. {
  2953. }
  2954. static inline void dp_reo_desc_deferred_freelist_destroy(struct dp_soc *soc)
  2955. {
  2956. }
  2957. #endif /* !WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY */
  2958. /**
  2959. * dp_soc_reset_txrx_ring_map() - reset tx ring map
  2960. * @soc: DP SOC handle
  2961. *
  2962. */
  2963. static void dp_soc_reset_txrx_ring_map(struct dp_soc *soc)
  2964. {
  2965. uint32_t i;
  2966. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++)
  2967. soc->tx_ring_map[i] = 0;
  2968. }
  2969. /**
  2970. * dp_soc_deinit() - Deinitialize txrx SOC
  2971. * @txrx_soc: Opaque DP SOC handle
  2972. *
  2973. * Return: None
  2974. */
  2975. void dp_soc_deinit(void *txrx_soc)
  2976. {
  2977. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2978. struct htt_soc *htt_soc = soc->htt_handle;
  2979. qdf_atomic_set(&soc->cmn_init_done, 0);
  2980. if (soc->arch_ops.txrx_soc_ppeds_stop)
  2981. soc->arch_ops.txrx_soc_ppeds_stop(soc);
  2982. soc->arch_ops.txrx_soc_deinit(soc);
  2983. dp_monitor_soc_deinit(soc);
  2984. /* free peer tables & AST tables allocated during peer_map_attach */
  2985. if (soc->peer_map_attach_success) {
  2986. dp_peer_find_detach(soc);
  2987. soc->arch_ops.txrx_peer_map_detach(soc);
  2988. soc->peer_map_attach_success = FALSE;
  2989. }
  2990. qdf_flush_work(&soc->htt_stats.work);
  2991. qdf_disable_work(&soc->htt_stats.work);
  2992. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2993. dp_soc_reset_txrx_ring_map(soc);
  2994. dp_reo_desc_freelist_destroy(soc);
  2995. dp_reo_desc_deferred_freelist_destroy(soc);
  2996. DEINIT_RX_HW_STATS_LOCK(soc);
  2997. qdf_spinlock_destroy(&soc->ast_lock);
  2998. dp_peer_mec_spinlock_destroy(soc);
  2999. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  3000. qdf_nbuf_queue_free(&soc->invalid_buf_queue);
  3001. qdf_spinlock_destroy(&soc->rx.defrag.defrag_lock);
  3002. qdf_spinlock_destroy(&soc->vdev_map_lock);
  3003. dp_reo_cmdlist_destroy(soc);
  3004. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  3005. dp_soc_tx_desc_sw_pools_deinit(soc);
  3006. dp_soc_srng_deinit(soc);
  3007. dp_hw_link_desc_ring_deinit(soc);
  3008. dp_soc_print_inactive_objects(soc);
  3009. qdf_spinlock_destroy(&soc->inactive_peer_list_lock);
  3010. qdf_spinlock_destroy(&soc->inactive_vdev_list_lock);
  3011. htt_soc_htc_dealloc(soc->htt_handle);
  3012. htt_soc_detach(htt_soc);
  3013. /* Free wbm sg list and reset flags in down path */
  3014. dp_rx_wbm_sg_list_deinit(soc);
  3015. wlan_minidump_remove(soc, sizeof(*soc), soc->ctrl_psoc,
  3016. WLAN_MD_DP_SOC, "dp_soc");
  3017. }
  3018. #ifdef QCA_HOST2FW_RXBUF_RING
  3019. void
  3020. dp_htt_setup_rxdma_err_dst_ring(struct dp_soc *soc, int mac_id,
  3021. int lmac_id)
  3022. {
  3023. if (soc->rxdma_err_dst_ring[lmac_id].hal_srng)
  3024. htt_srng_setup(soc->htt_handle, mac_id,
  3025. soc->rxdma_err_dst_ring[lmac_id].hal_srng,
  3026. RXDMA_DST);
  3027. }
  3028. #endif
  3029. #ifdef WLAN_SUPPORT_PPEDS
  3030. static inline
  3031. void dp_soc_txrx_peer_setup(enum wlan_op_mode vdev_opmode, struct dp_soc *soc,
  3032. struct dp_peer *peer)
  3033. {
  3034. if (((vdev_opmode == wlan_op_mode_ap) ||
  3035. (vdev_opmode == wlan_op_mode_sta)) &&
  3036. (soc->arch_ops.txrx_peer_setup)) {
  3037. if (soc->arch_ops.txrx_peer_setup(soc, peer)
  3038. != QDF_STATUS_SUCCESS) {
  3039. dp_err("unable to setup target peer features");
  3040. qdf_assert_always(0);
  3041. }
  3042. }
  3043. }
  3044. #else
  3045. static inline
  3046. void dp_soc_txrx_peer_setup(enum wlan_op_mode vdev_opmode, struct dp_soc *soc,
  3047. struct dp_peer *peer)
  3048. {
  3049. }
  3050. #endif /* WLAN_SUPPORT_PPEDS */
  3051. void dp_vdev_get_default_reo_hash(struct dp_vdev *vdev,
  3052. enum cdp_host_reo_dest_ring *reo_dest,
  3053. bool *hash_based)
  3054. {
  3055. struct dp_soc *soc;
  3056. struct dp_pdev *pdev;
  3057. pdev = vdev->pdev;
  3058. soc = pdev->soc;
  3059. /*
  3060. * hash based steering is disabled for Radios which are offloaded
  3061. * to NSS
  3062. */
  3063. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  3064. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  3065. /*
  3066. * Below line of code will ensure the proper reo_dest ring is chosen
  3067. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  3068. */
  3069. *reo_dest = pdev->reo_dest;
  3070. }
  3071. #ifdef IPA_OFFLOAD
  3072. /**
  3073. * dp_is_vdev_subtype_p2p() - Check if the subtype for vdev is P2P
  3074. * @vdev: Virtual device
  3075. *
  3076. * Return: true if the vdev is of subtype P2P
  3077. * false if the vdev is of any other subtype
  3078. */
  3079. static inline bool dp_is_vdev_subtype_p2p(struct dp_vdev *vdev)
  3080. {
  3081. if (vdev->subtype == wlan_op_subtype_p2p_device ||
  3082. vdev->subtype == wlan_op_subtype_p2p_cli ||
  3083. vdev->subtype == wlan_op_subtype_p2p_go)
  3084. return true;
  3085. return false;
  3086. }
  3087. /**
  3088. * dp_peer_setup_get_reo_hash() - get reo dest ring and hash values for a peer
  3089. * @vdev: Datapath VDEV handle
  3090. * @setup_info:
  3091. * @reo_dest: pointer to default reo_dest ring for vdev to be populated
  3092. * @hash_based: pointer to hash value (enabled/disabled) to be populated
  3093. * @lmac_peer_id_msb:
  3094. *
  3095. * If IPA is enabled in ini, for SAP mode, disable hash based
  3096. * steering, use default reo_dst ring for RX. Use config values for other modes.
  3097. *
  3098. * Return: None
  3099. */
  3100. static void dp_peer_setup_get_reo_hash(struct dp_vdev *vdev,
  3101. struct cdp_peer_setup_info *setup_info,
  3102. enum cdp_host_reo_dest_ring *reo_dest,
  3103. bool *hash_based,
  3104. uint8_t *lmac_peer_id_msb)
  3105. {
  3106. struct dp_soc *soc;
  3107. struct dp_pdev *pdev;
  3108. pdev = vdev->pdev;
  3109. soc = pdev->soc;
  3110. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  3111. /* For P2P-GO interfaces we do not need to change the REO
  3112. * configuration even if IPA config is enabled
  3113. */
  3114. if (dp_is_vdev_subtype_p2p(vdev))
  3115. return;
  3116. /*
  3117. * If IPA is enabled, disable hash-based flow steering and set
  3118. * reo_dest_ring_4 as the REO ring to receive packets on.
  3119. * IPA is configured to reap reo_dest_ring_4.
  3120. *
  3121. * Note - REO DST indexes are from 0 - 3, while cdp_host_reo_dest_ring
  3122. * value enum value is from 1 - 4.
  3123. * Hence, *reo_dest = IPA_REO_DEST_RING_IDX + 1
  3124. */
  3125. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  3126. if (vdev->opmode == wlan_op_mode_ap) {
  3127. *reo_dest = IPA_REO_DEST_RING_IDX + 1;
  3128. *hash_based = 0;
  3129. } else if (vdev->opmode == wlan_op_mode_sta &&
  3130. dp_ipa_is_mdm_platform()) {
  3131. *reo_dest = IPA_REO_DEST_RING_IDX + 1;
  3132. } else if (vdev->opmode == wlan_op_mode_sta &&
  3133. (!dp_ipa_is_mdm_platform())) {
  3134. dp_debug("opt_dp: default reo ring is set");
  3135. }
  3136. }
  3137. }
  3138. #else
  3139. /**
  3140. * dp_peer_setup_get_reo_hash() - get reo dest ring and hash values for a peer
  3141. * @vdev: Datapath VDEV handle
  3142. * @setup_info:
  3143. * @reo_dest: pointer to default reo_dest ring for vdev to be populated
  3144. * @hash_based: pointer to hash value (enabled/disabled) to be populated
  3145. * @lmac_peer_id_msb:
  3146. *
  3147. * Use system config values for hash based steering.
  3148. * Return: None
  3149. */
  3150. static void dp_peer_setup_get_reo_hash(struct dp_vdev *vdev,
  3151. struct cdp_peer_setup_info *setup_info,
  3152. enum cdp_host_reo_dest_ring *reo_dest,
  3153. bool *hash_based,
  3154. uint8_t *lmac_peer_id_msb)
  3155. {
  3156. struct dp_soc *soc = vdev->pdev->soc;
  3157. soc->arch_ops.peer_get_reo_hash(vdev, setup_info, reo_dest, hash_based,
  3158. lmac_peer_id_msb);
  3159. }
  3160. #endif /* IPA_OFFLOAD */
  3161. /**
  3162. * dp_peer_setup_wifi3() - initialize the peer
  3163. * @soc_hdl: soc handle object
  3164. * @vdev_id: vdev_id of vdev object
  3165. * @peer_mac: Peer's mac address
  3166. * @setup_info: peer setup info for MLO
  3167. *
  3168. * Return: QDF_STATUS
  3169. */
  3170. QDF_STATUS
  3171. dp_peer_setup_wifi3(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3172. uint8_t *peer_mac,
  3173. struct cdp_peer_setup_info *setup_info)
  3174. {
  3175. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3176. struct dp_pdev *pdev;
  3177. bool hash_based = 0;
  3178. enum cdp_host_reo_dest_ring reo_dest;
  3179. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3180. struct dp_vdev *vdev = NULL;
  3181. struct dp_peer *peer =
  3182. dp_peer_find_hash_find(soc, peer_mac, 0, vdev_id,
  3183. DP_MOD_ID_CDP);
  3184. struct dp_peer *mld_peer = NULL;
  3185. enum wlan_op_mode vdev_opmode;
  3186. uint8_t lmac_peer_id_msb = 0;
  3187. if (!peer)
  3188. return QDF_STATUS_E_FAILURE;
  3189. vdev = peer->vdev;
  3190. if (!vdev) {
  3191. status = QDF_STATUS_E_FAILURE;
  3192. goto fail;
  3193. }
  3194. /* save vdev related member in case vdev freed */
  3195. vdev_opmode = vdev->opmode;
  3196. pdev = vdev->pdev;
  3197. dp_peer_setup_get_reo_hash(vdev, setup_info,
  3198. &reo_dest, &hash_based,
  3199. &lmac_peer_id_msb);
  3200. dp_cfg_event_record_peer_setup_evt(soc, DP_CFG_EVENT_PEER_SETUP,
  3201. peer, vdev, vdev->vdev_id,
  3202. setup_info);
  3203. dp_info("pdev: %d vdev :%d opmode:%u peer %pK (" QDF_MAC_ADDR_FMT ") "
  3204. "hash-based-steering:%d default-reo_dest:%u",
  3205. pdev->pdev_id, vdev->vdev_id,
  3206. vdev->opmode, peer,
  3207. QDF_MAC_ADDR_REF(peer->mac_addr.raw), hash_based, reo_dest);
  3208. /*
  3209. * There are corner cases where the AD1 = AD2 = "VAPs address"
  3210. * i.e both the devices have same MAC address. In these
  3211. * cases we want such pkts to be processed in NULL Q handler
  3212. * which is REO2TCL ring. for this reason we should
  3213. * not setup reo_queues and default route for bss_peer.
  3214. */
  3215. if (!IS_MLO_DP_MLD_PEER(peer))
  3216. dp_monitor_peer_tx_init(pdev, peer);
  3217. if (!setup_info)
  3218. if (dp_peer_legacy_setup(soc, peer) !=
  3219. QDF_STATUS_SUCCESS) {
  3220. status = QDF_STATUS_E_RESOURCES;
  3221. goto fail;
  3222. }
  3223. if (peer->bss_peer && vdev->opmode == wlan_op_mode_ap) {
  3224. status = QDF_STATUS_E_FAILURE;
  3225. goto fail;
  3226. }
  3227. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  3228. /* TODO: Check the destination ring number to be passed to FW */
  3229. soc->cdp_soc.ol_ops->peer_set_default_routing(
  3230. soc->ctrl_psoc,
  3231. peer->vdev->pdev->pdev_id,
  3232. peer->mac_addr.raw,
  3233. peer->vdev->vdev_id, hash_based, reo_dest,
  3234. lmac_peer_id_msb);
  3235. }
  3236. qdf_atomic_set(&peer->is_default_route_set, 1);
  3237. status = dp_peer_mlo_setup(soc, peer, vdev->vdev_id, setup_info);
  3238. if (QDF_IS_STATUS_ERROR(status)) {
  3239. dp_peer_err("peer mlo setup failed");
  3240. qdf_assert_always(0);
  3241. }
  3242. if (vdev_opmode != wlan_op_mode_monitor) {
  3243. /* In case of MLD peer, switch peer to mld peer and
  3244. * do peer_rx_init.
  3245. */
  3246. if (hal_reo_shared_qaddr_is_enable(soc->hal_soc) &&
  3247. IS_MLO_DP_LINK_PEER(peer)) {
  3248. if (setup_info && setup_info->is_first_link) {
  3249. mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
  3250. if (mld_peer)
  3251. dp_peer_rx_init(pdev, mld_peer);
  3252. else
  3253. dp_peer_err("MLD peer null. Primary link peer:%pK", peer);
  3254. }
  3255. } else {
  3256. dp_peer_rx_init(pdev, peer);
  3257. }
  3258. }
  3259. dp_soc_txrx_peer_setup(vdev_opmode, soc, peer);
  3260. if (!IS_MLO_DP_MLD_PEER(peer))
  3261. dp_peer_ppdu_delayed_ba_init(peer);
  3262. fail:
  3263. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  3264. return status;
  3265. }
  3266. /**
  3267. * dp_set_ba_aging_timeout() - set ba aging timeout per AC
  3268. * @txrx_soc: cdp soc handle
  3269. * @ac: Access category
  3270. * @value: timeout value in millisec
  3271. *
  3272. * Return: void
  3273. */
  3274. void dp_set_ba_aging_timeout(struct cdp_soc_t *txrx_soc,
  3275. uint8_t ac, uint32_t value)
  3276. {
  3277. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3278. hal_set_ba_aging_timeout(soc->hal_soc, ac, value);
  3279. }
  3280. /**
  3281. * dp_get_ba_aging_timeout() - get ba aging timeout per AC
  3282. * @txrx_soc: cdp soc handle
  3283. * @ac: access category
  3284. * @value: timeout value in millisec
  3285. *
  3286. * Return: void
  3287. */
  3288. void dp_get_ba_aging_timeout(struct cdp_soc_t *txrx_soc,
  3289. uint8_t ac, uint32_t *value)
  3290. {
  3291. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3292. hal_get_ba_aging_timeout(soc->hal_soc, ac, value);
  3293. }
  3294. /**
  3295. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  3296. * @txrx_soc: cdp soc handle
  3297. * @pdev_id: id of physical device object
  3298. * @val: reo destination ring index (1 - 4)
  3299. *
  3300. * Return: QDF_STATUS
  3301. */
  3302. QDF_STATUS
  3303. dp_set_pdev_reo_dest(struct cdp_soc_t *txrx_soc, uint8_t pdev_id,
  3304. enum cdp_host_reo_dest_ring val)
  3305. {
  3306. struct dp_pdev *pdev =
  3307. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)txrx_soc,
  3308. pdev_id);
  3309. if (pdev) {
  3310. pdev->reo_dest = val;
  3311. return QDF_STATUS_SUCCESS;
  3312. }
  3313. return QDF_STATUS_E_FAILURE;
  3314. }
  3315. /**
  3316. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  3317. * @txrx_soc: cdp soc handle
  3318. * @pdev_id: id of physical device object
  3319. *
  3320. * Return: reo destination ring index
  3321. */
  3322. enum cdp_host_reo_dest_ring
  3323. dp_get_pdev_reo_dest(struct cdp_soc_t *txrx_soc, uint8_t pdev_id)
  3324. {
  3325. struct dp_pdev *pdev =
  3326. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)txrx_soc,
  3327. pdev_id);
  3328. if (pdev)
  3329. return pdev->reo_dest;
  3330. else
  3331. return cdp_host_reo_dest_ring_unknown;
  3332. }
  3333. void dp_rx_bar_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3334. union hal_reo_status *reo_status)
  3335. {
  3336. struct dp_pdev *pdev = (struct dp_pdev *)cb_ctxt;
  3337. struct hal_reo_queue_status *queue_status = &(reo_status->queue_status);
  3338. if (!dp_check_pdev_exists(soc, pdev)) {
  3339. dp_err_rl("pdev doesn't exist");
  3340. return;
  3341. }
  3342. if (!qdf_atomic_read(&soc->cmn_init_done))
  3343. return;
  3344. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3345. DP_PRINT_STATS("REO stats failure %d",
  3346. queue_status->header.status);
  3347. qdf_atomic_set(&(pdev->stats_cmd_complete), 1);
  3348. return;
  3349. }
  3350. pdev->stats.rx.bar_recv_cnt += queue_status->bar_rcvd_cnt;
  3351. qdf_atomic_set(&(pdev->stats_cmd_complete), 1);
  3352. }
  3353. /**
  3354. * dp_dump_wbm_idle_hptp() - dump wbm idle ring, hw hp tp info.
  3355. * @soc: dp soc.
  3356. * @pdev: dp pdev.
  3357. *
  3358. * Return: None.
  3359. */
  3360. void
  3361. dp_dump_wbm_idle_hptp(struct dp_soc *soc, struct dp_pdev *pdev)
  3362. {
  3363. uint32_t hw_head;
  3364. uint32_t hw_tail;
  3365. struct dp_srng *srng;
  3366. if (!soc) {
  3367. dp_err("soc is NULL");
  3368. return;
  3369. }
  3370. if (!pdev) {
  3371. dp_err("pdev is NULL");
  3372. return;
  3373. }
  3374. srng = &pdev->soc->wbm_idle_link_ring;
  3375. if (!srng) {
  3376. dp_err("wbm_idle_link_ring srng is NULL");
  3377. return;
  3378. }
  3379. hal_get_hw_hptp(soc->hal_soc, srng->hal_srng, &hw_head,
  3380. &hw_tail, WBM_IDLE_LINK);
  3381. dp_debug("WBM_IDLE_LINK: HW hp: %d, HW tp: %d",
  3382. hw_head, hw_tail);
  3383. }
  3384. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3385. static void dp_update_soft_irq_limits(struct dp_soc *soc, uint32_t tx_limit,
  3386. uint32_t rx_limit)
  3387. {
  3388. soc->wlan_cfg_ctx->tx_comp_loop_pkt_limit = tx_limit;
  3389. soc->wlan_cfg_ctx->rx_reap_loop_pkt_limit = rx_limit;
  3390. }
  3391. #else
  3392. static inline
  3393. void dp_update_soft_irq_limits(struct dp_soc *soc, uint32_t tx_limit,
  3394. uint32_t rx_limit)
  3395. {
  3396. }
  3397. #endif /* WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT */
  3398. /**
  3399. * dp_display_srng_info() - Dump the srng HP TP info
  3400. * @soc_hdl: CDP Soc handle
  3401. *
  3402. * This function dumps the SW hp/tp values for the important rings.
  3403. * HW hp/tp values are not being dumped, since it can lead to
  3404. * READ NOC error when UMAC is in low power state. MCC does not have
  3405. * device force wake working yet.
  3406. *
  3407. * Return: none
  3408. */
  3409. void dp_display_srng_info(struct cdp_soc_t *soc_hdl)
  3410. {
  3411. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3412. hal_soc_handle_t hal_soc = soc->hal_soc;
  3413. uint32_t hp, tp, i;
  3414. dp_info("SRNG HP-TP data:");
  3415. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3416. hal_get_sw_hptp(hal_soc, soc->tcl_data_ring[i].hal_srng,
  3417. &tp, &hp);
  3418. dp_info("TCL DATA ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3419. if (wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, i) ==
  3420. INVALID_WBM_RING_NUM)
  3421. continue;
  3422. hal_get_sw_hptp(hal_soc, soc->tx_comp_ring[i].hal_srng,
  3423. &tp, &hp);
  3424. dp_info("TX comp ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3425. }
  3426. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  3427. hal_get_sw_hptp(hal_soc, soc->reo_dest_ring[i].hal_srng,
  3428. &tp, &hp);
  3429. dp_info("REO DST ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3430. }
  3431. hal_get_sw_hptp(hal_soc, soc->reo_exception_ring.hal_srng, &tp, &hp);
  3432. dp_info("REO exception ring: hp=0x%x, tp=0x%x", hp, tp);
  3433. hal_get_sw_hptp(hal_soc, soc->rx_rel_ring.hal_srng, &tp, &hp);
  3434. dp_info("WBM RX release ring: hp=0x%x, tp=0x%x", hp, tp);
  3435. hal_get_sw_hptp(hal_soc, soc->wbm_desc_rel_ring.hal_srng, &tp, &hp);
  3436. dp_info("WBM desc release ring: hp=0x%x, tp=0x%x", hp, tp);
  3437. }
  3438. /**
  3439. * dp_set_pdev_pcp_tid_map_wifi3() - update pcp tid map in pdev
  3440. * @psoc: dp soc handle
  3441. * @pdev_id: id of DP_PDEV handle
  3442. * @pcp: pcp value
  3443. * @tid: tid value passed by the user
  3444. *
  3445. * Return: QDF_STATUS_SUCCESS on success
  3446. */
  3447. QDF_STATUS dp_set_pdev_pcp_tid_map_wifi3(ol_txrx_soc_handle psoc,
  3448. uint8_t pdev_id,
  3449. uint8_t pcp, uint8_t tid)
  3450. {
  3451. struct dp_soc *soc = (struct dp_soc *)psoc;
  3452. soc->pcp_tid_map[pcp] = tid;
  3453. hal_tx_update_pcp_tid_map(soc->hal_soc, pcp, tid);
  3454. return QDF_STATUS_SUCCESS;
  3455. }
  3456. /**
  3457. * dp_set_vdev_pcp_tid_map_wifi3() - update pcp tid map in vdev
  3458. * @soc_hdl: DP soc handle
  3459. * @vdev_id: id of DP_VDEV handle
  3460. * @pcp: pcp value
  3461. * @tid: tid value passed by the user
  3462. *
  3463. * Return: QDF_STATUS_SUCCESS on success
  3464. */
  3465. QDF_STATUS dp_set_vdev_pcp_tid_map_wifi3(struct cdp_soc_t *soc_hdl,
  3466. uint8_t vdev_id,
  3467. uint8_t pcp, uint8_t tid)
  3468. {
  3469. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3470. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3471. DP_MOD_ID_CDP);
  3472. if (!vdev)
  3473. return QDF_STATUS_E_FAILURE;
  3474. vdev->pcp_tid_map[pcp] = tid;
  3475. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3476. return QDF_STATUS_SUCCESS;
  3477. }
  3478. #if defined(FEATURE_RUNTIME_PM) || defined(DP_POWER_SAVE)
  3479. void dp_drain_txrx(struct cdp_soc_t *soc_handle)
  3480. {
  3481. struct dp_soc *soc = (struct dp_soc *)soc_handle;
  3482. uint32_t cur_tx_limit, cur_rx_limit;
  3483. uint32_t budget = 0xffff;
  3484. uint32_t val;
  3485. int i;
  3486. int cpu = dp_srng_get_cpu();
  3487. cur_tx_limit = soc->wlan_cfg_ctx->tx_comp_loop_pkt_limit;
  3488. cur_rx_limit = soc->wlan_cfg_ctx->rx_reap_loop_pkt_limit;
  3489. /* Temporarily increase soft irq limits when going to drain
  3490. * the UMAC/LMAC SRNGs and restore them after polling.
  3491. * Though the budget is on higher side, the TX/RX reaping loops
  3492. * will not execute longer as both TX and RX would be suspended
  3493. * by the time this API is called.
  3494. */
  3495. dp_update_soft_irq_limits(soc, budget, budget);
  3496. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  3497. dp_service_srngs(&soc->intr_ctx[i], budget, cpu);
  3498. dp_update_soft_irq_limits(soc, cur_tx_limit, cur_rx_limit);
  3499. /* Do a dummy read at offset 0; this will ensure all
  3500. * pendings writes(HP/TP) are flushed before read returns.
  3501. */
  3502. val = HAL_REG_READ((struct hal_soc *)soc->hal_soc, 0);
  3503. dp_debug("Register value at offset 0: %u\n", val);
  3504. }
  3505. #endif
  3506. #if defined(DP_POWER_SAVE) || defined(FEATURE_RUNTIME_PM)
  3507. /**
  3508. * dp_flush_ring_hptp() - Update ring shadow
  3509. * register HP/TP address when runtime
  3510. * resume
  3511. * @soc: DP soc context
  3512. * @hal_srng: srng
  3513. *
  3514. * Return: None
  3515. */
  3516. void dp_flush_ring_hptp(struct dp_soc *soc, hal_ring_handle_t hal_srng)
  3517. {
  3518. if (hal_srng && hal_srng_get_clear_event(hal_srng,
  3519. HAL_SRNG_FLUSH_EVENT)) {
  3520. /* Acquire the lock */
  3521. hal_srng_access_start(soc->hal_soc, hal_srng);
  3522. hal_srng_access_end(soc->hal_soc, hal_srng);
  3523. hal_srng_set_flush_last_ts(hal_srng);
  3524. dp_debug("flushed");
  3525. }
  3526. }
  3527. #endif
  3528. #ifdef FEATURE_RUNTIME_PM
  3529. /**
  3530. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  3531. * @soc_hdl: Datapath soc handle
  3532. * @pdev_id: id of data path pdev handle
  3533. *
  3534. * DP is ready to runtime suspend if there are no pending TX packets.
  3535. *
  3536. * Return: QDF_STATUS
  3537. */
  3538. QDF_STATUS dp_runtime_suspend(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  3539. {
  3540. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3541. struct dp_pdev *pdev;
  3542. uint8_t i;
  3543. int32_t tx_pending;
  3544. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3545. if (!pdev) {
  3546. dp_err("pdev is NULL");
  3547. return QDF_STATUS_E_INVAL;
  3548. }
  3549. /* Abort if there are any pending TX packets */
  3550. tx_pending = dp_get_tx_pending(dp_pdev_to_cdp_pdev(pdev));
  3551. if (tx_pending) {
  3552. dp_info_rl("%pK: Abort suspend due to pending TX packets %d",
  3553. soc, tx_pending);
  3554. dp_find_missing_tx_comp(soc);
  3555. /* perform a force flush if tx is pending */
  3556. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3557. hal_srng_set_event(soc->tcl_data_ring[i].hal_srng,
  3558. HAL_SRNG_FLUSH_EVENT);
  3559. dp_flush_ring_hptp(soc, soc->tcl_data_ring[i].hal_srng);
  3560. }
  3561. qdf_atomic_set(&soc->tx_pending_rtpm, 0);
  3562. return QDF_STATUS_E_AGAIN;
  3563. }
  3564. if (dp_runtime_get_refcount(soc)) {
  3565. dp_init_info("refcount: %d", dp_runtime_get_refcount(soc));
  3566. return QDF_STATUS_E_AGAIN;
  3567. }
  3568. if (soc->intr_mode == DP_INTR_POLL)
  3569. qdf_timer_stop(&soc->int_timer);
  3570. dp_rx_fst_update_pm_suspend_status(soc, true);
  3571. return QDF_STATUS_SUCCESS;
  3572. }
  3573. #define DP_FLUSH_WAIT_CNT 10
  3574. #define DP_RUNTIME_SUSPEND_WAIT_MS 10
  3575. /**
  3576. * dp_runtime_resume() - ensure DP is ready to runtime resume
  3577. * @soc_hdl: Datapath soc handle
  3578. * @pdev_id: id of data path pdev handle
  3579. *
  3580. * Resume DP for runtime PM.
  3581. *
  3582. * Return: QDF_STATUS
  3583. */
  3584. QDF_STATUS dp_runtime_resume(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  3585. {
  3586. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3587. int i, suspend_wait = 0;
  3588. if (soc->intr_mode == DP_INTR_POLL)
  3589. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  3590. /*
  3591. * Wait until dp runtime refcount becomes zero or time out, then flush
  3592. * pending tx for runtime suspend.
  3593. */
  3594. while (dp_runtime_get_refcount(soc) &&
  3595. suspend_wait < DP_FLUSH_WAIT_CNT) {
  3596. qdf_sleep(DP_RUNTIME_SUSPEND_WAIT_MS);
  3597. suspend_wait++;
  3598. }
  3599. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3600. dp_flush_ring_hptp(soc, soc->tcl_data_ring[i].hal_srng);
  3601. }
  3602. qdf_atomic_set(&soc->tx_pending_rtpm, 0);
  3603. dp_flush_ring_hptp(soc, soc->reo_cmd_ring.hal_srng);
  3604. dp_rx_fst_update_pm_suspend_status(soc, false);
  3605. return QDF_STATUS_SUCCESS;
  3606. }
  3607. #endif /* FEATURE_RUNTIME_PM */
  3608. #ifdef WLAN_FEATURE_STATS_EXT
  3609. /* rx hw stats event wait timeout in ms */
  3610. #define DP_REO_STATUS_STATS_TIMEOUT 850
  3611. /**
  3612. * dp_rx_hw_stats_cb() - request rx hw stats response callback
  3613. * @soc: soc handle
  3614. * @cb_ctxt: callback context
  3615. * @reo_status: reo command response status
  3616. *
  3617. * Return: None
  3618. */
  3619. static void dp_rx_hw_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3620. union hal_reo_status *reo_status)
  3621. {
  3622. struct dp_req_rx_hw_stats_t *rx_hw_stats = cb_ctxt;
  3623. struct hal_reo_queue_status *queue_status = &reo_status->queue_status;
  3624. bool is_query_timeout;
  3625. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3626. is_query_timeout = rx_hw_stats->is_query_timeout;
  3627. /* free the cb_ctxt if all pending tid stats query is received */
  3628. if (qdf_atomic_dec_and_test(&rx_hw_stats->pending_tid_stats_cnt)) {
  3629. if (!is_query_timeout) {
  3630. qdf_event_set(&soc->rx_hw_stats_event);
  3631. soc->is_last_stats_ctx_init = false;
  3632. }
  3633. qdf_mem_free(rx_hw_stats);
  3634. }
  3635. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3636. dp_info("REO stats failure %d",
  3637. queue_status->header.status);
  3638. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3639. return;
  3640. }
  3641. if (!is_query_timeout) {
  3642. soc->ext_stats.rx_mpdu_received +=
  3643. queue_status->mpdu_frms_cnt;
  3644. soc->ext_stats.rx_mpdu_missed +=
  3645. queue_status->hole_cnt;
  3646. }
  3647. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3648. }
  3649. /**
  3650. * dp_request_rx_hw_stats() - request rx hardware stats
  3651. * @soc_hdl: soc handle
  3652. * @vdev_id: vdev id
  3653. *
  3654. * Return: None
  3655. */
  3656. QDF_STATUS
  3657. dp_request_rx_hw_stats(struct cdp_soc_t *soc_hdl, uint8_t vdev_id)
  3658. {
  3659. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3660. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3661. DP_MOD_ID_CDP);
  3662. struct dp_peer *peer = NULL;
  3663. QDF_STATUS status;
  3664. struct dp_req_rx_hw_stats_t *rx_hw_stats;
  3665. int rx_stats_sent_cnt = 0;
  3666. uint32_t last_rx_mpdu_received;
  3667. uint32_t last_rx_mpdu_missed;
  3668. if (!vdev) {
  3669. dp_err("vdev is null for vdev_id: %u", vdev_id);
  3670. status = QDF_STATUS_E_INVAL;
  3671. goto out;
  3672. }
  3673. peer = dp_vdev_bss_peer_ref_n_get(soc, vdev, DP_MOD_ID_CDP);
  3674. if (!peer) {
  3675. dp_err("Peer is NULL");
  3676. status = QDF_STATUS_E_INVAL;
  3677. goto out;
  3678. }
  3679. rx_hw_stats = qdf_mem_malloc(sizeof(*rx_hw_stats));
  3680. if (!rx_hw_stats) {
  3681. dp_err("malloc failed for hw stats structure");
  3682. status = QDF_STATUS_E_INVAL;
  3683. goto out;
  3684. }
  3685. qdf_event_reset(&soc->rx_hw_stats_event);
  3686. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3687. /* save the last soc cumulative stats and reset it to 0 */
  3688. last_rx_mpdu_received = soc->ext_stats.rx_mpdu_received;
  3689. last_rx_mpdu_missed = soc->ext_stats.rx_mpdu_missed;
  3690. soc->ext_stats.rx_mpdu_received = 0;
  3691. soc->ext_stats.rx_mpdu_missed = 0;
  3692. dp_debug("HW stats query start");
  3693. rx_stats_sent_cnt =
  3694. dp_peer_rxtid_stats(peer, dp_rx_hw_stats_cb, rx_hw_stats);
  3695. if (!rx_stats_sent_cnt) {
  3696. dp_err("no tid stats sent successfully");
  3697. qdf_mem_free(rx_hw_stats);
  3698. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3699. status = QDF_STATUS_E_INVAL;
  3700. goto out;
  3701. }
  3702. qdf_atomic_set(&rx_hw_stats->pending_tid_stats_cnt,
  3703. rx_stats_sent_cnt);
  3704. rx_hw_stats->is_query_timeout = false;
  3705. soc->is_last_stats_ctx_init = true;
  3706. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3707. status = qdf_wait_single_event(&soc->rx_hw_stats_event,
  3708. DP_REO_STATUS_STATS_TIMEOUT);
  3709. dp_debug("HW stats query end with %d", rx_stats_sent_cnt);
  3710. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3711. if (status != QDF_STATUS_SUCCESS) {
  3712. dp_info("partial rx hw stats event collected with %d",
  3713. qdf_atomic_read(
  3714. &rx_hw_stats->pending_tid_stats_cnt));
  3715. if (soc->is_last_stats_ctx_init)
  3716. rx_hw_stats->is_query_timeout = true;
  3717. /*
  3718. * If query timeout happened, use the last saved stats
  3719. * for this time query.
  3720. */
  3721. soc->ext_stats.rx_mpdu_received = last_rx_mpdu_received;
  3722. soc->ext_stats.rx_mpdu_missed = last_rx_mpdu_missed;
  3723. DP_STATS_INC(soc, rx.rx_hw_stats_timeout, 1);
  3724. }
  3725. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3726. out:
  3727. if (peer)
  3728. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  3729. if (vdev)
  3730. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3731. DP_STATS_INC(soc, rx.rx_hw_stats_requested, 1);
  3732. return status;
  3733. }
  3734. /**
  3735. * dp_reset_rx_hw_ext_stats() - Reset rx hardware ext stats
  3736. * @soc_hdl: soc handle
  3737. *
  3738. * Return: None
  3739. */
  3740. void dp_reset_rx_hw_ext_stats(struct cdp_soc_t *soc_hdl)
  3741. {
  3742. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3743. soc->ext_stats.rx_mpdu_received = 0;
  3744. soc->ext_stats.rx_mpdu_missed = 0;
  3745. }
  3746. #endif /* WLAN_FEATURE_STATS_EXT */
  3747. uint32_t dp_get_tx_rings_grp_bitmap(struct cdp_soc_t *soc_hdl)
  3748. {
  3749. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3750. return soc->wlan_cfg_ctx->tx_rings_grp_bitmap;
  3751. }
  3752. void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  3753. {
  3754. uint32_t i;
  3755. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  3756. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_DEFAULT_MAP][i];
  3757. }
  3758. }
  3759. qdf_export_symbol(dp_soc_set_txrx_ring_map);
  3760. static void dp_soc_cfg_dump(struct dp_soc *soc, uint32_t target_type)
  3761. {
  3762. dp_init_info("DP soc Dump for Target = %d", target_type);
  3763. dp_init_info("ast_override_support = %d, da_war_enabled = %d,",
  3764. soc->ast_override_support, soc->da_war_enabled);
  3765. wlan_cfg_dp_soc_ctx_dump(soc->wlan_cfg_ctx);
  3766. }
  3767. /**
  3768. * dp_soc_cfg_init() - initialize target specific configuration
  3769. * during dp_soc_init
  3770. * @soc: dp soc handle
  3771. */
  3772. static void dp_soc_cfg_init(struct dp_soc *soc)
  3773. {
  3774. uint32_t target_type;
  3775. target_type = hal_get_target_type(soc->hal_soc);
  3776. switch (target_type) {
  3777. case TARGET_TYPE_QCA6290:
  3778. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  3779. REO_DST_RING_SIZE_QCA6290);
  3780. soc->ast_override_support = 1;
  3781. soc->da_war_enabled = false;
  3782. break;
  3783. case TARGET_TYPE_QCA6390:
  3784. case TARGET_TYPE_QCA6490:
  3785. case TARGET_TYPE_QCA6750:
  3786. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  3787. REO_DST_RING_SIZE_QCA6290);
  3788. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, true);
  3789. soc->ast_override_support = 1;
  3790. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3791. soc->cdp_soc.ol_ops->get_con_mode() ==
  3792. QDF_GLOBAL_MONITOR_MODE) {
  3793. int int_ctx;
  3794. for (int_ctx = 0; int_ctx < WLAN_CFG_INT_NUM_CONTEXTS; int_ctx++) {
  3795. soc->wlan_cfg_ctx->int_rx_ring_mask[int_ctx] = 0;
  3796. soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[int_ctx] = 0;
  3797. }
  3798. }
  3799. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  3800. break;
  3801. case TARGET_TYPE_KIWI:
  3802. case TARGET_TYPE_MANGO:
  3803. case TARGET_TYPE_PEACH:
  3804. soc->ast_override_support = 1;
  3805. soc->per_tid_basize_max_tid = 8;
  3806. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3807. soc->cdp_soc.ol_ops->get_con_mode() ==
  3808. QDF_GLOBAL_MONITOR_MODE) {
  3809. int int_ctx;
  3810. for (int_ctx = 0; int_ctx < WLAN_CFG_INT_NUM_CONTEXTS;
  3811. int_ctx++) {
  3812. soc->wlan_cfg_ctx->int_rx_ring_mask[int_ctx] = 0;
  3813. if (dp_is_monitor_mode_using_poll(soc))
  3814. soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[int_ctx] = 0;
  3815. }
  3816. }
  3817. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  3818. soc->wlan_cfg_ctx->num_rxdma_dst_rings_per_pdev = 1;
  3819. break;
  3820. case TARGET_TYPE_QCA8074:
  3821. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, true);
  3822. soc->da_war_enabled = true;
  3823. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3824. break;
  3825. case TARGET_TYPE_QCA8074V2:
  3826. case TARGET_TYPE_QCA6018:
  3827. case TARGET_TYPE_QCA9574:
  3828. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3829. soc->ast_override_support = 1;
  3830. soc->per_tid_basize_max_tid = 8;
  3831. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3832. soc->da_war_enabled = false;
  3833. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3834. break;
  3835. case TARGET_TYPE_QCN9000:
  3836. soc->ast_override_support = 1;
  3837. soc->da_war_enabled = false;
  3838. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3839. soc->per_tid_basize_max_tid = 8;
  3840. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3841. soc->lmac_polled_mode = 0;
  3842. soc->wbm_release_desc_rx_sg_support = 1;
  3843. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3844. break;
  3845. case TARGET_TYPE_QCA5018:
  3846. case TARGET_TYPE_QCN6122:
  3847. case TARGET_TYPE_QCN9160:
  3848. soc->ast_override_support = 1;
  3849. soc->da_war_enabled = false;
  3850. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3851. soc->per_tid_basize_max_tid = 8;
  3852. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_MAPS_11AX;
  3853. soc->disable_mac1_intr = 1;
  3854. soc->disable_mac2_intr = 1;
  3855. soc->wbm_release_desc_rx_sg_support = 1;
  3856. break;
  3857. case TARGET_TYPE_QCN9224:
  3858. soc->ast_override_support = 1;
  3859. soc->da_war_enabled = false;
  3860. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3861. soc->per_tid_basize_max_tid = 8;
  3862. soc->wbm_release_desc_rx_sg_support = 1;
  3863. soc->rxdma2sw_rings_not_supported = 1;
  3864. soc->wbm_sg_last_msdu_war = 1;
  3865. soc->ast_offload_support = AST_OFFLOAD_ENABLE_STATUS;
  3866. soc->mec_fw_offload = FW_MEC_FW_OFFLOAD_ENABLED;
  3867. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3868. wlan_cfg_set_txmon_hw_support(soc->wlan_cfg_ctx, true);
  3869. soc->host_ast_db_enable = cfg_get(soc->ctrl_psoc,
  3870. CFG_DP_HOST_AST_DB_ENABLE);
  3871. soc->features.wds_ext_ast_override_enable = true;
  3872. break;
  3873. case TARGET_TYPE_QCA5332:
  3874. soc->ast_override_support = 1;
  3875. soc->da_war_enabled = false;
  3876. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3877. soc->per_tid_basize_max_tid = 8;
  3878. soc->wbm_release_desc_rx_sg_support = 1;
  3879. soc->rxdma2sw_rings_not_supported = 1;
  3880. soc->wbm_sg_last_msdu_war = 1;
  3881. soc->ast_offload_support = AST_OFFLOAD_ENABLE_STATUS;
  3882. soc->mec_fw_offload = FW_MEC_FW_OFFLOAD_ENABLED;
  3883. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS_5332;
  3884. wlan_cfg_set_txmon_hw_support(soc->wlan_cfg_ctx, true);
  3885. soc->host_ast_db_enable = cfg_get(soc->ctrl_psoc,
  3886. CFG_DP_HOST_AST_DB_ENABLE);
  3887. soc->features.wds_ext_ast_override_enable = true;
  3888. break;
  3889. default:
  3890. qdf_print("%s: Unknown tgt type %d\n", __func__, target_type);
  3891. qdf_assert_always(0);
  3892. break;
  3893. }
  3894. dp_soc_cfg_dump(soc, target_type);
  3895. }
  3896. /**
  3897. * dp_soc_init() - Initialize txrx SOC
  3898. * @soc: Opaque DP SOC handle
  3899. * @htc_handle: Opaque HTC handle
  3900. * @hif_handle: Opaque HIF handle
  3901. *
  3902. * Return: DP SOC handle on success, NULL on failure
  3903. */
  3904. void *dp_soc_init(struct dp_soc *soc, HTC_HANDLE htc_handle,
  3905. struct hif_opaque_softc *hif_handle)
  3906. {
  3907. struct htt_soc *htt_soc = (struct htt_soc *)soc->htt_handle;
  3908. bool is_monitor_mode = false;
  3909. uint8_t i;
  3910. int num_dp_msi;
  3911. wlan_minidump_log(soc, sizeof(*soc), soc->ctrl_psoc,
  3912. WLAN_MD_DP_SOC, "dp_soc");
  3913. soc->hif_handle = hif_handle;
  3914. soc->hal_soc = hif_get_hal_handle(soc->hif_handle);
  3915. if (!soc->hal_soc)
  3916. goto fail0;
  3917. if (!QDF_IS_STATUS_SUCCESS(soc->arch_ops.txrx_soc_init(soc))) {
  3918. dp_err("unable to do target specific init");
  3919. goto fail0;
  3920. }
  3921. htt_soc = htt_soc_attach(soc, htc_handle);
  3922. if (!htt_soc)
  3923. goto fail1;
  3924. soc->htt_handle = htt_soc;
  3925. if (htt_soc_htc_prealloc(htt_soc) != QDF_STATUS_SUCCESS)
  3926. goto fail2;
  3927. htt_set_htc_handle(htt_soc, htc_handle);
  3928. dp_soc_cfg_init(soc);
  3929. dp_monitor_soc_cfg_init(soc);
  3930. /* Reset/Initialize wbm sg list and flags */
  3931. dp_rx_wbm_sg_list_reset(soc);
  3932. /* Note: Any SRNG ring initialization should happen only after
  3933. * Interrupt mode is set and followed by filling up the
  3934. * interrupt mask. IT SHOULD ALWAYS BE IN THIS ORDER.
  3935. */
  3936. dp_soc_set_interrupt_mode(soc);
  3937. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3938. soc->cdp_soc.ol_ops->get_con_mode() ==
  3939. QDF_GLOBAL_MONITOR_MODE) {
  3940. is_monitor_mode = true;
  3941. soc->curr_rx_pkt_tlv_size = soc->rx_mon_pkt_tlv_size;
  3942. } else {
  3943. soc->curr_rx_pkt_tlv_size = soc->rx_pkt_tlv_size;
  3944. }
  3945. num_dp_msi = dp_get_num_msi_available(soc, soc->intr_mode);
  3946. if (num_dp_msi < 0) {
  3947. dp_init_err("%pK: dp_interrupt assignment failed", soc);
  3948. goto fail3;
  3949. }
  3950. wlan_cfg_fill_interrupt_mask(soc->wlan_cfg_ctx, num_dp_msi,
  3951. soc->intr_mode, is_monitor_mode);
  3952. /* initialize WBM_IDLE_LINK ring */
  3953. if (dp_hw_link_desc_ring_init(soc)) {
  3954. dp_init_err("%pK: dp_hw_link_desc_ring_init failed", soc);
  3955. goto fail3;
  3956. }
  3957. dp_link_desc_ring_replenish(soc, WLAN_INVALID_PDEV_ID);
  3958. if (dp_soc_srng_init(soc)) {
  3959. dp_init_err("%pK: dp_soc_srng_init failed", soc);
  3960. goto fail4;
  3961. }
  3962. if (htt_soc_initialize(soc->htt_handle, soc->ctrl_psoc,
  3963. htt_get_htc_handle(htt_soc),
  3964. soc->hal_soc, soc->osdev) == NULL)
  3965. goto fail5;
  3966. /* Initialize descriptors in TCL Rings */
  3967. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3968. hal_tx_init_data_ring(soc->hal_soc,
  3969. soc->tcl_data_ring[i].hal_srng);
  3970. }
  3971. if (dp_soc_tx_desc_sw_pools_init(soc)) {
  3972. dp_init_err("%pK: dp_tx_soc_attach failed", soc);
  3973. goto fail6;
  3974. }
  3975. if (soc->arch_ops.txrx_soc_ppeds_start) {
  3976. if (soc->arch_ops.txrx_soc_ppeds_start(soc)) {
  3977. dp_init_err("%pK: ppeds start failed", soc);
  3978. goto fail7;
  3979. }
  3980. }
  3981. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx,
  3982. cfg_get(soc->ctrl_psoc, CFG_DP_RX_HASH));
  3983. soc->cce_disable = false;
  3984. soc->max_ast_ageout_count = MAX_AST_AGEOUT_COUNT;
  3985. soc->sta_mode_search_policy = DP_TX_ADDR_SEARCH_ADDR_POLICY;
  3986. qdf_mem_zero(&soc->vdev_id_map, sizeof(soc->vdev_id_map));
  3987. qdf_spinlock_create(&soc->vdev_map_lock);
  3988. qdf_atomic_init(&soc->num_tx_outstanding);
  3989. qdf_atomic_init(&soc->num_tx_exception);
  3990. soc->num_tx_allowed =
  3991. wlan_cfg_get_dp_soc_tx_device_limit(soc->wlan_cfg_ctx);
  3992. soc->num_tx_spl_allowed =
  3993. wlan_cfg_get_dp_soc_tx_spl_device_limit(soc->wlan_cfg_ctx);
  3994. soc->num_reg_tx_allowed = soc->num_tx_allowed - soc->num_tx_spl_allowed;
  3995. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  3996. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  3997. CDP_CFG_MAX_PEER_ID);
  3998. if (ret != -EINVAL)
  3999. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4000. ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  4001. CDP_CFG_CCE_DISABLE);
  4002. if (ret == 1)
  4003. soc->cce_disable = true;
  4004. }
  4005. /*
  4006. * Skip registering hw ring interrupts for WMAC2 on IPQ6018
  4007. * and IPQ5018 WMAC2 is not there in these platforms.
  4008. */
  4009. if (hal_get_target_type(soc->hal_soc) == TARGET_TYPE_QCA6018 ||
  4010. soc->disable_mac2_intr)
  4011. dp_soc_disable_unused_mac_intr_mask(soc, 0x2);
  4012. /*
  4013. * Skip registering hw ring interrupts for WMAC1 on IPQ5018
  4014. * WMAC1 is not there in this platform.
  4015. */
  4016. if (soc->disable_mac1_intr)
  4017. dp_soc_disable_unused_mac_intr_mask(soc, 0x1);
  4018. /* setup the global rx defrag waitlist */
  4019. TAILQ_INIT(&soc->rx.defrag.waitlist);
  4020. soc->rx.defrag.timeout_ms =
  4021. wlan_cfg_get_rx_defrag_min_timeout(soc->wlan_cfg_ctx);
  4022. soc->rx.defrag.next_flush_ms = 0;
  4023. soc->rx.flags.defrag_timeout_check =
  4024. wlan_cfg_get_defrag_timeout_check(soc->wlan_cfg_ctx);
  4025. qdf_spinlock_create(&soc->rx.defrag.defrag_lock);
  4026. dp_monitor_soc_init(soc);
  4027. qdf_atomic_set(&soc->cmn_init_done, 1);
  4028. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  4029. qdf_spinlock_create(&soc->ast_lock);
  4030. dp_peer_mec_spinlock_create(soc);
  4031. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4032. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4033. INIT_RX_HW_STATS_LOCK(soc);
  4034. qdf_nbuf_queue_init(&soc->invalid_buf_queue);
  4035. /* fill the tx/rx cpu ring map*/
  4036. dp_soc_set_txrx_ring_map(soc);
  4037. TAILQ_INIT(&soc->inactive_peer_list);
  4038. qdf_spinlock_create(&soc->inactive_peer_list_lock);
  4039. TAILQ_INIT(&soc->inactive_vdev_list);
  4040. qdf_spinlock_create(&soc->inactive_vdev_list_lock);
  4041. qdf_spinlock_create(&soc->htt_stats.lock);
  4042. /* initialize work queue for stats processing */
  4043. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4044. dp_reo_desc_deferred_freelist_create(soc);
  4045. dp_info("Mem stats: DMA = %u HEAP = %u SKB = %u",
  4046. qdf_dma_mem_stats_read(),
  4047. qdf_heap_mem_stats_read(),
  4048. qdf_skb_total_mem_stats_read());
  4049. soc->vdev_stats_id_map = 0;
  4050. return soc;
  4051. fail7:
  4052. dp_soc_tx_desc_sw_pools_deinit(soc);
  4053. fail6:
  4054. htt_soc_htc_dealloc(soc->htt_handle);
  4055. fail5:
  4056. dp_soc_srng_deinit(soc);
  4057. fail4:
  4058. dp_hw_link_desc_ring_deinit(soc);
  4059. fail3:
  4060. htt_htc_pkt_pool_free(htt_soc);
  4061. fail2:
  4062. htt_soc_detach(htt_soc);
  4063. fail1:
  4064. soc->arch_ops.txrx_soc_deinit(soc);
  4065. fail0:
  4066. return NULL;
  4067. }
  4068. #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG
  4069. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_init(struct dp_soc *soc)
  4070. {
  4071. QDF_STATUS status;
  4072. if (soc->init_tcl_cmd_cred_ring) {
  4073. status = dp_srng_init(soc, &soc->tcl_cmd_credit_ring,
  4074. TCL_CMD_CREDIT, 0, 0);
  4075. if (QDF_IS_STATUS_ERROR(status))
  4076. return status;
  4077. wlan_minidump_log(soc->tcl_cmd_credit_ring.base_vaddr_unaligned,
  4078. soc->tcl_cmd_credit_ring.alloc_size,
  4079. soc->ctrl_psoc,
  4080. WLAN_MD_DP_SRNG_TCL_CMD,
  4081. "wbm_desc_rel_ring");
  4082. }
  4083. return QDF_STATUS_SUCCESS;
  4084. }
  4085. static inline void dp_soc_tcl_cmd_cred_srng_deinit(struct dp_soc *soc)
  4086. {
  4087. if (soc->init_tcl_cmd_cred_ring) {
  4088. wlan_minidump_remove(soc->tcl_cmd_credit_ring.base_vaddr_unaligned,
  4089. soc->tcl_cmd_credit_ring.alloc_size,
  4090. soc->ctrl_psoc, WLAN_MD_DP_SRNG_TCL_CMD,
  4091. "wbm_desc_rel_ring");
  4092. dp_srng_deinit(soc, &soc->tcl_cmd_credit_ring,
  4093. TCL_CMD_CREDIT, 0);
  4094. }
  4095. }
  4096. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_alloc(struct dp_soc *soc)
  4097. {
  4098. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  4099. uint32_t entries;
  4100. QDF_STATUS status;
  4101. entries = wlan_cfg_get_dp_soc_tcl_cmd_credit_ring_size(soc_cfg_ctx);
  4102. if (soc->init_tcl_cmd_cred_ring) {
  4103. status = dp_srng_alloc(soc, &soc->tcl_cmd_credit_ring,
  4104. TCL_CMD_CREDIT, entries, 0);
  4105. if (QDF_IS_STATUS_ERROR(status))
  4106. return status;
  4107. }
  4108. return QDF_STATUS_SUCCESS;
  4109. }
  4110. static inline void dp_soc_tcl_cmd_cred_srng_free(struct dp_soc *soc)
  4111. {
  4112. if (soc->init_tcl_cmd_cred_ring)
  4113. dp_srng_free(soc, &soc->tcl_cmd_credit_ring);
  4114. }
  4115. inline void dp_tx_init_cmd_credit_ring(struct dp_soc *soc)
  4116. {
  4117. if (soc->init_tcl_cmd_cred_ring)
  4118. hal_tx_init_cmd_credit_ring(soc->hal_soc,
  4119. soc->tcl_cmd_credit_ring.hal_srng);
  4120. }
  4121. #else
  4122. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_init(struct dp_soc *soc)
  4123. {
  4124. return QDF_STATUS_SUCCESS;
  4125. }
  4126. static inline void dp_soc_tcl_cmd_cred_srng_deinit(struct dp_soc *soc)
  4127. {
  4128. }
  4129. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_alloc(struct dp_soc *soc)
  4130. {
  4131. return QDF_STATUS_SUCCESS;
  4132. }
  4133. static inline void dp_soc_tcl_cmd_cred_srng_free(struct dp_soc *soc)
  4134. {
  4135. }
  4136. inline void dp_tx_init_cmd_credit_ring(struct dp_soc *soc)
  4137. {
  4138. }
  4139. #endif
  4140. #ifndef WLAN_DP_DISABLE_TCL_STATUS_SRNG
  4141. static inline QDF_STATUS dp_soc_tcl_status_srng_init(struct dp_soc *soc)
  4142. {
  4143. QDF_STATUS status;
  4144. status = dp_srng_init(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0);
  4145. if (QDF_IS_STATUS_ERROR(status))
  4146. return status;
  4147. wlan_minidump_log(soc->tcl_status_ring.base_vaddr_unaligned,
  4148. soc->tcl_status_ring.alloc_size,
  4149. soc->ctrl_psoc,
  4150. WLAN_MD_DP_SRNG_TCL_STATUS,
  4151. "wbm_desc_rel_ring");
  4152. return QDF_STATUS_SUCCESS;
  4153. }
  4154. static inline void dp_soc_tcl_status_srng_deinit(struct dp_soc *soc)
  4155. {
  4156. wlan_minidump_remove(soc->tcl_status_ring.base_vaddr_unaligned,
  4157. soc->tcl_status_ring.alloc_size,
  4158. soc->ctrl_psoc, WLAN_MD_DP_SRNG_TCL_STATUS,
  4159. "wbm_desc_rel_ring");
  4160. dp_srng_deinit(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  4161. }
  4162. static inline QDF_STATUS dp_soc_tcl_status_srng_alloc(struct dp_soc *soc)
  4163. {
  4164. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  4165. uint32_t entries;
  4166. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4167. entries = wlan_cfg_get_dp_soc_tcl_status_ring_size(soc_cfg_ctx);
  4168. status = dp_srng_alloc(soc, &soc->tcl_status_ring,
  4169. TCL_STATUS, entries, 0);
  4170. return status;
  4171. }
  4172. static inline void dp_soc_tcl_status_srng_free(struct dp_soc *soc)
  4173. {
  4174. dp_srng_free(soc, &soc->tcl_status_ring);
  4175. }
  4176. #else
  4177. static inline QDF_STATUS dp_soc_tcl_status_srng_init(struct dp_soc *soc)
  4178. {
  4179. return QDF_STATUS_SUCCESS;
  4180. }
  4181. static inline void dp_soc_tcl_status_srng_deinit(struct dp_soc *soc)
  4182. {
  4183. }
  4184. static inline QDF_STATUS dp_soc_tcl_status_srng_alloc(struct dp_soc *soc)
  4185. {
  4186. return QDF_STATUS_SUCCESS;
  4187. }
  4188. static inline void dp_soc_tcl_status_srng_free(struct dp_soc *soc)
  4189. {
  4190. }
  4191. #endif
  4192. /**
  4193. * dp_soc_srng_deinit() - de-initialize soc srng rings
  4194. * @soc: Datapath soc handle
  4195. *
  4196. */
  4197. void dp_soc_srng_deinit(struct dp_soc *soc)
  4198. {
  4199. uint32_t i;
  4200. if (soc->arch_ops.txrx_soc_srng_deinit)
  4201. soc->arch_ops.txrx_soc_srng_deinit(soc);
  4202. /* Free the ring memories */
  4203. /* Common rings */
  4204. wlan_minidump_remove(soc->wbm_desc_rel_ring.base_vaddr_unaligned,
  4205. soc->wbm_desc_rel_ring.alloc_size,
  4206. soc->ctrl_psoc, WLAN_MD_DP_SRNG_WBM_DESC_REL,
  4207. "wbm_desc_rel_ring");
  4208. dp_srng_deinit(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  4209. /* Tx data rings */
  4210. for (i = 0; i < soc->num_tcl_data_rings; i++)
  4211. dp_deinit_tx_pair_by_index(soc, i);
  4212. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4213. dp_deinit_tx_pair_by_index(soc, IPA_TCL_DATA_RING_IDX);
  4214. dp_ipa_deinit_alt_tx_ring(soc);
  4215. }
  4216. /* TCL command and status rings */
  4217. dp_soc_tcl_cmd_cred_srng_deinit(soc);
  4218. dp_soc_tcl_status_srng_deinit(soc);
  4219. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4220. /* TODO: Get number of rings and ring sizes
  4221. * from wlan_cfg
  4222. */
  4223. wlan_minidump_remove(soc->reo_dest_ring[i].base_vaddr_unaligned,
  4224. soc->reo_dest_ring[i].alloc_size,
  4225. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_DEST,
  4226. "reo_dest_ring");
  4227. dp_srng_deinit(soc, &soc->reo_dest_ring[i], REO_DST, i);
  4228. }
  4229. /* REO reinjection ring */
  4230. wlan_minidump_remove(soc->reo_reinject_ring.base_vaddr_unaligned,
  4231. soc->reo_reinject_ring.alloc_size,
  4232. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_REINJECT,
  4233. "reo_reinject_ring");
  4234. dp_srng_deinit(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  4235. /* Rx release ring */
  4236. wlan_minidump_remove(soc->rx_rel_ring.base_vaddr_unaligned,
  4237. soc->rx_rel_ring.alloc_size,
  4238. soc->ctrl_psoc, WLAN_MD_DP_SRNG_RX_REL,
  4239. "reo_release_ring");
  4240. dp_srng_deinit(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  4241. /* Rx exception ring */
  4242. /* TODO: Better to store ring_type and ring_num in
  4243. * dp_srng during setup
  4244. */
  4245. wlan_minidump_remove(soc->reo_exception_ring.base_vaddr_unaligned,
  4246. soc->reo_exception_ring.alloc_size,
  4247. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_EXCEPTION,
  4248. "reo_exception_ring");
  4249. dp_srng_deinit(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  4250. /* REO command and status rings */
  4251. wlan_minidump_remove(soc->reo_cmd_ring.base_vaddr_unaligned,
  4252. soc->reo_cmd_ring.alloc_size,
  4253. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_CMD,
  4254. "reo_cmd_ring");
  4255. dp_srng_deinit(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  4256. wlan_minidump_remove(soc->reo_status_ring.base_vaddr_unaligned,
  4257. soc->reo_status_ring.alloc_size,
  4258. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_STATUS,
  4259. "reo_status_ring");
  4260. dp_srng_deinit(soc, &soc->reo_status_ring, REO_STATUS, 0);
  4261. }
  4262. /**
  4263. * dp_soc_srng_init() - Initialize soc level srng rings
  4264. * @soc: Datapath soc handle
  4265. *
  4266. * Return: QDF_STATUS_SUCCESS on success
  4267. * QDF_STATUS_E_FAILURE on failure
  4268. */
  4269. QDF_STATUS dp_soc_srng_init(struct dp_soc *soc)
  4270. {
  4271. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  4272. uint8_t i;
  4273. uint8_t wbm2_sw_rx_rel_ring_id;
  4274. soc_cfg_ctx = soc->wlan_cfg_ctx;
  4275. dp_enable_verbose_debug(soc);
  4276. /* WBM descriptor release ring */
  4277. if (dp_srng_init(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0)) {
  4278. dp_init_err("%pK: dp_srng_init failed for wbm_desc_rel_ring", soc);
  4279. goto fail1;
  4280. }
  4281. wlan_minidump_log(soc->wbm_desc_rel_ring.base_vaddr_unaligned,
  4282. soc->wbm_desc_rel_ring.alloc_size,
  4283. soc->ctrl_psoc,
  4284. WLAN_MD_DP_SRNG_WBM_DESC_REL,
  4285. "wbm_desc_rel_ring");
  4286. /* TCL command and status rings */
  4287. if (dp_soc_tcl_cmd_cred_srng_init(soc)) {
  4288. dp_init_err("%pK: dp_srng_init failed for tcl_cmd_ring", soc);
  4289. goto fail1;
  4290. }
  4291. if (dp_soc_tcl_status_srng_init(soc)) {
  4292. dp_init_err("%pK: dp_srng_init failed for tcl_status_ring", soc);
  4293. goto fail1;
  4294. }
  4295. /* REO reinjection ring */
  4296. if (dp_srng_init(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0)) {
  4297. dp_init_err("%pK: dp_srng_init failed for reo_reinject_ring", soc);
  4298. goto fail1;
  4299. }
  4300. wlan_minidump_log(soc->reo_reinject_ring.base_vaddr_unaligned,
  4301. soc->reo_reinject_ring.alloc_size,
  4302. soc->ctrl_psoc,
  4303. WLAN_MD_DP_SRNG_REO_REINJECT,
  4304. "reo_reinject_ring");
  4305. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc_cfg_ctx);
  4306. /* Rx release ring */
  4307. if (dp_srng_init(soc, &soc->rx_rel_ring, WBM2SW_RELEASE,
  4308. wbm2_sw_rx_rel_ring_id, 0)) {
  4309. dp_init_err("%pK: dp_srng_init failed for rx_rel_ring", soc);
  4310. goto fail1;
  4311. }
  4312. wlan_minidump_log(soc->rx_rel_ring.base_vaddr_unaligned,
  4313. soc->rx_rel_ring.alloc_size,
  4314. soc->ctrl_psoc,
  4315. WLAN_MD_DP_SRNG_RX_REL,
  4316. "reo_release_ring");
  4317. /* Rx exception ring */
  4318. if (dp_srng_init(soc, &soc->reo_exception_ring,
  4319. REO_EXCEPTION, 0, MAX_REO_DEST_RINGS)) {
  4320. dp_init_err("%pK: dp_srng_init failed - reo_exception", soc);
  4321. goto fail1;
  4322. }
  4323. wlan_minidump_log(soc->reo_exception_ring.base_vaddr_unaligned,
  4324. soc->reo_exception_ring.alloc_size,
  4325. soc->ctrl_psoc,
  4326. WLAN_MD_DP_SRNG_REO_EXCEPTION,
  4327. "reo_exception_ring");
  4328. /* REO command and status rings */
  4329. if (dp_srng_init(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0)) {
  4330. dp_init_err("%pK: dp_srng_init failed for reo_cmd_ring", soc);
  4331. goto fail1;
  4332. }
  4333. wlan_minidump_log(soc->reo_cmd_ring.base_vaddr_unaligned,
  4334. soc->reo_cmd_ring.alloc_size,
  4335. soc->ctrl_psoc,
  4336. WLAN_MD_DP_SRNG_REO_CMD,
  4337. "reo_cmd_ring");
  4338. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  4339. TAILQ_INIT(&soc->rx.reo_cmd_list);
  4340. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  4341. if (dp_srng_init(soc, &soc->reo_status_ring, REO_STATUS, 0, 0)) {
  4342. dp_init_err("%pK: dp_srng_init failed for reo_status_ring", soc);
  4343. goto fail1;
  4344. }
  4345. wlan_minidump_log(soc->reo_status_ring.base_vaddr_unaligned,
  4346. soc->reo_status_ring.alloc_size,
  4347. soc->ctrl_psoc,
  4348. WLAN_MD_DP_SRNG_REO_STATUS,
  4349. "reo_status_ring");
  4350. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  4351. if (dp_init_tx_ring_pair_by_index(soc, i))
  4352. goto fail1;
  4353. }
  4354. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4355. if (dp_init_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX))
  4356. goto fail1;
  4357. if (dp_ipa_init_alt_tx_ring(soc))
  4358. goto fail1;
  4359. }
  4360. dp_create_ext_stats_event(soc);
  4361. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4362. /* Initialize REO destination ring */
  4363. if (dp_srng_init(soc, &soc->reo_dest_ring[i], REO_DST, i, 0)) {
  4364. dp_init_err("%pK: dp_srng_init failed for reo_dest_ringn", soc);
  4365. goto fail1;
  4366. }
  4367. wlan_minidump_log(soc->reo_dest_ring[i].base_vaddr_unaligned,
  4368. soc->reo_dest_ring[i].alloc_size,
  4369. soc->ctrl_psoc,
  4370. WLAN_MD_DP_SRNG_REO_DEST,
  4371. "reo_dest_ring");
  4372. }
  4373. if (soc->arch_ops.txrx_soc_srng_init) {
  4374. if (soc->arch_ops.txrx_soc_srng_init(soc)) {
  4375. dp_init_err("%pK: dp_srng_init failed for arch rings",
  4376. soc);
  4377. goto fail1;
  4378. }
  4379. }
  4380. return QDF_STATUS_SUCCESS;
  4381. fail1:
  4382. /*
  4383. * Cleanup will be done as part of soc_detach, which will
  4384. * be called on pdev attach failure
  4385. */
  4386. dp_soc_srng_deinit(soc);
  4387. return QDF_STATUS_E_FAILURE;
  4388. }
  4389. /**
  4390. * dp_soc_srng_free() - free soc level srng rings
  4391. * @soc: Datapath soc handle
  4392. *
  4393. */
  4394. void dp_soc_srng_free(struct dp_soc *soc)
  4395. {
  4396. uint32_t i;
  4397. if (soc->arch_ops.txrx_soc_srng_free)
  4398. soc->arch_ops.txrx_soc_srng_free(soc);
  4399. dp_srng_free(soc, &soc->wbm_desc_rel_ring);
  4400. for (i = 0; i < soc->num_tcl_data_rings; i++)
  4401. dp_free_tx_ring_pair_by_index(soc, i);
  4402. /* Free IPA rings for TCL_TX and TCL_COMPL ring */
  4403. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4404. dp_free_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX);
  4405. dp_ipa_free_alt_tx_ring(soc);
  4406. }
  4407. dp_soc_tcl_cmd_cred_srng_free(soc);
  4408. dp_soc_tcl_status_srng_free(soc);
  4409. for (i = 0; i < soc->num_reo_dest_rings; i++)
  4410. dp_srng_free(soc, &soc->reo_dest_ring[i]);
  4411. dp_srng_free(soc, &soc->reo_reinject_ring);
  4412. dp_srng_free(soc, &soc->rx_rel_ring);
  4413. dp_srng_free(soc, &soc->reo_exception_ring);
  4414. dp_srng_free(soc, &soc->reo_cmd_ring);
  4415. dp_srng_free(soc, &soc->reo_status_ring);
  4416. }
  4417. /**
  4418. * dp_soc_srng_alloc() - Allocate memory for soc level srng rings
  4419. * @soc: Datapath soc handle
  4420. *
  4421. * Return: QDF_STATUS_SUCCESS on success
  4422. * QDF_STATUS_E_NOMEM on failure
  4423. */
  4424. QDF_STATUS dp_soc_srng_alloc(struct dp_soc *soc)
  4425. {
  4426. uint32_t entries;
  4427. uint32_t i;
  4428. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  4429. uint32_t cached = WLAN_CFG_DST_RING_CACHED_DESC;
  4430. uint32_t reo_dst_ring_size;
  4431. soc_cfg_ctx = soc->wlan_cfg_ctx;
  4432. /* sw2wbm link descriptor release ring */
  4433. entries = wlan_cfg_get_dp_soc_wbm_release_ring_size(soc_cfg_ctx);
  4434. if (dp_srng_alloc(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE,
  4435. entries, 0)) {
  4436. dp_init_err("%pK: dp_srng_alloc failed for wbm_desc_rel_ring", soc);
  4437. goto fail1;
  4438. }
  4439. /* TCL command and status rings */
  4440. if (dp_soc_tcl_cmd_cred_srng_alloc(soc)) {
  4441. dp_init_err("%pK: dp_srng_alloc failed for tcl_cmd_ring", soc);
  4442. goto fail1;
  4443. }
  4444. if (dp_soc_tcl_status_srng_alloc(soc)) {
  4445. dp_init_err("%pK: dp_srng_alloc failed for tcl_status_ring", soc);
  4446. goto fail1;
  4447. }
  4448. /* REO reinjection ring */
  4449. entries = wlan_cfg_get_dp_soc_reo_reinject_ring_size(soc_cfg_ctx);
  4450. if (dp_srng_alloc(soc, &soc->reo_reinject_ring, REO_REINJECT,
  4451. entries, 0)) {
  4452. dp_init_err("%pK: dp_srng_alloc failed for reo_reinject_ring", soc);
  4453. goto fail1;
  4454. }
  4455. /* Rx release ring */
  4456. entries = wlan_cfg_get_dp_soc_rx_release_ring_size(soc_cfg_ctx);
  4457. if (dp_srng_alloc(soc, &soc->rx_rel_ring, WBM2SW_RELEASE,
  4458. entries, 0)) {
  4459. dp_init_err("%pK: dp_srng_alloc failed for rx_rel_ring", soc);
  4460. goto fail1;
  4461. }
  4462. /* Rx exception ring */
  4463. entries = wlan_cfg_get_dp_soc_reo_exception_ring_size(soc_cfg_ctx);
  4464. if (dp_srng_alloc(soc, &soc->reo_exception_ring, REO_EXCEPTION,
  4465. entries, 0)) {
  4466. dp_init_err("%pK: dp_srng_alloc failed - reo_exception", soc);
  4467. goto fail1;
  4468. }
  4469. /* REO command and status rings */
  4470. entries = wlan_cfg_get_dp_soc_reo_cmd_ring_size(soc_cfg_ctx);
  4471. if (dp_srng_alloc(soc, &soc->reo_cmd_ring, REO_CMD, entries, 0)) {
  4472. dp_init_err("%pK: dp_srng_alloc failed for reo_cmd_ring", soc);
  4473. goto fail1;
  4474. }
  4475. entries = wlan_cfg_get_dp_soc_reo_status_ring_size(soc_cfg_ctx);
  4476. if (dp_srng_alloc(soc, &soc->reo_status_ring, REO_STATUS,
  4477. entries, 0)) {
  4478. dp_init_err("%pK: dp_srng_alloc failed for reo_status_ring", soc);
  4479. goto fail1;
  4480. }
  4481. reo_dst_ring_size = wlan_cfg_get_reo_dst_ring_size(soc_cfg_ctx);
  4482. /* Disable cached desc if NSS offload is enabled */
  4483. if (wlan_cfg_get_dp_soc_nss_cfg(soc_cfg_ctx))
  4484. cached = 0;
  4485. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  4486. if (dp_alloc_tx_ring_pair_by_index(soc, i))
  4487. goto fail1;
  4488. }
  4489. /* IPA rings for TCL_TX and TX_COMP will be allocated here */
  4490. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4491. if (dp_alloc_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX))
  4492. goto fail1;
  4493. if (dp_ipa_alloc_alt_tx_ring(soc))
  4494. goto fail1;
  4495. }
  4496. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4497. /* Setup REO destination ring */
  4498. if (dp_srng_alloc(soc, &soc->reo_dest_ring[i], REO_DST,
  4499. reo_dst_ring_size, cached)) {
  4500. dp_init_err("%pK: dp_srng_alloc failed for reo_dest_ring", soc);
  4501. goto fail1;
  4502. }
  4503. }
  4504. if (soc->arch_ops.txrx_soc_srng_alloc) {
  4505. if (soc->arch_ops.txrx_soc_srng_alloc(soc)) {
  4506. dp_init_err("%pK: dp_srng_alloc failed for arch rings",
  4507. soc);
  4508. goto fail1;
  4509. }
  4510. }
  4511. return QDF_STATUS_SUCCESS;
  4512. fail1:
  4513. dp_soc_srng_free(soc);
  4514. return QDF_STATUS_E_NOMEM;
  4515. }
  4516. /**
  4517. * dp_soc_cfg_attach() - set target specific configuration in
  4518. * dp soc cfg.
  4519. * @soc: dp soc handle
  4520. */
  4521. void dp_soc_cfg_attach(struct dp_soc *soc)
  4522. {
  4523. int target_type;
  4524. int nss_cfg = 0;
  4525. target_type = hal_get_target_type(soc->hal_soc);
  4526. switch (target_type) {
  4527. case TARGET_TYPE_QCA6290:
  4528. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  4529. REO_DST_RING_SIZE_QCA6290);
  4530. break;
  4531. case TARGET_TYPE_QCA6390:
  4532. case TARGET_TYPE_QCA6490:
  4533. case TARGET_TYPE_QCA6750:
  4534. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  4535. REO_DST_RING_SIZE_QCA6290);
  4536. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4537. break;
  4538. case TARGET_TYPE_KIWI:
  4539. case TARGET_TYPE_MANGO:
  4540. case TARGET_TYPE_PEACH:
  4541. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4542. break;
  4543. case TARGET_TYPE_QCA8074:
  4544. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4545. break;
  4546. case TARGET_TYPE_QCA8074V2:
  4547. case TARGET_TYPE_QCA6018:
  4548. case TARGET_TYPE_QCA9574:
  4549. case TARGET_TYPE_QCN6122:
  4550. case TARGET_TYPE_QCA5018:
  4551. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4552. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4553. break;
  4554. case TARGET_TYPE_QCN9160:
  4555. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4556. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4557. break;
  4558. case TARGET_TYPE_QCN9000:
  4559. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4560. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4561. break;
  4562. case TARGET_TYPE_QCN9224:
  4563. case TARGET_TYPE_QCA5332:
  4564. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4565. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4566. break;
  4567. default:
  4568. qdf_print("%s: Unknown tgt type %d\n", __func__, target_type);
  4569. qdf_assert_always(0);
  4570. break;
  4571. }
  4572. if (soc->cdp_soc.ol_ops->get_soc_nss_cfg)
  4573. nss_cfg = soc->cdp_soc.ol_ops->get_soc_nss_cfg(soc->ctrl_psoc);
  4574. wlan_cfg_set_dp_soc_nss_cfg(soc->wlan_cfg_ctx, nss_cfg);
  4575. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  4576. wlan_cfg_set_num_tx_desc_pool(soc->wlan_cfg_ctx, 0);
  4577. wlan_cfg_set_num_tx_ext_desc_pool(soc->wlan_cfg_ctx, 0);
  4578. wlan_cfg_set_num_tx_desc(soc->wlan_cfg_ctx, 0);
  4579. wlan_cfg_set_num_tx_ext_desc(soc->wlan_cfg_ctx, 0);
  4580. soc->init_tcl_cmd_cred_ring = false;
  4581. soc->num_tcl_data_rings =
  4582. wlan_cfg_num_nss_tcl_data_rings(soc->wlan_cfg_ctx);
  4583. soc->num_reo_dest_rings =
  4584. wlan_cfg_num_nss_reo_dest_rings(soc->wlan_cfg_ctx);
  4585. } else {
  4586. soc->init_tcl_cmd_cred_ring = true;
  4587. soc->num_tx_comp_rings =
  4588. wlan_cfg_num_tx_comp_rings(soc->wlan_cfg_ctx);
  4589. soc->num_tcl_data_rings =
  4590. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  4591. soc->num_reo_dest_rings =
  4592. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  4593. }
  4594. soc->arch_ops.soc_cfg_attach(soc);
  4595. }
  4596. void dp_pdev_set_default_reo(struct dp_pdev *pdev)
  4597. {
  4598. struct dp_soc *soc = pdev->soc;
  4599. switch (pdev->pdev_id) {
  4600. case 0:
  4601. pdev->reo_dest =
  4602. wlan_cfg_radio0_default_reo_get(soc->wlan_cfg_ctx);
  4603. break;
  4604. case 1:
  4605. pdev->reo_dest =
  4606. wlan_cfg_radio1_default_reo_get(soc->wlan_cfg_ctx);
  4607. break;
  4608. case 2:
  4609. pdev->reo_dest =
  4610. wlan_cfg_radio2_default_reo_get(soc->wlan_cfg_ctx);
  4611. break;
  4612. default:
  4613. dp_init_err("%pK: Invalid pdev_id %d for reo selection",
  4614. soc, pdev->pdev_id);
  4615. break;
  4616. }
  4617. }