qcs405.c 233 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/i2c.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/input.h>
  22. #include <linux/of_device.h>
  23. #include <linux/pm_qos.h>
  24. #include <sound/core.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/info.h>
  30. #include <dsp/audio_notifier.h>
  31. #include <dsp/q6afe-v2.h>
  32. #include <dsp/q6core.h>
  33. #include <dsp/msm_mdf.h>
  34. #include "device_event.h"
  35. #include "msm-pcm-routing-v2.h"
  36. #include "codecs/msm-cdc-pinctrl.h"
  37. #include "codecs/wcd9335.h"
  38. #include "codecs/wsa881x.h"
  39. #include "codecs/csra66x0/csra66x0.h"
  40. #include <dt-bindings/sound/audio-codec-port-types.h>
  41. #include "codecs/bolero/bolero-cdc.h"
  42. #include "codecs/bolero/wsa-macro.h"
  43. #define DRV_NAME "qcs405-asoc-snd"
  44. #define __CHIPSET__ "QCS405 "
  45. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  46. #define DEV_NAME_STR_LEN 32
  47. #define SAMPLING_RATE_8KHZ 8000
  48. #define SAMPLING_RATE_11P025KHZ 11025
  49. #define SAMPLING_RATE_16KHZ 16000
  50. #define SAMPLING_RATE_22P05KHZ 22050
  51. #define SAMPLING_RATE_32KHZ 32000
  52. #define SAMPLING_RATE_44P1KHZ 44100
  53. #define SAMPLING_RATE_48KHZ 48000
  54. #define SAMPLING_RATE_88P2KHZ 88200
  55. #define SAMPLING_RATE_96KHZ 96000
  56. #define SAMPLING_RATE_176P4KHZ 176400
  57. #define SAMPLING_RATE_192KHZ 192000
  58. #define SAMPLING_RATE_352P8KHZ 352800
  59. #define SAMPLING_RATE_384KHZ 384000
  60. #define SPDIF_TX_CORE_CLK_204_P8_MHZ 204800000
  61. #define TLMM_EAST_SPARE 0x07BA0000
  62. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  63. #define WSA8810_NAME_1 "wsa881x.20170211"
  64. #define WSA8810_NAME_2 "wsa881x.20170212"
  65. #define WCN_CDC_SLIM_RX_CH_MAX 2
  66. #define WCN_CDC_SLIM_TX_CH_MAX 3
  67. #define TDM_CHANNEL_MAX 8
  68. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  69. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  70. enum {
  71. SLIM_RX_0 = 0,
  72. SLIM_RX_1,
  73. SLIM_RX_2,
  74. SLIM_RX_3,
  75. SLIM_RX_4,
  76. SLIM_RX_5,
  77. SLIM_RX_6,
  78. SLIM_RX_7,
  79. SLIM_RX_MAX,
  80. };
  81. enum {
  82. SLIM_TX_0 = 0,
  83. SLIM_TX_1,
  84. SLIM_TX_2,
  85. SLIM_TX_3,
  86. SLIM_TX_4,
  87. SLIM_TX_5,
  88. SLIM_TX_6,
  89. SLIM_TX_7,
  90. SLIM_TX_8,
  91. SLIM_TX_MAX,
  92. };
  93. enum {
  94. PRIM_MI2S = 0,
  95. SEC_MI2S,
  96. TERT_MI2S,
  97. QUAT_MI2S,
  98. QUIN_MI2S,
  99. MI2S_MAX,
  100. };
  101. enum {
  102. PRIM_AUX_PCM = 0,
  103. SEC_AUX_PCM,
  104. TERT_AUX_PCM,
  105. QUAT_AUX_PCM,
  106. QUIN_AUX_PCM,
  107. AUX_PCM_MAX,
  108. };
  109. enum {
  110. WSA_CDC_DMA_RX_0 = 0,
  111. WSA_CDC_DMA_RX_1,
  112. CDC_DMA_RX_MAX,
  113. };
  114. enum {
  115. WSA_CDC_DMA_TX_0 = 0,
  116. WSA_CDC_DMA_TX_1,
  117. WSA_CDC_DMA_TX_2,
  118. VA_CDC_DMA_TX_0,
  119. VA_CDC_DMA_TX_1,
  120. CDC_DMA_TX_MAX,
  121. };
  122. enum {
  123. PRIM_SPDIF_RX = 0,
  124. SEC_SPDIF_RX,
  125. SPDIF_RX_MAX,
  126. };
  127. enum {
  128. PRIM_SPDIF_TX = 0,
  129. SEC_SPDIF_TX,
  130. SPDIF_TX_MAX,
  131. };
  132. struct mi2s_conf {
  133. struct mutex lock;
  134. u32 ref_cnt;
  135. u32 msm_is_mi2s_master;
  136. };
  137. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  138. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  139. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  140. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  141. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  142. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  143. };
  144. struct dev_config {
  145. u32 sample_rate;
  146. u32 bit_format;
  147. u32 channels;
  148. };
  149. struct msm_wsa881x_dev_info {
  150. struct device_node *of_node;
  151. u32 index;
  152. };
  153. struct msm_csra66x0_dev_info {
  154. struct device_node *of_node;
  155. u32 index;
  156. };
  157. enum pinctrl_pin_state {
  158. STATE_DISABLE = 0, /* All pins are in sleep state */
  159. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  160. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  161. };
  162. struct msm_pinctrl_info {
  163. struct pinctrl *pinctrl;
  164. struct pinctrl_state *mi2s_disable;
  165. struct pinctrl_state *tdm_disable;
  166. struct pinctrl_state *mi2s_active;
  167. struct pinctrl_state *tdm_active;
  168. enum pinctrl_pin_state curr_state;
  169. };
  170. struct msm_asoc_mach_data {
  171. struct snd_info_entry *codec_root;
  172. struct msm_pinctrl_info pinctrl_info;
  173. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  174. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  175. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  176. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  177. int dmic_01_gpio_cnt;
  178. int dmic_23_gpio_cnt;
  179. int dmic_45_gpio_cnt;
  180. int dmic_67_gpio_cnt;
  181. };
  182. struct msm_asoc_wcd93xx_codec {
  183. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  184. enum afe_config_type config_type);
  185. };
  186. static const char *const pin_states[] = {"sleep", "i2s-active",
  187. "tdm-active"};
  188. enum {
  189. TDM_0 = 0,
  190. TDM_1,
  191. TDM_2,
  192. TDM_3,
  193. TDM_4,
  194. TDM_5,
  195. TDM_6,
  196. TDM_7,
  197. TDM_PORT_MAX,
  198. };
  199. enum {
  200. TDM_PRI = 0,
  201. TDM_SEC,
  202. TDM_TERT,
  203. TDM_QUAT,
  204. TDM_QUIN,
  205. TDM_INTERFACE_MAX,
  206. };
  207. struct tdm_port {
  208. u32 mode;
  209. u32 channel;
  210. };
  211. /* TDM default config */
  212. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  213. { /* PRI TDM */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  222. },
  223. { /* SEC TDM */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  232. },
  233. { /* TERT TDM */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  242. },
  243. { /* QUAT TDM */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  252. },
  253. { /* QUIN TDM */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  262. }
  263. };
  264. /* TDM default config */
  265. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  266. { /* PRI TDM */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  275. },
  276. { /* SEC TDM */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  285. },
  286. { /* TERT TDM */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  295. },
  296. { /* QUAT TDM */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  305. },
  306. { /* QUIN TDM */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  315. }
  316. };
  317. /* Default configuration of slimbus channels */
  318. static struct dev_config slim_rx_cfg[] = {
  319. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  327. };
  328. static struct dev_config slim_tx_cfg[] = {
  329. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  330. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  331. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  332. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  333. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  334. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  335. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  336. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  337. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. };
  339. /* Default configuration of Codec DMA Interface Tx */
  340. static struct dev_config cdc_dma_rx_cfg[] = {
  341. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  342. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  343. };
  344. /* Default configuration of Codec DMA Interface Rx */
  345. static struct dev_config cdc_dma_tx_cfg[] = {
  346. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  347. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  349. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  350. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  351. };
  352. static struct dev_config usb_rx_cfg = {
  353. .sample_rate = SAMPLING_RATE_48KHZ,
  354. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  355. .channels = 2,
  356. };
  357. static struct dev_config usb_tx_cfg = {
  358. .sample_rate = SAMPLING_RATE_48KHZ,
  359. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  360. .channels = 1,
  361. };
  362. static struct dev_config proxy_rx_cfg = {
  363. .sample_rate = SAMPLING_RATE_48KHZ,
  364. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  365. .channels = 2,
  366. };
  367. /* Default configuration of MI2S channels */
  368. static struct dev_config mi2s_rx_cfg[] = {
  369. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  371. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  372. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  373. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  374. };
  375. /* Default configuration of SPDIF channels */
  376. static struct dev_config spdif_rx_cfg[] = {
  377. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  378. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  379. };
  380. static struct dev_config spdif_tx_cfg[] = {
  381. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  382. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  383. };
  384. static struct dev_config mi2s_tx_cfg[] = {
  385. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  389. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  390. };
  391. static struct dev_config aux_pcm_rx_cfg[] = {
  392. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  393. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. };
  398. static struct dev_config aux_pcm_tx_cfg[] = {
  399. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  400. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  401. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  402. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  403. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  404. };
  405. static int msm_vi_feed_tx_ch = 2;
  406. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  407. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  408. "Five", "Six", "Seven",
  409. "Eight"};
  410. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  411. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  412. "S32_LE"};
  413. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  414. "KHZ_32", "KHZ_44P1", "KHZ_48",
  415. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  416. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  417. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  418. "KHZ_44P1", "KHZ_48",
  419. "KHZ_88P2", "KHZ_96"};
  420. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  421. "Five", "Six", "Seven",
  422. "Eight"};
  423. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  424. "Six", "Seven", "Eight"};
  425. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  426. "KHZ_16", "KHZ_22P05",
  427. "KHZ_32", "KHZ_44P1", "KHZ_48",
  428. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  429. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  430. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  431. "Five", "Six", "Seven", "Eight"};
  432. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  433. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  434. "KHZ_48", "KHZ_176P4",
  435. "KHZ_352P8"};
  436. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  437. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  438. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  439. "KHZ_48", "KHZ_96", "KHZ_192"};
  440. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  441. "Five", "Six", "Seven",
  442. "Eight"};
  443. static const char *const qos_text[] = {"Disable", "Enable"};
  444. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  445. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  446. "Five", "Six", "Seven",
  447. "Eight"};
  448. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  449. "KHZ_16", "KHZ_22P05",
  450. "KHZ_32", "KHZ_44P1", "KHZ_48",
  451. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  452. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  453. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  454. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  455. "KHZ_192"};
  456. static const char *spdif_ch_text[] = {"One", "Two"};
  457. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  458. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  536. cdc_dma_sample_rate_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  538. cdc_dma_sample_rate_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  540. cdc_dma_sample_rate_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  542. cdc_dma_sample_rate_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  544. cdc_dma_sample_rate_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  546. cdc_dma_sample_rate_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  548. cdc_dma_sample_rate_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  555. static struct platform_device *spdev;
  556. static bool is_initial_boot;
  557. static bool codec_reg_done;
  558. static struct snd_soc_aux_dev *msm_aux_dev;
  559. static struct snd_soc_codec_conf *msm_codec_conf;
  560. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  561. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  562. int enable, bool dapm);
  563. static int msm_wsa881x_init(struct snd_soc_component *component);
  564. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  565. struct snd_ctl_elem_value *ucontrol);
  566. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  567. {"MIC BIAS1", NULL, "MCLK TX"},
  568. {"MIC BIAS2", NULL, "MCLK TX"},
  569. {"MIC BIAS3", NULL, "MCLK TX"},
  570. {"MIC BIAS4", NULL, "MCLK TX"},
  571. };
  572. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  573. {
  574. AFE_API_VERSION_I2S_CONFIG,
  575. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  576. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  577. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  578. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  579. 0,
  580. },
  581. {
  582. AFE_API_VERSION_I2S_CONFIG,
  583. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  584. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  585. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  586. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  587. 0,
  588. },
  589. {
  590. AFE_API_VERSION_I2S_CONFIG,
  591. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  592. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  593. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  594. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  595. 0,
  596. },
  597. {
  598. AFE_API_VERSION_I2S_CONFIG,
  599. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  600. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  601. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  602. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  603. 0,
  604. },
  605. {
  606. AFE_API_VERSION_I2S_CONFIG,
  607. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  608. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  609. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  610. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  611. 0,
  612. }
  613. };
  614. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  615. static int slim_get_sample_rate_val(int sample_rate)
  616. {
  617. int sample_rate_val = 0;
  618. switch (sample_rate) {
  619. case SAMPLING_RATE_8KHZ:
  620. sample_rate_val = 0;
  621. break;
  622. case SAMPLING_RATE_16KHZ:
  623. sample_rate_val = 1;
  624. break;
  625. case SAMPLING_RATE_32KHZ:
  626. sample_rate_val = 2;
  627. break;
  628. case SAMPLING_RATE_44P1KHZ:
  629. sample_rate_val = 3;
  630. break;
  631. case SAMPLING_RATE_48KHZ:
  632. sample_rate_val = 4;
  633. break;
  634. case SAMPLING_RATE_88P2KHZ:
  635. sample_rate_val = 5;
  636. break;
  637. case SAMPLING_RATE_96KHZ:
  638. sample_rate_val = 6;
  639. break;
  640. case SAMPLING_RATE_176P4KHZ:
  641. sample_rate_val = 7;
  642. break;
  643. case SAMPLING_RATE_192KHZ:
  644. sample_rate_val = 8;
  645. break;
  646. case SAMPLING_RATE_352P8KHZ:
  647. sample_rate_val = 9;
  648. break;
  649. case SAMPLING_RATE_384KHZ:
  650. sample_rate_val = 10;
  651. break;
  652. default:
  653. sample_rate_val = 4;
  654. break;
  655. }
  656. return sample_rate_val;
  657. }
  658. static int slim_get_sample_rate(int value)
  659. {
  660. int sample_rate = 0;
  661. switch (value) {
  662. case 0:
  663. sample_rate = SAMPLING_RATE_8KHZ;
  664. break;
  665. case 1:
  666. sample_rate = SAMPLING_RATE_16KHZ;
  667. break;
  668. case 2:
  669. sample_rate = SAMPLING_RATE_32KHZ;
  670. break;
  671. case 3:
  672. sample_rate = SAMPLING_RATE_44P1KHZ;
  673. break;
  674. case 4:
  675. sample_rate = SAMPLING_RATE_48KHZ;
  676. break;
  677. case 5:
  678. sample_rate = SAMPLING_RATE_88P2KHZ;
  679. break;
  680. case 6:
  681. sample_rate = SAMPLING_RATE_96KHZ;
  682. break;
  683. case 7:
  684. sample_rate = SAMPLING_RATE_176P4KHZ;
  685. break;
  686. case 8:
  687. sample_rate = SAMPLING_RATE_192KHZ;
  688. break;
  689. case 9:
  690. sample_rate = SAMPLING_RATE_352P8KHZ;
  691. break;
  692. case 10:
  693. sample_rate = SAMPLING_RATE_384KHZ;
  694. break;
  695. default:
  696. sample_rate = SAMPLING_RATE_48KHZ;
  697. break;
  698. }
  699. return sample_rate;
  700. }
  701. static int slim_get_bit_format_val(int bit_format)
  702. {
  703. int val = 0;
  704. switch (bit_format) {
  705. case SNDRV_PCM_FORMAT_S32_LE:
  706. val = 3;
  707. break;
  708. case SNDRV_PCM_FORMAT_S24_3LE:
  709. val = 2;
  710. break;
  711. case SNDRV_PCM_FORMAT_S24_LE:
  712. val = 1;
  713. break;
  714. case SNDRV_PCM_FORMAT_S16_LE:
  715. default:
  716. val = 0;
  717. break;
  718. }
  719. return val;
  720. }
  721. static int slim_get_bit_format(int val)
  722. {
  723. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  724. switch (val) {
  725. case 0:
  726. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  727. break;
  728. case 1:
  729. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  730. break;
  731. case 2:
  732. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  733. break;
  734. case 3:
  735. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  736. break;
  737. default:
  738. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  739. break;
  740. }
  741. return bit_fmt;
  742. }
  743. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  744. {
  745. int port_id = 0;
  746. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  747. port_id = SLIM_RX_0;
  748. } else if (strnstr(kcontrol->id.name,
  749. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  750. port_id = SLIM_RX_2;
  751. } else if (strnstr(kcontrol->id.name,
  752. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  753. port_id = SLIM_RX_5;
  754. } else if (strnstr(kcontrol->id.name,
  755. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  756. port_id = SLIM_RX_6;
  757. } else if (strnstr(kcontrol->id.name,
  758. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  759. port_id = SLIM_TX_0;
  760. } else if (strnstr(kcontrol->id.name,
  761. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  762. port_id = SLIM_TX_1;
  763. } else {
  764. pr_err("%s: unsupported channel: %s",
  765. __func__, kcontrol->id.name);
  766. return -EINVAL;
  767. }
  768. return port_id;
  769. }
  770. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  771. struct snd_ctl_elem_value *ucontrol)
  772. {
  773. int ch_num = slim_get_port_idx(kcontrol);
  774. if (ch_num < 0)
  775. return ch_num;
  776. ucontrol->value.enumerated.item[0] =
  777. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  778. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  779. ch_num, slim_rx_cfg[ch_num].sample_rate,
  780. ucontrol->value.enumerated.item[0]);
  781. return 0;
  782. }
  783. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  784. struct snd_ctl_elem_value *ucontrol)
  785. {
  786. int ch_num = slim_get_port_idx(kcontrol);
  787. if (ch_num < 0)
  788. return ch_num;
  789. slim_rx_cfg[ch_num].sample_rate =
  790. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  791. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  792. ch_num, slim_rx_cfg[ch_num].sample_rate,
  793. ucontrol->value.enumerated.item[0]);
  794. return 0;
  795. }
  796. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  797. struct snd_ctl_elem_value *ucontrol)
  798. {
  799. int ch_num = slim_get_port_idx(kcontrol);
  800. if (ch_num < 0)
  801. return ch_num;
  802. ucontrol->value.enumerated.item[0] =
  803. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  804. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  805. ch_num, slim_tx_cfg[ch_num].sample_rate,
  806. ucontrol->value.enumerated.item[0]);
  807. return 0;
  808. }
  809. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  810. struct snd_ctl_elem_value *ucontrol)
  811. {
  812. int sample_rate = 0;
  813. int ch_num = slim_get_port_idx(kcontrol);
  814. if (ch_num < 0)
  815. return ch_num;
  816. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  817. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  818. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  819. __func__, sample_rate);
  820. return -EINVAL;
  821. }
  822. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  823. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  824. ch_num, slim_tx_cfg[ch_num].sample_rate,
  825. ucontrol->value.enumerated.item[0]);
  826. return 0;
  827. }
  828. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  829. struct snd_ctl_elem_value *ucontrol)
  830. {
  831. int ch_num = slim_get_port_idx(kcontrol);
  832. if (ch_num < 0)
  833. return ch_num;
  834. ucontrol->value.enumerated.item[0] =
  835. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  836. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  837. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  838. ucontrol->value.enumerated.item[0]);
  839. return 0;
  840. }
  841. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  842. struct snd_ctl_elem_value *ucontrol)
  843. {
  844. int ch_num = slim_get_port_idx(kcontrol);
  845. if (ch_num < 0)
  846. return ch_num;
  847. slim_rx_cfg[ch_num].bit_format =
  848. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  849. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  850. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  851. ucontrol->value.enumerated.item[0]);
  852. return 0;
  853. }
  854. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  855. struct snd_ctl_elem_value *ucontrol)
  856. {
  857. int ch_num = slim_get_port_idx(kcontrol);
  858. if (ch_num < 0)
  859. return ch_num;
  860. ucontrol->value.enumerated.item[0] =
  861. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  862. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  863. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  864. ucontrol->value.enumerated.item[0]);
  865. return 0;
  866. }
  867. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  868. struct snd_ctl_elem_value *ucontrol)
  869. {
  870. int ch_num = slim_get_port_idx(kcontrol);
  871. if (ch_num < 0)
  872. return ch_num;
  873. slim_tx_cfg[ch_num].bit_format =
  874. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  875. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  876. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  877. ucontrol->value.enumerated.item[0]);
  878. return 0;
  879. }
  880. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  881. struct snd_ctl_elem_value *ucontrol)
  882. {
  883. int ch_num = slim_get_port_idx(kcontrol);
  884. if (ch_num < 0)
  885. return ch_num;
  886. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  887. ch_num, slim_rx_cfg[ch_num].channels);
  888. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  889. return 0;
  890. }
  891. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  892. struct snd_ctl_elem_value *ucontrol)
  893. {
  894. int ch_num = slim_get_port_idx(kcontrol);
  895. if (ch_num < 0)
  896. return ch_num;
  897. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  898. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  899. ch_num, slim_rx_cfg[ch_num].channels);
  900. return 1;
  901. }
  902. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  903. struct snd_ctl_elem_value *ucontrol)
  904. {
  905. int ch_num = slim_get_port_idx(kcontrol);
  906. if (ch_num < 0)
  907. return ch_num;
  908. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  909. ch_num, slim_tx_cfg[ch_num].channels);
  910. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  911. return 0;
  912. }
  913. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  914. struct snd_ctl_elem_value *ucontrol)
  915. {
  916. int ch_num = slim_get_port_idx(kcontrol);
  917. if (ch_num < 0)
  918. return ch_num;
  919. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  920. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  921. ch_num, slim_tx_cfg[ch_num].channels);
  922. return 1;
  923. }
  924. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  925. struct snd_ctl_elem_value *ucontrol)
  926. {
  927. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  928. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  929. ucontrol->value.integer.value[0]);
  930. return 0;
  931. }
  932. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  933. struct snd_ctl_elem_value *ucontrol)
  934. {
  935. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  936. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  937. return 1;
  938. }
  939. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  940. struct snd_ctl_elem_value *ucontrol)
  941. {
  942. /*
  943. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  944. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  945. * value.
  946. */
  947. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  948. case SAMPLING_RATE_96KHZ:
  949. ucontrol->value.integer.value[0] = 5;
  950. break;
  951. case SAMPLING_RATE_88P2KHZ:
  952. ucontrol->value.integer.value[0] = 4;
  953. break;
  954. case SAMPLING_RATE_48KHZ:
  955. ucontrol->value.integer.value[0] = 3;
  956. break;
  957. case SAMPLING_RATE_44P1KHZ:
  958. ucontrol->value.integer.value[0] = 2;
  959. break;
  960. case SAMPLING_RATE_16KHZ:
  961. ucontrol->value.integer.value[0] = 1;
  962. break;
  963. case SAMPLING_RATE_8KHZ:
  964. default:
  965. ucontrol->value.integer.value[0] = 0;
  966. break;
  967. }
  968. pr_debug("%s: sample rate = %d", __func__,
  969. slim_rx_cfg[SLIM_RX_7].sample_rate);
  970. return 0;
  971. }
  972. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  973. struct snd_ctl_elem_value *ucontrol)
  974. {
  975. switch (ucontrol->value.integer.value[0]) {
  976. case 1:
  977. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  978. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  979. break;
  980. case 2:
  981. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  982. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  983. break;
  984. case 3:
  985. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  986. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  987. break;
  988. case 4:
  989. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  990. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  991. break;
  992. case 5:
  993. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  994. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  995. break;
  996. case 0:
  997. default:
  998. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  999. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1000. break;
  1001. }
  1002. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1003. __func__,
  1004. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1005. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1006. ucontrol->value.enumerated.item[0]);
  1007. return 0;
  1008. }
  1009. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1010. {
  1011. int idx = 0;
  1012. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1013. sizeof("WSA_CDC_DMA_RX_0")))
  1014. idx = WSA_CDC_DMA_RX_0;
  1015. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1016. sizeof("WSA_CDC_DMA_RX_0")))
  1017. idx = WSA_CDC_DMA_RX_1;
  1018. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1019. sizeof("WSA_CDC_DMA_TX_0")))
  1020. idx = WSA_CDC_DMA_TX_0;
  1021. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1022. sizeof("WSA_CDC_DMA_TX_1")))
  1023. idx = WSA_CDC_DMA_TX_1;
  1024. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1025. sizeof("WSA_CDC_DMA_TX_2")))
  1026. idx = WSA_CDC_DMA_TX_2;
  1027. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1028. sizeof("VA_CDC_DMA_TX_0")))
  1029. idx = VA_CDC_DMA_TX_0;
  1030. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1031. sizeof("VA_CDC_DMA_TX_1")))
  1032. idx = VA_CDC_DMA_TX_1;
  1033. else {
  1034. pr_err("%s: unsupported port: %s\n",
  1035. __func__, kcontrol->id.name);
  1036. return -EINVAL;
  1037. }
  1038. return idx;
  1039. }
  1040. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1041. struct snd_ctl_elem_value *ucontrol)
  1042. {
  1043. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1044. if (ch_num < 0)
  1045. return ch_num;
  1046. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1047. cdc_dma_rx_cfg[ch_num].channels - 1);
  1048. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1049. return 0;
  1050. }
  1051. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1052. struct snd_ctl_elem_value *ucontrol)
  1053. {
  1054. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1055. if (ch_num < 0)
  1056. return ch_num;
  1057. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1058. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1059. cdc_dma_rx_cfg[ch_num].channels);
  1060. return 1;
  1061. }
  1062. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1063. struct snd_ctl_elem_value *ucontrol)
  1064. {
  1065. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1066. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1067. case SNDRV_PCM_FORMAT_S32_LE:
  1068. ucontrol->value.integer.value[0] = 3;
  1069. break;
  1070. case SNDRV_PCM_FORMAT_S24_3LE:
  1071. ucontrol->value.integer.value[0] = 2;
  1072. break;
  1073. case SNDRV_PCM_FORMAT_S24_LE:
  1074. ucontrol->value.integer.value[0] = 1;
  1075. break;
  1076. case SNDRV_PCM_FORMAT_S16_LE:
  1077. default:
  1078. ucontrol->value.integer.value[0] = 0;
  1079. break;
  1080. }
  1081. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1082. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1083. ucontrol->value.integer.value[0]);
  1084. return 0;
  1085. }
  1086. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1087. struct snd_ctl_elem_value *ucontrol)
  1088. {
  1089. int rc = 0;
  1090. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1091. switch (ucontrol->value.integer.value[0]) {
  1092. case 3:
  1093. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1094. break;
  1095. case 2:
  1096. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1097. break;
  1098. case 1:
  1099. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1100. break;
  1101. case 0:
  1102. default:
  1103. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1104. break;
  1105. }
  1106. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1107. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1108. ucontrol->value.integer.value[0]);
  1109. return rc;
  1110. }
  1111. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1112. {
  1113. int sample_rate_val = 0;
  1114. switch (sample_rate) {
  1115. case SAMPLING_RATE_8KHZ:
  1116. sample_rate_val = 0;
  1117. break;
  1118. case SAMPLING_RATE_11P025KHZ:
  1119. sample_rate_val = 1;
  1120. break;
  1121. case SAMPLING_RATE_16KHZ:
  1122. sample_rate_val = 2;
  1123. break;
  1124. case SAMPLING_RATE_22P05KHZ:
  1125. sample_rate_val = 3;
  1126. break;
  1127. case SAMPLING_RATE_32KHZ:
  1128. sample_rate_val = 4;
  1129. break;
  1130. case SAMPLING_RATE_44P1KHZ:
  1131. sample_rate_val = 5;
  1132. break;
  1133. case SAMPLING_RATE_48KHZ:
  1134. sample_rate_val = 6;
  1135. break;
  1136. case SAMPLING_RATE_88P2KHZ:
  1137. sample_rate_val = 7;
  1138. break;
  1139. case SAMPLING_RATE_96KHZ:
  1140. sample_rate_val = 8;
  1141. break;
  1142. case SAMPLING_RATE_176P4KHZ:
  1143. sample_rate_val = 9;
  1144. break;
  1145. case SAMPLING_RATE_192KHZ:
  1146. sample_rate_val = 10;
  1147. break;
  1148. case SAMPLING_RATE_352P8KHZ:
  1149. sample_rate_val = 11;
  1150. break;
  1151. case SAMPLING_RATE_384KHZ:
  1152. sample_rate_val = 12;
  1153. break;
  1154. default:
  1155. sample_rate_val = 6;
  1156. break;
  1157. }
  1158. return sample_rate_val;
  1159. }
  1160. static int cdc_dma_get_sample_rate(int value)
  1161. {
  1162. int sample_rate = 0;
  1163. switch (value) {
  1164. case 0:
  1165. sample_rate = SAMPLING_RATE_8KHZ;
  1166. break;
  1167. case 1:
  1168. sample_rate = SAMPLING_RATE_11P025KHZ;
  1169. break;
  1170. case 2:
  1171. sample_rate = SAMPLING_RATE_16KHZ;
  1172. break;
  1173. case 3:
  1174. sample_rate = SAMPLING_RATE_22P05KHZ;
  1175. break;
  1176. case 4:
  1177. sample_rate = SAMPLING_RATE_32KHZ;
  1178. break;
  1179. case 5:
  1180. sample_rate = SAMPLING_RATE_44P1KHZ;
  1181. break;
  1182. case 6:
  1183. sample_rate = SAMPLING_RATE_48KHZ;
  1184. break;
  1185. case 7:
  1186. sample_rate = SAMPLING_RATE_88P2KHZ;
  1187. break;
  1188. case 8:
  1189. sample_rate = SAMPLING_RATE_96KHZ;
  1190. break;
  1191. case 9:
  1192. sample_rate = SAMPLING_RATE_176P4KHZ;
  1193. break;
  1194. case 10:
  1195. sample_rate = SAMPLING_RATE_192KHZ;
  1196. break;
  1197. case 11:
  1198. sample_rate = SAMPLING_RATE_352P8KHZ;
  1199. break;
  1200. case 12:
  1201. sample_rate = SAMPLING_RATE_384KHZ;
  1202. break;
  1203. default:
  1204. sample_rate = SAMPLING_RATE_48KHZ;
  1205. break;
  1206. }
  1207. return sample_rate;
  1208. }
  1209. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1210. struct snd_ctl_elem_value *ucontrol)
  1211. {
  1212. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1213. if (ch_num < 0)
  1214. return ch_num;
  1215. ucontrol->value.enumerated.item[0] =
  1216. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1217. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1218. cdc_dma_rx_cfg[ch_num].sample_rate);
  1219. return 0;
  1220. }
  1221. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1222. struct snd_ctl_elem_value *ucontrol)
  1223. {
  1224. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1225. if (ch_num < 0)
  1226. return ch_num;
  1227. cdc_dma_rx_cfg[ch_num].sample_rate =
  1228. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1229. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1230. __func__, ucontrol->value.enumerated.item[0],
  1231. cdc_dma_rx_cfg[ch_num].sample_rate);
  1232. return 0;
  1233. }
  1234. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1235. struct snd_ctl_elem_value *ucontrol)
  1236. {
  1237. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1238. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1239. cdc_dma_tx_cfg[ch_num].channels);
  1240. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1241. return 0;
  1242. }
  1243. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1244. struct snd_ctl_elem_value *ucontrol)
  1245. {
  1246. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1247. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1248. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1249. cdc_dma_tx_cfg[ch_num].channels);
  1250. return 1;
  1251. }
  1252. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1253. struct snd_ctl_elem_value *ucontrol)
  1254. {
  1255. int sample_rate_val;
  1256. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1257. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1258. case SAMPLING_RATE_384KHZ:
  1259. sample_rate_val = 12;
  1260. break;
  1261. case SAMPLING_RATE_352P8KHZ:
  1262. sample_rate_val = 11;
  1263. break;
  1264. case SAMPLING_RATE_192KHZ:
  1265. sample_rate_val = 10;
  1266. break;
  1267. case SAMPLING_RATE_176P4KHZ:
  1268. sample_rate_val = 9;
  1269. break;
  1270. case SAMPLING_RATE_96KHZ:
  1271. sample_rate_val = 8;
  1272. break;
  1273. case SAMPLING_RATE_88P2KHZ:
  1274. sample_rate_val = 7;
  1275. break;
  1276. case SAMPLING_RATE_48KHZ:
  1277. sample_rate_val = 6;
  1278. break;
  1279. case SAMPLING_RATE_44P1KHZ:
  1280. sample_rate_val = 5;
  1281. break;
  1282. case SAMPLING_RATE_32KHZ:
  1283. sample_rate_val = 4;
  1284. break;
  1285. case SAMPLING_RATE_22P05KHZ:
  1286. sample_rate_val = 3;
  1287. break;
  1288. case SAMPLING_RATE_16KHZ:
  1289. sample_rate_val = 2;
  1290. break;
  1291. case SAMPLING_RATE_11P025KHZ:
  1292. sample_rate_val = 1;
  1293. break;
  1294. case SAMPLING_RATE_8KHZ:
  1295. sample_rate_val = 0;
  1296. break;
  1297. default:
  1298. sample_rate_val = 6;
  1299. break;
  1300. }
  1301. ucontrol->value.integer.value[0] = sample_rate_val;
  1302. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1303. cdc_dma_tx_cfg[ch_num].sample_rate);
  1304. return 0;
  1305. }
  1306. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1307. struct snd_ctl_elem_value *ucontrol)
  1308. {
  1309. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1310. switch (ucontrol->value.integer.value[0]) {
  1311. case 12:
  1312. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1313. break;
  1314. case 11:
  1315. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1316. break;
  1317. case 10:
  1318. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1319. break;
  1320. case 9:
  1321. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1322. break;
  1323. case 8:
  1324. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1325. break;
  1326. case 7:
  1327. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1328. break;
  1329. case 6:
  1330. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1331. break;
  1332. case 5:
  1333. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1334. break;
  1335. case 4:
  1336. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1337. break;
  1338. case 3:
  1339. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1340. break;
  1341. case 2:
  1342. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1343. break;
  1344. case 1:
  1345. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1346. break;
  1347. case 0:
  1348. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1349. break;
  1350. default:
  1351. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1352. break;
  1353. }
  1354. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1355. __func__, ucontrol->value.integer.value[0],
  1356. cdc_dma_tx_cfg[ch_num].sample_rate);
  1357. return 0;
  1358. }
  1359. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1360. struct snd_ctl_elem_value *ucontrol)
  1361. {
  1362. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1363. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1364. case SNDRV_PCM_FORMAT_S32_LE:
  1365. ucontrol->value.integer.value[0] = 3;
  1366. break;
  1367. case SNDRV_PCM_FORMAT_S24_3LE:
  1368. ucontrol->value.integer.value[0] = 2;
  1369. break;
  1370. case SNDRV_PCM_FORMAT_S24_LE:
  1371. ucontrol->value.integer.value[0] = 1;
  1372. break;
  1373. case SNDRV_PCM_FORMAT_S16_LE:
  1374. default:
  1375. ucontrol->value.integer.value[0] = 0;
  1376. break;
  1377. }
  1378. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1379. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1380. ucontrol->value.integer.value[0]);
  1381. return 0;
  1382. }
  1383. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1384. struct snd_ctl_elem_value *ucontrol)
  1385. {
  1386. int rc = 0;
  1387. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1388. switch (ucontrol->value.integer.value[0]) {
  1389. case 3:
  1390. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1391. break;
  1392. case 2:
  1393. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1394. break;
  1395. case 1:
  1396. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1397. break;
  1398. case 0:
  1399. default:
  1400. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1401. break;
  1402. }
  1403. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1404. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1405. ucontrol->value.integer.value[0]);
  1406. return rc;
  1407. }
  1408. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1409. struct snd_ctl_elem_value *ucontrol)
  1410. {
  1411. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1412. usb_rx_cfg.channels);
  1413. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1414. return 0;
  1415. }
  1416. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1417. struct snd_ctl_elem_value *ucontrol)
  1418. {
  1419. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1420. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1421. return 1;
  1422. }
  1423. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1424. struct snd_ctl_elem_value *ucontrol)
  1425. {
  1426. int sample_rate_val;
  1427. switch (usb_rx_cfg.sample_rate) {
  1428. case SAMPLING_RATE_384KHZ:
  1429. sample_rate_val = 12;
  1430. break;
  1431. case SAMPLING_RATE_352P8KHZ:
  1432. sample_rate_val = 11;
  1433. break;
  1434. case SAMPLING_RATE_192KHZ:
  1435. sample_rate_val = 10;
  1436. break;
  1437. case SAMPLING_RATE_176P4KHZ:
  1438. sample_rate_val = 9;
  1439. break;
  1440. case SAMPLING_RATE_96KHZ:
  1441. sample_rate_val = 8;
  1442. break;
  1443. case SAMPLING_RATE_88P2KHZ:
  1444. sample_rate_val = 7;
  1445. break;
  1446. case SAMPLING_RATE_48KHZ:
  1447. sample_rate_val = 6;
  1448. break;
  1449. case SAMPLING_RATE_44P1KHZ:
  1450. sample_rate_val = 5;
  1451. break;
  1452. case SAMPLING_RATE_32KHZ:
  1453. sample_rate_val = 4;
  1454. break;
  1455. case SAMPLING_RATE_22P05KHZ:
  1456. sample_rate_val = 3;
  1457. break;
  1458. case SAMPLING_RATE_16KHZ:
  1459. sample_rate_val = 2;
  1460. break;
  1461. case SAMPLING_RATE_11P025KHZ:
  1462. sample_rate_val = 1;
  1463. break;
  1464. case SAMPLING_RATE_8KHZ:
  1465. default:
  1466. sample_rate_val = 0;
  1467. break;
  1468. }
  1469. ucontrol->value.integer.value[0] = sample_rate_val;
  1470. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1471. usb_rx_cfg.sample_rate);
  1472. return 0;
  1473. }
  1474. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1475. struct snd_ctl_elem_value *ucontrol)
  1476. {
  1477. switch (ucontrol->value.integer.value[0]) {
  1478. case 12:
  1479. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1480. break;
  1481. case 11:
  1482. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1483. break;
  1484. case 10:
  1485. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1486. break;
  1487. case 9:
  1488. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1489. break;
  1490. case 8:
  1491. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1492. break;
  1493. case 7:
  1494. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1495. break;
  1496. case 6:
  1497. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1498. break;
  1499. case 5:
  1500. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1501. break;
  1502. case 4:
  1503. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1504. break;
  1505. case 3:
  1506. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1507. break;
  1508. case 2:
  1509. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1510. break;
  1511. case 1:
  1512. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1513. break;
  1514. case 0:
  1515. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1516. break;
  1517. default:
  1518. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1519. break;
  1520. }
  1521. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1522. __func__, ucontrol->value.integer.value[0],
  1523. usb_rx_cfg.sample_rate);
  1524. return 0;
  1525. }
  1526. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1527. struct snd_ctl_elem_value *ucontrol)
  1528. {
  1529. switch (usb_rx_cfg.bit_format) {
  1530. case SNDRV_PCM_FORMAT_S32_LE:
  1531. ucontrol->value.integer.value[0] = 3;
  1532. break;
  1533. case SNDRV_PCM_FORMAT_S24_3LE:
  1534. ucontrol->value.integer.value[0] = 2;
  1535. break;
  1536. case SNDRV_PCM_FORMAT_S24_LE:
  1537. ucontrol->value.integer.value[0] = 1;
  1538. break;
  1539. case SNDRV_PCM_FORMAT_S16_LE:
  1540. default:
  1541. ucontrol->value.integer.value[0] = 0;
  1542. break;
  1543. }
  1544. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1545. __func__, usb_rx_cfg.bit_format,
  1546. ucontrol->value.integer.value[0]);
  1547. return 0;
  1548. }
  1549. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1550. struct snd_ctl_elem_value *ucontrol)
  1551. {
  1552. int rc = 0;
  1553. switch (ucontrol->value.integer.value[0]) {
  1554. case 3:
  1555. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1556. break;
  1557. case 2:
  1558. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1559. break;
  1560. case 1:
  1561. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1562. break;
  1563. case 0:
  1564. default:
  1565. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1566. break;
  1567. }
  1568. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1569. __func__, usb_rx_cfg.bit_format,
  1570. ucontrol->value.integer.value[0]);
  1571. return rc;
  1572. }
  1573. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1574. struct snd_ctl_elem_value *ucontrol)
  1575. {
  1576. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1577. usb_tx_cfg.channels);
  1578. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1579. return 0;
  1580. }
  1581. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1582. struct snd_ctl_elem_value *ucontrol)
  1583. {
  1584. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1585. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1586. return 1;
  1587. }
  1588. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1589. struct snd_ctl_elem_value *ucontrol)
  1590. {
  1591. int sample_rate_val;
  1592. switch (usb_tx_cfg.sample_rate) {
  1593. case SAMPLING_RATE_384KHZ:
  1594. sample_rate_val = 12;
  1595. break;
  1596. case SAMPLING_RATE_352P8KHZ:
  1597. sample_rate_val = 11;
  1598. break;
  1599. case SAMPLING_RATE_192KHZ:
  1600. sample_rate_val = 10;
  1601. break;
  1602. case SAMPLING_RATE_176P4KHZ:
  1603. sample_rate_val = 9;
  1604. break;
  1605. case SAMPLING_RATE_96KHZ:
  1606. sample_rate_val = 8;
  1607. break;
  1608. case SAMPLING_RATE_88P2KHZ:
  1609. sample_rate_val = 7;
  1610. break;
  1611. case SAMPLING_RATE_48KHZ:
  1612. sample_rate_val = 6;
  1613. break;
  1614. case SAMPLING_RATE_44P1KHZ:
  1615. sample_rate_val = 5;
  1616. break;
  1617. case SAMPLING_RATE_32KHZ:
  1618. sample_rate_val = 4;
  1619. break;
  1620. case SAMPLING_RATE_22P05KHZ:
  1621. sample_rate_val = 3;
  1622. break;
  1623. case SAMPLING_RATE_16KHZ:
  1624. sample_rate_val = 2;
  1625. break;
  1626. case SAMPLING_RATE_11P025KHZ:
  1627. sample_rate_val = 1;
  1628. break;
  1629. case SAMPLING_RATE_8KHZ:
  1630. sample_rate_val = 0;
  1631. break;
  1632. default:
  1633. sample_rate_val = 6;
  1634. break;
  1635. }
  1636. ucontrol->value.integer.value[0] = sample_rate_val;
  1637. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1638. usb_tx_cfg.sample_rate);
  1639. return 0;
  1640. }
  1641. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1642. struct snd_ctl_elem_value *ucontrol)
  1643. {
  1644. switch (ucontrol->value.integer.value[0]) {
  1645. case 12:
  1646. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1647. break;
  1648. case 11:
  1649. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1650. break;
  1651. case 10:
  1652. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1653. break;
  1654. case 9:
  1655. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1656. break;
  1657. case 8:
  1658. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1659. break;
  1660. case 7:
  1661. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1662. break;
  1663. case 6:
  1664. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1665. break;
  1666. case 5:
  1667. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1668. break;
  1669. case 4:
  1670. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1671. break;
  1672. case 3:
  1673. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1674. break;
  1675. case 2:
  1676. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1677. break;
  1678. case 1:
  1679. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1680. break;
  1681. case 0:
  1682. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1683. break;
  1684. default:
  1685. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1686. break;
  1687. }
  1688. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1689. __func__, ucontrol->value.integer.value[0],
  1690. usb_tx_cfg.sample_rate);
  1691. return 0;
  1692. }
  1693. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1694. struct snd_ctl_elem_value *ucontrol)
  1695. {
  1696. switch (usb_tx_cfg.bit_format) {
  1697. case SNDRV_PCM_FORMAT_S32_LE:
  1698. ucontrol->value.integer.value[0] = 3;
  1699. break;
  1700. case SNDRV_PCM_FORMAT_S24_3LE:
  1701. ucontrol->value.integer.value[0] = 2;
  1702. break;
  1703. case SNDRV_PCM_FORMAT_S24_LE:
  1704. ucontrol->value.integer.value[0] = 1;
  1705. break;
  1706. case SNDRV_PCM_FORMAT_S16_LE:
  1707. default:
  1708. ucontrol->value.integer.value[0] = 0;
  1709. break;
  1710. }
  1711. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1712. __func__, usb_tx_cfg.bit_format,
  1713. ucontrol->value.integer.value[0]);
  1714. return 0;
  1715. }
  1716. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1717. struct snd_ctl_elem_value *ucontrol)
  1718. {
  1719. int rc = 0;
  1720. switch (ucontrol->value.integer.value[0]) {
  1721. case 3:
  1722. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1723. break;
  1724. case 2:
  1725. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1726. break;
  1727. case 1:
  1728. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1729. break;
  1730. case 0:
  1731. default:
  1732. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1733. break;
  1734. }
  1735. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1736. __func__, usb_tx_cfg.bit_format,
  1737. ucontrol->value.integer.value[0]);
  1738. return rc;
  1739. }
  1740. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1741. struct snd_ctl_elem_value *ucontrol)
  1742. {
  1743. pr_debug("%s: proxy_rx channels = %d\n",
  1744. __func__, proxy_rx_cfg.channels);
  1745. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1746. return 0;
  1747. }
  1748. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1749. struct snd_ctl_elem_value *ucontrol)
  1750. {
  1751. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1752. pr_debug("%s: proxy_rx channels = %d\n",
  1753. __func__, proxy_rx_cfg.channels);
  1754. return 1;
  1755. }
  1756. static int tdm_get_sample_rate(int value)
  1757. {
  1758. int sample_rate = 0;
  1759. switch (value) {
  1760. case 0:
  1761. sample_rate = SAMPLING_RATE_8KHZ;
  1762. break;
  1763. case 1:
  1764. sample_rate = SAMPLING_RATE_16KHZ;
  1765. break;
  1766. case 2:
  1767. sample_rate = SAMPLING_RATE_32KHZ;
  1768. break;
  1769. case 3:
  1770. sample_rate = SAMPLING_RATE_48KHZ;
  1771. break;
  1772. case 4:
  1773. sample_rate = SAMPLING_RATE_176P4KHZ;
  1774. break;
  1775. case 5:
  1776. sample_rate = SAMPLING_RATE_352P8KHZ;
  1777. break;
  1778. default:
  1779. sample_rate = SAMPLING_RATE_48KHZ;
  1780. break;
  1781. }
  1782. return sample_rate;
  1783. }
  1784. static int aux_pcm_get_sample_rate(int value)
  1785. {
  1786. int sample_rate;
  1787. switch (value) {
  1788. case 1:
  1789. sample_rate = SAMPLING_RATE_16KHZ;
  1790. break;
  1791. case 0:
  1792. default:
  1793. sample_rate = SAMPLING_RATE_8KHZ;
  1794. break;
  1795. }
  1796. return sample_rate;
  1797. }
  1798. static int tdm_get_sample_rate_val(int sample_rate)
  1799. {
  1800. int sample_rate_val = 0;
  1801. switch (sample_rate) {
  1802. case SAMPLING_RATE_8KHZ:
  1803. sample_rate_val = 0;
  1804. break;
  1805. case SAMPLING_RATE_16KHZ:
  1806. sample_rate_val = 1;
  1807. break;
  1808. case SAMPLING_RATE_32KHZ:
  1809. sample_rate_val = 2;
  1810. break;
  1811. case SAMPLING_RATE_48KHZ:
  1812. sample_rate_val = 3;
  1813. break;
  1814. case SAMPLING_RATE_176P4KHZ:
  1815. sample_rate_val = 4;
  1816. break;
  1817. case SAMPLING_RATE_352P8KHZ:
  1818. sample_rate_val = 5;
  1819. break;
  1820. default:
  1821. sample_rate_val = 3;
  1822. break;
  1823. }
  1824. return sample_rate_val;
  1825. }
  1826. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1827. {
  1828. int sample_rate_val;
  1829. switch (sample_rate) {
  1830. case SAMPLING_RATE_16KHZ:
  1831. sample_rate_val = 1;
  1832. break;
  1833. case SAMPLING_RATE_8KHZ:
  1834. default:
  1835. sample_rate_val = 0;
  1836. break;
  1837. }
  1838. return sample_rate_val;
  1839. }
  1840. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1841. struct tdm_port *port)
  1842. {
  1843. if (port) {
  1844. if (strnstr(kcontrol->id.name, "PRI",
  1845. sizeof(kcontrol->id.name))) {
  1846. port->mode = TDM_PRI;
  1847. } else if (strnstr(kcontrol->id.name, "SEC",
  1848. sizeof(kcontrol->id.name))) {
  1849. port->mode = TDM_SEC;
  1850. } else if (strnstr(kcontrol->id.name, "TERT",
  1851. sizeof(kcontrol->id.name))) {
  1852. port->mode = TDM_TERT;
  1853. } else if (strnstr(kcontrol->id.name, "QUAT",
  1854. sizeof(kcontrol->id.name))) {
  1855. port->mode = TDM_QUAT;
  1856. } else if (strnstr(kcontrol->id.name, "QUIN",
  1857. sizeof(kcontrol->id.name))) {
  1858. port->mode = TDM_QUIN;
  1859. } else {
  1860. pr_err("%s: unsupported mode in: %s",
  1861. __func__, kcontrol->id.name);
  1862. return -EINVAL;
  1863. }
  1864. if (strnstr(kcontrol->id.name, "RX_0",
  1865. sizeof(kcontrol->id.name)) ||
  1866. strnstr(kcontrol->id.name, "TX_0",
  1867. sizeof(kcontrol->id.name))) {
  1868. port->channel = TDM_0;
  1869. } else if (strnstr(kcontrol->id.name, "RX_1",
  1870. sizeof(kcontrol->id.name)) ||
  1871. strnstr(kcontrol->id.name, "TX_1",
  1872. sizeof(kcontrol->id.name))) {
  1873. port->channel = TDM_1;
  1874. } else if (strnstr(kcontrol->id.name, "RX_2",
  1875. sizeof(kcontrol->id.name)) ||
  1876. strnstr(kcontrol->id.name, "TX_2",
  1877. sizeof(kcontrol->id.name))) {
  1878. port->channel = TDM_2;
  1879. } else if (strnstr(kcontrol->id.name, "RX_3",
  1880. sizeof(kcontrol->id.name)) ||
  1881. strnstr(kcontrol->id.name, "TX_3",
  1882. sizeof(kcontrol->id.name))) {
  1883. port->channel = TDM_3;
  1884. } else if (strnstr(kcontrol->id.name, "RX_4",
  1885. sizeof(kcontrol->id.name)) ||
  1886. strnstr(kcontrol->id.name, "TX_4",
  1887. sizeof(kcontrol->id.name))) {
  1888. port->channel = TDM_4;
  1889. } else if (strnstr(kcontrol->id.name, "RX_5",
  1890. sizeof(kcontrol->id.name)) ||
  1891. strnstr(kcontrol->id.name, "TX_5",
  1892. sizeof(kcontrol->id.name))) {
  1893. port->channel = TDM_5;
  1894. } else if (strnstr(kcontrol->id.name, "RX_6",
  1895. sizeof(kcontrol->id.name)) ||
  1896. strnstr(kcontrol->id.name, "TX_6",
  1897. sizeof(kcontrol->id.name))) {
  1898. port->channel = TDM_6;
  1899. } else if (strnstr(kcontrol->id.name, "RX_7",
  1900. sizeof(kcontrol->id.name)) ||
  1901. strnstr(kcontrol->id.name, "TX_7",
  1902. sizeof(kcontrol->id.name))) {
  1903. port->channel = TDM_7;
  1904. } else {
  1905. pr_err("%s: unsupported channel in: %s",
  1906. __func__, kcontrol->id.name);
  1907. return -EINVAL;
  1908. }
  1909. } else
  1910. return -EINVAL;
  1911. return 0;
  1912. }
  1913. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1914. struct snd_ctl_elem_value *ucontrol)
  1915. {
  1916. struct tdm_port port;
  1917. int ret = tdm_get_port_idx(kcontrol, &port);
  1918. if (ret) {
  1919. pr_err("%s: unsupported control: %s",
  1920. __func__, kcontrol->id.name);
  1921. } else {
  1922. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1923. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1924. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1925. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1926. ucontrol->value.enumerated.item[0]);
  1927. }
  1928. return ret;
  1929. }
  1930. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1931. struct snd_ctl_elem_value *ucontrol)
  1932. {
  1933. struct tdm_port port;
  1934. int ret = tdm_get_port_idx(kcontrol, &port);
  1935. if (ret) {
  1936. pr_err("%s: unsupported control: %s",
  1937. __func__, kcontrol->id.name);
  1938. } else {
  1939. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1940. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1941. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1942. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1943. ucontrol->value.enumerated.item[0]);
  1944. }
  1945. return ret;
  1946. }
  1947. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1948. struct snd_ctl_elem_value *ucontrol)
  1949. {
  1950. struct tdm_port port;
  1951. int ret = tdm_get_port_idx(kcontrol, &port);
  1952. if (ret) {
  1953. pr_err("%s: unsupported control: %s",
  1954. __func__, kcontrol->id.name);
  1955. } else {
  1956. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1957. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1958. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1959. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1960. ucontrol->value.enumerated.item[0]);
  1961. }
  1962. return ret;
  1963. }
  1964. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1965. struct snd_ctl_elem_value *ucontrol)
  1966. {
  1967. struct tdm_port port;
  1968. int ret = tdm_get_port_idx(kcontrol, &port);
  1969. if (ret) {
  1970. pr_err("%s: unsupported control: %s",
  1971. __func__, kcontrol->id.name);
  1972. } else {
  1973. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1974. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1975. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1976. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1977. ucontrol->value.enumerated.item[0]);
  1978. }
  1979. return ret;
  1980. }
  1981. static int tdm_get_format(int value)
  1982. {
  1983. int format = 0;
  1984. switch (value) {
  1985. case 0:
  1986. format = SNDRV_PCM_FORMAT_S16_LE;
  1987. break;
  1988. case 1:
  1989. format = SNDRV_PCM_FORMAT_S24_LE;
  1990. break;
  1991. case 2:
  1992. format = SNDRV_PCM_FORMAT_S32_LE;
  1993. break;
  1994. default:
  1995. format = SNDRV_PCM_FORMAT_S16_LE;
  1996. break;
  1997. }
  1998. return format;
  1999. }
  2000. static int tdm_get_format_val(int format)
  2001. {
  2002. int value = 0;
  2003. switch (format) {
  2004. case SNDRV_PCM_FORMAT_S16_LE:
  2005. value = 0;
  2006. break;
  2007. case SNDRV_PCM_FORMAT_S24_LE:
  2008. value = 1;
  2009. break;
  2010. case SNDRV_PCM_FORMAT_S32_LE:
  2011. value = 2;
  2012. break;
  2013. default:
  2014. value = 0;
  2015. break;
  2016. }
  2017. return value;
  2018. }
  2019. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2020. struct snd_ctl_elem_value *ucontrol)
  2021. {
  2022. struct tdm_port port;
  2023. int ret = tdm_get_port_idx(kcontrol, &port);
  2024. if (ret) {
  2025. pr_err("%s: unsupported control: %s",
  2026. __func__, kcontrol->id.name);
  2027. } else {
  2028. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2029. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2030. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2031. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2032. ucontrol->value.enumerated.item[0]);
  2033. }
  2034. return ret;
  2035. }
  2036. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2037. struct snd_ctl_elem_value *ucontrol)
  2038. {
  2039. struct tdm_port port;
  2040. int ret = tdm_get_port_idx(kcontrol, &port);
  2041. if (ret) {
  2042. pr_err("%s: unsupported control: %s",
  2043. __func__, kcontrol->id.name);
  2044. } else {
  2045. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2046. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2047. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2048. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2049. ucontrol->value.enumerated.item[0]);
  2050. }
  2051. return ret;
  2052. }
  2053. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2054. struct snd_ctl_elem_value *ucontrol)
  2055. {
  2056. struct tdm_port port;
  2057. int ret = tdm_get_port_idx(kcontrol, &port);
  2058. if (ret) {
  2059. pr_err("%s: unsupported control: %s",
  2060. __func__, kcontrol->id.name);
  2061. } else {
  2062. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2063. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2064. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2065. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2066. ucontrol->value.enumerated.item[0]);
  2067. }
  2068. return ret;
  2069. }
  2070. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2071. struct snd_ctl_elem_value *ucontrol)
  2072. {
  2073. struct tdm_port port;
  2074. int ret = tdm_get_port_idx(kcontrol, &port);
  2075. if (ret) {
  2076. pr_err("%s: unsupported control: %s",
  2077. __func__, kcontrol->id.name);
  2078. } else {
  2079. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2080. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2081. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2082. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2083. ucontrol->value.enumerated.item[0]);
  2084. }
  2085. return ret;
  2086. }
  2087. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2088. struct snd_ctl_elem_value *ucontrol)
  2089. {
  2090. struct tdm_port port;
  2091. int ret = tdm_get_port_idx(kcontrol, &port);
  2092. if (ret) {
  2093. pr_err("%s: unsupported control: %s",
  2094. __func__, kcontrol->id.name);
  2095. } else {
  2096. ucontrol->value.enumerated.item[0] =
  2097. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2098. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2099. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2100. ucontrol->value.enumerated.item[0]);
  2101. }
  2102. return ret;
  2103. }
  2104. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2105. struct snd_ctl_elem_value *ucontrol)
  2106. {
  2107. struct tdm_port port;
  2108. int ret = tdm_get_port_idx(kcontrol, &port);
  2109. if (ret) {
  2110. pr_err("%s: unsupported control: %s",
  2111. __func__, kcontrol->id.name);
  2112. } else {
  2113. tdm_rx_cfg[port.mode][port.channel].channels =
  2114. ucontrol->value.enumerated.item[0] + 1;
  2115. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2116. tdm_rx_cfg[port.mode][port.channel].channels,
  2117. ucontrol->value.enumerated.item[0] + 1);
  2118. }
  2119. return ret;
  2120. }
  2121. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2122. struct snd_ctl_elem_value *ucontrol)
  2123. {
  2124. struct tdm_port port;
  2125. int ret = tdm_get_port_idx(kcontrol, &port);
  2126. if (ret) {
  2127. pr_err("%s: unsupported control: %s",
  2128. __func__, kcontrol->id.name);
  2129. } else {
  2130. ucontrol->value.enumerated.item[0] =
  2131. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2132. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2133. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2134. ucontrol->value.enumerated.item[0]);
  2135. }
  2136. return ret;
  2137. }
  2138. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2139. struct snd_ctl_elem_value *ucontrol)
  2140. {
  2141. struct tdm_port port;
  2142. int ret = tdm_get_port_idx(kcontrol, &port);
  2143. if (ret) {
  2144. pr_err("%s: unsupported control: %s",
  2145. __func__, kcontrol->id.name);
  2146. } else {
  2147. tdm_tx_cfg[port.mode][port.channel].channels =
  2148. ucontrol->value.enumerated.item[0] + 1;
  2149. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2150. tdm_tx_cfg[port.mode][port.channel].channels,
  2151. ucontrol->value.enumerated.item[0] + 1);
  2152. }
  2153. return ret;
  2154. }
  2155. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2156. {
  2157. int idx;
  2158. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2159. sizeof("PRIM_AUX_PCM")))
  2160. idx = PRIM_AUX_PCM;
  2161. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2162. sizeof("SEC_AUX_PCM")))
  2163. idx = SEC_AUX_PCM;
  2164. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2165. sizeof("TERT_AUX_PCM")))
  2166. idx = TERT_AUX_PCM;
  2167. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2168. sizeof("QUAT_AUX_PCM")))
  2169. idx = QUAT_AUX_PCM;
  2170. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2171. sizeof("QUIN_AUX_PCM")))
  2172. idx = QUIN_AUX_PCM;
  2173. else {
  2174. pr_err("%s: unsupported port: %s",
  2175. __func__, kcontrol->id.name);
  2176. idx = -EINVAL;
  2177. }
  2178. return idx;
  2179. }
  2180. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2181. struct snd_ctl_elem_value *ucontrol)
  2182. {
  2183. int idx = aux_pcm_get_port_idx(kcontrol);
  2184. if (idx < 0)
  2185. return idx;
  2186. aux_pcm_rx_cfg[idx].sample_rate =
  2187. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2188. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2189. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2190. ucontrol->value.enumerated.item[0]);
  2191. return 0;
  2192. }
  2193. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2194. struct snd_ctl_elem_value *ucontrol)
  2195. {
  2196. int idx = aux_pcm_get_port_idx(kcontrol);
  2197. if (idx < 0)
  2198. return idx;
  2199. ucontrol->value.enumerated.item[0] =
  2200. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2201. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2202. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2203. ucontrol->value.enumerated.item[0]);
  2204. return 0;
  2205. }
  2206. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2207. struct snd_ctl_elem_value *ucontrol)
  2208. {
  2209. int idx = aux_pcm_get_port_idx(kcontrol);
  2210. if (idx < 0)
  2211. return idx;
  2212. aux_pcm_tx_cfg[idx].sample_rate =
  2213. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2214. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2215. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2216. ucontrol->value.enumerated.item[0]);
  2217. return 0;
  2218. }
  2219. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2220. struct snd_ctl_elem_value *ucontrol)
  2221. {
  2222. int idx = aux_pcm_get_port_idx(kcontrol);
  2223. if (idx < 0)
  2224. return idx;
  2225. ucontrol->value.enumerated.item[0] =
  2226. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2227. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2228. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2229. ucontrol->value.enumerated.item[0]);
  2230. return 0;
  2231. }
  2232. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2233. {
  2234. int idx;
  2235. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2236. sizeof("PRIM_MI2S_RX")))
  2237. idx = PRIM_MI2S;
  2238. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2239. sizeof("SEC_MI2S_RX")))
  2240. idx = SEC_MI2S;
  2241. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2242. sizeof("TERT_MI2S_RX")))
  2243. idx = TERT_MI2S;
  2244. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2245. sizeof("QUAT_MI2S_RX")))
  2246. idx = QUAT_MI2S;
  2247. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2248. sizeof("QUIN_MI2S_RX")))
  2249. idx = QUIN_MI2S;
  2250. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2251. sizeof("PRIM_MI2S_TX")))
  2252. idx = PRIM_MI2S;
  2253. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2254. sizeof("SEC_MI2S_TX")))
  2255. idx = SEC_MI2S;
  2256. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2257. sizeof("TERT_MI2S_TX")))
  2258. idx = TERT_MI2S;
  2259. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2260. sizeof("QUAT_MI2S_TX")))
  2261. idx = QUAT_MI2S;
  2262. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2263. sizeof("QUIN_MI2S_TX")))
  2264. idx = QUIN_MI2S;
  2265. else {
  2266. pr_err("%s: unsupported channel: %s",
  2267. __func__, kcontrol->id.name);
  2268. idx = -EINVAL;
  2269. }
  2270. return idx;
  2271. }
  2272. static int mi2s_get_sample_rate_val(int sample_rate)
  2273. {
  2274. int sample_rate_val;
  2275. switch (sample_rate) {
  2276. case SAMPLING_RATE_8KHZ:
  2277. sample_rate_val = 0;
  2278. break;
  2279. case SAMPLING_RATE_11P025KHZ:
  2280. sample_rate_val = 1;
  2281. break;
  2282. case SAMPLING_RATE_16KHZ:
  2283. sample_rate_val = 2;
  2284. break;
  2285. case SAMPLING_RATE_22P05KHZ:
  2286. sample_rate_val = 3;
  2287. break;
  2288. case SAMPLING_RATE_32KHZ:
  2289. sample_rate_val = 4;
  2290. break;
  2291. case SAMPLING_RATE_44P1KHZ:
  2292. sample_rate_val = 5;
  2293. break;
  2294. case SAMPLING_RATE_48KHZ:
  2295. sample_rate_val = 6;
  2296. break;
  2297. case SAMPLING_RATE_96KHZ:
  2298. sample_rate_val = 7;
  2299. break;
  2300. case SAMPLING_RATE_192KHZ:
  2301. sample_rate_val = 8;
  2302. break;
  2303. default:
  2304. sample_rate_val = 6;
  2305. break;
  2306. }
  2307. return sample_rate_val;
  2308. }
  2309. static int mi2s_get_sample_rate(int value)
  2310. {
  2311. int sample_rate;
  2312. switch (value) {
  2313. case 0:
  2314. sample_rate = SAMPLING_RATE_8KHZ;
  2315. break;
  2316. case 1:
  2317. sample_rate = SAMPLING_RATE_11P025KHZ;
  2318. break;
  2319. case 2:
  2320. sample_rate = SAMPLING_RATE_16KHZ;
  2321. break;
  2322. case 3:
  2323. sample_rate = SAMPLING_RATE_22P05KHZ;
  2324. break;
  2325. case 4:
  2326. sample_rate = SAMPLING_RATE_32KHZ;
  2327. break;
  2328. case 5:
  2329. sample_rate = SAMPLING_RATE_44P1KHZ;
  2330. break;
  2331. case 6:
  2332. sample_rate = SAMPLING_RATE_48KHZ;
  2333. break;
  2334. case 7:
  2335. sample_rate = SAMPLING_RATE_96KHZ;
  2336. break;
  2337. case 8:
  2338. sample_rate = SAMPLING_RATE_192KHZ;
  2339. break;
  2340. default:
  2341. sample_rate = SAMPLING_RATE_48KHZ;
  2342. break;
  2343. }
  2344. return sample_rate;
  2345. }
  2346. static int mi2s_auxpcm_get_format(int value)
  2347. {
  2348. int format;
  2349. switch (value) {
  2350. case 0:
  2351. format = SNDRV_PCM_FORMAT_S16_LE;
  2352. break;
  2353. case 1:
  2354. format = SNDRV_PCM_FORMAT_S24_LE;
  2355. break;
  2356. case 2:
  2357. format = SNDRV_PCM_FORMAT_S24_3LE;
  2358. break;
  2359. case 3:
  2360. format = SNDRV_PCM_FORMAT_S32_LE;
  2361. break;
  2362. default:
  2363. format = SNDRV_PCM_FORMAT_S16_LE;
  2364. break;
  2365. }
  2366. return format;
  2367. }
  2368. static int mi2s_auxpcm_get_format_value(int format)
  2369. {
  2370. int value;
  2371. switch (format) {
  2372. case SNDRV_PCM_FORMAT_S16_LE:
  2373. value = 0;
  2374. break;
  2375. case SNDRV_PCM_FORMAT_S24_LE:
  2376. value = 1;
  2377. break;
  2378. case SNDRV_PCM_FORMAT_S24_3LE:
  2379. value = 2;
  2380. break;
  2381. case SNDRV_PCM_FORMAT_S32_LE:
  2382. value = 3;
  2383. break;
  2384. default:
  2385. value = 0;
  2386. break;
  2387. }
  2388. return value;
  2389. }
  2390. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2391. struct snd_ctl_elem_value *ucontrol)
  2392. {
  2393. int idx = mi2s_get_port_idx(kcontrol);
  2394. if (idx < 0)
  2395. return idx;
  2396. mi2s_rx_cfg[idx].sample_rate =
  2397. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2398. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2399. idx, mi2s_rx_cfg[idx].sample_rate,
  2400. ucontrol->value.enumerated.item[0]);
  2401. return 0;
  2402. }
  2403. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2404. struct snd_ctl_elem_value *ucontrol)
  2405. {
  2406. int idx = mi2s_get_port_idx(kcontrol);
  2407. if (idx < 0)
  2408. return idx;
  2409. ucontrol->value.enumerated.item[0] =
  2410. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2411. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2412. idx, mi2s_rx_cfg[idx].sample_rate,
  2413. ucontrol->value.enumerated.item[0]);
  2414. return 0;
  2415. }
  2416. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2417. struct snd_ctl_elem_value *ucontrol)
  2418. {
  2419. int idx = mi2s_get_port_idx(kcontrol);
  2420. if (idx < 0)
  2421. return idx;
  2422. mi2s_tx_cfg[idx].sample_rate =
  2423. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2424. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2425. idx, mi2s_tx_cfg[idx].sample_rate,
  2426. ucontrol->value.enumerated.item[0]);
  2427. return 0;
  2428. }
  2429. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2430. struct snd_ctl_elem_value *ucontrol)
  2431. {
  2432. int idx = mi2s_get_port_idx(kcontrol);
  2433. if (idx < 0)
  2434. return idx;
  2435. ucontrol->value.enumerated.item[0] =
  2436. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2437. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2438. idx, mi2s_tx_cfg[idx].sample_rate,
  2439. ucontrol->value.enumerated.item[0]);
  2440. return 0;
  2441. }
  2442. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2443. struct snd_ctl_elem_value *ucontrol)
  2444. {
  2445. int idx = mi2s_get_port_idx(kcontrol);
  2446. if (idx < 0)
  2447. return idx;
  2448. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2449. idx, mi2s_rx_cfg[idx].channels);
  2450. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2451. return 0;
  2452. }
  2453. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2454. struct snd_ctl_elem_value *ucontrol)
  2455. {
  2456. int idx = mi2s_get_port_idx(kcontrol);
  2457. if (idx < 0)
  2458. return idx;
  2459. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2460. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2461. idx, mi2s_rx_cfg[idx].channels);
  2462. return 1;
  2463. }
  2464. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2465. struct snd_ctl_elem_value *ucontrol)
  2466. {
  2467. int idx = mi2s_get_port_idx(kcontrol);
  2468. if (idx < 0)
  2469. return idx;
  2470. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2471. idx, mi2s_tx_cfg[idx].channels);
  2472. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2473. return 0;
  2474. }
  2475. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2476. struct snd_ctl_elem_value *ucontrol)
  2477. {
  2478. int idx = mi2s_get_port_idx(kcontrol);
  2479. if (idx < 0)
  2480. return idx;
  2481. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2482. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2483. idx, mi2s_tx_cfg[idx].channels);
  2484. return 1;
  2485. }
  2486. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2487. struct snd_ctl_elem_value *ucontrol)
  2488. {
  2489. int idx = mi2s_get_port_idx(kcontrol);
  2490. if (idx < 0)
  2491. return idx;
  2492. ucontrol->value.enumerated.item[0] =
  2493. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2494. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2495. idx, mi2s_rx_cfg[idx].bit_format,
  2496. ucontrol->value.enumerated.item[0]);
  2497. return 0;
  2498. }
  2499. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2500. struct snd_ctl_elem_value *ucontrol)
  2501. {
  2502. int idx = mi2s_get_port_idx(kcontrol);
  2503. if (idx < 0)
  2504. return idx;
  2505. mi2s_rx_cfg[idx].bit_format =
  2506. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2507. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2508. idx, mi2s_rx_cfg[idx].bit_format,
  2509. ucontrol->value.enumerated.item[0]);
  2510. return 0;
  2511. }
  2512. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2513. struct snd_ctl_elem_value *ucontrol)
  2514. {
  2515. int idx = mi2s_get_port_idx(kcontrol);
  2516. if (idx < 0)
  2517. return idx;
  2518. ucontrol->value.enumerated.item[0] =
  2519. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2520. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2521. idx, mi2s_tx_cfg[idx].bit_format,
  2522. ucontrol->value.enumerated.item[0]);
  2523. return 0;
  2524. }
  2525. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2526. struct snd_ctl_elem_value *ucontrol)
  2527. {
  2528. int idx = mi2s_get_port_idx(kcontrol);
  2529. if (idx < 0)
  2530. return idx;
  2531. mi2s_tx_cfg[idx].bit_format =
  2532. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2533. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2534. idx, mi2s_tx_cfg[idx].bit_format,
  2535. ucontrol->value.enumerated.item[0]);
  2536. return 0;
  2537. }
  2538. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2539. struct snd_ctl_elem_value *ucontrol)
  2540. {
  2541. int idx = aux_pcm_get_port_idx(kcontrol);
  2542. if (idx < 0)
  2543. return idx;
  2544. ucontrol->value.enumerated.item[0] =
  2545. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2546. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2547. idx, aux_pcm_rx_cfg[idx].bit_format,
  2548. ucontrol->value.enumerated.item[0]);
  2549. return 0;
  2550. }
  2551. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2552. struct snd_ctl_elem_value *ucontrol)
  2553. {
  2554. int idx = aux_pcm_get_port_idx(kcontrol);
  2555. if (idx < 0)
  2556. return idx;
  2557. aux_pcm_rx_cfg[idx].bit_format =
  2558. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2559. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2560. idx, aux_pcm_rx_cfg[idx].bit_format,
  2561. ucontrol->value.enumerated.item[0]);
  2562. return 0;
  2563. }
  2564. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2565. struct snd_ctl_elem_value *ucontrol)
  2566. {
  2567. int idx = aux_pcm_get_port_idx(kcontrol);
  2568. if (idx < 0)
  2569. return idx;
  2570. ucontrol->value.enumerated.item[0] =
  2571. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2572. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2573. idx, aux_pcm_tx_cfg[idx].bit_format,
  2574. ucontrol->value.enumerated.item[0]);
  2575. return 0;
  2576. }
  2577. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2578. struct snd_ctl_elem_value *ucontrol)
  2579. {
  2580. int idx = aux_pcm_get_port_idx(kcontrol);
  2581. if (idx < 0)
  2582. return idx;
  2583. aux_pcm_tx_cfg[idx].bit_format =
  2584. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2585. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2586. idx, aux_pcm_tx_cfg[idx].bit_format,
  2587. ucontrol->value.enumerated.item[0]);
  2588. return 0;
  2589. }
  2590. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2591. {
  2592. int idx;
  2593. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2594. sizeof("PRIM_SPDIF_RX")))
  2595. idx = PRIM_SPDIF_RX;
  2596. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2597. sizeof("SEC_SPDIF_RX")))
  2598. idx = SEC_SPDIF_RX;
  2599. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2600. sizeof("PRIM_SPDIF_TX")))
  2601. idx = PRIM_SPDIF_TX;
  2602. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2603. sizeof("SEC_SPDIF_TX")))
  2604. idx = SEC_SPDIF_TX;
  2605. else {
  2606. pr_err("%s: unsupported channel: %s",
  2607. __func__, kcontrol->id.name);
  2608. idx = -EINVAL;
  2609. }
  2610. return idx;
  2611. }
  2612. static int spdif_get_sample_rate_val(int sample_rate)
  2613. {
  2614. int sample_rate_val;
  2615. switch (sample_rate) {
  2616. case SAMPLING_RATE_32KHZ:
  2617. sample_rate_val = 0;
  2618. break;
  2619. case SAMPLING_RATE_44P1KHZ:
  2620. sample_rate_val = 1;
  2621. break;
  2622. case SAMPLING_RATE_48KHZ:
  2623. sample_rate_val = 2;
  2624. break;
  2625. case SAMPLING_RATE_88P2KHZ:
  2626. sample_rate_val = 3;
  2627. break;
  2628. case SAMPLING_RATE_96KHZ:
  2629. sample_rate_val = 4;
  2630. break;
  2631. case SAMPLING_RATE_176P4KHZ:
  2632. sample_rate_val = 5;
  2633. break;
  2634. case SAMPLING_RATE_192KHZ:
  2635. sample_rate_val = 6;
  2636. break;
  2637. default:
  2638. sample_rate_val = 2;
  2639. break;
  2640. }
  2641. return sample_rate_val;
  2642. }
  2643. static int spdif_get_sample_rate(int value)
  2644. {
  2645. int sample_rate;
  2646. switch (value) {
  2647. case 0:
  2648. sample_rate = SAMPLING_RATE_32KHZ;
  2649. break;
  2650. case 1:
  2651. sample_rate = SAMPLING_RATE_44P1KHZ;
  2652. break;
  2653. case 2:
  2654. sample_rate = SAMPLING_RATE_48KHZ;
  2655. break;
  2656. case 3:
  2657. sample_rate = SAMPLING_RATE_88P2KHZ;
  2658. break;
  2659. case 4:
  2660. sample_rate = SAMPLING_RATE_96KHZ;
  2661. break;
  2662. case 5:
  2663. sample_rate = SAMPLING_RATE_176P4KHZ;
  2664. break;
  2665. case 6:
  2666. sample_rate = SAMPLING_RATE_192KHZ;
  2667. break;
  2668. default:
  2669. sample_rate = SAMPLING_RATE_48KHZ;
  2670. break;
  2671. }
  2672. return sample_rate;
  2673. }
  2674. static int spdif_get_format(int value)
  2675. {
  2676. int format;
  2677. switch (value) {
  2678. case 0:
  2679. format = SNDRV_PCM_FORMAT_S16_LE;
  2680. break;
  2681. case 1:
  2682. format = SNDRV_PCM_FORMAT_S24_LE;
  2683. break;
  2684. default:
  2685. format = SNDRV_PCM_FORMAT_S16_LE;
  2686. break;
  2687. }
  2688. return format;
  2689. }
  2690. static int spdif_get_format_value(int format)
  2691. {
  2692. int value;
  2693. switch (format) {
  2694. case SNDRV_PCM_FORMAT_S16_LE:
  2695. value = 0;
  2696. break;
  2697. case SNDRV_PCM_FORMAT_S24_LE:
  2698. value = 1;
  2699. break;
  2700. default:
  2701. value = 0;
  2702. break;
  2703. }
  2704. return value;
  2705. }
  2706. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2707. struct snd_ctl_elem_value *ucontrol)
  2708. {
  2709. int idx = spdif_get_port_idx(kcontrol);
  2710. if (idx < 0)
  2711. return idx;
  2712. spdif_rx_cfg[idx].sample_rate =
  2713. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2714. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2715. idx, spdif_rx_cfg[idx].sample_rate,
  2716. ucontrol->value.enumerated.item[0]);
  2717. return 0;
  2718. }
  2719. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2720. struct snd_ctl_elem_value *ucontrol)
  2721. {
  2722. int idx = spdif_get_port_idx(kcontrol);
  2723. if (idx < 0)
  2724. return idx;
  2725. ucontrol->value.enumerated.item[0] =
  2726. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2727. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2728. idx, spdif_rx_cfg[idx].sample_rate,
  2729. ucontrol->value.enumerated.item[0]);
  2730. return 0;
  2731. }
  2732. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2733. struct snd_ctl_elem_value *ucontrol)
  2734. {
  2735. int idx = spdif_get_port_idx(kcontrol);
  2736. if (idx < 0)
  2737. return idx;
  2738. spdif_tx_cfg[idx].sample_rate =
  2739. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2740. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2741. idx, spdif_tx_cfg[idx].sample_rate,
  2742. ucontrol->value.enumerated.item[0]);
  2743. return 0;
  2744. }
  2745. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2746. struct snd_ctl_elem_value *ucontrol)
  2747. {
  2748. int idx = spdif_get_port_idx(kcontrol);
  2749. if (idx < 0)
  2750. return idx;
  2751. ucontrol->value.enumerated.item[0] =
  2752. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2753. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2754. idx, spdif_tx_cfg[idx].sample_rate,
  2755. ucontrol->value.enumerated.item[0]);
  2756. return 0;
  2757. }
  2758. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2759. struct snd_ctl_elem_value *ucontrol)
  2760. {
  2761. int idx = spdif_get_port_idx(kcontrol);
  2762. if (idx < 0)
  2763. return idx;
  2764. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2765. idx, spdif_rx_cfg[idx].channels);
  2766. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2767. return 0;
  2768. }
  2769. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2770. struct snd_ctl_elem_value *ucontrol)
  2771. {
  2772. int idx = spdif_get_port_idx(kcontrol);
  2773. if (idx < 0)
  2774. return idx;
  2775. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2776. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2777. idx, spdif_rx_cfg[idx].channels);
  2778. return 1;
  2779. }
  2780. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2781. struct snd_ctl_elem_value *ucontrol)
  2782. {
  2783. int idx = spdif_get_port_idx(kcontrol);
  2784. if (idx < 0)
  2785. return idx;
  2786. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2787. idx, spdif_tx_cfg[idx].channels);
  2788. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2789. return 0;
  2790. }
  2791. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2792. struct snd_ctl_elem_value *ucontrol)
  2793. {
  2794. int idx = spdif_get_port_idx(kcontrol);
  2795. if (idx < 0)
  2796. return idx;
  2797. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2798. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2799. idx, spdif_tx_cfg[idx].channels);
  2800. return 1;
  2801. }
  2802. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2803. struct snd_ctl_elem_value *ucontrol)
  2804. {
  2805. int idx = spdif_get_port_idx(kcontrol);
  2806. if (idx < 0)
  2807. return idx;
  2808. ucontrol->value.enumerated.item[0] =
  2809. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2810. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2811. idx, spdif_rx_cfg[idx].bit_format,
  2812. ucontrol->value.enumerated.item[0]);
  2813. return 0;
  2814. }
  2815. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2816. struct snd_ctl_elem_value *ucontrol)
  2817. {
  2818. int idx = spdif_get_port_idx(kcontrol);
  2819. if (idx < 0)
  2820. return idx;
  2821. spdif_rx_cfg[idx].bit_format =
  2822. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2823. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2824. idx, spdif_rx_cfg[idx].bit_format,
  2825. ucontrol->value.enumerated.item[0]);
  2826. return 0;
  2827. }
  2828. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2829. struct snd_ctl_elem_value *ucontrol)
  2830. {
  2831. int idx = spdif_get_port_idx(kcontrol);
  2832. if (idx < 0)
  2833. return idx;
  2834. ucontrol->value.enumerated.item[0] =
  2835. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2836. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2837. idx, spdif_tx_cfg[idx].bit_format,
  2838. ucontrol->value.enumerated.item[0]);
  2839. return 0;
  2840. }
  2841. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2842. struct snd_ctl_elem_value *ucontrol)
  2843. {
  2844. int idx = spdif_get_port_idx(kcontrol);
  2845. if (idx < 0)
  2846. return idx;
  2847. spdif_tx_cfg[idx].bit_format =
  2848. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2849. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2850. idx, spdif_tx_cfg[idx].bit_format,
  2851. ucontrol->value.enumerated.item[0]);
  2852. return 0;
  2853. }
  2854. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2855. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2856. slim_rx_ch_get, slim_rx_ch_put),
  2857. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2858. slim_rx_ch_get, slim_rx_ch_put),
  2859. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2860. slim_tx_ch_get, slim_tx_ch_put),
  2861. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2862. slim_tx_ch_get, slim_tx_ch_put),
  2863. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2864. slim_rx_ch_get, slim_rx_ch_put),
  2865. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2866. slim_rx_ch_get, slim_rx_ch_put),
  2867. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2868. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2869. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2870. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2871. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2872. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2873. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2874. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2875. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2876. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2877. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2878. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2879. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2880. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2881. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2882. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2883. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2884. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2885. };
  2886. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2887. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2888. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2889. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2890. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2891. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2892. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2893. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2894. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2895. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2896. va_cdc_dma_tx_0_sample_rate,
  2897. cdc_dma_tx_sample_rate_get,
  2898. cdc_dma_tx_sample_rate_put),
  2899. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2900. va_cdc_dma_tx_1_sample_rate,
  2901. cdc_dma_tx_sample_rate_get,
  2902. cdc_dma_tx_sample_rate_put),
  2903. };
  2904. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2905. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2906. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2907. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2908. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2909. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2910. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2911. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2912. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2913. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2914. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2915. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2916. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2917. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2918. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2919. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2920. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2921. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2922. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2923. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2924. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2925. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2926. wsa_cdc_dma_rx_0_sample_rate,
  2927. cdc_dma_rx_sample_rate_get,
  2928. cdc_dma_rx_sample_rate_put),
  2929. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2930. wsa_cdc_dma_rx_1_sample_rate,
  2931. cdc_dma_rx_sample_rate_get,
  2932. cdc_dma_rx_sample_rate_put),
  2933. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2934. wsa_cdc_dma_tx_0_sample_rate,
  2935. cdc_dma_tx_sample_rate_get,
  2936. cdc_dma_tx_sample_rate_put),
  2937. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2938. wsa_cdc_dma_tx_1_sample_rate,
  2939. cdc_dma_tx_sample_rate_get,
  2940. cdc_dma_tx_sample_rate_put),
  2941. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2942. wsa_cdc_dma_tx_2_sample_rate,
  2943. cdc_dma_tx_sample_rate_get,
  2944. cdc_dma_tx_sample_rate_put),
  2945. };
  2946. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2947. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2948. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2949. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2950. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2951. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2952. proxy_rx_ch_get, proxy_rx_ch_put),
  2953. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2954. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2955. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2956. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2957. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2958. msm_bt_sample_rate_get,
  2959. msm_bt_sample_rate_put),
  2960. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2961. usb_audio_rx_sample_rate_get,
  2962. usb_audio_rx_sample_rate_put),
  2963. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2964. usb_audio_tx_sample_rate_get,
  2965. usb_audio_tx_sample_rate_put),
  2966. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2967. tdm_rx_sample_rate_get,
  2968. tdm_rx_sample_rate_put),
  2969. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2970. tdm_tx_sample_rate_get,
  2971. tdm_tx_sample_rate_put),
  2972. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2973. tdm_rx_format_get,
  2974. tdm_rx_format_put),
  2975. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2976. tdm_tx_format_get,
  2977. tdm_tx_format_put),
  2978. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2979. tdm_rx_ch_get,
  2980. tdm_rx_ch_put),
  2981. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2982. tdm_tx_ch_get,
  2983. tdm_tx_ch_put),
  2984. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2985. tdm_rx_sample_rate_get,
  2986. tdm_rx_sample_rate_put),
  2987. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2988. tdm_tx_sample_rate_get,
  2989. tdm_tx_sample_rate_put),
  2990. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2991. tdm_rx_format_get,
  2992. tdm_rx_format_put),
  2993. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2994. tdm_tx_format_get,
  2995. tdm_tx_format_put),
  2996. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2997. tdm_rx_ch_get,
  2998. tdm_rx_ch_put),
  2999. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3000. tdm_tx_ch_get,
  3001. tdm_tx_ch_put),
  3002. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3003. tdm_rx_sample_rate_get,
  3004. tdm_rx_sample_rate_put),
  3005. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3006. tdm_tx_sample_rate_get,
  3007. tdm_tx_sample_rate_put),
  3008. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3009. tdm_rx_format_get,
  3010. tdm_rx_format_put),
  3011. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3012. tdm_tx_format_get,
  3013. tdm_tx_format_put),
  3014. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3015. tdm_rx_ch_get,
  3016. tdm_rx_ch_put),
  3017. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3018. tdm_tx_ch_get,
  3019. tdm_tx_ch_put),
  3020. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3021. tdm_rx_sample_rate_get,
  3022. tdm_rx_sample_rate_put),
  3023. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3024. tdm_tx_sample_rate_get,
  3025. tdm_tx_sample_rate_put),
  3026. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3027. tdm_rx_format_get,
  3028. tdm_rx_format_put),
  3029. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3030. tdm_tx_format_get,
  3031. tdm_tx_format_put),
  3032. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3033. tdm_rx_ch_get,
  3034. tdm_rx_ch_put),
  3035. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3036. tdm_tx_ch_get,
  3037. tdm_tx_ch_put),
  3038. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3039. tdm_rx_sample_rate_get,
  3040. tdm_rx_sample_rate_put),
  3041. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3042. tdm_tx_sample_rate_get,
  3043. tdm_tx_sample_rate_put),
  3044. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3045. tdm_rx_format_get,
  3046. tdm_rx_format_put),
  3047. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3048. tdm_tx_format_get,
  3049. tdm_tx_format_put),
  3050. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3051. tdm_rx_ch_get,
  3052. tdm_rx_ch_put),
  3053. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3054. tdm_tx_ch_get,
  3055. tdm_tx_ch_put),
  3056. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3057. aux_pcm_rx_sample_rate_get,
  3058. aux_pcm_rx_sample_rate_put),
  3059. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3060. aux_pcm_rx_sample_rate_get,
  3061. aux_pcm_rx_sample_rate_put),
  3062. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3063. aux_pcm_rx_sample_rate_get,
  3064. aux_pcm_rx_sample_rate_put),
  3065. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3066. aux_pcm_rx_sample_rate_get,
  3067. aux_pcm_rx_sample_rate_put),
  3068. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3069. aux_pcm_rx_sample_rate_get,
  3070. aux_pcm_rx_sample_rate_put),
  3071. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3072. aux_pcm_tx_sample_rate_get,
  3073. aux_pcm_tx_sample_rate_put),
  3074. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3075. aux_pcm_tx_sample_rate_get,
  3076. aux_pcm_tx_sample_rate_put),
  3077. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3078. aux_pcm_tx_sample_rate_get,
  3079. aux_pcm_tx_sample_rate_put),
  3080. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3081. aux_pcm_tx_sample_rate_get,
  3082. aux_pcm_tx_sample_rate_put),
  3083. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3084. aux_pcm_tx_sample_rate_get,
  3085. aux_pcm_tx_sample_rate_put),
  3086. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3087. mi2s_rx_sample_rate_get,
  3088. mi2s_rx_sample_rate_put),
  3089. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3090. mi2s_rx_sample_rate_get,
  3091. mi2s_rx_sample_rate_put),
  3092. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3093. mi2s_rx_sample_rate_get,
  3094. mi2s_rx_sample_rate_put),
  3095. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3096. mi2s_rx_sample_rate_get,
  3097. mi2s_rx_sample_rate_put),
  3098. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3099. mi2s_rx_sample_rate_get,
  3100. mi2s_rx_sample_rate_put),
  3101. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3102. mi2s_tx_sample_rate_get,
  3103. mi2s_tx_sample_rate_put),
  3104. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3105. mi2s_tx_sample_rate_get,
  3106. mi2s_tx_sample_rate_put),
  3107. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3108. mi2s_tx_sample_rate_get,
  3109. mi2s_tx_sample_rate_put),
  3110. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3111. mi2s_tx_sample_rate_get,
  3112. mi2s_tx_sample_rate_put),
  3113. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3114. mi2s_tx_sample_rate_get,
  3115. mi2s_tx_sample_rate_put),
  3116. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3117. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3118. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3119. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3120. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3121. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3122. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3123. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3124. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3125. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3126. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3127. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3128. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3129. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3130. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3131. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3132. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3133. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3134. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3135. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3136. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3137. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3138. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3139. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3140. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3141. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3142. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3143. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3144. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3145. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3146. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3147. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3148. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3149. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3150. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3151. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3152. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3153. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3154. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3155. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3156. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3157. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3158. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3159. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3160. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3161. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3162. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3163. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3164. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3165. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3166. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3167. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3168. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3169. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3170. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3171. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3172. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3173. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3174. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3175. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3176. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3177. msm_snd_vad_cfg_put),
  3178. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3179. msm_spdif_rx_sample_rate_get,
  3180. msm_spdif_rx_sample_rate_put),
  3181. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3182. msm_spdif_tx_sample_rate_get,
  3183. msm_spdif_tx_sample_rate_put),
  3184. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3185. msm_spdif_rx_sample_rate_get,
  3186. msm_spdif_rx_sample_rate_put),
  3187. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3188. msm_spdif_tx_sample_rate_get,
  3189. msm_spdif_tx_sample_rate_put),
  3190. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3191. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3192. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3193. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3194. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3195. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3196. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3197. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3198. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3199. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3200. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3201. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3202. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3203. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3204. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3205. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3206. };
  3207. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  3208. int enable, bool dapm)
  3209. {
  3210. int ret = 0;
  3211. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3212. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  3213. } else {
  3214. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  3215. __func__);
  3216. ret = -EINVAL;
  3217. }
  3218. return ret;
  3219. }
  3220. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  3221. int enable, bool dapm)
  3222. {
  3223. int ret = 0;
  3224. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3225. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  3226. } else {
  3227. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  3228. __func__);
  3229. ret = -EINVAL;
  3230. }
  3231. return ret;
  3232. }
  3233. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3234. struct snd_kcontrol *kcontrol, int event)
  3235. {
  3236. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3237. pr_debug("%s: event = %d\n", __func__, event);
  3238. switch (event) {
  3239. case SND_SOC_DAPM_PRE_PMU:
  3240. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  3241. case SND_SOC_DAPM_POST_PMD:
  3242. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  3243. }
  3244. return 0;
  3245. }
  3246. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3247. struct snd_kcontrol *kcontrol, int event)
  3248. {
  3249. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3250. pr_debug("%s: event = %d\n", __func__, event);
  3251. switch (event) {
  3252. case SND_SOC_DAPM_PRE_PMU:
  3253. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  3254. case SND_SOC_DAPM_POST_PMD:
  3255. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  3256. }
  3257. return 0;
  3258. }
  3259. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3260. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3261. msm_mclk_event,
  3262. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3263. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3264. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3265. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3266. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3267. };
  3268. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3269. struct snd_kcontrol *kcontrol, int event)
  3270. {
  3271. struct msm_asoc_mach_data *pdata = NULL;
  3272. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3273. int ret = 0;
  3274. uint32_t dmic_idx;
  3275. int *dmic_gpio_cnt;
  3276. struct device_node *dmic_gpio;
  3277. char *wname;
  3278. wname = strpbrk(w->name, "01234567");
  3279. if (!wname) {
  3280. dev_err(codec->dev, "%s: widget not found\n", __func__);
  3281. return -EINVAL;
  3282. }
  3283. ret = kstrtouint(wname, 10, &dmic_idx);
  3284. if (ret < 0) {
  3285. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  3286. __func__);
  3287. return -EINVAL;
  3288. }
  3289. pdata = snd_soc_card_get_drvdata(codec->component.card);
  3290. switch (dmic_idx) {
  3291. case 0:
  3292. case 1:
  3293. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3294. dmic_gpio = pdata->dmic_01_gpio_p;
  3295. break;
  3296. case 2:
  3297. case 3:
  3298. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3299. dmic_gpio = pdata->dmic_23_gpio_p;
  3300. break;
  3301. case 4:
  3302. case 5:
  3303. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3304. dmic_gpio = pdata->dmic_45_gpio_p;
  3305. break;
  3306. case 6:
  3307. case 7:
  3308. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3309. dmic_gpio = pdata->dmic_67_gpio_p;
  3310. break;
  3311. default:
  3312. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  3313. __func__);
  3314. return -EINVAL;
  3315. }
  3316. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3317. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3318. switch (event) {
  3319. case SND_SOC_DAPM_PRE_PMU:
  3320. (*dmic_gpio_cnt)++;
  3321. if (*dmic_gpio_cnt == 1) {
  3322. ret = msm_cdc_pinctrl_select_active_state(
  3323. dmic_gpio);
  3324. if (ret < 0) {
  3325. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  3326. __func__, "dmic_gpio");
  3327. return ret;
  3328. }
  3329. }
  3330. break;
  3331. case SND_SOC_DAPM_POST_PMD:
  3332. (*dmic_gpio_cnt)--;
  3333. if (*dmic_gpio_cnt == 0) {
  3334. ret = msm_cdc_pinctrl_select_sleep_state(
  3335. dmic_gpio);
  3336. if (ret < 0) {
  3337. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  3338. __func__, "dmic_gpio");
  3339. return ret;
  3340. }
  3341. }
  3342. break;
  3343. default:
  3344. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3345. __func__, event);
  3346. return -EINVAL;
  3347. }
  3348. return 0;
  3349. }
  3350. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3351. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3352. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3353. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3354. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3355. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3356. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3357. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3358. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3359. };
  3360. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3361. };
  3362. static inline int param_is_mask(int p)
  3363. {
  3364. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3365. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3366. }
  3367. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3368. int n)
  3369. {
  3370. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3371. }
  3372. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3373. unsigned int bit)
  3374. {
  3375. if (bit >= SNDRV_MASK_MAX)
  3376. return;
  3377. if (param_is_mask(n)) {
  3378. struct snd_mask *m = param_to_mask(p, n);
  3379. m->bits[0] = 0;
  3380. m->bits[1] = 0;
  3381. m->bits[bit >> 5] |= (1 << (bit & 31));
  3382. }
  3383. }
  3384. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3385. {
  3386. int ch_id = 0;
  3387. switch (be_id) {
  3388. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3389. ch_id = SLIM_RX_0;
  3390. break;
  3391. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3392. ch_id = SLIM_RX_1;
  3393. break;
  3394. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3395. ch_id = SLIM_RX_2;
  3396. break;
  3397. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3398. ch_id = SLIM_RX_3;
  3399. break;
  3400. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3401. ch_id = SLIM_RX_4;
  3402. break;
  3403. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3404. ch_id = SLIM_RX_6;
  3405. break;
  3406. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3407. ch_id = SLIM_TX_0;
  3408. break;
  3409. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3410. ch_id = SLIM_TX_3;
  3411. break;
  3412. default:
  3413. ch_id = SLIM_RX_0;
  3414. break;
  3415. }
  3416. return ch_id;
  3417. }
  3418. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3419. {
  3420. *port_id = 0xFFFF;
  3421. switch (be_id) {
  3422. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3423. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3424. break;
  3425. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3426. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3427. break;
  3428. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3429. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3430. break;
  3431. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3432. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3433. break;
  3434. default:
  3435. return -EINVAL;
  3436. }
  3437. return 0;
  3438. }
  3439. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3440. {
  3441. int idx = 0;
  3442. switch (be_id) {
  3443. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3444. idx = WSA_CDC_DMA_RX_0;
  3445. break;
  3446. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3447. idx = WSA_CDC_DMA_TX_0;
  3448. break;
  3449. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3450. idx = WSA_CDC_DMA_RX_1;
  3451. break;
  3452. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3453. idx = WSA_CDC_DMA_TX_1;
  3454. break;
  3455. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3456. idx = WSA_CDC_DMA_TX_2;
  3457. break;
  3458. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3459. idx = VA_CDC_DMA_TX_0;
  3460. break;
  3461. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3462. idx = VA_CDC_DMA_TX_1;
  3463. break;
  3464. default:
  3465. idx = VA_CDC_DMA_TX_0;
  3466. break;
  3467. }
  3468. return idx;
  3469. }
  3470. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3471. struct snd_pcm_hw_params *params)
  3472. {
  3473. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3474. struct snd_interval *rate = hw_param_interval(params,
  3475. SNDRV_PCM_HW_PARAM_RATE);
  3476. struct snd_interval *channels = hw_param_interval(params,
  3477. SNDRV_PCM_HW_PARAM_CHANNELS);
  3478. int rc = 0;
  3479. int idx;
  3480. void *config = NULL;
  3481. struct snd_soc_codec *codec = NULL;
  3482. pr_debug("%s: format = %d, rate = %d\n",
  3483. __func__, params_format(params), params_rate(params));
  3484. switch (dai_link->id) {
  3485. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3486. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3487. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3488. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3489. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3490. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3491. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3492. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3493. slim_rx_cfg[idx].bit_format);
  3494. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3495. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3496. break;
  3497. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3498. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3499. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3500. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3501. slim_tx_cfg[idx].bit_format);
  3502. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3503. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3504. break;
  3505. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3506. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3507. slim_tx_cfg[1].bit_format);
  3508. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3509. channels->min = channels->max = slim_tx_cfg[1].channels;
  3510. break;
  3511. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3512. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3513. SNDRV_PCM_FORMAT_S32_LE);
  3514. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3515. channels->min = channels->max = msm_vi_feed_tx_ch;
  3516. break;
  3517. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3518. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3519. slim_rx_cfg[5].bit_format);
  3520. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3521. channels->min = channels->max = slim_rx_cfg[5].channels;
  3522. break;
  3523. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3524. codec = rtd->codec;
  3525. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3526. channels->min = channels->max = 1;
  3527. config = msm_codec_fn.get_afe_config_fn(codec,
  3528. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3529. if (config) {
  3530. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3531. config, SLIMBUS_5_TX);
  3532. if (rc)
  3533. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3534. __func__, rc);
  3535. }
  3536. break;
  3537. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3538. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3539. slim_rx_cfg[SLIM_RX_7].bit_format);
  3540. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3541. channels->min = channels->max =
  3542. slim_rx_cfg[SLIM_RX_7].channels;
  3543. break;
  3544. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3545. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3546. channels->min = channels->max =
  3547. slim_tx_cfg[SLIM_TX_7].channels;
  3548. break;
  3549. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3550. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3551. channels->min = channels->max =
  3552. slim_tx_cfg[SLIM_TX_8].channels;
  3553. break;
  3554. case MSM_BACKEND_DAI_USB_RX:
  3555. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3556. usb_rx_cfg.bit_format);
  3557. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3558. channels->min = channels->max = usb_rx_cfg.channels;
  3559. break;
  3560. case MSM_BACKEND_DAI_USB_TX:
  3561. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3562. usb_tx_cfg.bit_format);
  3563. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3564. channels->min = channels->max = usb_tx_cfg.channels;
  3565. break;
  3566. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3567. channels->min = channels->max = proxy_rx_cfg.channels;
  3568. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3569. break;
  3570. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3571. channels->min = channels->max =
  3572. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3573. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3574. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3575. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3576. break;
  3577. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3578. channels->min = channels->max =
  3579. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3580. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3581. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3582. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3583. break;
  3584. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3585. channels->min = channels->max =
  3586. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3587. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3588. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3589. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3590. break;
  3591. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3592. channels->min = channels->max =
  3593. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3594. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3595. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3596. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3597. break;
  3598. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3599. channels->min = channels->max =
  3600. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3601. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3602. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3603. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3604. break;
  3605. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3606. channels->min = channels->max =
  3607. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3608. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3609. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3610. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3611. break;
  3612. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3613. channels->min = channels->max =
  3614. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3615. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3616. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3617. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3618. break;
  3619. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3620. channels->min = channels->max =
  3621. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3622. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3623. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3624. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3625. break;
  3626. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3627. channels->min = channels->max =
  3628. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3629. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3630. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3631. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3632. break;
  3633. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3634. channels->min = channels->max =
  3635. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3636. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3637. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3638. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3639. break;
  3640. case MSM_BACKEND_DAI_AUXPCM_RX:
  3641. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3642. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3643. rate->min = rate->max =
  3644. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3645. channels->min = channels->max =
  3646. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3647. break;
  3648. case MSM_BACKEND_DAI_AUXPCM_TX:
  3649. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3650. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3651. rate->min = rate->max =
  3652. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3653. channels->min = channels->max =
  3654. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3655. break;
  3656. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3657. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3658. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3659. rate->min = rate->max =
  3660. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3661. channels->min = channels->max =
  3662. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3663. break;
  3664. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3665. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3666. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3667. rate->min = rate->max =
  3668. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3669. channels->min = channels->max =
  3670. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3671. break;
  3672. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3673. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3674. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3675. rate->min = rate->max =
  3676. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3677. channels->min = channels->max =
  3678. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3679. break;
  3680. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3681. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3682. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3683. rate->min = rate->max =
  3684. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3685. channels->min = channels->max =
  3686. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3687. break;
  3688. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3689. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3690. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3691. rate->min = rate->max =
  3692. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3693. channels->min = channels->max =
  3694. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3695. break;
  3696. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3697. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3698. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3699. rate->min = rate->max =
  3700. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3701. channels->min = channels->max =
  3702. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3703. break;
  3704. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3705. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3706. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3707. rate->min = rate->max =
  3708. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3709. channels->min = channels->max =
  3710. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3711. break;
  3712. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3713. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3714. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3715. rate->min = rate->max =
  3716. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3717. channels->min = channels->max =
  3718. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3719. break;
  3720. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3721. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3722. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3723. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3724. channels->min = channels->max =
  3725. mi2s_rx_cfg[PRIM_MI2S].channels;
  3726. break;
  3727. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3728. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3729. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3730. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3731. channels->min = channels->max =
  3732. mi2s_tx_cfg[PRIM_MI2S].channels;
  3733. break;
  3734. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3735. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3736. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3737. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3738. channels->min = channels->max =
  3739. mi2s_rx_cfg[SEC_MI2S].channels;
  3740. break;
  3741. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3742. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3743. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3744. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3745. channels->min = channels->max =
  3746. mi2s_tx_cfg[SEC_MI2S].channels;
  3747. break;
  3748. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3749. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3750. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3751. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3752. channels->min = channels->max =
  3753. mi2s_rx_cfg[TERT_MI2S].channels;
  3754. break;
  3755. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3756. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3757. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3758. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3759. channels->min = channels->max =
  3760. mi2s_tx_cfg[TERT_MI2S].channels;
  3761. break;
  3762. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3763. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3764. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3765. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3766. channels->min = channels->max =
  3767. mi2s_rx_cfg[QUAT_MI2S].channels;
  3768. break;
  3769. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3770. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3771. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3772. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3773. channels->min = channels->max =
  3774. mi2s_tx_cfg[QUAT_MI2S].channels;
  3775. break;
  3776. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3777. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3778. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3779. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3780. channels->min = channels->max =
  3781. mi2s_rx_cfg[QUIN_MI2S].channels;
  3782. break;
  3783. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3784. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3785. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3786. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3787. channels->min = channels->max =
  3788. mi2s_tx_cfg[QUIN_MI2S].channels;
  3789. break;
  3790. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3791. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3792. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3793. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3794. cdc_dma_rx_cfg[idx].bit_format);
  3795. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3796. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3797. break;
  3798. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3799. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3800. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3801. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3802. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3803. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3804. cdc_dma_tx_cfg[idx].bit_format);
  3805. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3806. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3807. break;
  3808. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3809. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3810. SNDRV_PCM_FORMAT_S32_LE);
  3811. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3812. channels->min = channels->max = msm_vi_feed_tx_ch;
  3813. break;
  3814. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  3815. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3816. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  3817. rate->min = rate->max =
  3818. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  3819. channels->min = channels->max =
  3820. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  3821. break;
  3822. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  3823. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3824. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  3825. rate->min = rate->max =
  3826. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  3827. channels->min = channels->max =
  3828. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  3829. break;
  3830. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  3831. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3832. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  3833. rate->min = rate->max =
  3834. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  3835. channels->min = channels->max =
  3836. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  3837. break;
  3838. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  3839. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3840. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  3841. rate->min = rate->max =
  3842. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  3843. channels->min = channels->max =
  3844. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  3845. break;
  3846. default:
  3847. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3848. break;
  3849. }
  3850. return rc;
  3851. }
  3852. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3853. {
  3854. int ret = 0;
  3855. void *config_data = NULL;
  3856. if (!msm_codec_fn.get_afe_config_fn) {
  3857. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3858. __func__);
  3859. return -EINVAL;
  3860. }
  3861. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3862. AFE_CDC_REGISTERS_CONFIG);
  3863. if (config_data) {
  3864. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3865. if (ret) {
  3866. dev_err(codec->dev,
  3867. "%s: Failed to set codec registers config %d\n",
  3868. __func__, ret);
  3869. return ret;
  3870. }
  3871. }
  3872. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3873. AFE_CDC_REGISTER_PAGE_CONFIG);
  3874. if (config_data) {
  3875. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3876. 0);
  3877. if (ret)
  3878. dev_err(codec->dev,
  3879. "%s: Failed to set cdc register page config\n",
  3880. __func__);
  3881. }
  3882. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3883. AFE_SLIMBUS_SLAVE_CONFIG);
  3884. if (config_data) {
  3885. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3886. if (ret) {
  3887. dev_err(codec->dev,
  3888. "%s: Failed to set slimbus slave config %d\n",
  3889. __func__, ret);
  3890. return ret;
  3891. }
  3892. }
  3893. return 0;
  3894. }
  3895. static void msm_afe_clear_config(void)
  3896. {
  3897. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3898. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3899. }
  3900. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3901. struct snd_card *card)
  3902. {
  3903. int ret = 0;
  3904. unsigned long timeout;
  3905. int adsp_ready = 0;
  3906. bool snd_card_online = 0;
  3907. timeout = jiffies +
  3908. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3909. do {
  3910. if (!snd_card_online) {
  3911. snd_card_online = snd_card_is_online_state(card);
  3912. pr_debug("%s: Sound card is %s\n", __func__,
  3913. snd_card_online ? "Online" : "Offline");
  3914. }
  3915. if (!adsp_ready) {
  3916. adsp_ready = q6core_is_adsp_ready();
  3917. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3918. adsp_ready ? "ready" : "not ready");
  3919. }
  3920. if (snd_card_online && adsp_ready)
  3921. break;
  3922. /*
  3923. * Sound card/ADSP will be coming up after subsystem restart and
  3924. * it might not be fully up when the control reaches
  3925. * here. So, wait for 50msec before checking ADSP state
  3926. */
  3927. msleep(50);
  3928. } while (time_after(timeout, jiffies));
  3929. if (!snd_card_online || !adsp_ready) {
  3930. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3931. __func__,
  3932. snd_card_online ? "Online" : "Offline",
  3933. adsp_ready ? "ready" : "not ready");
  3934. ret = -ETIMEDOUT;
  3935. goto err;
  3936. }
  3937. ret = msm_afe_set_config(codec);
  3938. if (ret)
  3939. pr_err("%s: Failed to set AFE config. err %d\n",
  3940. __func__, ret);
  3941. return 0;
  3942. err:
  3943. return ret;
  3944. }
  3945. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3946. unsigned long opcode, void *ptr)
  3947. {
  3948. int ret;
  3949. struct snd_soc_card *card = NULL;
  3950. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3951. struct snd_soc_pcm_runtime *rtd;
  3952. struct snd_soc_codec *codec;
  3953. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3954. switch (opcode) {
  3955. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3956. /*
  3957. * Use flag to ignore initial boot notifications
  3958. * On initial boot msm_adsp_power_up_config is
  3959. * called on init. There is no need to clear
  3960. * and set the config again on initial boot.
  3961. */
  3962. if (is_initial_boot)
  3963. break;
  3964. msm_afe_clear_config();
  3965. break;
  3966. case AUDIO_NOTIFIER_SERVICE_UP:
  3967. if (is_initial_boot) {
  3968. is_initial_boot = false;
  3969. break;
  3970. }
  3971. if (!spdev)
  3972. return -EINVAL;
  3973. card = platform_get_drvdata(spdev);
  3974. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3975. if (!rtd) {
  3976. dev_err(card->dev,
  3977. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3978. __func__, be_dl_name);
  3979. ret = -EINVAL;
  3980. goto err;
  3981. }
  3982. codec = rtd->codec;
  3983. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3984. if (ret < 0) {
  3985. dev_err(card->dev,
  3986. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3987. __func__, ret);
  3988. goto err;
  3989. }
  3990. break;
  3991. default:
  3992. break;
  3993. }
  3994. err:
  3995. return NOTIFY_OK;
  3996. }
  3997. static struct notifier_block service_nb = {
  3998. .notifier_call = qcs405_notifier_service_cb,
  3999. .priority = -INT_MAX,
  4000. };
  4001. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4002. {
  4003. int ret = 0;
  4004. void *config_data;
  4005. struct snd_soc_codec *codec = rtd->codec;
  4006. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4007. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4008. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4009. struct snd_card *card;
  4010. struct msm_asoc_mach_data *pdata =
  4011. snd_soc_card_get_drvdata(rtd->card);
  4012. /*
  4013. * Codec SLIMBUS configuration
  4014. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4015. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4016. * TX14, TX15, TX16
  4017. */
  4018. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4019. 151, 152, 153, 154, 155, 156};
  4020. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4021. 134, 135, 136, 137, 138, 139,
  4022. 140, 141, 142, 143};
  4023. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4024. rtd->pmdown_time = 0;
  4025. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  4026. ARRAY_SIZE(msm_snd_sb_controls));
  4027. if (ret < 0) {
  4028. pr_err("%s: add_codec_controls failed, err %d\n",
  4029. __func__, ret);
  4030. return ret;
  4031. }
  4032. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4033. ARRAY_SIZE(msm_dapm_widgets));
  4034. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4035. ARRAY_SIZE(wcd_audio_paths));
  4036. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4037. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4038. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4039. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4040. snd_soc_dapm_sync(dapm);
  4041. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4042. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4043. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4044. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  4045. if (ret) {
  4046. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  4047. __func__, ret);
  4048. goto err;
  4049. }
  4050. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4051. AFE_AANC_VERSION);
  4052. if (config_data) {
  4053. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4054. if (ret) {
  4055. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  4056. __func__, ret);
  4057. goto err;
  4058. }
  4059. }
  4060. card = rtd->card->snd_card;
  4061. if (!pdata->codec_root)
  4062. pdata->codec_root = snd_info_create_subdir(card->module,
  4063. "codecs", card->proc_root);
  4064. if (!pdata->codec_root) {
  4065. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4066. __func__);
  4067. ret = 0;
  4068. goto err;
  4069. }
  4070. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  4071. codec_reg_done = true;
  4072. return 0;
  4073. err:
  4074. return ret;
  4075. }
  4076. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4077. {
  4078. int ret = 0;
  4079. struct snd_soc_codec *codec = rtd->codec;
  4080. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4081. struct snd_card *card;
  4082. struct msm_asoc_mach_data *pdata =
  4083. snd_soc_card_get_drvdata(rtd->card);
  4084. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  4085. ARRAY_SIZE(msm_snd_va_controls));
  4086. if (ret < 0) {
  4087. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  4088. __func__, ret);
  4089. return ret;
  4090. }
  4091. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4092. ARRAY_SIZE(msm_va_dapm_widgets));
  4093. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4094. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4095. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4096. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4097. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4098. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4099. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4100. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4101. snd_soc_dapm_sync(dapm);
  4102. card = rtd->card->snd_card;
  4103. if (!pdata->codec_root)
  4104. pdata->codec_root = snd_info_create_subdir(card->module,
  4105. "codecs", card->proc_root);
  4106. if (!pdata->codec_root) {
  4107. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4108. __func__);
  4109. ret = 0;
  4110. goto done;
  4111. }
  4112. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4113. done:
  4114. return ret;
  4115. }
  4116. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4117. {
  4118. int ret = 0;
  4119. struct snd_soc_codec *codec = rtd->codec;
  4120. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4121. struct snd_soc_component *aux_comp;
  4122. struct snd_card *card;
  4123. struct msm_asoc_mach_data *pdata =
  4124. snd_soc_card_get_drvdata(rtd->card);
  4125. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  4126. ARRAY_SIZE(msm_snd_wsa_controls));
  4127. if (ret < 0) {
  4128. dev_err(codec->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4129. __func__, ret);
  4130. return ret;
  4131. }
  4132. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4133. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4134. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4135. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4136. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4137. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4138. snd_soc_dapm_sync(dapm);
  4139. /*
  4140. * Send speaker configuration only for WSA8810.
  4141. * Default configuration is for WSA8815.
  4142. */
  4143. dev_dbg(codec->dev, "%s: Number of aux devices: %d\n",
  4144. __func__, rtd->card->num_aux_devs);
  4145. if (rtd->card->num_aux_devs &&
  4146. !list_empty(&rtd->card->component_dev_list)) {
  4147. aux_comp = list_first_entry(
  4148. &rtd->card->component_dev_list,
  4149. struct snd_soc_component,
  4150. card_aux_list);
  4151. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4152. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4153. wsa_macro_set_spkr_mode(rtd->codec,
  4154. WSA_MACRO_SPKR_MODE_1);
  4155. wsa_macro_set_spkr_gain_offset(rtd->codec,
  4156. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4157. }
  4158. }
  4159. card = rtd->card->snd_card;
  4160. if (!pdata->codec_root)
  4161. pdata->codec_root = snd_info_create_subdir(card->module,
  4162. "codecs", card->proc_root);
  4163. if (!pdata->codec_root) {
  4164. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4165. __func__);
  4166. ret = 0;
  4167. goto done;
  4168. }
  4169. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4170. done:
  4171. return ret;
  4172. }
  4173. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4174. {
  4175. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4176. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  4177. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4178. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4179. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4180. }
  4181. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4182. struct snd_pcm_hw_params *params)
  4183. {
  4184. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4185. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4186. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4187. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4188. int ret = 0;
  4189. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4190. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4191. u32 user_set_tx_ch = 0;
  4192. u32 rx_ch_count;
  4193. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4194. ret = snd_soc_dai_get_channel_map(codec_dai,
  4195. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4196. if (ret < 0) {
  4197. pr_err("%s: failed to get codec chan map, err:%d\n",
  4198. __func__, ret);
  4199. goto err;
  4200. }
  4201. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4202. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4203. slim_rx_cfg[5].channels);
  4204. rx_ch_count = slim_rx_cfg[5].channels;
  4205. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4206. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4207. slim_rx_cfg[2].channels);
  4208. rx_ch_count = slim_rx_cfg[2].channels;
  4209. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4210. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4211. slim_rx_cfg[6].channels);
  4212. rx_ch_count = slim_rx_cfg[6].channels;
  4213. } else {
  4214. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4215. slim_rx_cfg[0].channels);
  4216. rx_ch_count = slim_rx_cfg[0].channels;
  4217. }
  4218. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4219. rx_ch_count, rx_ch);
  4220. if (ret < 0) {
  4221. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4222. __func__, ret);
  4223. goto err;
  4224. }
  4225. } else {
  4226. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4227. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4228. ret = snd_soc_dai_get_channel_map(codec_dai,
  4229. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4230. if (ret < 0) {
  4231. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4232. __func__, ret);
  4233. goto err;
  4234. }
  4235. /* For <codec>_tx1 case */
  4236. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4237. user_set_tx_ch = slim_tx_cfg[0].channels;
  4238. /* For <codec>_tx3 case */
  4239. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4240. user_set_tx_ch = slim_tx_cfg[1].channels;
  4241. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4242. user_set_tx_ch = msm_vi_feed_tx_ch;
  4243. else
  4244. user_set_tx_ch = tx_ch_cnt;
  4245. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4246. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4247. tx_ch_cnt, dai_link->id);
  4248. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4249. user_set_tx_ch, tx_ch, 0, 0);
  4250. if (ret < 0)
  4251. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4252. __func__, ret);
  4253. }
  4254. err:
  4255. return ret;
  4256. }
  4257. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4258. struct snd_pcm_hw_params *params)
  4259. {
  4260. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4261. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4262. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4263. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4264. int ret = 0;
  4265. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4266. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4267. u32 user_set_tx_ch = 0;
  4268. u32 user_set_rx_ch = 0;
  4269. u32 ch_id;
  4270. ret = snd_soc_dai_get_channel_map(codec_dai,
  4271. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4272. &rx_ch_cdc_dma);
  4273. if (ret < 0) {
  4274. pr_err("%s: failed to get codec chan map, err:%d\n",
  4275. __func__, ret);
  4276. goto err;
  4277. }
  4278. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4279. switch (dai_link->id) {
  4280. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4281. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4282. {
  4283. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4284. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4285. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4286. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4287. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4288. user_set_rx_ch, &rx_ch_cdc_dma);
  4289. if (ret < 0) {
  4290. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4291. __func__, ret);
  4292. goto err;
  4293. }
  4294. }
  4295. break;
  4296. }
  4297. } else {
  4298. switch (dai_link->id) {
  4299. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4300. {
  4301. user_set_tx_ch = msm_vi_feed_tx_ch;
  4302. }
  4303. break;
  4304. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4305. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4306. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4307. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4308. {
  4309. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4310. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4311. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4312. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4313. }
  4314. break;
  4315. }
  4316. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4317. &tx_ch_cdc_dma, 0, 0);
  4318. if (ret < 0) {
  4319. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4320. __func__, ret);
  4321. goto err;
  4322. }
  4323. }
  4324. err:
  4325. return ret;
  4326. }
  4327. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4328. struct snd_pcm_hw_params *params)
  4329. {
  4330. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4331. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4332. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4333. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4334. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4335. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4336. int ret;
  4337. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4338. codec_dai->name, codec_dai->id);
  4339. ret = snd_soc_dai_get_channel_map(codec_dai,
  4340. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4341. if (ret) {
  4342. dev_err(rtd->dev,
  4343. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4344. __func__, ret);
  4345. goto err;
  4346. }
  4347. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4348. __func__, tx_ch_cnt, dai_link->id);
  4349. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4350. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4351. if (ret)
  4352. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4353. __func__, ret);
  4354. err:
  4355. return ret;
  4356. }
  4357. static int msm_get_port_id(int be_id)
  4358. {
  4359. int afe_port_id;
  4360. switch (be_id) {
  4361. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4362. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4363. break;
  4364. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4365. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4366. break;
  4367. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4368. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4369. break;
  4370. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4371. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4372. break;
  4373. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4374. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4375. break;
  4376. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4377. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4378. break;
  4379. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4380. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4381. break;
  4382. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4383. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4384. break;
  4385. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4386. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4387. break;
  4388. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4389. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4390. break;
  4391. default:
  4392. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4393. afe_port_id = -EINVAL;
  4394. }
  4395. return afe_port_id;
  4396. }
  4397. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4398. {
  4399. u32 bit_per_sample;
  4400. switch (bit_format) {
  4401. case SNDRV_PCM_FORMAT_S32_LE:
  4402. case SNDRV_PCM_FORMAT_S24_3LE:
  4403. case SNDRV_PCM_FORMAT_S24_LE:
  4404. bit_per_sample = 32;
  4405. break;
  4406. case SNDRV_PCM_FORMAT_S16_LE:
  4407. default:
  4408. bit_per_sample = 16;
  4409. break;
  4410. }
  4411. return bit_per_sample;
  4412. }
  4413. static void update_mi2s_clk_val(int dai_id, int stream)
  4414. {
  4415. u32 bit_per_sample;
  4416. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4417. bit_per_sample =
  4418. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4419. mi2s_clk[dai_id].clk_freq_in_hz =
  4420. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4421. } else {
  4422. bit_per_sample =
  4423. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4424. mi2s_clk[dai_id].clk_freq_in_hz =
  4425. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4426. }
  4427. }
  4428. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4429. {
  4430. int ret = 0;
  4431. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4432. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4433. int port_id = 0;
  4434. int index = cpu_dai->id;
  4435. port_id = msm_get_port_id(rtd->dai_link->id);
  4436. if (port_id < 0) {
  4437. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4438. ret = port_id;
  4439. goto err;
  4440. }
  4441. if (enable) {
  4442. update_mi2s_clk_val(index, substream->stream);
  4443. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4444. mi2s_clk[index].clk_freq_in_hz);
  4445. }
  4446. mi2s_clk[index].enable = enable;
  4447. ret = afe_set_lpass_clock_v2(port_id,
  4448. &mi2s_clk[index]);
  4449. if (ret < 0) {
  4450. dev_err(rtd->card->dev,
  4451. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4452. __func__, port_id, ret);
  4453. goto err;
  4454. }
  4455. err:
  4456. return ret;
  4457. }
  4458. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4459. enum pinctrl_pin_state new_state)
  4460. {
  4461. int ret = 0;
  4462. int curr_state = 0;
  4463. if (pinctrl_info == NULL) {
  4464. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4465. ret = -EINVAL;
  4466. goto err;
  4467. }
  4468. if (pinctrl_info->pinctrl == NULL) {
  4469. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4470. ret = -EINVAL;
  4471. goto err;
  4472. }
  4473. curr_state = pinctrl_info->curr_state;
  4474. pinctrl_info->curr_state = new_state;
  4475. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4476. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4477. if (curr_state == pinctrl_info->curr_state) {
  4478. pr_debug("%s: Already in same state\n", __func__);
  4479. goto err;
  4480. }
  4481. if (curr_state != STATE_DISABLE &&
  4482. pinctrl_info->curr_state != STATE_DISABLE) {
  4483. pr_debug("%s: state already active cannot switch\n", __func__);
  4484. ret = -EIO;
  4485. goto err;
  4486. }
  4487. switch (pinctrl_info->curr_state) {
  4488. case STATE_MI2S_ACTIVE:
  4489. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4490. pinctrl_info->mi2s_active);
  4491. if (ret) {
  4492. pr_err("%s: MI2S state select failed with %d\n",
  4493. __func__, ret);
  4494. ret = -EIO;
  4495. goto err;
  4496. }
  4497. break;
  4498. case STATE_TDM_ACTIVE:
  4499. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4500. pinctrl_info->tdm_active);
  4501. if (ret) {
  4502. pr_err("%s: TDM state select failed with %d\n",
  4503. __func__, ret);
  4504. ret = -EIO;
  4505. goto err;
  4506. }
  4507. break;
  4508. case STATE_DISABLE:
  4509. if (curr_state == STATE_MI2S_ACTIVE) {
  4510. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4511. pinctrl_info->mi2s_disable);
  4512. } else {
  4513. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4514. pinctrl_info->tdm_disable);
  4515. }
  4516. if (ret) {
  4517. pr_err("%s: state disable failed with %d\n",
  4518. __func__, ret);
  4519. ret = -EIO;
  4520. goto err;
  4521. }
  4522. break;
  4523. default:
  4524. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4525. return -EINVAL;
  4526. }
  4527. err:
  4528. return ret;
  4529. }
  4530. static void msm_release_pinctrl(struct platform_device *pdev)
  4531. {
  4532. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4533. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4534. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4535. if (pinctrl_info->pinctrl) {
  4536. devm_pinctrl_put(pinctrl_info->pinctrl);
  4537. pinctrl_info->pinctrl = NULL;
  4538. }
  4539. }
  4540. static int msm_get_pinctrl(struct platform_device *pdev)
  4541. {
  4542. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4543. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4544. struct msm_pinctrl_info *pinctrl_info = NULL;
  4545. struct pinctrl *pinctrl;
  4546. int ret;
  4547. pinctrl_info = &pdata->pinctrl_info;
  4548. if (pinctrl_info == NULL) {
  4549. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4550. return -EINVAL;
  4551. }
  4552. pinctrl = devm_pinctrl_get(&pdev->dev);
  4553. if (IS_ERR_OR_NULL(pinctrl)) {
  4554. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4555. return -EINVAL;
  4556. }
  4557. pinctrl_info->pinctrl = pinctrl;
  4558. /* get all the states handles from Device Tree */
  4559. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4560. "quat-mi2s-sleep");
  4561. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4562. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4563. goto err;
  4564. }
  4565. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4566. "quat-mi2s-active");
  4567. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4568. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4569. goto err;
  4570. }
  4571. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4572. "quat-tdm-sleep");
  4573. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4574. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4575. goto err;
  4576. }
  4577. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4578. "quat-tdm-active");
  4579. if (IS_ERR(pinctrl_info->tdm_active)) {
  4580. pr_err("%s: could not get tdm_active pinstate\n",
  4581. __func__);
  4582. goto err;
  4583. }
  4584. /* Reset the TLMM pins to a default state */
  4585. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4586. pinctrl_info->mi2s_disable);
  4587. if (ret != 0) {
  4588. pr_err("%s: Disable TLMM pins failed with %d\n",
  4589. __func__, ret);
  4590. ret = -EIO;
  4591. goto err;
  4592. }
  4593. pinctrl_info->curr_state = STATE_DISABLE;
  4594. return 0;
  4595. err:
  4596. devm_pinctrl_put(pinctrl);
  4597. pinctrl_info->pinctrl = NULL;
  4598. return -EINVAL;
  4599. }
  4600. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4601. struct snd_pcm_hw_params *params)
  4602. {
  4603. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4604. struct snd_interval *rate = hw_param_interval(params,
  4605. SNDRV_PCM_HW_PARAM_RATE);
  4606. struct snd_interval *channels = hw_param_interval(params,
  4607. SNDRV_PCM_HW_PARAM_CHANNELS);
  4608. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4609. channels->min = channels->max =
  4610. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4611. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4612. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4613. rate->min = rate->max =
  4614. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4615. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4616. channels->min = channels->max =
  4617. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4618. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4619. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4620. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4621. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4622. channels->min = channels->max =
  4623. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4624. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4625. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4626. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4627. } else {
  4628. pr_err("%s: dai id 0x%x not supported\n",
  4629. __func__, cpu_dai->id);
  4630. return -EINVAL;
  4631. }
  4632. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4633. __func__, cpu_dai->id, channels->max, rate->max,
  4634. params_format(params));
  4635. return 0;
  4636. }
  4637. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4638. struct snd_pcm_hw_params *params)
  4639. {
  4640. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4641. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4642. int ret = 0;
  4643. int slot_width = 32;
  4644. int channels, slots;
  4645. unsigned int slot_mask, rate, clk_freq;
  4646. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4647. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4648. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4649. switch (cpu_dai->id) {
  4650. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4651. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4652. break;
  4653. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4654. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4655. break;
  4656. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4657. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4658. break;
  4659. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4660. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4661. break;
  4662. case AFE_PORT_ID_QUINARY_TDM_RX:
  4663. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4664. break;
  4665. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4666. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4667. break;
  4668. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4669. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4670. break;
  4671. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4672. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4673. break;
  4674. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4675. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4676. break;
  4677. case AFE_PORT_ID_QUINARY_TDM_TX:
  4678. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4679. break;
  4680. default:
  4681. pr_err("%s: dai id 0x%x not supported\n",
  4682. __func__, cpu_dai->id);
  4683. return -EINVAL;
  4684. }
  4685. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4686. /*2 slot config - bits 0 and 1 set for the first two slots */
  4687. slot_mask = 0x0000FFFF >> (16-slots);
  4688. channels = slots;
  4689. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4690. __func__, slot_width, slots);
  4691. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4692. slots, slot_width);
  4693. if (ret < 0) {
  4694. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4695. __func__, ret);
  4696. goto end;
  4697. }
  4698. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4699. 0, NULL, channels, slot_offset);
  4700. if (ret < 0) {
  4701. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4702. __func__, ret);
  4703. goto end;
  4704. }
  4705. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4706. /*2 slot config - bits 0 and 1 set for the first two slots */
  4707. slot_mask = 0x0000FFFF >> (16-slots);
  4708. channels = slots;
  4709. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4710. __func__, slot_width, slots);
  4711. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4712. slots, slot_width);
  4713. if (ret < 0) {
  4714. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4715. __func__, ret);
  4716. goto end;
  4717. }
  4718. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4719. channels, slot_offset, 0, NULL);
  4720. if (ret < 0) {
  4721. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4722. __func__, ret);
  4723. goto end;
  4724. }
  4725. } else {
  4726. ret = -EINVAL;
  4727. pr_err("%s: invalid use case, err:%d\n",
  4728. __func__, ret);
  4729. goto end;
  4730. }
  4731. rate = params_rate(params);
  4732. clk_freq = rate * slot_width * slots;
  4733. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4734. if (ret < 0)
  4735. pr_err("%s: failed to set tdm clk, err:%d\n",
  4736. __func__, ret);
  4737. end:
  4738. return ret;
  4739. }
  4740. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4741. {
  4742. int ret = 0;
  4743. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4744. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4745. struct snd_soc_card *card = rtd->card;
  4746. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4747. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4748. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4749. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4750. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4751. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4752. if (ret)
  4753. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4754. __func__, ret);
  4755. }
  4756. return ret;
  4757. }
  4758. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4759. {
  4760. int ret = 0;
  4761. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4762. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4763. struct snd_soc_card *card = rtd->card;
  4764. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4765. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4766. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4767. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4768. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4769. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4770. if (ret)
  4771. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4772. __func__, ret);
  4773. }
  4774. }
  4775. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4776. .hw_params = qcs405_tdm_snd_hw_params,
  4777. .startup = qcs405_tdm_snd_startup,
  4778. .shutdown = qcs405_tdm_snd_shutdown
  4779. };
  4780. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4781. {
  4782. cpumask_t mask;
  4783. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4784. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4785. cpumask_clear(&mask);
  4786. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4787. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4788. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4789. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4790. pm_qos_add_request(&substream->latency_pm_qos_req,
  4791. PM_QOS_CPU_DMA_LATENCY,
  4792. MSM_LL_QOS_VALUE);
  4793. return 0;
  4794. }
  4795. static struct snd_soc_ops msm_fe_qos_ops = {
  4796. .prepare = msm_fe_qos_prepare,
  4797. };
  4798. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4799. {
  4800. int ret = 0;
  4801. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4802. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4803. int index = cpu_dai->id;
  4804. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4805. struct snd_soc_card *card = rtd->card;
  4806. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4807. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4808. int ret_pinctrl = 0;
  4809. dev_dbg(rtd->card->dev,
  4810. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4811. __func__, substream->name, substream->stream,
  4812. cpu_dai->name, cpu_dai->id);
  4813. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4814. ret = -EINVAL;
  4815. dev_err(rtd->card->dev,
  4816. "%s: CPU DAI id (%d) out of range\n",
  4817. __func__, cpu_dai->id);
  4818. goto err;
  4819. }
  4820. /*
  4821. * Mutex protection in case the same MI2S
  4822. * interface using for both TX and RX so
  4823. * that the same clock won't be enable twice.
  4824. */
  4825. mutex_lock(&mi2s_intf_conf[index].lock);
  4826. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4827. /* Check if msm needs to provide the clock to the interface */
  4828. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4829. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4830. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4831. }
  4832. ret = msm_mi2s_set_sclk(substream, true);
  4833. if (ret < 0) {
  4834. dev_err(rtd->card->dev,
  4835. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4836. __func__, ret);
  4837. goto clean_up;
  4838. }
  4839. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4840. if (ret < 0) {
  4841. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4842. __func__, index, ret);
  4843. goto clk_off;
  4844. }
  4845. if (index == QUAT_MI2S) {
  4846. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4847. STATE_MI2S_ACTIVE);
  4848. if (ret_pinctrl)
  4849. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4850. __func__, ret_pinctrl);
  4851. }
  4852. }
  4853. clk_off:
  4854. if (ret < 0)
  4855. msm_mi2s_set_sclk(substream, false);
  4856. clean_up:
  4857. if (ret < 0)
  4858. mi2s_intf_conf[index].ref_cnt--;
  4859. mutex_unlock(&mi2s_intf_conf[index].lock);
  4860. err:
  4861. return ret;
  4862. }
  4863. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4864. {
  4865. int ret;
  4866. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4867. int index = rtd->cpu_dai->id;
  4868. struct snd_soc_card *card = rtd->card;
  4869. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4870. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4871. int ret_pinctrl = 0;
  4872. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4873. substream->name, substream->stream);
  4874. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4875. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4876. return;
  4877. }
  4878. mutex_lock(&mi2s_intf_conf[index].lock);
  4879. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4880. ret = msm_mi2s_set_sclk(substream, false);
  4881. if (ret < 0)
  4882. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4883. __func__, index, ret);
  4884. if (index == QUAT_MI2S) {
  4885. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4886. STATE_DISABLE);
  4887. if (ret_pinctrl)
  4888. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4889. __func__, ret_pinctrl);
  4890. }
  4891. }
  4892. mutex_unlock(&mi2s_intf_conf[index].lock);
  4893. }
  4894. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  4895. {
  4896. int ret = 0;
  4897. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4898. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4899. int port_id = cpu_dai->id;
  4900. struct afe_clk_set clk_cfg;
  4901. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  4902. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  4903. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  4904. clk_cfg.enable = enable;
  4905. /* Set core clock (based on sample rate for RX, fixed for TX) */
  4906. switch (port_id) {
  4907. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4908. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  4909. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  4910. clk_cfg.clk_freq_in_hz =
  4911. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4912. break;
  4913. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4914. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  4915. clk_cfg.clk_freq_in_hz =
  4916. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4917. break;
  4918. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  4919. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  4920. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_204_P8_MHZ;
  4921. break;
  4922. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  4923. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  4924. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_204_P8_MHZ;
  4925. break;
  4926. }
  4927. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4928. if (ret < 0) {
  4929. dev_err(rtd->card->dev,
  4930. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4931. __func__, port_id, ret);
  4932. goto err;
  4933. }
  4934. /* Set NPL clock for RX in addition */
  4935. switch (port_id) {
  4936. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4937. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  4938. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4939. if (ret < 0) {
  4940. dev_err(rtd->card->dev,
  4941. "%s: afe NPL failed port 0x%x, err:%d\n",
  4942. __func__, port_id, ret);
  4943. goto err;
  4944. }
  4945. break;
  4946. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4947. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  4948. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4949. if (ret < 0) {
  4950. dev_err(rtd->card->dev,
  4951. "%s: afe NPL failed for port 0x%x, err:%d\n",
  4952. __func__, port_id, ret);
  4953. goto err;
  4954. }
  4955. break;
  4956. }
  4957. if (enable) {
  4958. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4959. clk_cfg.clk_freq_in_hz);
  4960. }
  4961. err:
  4962. return ret;
  4963. }
  4964. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  4965. {
  4966. int ret = 0;
  4967. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4968. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4969. int port_id = cpu_dai->id;
  4970. dev_dbg(rtd->card->dev,
  4971. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4972. __func__, substream->name, substream->stream,
  4973. cpu_dai->name, cpu_dai->id);
  4974. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  4975. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  4976. ret = -EINVAL;
  4977. dev_err(rtd->card->dev,
  4978. "%s: CPU DAI id (%d) out of range\n",
  4979. __func__, cpu_dai->id);
  4980. goto err;
  4981. }
  4982. ret = msm_spdif_set_clk(substream, true);
  4983. if (ret < 0) {
  4984. dev_err(rtd->card->dev,
  4985. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  4986. __func__, port_id, ret);
  4987. }
  4988. err:
  4989. return ret;
  4990. }
  4991. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  4992. {
  4993. int ret;
  4994. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4995. int port_id = rtd->cpu_dai->id;
  4996. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4997. substream->name, substream->stream);
  4998. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  4999. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5000. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  5001. return;
  5002. }
  5003. ret = msm_spdif_set_clk(substream, false);
  5004. if (ret < 0)
  5005. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  5006. __func__, port_id, ret);
  5007. }
  5008. static struct snd_soc_ops msm_mi2s_be_ops = {
  5009. .startup = msm_mi2s_snd_startup,
  5010. .shutdown = msm_mi2s_snd_shutdown,
  5011. };
  5012. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5013. .hw_params = msm_snd_cdc_dma_hw_params,
  5014. };
  5015. static struct snd_soc_ops msm_be_ops = {
  5016. .hw_params = msm_snd_hw_params,
  5017. };
  5018. static struct snd_soc_ops msm_wcn_ops = {
  5019. .hw_params = msm_wcn_hw_params,
  5020. };
  5021. static struct snd_soc_ops msm_spdif_be_ops = {
  5022. .startup = msm_spdif_snd_startup,
  5023. .shutdown = msm_spdif_snd_shutdown,
  5024. };
  5025. /* Digital audio interface glue - connects codec <---> CPU */
  5026. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5027. /* FrontEnd DAI Links */
  5028. {
  5029. .name = MSM_DAILINK_NAME(Media1),
  5030. .stream_name = "MultiMedia1",
  5031. .cpu_dai_name = "MultiMedia1",
  5032. .platform_name = "msm-pcm-dsp.0",
  5033. .dynamic = 1,
  5034. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5035. .dpcm_playback = 1,
  5036. .dpcm_capture = 1,
  5037. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5038. SND_SOC_DPCM_TRIGGER_POST},
  5039. .codec_dai_name = "snd-soc-dummy-dai",
  5040. .codec_name = "snd-soc-dummy",
  5041. .ignore_suspend = 1,
  5042. /* this dainlink has playback support */
  5043. .ignore_pmdown_time = 1,
  5044. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5045. },
  5046. {
  5047. .name = MSM_DAILINK_NAME(Media2),
  5048. .stream_name = "MultiMedia2",
  5049. .cpu_dai_name = "MultiMedia2",
  5050. .platform_name = "msm-pcm-dsp.0",
  5051. .dynamic = 1,
  5052. .dpcm_playback = 1,
  5053. .dpcm_capture = 1,
  5054. .codec_dai_name = "snd-soc-dummy-dai",
  5055. .codec_name = "snd-soc-dummy",
  5056. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5057. SND_SOC_DPCM_TRIGGER_POST},
  5058. .ignore_suspend = 1,
  5059. /* this dainlink has playback support */
  5060. .ignore_pmdown_time = 1,
  5061. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5062. },
  5063. {
  5064. .name = "VoiceMMode1",
  5065. .stream_name = "VoiceMMode1",
  5066. .cpu_dai_name = "VoiceMMode1",
  5067. .platform_name = "msm-pcm-voice",
  5068. .dynamic = 1,
  5069. .dpcm_playback = 1,
  5070. .dpcm_capture = 1,
  5071. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5072. SND_SOC_DPCM_TRIGGER_POST},
  5073. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5074. .ignore_suspend = 1,
  5075. .ignore_pmdown_time = 1,
  5076. .codec_dai_name = "snd-soc-dummy-dai",
  5077. .codec_name = "snd-soc-dummy",
  5078. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5079. },
  5080. {
  5081. .name = "MSM VoIP",
  5082. .stream_name = "VoIP",
  5083. .cpu_dai_name = "VoIP",
  5084. .platform_name = "msm-voip-dsp",
  5085. .dynamic = 1,
  5086. .dpcm_playback = 1,
  5087. .dpcm_capture = 1,
  5088. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5089. SND_SOC_DPCM_TRIGGER_POST},
  5090. .codec_dai_name = "snd-soc-dummy-dai",
  5091. .codec_name = "snd-soc-dummy",
  5092. .ignore_suspend = 1,
  5093. /* this dainlink has playback support */
  5094. .ignore_pmdown_time = 1,
  5095. .id = MSM_FRONTEND_DAI_VOIP,
  5096. },
  5097. {
  5098. .name = MSM_DAILINK_NAME(ULL),
  5099. .stream_name = "MultiMedia3",
  5100. .cpu_dai_name = "MultiMedia3",
  5101. .platform_name = "msm-pcm-dsp.2",
  5102. .dynamic = 1,
  5103. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5104. .dpcm_playback = 1,
  5105. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5106. SND_SOC_DPCM_TRIGGER_POST},
  5107. .codec_dai_name = "snd-soc-dummy-dai",
  5108. .codec_name = "snd-soc-dummy",
  5109. .ignore_suspend = 1,
  5110. /* this dainlink has playback support */
  5111. .ignore_pmdown_time = 1,
  5112. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5113. },
  5114. /* Hostless PCM purpose */
  5115. {
  5116. .name = "SLIMBUS_0 Hostless",
  5117. .stream_name = "SLIMBUS_0 Hostless",
  5118. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5119. .platform_name = "msm-pcm-hostless",
  5120. .dynamic = 1,
  5121. .dpcm_playback = 1,
  5122. .dpcm_capture = 1,
  5123. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5124. SND_SOC_DPCM_TRIGGER_POST},
  5125. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5126. .ignore_suspend = 1,
  5127. /* this dailink has playback support */
  5128. .ignore_pmdown_time = 1,
  5129. .codec_dai_name = "snd-soc-dummy-dai",
  5130. .codec_name = "snd-soc-dummy",
  5131. },
  5132. {
  5133. .name = "MSM AFE-PCM RX",
  5134. .stream_name = "AFE-PROXY RX",
  5135. .cpu_dai_name = "msm-dai-q6-dev.241",
  5136. .codec_name = "msm-stub-codec.1",
  5137. .codec_dai_name = "msm-stub-rx",
  5138. .platform_name = "msm-pcm-afe",
  5139. .dpcm_playback = 1,
  5140. .ignore_suspend = 1,
  5141. /* this dainlink has playback support */
  5142. .ignore_pmdown_time = 1,
  5143. },
  5144. {
  5145. .name = "MSM AFE-PCM TX",
  5146. .stream_name = "AFE-PROXY TX",
  5147. .cpu_dai_name = "msm-dai-q6-dev.240",
  5148. .codec_name = "msm-stub-codec.1",
  5149. .codec_dai_name = "msm-stub-tx",
  5150. .platform_name = "msm-pcm-afe",
  5151. .dpcm_capture = 1,
  5152. .ignore_suspend = 1,
  5153. },
  5154. {
  5155. .name = MSM_DAILINK_NAME(Compress1),
  5156. .stream_name = "Compress1",
  5157. .cpu_dai_name = "MultiMedia4",
  5158. .platform_name = "msm-compress-dsp",
  5159. .dynamic = 1,
  5160. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5161. .dpcm_playback = 1,
  5162. .dpcm_capture = 1,
  5163. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5164. SND_SOC_DPCM_TRIGGER_POST},
  5165. .codec_dai_name = "snd-soc-dummy-dai",
  5166. .codec_name = "snd-soc-dummy",
  5167. .ignore_suspend = 1,
  5168. .ignore_pmdown_time = 1,
  5169. /* this dainlink has playback support */
  5170. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5171. },
  5172. {
  5173. .name = "AUXPCM Hostless",
  5174. .stream_name = "AUXPCM Hostless",
  5175. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5176. .platform_name = "msm-pcm-hostless",
  5177. .dynamic = 1,
  5178. .dpcm_playback = 1,
  5179. .dpcm_capture = 1,
  5180. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5181. SND_SOC_DPCM_TRIGGER_POST},
  5182. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5183. .ignore_suspend = 1,
  5184. /* this dainlink has playback support */
  5185. .ignore_pmdown_time = 1,
  5186. .codec_dai_name = "snd-soc-dummy-dai",
  5187. .codec_name = "snd-soc-dummy",
  5188. },
  5189. {
  5190. .name = "SLIMBUS_1 Hostless",
  5191. .stream_name = "SLIMBUS_1 Hostless",
  5192. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5193. .platform_name = "msm-pcm-hostless",
  5194. .dynamic = 1,
  5195. .dpcm_playback = 1,
  5196. .dpcm_capture = 1,
  5197. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5198. SND_SOC_DPCM_TRIGGER_POST},
  5199. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5200. .ignore_suspend = 1,
  5201. /* this dailink has playback support */
  5202. .ignore_pmdown_time = 1,
  5203. .codec_dai_name = "snd-soc-dummy-dai",
  5204. .codec_name = "snd-soc-dummy",
  5205. },
  5206. {
  5207. .name = "SLIMBUS_3 Hostless",
  5208. .stream_name = "SLIMBUS_3 Hostless",
  5209. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5210. .platform_name = "msm-pcm-hostless",
  5211. .dynamic = 1,
  5212. .dpcm_playback = 1,
  5213. .dpcm_capture = 1,
  5214. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5215. SND_SOC_DPCM_TRIGGER_POST},
  5216. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5217. .ignore_suspend = 1,
  5218. /* this dailink has playback support */
  5219. .ignore_pmdown_time = 1,
  5220. .codec_dai_name = "snd-soc-dummy-dai",
  5221. .codec_name = "snd-soc-dummy",
  5222. },
  5223. {
  5224. .name = "SLIMBUS_4 Hostless",
  5225. .stream_name = "SLIMBUS_4 Hostless",
  5226. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5227. .platform_name = "msm-pcm-hostless",
  5228. .dynamic = 1,
  5229. .dpcm_playback = 1,
  5230. .dpcm_capture = 1,
  5231. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5232. SND_SOC_DPCM_TRIGGER_POST},
  5233. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5234. .ignore_suspend = 1,
  5235. /* this dailink has playback support */
  5236. .ignore_pmdown_time = 1,
  5237. .codec_dai_name = "snd-soc-dummy-dai",
  5238. .codec_name = "snd-soc-dummy",
  5239. },
  5240. {
  5241. .name = MSM_DAILINK_NAME(LowLatency),
  5242. .stream_name = "MultiMedia5",
  5243. .cpu_dai_name = "MultiMedia5",
  5244. .platform_name = "msm-pcm-dsp.1",
  5245. .dynamic = 1,
  5246. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5247. .dpcm_playback = 1,
  5248. .dpcm_capture = 1,
  5249. .codec_dai_name = "snd-soc-dummy-dai",
  5250. .codec_name = "snd-soc-dummy",
  5251. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5252. SND_SOC_DPCM_TRIGGER_POST},
  5253. .ignore_suspend = 1,
  5254. /* this dainlink has playback support */
  5255. .ignore_pmdown_time = 1,
  5256. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5257. .ops = &msm_fe_qos_ops,
  5258. },
  5259. {
  5260. .name = "Listen 1 Audio Service",
  5261. .stream_name = "Listen 1 Audio Service",
  5262. .cpu_dai_name = "LSM1",
  5263. .platform_name = "msm-lsm-client",
  5264. .dynamic = 1,
  5265. .dpcm_capture = 1,
  5266. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5267. SND_SOC_DPCM_TRIGGER_POST },
  5268. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5269. .ignore_suspend = 1,
  5270. .codec_dai_name = "snd-soc-dummy-dai",
  5271. .codec_name = "snd-soc-dummy",
  5272. .id = MSM_FRONTEND_DAI_LSM1,
  5273. },
  5274. /* Multiple Tunnel instances */
  5275. {
  5276. .name = MSM_DAILINK_NAME(Compress2),
  5277. .stream_name = "Compress2",
  5278. .cpu_dai_name = "MultiMedia7",
  5279. .platform_name = "msm-compress-dsp",
  5280. .dynamic = 1,
  5281. .dpcm_playback = 1,
  5282. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5283. SND_SOC_DPCM_TRIGGER_POST},
  5284. .codec_dai_name = "snd-soc-dummy-dai",
  5285. .codec_name = "snd-soc-dummy",
  5286. .ignore_suspend = 1,
  5287. .ignore_pmdown_time = 1,
  5288. /* this dainlink has playback support */
  5289. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5290. },
  5291. {
  5292. .name = MSM_DAILINK_NAME(MultiMedia10),
  5293. .stream_name = "MultiMedia10",
  5294. .cpu_dai_name = "MultiMedia10",
  5295. .platform_name = "msm-pcm-dsp.1",
  5296. .dynamic = 1,
  5297. .dpcm_playback = 1,
  5298. .dpcm_capture = 1,
  5299. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5300. SND_SOC_DPCM_TRIGGER_POST},
  5301. .codec_dai_name = "snd-soc-dummy-dai",
  5302. .codec_name = "snd-soc-dummy",
  5303. .ignore_suspend = 1,
  5304. .ignore_pmdown_time = 1,
  5305. /* this dainlink has playback support */
  5306. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5307. },
  5308. {
  5309. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5310. .stream_name = "MM_NOIRQ",
  5311. .cpu_dai_name = "MultiMedia8",
  5312. .platform_name = "msm-pcm-dsp-noirq",
  5313. .dynamic = 1,
  5314. .dpcm_playback = 1,
  5315. .dpcm_capture = 1,
  5316. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5317. SND_SOC_DPCM_TRIGGER_POST},
  5318. .codec_dai_name = "snd-soc-dummy-dai",
  5319. .codec_name = "snd-soc-dummy",
  5320. .ignore_suspend = 1,
  5321. .ignore_pmdown_time = 1,
  5322. /* this dainlink has playback support */
  5323. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5324. .ops = &msm_fe_qos_ops,
  5325. },
  5326. /* HDMI Hostless */
  5327. {
  5328. .name = "HDMI_RX_HOSTLESS",
  5329. .stream_name = "HDMI_RX_HOSTLESS",
  5330. .cpu_dai_name = "HDMI_HOSTLESS",
  5331. .platform_name = "msm-pcm-hostless",
  5332. .dynamic = 1,
  5333. .dpcm_playback = 1,
  5334. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5335. SND_SOC_DPCM_TRIGGER_POST},
  5336. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5337. .ignore_suspend = 1,
  5338. .ignore_pmdown_time = 1,
  5339. .codec_dai_name = "snd-soc-dummy-dai",
  5340. .codec_name = "snd-soc-dummy",
  5341. },
  5342. {
  5343. .name = "VoiceMMode2",
  5344. .stream_name = "VoiceMMode2",
  5345. .cpu_dai_name = "VoiceMMode2",
  5346. .platform_name = "msm-pcm-voice",
  5347. .dynamic = 1,
  5348. .dpcm_playback = 1,
  5349. .dpcm_capture = 1,
  5350. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5351. SND_SOC_DPCM_TRIGGER_POST},
  5352. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5353. .ignore_suspend = 1,
  5354. .ignore_pmdown_time = 1,
  5355. .codec_dai_name = "snd-soc-dummy-dai",
  5356. .codec_name = "snd-soc-dummy",
  5357. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5358. },
  5359. /* LSM FE */
  5360. {
  5361. .name = "Listen 2 Audio Service",
  5362. .stream_name = "Listen 2 Audio Service",
  5363. .cpu_dai_name = "LSM2",
  5364. .platform_name = "msm-lsm-client",
  5365. .dynamic = 1,
  5366. .dpcm_capture = 1,
  5367. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5368. SND_SOC_DPCM_TRIGGER_POST },
  5369. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5370. .ignore_suspend = 1,
  5371. .codec_dai_name = "snd-soc-dummy-dai",
  5372. .codec_name = "snd-soc-dummy",
  5373. .id = MSM_FRONTEND_DAI_LSM2,
  5374. },
  5375. {
  5376. .name = "Listen 3 Audio Service",
  5377. .stream_name = "Listen 3 Audio Service",
  5378. .cpu_dai_name = "LSM3",
  5379. .platform_name = "msm-lsm-client",
  5380. .dynamic = 1,
  5381. .dpcm_capture = 1,
  5382. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5383. SND_SOC_DPCM_TRIGGER_POST },
  5384. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5385. .ignore_suspend = 1,
  5386. .codec_dai_name = "snd-soc-dummy-dai",
  5387. .codec_name = "snd-soc-dummy",
  5388. .id = MSM_FRONTEND_DAI_LSM3,
  5389. },
  5390. {
  5391. .name = "Listen 4 Audio Service",
  5392. .stream_name = "Listen 4 Audio Service",
  5393. .cpu_dai_name = "LSM4",
  5394. .platform_name = "msm-lsm-client",
  5395. .dynamic = 1,
  5396. .dpcm_capture = 1,
  5397. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5398. SND_SOC_DPCM_TRIGGER_POST },
  5399. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5400. .ignore_suspend = 1,
  5401. .codec_dai_name = "snd-soc-dummy-dai",
  5402. .codec_name = "snd-soc-dummy",
  5403. .id = MSM_FRONTEND_DAI_LSM4,
  5404. },
  5405. {
  5406. .name = "Listen 5 Audio Service",
  5407. .stream_name = "Listen 5 Audio Service",
  5408. .cpu_dai_name = "LSM5",
  5409. .platform_name = "msm-lsm-client",
  5410. .dynamic = 1,
  5411. .dpcm_capture = 1,
  5412. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5413. SND_SOC_DPCM_TRIGGER_POST },
  5414. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5415. .ignore_suspend = 1,
  5416. .codec_dai_name = "snd-soc-dummy-dai",
  5417. .codec_name = "snd-soc-dummy",
  5418. .id = MSM_FRONTEND_DAI_LSM5,
  5419. },
  5420. {
  5421. .name = "Listen 6 Audio Service",
  5422. .stream_name = "Listen 6 Audio Service",
  5423. .cpu_dai_name = "LSM6",
  5424. .platform_name = "msm-lsm-client",
  5425. .dynamic = 1,
  5426. .dpcm_capture = 1,
  5427. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5428. SND_SOC_DPCM_TRIGGER_POST },
  5429. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5430. .ignore_suspend = 1,
  5431. .codec_dai_name = "snd-soc-dummy-dai",
  5432. .codec_name = "snd-soc-dummy",
  5433. .id = MSM_FRONTEND_DAI_LSM6,
  5434. },
  5435. {
  5436. .name = "Listen 7 Audio Service",
  5437. .stream_name = "Listen 7 Audio Service",
  5438. .cpu_dai_name = "LSM7",
  5439. .platform_name = "msm-lsm-client",
  5440. .dynamic = 1,
  5441. .dpcm_capture = 1,
  5442. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5443. SND_SOC_DPCM_TRIGGER_POST },
  5444. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5445. .ignore_suspend = 1,
  5446. .codec_dai_name = "snd-soc-dummy-dai",
  5447. .codec_name = "snd-soc-dummy",
  5448. .id = MSM_FRONTEND_DAI_LSM7,
  5449. },
  5450. {
  5451. .name = "Listen 8 Audio Service",
  5452. .stream_name = "Listen 8 Audio Service",
  5453. .cpu_dai_name = "LSM8",
  5454. .platform_name = "msm-lsm-client",
  5455. .dynamic = 1,
  5456. .dpcm_capture = 1,
  5457. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5458. SND_SOC_DPCM_TRIGGER_POST },
  5459. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5460. .ignore_suspend = 1,
  5461. .codec_dai_name = "snd-soc-dummy-dai",
  5462. .codec_name = "snd-soc-dummy",
  5463. .id = MSM_FRONTEND_DAI_LSM8,
  5464. },
  5465. {
  5466. .name = MSM_DAILINK_NAME(Media9),
  5467. .stream_name = "MultiMedia9",
  5468. .cpu_dai_name = "MultiMedia9",
  5469. .platform_name = "msm-pcm-dsp.0",
  5470. .dynamic = 1,
  5471. .dpcm_playback = 1,
  5472. .dpcm_capture = 1,
  5473. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5474. SND_SOC_DPCM_TRIGGER_POST},
  5475. .codec_dai_name = "snd-soc-dummy-dai",
  5476. .codec_name = "snd-soc-dummy",
  5477. .ignore_suspend = 1,
  5478. /* this dainlink has playback support */
  5479. .ignore_pmdown_time = 1,
  5480. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5481. },
  5482. {
  5483. .name = MSM_DAILINK_NAME(Compress4),
  5484. .stream_name = "Compress4",
  5485. .cpu_dai_name = "MultiMedia11",
  5486. .platform_name = "msm-compress-dsp",
  5487. .dynamic = 1,
  5488. .dpcm_playback = 1,
  5489. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5490. SND_SOC_DPCM_TRIGGER_POST},
  5491. .codec_dai_name = "snd-soc-dummy-dai",
  5492. .codec_name = "snd-soc-dummy",
  5493. .ignore_suspend = 1,
  5494. .ignore_pmdown_time = 1,
  5495. /* this dainlink has playback support */
  5496. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5497. },
  5498. {
  5499. .name = MSM_DAILINK_NAME(Compress5),
  5500. .stream_name = "Compress5",
  5501. .cpu_dai_name = "MultiMedia12",
  5502. .platform_name = "msm-compress-dsp",
  5503. .dynamic = 1,
  5504. .dpcm_playback = 1,
  5505. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5506. SND_SOC_DPCM_TRIGGER_POST},
  5507. .codec_dai_name = "snd-soc-dummy-dai",
  5508. .codec_name = "snd-soc-dummy",
  5509. .ignore_suspend = 1,
  5510. .ignore_pmdown_time = 1,
  5511. /* this dainlink has playback support */
  5512. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5513. },
  5514. {
  5515. .name = MSM_DAILINK_NAME(Compress6),
  5516. .stream_name = "Compress6",
  5517. .cpu_dai_name = "MultiMedia13",
  5518. .platform_name = "msm-compress-dsp",
  5519. .dynamic = 1,
  5520. .dpcm_playback = 1,
  5521. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5522. SND_SOC_DPCM_TRIGGER_POST},
  5523. .codec_dai_name = "snd-soc-dummy-dai",
  5524. .codec_name = "snd-soc-dummy",
  5525. .ignore_suspend = 1,
  5526. .ignore_pmdown_time = 1,
  5527. /* this dainlink has playback support */
  5528. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5529. },
  5530. {
  5531. .name = MSM_DAILINK_NAME(Compress7),
  5532. .stream_name = "Compress7",
  5533. .cpu_dai_name = "MultiMedia14",
  5534. .platform_name = "msm-compress-dsp",
  5535. .dynamic = 1,
  5536. .dpcm_playback = 1,
  5537. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5538. SND_SOC_DPCM_TRIGGER_POST},
  5539. .codec_dai_name = "snd-soc-dummy-dai",
  5540. .codec_name = "snd-soc-dummy",
  5541. .ignore_suspend = 1,
  5542. .ignore_pmdown_time = 1,
  5543. /* this dainlink has playback support */
  5544. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5545. },
  5546. {
  5547. .name = MSM_DAILINK_NAME(Compress8),
  5548. .stream_name = "Compress8",
  5549. .cpu_dai_name = "MultiMedia15",
  5550. .platform_name = "msm-compress-dsp",
  5551. .dynamic = 1,
  5552. .dpcm_playback = 1,
  5553. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5554. SND_SOC_DPCM_TRIGGER_POST},
  5555. .codec_dai_name = "snd-soc-dummy-dai",
  5556. .codec_name = "snd-soc-dummy",
  5557. .ignore_suspend = 1,
  5558. .ignore_pmdown_time = 1,
  5559. /* this dainlink has playback support */
  5560. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5561. },
  5562. {
  5563. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5564. .stream_name = "MM_NOIRQ_2",
  5565. .cpu_dai_name = "MultiMedia16",
  5566. .platform_name = "msm-pcm-dsp-noirq",
  5567. .dynamic = 1,
  5568. .dpcm_playback = 1,
  5569. .dpcm_capture = 1,
  5570. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5571. SND_SOC_DPCM_TRIGGER_POST},
  5572. .codec_dai_name = "snd-soc-dummy-dai",
  5573. .codec_name = "snd-soc-dummy",
  5574. .ignore_suspend = 1,
  5575. .ignore_pmdown_time = 1,
  5576. /* this dainlink has playback support */
  5577. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5578. },
  5579. {
  5580. .name = "SLIMBUS_8 Hostless",
  5581. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5582. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5583. .platform_name = "msm-pcm-hostless",
  5584. .dynamic = 1,
  5585. .dpcm_capture = 1,
  5586. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5587. SND_SOC_DPCM_TRIGGER_POST},
  5588. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5589. .ignore_suspend = 1,
  5590. .codec_dai_name = "snd-soc-dummy-dai",
  5591. .codec_name = "snd-soc-dummy",
  5592. },
  5593. /* Hostless PCM purpose */
  5594. {
  5595. .name = "CDC_DMA Hostless",
  5596. .stream_name = "CDC_DMA Hostless",
  5597. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5598. .platform_name = "msm-pcm-hostless",
  5599. .dynamic = 1,
  5600. .dpcm_playback = 1,
  5601. .dpcm_capture = 1,
  5602. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5603. SND_SOC_DPCM_TRIGGER_POST},
  5604. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5605. .ignore_suspend = 1,
  5606. /* this dailink has playback support */
  5607. .ignore_pmdown_time = 1,
  5608. .codec_dai_name = "snd-soc-dummy-dai",
  5609. .codec_name = "snd-soc-dummy",
  5610. },
  5611. };
  5612. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5613. {
  5614. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5615. .stream_name = "WSA CDC DMA0 Capture",
  5616. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5617. .platform_name = "msm-pcm-hostless",
  5618. .codec_name = "bolero_codec",
  5619. .codec_dai_name = "wsa_macro_vifeedback",
  5620. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5621. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5622. .ignore_suspend = 1,
  5623. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5624. .ops = &msm_cdc_dma_be_ops,
  5625. },
  5626. };
  5627. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5628. {
  5629. .name = MSM_DAILINK_NAME(ASM Loopback),
  5630. .stream_name = "MultiMedia6",
  5631. .cpu_dai_name = "MultiMedia6",
  5632. .platform_name = "msm-pcm-loopback",
  5633. .dynamic = 1,
  5634. .dpcm_playback = 1,
  5635. .dpcm_capture = 1,
  5636. .codec_dai_name = "snd-soc-dummy-dai",
  5637. .codec_name = "snd-soc-dummy",
  5638. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5639. SND_SOC_DPCM_TRIGGER_POST},
  5640. .ignore_suspend = 1,
  5641. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5642. .ignore_pmdown_time = 1,
  5643. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5644. },
  5645. {
  5646. .name = "USB Audio Hostless",
  5647. .stream_name = "USB Audio Hostless",
  5648. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5649. .platform_name = "msm-pcm-hostless",
  5650. .dynamic = 1,
  5651. .dpcm_playback = 1,
  5652. .dpcm_capture = 1,
  5653. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5654. SND_SOC_DPCM_TRIGGER_POST},
  5655. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5656. .ignore_suspend = 1,
  5657. .ignore_pmdown_time = 1,
  5658. .codec_dai_name = "snd-soc-dummy-dai",
  5659. .codec_name = "snd-soc-dummy",
  5660. },
  5661. {
  5662. .name = "SLIMBUS_7 Hostless",
  5663. .stream_name = "SLIMBUS_7 Hostless",
  5664. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5665. .platform_name = "msm-pcm-hostless",
  5666. .dynamic = 1,
  5667. .dpcm_capture = 1,
  5668. .dpcm_playback = 1,
  5669. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5670. SND_SOC_DPCM_TRIGGER_POST},
  5671. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5672. .ignore_suspend = 1,
  5673. .ignore_pmdown_time = 1,
  5674. .codec_dai_name = "snd-soc-dummy-dai",
  5675. .codec_name = "snd-soc-dummy",
  5676. },
  5677. {
  5678. .name = MSM_DAILINK_NAME(Compr Capture),
  5679. .stream_name = "Compr Capture",
  5680. .cpu_dai_name = "MultiMedia18",
  5681. .platform_name = "msm-compress-dsp",
  5682. .dynamic = 1,
  5683. .dpcm_capture = 1,
  5684. .codec_dai_name = "snd-soc-dummy-dai",
  5685. .codec_name = "snd-soc-dummy",
  5686. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5687. SND_SOC_DPCM_TRIGGER_POST},
  5688. .ignore_pmdown_time = 1,
  5689. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  5690. },
  5691. };
  5692. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5693. /* Backend AFE DAI Links */
  5694. {
  5695. .name = LPASS_BE_AFE_PCM_RX,
  5696. .stream_name = "AFE Playback",
  5697. .cpu_dai_name = "msm-dai-q6-dev.224",
  5698. .platform_name = "msm-pcm-routing",
  5699. .codec_name = "msm-stub-codec.1",
  5700. .codec_dai_name = "msm-stub-rx",
  5701. .no_pcm = 1,
  5702. .dpcm_playback = 1,
  5703. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5704. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5705. /* this dainlink has playback support */
  5706. .ignore_pmdown_time = 1,
  5707. .ignore_suspend = 1,
  5708. },
  5709. {
  5710. .name = LPASS_BE_AFE_PCM_TX,
  5711. .stream_name = "AFE Capture",
  5712. .cpu_dai_name = "msm-dai-q6-dev.225",
  5713. .platform_name = "msm-pcm-routing",
  5714. .codec_name = "msm-stub-codec.1",
  5715. .codec_dai_name = "msm-stub-tx",
  5716. .no_pcm = 1,
  5717. .dpcm_capture = 1,
  5718. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5719. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5720. .ignore_suspend = 1,
  5721. },
  5722. /* Incall Record Uplink BACK END DAI Link */
  5723. {
  5724. .name = LPASS_BE_INCALL_RECORD_TX,
  5725. .stream_name = "Voice Uplink Capture",
  5726. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5727. .platform_name = "msm-pcm-routing",
  5728. .codec_name = "msm-stub-codec.1",
  5729. .codec_dai_name = "msm-stub-tx",
  5730. .no_pcm = 1,
  5731. .dpcm_capture = 1,
  5732. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5733. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5734. .ignore_suspend = 1,
  5735. },
  5736. /* Incall Record Downlink BACK END DAI Link */
  5737. {
  5738. .name = LPASS_BE_INCALL_RECORD_RX,
  5739. .stream_name = "Voice Downlink Capture",
  5740. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5741. .platform_name = "msm-pcm-routing",
  5742. .codec_name = "msm-stub-codec.1",
  5743. .codec_dai_name = "msm-stub-tx",
  5744. .no_pcm = 1,
  5745. .dpcm_capture = 1,
  5746. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5747. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5748. .ignore_suspend = 1,
  5749. },
  5750. /* Incall Music BACK END DAI Link */
  5751. {
  5752. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5753. .stream_name = "Voice Farend Playback",
  5754. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5755. .platform_name = "msm-pcm-routing",
  5756. .codec_name = "msm-stub-codec.1",
  5757. .codec_dai_name = "msm-stub-rx",
  5758. .no_pcm = 1,
  5759. .dpcm_playback = 1,
  5760. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5761. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5762. .ignore_suspend = 1,
  5763. .ignore_pmdown_time = 1,
  5764. },
  5765. /* Incall Music 2 BACK END DAI Link */
  5766. {
  5767. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5768. .stream_name = "Voice2 Farend Playback",
  5769. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5770. .platform_name = "msm-pcm-routing",
  5771. .codec_name = "msm-stub-codec.1",
  5772. .codec_dai_name = "msm-stub-rx",
  5773. .no_pcm = 1,
  5774. .dpcm_playback = 1,
  5775. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5776. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5777. .ignore_suspend = 1,
  5778. .ignore_pmdown_time = 1,
  5779. },
  5780. {
  5781. .name = LPASS_BE_USB_AUDIO_RX,
  5782. .stream_name = "USB Audio Playback",
  5783. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5784. .platform_name = "msm-pcm-routing",
  5785. .codec_name = "msm-stub-codec.1",
  5786. .codec_dai_name = "msm-stub-rx",
  5787. .no_pcm = 1,
  5788. .dpcm_playback = 1,
  5789. .id = MSM_BACKEND_DAI_USB_RX,
  5790. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5791. .ignore_pmdown_time = 1,
  5792. .ignore_suspend = 1,
  5793. },
  5794. {
  5795. .name = LPASS_BE_USB_AUDIO_TX,
  5796. .stream_name = "USB Audio Capture",
  5797. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5798. .platform_name = "msm-pcm-routing",
  5799. .codec_name = "msm-stub-codec.1",
  5800. .codec_dai_name = "msm-stub-tx",
  5801. .no_pcm = 1,
  5802. .dpcm_capture = 1,
  5803. .id = MSM_BACKEND_DAI_USB_TX,
  5804. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5805. .ignore_suspend = 1,
  5806. },
  5807. {
  5808. .name = LPASS_BE_PRI_TDM_RX_0,
  5809. .stream_name = "Primary TDM0 Playback",
  5810. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5811. .platform_name = "msm-pcm-routing",
  5812. .codec_name = "msm-stub-codec.1",
  5813. .codec_dai_name = "msm-stub-rx",
  5814. .no_pcm = 1,
  5815. .dpcm_playback = 1,
  5816. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5817. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5818. .ops = &qcs405_tdm_be_ops,
  5819. .ignore_suspend = 1,
  5820. .ignore_pmdown_time = 1,
  5821. },
  5822. {
  5823. .name = LPASS_BE_PRI_TDM_TX_0,
  5824. .stream_name = "Primary TDM0 Capture",
  5825. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5826. .platform_name = "msm-pcm-routing",
  5827. .codec_name = "msm-stub-codec.1",
  5828. .codec_dai_name = "msm-stub-tx",
  5829. .no_pcm = 1,
  5830. .dpcm_capture = 1,
  5831. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5832. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5833. .ops = &qcs405_tdm_be_ops,
  5834. .ignore_suspend = 1,
  5835. },
  5836. {
  5837. .name = LPASS_BE_SEC_TDM_RX_0,
  5838. .stream_name = "Secondary TDM0 Playback",
  5839. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5840. .platform_name = "msm-pcm-routing",
  5841. .codec_name = "msm-stub-codec.1",
  5842. .codec_dai_name = "msm-stub-rx",
  5843. .no_pcm = 1,
  5844. .dpcm_playback = 1,
  5845. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5846. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5847. .ops = &qcs405_tdm_be_ops,
  5848. .ignore_suspend = 1,
  5849. .ignore_pmdown_time = 1,
  5850. },
  5851. {
  5852. .name = LPASS_BE_SEC_TDM_TX_0,
  5853. .stream_name = "Secondary TDM0 Capture",
  5854. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5855. .platform_name = "msm-pcm-routing",
  5856. .codec_name = "msm-stub-codec.1",
  5857. .codec_dai_name = "msm-stub-tx",
  5858. .no_pcm = 1,
  5859. .dpcm_capture = 1,
  5860. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5861. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5862. .ops = &qcs405_tdm_be_ops,
  5863. .ignore_suspend = 1,
  5864. },
  5865. {
  5866. .name = LPASS_BE_TERT_TDM_RX_0,
  5867. .stream_name = "Tertiary TDM0 Playback",
  5868. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5869. .platform_name = "msm-pcm-routing",
  5870. .codec_name = "msm-stub-codec.1",
  5871. .codec_dai_name = "msm-stub-rx",
  5872. .no_pcm = 1,
  5873. .dpcm_playback = 1,
  5874. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5875. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5876. .ops = &qcs405_tdm_be_ops,
  5877. .ignore_suspend = 1,
  5878. .ignore_pmdown_time = 1,
  5879. },
  5880. {
  5881. .name = LPASS_BE_TERT_TDM_TX_0,
  5882. .stream_name = "Tertiary TDM0 Capture",
  5883. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5884. .platform_name = "msm-pcm-routing",
  5885. .codec_name = "msm-stub-codec.1",
  5886. .codec_dai_name = "msm-stub-tx",
  5887. .no_pcm = 1,
  5888. .dpcm_capture = 1,
  5889. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5890. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5891. .ops = &qcs405_tdm_be_ops,
  5892. .ignore_suspend = 1,
  5893. },
  5894. {
  5895. .name = LPASS_BE_QUAT_TDM_RX_0,
  5896. .stream_name = "Quaternary TDM0 Playback",
  5897. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5898. .platform_name = "msm-pcm-routing",
  5899. .codec_name = "msm-stub-codec.1",
  5900. .codec_dai_name = "msm-stub-rx",
  5901. .no_pcm = 1,
  5902. .dpcm_playback = 1,
  5903. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5904. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5905. .ops = &qcs405_tdm_be_ops,
  5906. .ignore_suspend = 1,
  5907. .ignore_pmdown_time = 1,
  5908. },
  5909. {
  5910. .name = LPASS_BE_QUAT_TDM_TX_0,
  5911. .stream_name = "Quaternary TDM0 Capture",
  5912. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5913. .platform_name = "msm-pcm-routing",
  5914. .codec_name = "msm-stub-codec.1",
  5915. .codec_dai_name = "msm-stub-tx",
  5916. .no_pcm = 1,
  5917. .dpcm_capture = 1,
  5918. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5919. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5920. .ops = &qcs405_tdm_be_ops,
  5921. .ignore_suspend = 1,
  5922. },
  5923. {
  5924. .name = LPASS_BE_QUIN_TDM_RX_0,
  5925. .stream_name = "Quinary TDM0 Playback",
  5926. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5927. .platform_name = "msm-pcm-routing",
  5928. .codec_name = "msm-stub-codec.1",
  5929. .codec_dai_name = "msm-stub-rx",
  5930. .no_pcm = 1,
  5931. .dpcm_playback = 1,
  5932. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5933. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5934. .ops = &qcs405_tdm_be_ops,
  5935. .ignore_suspend = 1,
  5936. .ignore_pmdown_time = 1,
  5937. },
  5938. {
  5939. .name = LPASS_BE_QUIN_TDM_TX_0,
  5940. .stream_name = "Quinary TDM0 Capture",
  5941. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5942. .platform_name = "msm-pcm-routing",
  5943. .codec_name = "msm-stub-codec.1",
  5944. .codec_dai_name = "msm-stub-tx",
  5945. .no_pcm = 1,
  5946. .dpcm_capture = 1,
  5947. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5948. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5949. .ops = &qcs405_tdm_be_ops,
  5950. .ignore_suspend = 1,
  5951. },
  5952. };
  5953. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5954. {
  5955. .name = LPASS_BE_SLIMBUS_0_RX,
  5956. .stream_name = "Slimbus Playback",
  5957. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5958. .platform_name = "msm-pcm-routing",
  5959. .codec_name = "tasha_codec",
  5960. .codec_dai_name = "tasha_mix_rx1",
  5961. .no_pcm = 1,
  5962. .dpcm_playback = 1,
  5963. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5964. .init = &msm_audrx_init,
  5965. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5966. /* this dainlink has playback support */
  5967. .ignore_pmdown_time = 1,
  5968. .ignore_suspend = 1,
  5969. .ops = &msm_be_ops,
  5970. },
  5971. {
  5972. .name = LPASS_BE_SLIMBUS_0_TX,
  5973. .stream_name = "Slimbus Capture",
  5974. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5975. .platform_name = "msm-pcm-routing",
  5976. .codec_name = "tasha_codec",
  5977. .codec_dai_name = "tasha_tx1",
  5978. .no_pcm = 1,
  5979. .dpcm_capture = 1,
  5980. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5981. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5982. .ignore_suspend = 1,
  5983. .ops = &msm_be_ops,
  5984. },
  5985. {
  5986. .name = LPASS_BE_SLIMBUS_1_RX,
  5987. .stream_name = "Slimbus1 Playback",
  5988. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5989. .platform_name = "msm-pcm-routing",
  5990. .codec_name = "tasha_codec",
  5991. .codec_dai_name = "tasha_mix_rx1",
  5992. .no_pcm = 1,
  5993. .dpcm_playback = 1,
  5994. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5995. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5996. .ops = &msm_be_ops,
  5997. /* dai link has playback support */
  5998. .ignore_pmdown_time = 1,
  5999. .ignore_suspend = 1,
  6000. },
  6001. {
  6002. .name = LPASS_BE_SLIMBUS_1_TX,
  6003. .stream_name = "Slimbus1 Capture",
  6004. .cpu_dai_name = "msm-dai-q6-dev.16387",
  6005. .platform_name = "msm-pcm-routing",
  6006. .codec_name = "tasha_codec",
  6007. .codec_dai_name = "tasha_tx3",
  6008. .no_pcm = 1,
  6009. .dpcm_capture = 1,
  6010. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  6011. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6012. .ops = &msm_be_ops,
  6013. .ignore_suspend = 1,
  6014. },
  6015. {
  6016. .name = LPASS_BE_SLIMBUS_2_RX,
  6017. .stream_name = "Slimbus2 Playback",
  6018. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6019. .platform_name = "msm-pcm-routing",
  6020. .codec_name = "tasha_codec",
  6021. .codec_dai_name = "tasha_rx2",
  6022. .no_pcm = 1,
  6023. .dpcm_playback = 1,
  6024. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6025. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6026. .ops = &msm_be_ops,
  6027. .ignore_pmdown_time = 1,
  6028. .ignore_suspend = 1,
  6029. },
  6030. {
  6031. .name = LPASS_BE_SLIMBUS_3_RX,
  6032. .stream_name = "Slimbus3 Playback",
  6033. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6034. .platform_name = "msm-pcm-routing",
  6035. .codec_name = "tasha_codec",
  6036. .codec_dai_name = "tasha_mix_rx1",
  6037. .no_pcm = 1,
  6038. .dpcm_playback = 1,
  6039. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6040. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6041. .ops = &msm_be_ops,
  6042. /* dai link has playback support */
  6043. .ignore_pmdown_time = 1,
  6044. .ignore_suspend = 1,
  6045. },
  6046. {
  6047. .name = LPASS_BE_SLIMBUS_3_TX,
  6048. .stream_name = "Slimbus3 Capture",
  6049. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6050. .platform_name = "msm-pcm-routing",
  6051. .codec_name = "tasha_codec",
  6052. .codec_dai_name = "tasha_tx1",
  6053. .no_pcm = 1,
  6054. .dpcm_capture = 1,
  6055. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6056. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6057. .ops = &msm_be_ops,
  6058. .ignore_suspend = 1,
  6059. },
  6060. {
  6061. .name = LPASS_BE_SLIMBUS_4_RX,
  6062. .stream_name = "Slimbus4 Playback",
  6063. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6064. .platform_name = "msm-pcm-routing",
  6065. .codec_name = "tasha_codec",
  6066. .codec_dai_name = "tasha_mix_rx1",
  6067. .no_pcm = 1,
  6068. .dpcm_playback = 1,
  6069. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6070. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6071. .ops = &msm_be_ops,
  6072. /* dai link has playback support */
  6073. .ignore_pmdown_time = 1,
  6074. .ignore_suspend = 1,
  6075. },
  6076. {
  6077. .name = LPASS_BE_SLIMBUS_5_RX,
  6078. .stream_name = "Slimbus5 Playback",
  6079. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6080. .platform_name = "msm-pcm-routing",
  6081. .codec_name = "tasha_codec",
  6082. .codec_dai_name = "tasha_rx3",
  6083. .no_pcm = 1,
  6084. .dpcm_playback = 1,
  6085. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6086. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6087. .ops = &msm_be_ops,
  6088. /* dai link has playback support */
  6089. .ignore_pmdown_time = 1,
  6090. .ignore_suspend = 1,
  6091. },
  6092. {
  6093. .name = LPASS_BE_SLIMBUS_6_RX,
  6094. .stream_name = "Slimbus6 Playback",
  6095. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6096. .platform_name = "msm-pcm-routing",
  6097. .codec_name = "tasha_codec",
  6098. .codec_dai_name = "tasha_rx4",
  6099. .no_pcm = 1,
  6100. .dpcm_playback = 1,
  6101. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6102. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6103. .ops = &msm_be_ops,
  6104. /* dai link has playback support */
  6105. .ignore_pmdown_time = 1,
  6106. .ignore_suspend = 1,
  6107. },
  6108. /* Slimbus VI Recording */
  6109. {
  6110. .name = LPASS_BE_SLIMBUS_TX_VI,
  6111. .stream_name = "Slimbus4 Capture",
  6112. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6113. .platform_name = "msm-pcm-routing",
  6114. .codec_name = "tasha_codec",
  6115. .codec_dai_name = "tasha_vifeedback",
  6116. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6117. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6118. .ops = &msm_be_ops,
  6119. .ignore_suspend = 1,
  6120. .no_pcm = 1,
  6121. .dpcm_capture = 1,
  6122. .ignore_pmdown_time = 1,
  6123. },
  6124. };
  6125. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6126. {
  6127. .name = LPASS_BE_SLIMBUS_7_RX,
  6128. .stream_name = "Slimbus7 Playback",
  6129. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6130. .platform_name = "msm-pcm-routing",
  6131. .codec_name = "btfmslim_slave",
  6132. /* BT codec driver determines capabilities based on
  6133. * dai name, bt codecdai name should always contains
  6134. * supported usecase information
  6135. */
  6136. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6137. .no_pcm = 1,
  6138. .dpcm_playback = 1,
  6139. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6140. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6141. .ops = &msm_wcn_ops,
  6142. /* dai link has playback support */
  6143. .ignore_pmdown_time = 1,
  6144. .ignore_suspend = 1,
  6145. },
  6146. {
  6147. .name = LPASS_BE_SLIMBUS_7_TX,
  6148. .stream_name = "Slimbus7 Capture",
  6149. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6150. .platform_name = "msm-pcm-routing",
  6151. .codec_name = "btfmslim_slave",
  6152. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6153. .no_pcm = 1,
  6154. .dpcm_capture = 1,
  6155. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6156. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6157. .ops = &msm_wcn_ops,
  6158. .ignore_suspend = 1,
  6159. },
  6160. {
  6161. .name = LPASS_BE_SLIMBUS_8_TX,
  6162. .stream_name = "Slimbus8 Capture",
  6163. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6164. .platform_name = "msm-pcm-routing",
  6165. .codec_name = "btfmslim_slave",
  6166. .codec_dai_name = "btfm_fm_slim_tx",
  6167. .no_pcm = 1,
  6168. .dpcm_capture = 1,
  6169. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6170. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6171. .init = &msm_wcn_init,
  6172. .ops = &msm_wcn_ops,
  6173. .ignore_suspend = 1,
  6174. },
  6175. };
  6176. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6177. {
  6178. .name = LPASS_BE_PRI_MI2S_RX,
  6179. .stream_name = "Primary MI2S Playback",
  6180. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6181. .platform_name = "msm-pcm-routing",
  6182. .codec_name = "msm-stub-codec.1",
  6183. .codec_dai_name = "msm-stub-rx",
  6184. .no_pcm = 1,
  6185. .dpcm_playback = 1,
  6186. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6187. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6188. .ops = &msm_mi2s_be_ops,
  6189. .ignore_suspend = 1,
  6190. .ignore_pmdown_time = 1,
  6191. },
  6192. {
  6193. .name = LPASS_BE_PRI_MI2S_TX,
  6194. .stream_name = "Primary MI2S Capture",
  6195. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6196. .platform_name = "msm-pcm-routing",
  6197. .codec_name = "msm-stub-codec.1",
  6198. .codec_dai_name = "msm-stub-tx",
  6199. .no_pcm = 1,
  6200. .dpcm_capture = 1,
  6201. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6202. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6203. .ops = &msm_mi2s_be_ops,
  6204. .ignore_suspend = 1,
  6205. },
  6206. {
  6207. .name = LPASS_BE_SEC_MI2S_RX,
  6208. .stream_name = "Secondary MI2S Playback",
  6209. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6210. .platform_name = "msm-pcm-routing",
  6211. .codec_name = "msm-stub-codec.1",
  6212. .codec_dai_name = "msm-stub-rx",
  6213. .no_pcm = 1,
  6214. .dpcm_playback = 1,
  6215. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6216. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6217. .ops = &msm_mi2s_be_ops,
  6218. .ignore_suspend = 1,
  6219. .ignore_pmdown_time = 1,
  6220. },
  6221. {
  6222. .name = LPASS_BE_SEC_MI2S_TX,
  6223. .stream_name = "Secondary MI2S Capture",
  6224. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6225. .platform_name = "msm-pcm-routing",
  6226. .codec_name = "msm-stub-codec.1",
  6227. .codec_dai_name = "msm-stub-tx",
  6228. .no_pcm = 1,
  6229. .dpcm_capture = 1,
  6230. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6231. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6232. .ops = &msm_mi2s_be_ops,
  6233. .ignore_suspend = 1,
  6234. },
  6235. {
  6236. .name = LPASS_BE_TERT_MI2S_RX,
  6237. .stream_name = "Tertiary MI2S Playback",
  6238. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6239. .platform_name = "msm-pcm-routing",
  6240. .codec_name = "msm-stub-codec.1",
  6241. .codec_dai_name = "msm-stub-rx",
  6242. .no_pcm = 1,
  6243. .dpcm_playback = 1,
  6244. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6245. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6246. .ops = &msm_mi2s_be_ops,
  6247. .ignore_suspend = 1,
  6248. .ignore_pmdown_time = 1,
  6249. },
  6250. {
  6251. .name = LPASS_BE_TERT_MI2S_TX,
  6252. .stream_name = "Tertiary MI2S Capture",
  6253. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6254. .platform_name = "msm-pcm-routing",
  6255. .codec_name = "msm-stub-codec.1",
  6256. .codec_dai_name = "msm-stub-tx",
  6257. .no_pcm = 1,
  6258. .dpcm_capture = 1,
  6259. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6260. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6261. .ops = &msm_mi2s_be_ops,
  6262. .ignore_suspend = 1,
  6263. },
  6264. {
  6265. .name = LPASS_BE_QUAT_MI2S_RX,
  6266. .stream_name = "Quaternary MI2S Playback",
  6267. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6268. .platform_name = "msm-pcm-routing",
  6269. .codec_name = "msm-stub-codec.1",
  6270. .codec_dai_name = "msm-stub-rx",
  6271. .no_pcm = 1,
  6272. .dpcm_playback = 1,
  6273. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6274. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6275. .ops = &msm_mi2s_be_ops,
  6276. .ignore_suspend = 1,
  6277. .ignore_pmdown_time = 1,
  6278. },
  6279. {
  6280. .name = LPASS_BE_QUAT_MI2S_TX,
  6281. .stream_name = "Quaternary MI2S Capture",
  6282. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6283. .platform_name = "msm-pcm-routing",
  6284. .codec_name = "msm-stub-codec.1",
  6285. .codec_dai_name = "msm-stub-tx",
  6286. .no_pcm = 1,
  6287. .dpcm_capture = 1,
  6288. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6289. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6290. .ops = &msm_mi2s_be_ops,
  6291. .ignore_suspend = 1,
  6292. },
  6293. {
  6294. .name = LPASS_BE_QUIN_MI2S_RX,
  6295. .stream_name = "Quinary MI2S Playback",
  6296. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6297. .platform_name = "msm-pcm-routing",
  6298. .codec_name = "msm-stub-codec.1",
  6299. .codec_dai_name = "msm-stub-rx",
  6300. .no_pcm = 1,
  6301. .dpcm_playback = 1,
  6302. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6303. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6304. .ops = &msm_mi2s_be_ops,
  6305. .ignore_suspend = 1,
  6306. .ignore_pmdown_time = 1,
  6307. },
  6308. {
  6309. .name = LPASS_BE_QUIN_MI2S_TX,
  6310. .stream_name = "Quinary MI2S Capture",
  6311. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6312. .platform_name = "msm-pcm-routing",
  6313. .codec_name = "msm-stub-codec.1",
  6314. .codec_dai_name = "msm-stub-tx",
  6315. .no_pcm = 1,
  6316. .dpcm_capture = 1,
  6317. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6318. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6319. .ops = &msm_mi2s_be_ops,
  6320. .ignore_suspend = 1,
  6321. },
  6322. };
  6323. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6324. /* Primary AUX PCM Backend DAI Links */
  6325. {
  6326. .name = LPASS_BE_AUXPCM_RX,
  6327. .stream_name = "AUX PCM Playback",
  6328. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6329. .platform_name = "msm-pcm-routing",
  6330. .codec_name = "msm-stub-codec.1",
  6331. .codec_dai_name = "msm-stub-rx",
  6332. .no_pcm = 1,
  6333. .dpcm_playback = 1,
  6334. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6335. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6336. .ignore_pmdown_time = 1,
  6337. .ignore_suspend = 1,
  6338. },
  6339. {
  6340. .name = LPASS_BE_AUXPCM_TX,
  6341. .stream_name = "AUX PCM Capture",
  6342. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6343. .platform_name = "msm-pcm-routing",
  6344. .codec_name = "msm-stub-codec.1",
  6345. .codec_dai_name = "msm-stub-tx",
  6346. .no_pcm = 1,
  6347. .dpcm_capture = 1,
  6348. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6349. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6350. .ignore_suspend = 1,
  6351. },
  6352. /* Secondary AUX PCM Backend DAI Links */
  6353. {
  6354. .name = LPASS_BE_SEC_AUXPCM_RX,
  6355. .stream_name = "Sec AUX PCM Playback",
  6356. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6357. .platform_name = "msm-pcm-routing",
  6358. .codec_name = "msm-stub-codec.1",
  6359. .codec_dai_name = "msm-stub-rx",
  6360. .no_pcm = 1,
  6361. .dpcm_playback = 1,
  6362. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6363. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6364. .ignore_pmdown_time = 1,
  6365. .ignore_suspend = 1,
  6366. },
  6367. {
  6368. .name = LPASS_BE_SEC_AUXPCM_TX,
  6369. .stream_name = "Sec AUX PCM Capture",
  6370. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6371. .platform_name = "msm-pcm-routing",
  6372. .codec_name = "msm-stub-codec.1",
  6373. .codec_dai_name = "msm-stub-tx",
  6374. .no_pcm = 1,
  6375. .dpcm_capture = 1,
  6376. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6377. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6378. .ignore_suspend = 1,
  6379. },
  6380. /* Tertiary AUX PCM Backend DAI Links */
  6381. {
  6382. .name = LPASS_BE_TERT_AUXPCM_RX,
  6383. .stream_name = "Tert AUX PCM Playback",
  6384. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6385. .platform_name = "msm-pcm-routing",
  6386. .codec_name = "msm-stub-codec.1",
  6387. .codec_dai_name = "msm-stub-rx",
  6388. .no_pcm = 1,
  6389. .dpcm_playback = 1,
  6390. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6391. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6392. .ignore_suspend = 1,
  6393. },
  6394. {
  6395. .name = LPASS_BE_TERT_AUXPCM_TX,
  6396. .stream_name = "Tert AUX PCM Capture",
  6397. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6398. .platform_name = "msm-pcm-routing",
  6399. .codec_name = "msm-stub-codec.1",
  6400. .codec_dai_name = "msm-stub-tx",
  6401. .no_pcm = 1,
  6402. .dpcm_capture = 1,
  6403. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6404. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6405. .ignore_suspend = 1,
  6406. },
  6407. /* Quaternary AUX PCM Backend DAI Links */
  6408. {
  6409. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6410. .stream_name = "Quat AUX PCM Playback",
  6411. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6412. .platform_name = "msm-pcm-routing",
  6413. .codec_name = "msm-stub-codec.1",
  6414. .codec_dai_name = "msm-stub-rx",
  6415. .no_pcm = 1,
  6416. .dpcm_playback = 1,
  6417. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6418. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6419. .ignore_pmdown_time = 1,
  6420. .ignore_suspend = 1,
  6421. },
  6422. {
  6423. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6424. .stream_name = "Quat AUX PCM Capture",
  6425. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6426. .platform_name = "msm-pcm-routing",
  6427. .codec_name = "msm-stub-codec.1",
  6428. .codec_dai_name = "msm-stub-tx",
  6429. .no_pcm = 1,
  6430. .dpcm_capture = 1,
  6431. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6432. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6433. .ignore_suspend = 1,
  6434. },
  6435. /* Quinary AUX PCM Backend DAI Links */
  6436. {
  6437. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6438. .stream_name = "Quin AUX PCM Playback",
  6439. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6440. .platform_name = "msm-pcm-routing",
  6441. .codec_name = "msm-stub-codec.1",
  6442. .codec_dai_name = "msm-stub-rx",
  6443. .no_pcm = 1,
  6444. .dpcm_playback = 1,
  6445. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6446. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6447. .ignore_pmdown_time = 1,
  6448. .ignore_suspend = 1,
  6449. },
  6450. {
  6451. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6452. .stream_name = "Quin AUX PCM Capture",
  6453. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6454. .platform_name = "msm-pcm-routing",
  6455. .codec_name = "msm-stub-codec.1",
  6456. .codec_dai_name = "msm-stub-tx",
  6457. .no_pcm = 1,
  6458. .dpcm_capture = 1,
  6459. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6460. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6461. .ignore_suspend = 1,
  6462. },
  6463. };
  6464. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6465. /* WSA CDC DMA Backend DAI Links */
  6466. {
  6467. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6468. .stream_name = "WSA CDC DMA0 Playback",
  6469. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6470. .platform_name = "msm-pcm-routing",
  6471. .codec_name = "bolero_codec",
  6472. .codec_dai_name = "wsa_macro_rx1",
  6473. .no_pcm = 1,
  6474. .dpcm_playback = 1,
  6475. .init = &msm_wsa_cdc_dma_init,
  6476. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6477. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6478. .ignore_pmdown_time = 1,
  6479. .ignore_suspend = 1,
  6480. .ops = &msm_cdc_dma_be_ops,
  6481. },
  6482. {
  6483. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6484. .stream_name = "WSA CDC DMA1 Playback",
  6485. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6486. .platform_name = "msm-pcm-routing",
  6487. .codec_name = "bolero_codec",
  6488. .codec_dai_name = "wsa_macro_rx_mix",
  6489. .no_pcm = 1,
  6490. .dpcm_playback = 1,
  6491. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6492. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6493. .ignore_pmdown_time = 1,
  6494. .ignore_suspend = 1,
  6495. .ops = &msm_cdc_dma_be_ops,
  6496. },
  6497. {
  6498. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6499. .stream_name = "WSA CDC DMA1 Capture",
  6500. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6501. .platform_name = "msm-pcm-routing",
  6502. .codec_name = "bolero_codec",
  6503. .codec_dai_name = "wsa_macro_echo",
  6504. .no_pcm = 1,
  6505. .dpcm_capture = 1,
  6506. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6507. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6508. .ignore_suspend = 1,
  6509. .ops = &msm_cdc_dma_be_ops,
  6510. },
  6511. };
  6512. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6513. {
  6514. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6515. .stream_name = "VA CDC DMA0 Capture",
  6516. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6517. .platform_name = "msm-pcm-routing",
  6518. .codec_name = "bolero_codec",
  6519. .codec_dai_name = "va_macro_tx1",
  6520. .no_pcm = 1,
  6521. .dpcm_capture = 1,
  6522. .init = &msm_va_cdc_dma_init,
  6523. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6524. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6525. .ignore_suspend = 1,
  6526. .ops = &msm_cdc_dma_be_ops,
  6527. },
  6528. {
  6529. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6530. .stream_name = "VA CDC DMA1 Capture",
  6531. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6532. .platform_name = "msm-pcm-routing",
  6533. .codec_name = "bolero_codec",
  6534. .codec_dai_name = "va_macro_tx2",
  6535. .no_pcm = 1,
  6536. .dpcm_capture = 1,
  6537. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6538. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6539. .ignore_suspend = 1,
  6540. .ops = &msm_cdc_dma_be_ops,
  6541. },
  6542. };
  6543. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  6544. {
  6545. .name = LPASS_BE_PRI_SPDIF_RX,
  6546. .stream_name = "Primary SPDIF Playback",
  6547. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  6548. .platform_name = "msm-pcm-routing",
  6549. .codec_name = "msm-stub-codec.1",
  6550. .codec_dai_name = "msm-stub-rx",
  6551. .no_pcm = 1,
  6552. .dpcm_playback = 1,
  6553. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  6554. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6555. .ops = &msm_spdif_be_ops,
  6556. .ignore_suspend = 1,
  6557. .ignore_pmdown_time = 1,
  6558. },
  6559. {
  6560. .name = LPASS_BE_PRI_SPDIF_TX,
  6561. .stream_name = "Primary SPDIF Capture",
  6562. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  6563. .platform_name = "msm-pcm-routing",
  6564. .codec_name = "msm-stub-codec.1",
  6565. .codec_dai_name = "msm-stub-tx",
  6566. .no_pcm = 1,
  6567. .dpcm_capture = 1,
  6568. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  6569. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6570. .ops = &msm_spdif_be_ops,
  6571. .ignore_suspend = 1,
  6572. },
  6573. {
  6574. .name = LPASS_BE_SEC_SPDIF_RX,
  6575. .stream_name = "Secondary SPDIF Playback",
  6576. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  6577. .platform_name = "msm-pcm-routing",
  6578. .codec_name = "msm-stub-codec.1",
  6579. .codec_dai_name = "msm-stub-rx",
  6580. .no_pcm = 1,
  6581. .dpcm_playback = 1,
  6582. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  6583. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6584. .ops = &msm_spdif_be_ops,
  6585. .ignore_suspend = 1,
  6586. .ignore_pmdown_time = 1,
  6587. },
  6588. {
  6589. .name = LPASS_BE_SEC_SPDIF_TX,
  6590. .stream_name = "Secondary SPDIF Capture",
  6591. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  6592. .platform_name = "msm-pcm-routing",
  6593. .codec_name = "msm-stub-codec.1",
  6594. .codec_dai_name = "msm-stub-tx",
  6595. .no_pcm = 1,
  6596. .dpcm_capture = 1,
  6597. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  6598. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6599. .ops = &msm_spdif_be_ops,
  6600. .ignore_suspend = 1,
  6601. },
  6602. };
  6603. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6604. ARRAY_SIZE(msm_common_dai_links) +
  6605. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6606. ARRAY_SIZE(msm_common_be_dai_links) +
  6607. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6608. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6609. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6610. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6611. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6612. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6613. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6614. ARRAY_SIZE(msm_spdif_be_dai_links)];
  6615. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6616. {
  6617. int ret = 0;
  6618. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6619. &service_nb);
  6620. if (ret < 0)
  6621. pr_err("%s: Audio notifier register failed ret = %d\n",
  6622. __func__, ret);
  6623. return ret;
  6624. }
  6625. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6626. struct snd_ctl_elem_value *ucontrol)
  6627. {
  6628. int ret = 0;
  6629. int port_id;
  6630. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6631. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6632. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6633. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6634. (vad_enable < 0) || (vad_enable > 1) ||
  6635. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6636. pr_err("%s: Invalid arguments\n", __func__);
  6637. ret = -EINVAL;
  6638. goto done;
  6639. }
  6640. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6641. vad_enable, preroll_config, vad_intf);
  6642. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6643. if (ret) {
  6644. pr_err("%s: Invalid vad interface\n", __func__);
  6645. goto done;
  6646. }
  6647. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6648. done:
  6649. return ret;
  6650. }
  6651. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6652. {
  6653. int ret = 0;
  6654. uint32_t tasha_codec = 0;
  6655. ret = afe_cal_init_hwdep(card);
  6656. if (ret) {
  6657. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6658. ret = 0;
  6659. }
  6660. /* tasha late probe when it is present */
  6661. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6662. &tasha_codec);
  6663. if (ret) {
  6664. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6665. ret = 0;
  6666. } else {
  6667. if (tasha_codec) {
  6668. ret = msm_snd_card_tasha_late_probe(card);
  6669. if (ret)
  6670. dev_err(card->dev, "%s: tasha late probe err\n",
  6671. __func__);
  6672. }
  6673. }
  6674. return ret;
  6675. }
  6676. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6677. .name = "qcs405-snd-card",
  6678. .controls = msm_snd_controls,
  6679. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6680. .late_probe = msm_snd_card_codec_late_probe,
  6681. };
  6682. static int msm_populate_dai_link_component_of_node(
  6683. struct snd_soc_card *card)
  6684. {
  6685. int i, index, ret = 0;
  6686. struct device *cdev = card->dev;
  6687. struct snd_soc_dai_link *dai_link = card->dai_link;
  6688. struct device_node *np;
  6689. if (!cdev) {
  6690. pr_err("%s: Sound card device memory NULL\n", __func__);
  6691. return -ENODEV;
  6692. }
  6693. for (i = 0; i < card->num_links; i++) {
  6694. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6695. continue;
  6696. /* populate platform_of_node for snd card dai links */
  6697. if (dai_link[i].platform_name &&
  6698. !dai_link[i].platform_of_node) {
  6699. index = of_property_match_string(cdev->of_node,
  6700. "asoc-platform-names",
  6701. dai_link[i].platform_name);
  6702. if (index < 0) {
  6703. pr_err("%s: No match found for platform name: %s\n",
  6704. __func__, dai_link[i].platform_name);
  6705. ret = index;
  6706. goto err;
  6707. }
  6708. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6709. index);
  6710. if (!np) {
  6711. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6712. __func__, dai_link[i].platform_name,
  6713. index);
  6714. ret = -ENODEV;
  6715. goto err;
  6716. }
  6717. dai_link[i].platform_of_node = np;
  6718. dai_link[i].platform_name = NULL;
  6719. }
  6720. /* populate cpu_of_node for snd card dai links */
  6721. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6722. index = of_property_match_string(cdev->of_node,
  6723. "asoc-cpu-names",
  6724. dai_link[i].cpu_dai_name);
  6725. if (index >= 0) {
  6726. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6727. index);
  6728. if (!np) {
  6729. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6730. __func__,
  6731. dai_link[i].cpu_dai_name);
  6732. ret = -ENODEV;
  6733. goto err;
  6734. }
  6735. dai_link[i].cpu_of_node = np;
  6736. dai_link[i].cpu_dai_name = NULL;
  6737. }
  6738. }
  6739. /* populate codec_of_node for snd card dai links */
  6740. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6741. index = of_property_match_string(cdev->of_node,
  6742. "asoc-codec-names",
  6743. dai_link[i].codec_name);
  6744. if (index < 0)
  6745. continue;
  6746. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6747. index);
  6748. if (!np) {
  6749. pr_err("%s: retrieving phandle for codec %s failed\n",
  6750. __func__, dai_link[i].codec_name);
  6751. ret = -ENODEV;
  6752. goto err;
  6753. }
  6754. dai_link[i].codec_of_node = np;
  6755. dai_link[i].codec_name = NULL;
  6756. }
  6757. }
  6758. err:
  6759. return ret;
  6760. }
  6761. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6762. /* FrontEnd DAI Links */
  6763. {
  6764. .name = "MSMSTUB Media1",
  6765. .stream_name = "MultiMedia1",
  6766. .cpu_dai_name = "MultiMedia1",
  6767. .platform_name = "msm-pcm-dsp.0",
  6768. .dynamic = 1,
  6769. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6770. .dpcm_playback = 1,
  6771. .dpcm_capture = 1,
  6772. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6773. SND_SOC_DPCM_TRIGGER_POST},
  6774. .codec_dai_name = "snd-soc-dummy-dai",
  6775. .codec_name = "snd-soc-dummy",
  6776. .ignore_suspend = 1,
  6777. /* this dainlink has playback support */
  6778. .ignore_pmdown_time = 1,
  6779. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6780. },
  6781. };
  6782. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6783. /* Backend DAI Links */
  6784. {
  6785. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6786. .stream_name = "VA CDC DMA0 Capture",
  6787. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6788. .platform_name = "msm-pcm-routing",
  6789. .codec_name = "bolero_codec",
  6790. .codec_dai_name = "va_macro_tx1",
  6791. .no_pcm = 1,
  6792. .dpcm_capture = 1,
  6793. .init = &msm_va_cdc_dma_init,
  6794. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6795. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6796. .ignore_suspend = 1,
  6797. .ops = &msm_cdc_dma_be_ops,
  6798. },
  6799. {
  6800. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6801. .stream_name = "VA CDC DMA1 Capture",
  6802. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6803. .platform_name = "msm-pcm-routing",
  6804. .codec_name = "bolero_codec",
  6805. .codec_dai_name = "va_macro_tx2",
  6806. .no_pcm = 1,
  6807. .dpcm_capture = 1,
  6808. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6809. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6810. .ignore_suspend = 1,
  6811. .ops = &msm_cdc_dma_be_ops,
  6812. },
  6813. };
  6814. static struct snd_soc_dai_link msm_stub_dai_links[
  6815. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6816. ARRAY_SIZE(msm_stub_be_dai_links)];
  6817. struct snd_soc_card snd_soc_card_stub_msm = {
  6818. .name = "qcs405-stub-snd-card",
  6819. };
  6820. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6821. { .compatible = "qcom,qcs405-asoc-snd",
  6822. .data = "codec"},
  6823. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6824. .data = "stub_codec"},
  6825. {},
  6826. };
  6827. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6828. {
  6829. struct snd_soc_card *card = NULL;
  6830. struct snd_soc_dai_link *dailink;
  6831. int total_links = 0;
  6832. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6833. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6834. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  6835. const struct of_device_id *match;
  6836. char __iomem *spdif_cfg, *spdif_pin_ctl;
  6837. int rc = 0;
  6838. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6839. if (!match) {
  6840. dev_err(dev, "%s: No DT match found for sound card\n",
  6841. __func__);
  6842. return NULL;
  6843. }
  6844. if (!strcmp(match->data, "codec")) {
  6845. card = &snd_soc_card_qcs405_msm;
  6846. memcpy(msm_qcs405_dai_links + total_links,
  6847. msm_common_dai_links,
  6848. sizeof(msm_common_dai_links));
  6849. total_links += ARRAY_SIZE(msm_common_dai_links);
  6850. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6851. &wsa_bolero_codec);
  6852. if (rc) {
  6853. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6854. __func__);
  6855. } else {
  6856. if (wsa_bolero_codec) {
  6857. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  6858. __func__);
  6859. memcpy(msm_qcs405_dai_links + total_links,
  6860. msm_bolero_fe_dai_links,
  6861. sizeof(msm_bolero_fe_dai_links));
  6862. total_links +=
  6863. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6864. }
  6865. }
  6866. memcpy(msm_qcs405_dai_links + total_links,
  6867. msm_common_misc_fe_dai_links,
  6868. sizeof(msm_common_misc_fe_dai_links));
  6869. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6870. memcpy(msm_qcs405_dai_links + total_links,
  6871. msm_common_be_dai_links,
  6872. sizeof(msm_common_be_dai_links));
  6873. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6874. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6875. &tasha_codec);
  6876. if (rc) {
  6877. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6878. __func__);
  6879. } else {
  6880. if (tasha_codec) {
  6881. memcpy(msm_qcs405_dai_links + total_links,
  6882. msm_tasha_be_dai_links,
  6883. sizeof(msm_tasha_be_dai_links));
  6884. total_links +=
  6885. ARRAY_SIZE(msm_tasha_be_dai_links);
  6886. }
  6887. }
  6888. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6889. &va_bolero_codec);
  6890. if (rc) {
  6891. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6892. __func__);
  6893. } else {
  6894. if (va_bolero_codec) {
  6895. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6896. __func__);
  6897. memcpy(msm_qcs405_dai_links + total_links,
  6898. msm_va_cdc_dma_be_dai_links,
  6899. sizeof(msm_va_cdc_dma_be_dai_links));
  6900. total_links +=
  6901. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6902. }
  6903. }
  6904. if (wsa_bolero_codec) {
  6905. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6906. __func__);
  6907. memcpy(msm_qcs405_dai_links + total_links,
  6908. msm_wsa_cdc_dma_be_dai_links,
  6909. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6910. total_links +=
  6911. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6912. }
  6913. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6914. &mi2s_audio_intf);
  6915. if (rc) {
  6916. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6917. __func__);
  6918. } else {
  6919. if (mi2s_audio_intf) {
  6920. memcpy(msm_qcs405_dai_links + total_links,
  6921. msm_mi2s_be_dai_links,
  6922. sizeof(msm_mi2s_be_dai_links));
  6923. total_links +=
  6924. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6925. }
  6926. }
  6927. rc = of_property_read_u32(dev->of_node,
  6928. "qcom,auxpcm-audio-intf",
  6929. &auxpcm_audio_intf);
  6930. if (rc) {
  6931. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6932. __func__);
  6933. } else {
  6934. if (auxpcm_audio_intf) {
  6935. memcpy(msm_qcs405_dai_links + total_links,
  6936. msm_auxpcm_be_dai_links,
  6937. sizeof(msm_auxpcm_be_dai_links));
  6938. total_links +=
  6939. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6940. }
  6941. }
  6942. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  6943. &spdif_audio_intf);
  6944. if (rc) {
  6945. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  6946. __func__);
  6947. } else {
  6948. if (spdif_audio_intf) {
  6949. memcpy(msm_qcs405_dai_links + total_links,
  6950. msm_spdif_be_dai_links,
  6951. sizeof(msm_spdif_be_dai_links));
  6952. total_links +=
  6953. ARRAY_SIZE(msm_spdif_be_dai_links);
  6954. /* enable spdif coax pins */
  6955. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  6956. spdif_pin_ctl =
  6957. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  6958. iowrite32(0xc0, spdif_cfg);
  6959. iowrite32(0x2220, spdif_pin_ctl);
  6960. }
  6961. }
  6962. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  6963. &wcn_audio_intf);
  6964. if (rc) {
  6965. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  6966. __func__);
  6967. } else {
  6968. if (wcn_audio_intf) {
  6969. memcpy(msm_qcs405_dai_links + total_links,
  6970. msm_wcn_be_dai_links,
  6971. sizeof(msm_wcn_be_dai_links));
  6972. total_links +=
  6973. ARRAY_SIZE(msm_wcn_be_dai_links);
  6974. }
  6975. }
  6976. dailink = msm_qcs405_dai_links;
  6977. } else if (!strcmp(match->data, "stub_codec")) {
  6978. card = &snd_soc_card_stub_msm;
  6979. memcpy(msm_stub_dai_links + total_links,
  6980. msm_stub_fe_dai_links,
  6981. sizeof(msm_stub_fe_dai_links));
  6982. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6983. memcpy(msm_stub_dai_links + total_links,
  6984. msm_stub_be_dai_links,
  6985. sizeof(msm_stub_be_dai_links));
  6986. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6987. dailink = msm_stub_dai_links;
  6988. }
  6989. if (card) {
  6990. card->dai_link = dailink;
  6991. card->num_links = total_links;
  6992. }
  6993. return card;
  6994. }
  6995. static int msm_wsa881x_init(struct snd_soc_component *component)
  6996. {
  6997. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6998. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6999. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  7000. SPKR_L_BOOST, SPKR_L_VI};
  7001. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  7002. SPKR_R_BOOST, SPKR_R_VI};
  7003. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  7004. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  7005. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7006. struct msm_asoc_mach_data *pdata;
  7007. struct snd_soc_dapm_context *dapm;
  7008. int ret = 0;
  7009. if (!codec) {
  7010. pr_err("%s codec is NULL\n", __func__);
  7011. return -EINVAL;
  7012. }
  7013. dapm = snd_soc_codec_get_dapm(codec);
  7014. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  7015. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  7016. __func__, codec->component.name);
  7017. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  7018. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7019. &ch_rate[0], &spkleft_port_types[0]);
  7020. if (dapm->component) {
  7021. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  7022. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  7023. }
  7024. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  7025. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  7026. __func__, codec->component.name);
  7027. wsa881x_set_channel_map(codec, &spkright_ports[0],
  7028. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7029. &ch_rate[0], &spkright_port_types[0]);
  7030. if (dapm->component) {
  7031. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7032. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7033. }
  7034. } else {
  7035. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  7036. codec->component.name);
  7037. ret = -EINVAL;
  7038. goto err;
  7039. }
  7040. pdata = snd_soc_card_get_drvdata(component->card);
  7041. if (pdata && pdata->codec_root)
  7042. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7043. codec);
  7044. err:
  7045. return ret;
  7046. }
  7047. static int msm_init_wsa_dev(struct platform_device *pdev,
  7048. struct snd_soc_card *card)
  7049. {
  7050. struct device_node *wsa_of_node;
  7051. u32 wsa_max_devs;
  7052. u32 wsa_dev_cnt;
  7053. int i;
  7054. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7055. const char *wsa_auxdev_name_prefix[1];
  7056. char *dev_name_str = NULL;
  7057. int found = 0;
  7058. int ret = 0;
  7059. /* Get maximum WSA device count for this platform */
  7060. ret = of_property_read_u32(pdev->dev.of_node,
  7061. "qcom,wsa-max-devs", &wsa_max_devs);
  7062. if (ret) {
  7063. dev_info(&pdev->dev,
  7064. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7065. __func__, pdev->dev.of_node->full_name, ret);
  7066. card->num_aux_devs = 0;
  7067. return 0;
  7068. }
  7069. if (wsa_max_devs == 0) {
  7070. dev_warn(&pdev->dev,
  7071. "%s: Max WSA devices is 0 for this target?\n",
  7072. __func__);
  7073. card->num_aux_devs = 0;
  7074. return 0;
  7075. }
  7076. /* Get count of WSA device phandles for this platform */
  7077. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7078. "qcom,wsa-devs", NULL);
  7079. if (wsa_dev_cnt == -ENOENT) {
  7080. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7081. __func__);
  7082. goto err;
  7083. } else if (wsa_dev_cnt <= 0) {
  7084. dev_err(&pdev->dev,
  7085. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7086. __func__, wsa_dev_cnt);
  7087. ret = -EINVAL;
  7088. goto err;
  7089. }
  7090. /*
  7091. * Expect total phandles count to be NOT less than maximum possible
  7092. * WSA count. However, if it is less, then assign same value to
  7093. * max count as well.
  7094. */
  7095. if (wsa_dev_cnt < wsa_max_devs) {
  7096. dev_dbg(&pdev->dev,
  7097. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7098. __func__, wsa_max_devs, wsa_dev_cnt);
  7099. wsa_max_devs = wsa_dev_cnt;
  7100. }
  7101. /* Make sure prefix string passed for each WSA device */
  7102. ret = of_property_count_strings(pdev->dev.of_node,
  7103. "qcom,wsa-aux-dev-prefix");
  7104. if (ret != wsa_dev_cnt) {
  7105. dev_err(&pdev->dev,
  7106. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7107. __func__, wsa_dev_cnt, ret);
  7108. ret = -EINVAL;
  7109. goto err;
  7110. }
  7111. /*
  7112. * Alloc mem to store phandle and index info of WSA device, if already
  7113. * registered with ALSA core
  7114. */
  7115. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7116. sizeof(struct msm_wsa881x_dev_info),
  7117. GFP_KERNEL);
  7118. if (!wsa881x_dev_info) {
  7119. ret = -ENOMEM;
  7120. goto err;
  7121. }
  7122. /*
  7123. * search and check whether all WSA devices are already
  7124. * registered with ALSA core or not. If found a node, store
  7125. * the node and the index in a local array of struct for later
  7126. * use.
  7127. */
  7128. for (i = 0; i < wsa_dev_cnt; i++) {
  7129. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7130. "qcom,wsa-devs", i);
  7131. if (unlikely(!wsa_of_node)) {
  7132. /* we should not be here */
  7133. dev_err(&pdev->dev,
  7134. "%s: wsa dev node is not present\n",
  7135. __func__);
  7136. ret = -EINVAL;
  7137. goto err_free_dev_info;
  7138. }
  7139. if (soc_find_component(wsa_of_node, NULL)) {
  7140. /* WSA device registered with ALSA core */
  7141. wsa881x_dev_info[found].of_node = wsa_of_node;
  7142. wsa881x_dev_info[found].index = i;
  7143. found++;
  7144. if (found == wsa_max_devs)
  7145. break;
  7146. }
  7147. }
  7148. if (found < wsa_max_devs) {
  7149. dev_err(&pdev->dev,
  7150. "%s: failed to find %d components. Found only %d\n",
  7151. __func__, wsa_max_devs, found);
  7152. return -EPROBE_DEFER;
  7153. }
  7154. dev_info(&pdev->dev,
  7155. "%s: found %d wsa881x devices registered with ALSA core\n",
  7156. __func__, found);
  7157. card->num_aux_devs = wsa_max_devs;
  7158. card->num_configs = wsa_max_devs;
  7159. /* Alloc array of AUX devs struct */
  7160. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7161. sizeof(struct snd_soc_aux_dev),
  7162. GFP_KERNEL);
  7163. if (!msm_aux_dev) {
  7164. ret = -ENOMEM;
  7165. goto err_free_dev_info;
  7166. }
  7167. /* Alloc array of codec conf struct */
  7168. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7169. sizeof(struct snd_soc_codec_conf),
  7170. GFP_KERNEL);
  7171. if (!msm_codec_conf) {
  7172. ret = -ENOMEM;
  7173. goto err_free_aux_dev;
  7174. }
  7175. for (i = 0; i < card->num_aux_devs; i++) {
  7176. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7177. GFP_KERNEL);
  7178. if (!dev_name_str) {
  7179. ret = -ENOMEM;
  7180. goto err_free_cdc_conf;
  7181. }
  7182. ret = of_property_read_string_index(pdev->dev.of_node,
  7183. "qcom,wsa-aux-dev-prefix",
  7184. wsa881x_dev_info[i].index,
  7185. wsa_auxdev_name_prefix);
  7186. if (ret) {
  7187. dev_err(&pdev->dev,
  7188. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7189. __func__, ret);
  7190. ret = -EINVAL;
  7191. goto err_free_dev_name_str;
  7192. }
  7193. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7194. msm_aux_dev[i].name = dev_name_str;
  7195. msm_aux_dev[i].codec_name = NULL;
  7196. msm_aux_dev[i].codec_of_node =
  7197. wsa881x_dev_info[i].of_node;
  7198. msm_aux_dev[i].init = msm_wsa881x_init;
  7199. msm_codec_conf[i].dev_name = NULL;
  7200. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7201. msm_codec_conf[i].of_node =
  7202. wsa881x_dev_info[i].of_node;
  7203. }
  7204. card->codec_conf = msm_codec_conf;
  7205. card->aux_dev = msm_aux_dev;
  7206. return 0;
  7207. err_free_dev_name_str:
  7208. devm_kfree(&pdev->dev, dev_name_str);
  7209. err_free_cdc_conf:
  7210. devm_kfree(&pdev->dev, msm_codec_conf);
  7211. err_free_aux_dev:
  7212. devm_kfree(&pdev->dev, msm_aux_dev);
  7213. err_free_dev_info:
  7214. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7215. err:
  7216. return ret;
  7217. }
  7218. static int msm_csra66x0_init(struct snd_soc_component *component)
  7219. {
  7220. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7221. if (!codec) {
  7222. pr_err("%s codec is NULL\n", __func__);
  7223. return -EINVAL;
  7224. }
  7225. return 0;
  7226. }
  7227. static int msm_init_csra_dev(struct platform_device *pdev,
  7228. struct snd_soc_card *card)
  7229. {
  7230. struct device_node *csra_of_node;
  7231. u32 csra_max_devs;
  7232. u32 csra_dev_cnt;
  7233. char *dev_name_str = NULL;
  7234. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7235. const char *csra_auxdev_name_prefix[1];
  7236. int i;
  7237. int found = 0;
  7238. int ret = 0;
  7239. /* Get maximum CSRA device count for this platform */
  7240. ret = of_property_read_u32(pdev->dev.of_node,
  7241. "qcom,csra-max-devs", &csra_max_devs);
  7242. if (ret) {
  7243. dev_info(&pdev->dev,
  7244. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7245. __func__, pdev->dev.of_node->full_name, ret);
  7246. card->num_aux_devs = 0;
  7247. return 0;
  7248. }
  7249. if (csra_max_devs == 0) {
  7250. dev_warn(&pdev->dev,
  7251. "%s: Max CSRA devices is 0 for this target?\n",
  7252. __func__);
  7253. return 0;
  7254. }
  7255. /* Get count of CSRA device phandles for this platform */
  7256. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7257. "qcom,csra-devs", NULL);
  7258. if (csra_dev_cnt == -ENOENT) {
  7259. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7260. __func__);
  7261. goto err;
  7262. } else if (csra_dev_cnt <= 0) {
  7263. dev_err(&pdev->dev,
  7264. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7265. __func__, csra_dev_cnt);
  7266. ret = -EINVAL;
  7267. goto err;
  7268. }
  7269. /*
  7270. * Expect total phandles count to be NOT less than maximum possible
  7271. * CSRA count. However, if it is less, then assign same value to
  7272. * max count as well.
  7273. */
  7274. if (csra_dev_cnt < csra_max_devs) {
  7275. dev_dbg(&pdev->dev,
  7276. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7277. __func__, csra_max_devs, csra_dev_cnt);
  7278. csra_max_devs = csra_dev_cnt;
  7279. }
  7280. /* Make sure prefix string passed for each CSRA device */
  7281. ret = of_property_count_strings(pdev->dev.of_node,
  7282. "qcom,csra-aux-dev-prefix");
  7283. if (ret != csra_dev_cnt) {
  7284. dev_err(&pdev->dev,
  7285. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7286. __func__, csra_dev_cnt, ret);
  7287. ret = -EINVAL;
  7288. goto err;
  7289. }
  7290. /*
  7291. * Alloc mem to store phandle and index info of CSRA device, if already
  7292. * registered with ALSA core
  7293. */
  7294. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7295. sizeof(struct msm_csra66x0_dev_info),
  7296. GFP_KERNEL);
  7297. if (!csra66x0_dev_info) {
  7298. ret = -ENOMEM;
  7299. goto err;
  7300. }
  7301. /*
  7302. * search and check whether all CSRA devices are already
  7303. * registered with ALSA core or not. If found a node, store
  7304. * the node and the index in a local array of struct for later
  7305. * use.
  7306. */
  7307. for (i = 0; i < csra_dev_cnt; i++) {
  7308. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7309. "qcom,csra-devs", i);
  7310. if (unlikely(!csra_of_node)) {
  7311. /* we should not be here */
  7312. dev_err(&pdev->dev,
  7313. "%s: csra dev node is not present\n",
  7314. __func__);
  7315. ret = -EINVAL;
  7316. goto err_free_dev_info;
  7317. }
  7318. if (soc_find_component(csra_of_node, NULL)) {
  7319. /* CSRA device registered with ALSA core */
  7320. csra66x0_dev_info[found].of_node = csra_of_node;
  7321. csra66x0_dev_info[found].index = i;
  7322. found++;
  7323. if (found == csra_max_devs)
  7324. break;
  7325. }
  7326. }
  7327. if (found < csra_max_devs) {
  7328. dev_dbg(&pdev->dev,
  7329. "%s: failed to find %d components. Found only %d\n",
  7330. __func__, csra_max_devs, found);
  7331. return -EPROBE_DEFER;
  7332. }
  7333. dev_info(&pdev->dev,
  7334. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7335. __func__, found);
  7336. card->num_aux_devs = csra_max_devs;
  7337. card->num_configs = csra_max_devs;
  7338. /* Alloc array of AUX devs struct */
  7339. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7340. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7341. if (!msm_aux_dev) {
  7342. ret = -ENOMEM;
  7343. goto err_free_dev_info;
  7344. }
  7345. /* Alloc array of codec conf struct */
  7346. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7347. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7348. if (!msm_codec_conf) {
  7349. ret = -ENOMEM;
  7350. goto err_free_aux_dev;
  7351. }
  7352. for (i = 0; i < card->num_aux_devs; i++) {
  7353. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7354. GFP_KERNEL);
  7355. if (!dev_name_str) {
  7356. ret = -ENOMEM;
  7357. goto err_free_cdc_conf;
  7358. }
  7359. ret = of_property_read_string_index(pdev->dev.of_node,
  7360. "qcom,csra-aux-dev-prefix",
  7361. csra66x0_dev_info[i].index,
  7362. csra_auxdev_name_prefix);
  7363. if (ret) {
  7364. dev_err(&pdev->dev,
  7365. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7366. __func__, ret);
  7367. ret = -EINVAL;
  7368. goto err_free_dev_name_str;
  7369. }
  7370. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7371. msm_aux_dev[i].name = dev_name_str;
  7372. msm_aux_dev[i].codec_name = NULL;
  7373. msm_aux_dev[i].codec_of_node =
  7374. csra66x0_dev_info[i].of_node;
  7375. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7376. msm_codec_conf[i].dev_name = NULL;
  7377. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7378. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7379. }
  7380. card->codec_conf = msm_codec_conf;
  7381. card->aux_dev = msm_aux_dev;
  7382. return 0;
  7383. err_free_dev_name_str:
  7384. devm_kfree(&pdev->dev, dev_name_str);
  7385. err_free_cdc_conf:
  7386. devm_kfree(&pdev->dev, msm_codec_conf);
  7387. err_free_aux_dev:
  7388. devm_kfree(&pdev->dev, msm_aux_dev);
  7389. err_free_dev_info:
  7390. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7391. err:
  7392. return ret;
  7393. }
  7394. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7395. {
  7396. int count;
  7397. u32 mi2s_master_slave[MI2S_MAX];
  7398. int ret;
  7399. for (count = 0; count < MI2S_MAX; count++) {
  7400. mutex_init(&mi2s_intf_conf[count].lock);
  7401. mi2s_intf_conf[count].ref_cnt = 0;
  7402. }
  7403. ret = of_property_read_u32_array(pdev->dev.of_node,
  7404. "qcom,msm-mi2s-master",
  7405. mi2s_master_slave, MI2S_MAX);
  7406. if (ret) {
  7407. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7408. __func__);
  7409. } else {
  7410. for (count = 0; count < MI2S_MAX; count++) {
  7411. mi2s_intf_conf[count].msm_is_mi2s_master =
  7412. mi2s_master_slave[count];
  7413. }
  7414. }
  7415. }
  7416. static void msm_i2s_auxpcm_deinit(void)
  7417. {
  7418. int count;
  7419. for (count = 0; count < MI2S_MAX; count++) {
  7420. mutex_destroy(&mi2s_intf_conf[count].lock);
  7421. mi2s_intf_conf[count].ref_cnt = 0;
  7422. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7423. }
  7424. }
  7425. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7426. uint32_t busnum, uint32_t addr)
  7427. {
  7428. struct i2c_adapter *adap;
  7429. u8 rbuf;
  7430. struct i2c_msg msg;
  7431. int status = 0;
  7432. adap = i2c_get_adapter(busnum);
  7433. if (!adap) {
  7434. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7435. __func__, busnum);
  7436. return -EBUSY;
  7437. }
  7438. /* to test presence, read one byte from device */
  7439. msg.addr = addr;
  7440. msg.flags = I2C_M_RD;
  7441. msg.len = 1;
  7442. msg.buf = &rbuf;
  7443. status = i2c_transfer(adap, &msg, 1);
  7444. i2c_put_adapter(adap);
  7445. if (status != 1) {
  7446. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  7447. __func__, addr);
  7448. return -ENODEV;
  7449. }
  7450. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  7451. __func__, addr);
  7452. return 0;
  7453. }
  7454. static int msm_detect_ep92_dev(struct platform_device *pdev,
  7455. struct snd_soc_card *card)
  7456. {
  7457. int i;
  7458. uint32_t ep92_busnum = 0;
  7459. uint32_t ep92_reg = 0;
  7460. const char *ep92_name = NULL;
  7461. struct snd_soc_dai_link *dai;
  7462. int rc = 0;
  7463. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  7464. &ep92_busnum);
  7465. if (rc) {
  7466. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  7467. return 0;
  7468. }
  7469. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  7470. &ep92_reg);
  7471. if (rc) {
  7472. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  7473. return 0;
  7474. }
  7475. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  7476. &ep92_name);
  7477. if (rc) {
  7478. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  7479. return 0;
  7480. }
  7481. /* check I2C bus for connected ep92 chip */
  7482. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7483. /* check a second time after a short delay */
  7484. msleep(20);
  7485. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7486. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  7487. __func__);
  7488. /* continue with snd_card registration without ep92 */
  7489. return 0;
  7490. }
  7491. }
  7492. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  7493. /* update codec info in MI2S dai link */
  7494. dai = &msm_mi2s_be_dai_links[0];
  7495. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  7496. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  7497. dev_dbg(&pdev->dev,
  7498. "%s: Set Sec MI2S dai to ep92 codec\n",
  7499. __func__);
  7500. dai->codec_name = ep92_name;
  7501. dai->codec_dai_name = "ep92-hdmi";
  7502. break;
  7503. }
  7504. dai++;
  7505. }
  7506. /* update codec info in SPDIF dai link */
  7507. dai = &msm_spdif_be_dai_links[0];
  7508. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  7509. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  7510. dev_dbg(&pdev->dev,
  7511. "%s: Set Sec SPDIF dai to ep92 codec\n",
  7512. __func__);
  7513. dai->codec_name = ep92_name;
  7514. dai->codec_dai_name = "ep92-arc";
  7515. break;
  7516. }
  7517. dai++;
  7518. }
  7519. return 0;
  7520. }
  7521. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7522. {
  7523. struct snd_soc_card *card;
  7524. struct msm_asoc_mach_data *pdata;
  7525. int ret;
  7526. u32 val;
  7527. if (!pdev->dev.of_node) {
  7528. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  7529. return -EINVAL;
  7530. }
  7531. pdata = devm_kzalloc(&pdev->dev,
  7532. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7533. if (!pdata)
  7534. return -ENOMEM;
  7535. /* test for ep92 HDMI bridge and update dai links accordingly */
  7536. ret = msm_detect_ep92_dev(pdev, card);
  7537. if (ret)
  7538. goto err;
  7539. card = populate_snd_card_dailinks(&pdev->dev);
  7540. if (!card) {
  7541. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7542. ret = -EINVAL;
  7543. goto err;
  7544. }
  7545. card->dev = &pdev->dev;
  7546. platform_set_drvdata(pdev, card);
  7547. snd_soc_card_set_drvdata(card, pdata);
  7548. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7549. if (ret) {
  7550. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  7551. ret);
  7552. goto err;
  7553. }
  7554. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7555. if (ret) {
  7556. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  7557. ret);
  7558. goto err;
  7559. }
  7560. ret = msm_populate_dai_link_component_of_node(card);
  7561. if (ret) {
  7562. ret = -EPROBE_DEFER;
  7563. goto err;
  7564. }
  7565. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  7566. if (ret) {
  7567. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  7568. val = 0;
  7569. }
  7570. if (val) {
  7571. ret = msm_init_csra_dev(pdev, card);
  7572. if (ret)
  7573. goto err;
  7574. } else {
  7575. ret = msm_init_wsa_dev(pdev, card);
  7576. if (ret)
  7577. goto err;
  7578. }
  7579. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7580. "qcom,cdc-dmic01-gpios",
  7581. 0);
  7582. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7583. "qcom,cdc-dmic23-gpios",
  7584. 0);
  7585. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7586. "qcom,cdc-dmic45-gpios",
  7587. 0);
  7588. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7589. "qcom,cdc-dmic67-gpios",
  7590. 0);
  7591. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7592. if (ret == -EPROBE_DEFER) {
  7593. if (codec_reg_done)
  7594. ret = -EINVAL;
  7595. goto err;
  7596. } else if (ret) {
  7597. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  7598. ret);
  7599. goto err;
  7600. }
  7601. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7602. spdev = pdev;
  7603. ret = msm_mdf_mem_init();
  7604. if (ret)
  7605. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  7606. ret);
  7607. /* Parse pinctrl info from devicetree */
  7608. ret = msm_get_pinctrl(pdev);
  7609. if (!ret) {
  7610. pr_debug("%s: pinctrl parsing successful\n", __func__);
  7611. } else {
  7612. dev_dbg(&pdev->dev,
  7613. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  7614. __func__, ret);
  7615. ret = 0;
  7616. }
  7617. msm_i2s_auxpcm_init(pdev);
  7618. is_initial_boot = true;
  7619. return 0;
  7620. err:
  7621. msm_release_pinctrl(pdev);
  7622. return ret;
  7623. }
  7624. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7625. {
  7626. audio_notifier_deregister("qcs405");
  7627. msm_i2s_auxpcm_deinit();
  7628. msm_mdf_mem_deinit();
  7629. msm_release_pinctrl(pdev);
  7630. return 0;
  7631. }
  7632. static struct platform_driver qcs405_asoc_machine_driver = {
  7633. .driver = {
  7634. .name = DRV_NAME,
  7635. .owner = THIS_MODULE,
  7636. .pm = &snd_soc_pm_ops,
  7637. .of_match_table = qcs405_asoc_machine_of_match,
  7638. },
  7639. .probe = msm_asoc_machine_probe,
  7640. .remove = msm_asoc_machine_remove,
  7641. };
  7642. module_platform_driver(qcs405_asoc_machine_driver);
  7643. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  7644. MODULE_LICENSE("GPL v2");
  7645. MODULE_ALIAS("platform:" DRV_NAME);
  7646. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);