hal_api.h 61 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_API_H_
  19. #define _HAL_API_H_
  20. #include "qdf_types.h"
  21. #include "qdf_util.h"
  22. #include "qdf_atomic.h"
  23. #include "hal_internal.h"
  24. #include "hif.h"
  25. #include "hif_io32.h"
  26. #include "qdf_platform.h"
  27. /* calculate the register address offset from bar0 of shadow register x */
  28. #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490)
  29. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x000008FC
  30. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  31. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  32. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  33. #elif defined(QCA_WIFI_QCA6290) || defined(QCA_WIFI_QCN9000)
  34. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x00003024
  35. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  36. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  37. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  38. #elif defined(QCA_WIFI_QCA6750)
  39. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x00000504
  40. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  41. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  42. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  43. #else
  44. #define SHADOW_REGISTER(x) 0
  45. #endif /* QCA_WIFI_QCA6390 || QCA_WIFI_QCA6490 || QCA_WIFI_QCA6750 */
  46. #define MAX_UNWINDOWED_ADDRESS 0x80000
  47. #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \
  48. defined(QCA_WIFI_QCN9000) || defined(QCA_WIFI_QCA6750)
  49. #define WINDOW_ENABLE_BIT 0x40000000
  50. #else
  51. #define WINDOW_ENABLE_BIT 0x80000000
  52. #endif
  53. #define WINDOW_REG_ADDRESS 0x310C
  54. #define WINDOW_SHIFT 19
  55. #define WINDOW_VALUE_MASK 0x3F
  56. #define WINDOW_START MAX_UNWINDOWED_ADDRESS
  57. #define WINDOW_RANGE_MASK 0x7FFFF
  58. /*
  59. * BAR + 4K is always accessible, any access outside this
  60. * space requires force wake procedure.
  61. * OFFSET = 4K - 32 bytes = 0xFE0
  62. */
  63. #define MAPPED_REF_OFF 0xFE0
  64. #ifdef ENABLE_VERBOSE_DEBUG
  65. static inline void
  66. hal_set_verbose_debug(bool flag)
  67. {
  68. is_hal_verbose_debug_enabled = flag;
  69. }
  70. #endif
  71. #ifdef ENABLE_HAL_SOC_STATS
  72. #define HAL_STATS_INC(_handle, _field, _delta) \
  73. { \
  74. if (likely(_handle)) \
  75. _handle->stats._field += _delta; \
  76. }
  77. #else
  78. #define HAL_STATS_INC(_handle, _field, _delta)
  79. #endif
  80. #ifdef ENABLE_HAL_REG_WR_HISTORY
  81. #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \
  82. hal_reg_wr_fail_history_add(hal_soc, offset, wr_val, rd_val)
  83. void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc,
  84. uint32_t offset,
  85. uint32_t wr_val,
  86. uint32_t rd_val);
  87. static inline int hal_history_get_next_index(qdf_atomic_t *table_index,
  88. int array_size)
  89. {
  90. int record_index = qdf_atomic_inc_return(table_index);
  91. return record_index & (array_size - 1);
  92. }
  93. #else
  94. #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \
  95. hal_err("write failed at reg offset 0x%x, write 0x%x read 0x%x\n", \
  96. offset, \
  97. wr_val, \
  98. rd_val)
  99. #endif
  100. /**
  101. * hal_reg_write_result_check() - check register writing result
  102. * @hal_soc: HAL soc handle
  103. * @offset: register offset to read
  104. * @exp_val: the expected value of register
  105. * @ret_confirm: result confirm flag
  106. *
  107. * Return: none
  108. */
  109. static inline void hal_reg_write_result_check(struct hal_soc *hal_soc,
  110. uint32_t offset,
  111. uint32_t exp_val)
  112. {
  113. uint32_t value;
  114. value = qdf_ioread32(hal_soc->dev_base_addr + offset);
  115. if (exp_val != value) {
  116. HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, exp_val, value);
  117. HAL_STATS_INC(hal_soc, reg_write_fail, 1);
  118. }
  119. }
  120. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) || \
  121. !defined(QCA_WIFI_QCA6750)
  122. static inline void hal_lock_reg_access(struct hal_soc *soc,
  123. unsigned long *flags)
  124. {
  125. qdf_spin_lock_irqsave(&soc->register_access_lock);
  126. }
  127. static inline void hal_unlock_reg_access(struct hal_soc *soc,
  128. unsigned long *flags)
  129. {
  130. qdf_spin_unlock_irqrestore(&soc->register_access_lock);
  131. }
  132. #else
  133. static inline void hal_lock_reg_access(struct hal_soc *soc,
  134. unsigned long *flags)
  135. {
  136. pld_lock_reg_window(soc->qdf_dev->dev, flags);
  137. }
  138. static inline void hal_unlock_reg_access(struct hal_soc *soc,
  139. unsigned long *flags)
  140. {
  141. pld_unlock_reg_window(soc->qdf_dev->dev, flags);
  142. }
  143. #endif
  144. #ifdef PCIE_REG_WINDOW_LOCAL_NO_CACHE
  145. static inline void hal_select_window(struct hal_soc *hal_soc, uint32_t offset)
  146. {
  147. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  148. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  149. WINDOW_ENABLE_BIT | window);
  150. hal_soc->register_window = window;
  151. }
  152. /**
  153. * hal_select_window_confirm() - write remap window register and
  154. check writing result
  155. *
  156. */
  157. static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
  158. uint32_t offset)
  159. {
  160. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  161. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  162. WINDOW_ENABLE_BIT | window);
  163. hal_soc->register_window = window;
  164. hal_reg_write_result_check(hal_soc, WINDOW_REG_ADDRESS,
  165. WINDOW_ENABLE_BIT | window);
  166. }
  167. #else
  168. static inline void hal_select_window(struct hal_soc *hal_soc, uint32_t offset)
  169. {
  170. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  171. if (window != hal_soc->register_window) {
  172. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  173. WINDOW_ENABLE_BIT | window);
  174. hal_soc->register_window = window;
  175. }
  176. }
  177. static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
  178. uint32_t offset)
  179. {
  180. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  181. if (window != hal_soc->register_window) {
  182. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  183. WINDOW_ENABLE_BIT | window);
  184. hal_soc->register_window = window;
  185. hal_reg_write_result_check(
  186. hal_soc,
  187. WINDOW_REG_ADDRESS,
  188. WINDOW_ENABLE_BIT | window);
  189. }
  190. }
  191. #endif
  192. static inline qdf_iomem_t hal_get_window_address(struct hal_soc *hal_soc,
  193. qdf_iomem_t addr)
  194. {
  195. return hal_soc->ops->hal_get_window_address(hal_soc, addr);
  196. }
  197. static inline void hal_tx_init_cmd_credit_ring(hal_soc_handle_t hal_soc_hdl,
  198. hal_ring_handle_t hal_ring_hdl)
  199. {
  200. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  201. return hal_soc->ops->hal_tx_init_cmd_credit_ring(hal_soc_hdl,
  202. hal_ring_hdl);
  203. }
  204. /**
  205. * hal_write32_mb() - Access registers to update configuration
  206. * @hal_soc: hal soc handle
  207. * @offset: offset address from the BAR
  208. * @value: value to write
  209. *
  210. * Return: None
  211. *
  212. * Description: Register address space is split below:
  213. * SHADOW REGION UNWINDOWED REGION WINDOWED REGION
  214. * |--------------------|-------------------|------------------|
  215. * BAR NO FORCE WAKE BAR+4K FORCE WAKE BAR+512K FORCE WAKE
  216. *
  217. * 1. Any access to the shadow region, doesn't need force wake
  218. * and windowing logic to access.
  219. * 2. Any access beyond BAR + 4K:
  220. * If init_phase enabled, no force wake is needed and access
  221. * should be based on windowed or unwindowed access.
  222. * If init_phase disabled, force wake is needed and access
  223. * should be based on windowed or unwindowed access.
  224. *
  225. * note1: WINDOW_RANGE_MASK = (1 << WINDOW_SHIFT) -1
  226. * note2: 1 << WINDOW_SHIFT = MAX_UNWINDOWED_ADDRESS
  227. * note3: WINDOW_VALUE_MASK = big enough that trying to write past
  228. * that window would be a bug
  229. */
  230. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
  231. !defined(QCA_WIFI_QCA6750)
  232. static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
  233. uint32_t value)
  234. {
  235. unsigned long flags;
  236. qdf_iomem_t new_addr;
  237. if (!hal_soc->use_register_windowing ||
  238. offset < MAX_UNWINDOWED_ADDRESS) {
  239. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  240. } else if (hal_soc->static_window_map) {
  241. new_addr = hal_get_window_address(hal_soc,
  242. hal_soc->dev_base_addr + offset);
  243. qdf_iowrite32(new_addr, value);
  244. } else {
  245. hal_lock_reg_access(hal_soc, &flags);
  246. hal_select_window(hal_soc, offset);
  247. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  248. (offset & WINDOW_RANGE_MASK), value);
  249. hal_unlock_reg_access(hal_soc, &flags);
  250. }
  251. }
  252. #define hal_write32_mb_confirm(_hal_soc, _offset, _value) \
  253. hal_write32_mb(_hal_soc, _offset, _value)
  254. #else
  255. static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
  256. uint32_t value)
  257. {
  258. int ret;
  259. unsigned long flags;
  260. qdf_iomem_t new_addr;
  261. /* Region < BAR + 4K can be directly accessed */
  262. if (offset < MAPPED_REF_OFF) {
  263. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  264. return;
  265. }
  266. /* Region greater than BAR + 4K */
  267. if (!hal_soc->init_phase) {
  268. ret = hif_force_wake_request(hal_soc->hif_handle);
  269. if (ret) {
  270. hal_err("Wake up request failed");
  271. qdf_check_state_before_panic();
  272. return;
  273. }
  274. }
  275. if (!hal_soc->use_register_windowing ||
  276. offset < MAX_UNWINDOWED_ADDRESS) {
  277. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  278. } else if (hal_soc->static_window_map) {
  279. new_addr = hal_get_window_address(
  280. hal_soc,
  281. hal_soc->dev_base_addr + offset);
  282. qdf_iowrite32(new_addr, value);
  283. } else {
  284. hal_lock_reg_access(hal_soc, &flags);
  285. hal_select_window(hal_soc, offset);
  286. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  287. (offset & WINDOW_RANGE_MASK), value);
  288. hal_unlock_reg_access(hal_soc, &flags);
  289. }
  290. if (!hal_soc->init_phase) {
  291. ret = hif_force_wake_release(hal_soc->hif_handle);
  292. if (ret) {
  293. hal_err("Wake up release failed");
  294. qdf_check_state_before_panic();
  295. return;
  296. }
  297. }
  298. }
  299. /**
  300. * hal_write32_mb_confirm() - write register and check wirting result
  301. *
  302. */
  303. static inline void hal_write32_mb_confirm(struct hal_soc *hal_soc,
  304. uint32_t offset,
  305. uint32_t value)
  306. {
  307. int ret;
  308. unsigned long flags;
  309. qdf_iomem_t new_addr;
  310. /* Region < BAR + 4K can be directly accessed */
  311. if (offset < MAPPED_REF_OFF) {
  312. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  313. return;
  314. }
  315. /* Region greater than BAR + 4K */
  316. if (!hal_soc->init_phase) {
  317. ret = hif_force_wake_request(hal_soc->hif_handle);
  318. if (ret) {
  319. hal_err("Wake up request failed");
  320. qdf_check_state_before_panic();
  321. return;
  322. }
  323. }
  324. if (!hal_soc->use_register_windowing ||
  325. offset < MAX_UNWINDOWED_ADDRESS) {
  326. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  327. hal_reg_write_result_check(hal_soc, offset,
  328. value);
  329. } else if (hal_soc->static_window_map) {
  330. new_addr = hal_get_window_address(
  331. hal_soc,
  332. hal_soc->dev_base_addr + offset);
  333. qdf_iowrite32(new_addr, value);
  334. hal_reg_write_result_check(hal_soc,
  335. new_addr - hal_soc->dev_base_addr,
  336. value);
  337. } else {
  338. hal_lock_reg_access(hal_soc, &flags);
  339. hal_select_window_confirm(hal_soc, offset);
  340. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  341. (offset & WINDOW_RANGE_MASK), value);
  342. hal_reg_write_result_check(
  343. hal_soc,
  344. WINDOW_START + (offset & WINDOW_RANGE_MASK),
  345. value);
  346. hal_unlock_reg_access(hal_soc, &flags);
  347. }
  348. if (!hal_soc->init_phase) {
  349. ret = hif_force_wake_release(hal_soc->hif_handle);
  350. if (ret) {
  351. hal_err("Wake up release failed");
  352. qdf_check_state_before_panic();
  353. return;
  354. }
  355. }
  356. }
  357. #endif
  358. /**
  359. * hal_write_address_32_mb - write a value to a register
  360. *
  361. */
  362. static inline
  363. void hal_write_address_32_mb(struct hal_soc *hal_soc,
  364. qdf_iomem_t addr, uint32_t value, bool wr_confirm)
  365. {
  366. uint32_t offset;
  367. if (!hal_soc->use_register_windowing)
  368. return qdf_iowrite32(addr, value);
  369. offset = addr - hal_soc->dev_base_addr;
  370. if (qdf_unlikely(wr_confirm))
  371. hal_write32_mb_confirm(hal_soc, offset, value);
  372. else
  373. hal_write32_mb(hal_soc, offset, value);
  374. }
  375. #ifdef DP_HAL_MULTIWINDOW_DIRECT_ACCESS
  376. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  377. struct hal_srng *srng,
  378. void __iomem *addr,
  379. uint32_t value)
  380. {
  381. qdf_iowrite32(addr, value);
  382. }
  383. #elif defined(FEATURE_HAL_DELAYED_REG_WRITE)
  384. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  385. struct hal_srng *srng,
  386. void __iomem *addr,
  387. uint32_t value)
  388. {
  389. hal_delayed_reg_write(hal_soc, srng, addr, value);
  390. }
  391. #else
  392. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  393. struct hal_srng *srng,
  394. void __iomem *addr,
  395. uint32_t value)
  396. {
  397. hal_write_address_32_mb(hal_soc, addr, value, false);
  398. }
  399. #endif
  400. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
  401. !defined(QCA_WIFI_QCA6750)
  402. /**
  403. * hal_read32_mb() - Access registers to read configuration
  404. * @hal_soc: hal soc handle
  405. * @offset: offset address from the BAR
  406. * @value: value to write
  407. *
  408. * Description: Register address space is split below:
  409. * SHADOW REGION UNWINDOWED REGION WINDOWED REGION
  410. * |--------------------|-------------------|------------------|
  411. * BAR NO FORCE WAKE BAR+4K FORCE WAKE BAR+512K FORCE WAKE
  412. *
  413. * 1. Any access to the shadow region, doesn't need force wake
  414. * and windowing logic to access.
  415. * 2. Any access beyond BAR + 4K:
  416. * If init_phase enabled, no force wake is needed and access
  417. * should be based on windowed or unwindowed access.
  418. * If init_phase disabled, force wake is needed and access
  419. * should be based on windowed or unwindowed access.
  420. *
  421. * Return: < 0 for failure/>= 0 for success
  422. */
  423. static inline uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
  424. {
  425. uint32_t ret;
  426. unsigned long flags;
  427. qdf_iomem_t new_addr;
  428. if (!hal_soc->use_register_windowing ||
  429. offset < MAX_UNWINDOWED_ADDRESS) {
  430. return qdf_ioread32(hal_soc->dev_base_addr + offset);
  431. } else if (hal_soc->static_window_map) {
  432. new_addr = hal_get_window_address(hal_soc, hal_soc->dev_base_addr + offset);
  433. return qdf_ioread32(new_addr);
  434. }
  435. hal_lock_reg_access(hal_soc, &flags);
  436. hal_select_window(hal_soc, offset);
  437. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  438. (offset & WINDOW_RANGE_MASK));
  439. hal_unlock_reg_access(hal_soc, &flags);
  440. return ret;
  441. }
  442. #else
  443. static
  444. uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
  445. {
  446. uint32_t ret;
  447. unsigned long flags;
  448. qdf_iomem_t new_addr;
  449. /* Region < BAR + 4K can be directly accessed */
  450. if (offset < MAPPED_REF_OFF)
  451. return qdf_ioread32(hal_soc->dev_base_addr + offset);
  452. if ((!hal_soc->init_phase) &&
  453. hif_force_wake_request(hal_soc->hif_handle)) {
  454. hal_err("Wake up request failed");
  455. qdf_check_state_before_panic();
  456. return 0;
  457. }
  458. if (!hal_soc->use_register_windowing ||
  459. offset < MAX_UNWINDOWED_ADDRESS) {
  460. ret = qdf_ioread32(hal_soc->dev_base_addr + offset);
  461. } else if (hal_soc->static_window_map) {
  462. new_addr = hal_get_window_address(
  463. hal_soc,
  464. hal_soc->dev_base_addr + offset);
  465. ret = qdf_ioread32(new_addr);
  466. } else {
  467. hal_lock_reg_access(hal_soc, &flags);
  468. hal_select_window(hal_soc, offset);
  469. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  470. (offset & WINDOW_RANGE_MASK));
  471. hal_unlock_reg_access(hal_soc, &flags);
  472. }
  473. if ((!hal_soc->init_phase) &&
  474. hif_force_wake_release(hal_soc->hif_handle)) {
  475. hal_err("Wake up release failed");
  476. qdf_check_state_before_panic();
  477. return 0;
  478. }
  479. return ret;
  480. }
  481. #endif
  482. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  483. /**
  484. * hal_dump_reg_write_srng_stats() - dump SRNG reg write stats
  485. * @hal_soc: HAL soc handle
  486. *
  487. * Return: none
  488. */
  489. void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl);
  490. /**
  491. * hal_dump_reg_write_stats() - dump reg write stats
  492. * @hal_soc: HAL soc handle
  493. *
  494. * Return: none
  495. */
  496. void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl);
  497. /**
  498. * hal_get_reg_write_pending_work() - get the number of entries
  499. * pending in the workqueue to be processed.
  500. * @hal_soc: HAL soc handle
  501. *
  502. * Returns: the number of entries pending to be processed
  503. */
  504. int hal_get_reg_write_pending_work(void *hal_soc);
  505. #else
  506. static inline void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
  507. {
  508. }
  509. static inline void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
  510. {
  511. }
  512. static inline int hal_get_reg_write_pending_work(void *hal_soc)
  513. {
  514. return 0;
  515. }
  516. #endif
  517. /**
  518. * hal_read_address_32_mb() - Read 32-bit value from the register
  519. * @soc: soc handle
  520. * @addr: register address to read
  521. *
  522. * Return: 32-bit value
  523. */
  524. static inline
  525. uint32_t hal_read_address_32_mb(struct hal_soc *soc,
  526. qdf_iomem_t addr)
  527. {
  528. uint32_t offset;
  529. uint32_t ret;
  530. if (!soc->use_register_windowing)
  531. return qdf_ioread32(addr);
  532. offset = addr - soc->dev_base_addr;
  533. ret = hal_read32_mb(soc, offset);
  534. return ret;
  535. }
  536. /**
  537. * hal_attach - Initialize HAL layer
  538. * @hif_handle: Opaque HIF handle
  539. * @qdf_dev: QDF device
  540. *
  541. * Return: Opaque HAL SOC handle
  542. * NULL on failure (if given ring is not available)
  543. *
  544. * This function should be called as part of HIF initialization (for accessing
  545. * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle()
  546. */
  547. void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev);
  548. /**
  549. * hal_detach - Detach HAL layer
  550. * @hal_soc: HAL SOC handle
  551. *
  552. * This function should be called as part of HIF detach
  553. *
  554. */
  555. extern void hal_detach(void *hal_soc);
  556. /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */
  557. enum hal_ring_type {
  558. REO_DST = 0,
  559. REO_EXCEPTION = 1,
  560. REO_REINJECT = 2,
  561. REO_CMD = 3,
  562. REO_STATUS = 4,
  563. TCL_DATA = 5,
  564. TCL_CMD_CREDIT = 6,
  565. TCL_STATUS = 7,
  566. CE_SRC = 8,
  567. CE_DST = 9,
  568. CE_DST_STATUS = 10,
  569. WBM_IDLE_LINK = 11,
  570. SW2WBM_RELEASE = 12,
  571. WBM2SW_RELEASE = 13,
  572. RXDMA_BUF = 14,
  573. RXDMA_DST = 15,
  574. RXDMA_MONITOR_BUF = 16,
  575. RXDMA_MONITOR_STATUS = 17,
  576. RXDMA_MONITOR_DST = 18,
  577. RXDMA_MONITOR_DESC = 19,
  578. DIR_BUF_RX_DMA_SRC = 20,
  579. #ifdef WLAN_FEATURE_CIF_CFR
  580. WIFI_POS_SRC,
  581. #endif
  582. MAX_RING_TYPES
  583. };
  584. #define HAL_SRNG_LMAC_RING 0x80000000
  585. /* SRNG flags passed in hal_srng_params.flags */
  586. #define HAL_SRNG_MSI_SWAP 0x00000008
  587. #define HAL_SRNG_RING_PTR_SWAP 0x00000010
  588. #define HAL_SRNG_DATA_TLV_SWAP 0x00000020
  589. #define HAL_SRNG_LOW_THRES_INTR_ENABLE 0x00010000
  590. #define HAL_SRNG_MSI_INTR 0x00020000
  591. #define HAL_SRNG_CACHED_DESC 0x00040000
  592. #ifdef QCA_WIFI_QCA6490
  593. #define HAL_SRNG_PREFETCH_TIMER 1
  594. #else
  595. #define HAL_SRNG_PREFETCH_TIMER 0
  596. #endif
  597. #define PN_SIZE_24 0
  598. #define PN_SIZE_48 1
  599. #define PN_SIZE_128 2
  600. #ifdef FORCE_WAKE
  601. /**
  602. * hal_set_init_phase() - Indicate initialization of
  603. * datapath rings
  604. * @soc: hal_soc handle
  605. * @init_phase: flag to indicate datapath rings
  606. * initialization status
  607. *
  608. * Return: None
  609. */
  610. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase);
  611. #else
  612. static inline
  613. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase)
  614. {
  615. }
  616. #endif /* FORCE_WAKE */
  617. /**
  618. * hal_srng_get_entrysize - Returns size of ring entry in bytes. Should be
  619. * used by callers for calculating the size of memory to be allocated before
  620. * calling hal_srng_setup to setup the ring
  621. *
  622. * @hal_soc: Opaque HAL SOC handle
  623. * @ring_type: one of the types from hal_ring_type
  624. *
  625. */
  626. extern uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type);
  627. /**
  628. * hal_srng_max_entries - Returns maximum possible number of ring entries
  629. * @hal_soc: Opaque HAL SOC handle
  630. * @ring_type: one of the types from hal_ring_type
  631. *
  632. * Return: Maximum number of entries for the given ring_type
  633. */
  634. uint32_t hal_srng_max_entries(void *hal_soc, int ring_type);
  635. /**
  636. * hal_srng_dump - Dump ring status
  637. * @srng: hal srng pointer
  638. */
  639. void hal_srng_dump(struct hal_srng *srng);
  640. /**
  641. * hal_srng_get_dir - Returns the direction of the ring
  642. * @hal_soc: Opaque HAL SOC handle
  643. * @ring_type: one of the types from hal_ring_type
  644. *
  645. * Return: Ring direction
  646. */
  647. enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type);
  648. /* HAL memory information */
  649. struct hal_mem_info {
  650. /* dev base virutal addr */
  651. void *dev_base_addr;
  652. /* dev base physical addr */
  653. void *dev_base_paddr;
  654. /* Remote virtual pointer memory for HW/FW updates */
  655. void *shadow_rdptr_mem_vaddr;
  656. /* Remote physical pointer memory for HW/FW updates */
  657. void *shadow_rdptr_mem_paddr;
  658. /* Shared memory for ring pointer updates from host to FW */
  659. void *shadow_wrptr_mem_vaddr;
  660. /* Shared physical memory for ring pointer updates from host to FW */
  661. void *shadow_wrptr_mem_paddr;
  662. };
  663. /* SRNG parameters to be passed to hal_srng_setup */
  664. struct hal_srng_params {
  665. /* Physical base address of the ring */
  666. qdf_dma_addr_t ring_base_paddr;
  667. /* Virtual base address of the ring */
  668. void *ring_base_vaddr;
  669. /* Number of entries in ring */
  670. uint32_t num_entries;
  671. /* max transfer length */
  672. uint16_t max_buffer_length;
  673. /* MSI Address */
  674. qdf_dma_addr_t msi_addr;
  675. /* MSI data */
  676. uint32_t msi_data;
  677. /* Interrupt timer threshold – in micro seconds */
  678. uint32_t intr_timer_thres_us;
  679. /* Interrupt batch counter threshold – in number of ring entries */
  680. uint32_t intr_batch_cntr_thres_entries;
  681. /* Low threshold – in number of ring entries
  682. * (valid for src rings only)
  683. */
  684. uint32_t low_threshold;
  685. /* Misc flags */
  686. uint32_t flags;
  687. /* Unique ring id */
  688. uint8_t ring_id;
  689. /* Source or Destination ring */
  690. enum hal_srng_dir ring_dir;
  691. /* Size of ring entry */
  692. uint32_t entry_size;
  693. /* hw register base address */
  694. void *hwreg_base[MAX_SRNG_REG_GROUPS];
  695. /* prefetch timer config - in micro seconds */
  696. uint32_t prefetch_timer;
  697. };
  698. /* hal_construct_shadow_config() - initialize the shadow registers for dp rings
  699. * @hal_soc: hal handle
  700. *
  701. * Return: QDF_STATUS_OK on success
  702. */
  703. extern QDF_STATUS hal_construct_shadow_config(void *hal_soc);
  704. /* hal_set_one_shadow_config() - add a config for the specified ring
  705. * @hal_soc: hal handle
  706. * @ring_type: ring type
  707. * @ring_num: ring num
  708. *
  709. * The ring type and ring num uniquely specify the ring. After this call,
  710. * the hp/tp will be added as the next entry int the shadow register
  711. * configuration table. The hal code will use the shadow register address
  712. * in place of the hp/tp address.
  713. *
  714. * This function is exposed, so that the CE module can skip configuring shadow
  715. * registers for unused ring and rings assigned to the firmware.
  716. *
  717. * Return: QDF_STATUS_OK on success
  718. */
  719. extern QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type,
  720. int ring_num);
  721. /**
  722. * hal_get_shadow_config() - retrieve the config table
  723. * @hal_soc: hal handle
  724. * @shadow_config: will point to the table after
  725. * @num_shadow_registers_configured: will contain the number of valid entries
  726. */
  727. extern void hal_get_shadow_config(void *hal_soc,
  728. struct pld_shadow_reg_v2_cfg **shadow_config,
  729. int *num_shadow_registers_configured);
  730. /**
  731. * hal_srng_setup - Initialize HW SRNG ring.
  732. *
  733. * @hal_soc: Opaque HAL SOC handle
  734. * @ring_type: one of the types from hal_ring_type
  735. * @ring_num: Ring number if there are multiple rings of
  736. * same type (staring from 0)
  737. * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
  738. * @ring_params: SRNG ring params in hal_srng_params structure.
  739. * Callers are expected to allocate contiguous ring memory of size
  740. * 'num_entries * entry_size' bytes and pass the physical and virtual base
  741. * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in hal_srng_params
  742. * structure. Ring base address should be 8 byte aligned and size of each ring
  743. * entry should be queried using the API hal_srng_get_entrysize
  744. *
  745. * Return: Opaque pointer to ring on success
  746. * NULL on failure (if given ring is not available)
  747. */
  748. extern void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
  749. int mac_id, struct hal_srng_params *ring_params);
  750. /* Remapping ids of REO rings */
  751. #define REO_REMAP_TCL 0
  752. #define REO_REMAP_SW1 1
  753. #define REO_REMAP_SW2 2
  754. #define REO_REMAP_SW3 3
  755. #define REO_REMAP_SW4 4
  756. #define REO_REMAP_RELEASE 5
  757. #define REO_REMAP_FW 6
  758. #define REO_REMAP_UNUSED 7
  759. /*
  760. * Macro to access HWIO_REO_R0_ERROR_DESTINATION_RING_CTRL_IX_0
  761. * to map destination to rings
  762. */
  763. #define HAL_REO_ERR_REMAP_IX0(_VALUE, _OFFSET) \
  764. ((_VALUE) << \
  765. (HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_ ## \
  766. DESTINATION_RING_ ## _OFFSET ## _SHFT))
  767. /*
  768. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0
  769. * to map destination to rings
  770. */
  771. #define HAL_REO_REMAP_IX0(_VALUE, _OFFSET) \
  772. ((_VALUE) << \
  773. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_ ## \
  774. _OFFSET ## _SHFT))
  775. /*
  776. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1
  777. * to map destination to rings
  778. */
  779. #define HAL_REO_REMAP_IX2(_VALUE, _OFFSET) \
  780. ((_VALUE) << \
  781. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_ ## \
  782. _OFFSET ## _SHFT))
  783. /*
  784. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3
  785. * to map destination to rings
  786. */
  787. #define HAL_REO_REMAP_IX3(_VALUE, _OFFSET) \
  788. ((_VALUE) << \
  789. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_ ## \
  790. _OFFSET ## _SHFT))
  791. /**
  792. * hal_reo_read_write_ctrl_ix - Read or write REO_DESTINATION_RING_CTRL_IX
  793. * @hal_soc_hdl: HAL SOC handle
  794. * @read: boolean value to indicate if read or write
  795. * @ix0: pointer to store IX0 reg value
  796. * @ix1: pointer to store IX1 reg value
  797. * @ix2: pointer to store IX2 reg value
  798. * @ix3: pointer to store IX3 reg value
  799. */
  800. void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read,
  801. uint32_t *ix0, uint32_t *ix1,
  802. uint32_t *ix2, uint32_t *ix3);
  803. /**
  804. * hal_srng_set_hp_paddr() - Set physical address to dest SRNG head pointer
  805. * @sring: sring pointer
  806. * @paddr: physical address
  807. */
  808. extern void hal_srng_dst_set_hp_paddr(struct hal_srng *sring, uint64_t paddr);
  809. /**
  810. * hal_srng_dst_init_hp() - Initilaize head pointer with cached head pointer
  811. * @srng: sring pointer
  812. * @vaddr: virtual address
  813. */
  814. extern void hal_srng_dst_init_hp(struct hal_srng *srng, uint32_t *vaddr);
  815. /**
  816. * hal_srng_cleanup - Deinitialize HW SRNG ring.
  817. * @hal_soc: Opaque HAL SOC handle
  818. * @hal_srng: Opaque HAL SRNG pointer
  819. */
  820. void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl);
  821. static inline bool hal_srng_initialized(hal_ring_handle_t hal_ring_hdl)
  822. {
  823. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  824. return !!srng->initialized;
  825. }
  826. /**
  827. * hal_srng_dst_peek - Check if there are any entries in the ring (peek)
  828. * @hal_soc: Opaque HAL SOC handle
  829. * @hal_ring_hdl: Destination ring pointer
  830. *
  831. * Caller takes responsibility for any locking needs.
  832. *
  833. * Return: Opaque pointer for next ring entry; NULL on failire
  834. */
  835. static inline
  836. void *hal_srng_dst_peek(hal_soc_handle_t hal_soc_hdl,
  837. hal_ring_handle_t hal_ring_hdl)
  838. {
  839. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  840. if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp)
  841. return (void *)(&srng->ring_base_vaddr[srng->u.dst_ring.tp]);
  842. return NULL;
  843. }
  844. /**
  845. * hal_srng_access_start_unlocked - Start ring access (unlocked). Should use
  846. * hal_srng_access_start if locked access is required
  847. *
  848. * @hal_soc: Opaque HAL SOC handle
  849. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  850. *
  851. * Return: 0 on success; error on failire
  852. */
  853. static inline int
  854. hal_srng_access_start_unlocked(hal_soc_handle_t hal_soc_hdl,
  855. hal_ring_handle_t hal_ring_hdl)
  856. {
  857. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  858. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  859. uint32_t *desc;
  860. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  861. srng->u.src_ring.cached_tp =
  862. *(volatile uint32_t *)(srng->u.src_ring.tp_addr);
  863. else {
  864. srng->u.dst_ring.cached_hp =
  865. *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  866. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  867. desc = hal_srng_dst_peek(hal_soc_hdl, hal_ring_hdl);
  868. if (qdf_likely(desc)) {
  869. qdf_mem_dma_cache_sync(soc->qdf_dev,
  870. qdf_mem_virt_to_phys
  871. (desc),
  872. QDF_DMA_FROM_DEVICE,
  873. (srng->entry_size *
  874. sizeof(uint32_t)));
  875. qdf_prefetch(desc);
  876. }
  877. }
  878. }
  879. return 0;
  880. }
  881. /**
  882. * hal_srng_access_start - Start (locked) ring access
  883. *
  884. * @hal_soc: Opaque HAL SOC handle
  885. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  886. *
  887. * Return: 0 on success; error on failire
  888. */
  889. static inline int hal_srng_access_start(hal_soc_handle_t hal_soc_hdl,
  890. hal_ring_handle_t hal_ring_hdl)
  891. {
  892. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  893. if (qdf_unlikely(!hal_ring_hdl)) {
  894. qdf_print("Error: Invalid hal_ring\n");
  895. return -EINVAL;
  896. }
  897. SRNG_LOCK(&(srng->lock));
  898. return hal_srng_access_start_unlocked(hal_soc_hdl, hal_ring_hdl);
  899. }
  900. /**
  901. * hal_srng_dst_get_next - Get next entry from a destination ring
  902. * @hal_soc: Opaque HAL SOC handle
  903. * @hal_ring_hdl: Destination ring pointer
  904. *
  905. * Return: Opaque pointer for next ring entry; NULL on failure
  906. */
  907. static inline
  908. void *hal_srng_dst_get_next(void *hal_soc,
  909. hal_ring_handle_t hal_ring_hdl)
  910. {
  911. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  912. uint32_t *desc;
  913. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  914. return NULL;
  915. desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  916. /* TODO: Using % is expensive, but we have to do this since
  917. * size of some SRNG rings is not power of 2 (due to descriptor
  918. * sizes). Need to create separate API for rings used
  919. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  920. * SW2RXDMA and CE rings)
  921. */
  922. srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size);
  923. if (srng->u.dst_ring.tp == srng->ring_size)
  924. srng->u.dst_ring.tp = 0;
  925. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  926. struct hal_soc *soc = (struct hal_soc *)hal_soc;
  927. uint32_t *desc_next;
  928. uint32_t tp;
  929. tp = srng->u.dst_ring.tp;
  930. desc_next = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  931. qdf_mem_dma_cache_sync(soc->qdf_dev,
  932. qdf_mem_virt_to_phys(desc_next),
  933. QDF_DMA_FROM_DEVICE,
  934. (srng->entry_size *
  935. sizeof(uint32_t)));
  936. qdf_prefetch(desc_next);
  937. }
  938. return (void *)desc;
  939. }
  940. /**
  941. * hal_srng_dst_get_next_cached - Get cached next entry
  942. * @hal_soc: Opaque HAL SOC handle
  943. * @hal_ring_hdl: Destination ring pointer
  944. *
  945. * Get next entry from a destination ring and move cached tail pointer
  946. *
  947. * Return: Opaque pointer for next ring entry; NULL on failure
  948. */
  949. static inline
  950. void *hal_srng_dst_get_next_cached(void *hal_soc,
  951. hal_ring_handle_t hal_ring_hdl)
  952. {
  953. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  954. uint32_t *desc;
  955. uint32_t *desc_next;
  956. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  957. return NULL;
  958. desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  959. /* TODO: Using % is expensive, but we have to do this since
  960. * size of some SRNG rings is not power of 2 (due to descriptor
  961. * sizes). Need to create separate API for rings used
  962. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  963. * SW2RXDMA and CE rings)
  964. */
  965. srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size);
  966. if (srng->u.dst_ring.tp == srng->ring_size)
  967. srng->u.dst_ring.tp = 0;
  968. desc_next = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  969. qdf_prefetch(desc_next);
  970. return (void *)desc;
  971. }
  972. /**
  973. * hal_srng_dst_get_next_hp - Get next entry from a destination ring and move
  974. * cached head pointer
  975. *
  976. * @hal_soc: Opaque HAL SOC handle
  977. * @hal_ring_hdl: Destination ring pointer
  978. *
  979. * Return: Opaque pointer for next ring entry; NULL on failire
  980. */
  981. static inline void *
  982. hal_srng_dst_get_next_hp(hal_soc_handle_t hal_soc_hdl,
  983. hal_ring_handle_t hal_ring_hdl)
  984. {
  985. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  986. uint32_t *desc;
  987. /* TODO: Using % is expensive, but we have to do this since
  988. * size of some SRNG rings is not power of 2 (due to descriptor
  989. * sizes). Need to create separate API for rings used
  990. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  991. * SW2RXDMA and CE rings)
  992. */
  993. uint32_t next_hp = (srng->u.dst_ring.cached_hp + srng->entry_size) %
  994. srng->ring_size;
  995. if (next_hp != srng->u.dst_ring.tp) {
  996. desc = &(srng->ring_base_vaddr[srng->u.dst_ring.cached_hp]);
  997. srng->u.dst_ring.cached_hp = next_hp;
  998. return (void *)desc;
  999. }
  1000. return NULL;
  1001. }
  1002. /**
  1003. * hal_srng_dst_peek_sync - Check if there are any entries in the ring (peek)
  1004. * @hal_soc: Opaque HAL SOC handle
  1005. * @hal_ring_hdl: Destination ring pointer
  1006. *
  1007. * Sync cached head pointer with HW.
  1008. * Caller takes responsibility for any locking needs.
  1009. *
  1010. * Return: Opaque pointer for next ring entry; NULL on failire
  1011. */
  1012. static inline
  1013. void *hal_srng_dst_peek_sync(hal_soc_handle_t hal_soc_hdl,
  1014. hal_ring_handle_t hal_ring_hdl)
  1015. {
  1016. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1017. srng->u.dst_ring.cached_hp =
  1018. *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1019. if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp)
  1020. return (void *)(&(srng->ring_base_vaddr[srng->u.dst_ring.tp]));
  1021. return NULL;
  1022. }
  1023. /**
  1024. * hal_srng_dst_peek_sync_locked - Peek for any entries in the ring
  1025. * @hal_soc: Opaque HAL SOC handle
  1026. * @hal_ring_hdl: Destination ring pointer
  1027. *
  1028. * Sync cached head pointer with HW.
  1029. * This function takes up SRNG_LOCK. Should not be called with SRNG lock held.
  1030. *
  1031. * Return: Opaque pointer for next ring entry; NULL on failire
  1032. */
  1033. static inline
  1034. void *hal_srng_dst_peek_sync_locked(hal_soc_handle_t hal_soc_hdl,
  1035. hal_ring_handle_t hal_ring_hdl)
  1036. {
  1037. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1038. void *ring_desc_ptr = NULL;
  1039. if (qdf_unlikely(!hal_ring_hdl)) {
  1040. qdf_print("Error: Invalid hal_ring\n");
  1041. return NULL;
  1042. }
  1043. SRNG_LOCK(&srng->lock);
  1044. ring_desc_ptr = hal_srng_dst_peek_sync(hal_soc_hdl, hal_ring_hdl);
  1045. SRNG_UNLOCK(&srng->lock);
  1046. return ring_desc_ptr;
  1047. }
  1048. /**
  1049. * hal_srng_dst_num_valid - Returns number of valid entries (to be processed
  1050. * by SW) in destination ring
  1051. *
  1052. * @hal_soc: Opaque HAL SOC handle
  1053. * @hal_ring_hdl: Destination ring pointer
  1054. * @sync_hw_ptr: Sync cached head pointer with HW
  1055. *
  1056. */
  1057. static inline
  1058. uint32_t hal_srng_dst_num_valid(void *hal_soc,
  1059. hal_ring_handle_t hal_ring_hdl,
  1060. int sync_hw_ptr)
  1061. {
  1062. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1063. uint32_t hp;
  1064. uint32_t tp = srng->u.dst_ring.tp;
  1065. if (sync_hw_ptr) {
  1066. hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1067. srng->u.dst_ring.cached_hp = hp;
  1068. } else {
  1069. hp = srng->u.dst_ring.cached_hp;
  1070. }
  1071. if (hp >= tp)
  1072. return (hp - tp) / srng->entry_size;
  1073. return (srng->ring_size - tp + hp) / srng->entry_size;
  1074. }
  1075. /**
  1076. * hal_srng_dst_inv_cached_descs - API to invalidate descriptors in batch mode
  1077. * @hal_soc: Opaque HAL SOC handle
  1078. * @hal_ring_hdl: Destination ring pointer
  1079. * @entry_count: Number of descriptors to be invalidated
  1080. *
  1081. * Invalidates a set of cached descriptors starting from tail to
  1082. * provided count worth
  1083. *
  1084. * Return - None
  1085. */
  1086. static inline void hal_srng_dst_inv_cached_descs(void *hal_soc,
  1087. hal_ring_handle_t hal_ring_hdl,
  1088. uint32_t entry_count)
  1089. {
  1090. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1091. uint32_t hp = srng->u.dst_ring.cached_hp;
  1092. uint32_t tp = srng->u.dst_ring.tp;
  1093. uint32_t sync_p = 0;
  1094. /*
  1095. * If SRNG does not have cached descriptors this
  1096. * API call should be a no op
  1097. */
  1098. if (!(srng->flags & HAL_SRNG_CACHED_DESC))
  1099. return;
  1100. if (qdf_unlikely(entry_count == 0))
  1101. return;
  1102. sync_p = (entry_count - 1) * srng->entry_size;
  1103. if (hp > tp) {
  1104. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[tp],
  1105. &srng->ring_base_vaddr[tp + sync_p]
  1106. + (srng->entry_size * sizeof(uint32_t)));
  1107. } else {
  1108. /*
  1109. * We have wrapped around
  1110. */
  1111. uint32_t wrap_cnt = ((srng->ring_size - tp) / srng->entry_size);
  1112. if (entry_count <= wrap_cnt) {
  1113. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[tp],
  1114. &srng->ring_base_vaddr[tp + sync_p] +
  1115. (srng->entry_size * sizeof(uint32_t)));
  1116. return;
  1117. }
  1118. entry_count -= wrap_cnt;
  1119. sync_p = (entry_count - 1) * srng->entry_size;
  1120. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[tp],
  1121. &srng->ring_base_vaddr[srng->ring_size - srng->entry_size] +
  1122. (srng->entry_size * sizeof(uint32_t)));
  1123. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[0],
  1124. &srng->ring_base_vaddr[sync_p]
  1125. + (srng->entry_size * sizeof(uint32_t)));
  1126. }
  1127. }
  1128. /**
  1129. * hal_srng_dst_num_valid_locked - Returns num valid entries to be processed
  1130. *
  1131. * @hal_soc: Opaque HAL SOC handle
  1132. * @hal_ring_hdl: Destination ring pointer
  1133. * @sync_hw_ptr: Sync cached head pointer with HW
  1134. *
  1135. * Returns number of valid entries to be processed by the host driver. The
  1136. * function takes up SRNG lock.
  1137. *
  1138. * Return: Number of valid destination entries
  1139. */
  1140. static inline uint32_t
  1141. hal_srng_dst_num_valid_locked(hal_soc_handle_t hal_soc,
  1142. hal_ring_handle_t hal_ring_hdl,
  1143. int sync_hw_ptr)
  1144. {
  1145. uint32_t num_valid;
  1146. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1147. SRNG_LOCK(&srng->lock);
  1148. num_valid = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, sync_hw_ptr);
  1149. SRNG_UNLOCK(&srng->lock);
  1150. return num_valid;
  1151. }
  1152. /**
  1153. * hal_srng_sync_cachedhp - sync cachehp pointer from hw hp
  1154. *
  1155. * @hal_soc: Opaque HAL SOC handle
  1156. * @hal_ring_hdl: Destination ring pointer
  1157. *
  1158. */
  1159. static inline
  1160. void hal_srng_sync_cachedhp(void *hal_soc,
  1161. hal_ring_handle_t hal_ring_hdl)
  1162. {
  1163. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1164. uint32_t hp;
  1165. hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1166. srng->u.dst_ring.cached_hp = hp;
  1167. }
  1168. /**
  1169. * hal_srng_src_reap_next - Reap next entry from a source ring and move reap
  1170. * pointer. This can be used to release any buffers associated with completed
  1171. * ring entries. Note that this should not be used for posting new descriptor
  1172. * entries. Posting of new entries should be done only using
  1173. * hal_srng_src_get_next_reaped when this function is used for reaping.
  1174. *
  1175. * @hal_soc: Opaque HAL SOC handle
  1176. * @hal_ring_hdl: Source ring pointer
  1177. *
  1178. * Return: Opaque pointer for next ring entry; NULL on failire
  1179. */
  1180. static inline void *
  1181. hal_srng_src_reap_next(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1182. {
  1183. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1184. uint32_t *desc;
  1185. /* TODO: Using % is expensive, but we have to do this since
  1186. * size of some SRNG rings is not power of 2 (due to descriptor
  1187. * sizes). Need to create separate API for rings used
  1188. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1189. * SW2RXDMA and CE rings)
  1190. */
  1191. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1192. srng->ring_size;
  1193. if (next_reap_hp != srng->u.src_ring.cached_tp) {
  1194. desc = &(srng->ring_base_vaddr[next_reap_hp]);
  1195. srng->u.src_ring.reap_hp = next_reap_hp;
  1196. return (void *)desc;
  1197. }
  1198. return NULL;
  1199. }
  1200. /**
  1201. * hal_srng_src_get_next_reaped - Get next entry from a source ring that is
  1202. * already reaped using hal_srng_src_reap_next, for posting new entries to
  1203. * the ring
  1204. *
  1205. * @hal_soc: Opaque HAL SOC handle
  1206. * @hal_ring_hdl: Source ring pointer
  1207. *
  1208. * Return: Opaque pointer for next (reaped) source ring entry; NULL on failire
  1209. */
  1210. static inline void *
  1211. hal_srng_src_get_next_reaped(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1212. {
  1213. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1214. uint32_t *desc;
  1215. if (srng->u.src_ring.hp != srng->u.src_ring.reap_hp) {
  1216. desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]);
  1217. srng->u.src_ring.hp = (srng->u.src_ring.hp + srng->entry_size) %
  1218. srng->ring_size;
  1219. return (void *)desc;
  1220. }
  1221. return NULL;
  1222. }
  1223. /**
  1224. * hal_srng_src_pending_reap_next - Reap next entry from a source ring and
  1225. * move reap pointer. This API is used in detach path to release any buffers
  1226. * associated with ring entries which are pending reap.
  1227. *
  1228. * @hal_soc: Opaque HAL SOC handle
  1229. * @hal_ring_hdl: Source ring pointer
  1230. *
  1231. * Return: Opaque pointer for next ring entry; NULL on failire
  1232. */
  1233. static inline void *
  1234. hal_srng_src_pending_reap_next(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1235. {
  1236. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1237. uint32_t *desc;
  1238. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1239. srng->ring_size;
  1240. if (next_reap_hp != srng->u.src_ring.hp) {
  1241. desc = &(srng->ring_base_vaddr[next_reap_hp]);
  1242. srng->u.src_ring.reap_hp = next_reap_hp;
  1243. return (void *)desc;
  1244. }
  1245. return NULL;
  1246. }
  1247. /**
  1248. * hal_srng_src_done_val -
  1249. *
  1250. * @hal_soc: Opaque HAL SOC handle
  1251. * @hal_ring_hdl: Source ring pointer
  1252. *
  1253. * Return: Opaque pointer for next ring entry; NULL on failire
  1254. */
  1255. static inline uint32_t
  1256. hal_srng_src_done_val(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1257. {
  1258. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1259. /* TODO: Using % is expensive, but we have to do this since
  1260. * size of some SRNG rings is not power of 2 (due to descriptor
  1261. * sizes). Need to create separate API for rings used
  1262. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1263. * SW2RXDMA and CE rings)
  1264. */
  1265. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1266. srng->ring_size;
  1267. if (next_reap_hp == srng->u.src_ring.cached_tp)
  1268. return 0;
  1269. if (srng->u.src_ring.cached_tp > next_reap_hp)
  1270. return (srng->u.src_ring.cached_tp - next_reap_hp) /
  1271. srng->entry_size;
  1272. else
  1273. return ((srng->ring_size - next_reap_hp) +
  1274. srng->u.src_ring.cached_tp) / srng->entry_size;
  1275. }
  1276. /**
  1277. * hal_get_entrysize_from_srng() - Retrieve ring entry size
  1278. * @hal_ring_hdl: Source ring pointer
  1279. *
  1280. * Return: uint8_t
  1281. */
  1282. static inline
  1283. uint8_t hal_get_entrysize_from_srng(hal_ring_handle_t hal_ring_hdl)
  1284. {
  1285. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1286. return srng->entry_size;
  1287. }
  1288. /**
  1289. * hal_get_sw_hptp - Get SW head and tail pointer location for any ring
  1290. * @hal_soc: Opaque HAL SOC handle
  1291. * @hal_ring_hdl: Source ring pointer
  1292. * @tailp: Tail Pointer
  1293. * @headp: Head Pointer
  1294. *
  1295. * Return: Update tail pointer and head pointer in arguments.
  1296. */
  1297. static inline
  1298. void hal_get_sw_hptp(void *hal_soc, hal_ring_handle_t hal_ring_hdl,
  1299. uint32_t *tailp, uint32_t *headp)
  1300. {
  1301. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1302. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1303. *headp = srng->u.src_ring.hp;
  1304. *tailp = *srng->u.src_ring.tp_addr;
  1305. } else {
  1306. *tailp = srng->u.dst_ring.tp;
  1307. *headp = *srng->u.dst_ring.hp_addr;
  1308. }
  1309. }
  1310. /**
  1311. * hal_srng_src_get_next - Get next entry from a source ring and move cached tail pointer
  1312. *
  1313. * @hal_soc: Opaque HAL SOC handle
  1314. * @hal_ring_hdl: Source ring pointer
  1315. *
  1316. * Return: Opaque pointer for next ring entry; NULL on failire
  1317. */
  1318. static inline
  1319. void *hal_srng_src_get_next(void *hal_soc,
  1320. hal_ring_handle_t hal_ring_hdl)
  1321. {
  1322. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1323. uint32_t *desc;
  1324. /* TODO: Using % is expensive, but we have to do this since
  1325. * size of some SRNG rings is not power of 2 (due to descriptor
  1326. * sizes). Need to create separate API for rings used
  1327. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1328. * SW2RXDMA and CE rings)
  1329. */
  1330. uint32_t next_hp = (srng->u.src_ring.hp + srng->entry_size) %
  1331. srng->ring_size;
  1332. if (next_hp != srng->u.src_ring.cached_tp) {
  1333. desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]);
  1334. srng->u.src_ring.hp = next_hp;
  1335. /* TODO: Since reap function is not used by all rings, we can
  1336. * remove the following update of reap_hp in this function
  1337. * if we can ensure that only hal_srng_src_get_next_reaped
  1338. * is used for the rings requiring reap functionality
  1339. */
  1340. srng->u.src_ring.reap_hp = next_hp;
  1341. return (void *)desc;
  1342. }
  1343. return NULL;
  1344. }
  1345. /**
  1346. * hal_srng_src_peek_n_get_next - Get next entry from a ring without
  1347. * moving head pointer.
  1348. * hal_srng_src_get_next should be called subsequently to move the head pointer
  1349. *
  1350. * @hal_soc: Opaque HAL SOC handle
  1351. * @hal_ring_hdl: Source ring pointer
  1352. *
  1353. * Return: Opaque pointer for next ring entry; NULL on failire
  1354. */
  1355. static inline
  1356. void *hal_srng_src_peek_n_get_next(hal_soc_handle_t hal_soc_hdl,
  1357. hal_ring_handle_t hal_ring_hdl)
  1358. {
  1359. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1360. uint32_t *desc;
  1361. /* TODO: Using % is expensive, but we have to do this since
  1362. * size of some SRNG rings is not power of 2 (due to descriptor
  1363. * sizes). Need to create separate API for rings used
  1364. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1365. * SW2RXDMA and CE rings)
  1366. */
  1367. if (((srng->u.src_ring.hp + srng->entry_size) %
  1368. srng->ring_size) != srng->u.src_ring.cached_tp) {
  1369. desc = &(srng->ring_base_vaddr[(srng->u.src_ring.hp +
  1370. srng->entry_size) %
  1371. srng->ring_size]);
  1372. return (void *)desc;
  1373. }
  1374. return NULL;
  1375. }
  1376. /**
  1377. * hal_srng_src_get_cur_hp_n_move_next () - API returns current hp
  1378. * and move hp to next in src ring
  1379. *
  1380. * Usage: This API should only be used at init time replenish.
  1381. *
  1382. * @hal_soc_hdl: HAL soc handle
  1383. * @hal_ring_hdl: Source ring pointer
  1384. *
  1385. */
  1386. static inline void *
  1387. hal_srng_src_get_cur_hp_n_move_next(hal_soc_handle_t hal_soc_hdl,
  1388. hal_ring_handle_t hal_ring_hdl)
  1389. {
  1390. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1391. uint32_t *cur_desc = NULL;
  1392. uint32_t next_hp;
  1393. cur_desc = &srng->ring_base_vaddr[(srng->u.src_ring.hp)];
  1394. next_hp = (srng->u.src_ring.hp + srng->entry_size) %
  1395. srng->ring_size;
  1396. if (next_hp != srng->u.src_ring.cached_tp)
  1397. srng->u.src_ring.hp = next_hp;
  1398. return (void *)cur_desc;
  1399. }
  1400. /**
  1401. * hal_srng_src_num_avail - Returns number of available entries in src ring
  1402. *
  1403. * @hal_soc: Opaque HAL SOC handle
  1404. * @hal_ring_hdl: Source ring pointer
  1405. * @sync_hw_ptr: Sync cached tail pointer with HW
  1406. *
  1407. */
  1408. static inline uint32_t
  1409. hal_srng_src_num_avail(void *hal_soc,
  1410. hal_ring_handle_t hal_ring_hdl, int sync_hw_ptr)
  1411. {
  1412. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1413. uint32_t tp;
  1414. uint32_t hp = srng->u.src_ring.hp;
  1415. if (sync_hw_ptr) {
  1416. tp = *(srng->u.src_ring.tp_addr);
  1417. srng->u.src_ring.cached_tp = tp;
  1418. } else {
  1419. tp = srng->u.src_ring.cached_tp;
  1420. }
  1421. if (tp > hp)
  1422. return ((tp - hp) / srng->entry_size) - 1;
  1423. else
  1424. return ((srng->ring_size - hp + tp) / srng->entry_size) - 1;
  1425. }
  1426. /**
  1427. * hal_srng_access_end_unlocked - End ring access (unlocked) - update cached
  1428. * ring head/tail pointers to HW.
  1429. * This should be used only if hal_srng_access_start_unlocked to start ring
  1430. * access
  1431. *
  1432. * @hal_soc: Opaque HAL SOC handle
  1433. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1434. *
  1435. * Return: 0 on success; error on failire
  1436. */
  1437. static inline void
  1438. hal_srng_access_end_unlocked(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1439. {
  1440. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1441. /* TODO: See if we need a write memory barrier here */
  1442. if (srng->flags & HAL_SRNG_LMAC_RING) {
  1443. /* For LMAC rings, ring pointer updates are done through FW and
  1444. * hence written to a shared memory location that is read by FW
  1445. */
  1446. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1447. *(srng->u.src_ring.hp_addr) = srng->u.src_ring.hp;
  1448. } else {
  1449. *(srng->u.dst_ring.tp_addr) = srng->u.dst_ring.tp;
  1450. }
  1451. } else {
  1452. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1453. hal_srng_write_address_32_mb(hal_soc,
  1454. srng,
  1455. srng->u.src_ring.hp_addr,
  1456. srng->u.src_ring.hp);
  1457. else
  1458. hal_srng_write_address_32_mb(hal_soc,
  1459. srng,
  1460. srng->u.dst_ring.tp_addr,
  1461. srng->u.dst_ring.tp);
  1462. }
  1463. }
  1464. /**
  1465. * hal_srng_access_end - Unlock ring access and update cached ring head/tail
  1466. * pointers to HW
  1467. * This should be used only if hal_srng_access_start to start ring access
  1468. *
  1469. * @hal_soc: Opaque HAL SOC handle
  1470. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1471. *
  1472. * Return: 0 on success; error on failire
  1473. */
  1474. static inline void
  1475. hal_srng_access_end(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1476. {
  1477. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1478. if (qdf_unlikely(!hal_ring_hdl)) {
  1479. qdf_print("Error: Invalid hal_ring\n");
  1480. return;
  1481. }
  1482. hal_srng_access_end_unlocked(hal_soc, hal_ring_hdl);
  1483. SRNG_UNLOCK(&(srng->lock));
  1484. }
  1485. /**
  1486. * hal_srng_access_end_reap - Unlock ring access
  1487. * This should be used only if hal_srng_access_start to start ring access
  1488. * and should be used only while reaping SRC ring completions
  1489. *
  1490. * @hal_soc: Opaque HAL SOC handle
  1491. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1492. *
  1493. * Return: 0 on success; error on failire
  1494. */
  1495. static inline void
  1496. hal_srng_access_end_reap(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1497. {
  1498. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1499. SRNG_UNLOCK(&(srng->lock));
  1500. }
  1501. /* TODO: Check if the following definitions is available in HW headers */
  1502. #define WBM_IDLE_SCATTER_BUF_SIZE 32704
  1503. #define NUM_MPDUS_PER_LINK_DESC 6
  1504. #define NUM_MSDUS_PER_LINK_DESC 7
  1505. #define REO_QUEUE_DESC_ALIGN 128
  1506. #define LINK_DESC_ALIGN 128
  1507. #define ADDRESS_MATCH_TAG_VAL 0x5
  1508. /* Number of mpdu link pointers is 9 in case of TX_MPDU_QUEUE_HEAD and 14 in
  1509. * of TX_MPDU_QUEUE_EXT. We are defining a common average count here
  1510. */
  1511. #define NUM_MPDU_LINKS_PER_QUEUE_DESC 12
  1512. /* TODO: Check with HW team on the scatter buffer size supported. As per WBM
  1513. * MLD, scatter_buffer_size in IDLE_LIST_CONTROL register is 9 bits and size
  1514. * should be specified in 16 word units. But the number of bits defined for
  1515. * this field in HW header files is 5.
  1516. */
  1517. #define WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE 8
  1518. /**
  1519. * hal_idle_list_scatter_buf_size - Get the size of each scatter buffer
  1520. * in an idle list
  1521. *
  1522. * @hal_soc: Opaque HAL SOC handle
  1523. *
  1524. */
  1525. static inline
  1526. uint32_t hal_idle_list_scatter_buf_size(hal_soc_handle_t hal_soc_hdl)
  1527. {
  1528. return WBM_IDLE_SCATTER_BUF_SIZE;
  1529. }
  1530. /**
  1531. * hal_get_link_desc_size - Get the size of each link descriptor
  1532. *
  1533. * @hal_soc: Opaque HAL SOC handle
  1534. *
  1535. */
  1536. static inline uint32_t hal_get_link_desc_size(hal_soc_handle_t hal_soc_hdl)
  1537. {
  1538. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1539. if (!hal_soc || !hal_soc->ops) {
  1540. qdf_print("Error: Invalid ops\n");
  1541. QDF_BUG(0);
  1542. return -EINVAL;
  1543. }
  1544. if (!hal_soc->ops->hal_get_link_desc_size) {
  1545. qdf_print("Error: Invalid function pointer\n");
  1546. QDF_BUG(0);
  1547. return -EINVAL;
  1548. }
  1549. return hal_soc->ops->hal_get_link_desc_size();
  1550. }
  1551. /**
  1552. * hal_get_link_desc_align - Get the required start address alignment for
  1553. * link descriptors
  1554. *
  1555. * @hal_soc: Opaque HAL SOC handle
  1556. *
  1557. */
  1558. static inline
  1559. uint32_t hal_get_link_desc_align(hal_soc_handle_t hal_soc_hdl)
  1560. {
  1561. return LINK_DESC_ALIGN;
  1562. }
  1563. /**
  1564. * hal_num_mpdus_per_link_desc - Get number of mpdus each link desc can hold
  1565. *
  1566. * @hal_soc: Opaque HAL SOC handle
  1567. *
  1568. */
  1569. static inline
  1570. uint32_t hal_num_mpdus_per_link_desc(hal_soc_handle_t hal_soc_hdl)
  1571. {
  1572. return NUM_MPDUS_PER_LINK_DESC;
  1573. }
  1574. /**
  1575. * hal_num_msdus_per_link_desc - Get number of msdus each link desc can hold
  1576. *
  1577. * @hal_soc: Opaque HAL SOC handle
  1578. *
  1579. */
  1580. static inline
  1581. uint32_t hal_num_msdus_per_link_desc(hal_soc_handle_t hal_soc_hdl)
  1582. {
  1583. return NUM_MSDUS_PER_LINK_DESC;
  1584. }
  1585. /**
  1586. * hal_num_mpdu_links_per_queue_desc - Get number of mpdu links each queue
  1587. * descriptor can hold
  1588. *
  1589. * @hal_soc: Opaque HAL SOC handle
  1590. *
  1591. */
  1592. static inline
  1593. uint32_t hal_num_mpdu_links_per_queue_desc(hal_soc_handle_t hal_soc_hdl)
  1594. {
  1595. return NUM_MPDU_LINKS_PER_QUEUE_DESC;
  1596. }
  1597. /**
  1598. * hal_idle_list_scatter_buf_num_entries - Get the number of link desc entries
  1599. * that the given buffer size
  1600. *
  1601. * @hal_soc: Opaque HAL SOC handle
  1602. * @scatter_buf_size: Size of scatter buffer
  1603. *
  1604. */
  1605. static inline
  1606. uint32_t hal_idle_scatter_buf_num_entries(hal_soc_handle_t hal_soc_hdl,
  1607. uint32_t scatter_buf_size)
  1608. {
  1609. return (scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) /
  1610. hal_srng_get_entrysize(hal_soc_hdl, WBM_IDLE_LINK);
  1611. }
  1612. /**
  1613. * hal_idle_list_num_scatter_bufs - Get the number of sctater buffer
  1614. * each given buffer size
  1615. *
  1616. * @hal_soc: Opaque HAL SOC handle
  1617. * @total_mem: size of memory to be scattered
  1618. * @scatter_buf_size: Size of scatter buffer
  1619. *
  1620. */
  1621. static inline
  1622. uint32_t hal_idle_list_num_scatter_bufs(hal_soc_handle_t hal_soc_hdl,
  1623. uint32_t total_mem,
  1624. uint32_t scatter_buf_size)
  1625. {
  1626. uint8_t rem = (total_mem % (scatter_buf_size -
  1627. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) ? 1 : 0;
  1628. uint32_t num_scatter_bufs = (total_mem / (scatter_buf_size -
  1629. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) + rem;
  1630. return num_scatter_bufs;
  1631. }
  1632. enum hal_pn_type {
  1633. HAL_PN_NONE,
  1634. HAL_PN_WPA,
  1635. HAL_PN_WAPI_EVEN,
  1636. HAL_PN_WAPI_UNEVEN,
  1637. };
  1638. #define HAL_RX_MAX_BA_WINDOW 256
  1639. /**
  1640. * hal_get_reo_qdesc_align - Get start address alignment for reo
  1641. * queue descriptors
  1642. *
  1643. * @hal_soc: Opaque HAL SOC handle
  1644. *
  1645. */
  1646. static inline
  1647. uint32_t hal_get_reo_qdesc_align(hal_soc_handle_t hal_soc_hdl)
  1648. {
  1649. return REO_QUEUE_DESC_ALIGN;
  1650. }
  1651. /**
  1652. * hal_reo_qdesc_setup - Setup HW REO queue descriptor
  1653. *
  1654. * @hal_soc: Opaque HAL SOC handle
  1655. * @ba_window_size: BlockAck window size
  1656. * @start_seq: Starting sequence number
  1657. * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
  1658. * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
  1659. * @pn_type: PN type (one of the types defined in 'enum hal_pn_type')
  1660. *
  1661. */
  1662. void hal_reo_qdesc_setup(hal_soc_handle_t hal_soc_hdl,
  1663. int tid, uint32_t ba_window_size,
  1664. uint32_t start_seq, void *hw_qdesc_vaddr,
  1665. qdf_dma_addr_t hw_qdesc_paddr,
  1666. int pn_type);
  1667. /**
  1668. * hal_srng_get_hp_addr - Get head pointer physical address
  1669. *
  1670. * @hal_soc: Opaque HAL SOC handle
  1671. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1672. *
  1673. */
  1674. static inline qdf_dma_addr_t
  1675. hal_srng_get_hp_addr(void *hal_soc,
  1676. hal_ring_handle_t hal_ring_hdl)
  1677. {
  1678. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1679. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1680. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1681. return hal->shadow_wrptr_mem_paddr +
  1682. ((unsigned long)(srng->u.src_ring.hp_addr) -
  1683. (unsigned long)(hal->shadow_wrptr_mem_vaddr));
  1684. } else {
  1685. return hal->shadow_rdptr_mem_paddr +
  1686. ((unsigned long)(srng->u.dst_ring.hp_addr) -
  1687. (unsigned long)(hal->shadow_rdptr_mem_vaddr));
  1688. }
  1689. }
  1690. /**
  1691. * hal_srng_get_tp_addr - Get tail pointer physical address
  1692. *
  1693. * @hal_soc: Opaque HAL SOC handle
  1694. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1695. *
  1696. */
  1697. static inline qdf_dma_addr_t
  1698. hal_srng_get_tp_addr(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1699. {
  1700. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1701. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1702. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1703. return hal->shadow_rdptr_mem_paddr +
  1704. ((unsigned long)(srng->u.src_ring.tp_addr) -
  1705. (unsigned long)(hal->shadow_rdptr_mem_vaddr));
  1706. } else {
  1707. return hal->shadow_wrptr_mem_paddr +
  1708. ((unsigned long)(srng->u.dst_ring.tp_addr) -
  1709. (unsigned long)(hal->shadow_wrptr_mem_vaddr));
  1710. }
  1711. }
  1712. /**
  1713. * hal_srng_get_num_entries - Get total entries in the HAL Srng
  1714. *
  1715. * @hal_soc: Opaque HAL SOC handle
  1716. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1717. *
  1718. * Return: total number of entries in hal ring
  1719. */
  1720. static inline
  1721. uint32_t hal_srng_get_num_entries(hal_soc_handle_t hal_soc_hdl,
  1722. hal_ring_handle_t hal_ring_hdl)
  1723. {
  1724. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1725. return srng->num_entries;
  1726. }
  1727. /**
  1728. * hal_get_srng_params - Retrieve SRNG parameters for a given ring from HAL
  1729. *
  1730. * @hal_soc: Opaque HAL SOC handle
  1731. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1732. * @ring_params: SRNG parameters will be returned through this structure
  1733. */
  1734. void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl,
  1735. hal_ring_handle_t hal_ring_hdl,
  1736. struct hal_srng_params *ring_params);
  1737. /**
  1738. * hal_mem_info - Retrieve hal memory base address
  1739. *
  1740. * @hal_soc: Opaque HAL SOC handle
  1741. * @mem: pointer to structure to be updated with hal mem info
  1742. */
  1743. void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem);
  1744. /**
  1745. * hal_get_target_type - Return target type
  1746. *
  1747. * @hal_soc: Opaque HAL SOC handle
  1748. */
  1749. uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl);
  1750. /**
  1751. * hal_get_ba_aging_timeout - Retrieve BA aging timeout
  1752. *
  1753. * @hal_soc: Opaque HAL SOC handle
  1754. * @ac: Access category
  1755. * @value: timeout duration in millisec
  1756. */
  1757. void hal_get_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
  1758. uint32_t *value);
  1759. /**
  1760. * hal_set_aging_timeout - Set BA aging timeout
  1761. *
  1762. * @hal_soc: Opaque HAL SOC handle
  1763. * @ac: Access category in millisec
  1764. * @value: timeout duration value
  1765. */
  1766. void hal_set_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
  1767. uint32_t value);
  1768. /**
  1769. * hal_srng_dst_hw_init - Private function to initialize SRNG
  1770. * destination ring HW
  1771. * @hal_soc: HAL SOC handle
  1772. * @srng: SRNG ring pointer
  1773. */
  1774. static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
  1775. struct hal_srng *srng)
  1776. {
  1777. hal->ops->hal_srng_dst_hw_init(hal, srng);
  1778. }
  1779. /**
  1780. * hal_srng_src_hw_init - Private function to initialize SRNG
  1781. * source ring HW
  1782. * @hal_soc: HAL SOC handle
  1783. * @srng: SRNG ring pointer
  1784. */
  1785. static inline void hal_srng_src_hw_init(struct hal_soc *hal,
  1786. struct hal_srng *srng)
  1787. {
  1788. hal->ops->hal_srng_src_hw_init(hal, srng);
  1789. }
  1790. /**
  1791. * hal_get_hw_hptp() - Get HW head and tail pointer value for any ring
  1792. * @hal_soc: Opaque HAL SOC handle
  1793. * @hal_ring_hdl: Source ring pointer
  1794. * @headp: Head Pointer
  1795. * @tailp: Tail Pointer
  1796. * @ring_type: Ring
  1797. *
  1798. * Return: Update tail pointer and head pointer in arguments.
  1799. */
  1800. static inline
  1801. void hal_get_hw_hptp(hal_soc_handle_t hal_soc_hdl,
  1802. hal_ring_handle_t hal_ring_hdl,
  1803. uint32_t *headp, uint32_t *tailp,
  1804. uint8_t ring_type)
  1805. {
  1806. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1807. hal_soc->ops->hal_get_hw_hptp(hal_soc, hal_ring_hdl,
  1808. headp, tailp, ring_type);
  1809. }
  1810. /**
  1811. * hal_reo_setup - Initialize HW REO block
  1812. *
  1813. * @hal_soc: Opaque HAL SOC handle
  1814. * @reo_params: parameters needed by HAL for REO config
  1815. */
  1816. static inline void hal_reo_setup(hal_soc_handle_t hal_soc_hdl,
  1817. void *reoparams)
  1818. {
  1819. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1820. hal_soc->ops->hal_reo_setup(hal_soc, reoparams);
  1821. }
  1822. /**
  1823. * hal_setup_link_idle_list - Setup scattered idle list using the
  1824. * buffer list provided
  1825. *
  1826. * @hal_soc: Opaque HAL SOC handle
  1827. * @scatter_bufs_base_paddr: Array of physical base addresses
  1828. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  1829. * @num_scatter_bufs: Number of scatter buffers in the above lists
  1830. * @scatter_buf_size: Size of each scatter buffer
  1831. * @last_buf_end_offset: Offset to the last entry
  1832. * @num_entries: Total entries of all scatter bufs
  1833. *
  1834. */
  1835. static inline
  1836. void hal_setup_link_idle_list(hal_soc_handle_t hal_soc_hdl,
  1837. qdf_dma_addr_t scatter_bufs_base_paddr[],
  1838. void *scatter_bufs_base_vaddr[],
  1839. uint32_t num_scatter_bufs,
  1840. uint32_t scatter_buf_size,
  1841. uint32_t last_buf_end_offset,
  1842. uint32_t num_entries)
  1843. {
  1844. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1845. hal_soc->ops->hal_setup_link_idle_list(hal_soc, scatter_bufs_base_paddr,
  1846. scatter_bufs_base_vaddr, num_scatter_bufs,
  1847. scatter_buf_size, last_buf_end_offset,
  1848. num_entries);
  1849. }
  1850. /**
  1851. * hal_srng_dump_ring_desc() - Dump ring descriptor info
  1852. *
  1853. * @hal_soc: Opaque HAL SOC handle
  1854. * @hal_ring_hdl: Source ring pointer
  1855. * @ring_desc: Opaque ring descriptor handle
  1856. */
  1857. static inline void hal_srng_dump_ring_desc(hal_soc_handle_t hal_soc_hdl,
  1858. hal_ring_handle_t hal_ring_hdl,
  1859. hal_ring_desc_t ring_desc)
  1860. {
  1861. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1862. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1863. ring_desc, (srng->entry_size << 2));
  1864. }
  1865. /**
  1866. * hal_srng_dump_ring() - Dump last 128 descs of the ring
  1867. *
  1868. * @hal_soc: Opaque HAL SOC handle
  1869. * @hal_ring_hdl: Source ring pointer
  1870. */
  1871. static inline void hal_srng_dump_ring(hal_soc_handle_t hal_soc_hdl,
  1872. hal_ring_handle_t hal_ring_hdl)
  1873. {
  1874. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1875. uint32_t *desc;
  1876. uint32_t tp, i;
  1877. tp = srng->u.dst_ring.tp;
  1878. for (i = 0; i < 128; i++) {
  1879. if (!tp)
  1880. tp = srng->ring_size;
  1881. desc = &srng->ring_base_vaddr[tp - srng->entry_size];
  1882. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP,
  1883. QDF_TRACE_LEVEL_DEBUG,
  1884. desc, (srng->entry_size << 2));
  1885. tp -= srng->entry_size;
  1886. }
  1887. }
  1888. /*
  1889. * hal_rxdma_desc_to_hal_ring_desc - API to convert rxdma ring desc
  1890. * to opaque dp_ring desc type
  1891. * @ring_desc - rxdma ring desc
  1892. *
  1893. * Return: hal_rxdma_desc_t type
  1894. */
  1895. static inline
  1896. hal_ring_desc_t hal_rxdma_desc_to_hal_ring_desc(hal_rxdma_desc_t ring_desc)
  1897. {
  1898. return (hal_ring_desc_t)ring_desc;
  1899. }
  1900. /**
  1901. * hal_srng_set_event() - Set hal_srng event
  1902. * @hal_ring_hdl: Source ring pointer
  1903. * @event: SRNG ring event
  1904. *
  1905. * Return: None
  1906. */
  1907. static inline void hal_srng_set_event(hal_ring_handle_t hal_ring_hdl, int event)
  1908. {
  1909. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1910. qdf_atomic_set_bit(event, &srng->srng_event);
  1911. }
  1912. /**
  1913. * hal_srng_clear_event() - Clear hal_srng event
  1914. * @hal_ring_hdl: Source ring pointer
  1915. * @event: SRNG ring event
  1916. *
  1917. * Return: None
  1918. */
  1919. static inline
  1920. void hal_srng_clear_event(hal_ring_handle_t hal_ring_hdl, int event)
  1921. {
  1922. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1923. qdf_atomic_clear_bit(event, &srng->srng_event);
  1924. }
  1925. /**
  1926. * hal_srng_get_clear_event() - Clear srng event and return old value
  1927. * @hal_ring_hdl: Source ring pointer
  1928. * @event: SRNG ring event
  1929. *
  1930. * Return: Return old event value
  1931. */
  1932. static inline
  1933. int hal_srng_get_clear_event(hal_ring_handle_t hal_ring_hdl, int event)
  1934. {
  1935. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1936. return qdf_atomic_test_and_clear_bit(event, &srng->srng_event);
  1937. }
  1938. /**
  1939. * hal_srng_set_flush_last_ts() - Record last flush time stamp
  1940. * @hal_ring_hdl: Source ring pointer
  1941. *
  1942. * Return: None
  1943. */
  1944. static inline void hal_srng_set_flush_last_ts(hal_ring_handle_t hal_ring_hdl)
  1945. {
  1946. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1947. srng->last_flush_ts = qdf_get_log_timestamp();
  1948. }
  1949. /**
  1950. * hal_srng_inc_flush_cnt() - Increment flush counter
  1951. * @hal_ring_hdl: Source ring pointer
  1952. *
  1953. * Return: None
  1954. */
  1955. static inline void hal_srng_inc_flush_cnt(hal_ring_handle_t hal_ring_hdl)
  1956. {
  1957. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1958. srng->flush_count++;
  1959. }
  1960. /**
  1961. * hal_rx_sw_mon_desc_info_get () - Get SW monitor desc info
  1962. *
  1963. * @hal: Core HAL soc handle
  1964. * @ring_desc: Mon dest ring descriptor
  1965. * @desc_info: Desc info to be populated
  1966. *
  1967. * Return void
  1968. */
  1969. static inline void
  1970. hal_rx_sw_mon_desc_info_get(struct hal_soc *hal,
  1971. hal_ring_desc_t ring_desc,
  1972. hal_rx_mon_desc_info_t desc_info)
  1973. {
  1974. return hal->ops->hal_rx_sw_mon_desc_info_get(ring_desc, desc_info);
  1975. }
  1976. /**
  1977. * hal_reo_set_err_dst_remap() - Set REO error destination ring remap
  1978. * register value.
  1979. *
  1980. * @hal_soc_hdl: Opaque HAL soc handle
  1981. *
  1982. * Return: None
  1983. */
  1984. static inline void hal_reo_set_err_dst_remap(hal_soc_handle_t hal_soc_hdl)
  1985. {
  1986. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1987. if (hal_soc->ops->hal_reo_set_err_dst_remap)
  1988. hal_soc->ops->hal_reo_set_err_dst_remap(hal_soc);
  1989. }
  1990. #endif /* _HAL_APIH_ */