dp_tx.c 109 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "enet.h"
  34. #include "dp_internal.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. /* TODO Add support in TSO */
  42. #define DP_DESC_NUM_FRAG(x) 0
  43. /* disable TQM_BYPASS */
  44. #define TQM_BYPASS_WAR 0
  45. /* invalid peer id for reinject*/
  46. #define DP_INVALID_PEER 0XFFFE
  47. /*mapping between hal encrypt type and cdp_sec_type*/
  48. #define MAX_CDP_SEC_TYPE 12
  49. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  50. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  51. HAL_TX_ENCRYPT_TYPE_WEP_128,
  52. HAL_TX_ENCRYPT_TYPE_WEP_104,
  53. HAL_TX_ENCRYPT_TYPE_WEP_40,
  54. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  56. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  57. HAL_TX_ENCRYPT_TYPE_WAPI,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  59. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  62. #if defined(FEATURE_TSO)
  63. /**
  64. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  65. *
  66. * @soc - core txrx main context
  67. * @seg_desc - tso segment descriptor
  68. * @num_seg_desc - tso number segment descriptor
  69. */
  70. static void dp_tx_tso_unmap_segment(
  71. struct dp_soc *soc,
  72. struct qdf_tso_seg_elem_t *seg_desc,
  73. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  74. {
  75. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  76. if (qdf_unlikely(!seg_desc)) {
  77. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  78. __func__, __LINE__);
  79. qdf_assert(0);
  80. } else if (qdf_unlikely(!num_seg_desc)) {
  81. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  82. __func__, __LINE__);
  83. qdf_assert(0);
  84. } else {
  85. bool is_last_seg;
  86. /* no tso segment left to do dma unmap */
  87. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  88. return;
  89. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  90. true : false;
  91. qdf_nbuf_unmap_tso_segment(soc->osdev,
  92. seg_desc, is_last_seg);
  93. num_seg_desc->num_seg.tso_cmn_num_seg--;
  94. }
  95. }
  96. /**
  97. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  98. * back to the freelist
  99. *
  100. * @soc - soc device handle
  101. * @tx_desc - Tx software descriptor
  102. */
  103. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  104. struct dp_tx_desc_s *tx_desc)
  105. {
  106. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  107. if (qdf_unlikely(!tx_desc->tso_desc)) {
  108. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  109. "%s %d TSO desc is NULL!",
  110. __func__, __LINE__);
  111. qdf_assert(0);
  112. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  113. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  114. "%s %d TSO num desc is NULL!",
  115. __func__, __LINE__);
  116. qdf_assert(0);
  117. } else {
  118. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  119. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  120. /* Add the tso num segment into the free list */
  121. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  122. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  123. tx_desc->tso_num_desc);
  124. tx_desc->tso_num_desc = NULL;
  125. }
  126. /* Add the tso segment into the free list*/
  127. dp_tx_tso_desc_free(soc,
  128. tx_desc->pool_id, tx_desc->tso_desc);
  129. tx_desc->tso_desc = NULL;
  130. }
  131. }
  132. #else
  133. static void dp_tx_tso_unmap_segment(
  134. struct dp_soc *soc,
  135. struct qdf_tso_seg_elem_t *seg_desc,
  136. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  137. {
  138. }
  139. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  140. struct dp_tx_desc_s *tx_desc)
  141. {
  142. }
  143. #endif
  144. /**
  145. * dp_tx_desc_release() - Release Tx Descriptor
  146. * @tx_desc : Tx Descriptor
  147. * @desc_pool_id: Descriptor Pool ID
  148. *
  149. * Deallocate all resources attached to Tx descriptor and free the Tx
  150. * descriptor.
  151. *
  152. * Return:
  153. */
  154. static void
  155. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  156. {
  157. struct dp_pdev *pdev = tx_desc->pdev;
  158. struct dp_soc *soc;
  159. uint8_t comp_status = 0;
  160. qdf_assert(pdev);
  161. soc = pdev->soc;
  162. if (tx_desc->frm_type == dp_tx_frm_tso)
  163. dp_tx_tso_desc_release(soc, tx_desc);
  164. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  165. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  166. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  167. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  170. qdf_atomic_dec(&pdev->num_tx_exception);
  171. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  172. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  173. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  174. soc->hal_soc);
  175. else
  176. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  177. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  178. "Tx Completion Release desc %d status %d outstanding %d",
  179. tx_desc->id, comp_status,
  180. qdf_atomic_read(&pdev->num_tx_outstanding));
  181. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  182. return;
  183. }
  184. /**
  185. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  186. * @vdev: DP vdev Handle
  187. * @nbuf: skb
  188. * @msdu_info: msdu_info required to create HTT metadata
  189. *
  190. * Prepares and fills HTT metadata in the frame pre-header for special frames
  191. * that should be transmitted using varying transmit parameters.
  192. * There are 2 VDEV modes that currently needs this special metadata -
  193. * 1) Mesh Mode
  194. * 2) DSRC Mode
  195. *
  196. * Return: HTT metadata size
  197. *
  198. */
  199. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  200. struct dp_tx_msdu_info_s *msdu_info)
  201. {
  202. uint32_t *meta_data = msdu_info->meta_data;
  203. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  204. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  205. uint8_t htt_desc_size;
  206. /* Size rounded of multiple of 8 bytes */
  207. uint8_t htt_desc_size_aligned;
  208. uint8_t *hdr = NULL;
  209. /*
  210. * Metadata - HTT MSDU Extension header
  211. */
  212. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  213. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  214. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer) {
  215. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  216. htt_desc_size_aligned)) {
  217. DP_STATS_INC(vdev,
  218. tx_i.dropped.headroom_insufficient, 1);
  219. return 0;
  220. }
  221. /* Fill and add HTT metaheader */
  222. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  223. if (!hdr) {
  224. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  225. "Error in filling HTT metadata");
  226. return 0;
  227. }
  228. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  229. } else if (vdev->opmode == wlan_op_mode_ocb) {
  230. /* Todo - Add support for DSRC */
  231. }
  232. return htt_desc_size_aligned;
  233. }
  234. /**
  235. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  236. * @tso_seg: TSO segment to process
  237. * @ext_desc: Pointer to MSDU extension descriptor
  238. *
  239. * Return: void
  240. */
  241. #if defined(FEATURE_TSO)
  242. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  243. void *ext_desc)
  244. {
  245. uint8_t num_frag;
  246. uint32_t tso_flags;
  247. /*
  248. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  249. * tcp_flag_mask
  250. *
  251. * Checksum enable flags are set in TCL descriptor and not in Extension
  252. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  253. */
  254. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  255. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  256. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  257. tso_seg->tso_flags.ip_len);
  258. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  259. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  260. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  261. uint32_t lo = 0;
  262. uint32_t hi = 0;
  263. qdf_dmaaddr_to_32s(
  264. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  265. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  266. tso_seg->tso_frags[num_frag].length);
  267. }
  268. return;
  269. }
  270. #else
  271. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  272. void *ext_desc)
  273. {
  274. return;
  275. }
  276. #endif
  277. #if defined(FEATURE_TSO)
  278. /**
  279. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  280. * allocated and free them
  281. *
  282. * @soc: soc handle
  283. * @free_seg: list of tso segments
  284. * @msdu_info: msdu descriptor
  285. *
  286. * Return - void
  287. */
  288. static void dp_tx_free_tso_seg_list(
  289. struct dp_soc *soc,
  290. struct qdf_tso_seg_elem_t *free_seg,
  291. struct dp_tx_msdu_info_s *msdu_info)
  292. {
  293. struct qdf_tso_seg_elem_t *next_seg;
  294. while (free_seg) {
  295. next_seg = free_seg->next;
  296. dp_tx_tso_desc_free(soc,
  297. msdu_info->tx_queue.desc_pool_id,
  298. free_seg);
  299. free_seg = next_seg;
  300. }
  301. }
  302. /**
  303. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  304. * allocated and free them
  305. *
  306. * @soc: soc handle
  307. * @free_num_seg: list of tso number segments
  308. * @msdu_info: msdu descriptor
  309. * Return - void
  310. */
  311. static void dp_tx_free_tso_num_seg_list(
  312. struct dp_soc *soc,
  313. struct qdf_tso_num_seg_elem_t *free_num_seg,
  314. struct dp_tx_msdu_info_s *msdu_info)
  315. {
  316. struct qdf_tso_num_seg_elem_t *next_num_seg;
  317. while (free_num_seg) {
  318. next_num_seg = free_num_seg->next;
  319. dp_tso_num_seg_free(soc,
  320. msdu_info->tx_queue.desc_pool_id,
  321. free_num_seg);
  322. free_num_seg = next_num_seg;
  323. }
  324. }
  325. /**
  326. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  327. * do dma unmap for each segment
  328. *
  329. * @soc: soc handle
  330. * @free_seg: list of tso segments
  331. * @num_seg_desc: tso number segment descriptor
  332. *
  333. * Return - void
  334. */
  335. static void dp_tx_unmap_tso_seg_list(
  336. struct dp_soc *soc,
  337. struct qdf_tso_seg_elem_t *free_seg,
  338. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  339. {
  340. struct qdf_tso_seg_elem_t *next_seg;
  341. if (qdf_unlikely(!num_seg_desc)) {
  342. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  343. return;
  344. }
  345. while (free_seg) {
  346. next_seg = free_seg->next;
  347. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  348. free_seg = next_seg;
  349. }
  350. }
  351. /**
  352. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  353. * free the tso segments descriptor and
  354. * tso num segments descriptor
  355. *
  356. * @soc: soc handle
  357. * @msdu_info: msdu descriptor
  358. * @tso_seg_unmap: flag to show if dma unmap is necessary
  359. *
  360. * Return - void
  361. */
  362. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  363. struct dp_tx_msdu_info_s *msdu_info,
  364. bool tso_seg_unmap)
  365. {
  366. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  367. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  368. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  369. tso_info->tso_num_seg_list;
  370. /* do dma unmap for each segment */
  371. if (tso_seg_unmap)
  372. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  373. /* free all tso number segment descriptor though looks only have 1 */
  374. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  375. /* free all tso segment descriptor */
  376. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  377. }
  378. /**
  379. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  380. * @vdev: virtual device handle
  381. * @msdu: network buffer
  382. * @msdu_info: meta data associated with the msdu
  383. *
  384. * Return: QDF_STATUS_SUCCESS success
  385. */
  386. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  387. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  388. {
  389. struct qdf_tso_seg_elem_t *tso_seg;
  390. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  391. struct dp_soc *soc = vdev->pdev->soc;
  392. struct qdf_tso_info_t *tso_info;
  393. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  394. tso_info = &msdu_info->u.tso_info;
  395. tso_info->curr_seg = NULL;
  396. tso_info->tso_seg_list = NULL;
  397. tso_info->num_segs = num_seg;
  398. msdu_info->frm_type = dp_tx_frm_tso;
  399. tso_info->tso_num_seg_list = NULL;
  400. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  401. while (num_seg) {
  402. tso_seg = dp_tx_tso_desc_alloc(
  403. soc, msdu_info->tx_queue.desc_pool_id);
  404. if (tso_seg) {
  405. tso_seg->next = tso_info->tso_seg_list;
  406. tso_info->tso_seg_list = tso_seg;
  407. num_seg--;
  408. } else {
  409. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  410. __func__);
  411. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  412. return QDF_STATUS_E_NOMEM;
  413. }
  414. }
  415. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  416. tso_num_seg = dp_tso_num_seg_alloc(soc,
  417. msdu_info->tx_queue.desc_pool_id);
  418. if (tso_num_seg) {
  419. tso_num_seg->next = tso_info->tso_num_seg_list;
  420. tso_info->tso_num_seg_list = tso_num_seg;
  421. } else {
  422. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  423. __func__);
  424. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  425. return QDF_STATUS_E_NOMEM;
  426. }
  427. msdu_info->num_seg =
  428. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  429. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  430. msdu_info->num_seg);
  431. if (!(msdu_info->num_seg)) {
  432. /*
  433. * Free allocated TSO seg desc and number seg desc,
  434. * do unmap for segments if dma map has done.
  435. */
  436. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  437. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  438. return QDF_STATUS_E_INVAL;
  439. }
  440. tso_info->curr_seg = tso_info->tso_seg_list;
  441. return QDF_STATUS_SUCCESS;
  442. }
  443. #else
  444. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  445. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  446. {
  447. return QDF_STATUS_E_NOMEM;
  448. }
  449. #endif
  450. /**
  451. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  452. * @vdev: DP Vdev handle
  453. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  454. * @desc_pool_id: Descriptor Pool ID
  455. *
  456. * Return:
  457. */
  458. static
  459. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  460. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  461. {
  462. uint8_t i;
  463. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  464. struct dp_tx_seg_info_s *seg_info;
  465. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  466. struct dp_soc *soc = vdev->pdev->soc;
  467. /* Allocate an extension descriptor */
  468. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  469. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  470. if (!msdu_ext_desc) {
  471. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  472. return NULL;
  473. }
  474. if (msdu_info->exception_fw &&
  475. qdf_unlikely(vdev->mesh_vdev)) {
  476. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  477. &msdu_info->meta_data[0],
  478. sizeof(struct htt_tx_msdu_desc_ext2_t));
  479. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  480. }
  481. switch (msdu_info->frm_type) {
  482. case dp_tx_frm_sg:
  483. case dp_tx_frm_me:
  484. case dp_tx_frm_raw:
  485. seg_info = msdu_info->u.sg_info.curr_seg;
  486. /* Update the buffer pointers in MSDU Extension Descriptor */
  487. for (i = 0; i < seg_info->frag_cnt; i++) {
  488. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  489. seg_info->frags[i].paddr_lo,
  490. seg_info->frags[i].paddr_hi,
  491. seg_info->frags[i].len);
  492. }
  493. break;
  494. case dp_tx_frm_tso:
  495. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  496. &cached_ext_desc[0]);
  497. break;
  498. default:
  499. break;
  500. }
  501. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  502. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  503. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  504. msdu_ext_desc->vaddr);
  505. return msdu_ext_desc;
  506. }
  507. /**
  508. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  509. *
  510. * @skb: skb to be traced
  511. * @msdu_id: msdu_id of the packet
  512. * @vdev_id: vdev_id of the packet
  513. *
  514. * Return: None
  515. */
  516. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  517. uint8_t vdev_id)
  518. {
  519. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  520. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  521. DPTRACE(qdf_dp_trace_ptr(skb,
  522. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  523. QDF_TRACE_DEFAULT_PDEV_ID,
  524. qdf_nbuf_data_addr(skb),
  525. sizeof(qdf_nbuf_data(skb)),
  526. msdu_id, vdev_id));
  527. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  528. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  529. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  530. msdu_id, QDF_TX));
  531. }
  532. #ifdef QCA_512M_CONFIG
  533. /**
  534. * dp_tx_pdev_pflow_control - Check if allocated tx descriptors reached max
  535. * tx descriptor configured value
  536. * @vdev: DP vdev handle
  537. *
  538. * Return: true if allocated tx descriptors reached max configured value, else
  539. * false.
  540. */
  541. static inline bool
  542. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  543. {
  544. struct dp_pdev *pdev = vdev->pdev;
  545. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  546. pdev->num_tx_allowed) {
  547. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  548. "%s: queued packets are more than max tx, drop the frame",
  549. __func__);
  550. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  551. return true;
  552. }
  553. return false;
  554. }
  555. #else
  556. static inline bool
  557. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  558. {
  559. return false;
  560. }
  561. #endif
  562. /**
  563. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  564. * @vdev: DP vdev handle
  565. * @nbuf: skb
  566. * @desc_pool_id: Descriptor pool ID
  567. * @meta_data: Metadata to the fw
  568. * @tx_exc_metadata: Handle that holds exception path metadata
  569. * Allocate and prepare Tx descriptor with msdu information.
  570. *
  571. * Return: Pointer to Tx Descriptor on success,
  572. * NULL on failure
  573. */
  574. static
  575. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  576. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  577. struct dp_tx_msdu_info_s *msdu_info,
  578. struct cdp_tx_exception_metadata *tx_exc_metadata)
  579. {
  580. uint8_t align_pad;
  581. uint8_t is_exception = 0;
  582. uint8_t htt_hdr_size;
  583. qdf_ether_header_t *eh;
  584. struct dp_tx_desc_s *tx_desc;
  585. struct dp_pdev *pdev = vdev->pdev;
  586. struct dp_soc *soc = pdev->soc;
  587. if (dp_tx_pdev_pflow_control(vdev))
  588. return NULL;
  589. /* Allocate software Tx descriptor */
  590. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  591. if (qdf_unlikely(!tx_desc)) {
  592. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  593. return NULL;
  594. }
  595. /* Flow control/Congestion Control counters */
  596. qdf_atomic_inc(&pdev->num_tx_outstanding);
  597. /* Initialize the SW tx descriptor */
  598. tx_desc->nbuf = nbuf;
  599. tx_desc->frm_type = dp_tx_frm_std;
  600. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  601. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  602. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  603. tx_desc->vdev = vdev;
  604. tx_desc->pdev = pdev;
  605. tx_desc->msdu_ext_desc = NULL;
  606. tx_desc->pkt_offset = 0;
  607. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  608. /*
  609. * For special modes (vdev_type == ocb or mesh), data frames should be
  610. * transmitted using varying transmit parameters (tx spec) which include
  611. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  612. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  613. * These frames are sent as exception packets to firmware.
  614. *
  615. * HW requirement is that metadata should always point to a
  616. * 8-byte aligned address. So we add alignment pad to start of buffer.
  617. * HTT Metadata should be ensured to be multiple of 8-bytes,
  618. * to get 8-byte aligned start address along with align_pad added
  619. *
  620. * |-----------------------------|
  621. * | |
  622. * |-----------------------------| <-----Buffer Pointer Address given
  623. * | | ^ in HW descriptor (aligned)
  624. * | HTT Metadata | |
  625. * | | |
  626. * | | | Packet Offset given in descriptor
  627. * | | |
  628. * |-----------------------------| |
  629. * | Alignment Pad | v
  630. * |-----------------------------| <----- Actual buffer start address
  631. * | SKB Data | (Unaligned)
  632. * | |
  633. * | |
  634. * | |
  635. * | |
  636. * | |
  637. * |-----------------------------|
  638. */
  639. if (qdf_unlikely((msdu_info->exception_fw)) ||
  640. (vdev->opmode == wlan_op_mode_ocb) ||
  641. (tx_exc_metadata &&
  642. tx_exc_metadata->is_tx_sniffer)) {
  643. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  644. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  645. DP_STATS_INC(vdev,
  646. tx_i.dropped.headroom_insufficient, 1);
  647. goto failure;
  648. }
  649. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  650. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  651. "qdf_nbuf_push_head failed");
  652. goto failure;
  653. }
  654. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  655. msdu_info);
  656. if (htt_hdr_size == 0)
  657. goto failure;
  658. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  659. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  660. is_exception = 1;
  661. }
  662. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  663. qdf_nbuf_map(soc->osdev, nbuf,
  664. QDF_DMA_TO_DEVICE))) {
  665. /* Handle failure */
  666. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  667. "qdf_nbuf_map failed");
  668. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  669. goto failure;
  670. }
  671. if (qdf_unlikely(vdev->nawds_enabled)) {
  672. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  673. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  674. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  675. is_exception = 1;
  676. }
  677. }
  678. #if !TQM_BYPASS_WAR
  679. if (is_exception || tx_exc_metadata)
  680. #endif
  681. {
  682. /* Temporary WAR due to TQM VP issues */
  683. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  684. qdf_atomic_inc(&pdev->num_tx_exception);
  685. }
  686. return tx_desc;
  687. failure:
  688. dp_tx_desc_release(tx_desc, desc_pool_id);
  689. return NULL;
  690. }
  691. /**
  692. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  693. * @vdev: DP vdev handle
  694. * @nbuf: skb
  695. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  696. * @desc_pool_id : Descriptor Pool ID
  697. *
  698. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  699. * information. For frames wth fragments, allocate and prepare
  700. * an MSDU extension descriptor
  701. *
  702. * Return: Pointer to Tx Descriptor on success,
  703. * NULL on failure
  704. */
  705. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  706. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  707. uint8_t desc_pool_id)
  708. {
  709. struct dp_tx_desc_s *tx_desc;
  710. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  711. struct dp_pdev *pdev = vdev->pdev;
  712. struct dp_soc *soc = pdev->soc;
  713. if (dp_tx_pdev_pflow_control(vdev))
  714. return NULL;
  715. /* Allocate software Tx descriptor */
  716. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  717. if (!tx_desc) {
  718. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  719. return NULL;
  720. }
  721. /* Flow control/Congestion Control counters */
  722. qdf_atomic_inc(&pdev->num_tx_outstanding);
  723. /* Initialize the SW tx descriptor */
  724. tx_desc->nbuf = nbuf;
  725. tx_desc->frm_type = msdu_info->frm_type;
  726. tx_desc->tx_encap_type = vdev->tx_encap_type;
  727. tx_desc->vdev = vdev;
  728. tx_desc->pdev = pdev;
  729. tx_desc->pkt_offset = 0;
  730. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  731. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  732. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  733. /* Handle scattered frames - TSO/SG/ME */
  734. /* Allocate and prepare an extension descriptor for scattered frames */
  735. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  736. if (!msdu_ext_desc) {
  737. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  738. "%s Tx Extension Descriptor Alloc Fail",
  739. __func__);
  740. goto failure;
  741. }
  742. #if TQM_BYPASS_WAR
  743. /* Temporary WAR due to TQM VP issues */
  744. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  745. qdf_atomic_inc(&pdev->num_tx_exception);
  746. #endif
  747. if (qdf_unlikely(msdu_info->exception_fw))
  748. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  749. tx_desc->msdu_ext_desc = msdu_ext_desc;
  750. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  751. return tx_desc;
  752. failure:
  753. dp_tx_desc_release(tx_desc, desc_pool_id);
  754. return NULL;
  755. }
  756. /**
  757. * dp_tx_prepare_raw() - Prepare RAW packet TX
  758. * @vdev: DP vdev handle
  759. * @nbuf: buffer pointer
  760. * @seg_info: Pointer to Segment info Descriptor to be prepared
  761. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  762. * descriptor
  763. *
  764. * Return:
  765. */
  766. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  767. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  768. {
  769. qdf_nbuf_t curr_nbuf = NULL;
  770. uint16_t total_len = 0;
  771. qdf_dma_addr_t paddr;
  772. int32_t i;
  773. int32_t mapped_buf_num = 0;
  774. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  775. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  776. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  777. /* Continue only if frames are of DATA type */
  778. if (!DP_FRAME_IS_DATA(qos_wh)) {
  779. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  780. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  781. "Pkt. recd is of not data type");
  782. goto error;
  783. }
  784. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  785. if (vdev->raw_mode_war &&
  786. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  787. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  788. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  789. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  790. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  791. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  792. QDF_DMA_TO_DEVICE)) {
  793. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  794. "%s dma map error ", __func__);
  795. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  796. mapped_buf_num = i;
  797. goto error;
  798. }
  799. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  800. seg_info->frags[i].paddr_lo = paddr;
  801. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  802. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  803. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  804. total_len += qdf_nbuf_len(curr_nbuf);
  805. }
  806. seg_info->frag_cnt = i;
  807. seg_info->total_len = total_len;
  808. seg_info->next = NULL;
  809. sg_info->curr_seg = seg_info;
  810. msdu_info->frm_type = dp_tx_frm_raw;
  811. msdu_info->num_seg = 1;
  812. return nbuf;
  813. error:
  814. i = 0;
  815. while (nbuf) {
  816. curr_nbuf = nbuf;
  817. if (i < mapped_buf_num) {
  818. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  819. i++;
  820. }
  821. nbuf = qdf_nbuf_next(nbuf);
  822. qdf_nbuf_free(curr_nbuf);
  823. }
  824. return NULL;
  825. }
  826. /**
  827. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  828. * @soc: DP soc handle
  829. * @nbuf: Buffer pointer
  830. *
  831. * unmap the chain of nbufs that belong to this RAW frame.
  832. *
  833. * Return: None
  834. */
  835. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  836. qdf_nbuf_t nbuf)
  837. {
  838. qdf_nbuf_t cur_nbuf = nbuf;
  839. do {
  840. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  841. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  842. } while (cur_nbuf);
  843. }
  844. /**
  845. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  846. * @soc: DP Soc Handle
  847. * @vdev: DP vdev handle
  848. * @tx_desc: Tx Descriptor Handle
  849. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  850. * @fw_metadata: Metadata to send to Target Firmware along with frame
  851. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  852. * @tx_exc_metadata: Handle that holds exception path meta data
  853. *
  854. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  855. * from software Tx descriptor
  856. *
  857. * Return:
  858. */
  859. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  860. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  861. uint16_t fw_metadata, uint8_t ring_id,
  862. struct cdp_tx_exception_metadata
  863. *tx_exc_metadata)
  864. {
  865. uint8_t type;
  866. uint16_t length;
  867. void *hal_tx_desc, *hal_tx_desc_cached;
  868. qdf_dma_addr_t dma_addr;
  869. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  870. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  871. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  872. tx_exc_metadata->sec_type : vdev->sec_type);
  873. /* Return Buffer Manager ID */
  874. uint8_t bm_id = ring_id;
  875. hal_ring_handle_t hal_ring_hdl = soc->tcl_data_ring[ring_id].hal_srng;
  876. hal_tx_desc_cached = (void *) cached_desc;
  877. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  878. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  879. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  880. type = HAL_TX_BUF_TYPE_EXT_DESC;
  881. dma_addr = tx_desc->msdu_ext_desc->paddr;
  882. } else {
  883. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  884. type = HAL_TX_BUF_TYPE_BUFFER;
  885. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  886. }
  887. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  888. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  889. dma_addr, bm_id, tx_desc->id,
  890. type, soc->hal_soc);
  891. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  892. return QDF_STATUS_E_RESOURCES;
  893. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  894. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  895. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  896. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  897. vdev->pdev->lmac_id);
  898. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  899. vdev->search_type);
  900. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  901. vdev->bss_ast_hash);
  902. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  903. vdev->dscp_tid_map_id);
  904. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  905. sec_type_map[sec_type]);
  906. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  907. length, type, (uint64_t)dma_addr,
  908. tx_desc->pkt_offset, tx_desc->id);
  909. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  910. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  911. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  912. vdev->hal_desc_addr_search_flags);
  913. /* verify checksum offload configuration*/
  914. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  915. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  916. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  917. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  918. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  919. }
  920. if (tid != HTT_TX_EXT_TID_INVALID)
  921. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  922. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  923. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  924. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  925. /* Sync cached descriptor with HW */
  926. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  927. if (!hal_tx_desc) {
  928. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  929. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  930. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  931. return QDF_STATUS_E_RESOURCES;
  932. }
  933. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  934. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  935. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  936. return QDF_STATUS_SUCCESS;
  937. }
  938. /**
  939. * dp_cce_classify() - Classify the frame based on CCE rules
  940. * @vdev: DP vdev handle
  941. * @nbuf: skb
  942. *
  943. * Classify frames based on CCE rules
  944. * Return: bool( true if classified,
  945. * else false)
  946. */
  947. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  948. {
  949. qdf_ether_header_t *eh = NULL;
  950. uint16_t ether_type;
  951. qdf_llc_t *llcHdr;
  952. qdf_nbuf_t nbuf_clone = NULL;
  953. qdf_dot3_qosframe_t *qos_wh = NULL;
  954. /* for mesh packets don't do any classification */
  955. if (qdf_unlikely(vdev->mesh_vdev))
  956. return false;
  957. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  958. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  959. ether_type = eh->ether_type;
  960. llcHdr = (qdf_llc_t *)(nbuf->data +
  961. sizeof(qdf_ether_header_t));
  962. } else {
  963. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  964. /* For encrypted packets don't do any classification */
  965. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  966. return false;
  967. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  968. if (qdf_unlikely(
  969. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  970. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  971. ether_type = *(uint16_t *)(nbuf->data
  972. + QDF_IEEE80211_4ADDR_HDR_LEN
  973. + sizeof(qdf_llc_t)
  974. - sizeof(ether_type));
  975. llcHdr = (qdf_llc_t *)(nbuf->data +
  976. QDF_IEEE80211_4ADDR_HDR_LEN);
  977. } else {
  978. ether_type = *(uint16_t *)(nbuf->data
  979. + QDF_IEEE80211_3ADDR_HDR_LEN
  980. + sizeof(qdf_llc_t)
  981. - sizeof(ether_type));
  982. llcHdr = (qdf_llc_t *)(nbuf->data +
  983. QDF_IEEE80211_3ADDR_HDR_LEN);
  984. }
  985. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  986. && (ether_type ==
  987. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  988. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  989. return true;
  990. }
  991. }
  992. return false;
  993. }
  994. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  995. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  996. sizeof(*llcHdr));
  997. nbuf_clone = qdf_nbuf_clone(nbuf);
  998. if (qdf_unlikely(nbuf_clone)) {
  999. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1000. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1001. qdf_nbuf_pull_head(nbuf_clone,
  1002. sizeof(qdf_net_vlanhdr_t));
  1003. }
  1004. }
  1005. } else {
  1006. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1007. nbuf_clone = qdf_nbuf_clone(nbuf);
  1008. if (qdf_unlikely(nbuf_clone)) {
  1009. qdf_nbuf_pull_head(nbuf_clone,
  1010. sizeof(qdf_net_vlanhdr_t));
  1011. }
  1012. }
  1013. }
  1014. if (qdf_unlikely(nbuf_clone))
  1015. nbuf = nbuf_clone;
  1016. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1017. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1018. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1019. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1020. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1021. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1022. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1023. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1024. if (qdf_unlikely(nbuf_clone))
  1025. qdf_nbuf_free(nbuf_clone);
  1026. return true;
  1027. }
  1028. if (qdf_unlikely(nbuf_clone))
  1029. qdf_nbuf_free(nbuf_clone);
  1030. return false;
  1031. }
  1032. /**
  1033. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1034. * @vdev: DP vdev handle
  1035. * @nbuf: skb
  1036. *
  1037. * Extract the DSCP or PCP information from frame and map into TID value.
  1038. *
  1039. * Return: void
  1040. */
  1041. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1042. struct dp_tx_msdu_info_s *msdu_info)
  1043. {
  1044. uint8_t tos = 0, dscp_tid_override = 0;
  1045. uint8_t *hdr_ptr, *L3datap;
  1046. uint8_t is_mcast = 0;
  1047. qdf_ether_header_t *eh = NULL;
  1048. qdf_ethervlan_header_t *evh = NULL;
  1049. uint16_t ether_type;
  1050. qdf_llc_t *llcHdr;
  1051. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1052. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1053. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1054. eh = (qdf_ether_header_t *)nbuf->data;
  1055. hdr_ptr = eh->ether_dhost;
  1056. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1057. } else {
  1058. qdf_dot3_qosframe_t *qos_wh =
  1059. (qdf_dot3_qosframe_t *) nbuf->data;
  1060. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1061. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1062. return;
  1063. }
  1064. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1065. ether_type = eh->ether_type;
  1066. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1067. /*
  1068. * Check if packet is dot3 or eth2 type.
  1069. */
  1070. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1071. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1072. sizeof(*llcHdr));
  1073. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1074. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1075. sizeof(*llcHdr);
  1076. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1077. + sizeof(*llcHdr) +
  1078. sizeof(qdf_net_vlanhdr_t));
  1079. } else {
  1080. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1081. sizeof(*llcHdr);
  1082. }
  1083. } else {
  1084. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1085. evh = (qdf_ethervlan_header_t *) eh;
  1086. ether_type = evh->ether_type;
  1087. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1088. }
  1089. }
  1090. /*
  1091. * Find priority from IP TOS DSCP field
  1092. */
  1093. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1094. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1095. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1096. /* Only for unicast frames */
  1097. if (!is_mcast) {
  1098. /* send it on VO queue */
  1099. msdu_info->tid = DP_VO_TID;
  1100. }
  1101. } else {
  1102. /*
  1103. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1104. * from TOS byte.
  1105. */
  1106. tos = ip->ip_tos;
  1107. dscp_tid_override = 1;
  1108. }
  1109. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1110. /* TODO
  1111. * use flowlabel
  1112. *igmpmld cases to be handled in phase 2
  1113. */
  1114. unsigned long ver_pri_flowlabel;
  1115. unsigned long pri;
  1116. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1117. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1118. DP_IPV6_PRIORITY_SHIFT;
  1119. tos = pri;
  1120. dscp_tid_override = 1;
  1121. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1122. msdu_info->tid = DP_VO_TID;
  1123. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1124. /* Only for unicast frames */
  1125. if (!is_mcast) {
  1126. /* send ucast arp on VO queue */
  1127. msdu_info->tid = DP_VO_TID;
  1128. }
  1129. }
  1130. /*
  1131. * Assign all MCAST packets to BE
  1132. */
  1133. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1134. if (is_mcast) {
  1135. tos = 0;
  1136. dscp_tid_override = 1;
  1137. }
  1138. }
  1139. if (dscp_tid_override == 1) {
  1140. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1141. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1142. }
  1143. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1144. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1145. return;
  1146. }
  1147. /**
  1148. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1149. * @vdev: DP vdev handle
  1150. * @nbuf: skb
  1151. *
  1152. * Software based TID classification is required when more than 2 DSCP-TID
  1153. * mapping tables are needed.
  1154. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1155. *
  1156. * Return: void
  1157. */
  1158. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1159. struct dp_tx_msdu_info_s *msdu_info)
  1160. {
  1161. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1162. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1163. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1164. return;
  1165. /* for mesh packets don't do any classification */
  1166. if (qdf_unlikely(vdev->mesh_vdev))
  1167. return;
  1168. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1169. }
  1170. #ifdef FEATURE_WLAN_TDLS
  1171. /**
  1172. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1173. * @tx_desc: TX descriptor
  1174. *
  1175. * Return: None
  1176. */
  1177. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1178. {
  1179. if (tx_desc->vdev) {
  1180. if (tx_desc->vdev->is_tdls_frame) {
  1181. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1182. tx_desc->vdev->is_tdls_frame = false;
  1183. }
  1184. }
  1185. }
  1186. /**
  1187. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1188. * @tx_desc: TX descriptor
  1189. * @vdev: datapath vdev handle
  1190. *
  1191. * Return: None
  1192. */
  1193. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1194. struct dp_vdev *vdev)
  1195. {
  1196. struct hal_tx_completion_status ts = {0};
  1197. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1198. if (qdf_unlikely(!vdev)) {
  1199. dp_err("vdev is null!");
  1200. return;
  1201. }
  1202. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1203. if (vdev->tx_non_std_data_callback.func) {
  1204. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1205. vdev->tx_non_std_data_callback.func(
  1206. vdev->tx_non_std_data_callback.ctxt,
  1207. nbuf, ts.status);
  1208. return;
  1209. }
  1210. }
  1211. #else
  1212. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1213. {
  1214. }
  1215. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1216. struct dp_vdev *vdev)
  1217. {
  1218. }
  1219. #endif
  1220. /**
  1221. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1222. * @vdev: DP vdev handle
  1223. * @nbuf: skb
  1224. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1225. * @meta_data: Metadata to the fw
  1226. * @tx_q: Tx queue to be used for this Tx frame
  1227. * @peer_id: peer_id of the peer in case of NAWDS frames
  1228. * @tx_exc_metadata: Handle that holds exception path metadata
  1229. *
  1230. * Return: NULL on success,
  1231. * nbuf when it fails to send
  1232. */
  1233. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1234. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1235. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1236. {
  1237. struct dp_pdev *pdev = vdev->pdev;
  1238. struct dp_soc *soc = pdev->soc;
  1239. struct dp_tx_desc_s *tx_desc;
  1240. QDF_STATUS status;
  1241. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1242. hal_ring_handle_t hal_ring_hdl =
  1243. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1244. uint16_t htt_tcl_metadata = 0;
  1245. uint8_t tid = msdu_info->tid;
  1246. struct cdp_tid_tx_stats *tid_stats = NULL;
  1247. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1248. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1249. msdu_info, tx_exc_metadata);
  1250. if (!tx_desc) {
  1251. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1252. vdev, tx_q->desc_pool_id);
  1253. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1254. tid_stats = &pdev->stats.tid_stats.
  1255. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1256. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1257. return nbuf;
  1258. }
  1259. if (qdf_unlikely(soc->cce_disable)) {
  1260. if (dp_cce_classify(vdev, nbuf) == true) {
  1261. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1262. tid = DP_VO_TID;
  1263. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1264. }
  1265. }
  1266. dp_tx_update_tdls_flags(tx_desc);
  1267. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1268. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1269. "%s %d : HAL RING Access Failed -- %pK",
  1270. __func__, __LINE__, hal_ring_hdl);
  1271. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1272. tid_stats = &pdev->stats.tid_stats.
  1273. tid_tx_stats[tx_q->ring_id][tid];
  1274. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1275. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1276. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1277. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1278. goto fail_return;
  1279. }
  1280. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1281. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1282. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1283. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1284. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1285. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1286. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1287. peer_id);
  1288. } else
  1289. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1290. if (msdu_info->exception_fw) {
  1291. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1292. }
  1293. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1294. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1295. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1296. if (status != QDF_STATUS_SUCCESS) {
  1297. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1298. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1299. __func__, tx_desc, tx_q->ring_id);
  1300. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1301. tid_stats = &pdev->stats.tid_stats.
  1302. tid_tx_stats[tx_q->ring_id][tid];
  1303. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1304. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1305. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1306. goto fail_return;
  1307. }
  1308. nbuf = NULL;
  1309. fail_return:
  1310. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1311. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1312. hif_pm_runtime_put(soc->hif_handle);
  1313. } else {
  1314. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1315. }
  1316. return nbuf;
  1317. }
  1318. /**
  1319. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1320. * @vdev: DP vdev handle
  1321. * @nbuf: skb
  1322. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1323. *
  1324. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1325. *
  1326. * Return: NULL on success,
  1327. * nbuf when it fails to send
  1328. */
  1329. #if QDF_LOCK_STATS
  1330. noinline
  1331. #else
  1332. #endif
  1333. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1334. struct dp_tx_msdu_info_s *msdu_info)
  1335. {
  1336. uint8_t i;
  1337. struct dp_pdev *pdev = vdev->pdev;
  1338. struct dp_soc *soc = pdev->soc;
  1339. struct dp_tx_desc_s *tx_desc;
  1340. bool is_cce_classified = false;
  1341. QDF_STATUS status;
  1342. uint16_t htt_tcl_metadata = 0;
  1343. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1344. hal_ring_handle_t hal_ring_hdl =
  1345. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1346. struct cdp_tid_tx_stats *tid_stats = NULL;
  1347. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1348. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1349. "%s %d : HAL RING Access Failed -- %pK",
  1350. __func__, __LINE__, hal_ring_hdl);
  1351. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1352. tid_stats = &pdev->stats.tid_stats.
  1353. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1354. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1355. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1356. return nbuf;
  1357. }
  1358. if (qdf_unlikely(soc->cce_disable)) {
  1359. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1360. if (is_cce_classified) {
  1361. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1362. msdu_info->tid = DP_VO_TID;
  1363. }
  1364. }
  1365. if (msdu_info->frm_type == dp_tx_frm_me)
  1366. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1367. i = 0;
  1368. /* Print statement to track i and num_seg */
  1369. /*
  1370. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1371. * descriptors using information in msdu_info
  1372. */
  1373. while (i < msdu_info->num_seg) {
  1374. /*
  1375. * Setup Tx descriptor for an MSDU, and MSDU extension
  1376. * descriptor
  1377. */
  1378. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1379. tx_q->desc_pool_id);
  1380. if (!tx_desc) {
  1381. if (msdu_info->frm_type == dp_tx_frm_me) {
  1382. dp_tx_me_free_buf(pdev,
  1383. (void *)(msdu_info->u.sg_info
  1384. .curr_seg->frags[0].vaddr));
  1385. }
  1386. goto done;
  1387. }
  1388. if (msdu_info->frm_type == dp_tx_frm_me) {
  1389. tx_desc->me_buffer =
  1390. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1391. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1392. }
  1393. if (is_cce_classified)
  1394. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1395. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1396. if (msdu_info->exception_fw) {
  1397. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1398. }
  1399. /*
  1400. * Enqueue the Tx MSDU descriptor to HW for transmit
  1401. */
  1402. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1403. htt_tcl_metadata, tx_q->ring_id, NULL);
  1404. if (status != QDF_STATUS_SUCCESS) {
  1405. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1406. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1407. __func__, tx_desc, tx_q->ring_id);
  1408. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1409. tid_stats = &pdev->stats.tid_stats.
  1410. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1411. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1412. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1413. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1414. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1415. goto done;
  1416. }
  1417. /*
  1418. * TODO
  1419. * if tso_info structure can be modified to have curr_seg
  1420. * as first element, following 2 blocks of code (for TSO and SG)
  1421. * can be combined into 1
  1422. */
  1423. /*
  1424. * For frames with multiple segments (TSO, ME), jump to next
  1425. * segment.
  1426. */
  1427. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1428. if (msdu_info->u.tso_info.curr_seg->next) {
  1429. msdu_info->u.tso_info.curr_seg =
  1430. msdu_info->u.tso_info.curr_seg->next;
  1431. /*
  1432. * If this is a jumbo nbuf, then increment the number of
  1433. * nbuf users for each additional segment of the msdu.
  1434. * This will ensure that the skb is freed only after
  1435. * receiving tx completion for all segments of an nbuf
  1436. */
  1437. qdf_nbuf_inc_users(nbuf);
  1438. /* Check with MCL if this is needed */
  1439. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1440. }
  1441. }
  1442. /*
  1443. * For Multicast-Unicast converted packets,
  1444. * each converted frame (for a client) is represented as
  1445. * 1 segment
  1446. */
  1447. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1448. (msdu_info->frm_type == dp_tx_frm_me)) {
  1449. if (msdu_info->u.sg_info.curr_seg->next) {
  1450. msdu_info->u.sg_info.curr_seg =
  1451. msdu_info->u.sg_info.curr_seg->next;
  1452. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1453. }
  1454. }
  1455. i++;
  1456. }
  1457. nbuf = NULL;
  1458. done:
  1459. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1460. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1461. hif_pm_runtime_put(soc->hif_handle);
  1462. } else {
  1463. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1464. }
  1465. return nbuf;
  1466. }
  1467. /**
  1468. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1469. * for SG frames
  1470. * @vdev: DP vdev handle
  1471. * @nbuf: skb
  1472. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1473. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1474. *
  1475. * Return: NULL on success,
  1476. * nbuf when it fails to send
  1477. */
  1478. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1479. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1480. {
  1481. uint32_t cur_frag, nr_frags;
  1482. qdf_dma_addr_t paddr;
  1483. struct dp_tx_sg_info_s *sg_info;
  1484. sg_info = &msdu_info->u.sg_info;
  1485. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1486. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1487. QDF_DMA_TO_DEVICE)) {
  1488. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1489. "dma map error");
  1490. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1491. qdf_nbuf_free(nbuf);
  1492. return NULL;
  1493. }
  1494. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1495. seg_info->frags[0].paddr_lo = paddr;
  1496. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1497. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1498. seg_info->frags[0].vaddr = (void *) nbuf;
  1499. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1500. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1501. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1502. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1503. "frag dma map error");
  1504. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1505. qdf_nbuf_free(nbuf);
  1506. return NULL;
  1507. }
  1508. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1509. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1510. seg_info->frags[cur_frag + 1].paddr_hi =
  1511. ((uint64_t) paddr) >> 32;
  1512. seg_info->frags[cur_frag + 1].len =
  1513. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1514. }
  1515. seg_info->frag_cnt = (cur_frag + 1);
  1516. seg_info->total_len = qdf_nbuf_len(nbuf);
  1517. seg_info->next = NULL;
  1518. sg_info->curr_seg = seg_info;
  1519. msdu_info->frm_type = dp_tx_frm_sg;
  1520. msdu_info->num_seg = 1;
  1521. return nbuf;
  1522. }
  1523. /**
  1524. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1525. * @vdev: DP vdev handle
  1526. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1527. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1528. *
  1529. * Return: NULL on failure,
  1530. * nbuf when extracted successfully
  1531. */
  1532. static
  1533. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1534. struct dp_tx_msdu_info_s *msdu_info,
  1535. uint16_t ppdu_cookie)
  1536. {
  1537. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1538. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1539. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1540. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1541. (msdu_info->meta_data[5], 1);
  1542. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1543. (msdu_info->meta_data[5], 1);
  1544. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1545. (msdu_info->meta_data[6], ppdu_cookie);
  1546. msdu_info->exception_fw = 1;
  1547. msdu_info->is_tx_sniffer = 1;
  1548. }
  1549. #ifdef MESH_MODE_SUPPORT
  1550. /**
  1551. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1552. and prepare msdu_info for mesh frames.
  1553. * @vdev: DP vdev handle
  1554. * @nbuf: skb
  1555. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1556. *
  1557. * Return: NULL on failure,
  1558. * nbuf when extracted successfully
  1559. */
  1560. static
  1561. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1562. struct dp_tx_msdu_info_s *msdu_info)
  1563. {
  1564. struct meta_hdr_s *mhdr;
  1565. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1566. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1567. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1568. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1569. msdu_info->exception_fw = 0;
  1570. goto remove_meta_hdr;
  1571. }
  1572. msdu_info->exception_fw = 1;
  1573. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1574. meta_data->host_tx_desc_pool = 1;
  1575. meta_data->update_peer_cache = 1;
  1576. meta_data->learning_frame = 1;
  1577. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1578. meta_data->power = mhdr->power;
  1579. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1580. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1581. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1582. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1583. meta_data->dyn_bw = 1;
  1584. meta_data->valid_pwr = 1;
  1585. meta_data->valid_mcs_mask = 1;
  1586. meta_data->valid_nss_mask = 1;
  1587. meta_data->valid_preamble_type = 1;
  1588. meta_data->valid_retries = 1;
  1589. meta_data->valid_bw_info = 1;
  1590. }
  1591. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1592. meta_data->encrypt_type = 0;
  1593. meta_data->valid_encrypt_type = 1;
  1594. meta_data->learning_frame = 0;
  1595. }
  1596. meta_data->valid_key_flags = 1;
  1597. meta_data->key_flags = (mhdr->keyix & 0x3);
  1598. remove_meta_hdr:
  1599. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1600. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1601. "qdf_nbuf_pull_head failed");
  1602. qdf_nbuf_free(nbuf);
  1603. return NULL;
  1604. }
  1605. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1606. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1607. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1608. " tid %d to_fw %d",
  1609. __func__, msdu_info->meta_data[0],
  1610. msdu_info->meta_data[1],
  1611. msdu_info->meta_data[2],
  1612. msdu_info->meta_data[3],
  1613. msdu_info->meta_data[4],
  1614. msdu_info->meta_data[5],
  1615. msdu_info->tid, msdu_info->exception_fw);
  1616. return nbuf;
  1617. }
  1618. #else
  1619. static
  1620. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1621. struct dp_tx_msdu_info_s *msdu_info)
  1622. {
  1623. return nbuf;
  1624. }
  1625. #endif
  1626. /**
  1627. * dp_check_exc_metadata() - Checks if parameters are valid
  1628. * @tx_exc - holds all exception path parameters
  1629. *
  1630. * Returns true when all the parameters are valid else false
  1631. *
  1632. */
  1633. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1634. {
  1635. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1636. HTT_INVALID_TID);
  1637. bool invalid_encap_type =
  1638. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1639. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1640. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1641. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1642. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1643. tx_exc->ppdu_cookie == 0);
  1644. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1645. invalid_cookie) {
  1646. return false;
  1647. }
  1648. return true;
  1649. }
  1650. /**
  1651. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1652. * @vap_dev: DP vdev handle
  1653. * @nbuf: skb
  1654. * @tx_exc_metadata: Handle that holds exception path meta data
  1655. *
  1656. * Entry point for Core Tx layer (DP_TX) invoked from
  1657. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1658. *
  1659. * Return: NULL on success,
  1660. * nbuf when it fails to send
  1661. */
  1662. qdf_nbuf_t
  1663. dp_tx_send_exception(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf,
  1664. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1665. {
  1666. qdf_ether_header_t *eh = NULL;
  1667. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1668. struct dp_tx_msdu_info_s msdu_info;
  1669. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1670. if (!tx_exc_metadata)
  1671. goto fail;
  1672. msdu_info.tid = tx_exc_metadata->tid;
  1673. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1674. dp_verbose_debug("skb %pM", nbuf->data);
  1675. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1676. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1677. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1678. "Invalid parameters in exception path");
  1679. goto fail;
  1680. }
  1681. /* Basic sanity checks for unsupported packets */
  1682. /* MESH mode */
  1683. if (qdf_unlikely(vdev->mesh_vdev)) {
  1684. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1685. "Mesh mode is not supported in exception path");
  1686. goto fail;
  1687. }
  1688. /* TSO or SG */
  1689. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1690. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1691. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1692. "TSO and SG are not supported in exception path");
  1693. goto fail;
  1694. }
  1695. /* RAW */
  1696. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1697. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1698. "Raw frame is not supported in exception path");
  1699. goto fail;
  1700. }
  1701. /* Mcast enhancement*/
  1702. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1703. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1704. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1705. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1706. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1707. }
  1708. }
  1709. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1710. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1711. qdf_nbuf_len(nbuf));
  1712. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1713. tx_exc_metadata->ppdu_cookie);
  1714. }
  1715. /*
  1716. * Get HW Queue to use for this frame.
  1717. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1718. * dedicated for data and 1 for command.
  1719. * "queue_id" maps to one hardware ring.
  1720. * With each ring, we also associate a unique Tx descriptor pool
  1721. * to minimize lock contention for these resources.
  1722. */
  1723. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1724. /* Single linear frame */
  1725. /*
  1726. * If nbuf is a simple linear frame, use send_single function to
  1727. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1728. * SRNG. There is no need to setup a MSDU extension descriptor.
  1729. */
  1730. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1731. tx_exc_metadata->peer_id, tx_exc_metadata);
  1732. return nbuf;
  1733. fail:
  1734. dp_verbose_debug("pkt send failed");
  1735. return nbuf;
  1736. }
  1737. /**
  1738. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1739. * @vap_dev: DP vdev handle
  1740. * @nbuf: skb
  1741. *
  1742. * Entry point for Core Tx layer (DP_TX) invoked from
  1743. * hard_start_xmit in OSIF/HDD
  1744. *
  1745. * Return: NULL on success,
  1746. * nbuf when it fails to send
  1747. */
  1748. #ifdef MESH_MODE_SUPPORT
  1749. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1750. {
  1751. struct meta_hdr_s *mhdr;
  1752. qdf_nbuf_t nbuf_mesh = NULL;
  1753. qdf_nbuf_t nbuf_clone = NULL;
  1754. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1755. uint8_t no_enc_frame = 0;
  1756. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1757. if (!nbuf_mesh) {
  1758. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1759. "qdf_nbuf_unshare failed");
  1760. return nbuf;
  1761. }
  1762. nbuf = nbuf_mesh;
  1763. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1764. if ((vdev->sec_type != cdp_sec_type_none) &&
  1765. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1766. no_enc_frame = 1;
  1767. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1768. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1769. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1770. !no_enc_frame) {
  1771. nbuf_clone = qdf_nbuf_clone(nbuf);
  1772. if (!nbuf_clone) {
  1773. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1774. "qdf_nbuf_clone failed");
  1775. return nbuf;
  1776. }
  1777. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1778. }
  1779. if (nbuf_clone) {
  1780. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1781. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1782. } else {
  1783. qdf_nbuf_free(nbuf_clone);
  1784. }
  1785. }
  1786. if (no_enc_frame)
  1787. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1788. else
  1789. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1790. nbuf = dp_tx_send(vap_dev, nbuf);
  1791. if ((!nbuf) && no_enc_frame) {
  1792. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1793. }
  1794. return nbuf;
  1795. }
  1796. #else
  1797. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1798. {
  1799. return dp_tx_send(vap_dev, nbuf);
  1800. }
  1801. #endif
  1802. /**
  1803. * dp_tx_send() - Transmit a frame on a given VAP
  1804. * @vap_dev: DP vdev handle
  1805. * @nbuf: skb
  1806. *
  1807. * Entry point for Core Tx layer (DP_TX) invoked from
  1808. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1809. * cases
  1810. *
  1811. * Return: NULL on success,
  1812. * nbuf when it fails to send
  1813. */
  1814. qdf_nbuf_t dp_tx_send(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1815. {
  1816. qdf_ether_header_t *eh = NULL;
  1817. struct dp_tx_msdu_info_s msdu_info;
  1818. struct dp_tx_seg_info_s seg_info;
  1819. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1820. uint16_t peer_id = HTT_INVALID_PEER;
  1821. qdf_nbuf_t nbuf_mesh = NULL;
  1822. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1823. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1824. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1825. dp_verbose_debug("skb %pM", nbuf->data);
  1826. /*
  1827. * Set Default Host TID value to invalid TID
  1828. * (TID override disabled)
  1829. */
  1830. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1831. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1832. if (qdf_unlikely(vdev->mesh_vdev)) {
  1833. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1834. &msdu_info);
  1835. if (!nbuf_mesh) {
  1836. dp_verbose_debug("Extracting mesh metadata failed");
  1837. return nbuf;
  1838. }
  1839. nbuf = nbuf_mesh;
  1840. }
  1841. /*
  1842. * Get HW Queue to use for this frame.
  1843. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1844. * dedicated for data and 1 for command.
  1845. * "queue_id" maps to one hardware ring.
  1846. * With each ring, we also associate a unique Tx descriptor pool
  1847. * to minimize lock contention for these resources.
  1848. */
  1849. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1850. /*
  1851. * TCL H/W supports 2 DSCP-TID mapping tables.
  1852. * Table 1 - Default DSCP-TID mapping table
  1853. * Table 2 - 1 DSCP-TID override table
  1854. *
  1855. * If we need a different DSCP-TID mapping for this vap,
  1856. * call tid_classify to extract DSCP/ToS from frame and
  1857. * map to a TID and store in msdu_info. This is later used
  1858. * to fill in TCL Input descriptor (per-packet TID override).
  1859. */
  1860. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1861. /*
  1862. * Classify the frame and call corresponding
  1863. * "prepare" function which extracts the segment (TSO)
  1864. * and fragmentation information (for TSO , SG, ME, or Raw)
  1865. * into MSDU_INFO structure which is later used to fill
  1866. * SW and HW descriptors.
  1867. */
  1868. if (qdf_nbuf_is_tso(nbuf)) {
  1869. dp_verbose_debug("TSO frame %pK", vdev);
  1870. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1871. qdf_nbuf_len(nbuf));
  1872. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1873. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1874. qdf_nbuf_len(nbuf));
  1875. return nbuf;
  1876. }
  1877. goto send_multiple;
  1878. }
  1879. /* SG */
  1880. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1881. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1882. if (!nbuf)
  1883. return NULL;
  1884. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1885. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1886. qdf_nbuf_len(nbuf));
  1887. goto send_multiple;
  1888. }
  1889. #ifdef ATH_SUPPORT_IQUE
  1890. /* Mcast to Ucast Conversion*/
  1891. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1892. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1893. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1894. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1895. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1896. DP_STATS_INC_PKT(vdev,
  1897. tx_i.mcast_en.mcast_pkt, 1,
  1898. qdf_nbuf_len(nbuf));
  1899. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1900. QDF_STATUS_SUCCESS) {
  1901. return NULL;
  1902. }
  1903. }
  1904. }
  1905. #endif
  1906. /* RAW */
  1907. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1908. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1909. if (!nbuf)
  1910. return NULL;
  1911. dp_verbose_debug("Raw frame %pK", vdev);
  1912. goto send_multiple;
  1913. }
  1914. /* Single linear frame */
  1915. /*
  1916. * If nbuf is a simple linear frame, use send_single function to
  1917. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1918. * SRNG. There is no need to setup a MSDU extension descriptor.
  1919. */
  1920. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1921. return nbuf;
  1922. send_multiple:
  1923. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1924. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  1925. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  1926. return nbuf;
  1927. }
  1928. /**
  1929. * dp_tx_reinject_handler() - Tx Reinject Handler
  1930. * @tx_desc: software descriptor head pointer
  1931. * @status : Tx completion status from HTT descriptor
  1932. *
  1933. * This function reinjects frames back to Target.
  1934. * Todo - Host queue needs to be added
  1935. *
  1936. * Return: none
  1937. */
  1938. static
  1939. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1940. {
  1941. struct dp_vdev *vdev;
  1942. struct dp_peer *peer = NULL;
  1943. uint32_t peer_id = HTT_INVALID_PEER;
  1944. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1945. qdf_nbuf_t nbuf_copy = NULL;
  1946. struct dp_tx_msdu_info_s msdu_info;
  1947. struct dp_peer *sa_peer = NULL;
  1948. struct dp_ast_entry *ast_entry = NULL;
  1949. struct dp_soc *soc = NULL;
  1950. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1951. #ifdef WDS_VENDOR_EXTENSION
  1952. int is_mcast = 0, is_ucast = 0;
  1953. int num_peers_3addr = 0;
  1954. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1955. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1956. #endif
  1957. vdev = tx_desc->vdev;
  1958. soc = vdev->pdev->soc;
  1959. qdf_assert(vdev);
  1960. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1961. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1962. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1963. "%s Tx reinject path", __func__);
  1964. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1965. qdf_nbuf_len(tx_desc->nbuf));
  1966. qdf_spin_lock_bh(&(soc->ast_lock));
  1967. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1968. (soc,
  1969. (uint8_t *)(eh->ether_shost),
  1970. vdev->pdev->pdev_id);
  1971. if (ast_entry)
  1972. sa_peer = ast_entry->peer;
  1973. qdf_spin_unlock_bh(&(soc->ast_lock));
  1974. #ifdef WDS_VENDOR_EXTENSION
  1975. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1976. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1977. } else {
  1978. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1979. }
  1980. is_ucast = !is_mcast;
  1981. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1982. if (peer->bss_peer)
  1983. continue;
  1984. /* Detect wds peers that use 3-addr framing for mcast.
  1985. * if there are any, the bss_peer is used to send the
  1986. * the mcast frame using 3-addr format. all wds enabled
  1987. * peers that use 4-addr framing for mcast frames will
  1988. * be duplicated and sent as 4-addr frames below.
  1989. */
  1990. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1991. num_peers_3addr = 1;
  1992. break;
  1993. }
  1994. }
  1995. #endif
  1996. if (qdf_unlikely(vdev->mesh_vdev)) {
  1997. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1998. } else {
  1999. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2000. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2001. #ifdef WDS_VENDOR_EXTENSION
  2002. /*
  2003. * . if 3-addr STA, then send on BSS Peer
  2004. * . if Peer WDS enabled and accept 4-addr mcast,
  2005. * send mcast on that peer only
  2006. * . if Peer WDS enabled and accept 4-addr ucast,
  2007. * send ucast on that peer only
  2008. */
  2009. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2010. (peer->wds_enabled &&
  2011. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2012. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2013. #else
  2014. ((peer->bss_peer &&
  2015. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2016. peer->nawds_enabled)) {
  2017. #endif
  2018. peer_id = DP_INVALID_PEER;
  2019. if (peer->nawds_enabled) {
  2020. peer_id = peer->peer_ids[0];
  2021. if (sa_peer == peer) {
  2022. QDF_TRACE(
  2023. QDF_MODULE_ID_DP,
  2024. QDF_TRACE_LEVEL_DEBUG,
  2025. " %s: multicast packet",
  2026. __func__);
  2027. DP_STATS_INC(peer,
  2028. tx.nawds_mcast_drop, 1);
  2029. continue;
  2030. }
  2031. }
  2032. nbuf_copy = qdf_nbuf_copy(nbuf);
  2033. if (!nbuf_copy) {
  2034. QDF_TRACE(QDF_MODULE_ID_DP,
  2035. QDF_TRACE_LEVEL_DEBUG,
  2036. FL("nbuf copy failed"));
  2037. break;
  2038. }
  2039. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2040. nbuf_copy,
  2041. &msdu_info,
  2042. peer_id,
  2043. NULL);
  2044. if (nbuf_copy) {
  2045. QDF_TRACE(QDF_MODULE_ID_DP,
  2046. QDF_TRACE_LEVEL_DEBUG,
  2047. FL("pkt send failed"));
  2048. qdf_nbuf_free(nbuf_copy);
  2049. } else {
  2050. if (peer_id != DP_INVALID_PEER)
  2051. DP_STATS_INC_PKT(peer,
  2052. tx.nawds_mcast,
  2053. 1, qdf_nbuf_len(nbuf));
  2054. }
  2055. }
  2056. }
  2057. }
  2058. if (vdev->nawds_enabled) {
  2059. peer_id = DP_INVALID_PEER;
  2060. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2061. 1, qdf_nbuf_len(nbuf));
  2062. nbuf = dp_tx_send_msdu_single(vdev,
  2063. nbuf,
  2064. &msdu_info,
  2065. peer_id, NULL);
  2066. if (nbuf) {
  2067. QDF_TRACE(QDF_MODULE_ID_DP,
  2068. QDF_TRACE_LEVEL_DEBUG,
  2069. FL("pkt send failed"));
  2070. qdf_nbuf_free(nbuf);
  2071. }
  2072. } else
  2073. qdf_nbuf_free(nbuf);
  2074. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2075. }
  2076. /**
  2077. * dp_tx_inspect_handler() - Tx Inspect Handler
  2078. * @tx_desc: software descriptor head pointer
  2079. * @status : Tx completion status from HTT descriptor
  2080. *
  2081. * Handles Tx frames sent back to Host for inspection
  2082. * (ProxyARP)
  2083. *
  2084. * Return: none
  2085. */
  2086. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2087. {
  2088. struct dp_soc *soc;
  2089. struct dp_pdev *pdev = tx_desc->pdev;
  2090. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2091. "%s Tx inspect path",
  2092. __func__);
  2093. qdf_assert(pdev);
  2094. soc = pdev->soc;
  2095. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2096. qdf_nbuf_len(tx_desc->nbuf));
  2097. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2098. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2099. }
  2100. #ifdef FEATURE_PERPKT_INFO
  2101. /**
  2102. * dp_get_completion_indication_for_stack() - send completion to stack
  2103. * @soc : dp_soc handle
  2104. * @pdev: dp_pdev handle
  2105. * @peer: dp peer handle
  2106. * @ts: transmit completion status structure
  2107. * @netbuf: Buffer pointer for free
  2108. *
  2109. * This function is used for indication whether buffer needs to be
  2110. * sent to stack for freeing or not
  2111. */
  2112. QDF_STATUS
  2113. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2114. struct dp_pdev *pdev,
  2115. struct dp_peer *peer,
  2116. struct hal_tx_completion_status *ts,
  2117. qdf_nbuf_t netbuf,
  2118. uint64_t time_latency)
  2119. {
  2120. struct tx_capture_hdr *ppdu_hdr;
  2121. uint16_t peer_id = ts->peer_id;
  2122. uint32_t ppdu_id = ts->ppdu_id;
  2123. uint8_t first_msdu = ts->first_msdu;
  2124. uint8_t last_msdu = ts->last_msdu;
  2125. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2126. !pdev->latency_capture_enable))
  2127. return QDF_STATUS_E_NOSUPPORT;
  2128. if (!peer) {
  2129. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2130. FL("Peer Invalid"));
  2131. return QDF_STATUS_E_INVAL;
  2132. }
  2133. if (pdev->mcopy_mode) {
  2134. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2135. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2136. return QDF_STATUS_E_INVAL;
  2137. }
  2138. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2139. pdev->m_copy_id.tx_peer_id = peer_id;
  2140. }
  2141. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2142. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2143. FL("No headroom"));
  2144. return QDF_STATUS_E_NOMEM;
  2145. }
  2146. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2147. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2148. QDF_MAC_ADDR_SIZE);
  2149. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2150. QDF_MAC_ADDR_SIZE);
  2151. ppdu_hdr->ppdu_id = ppdu_id;
  2152. ppdu_hdr->peer_id = peer_id;
  2153. ppdu_hdr->first_msdu = first_msdu;
  2154. ppdu_hdr->last_msdu = last_msdu;
  2155. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2156. ppdu_hdr->tsf = ts->tsf;
  2157. ppdu_hdr->time_latency = time_latency;
  2158. }
  2159. return QDF_STATUS_SUCCESS;
  2160. }
  2161. /**
  2162. * dp_send_completion_to_stack() - send completion to stack
  2163. * @soc : dp_soc handle
  2164. * @pdev: dp_pdev handle
  2165. * @peer_id: peer_id of the peer for which completion came
  2166. * @ppdu_id: ppdu_id
  2167. * @netbuf: Buffer pointer for free
  2168. *
  2169. * This function is used to send completion to stack
  2170. * to free buffer
  2171. */
  2172. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2173. uint16_t peer_id, uint32_t ppdu_id,
  2174. qdf_nbuf_t netbuf)
  2175. {
  2176. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2177. netbuf, peer_id,
  2178. WDI_NO_VAL, pdev->pdev_id);
  2179. }
  2180. #else
  2181. static QDF_STATUS
  2182. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2183. struct dp_pdev *pdev,
  2184. struct dp_peer *peer,
  2185. struct hal_tx_completion_status *ts,
  2186. qdf_nbuf_t netbuf,
  2187. uint64_t time_latency)
  2188. {
  2189. return QDF_STATUS_E_NOSUPPORT;
  2190. }
  2191. static void
  2192. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2193. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2194. {
  2195. }
  2196. #endif
  2197. /**
  2198. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2199. * @soc: Soc handle
  2200. * @desc: software Tx descriptor to be processed
  2201. *
  2202. * Return: none
  2203. */
  2204. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2205. struct dp_tx_desc_s *desc)
  2206. {
  2207. struct dp_vdev *vdev = desc->vdev;
  2208. qdf_nbuf_t nbuf = desc->nbuf;
  2209. /* nbuf already freed in vdev detach path */
  2210. if (!nbuf)
  2211. return;
  2212. /* If it is TDLS mgmt, don't unmap or free the frame */
  2213. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2214. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2215. /* 0 : MSDU buffer, 1 : MLE */
  2216. if (desc->msdu_ext_desc) {
  2217. /* TSO free */
  2218. if (hal_tx_ext_desc_get_tso_enable(
  2219. desc->msdu_ext_desc->vaddr)) {
  2220. /* unmap eash TSO seg before free the nbuf */
  2221. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2222. desc->tso_num_desc);
  2223. qdf_nbuf_free(nbuf);
  2224. return;
  2225. }
  2226. }
  2227. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2228. if (qdf_unlikely(!vdev)) {
  2229. qdf_nbuf_free(nbuf);
  2230. return;
  2231. }
  2232. if (qdf_likely(!vdev->mesh_vdev))
  2233. qdf_nbuf_free(nbuf);
  2234. else {
  2235. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2236. qdf_nbuf_free(nbuf);
  2237. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2238. } else
  2239. vdev->osif_tx_free_ext((nbuf));
  2240. }
  2241. }
  2242. #ifdef MESH_MODE_SUPPORT
  2243. /**
  2244. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2245. * in mesh meta header
  2246. * @tx_desc: software descriptor head pointer
  2247. * @ts: pointer to tx completion stats
  2248. * Return: none
  2249. */
  2250. static
  2251. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2252. struct hal_tx_completion_status *ts)
  2253. {
  2254. struct meta_hdr_s *mhdr;
  2255. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2256. if (!tx_desc->msdu_ext_desc) {
  2257. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2258. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2259. "netbuf %pK offset %d",
  2260. netbuf, tx_desc->pkt_offset);
  2261. return;
  2262. }
  2263. }
  2264. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2265. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2266. "netbuf %pK offset %lu", netbuf,
  2267. sizeof(struct meta_hdr_s));
  2268. return;
  2269. }
  2270. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2271. mhdr->rssi = ts->ack_frame_rssi;
  2272. mhdr->channel = tx_desc->pdev->operating_channel;
  2273. }
  2274. #else
  2275. static
  2276. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2277. struct hal_tx_completion_status *ts)
  2278. {
  2279. }
  2280. #endif
  2281. /**
  2282. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2283. * to pass in correct fields
  2284. *
  2285. * @vdev: pdev handle
  2286. * @tx_desc: tx descriptor
  2287. * @tid: tid value
  2288. * @ring_id: TCL or WBM ring number for transmit path
  2289. * Return: none
  2290. */
  2291. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2292. struct dp_tx_desc_s *tx_desc,
  2293. uint8_t tid, uint8_t ring_id)
  2294. {
  2295. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2296. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2297. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2298. return;
  2299. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2300. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2301. timestamp_hw_enqueue = tx_desc->timestamp;
  2302. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2303. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2304. timestamp_hw_enqueue);
  2305. interframe_delay = (uint32_t)(timestamp_ingress -
  2306. vdev->prev_tx_enq_tstamp);
  2307. /*
  2308. * Delay in software enqueue
  2309. */
  2310. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2311. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2312. /*
  2313. * Delay between packet enqueued to HW and Tx completion
  2314. */
  2315. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2316. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2317. /*
  2318. * Update interframe delay stats calculated at hardstart receive point.
  2319. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2320. * interframe delay will not be calculate correctly for 1st frame.
  2321. * On the other side, this will help in avoiding extra per packet check
  2322. * of !vdev->prev_tx_enq_tstamp.
  2323. */
  2324. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2325. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2326. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2327. }
  2328. /**
  2329. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2330. * per wbm ring
  2331. *
  2332. * @tx_desc: software descriptor head pointer
  2333. * @ts: Tx completion status
  2334. * @peer: peer handle
  2335. * @ring_id: ring number
  2336. *
  2337. * Return: None
  2338. */
  2339. static inline void
  2340. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2341. struct hal_tx_completion_status *ts,
  2342. struct dp_peer *peer, uint8_t ring_id)
  2343. {
  2344. struct dp_pdev *pdev = peer->vdev->pdev;
  2345. struct dp_soc *soc = NULL;
  2346. uint8_t mcs, pkt_type;
  2347. uint8_t tid = ts->tid;
  2348. uint32_t length;
  2349. struct cdp_tid_tx_stats *tid_stats;
  2350. if (!pdev)
  2351. return;
  2352. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2353. tid = CDP_MAX_DATA_TIDS - 1;
  2354. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2355. soc = pdev->soc;
  2356. mcs = ts->mcs;
  2357. pkt_type = ts->pkt_type;
  2358. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2359. dp_err("Release source is not from TQM");
  2360. return;
  2361. }
  2362. length = qdf_nbuf_len(tx_desc->nbuf);
  2363. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2364. if (qdf_unlikely(pdev->delay_stats_flag))
  2365. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2366. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2367. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2368. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2369. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2370. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2371. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2372. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2373. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2374. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2375. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2376. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2377. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2378. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2379. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2380. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2381. tid_stats->comp_fail_cnt++;
  2382. return;
  2383. }
  2384. tid_stats->success_cnt++;
  2385. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2386. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2387. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2388. /*
  2389. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2390. * Return from here if HTT PPDU events are enabled.
  2391. */
  2392. if (!(soc->process_tx_status))
  2393. return;
  2394. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2395. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2396. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2397. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2398. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2399. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2400. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2401. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2402. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2403. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2404. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2405. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2406. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2407. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2408. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2409. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2410. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2411. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2412. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2413. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2414. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2415. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2416. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2417. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2418. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2419. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2420. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2421. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2422. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2423. &peer->stats, ts->peer_id,
  2424. UPDATE_PEER_STATS, pdev->pdev_id);
  2425. #endif
  2426. }
  2427. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2428. /**
  2429. * dp_tx_flow_pool_lock() - take flow pool lock
  2430. * @soc: core txrx main context
  2431. * @tx_desc: tx desc
  2432. *
  2433. * Return: None
  2434. */
  2435. static inline
  2436. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2437. struct dp_tx_desc_s *tx_desc)
  2438. {
  2439. struct dp_tx_desc_pool_s *pool;
  2440. uint8_t desc_pool_id;
  2441. desc_pool_id = tx_desc->pool_id;
  2442. pool = &soc->tx_desc[desc_pool_id];
  2443. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2444. }
  2445. /**
  2446. * dp_tx_flow_pool_unlock() - release flow pool lock
  2447. * @soc: core txrx main context
  2448. * @tx_desc: tx desc
  2449. *
  2450. * Return: None
  2451. */
  2452. static inline
  2453. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2454. struct dp_tx_desc_s *tx_desc)
  2455. {
  2456. struct dp_tx_desc_pool_s *pool;
  2457. uint8_t desc_pool_id;
  2458. desc_pool_id = tx_desc->pool_id;
  2459. pool = &soc->tx_desc[desc_pool_id];
  2460. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2461. }
  2462. #else
  2463. static inline
  2464. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2465. {
  2466. }
  2467. static inline
  2468. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2469. {
  2470. }
  2471. #endif
  2472. /**
  2473. * dp_tx_notify_completion() - Notify tx completion for this desc
  2474. * @soc: core txrx main context
  2475. * @tx_desc: tx desc
  2476. * @netbuf: buffer
  2477. *
  2478. * Return: none
  2479. */
  2480. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2481. struct dp_tx_desc_s *tx_desc,
  2482. qdf_nbuf_t netbuf)
  2483. {
  2484. void *osif_dev;
  2485. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2486. qdf_assert(tx_desc);
  2487. dp_tx_flow_pool_lock(soc, tx_desc);
  2488. if (!tx_desc->vdev ||
  2489. !tx_desc->vdev->osif_vdev) {
  2490. dp_tx_flow_pool_unlock(soc, tx_desc);
  2491. return;
  2492. }
  2493. osif_dev = tx_desc->vdev->osif_vdev;
  2494. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2495. dp_tx_flow_pool_unlock(soc, tx_desc);
  2496. if (tx_compl_cbk)
  2497. tx_compl_cbk(netbuf, osif_dev);
  2498. }
  2499. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2500. * @pdev: pdev handle
  2501. * @tid: tid value
  2502. * @txdesc_ts: timestamp from txdesc
  2503. * @ppdu_id: ppdu id
  2504. *
  2505. * Return: none
  2506. */
  2507. #ifdef FEATURE_PERPKT_INFO
  2508. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2509. struct dp_peer *peer,
  2510. uint8_t tid,
  2511. uint64_t txdesc_ts,
  2512. uint32_t ppdu_id)
  2513. {
  2514. uint64_t delta_ms;
  2515. struct cdp_tx_sojourn_stats *sojourn_stats;
  2516. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2517. return;
  2518. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2519. tid >= CDP_DATA_TID_MAX))
  2520. return;
  2521. if (qdf_unlikely(!pdev->sojourn_buf))
  2522. return;
  2523. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2524. qdf_nbuf_data(pdev->sojourn_buf);
  2525. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2526. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2527. txdesc_ts;
  2528. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2529. delta_ms);
  2530. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2531. sojourn_stats->num_msdus[tid] = 1;
  2532. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2533. peer->avg_sojourn_msdu[tid].internal;
  2534. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2535. pdev->sojourn_buf, HTT_INVALID_PEER,
  2536. WDI_NO_VAL, pdev->pdev_id);
  2537. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2538. sojourn_stats->num_msdus[tid] = 0;
  2539. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2540. }
  2541. #else
  2542. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2543. uint8_t tid,
  2544. uint64_t txdesc_ts,
  2545. uint32_t ppdu_id)
  2546. {
  2547. }
  2548. #endif
  2549. /**
  2550. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2551. * @soc: DP Soc handle
  2552. * @tx_desc: software Tx descriptor
  2553. * @ts : Tx completion status from HAL/HTT descriptor
  2554. *
  2555. * Return: none
  2556. */
  2557. static inline void
  2558. dp_tx_comp_process_desc(struct dp_soc *soc,
  2559. struct dp_tx_desc_s *desc,
  2560. struct hal_tx_completion_status *ts,
  2561. struct dp_peer *peer)
  2562. {
  2563. uint64_t time_latency = 0;
  2564. /*
  2565. * m_copy/tx_capture modes are not supported for
  2566. * scatter gather packets
  2567. */
  2568. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2569. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2570. desc->timestamp);
  2571. }
  2572. if (!(desc->msdu_ext_desc)) {
  2573. if (QDF_STATUS_SUCCESS ==
  2574. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2575. return;
  2576. }
  2577. if (QDF_STATUS_SUCCESS ==
  2578. dp_get_completion_indication_for_stack(soc,
  2579. desc->pdev,
  2580. peer, ts,
  2581. desc->nbuf,
  2582. time_latency)) {
  2583. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2584. QDF_DMA_TO_DEVICE);
  2585. dp_send_completion_to_stack(soc,
  2586. desc->pdev,
  2587. ts->peer_id,
  2588. ts->ppdu_id,
  2589. desc->nbuf);
  2590. return;
  2591. }
  2592. }
  2593. dp_tx_comp_free_buf(soc, desc);
  2594. }
  2595. /**
  2596. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2597. * @tx_desc: software descriptor head pointer
  2598. * @ts: Tx completion status
  2599. * @peer: peer handle
  2600. * @ring_id: ring number
  2601. *
  2602. * Return: none
  2603. */
  2604. static inline
  2605. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2606. struct hal_tx_completion_status *ts,
  2607. struct dp_peer *peer, uint8_t ring_id)
  2608. {
  2609. uint32_t length;
  2610. qdf_ether_header_t *eh;
  2611. struct dp_soc *soc = NULL;
  2612. struct dp_vdev *vdev = tx_desc->vdev;
  2613. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2614. if (!vdev || !nbuf) {
  2615. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2616. "invalid tx descriptor. vdev or nbuf NULL");
  2617. goto out;
  2618. }
  2619. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2620. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2621. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2622. QDF_TRACE_DEFAULT_PDEV_ID,
  2623. qdf_nbuf_data_addr(nbuf),
  2624. sizeof(qdf_nbuf_data(nbuf)),
  2625. tx_desc->id,
  2626. ts->status));
  2627. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2628. "-------------------- \n"
  2629. "Tx Completion Stats: \n"
  2630. "-------------------- \n"
  2631. "ack_frame_rssi = %d \n"
  2632. "first_msdu = %d \n"
  2633. "last_msdu = %d \n"
  2634. "msdu_part_of_amsdu = %d \n"
  2635. "rate_stats valid = %d \n"
  2636. "bw = %d \n"
  2637. "pkt_type = %d \n"
  2638. "stbc = %d \n"
  2639. "ldpc = %d \n"
  2640. "sgi = %d \n"
  2641. "mcs = %d \n"
  2642. "ofdma = %d \n"
  2643. "tones_in_ru = %d \n"
  2644. "tsf = %d \n"
  2645. "ppdu_id = %d \n"
  2646. "transmit_cnt = %d \n"
  2647. "tid = %d \n"
  2648. "peer_id = %d\n",
  2649. ts->ack_frame_rssi, ts->first_msdu,
  2650. ts->last_msdu, ts->msdu_part_of_amsdu,
  2651. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2652. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2653. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2654. ts->transmit_cnt, ts->tid, ts->peer_id);
  2655. soc = vdev->pdev->soc;
  2656. /* Update SoC level stats */
  2657. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2658. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2659. /* Update per-packet stats for mesh mode */
  2660. if (qdf_unlikely(vdev->mesh_vdev) &&
  2661. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2662. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2663. length = qdf_nbuf_len(nbuf);
  2664. /* Update peer level stats */
  2665. if (!peer) {
  2666. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2667. "peer is null or deletion in progress");
  2668. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2669. goto out;
  2670. }
  2671. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2672. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2673. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2674. if ((peer->vdev->tx_encap_type ==
  2675. htt_cmn_pkt_type_ethernet) &&
  2676. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2677. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2678. }
  2679. }
  2680. } else {
  2681. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2682. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2683. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2684. }
  2685. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2686. #ifdef QCA_SUPPORT_RDK_STATS
  2687. if (soc->wlanstats_enabled)
  2688. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2689. tx_desc->timestamp,
  2690. ts->ppdu_id);
  2691. #endif
  2692. out:
  2693. return;
  2694. }
  2695. /**
  2696. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2697. * @soc: core txrx main context
  2698. * @comp_head: software descriptor head pointer
  2699. * @ring_id: ring number
  2700. *
  2701. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2702. * and release the software descriptors after processing is complete
  2703. *
  2704. * Return: none
  2705. */
  2706. static void
  2707. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2708. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2709. {
  2710. struct dp_tx_desc_s *desc;
  2711. struct dp_tx_desc_s *next;
  2712. struct hal_tx_completion_status ts = {0};
  2713. struct dp_peer *peer;
  2714. qdf_nbuf_t netbuf;
  2715. desc = comp_head;
  2716. while (desc) {
  2717. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2718. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2719. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2720. netbuf = desc->nbuf;
  2721. /* check tx complete notification */
  2722. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2723. dp_tx_notify_completion(soc, desc, netbuf);
  2724. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2725. if (peer)
  2726. dp_peer_unref_del_find_by_id(peer);
  2727. next = desc->next;
  2728. dp_tx_desc_release(desc, desc->pool_id);
  2729. desc = next;
  2730. }
  2731. }
  2732. /**
  2733. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2734. * @tx_desc: software descriptor head pointer
  2735. * @status : Tx completion status from HTT descriptor
  2736. * @ring_id: ring number
  2737. *
  2738. * This function will process HTT Tx indication messages from Target
  2739. *
  2740. * Return: none
  2741. */
  2742. static
  2743. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2744. uint8_t ring_id)
  2745. {
  2746. uint8_t tx_status;
  2747. struct dp_pdev *pdev;
  2748. struct dp_vdev *vdev;
  2749. struct dp_soc *soc;
  2750. struct hal_tx_completion_status ts = {0};
  2751. uint32_t *htt_desc = (uint32_t *)status;
  2752. struct dp_peer *peer;
  2753. struct cdp_tid_tx_stats *tid_stats = NULL;
  2754. struct htt_soc *htt_handle;
  2755. qdf_assert(tx_desc->pdev);
  2756. pdev = tx_desc->pdev;
  2757. vdev = tx_desc->vdev;
  2758. soc = pdev->soc;
  2759. if (!vdev)
  2760. return;
  2761. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2762. htt_handle = (struct htt_soc *)soc->htt_handle;
  2763. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  2764. switch (tx_status) {
  2765. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2766. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2767. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2768. {
  2769. uint8_t tid;
  2770. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2771. ts.peer_id =
  2772. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2773. htt_desc[2]);
  2774. ts.tid =
  2775. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2776. htt_desc[2]);
  2777. } else {
  2778. ts.peer_id = HTT_INVALID_PEER;
  2779. ts.tid = HTT_INVALID_TID;
  2780. }
  2781. ts.ppdu_id =
  2782. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2783. htt_desc[1]);
  2784. ts.ack_frame_rssi =
  2785. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2786. htt_desc[1]);
  2787. ts.first_msdu = 1;
  2788. ts.last_msdu = 1;
  2789. tid = ts.tid;
  2790. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2791. tid = CDP_MAX_DATA_TIDS - 1;
  2792. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2793. if (qdf_unlikely(pdev->delay_stats_flag))
  2794. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2795. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2796. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2797. tid_stats->comp_fail_cnt++;
  2798. } else {
  2799. tid_stats->success_cnt++;
  2800. }
  2801. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2802. if (qdf_likely(peer))
  2803. dp_peer_unref_del_find_by_id(peer);
  2804. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2805. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2806. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2807. break;
  2808. }
  2809. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2810. {
  2811. dp_tx_reinject_handler(tx_desc, status);
  2812. break;
  2813. }
  2814. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2815. {
  2816. dp_tx_inspect_handler(tx_desc, status);
  2817. break;
  2818. }
  2819. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2820. {
  2821. dp_tx_mec_handler(vdev, status);
  2822. break;
  2823. }
  2824. default:
  2825. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2826. "%s Invalid HTT tx_status %d\n",
  2827. __func__, tx_status);
  2828. break;
  2829. }
  2830. }
  2831. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2832. static inline
  2833. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2834. {
  2835. bool limit_hit = false;
  2836. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2837. limit_hit =
  2838. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2839. if (limit_hit)
  2840. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2841. return limit_hit;
  2842. }
  2843. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2844. {
  2845. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2846. }
  2847. #else
  2848. static inline
  2849. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2850. {
  2851. return false;
  2852. }
  2853. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2854. {
  2855. return false;
  2856. }
  2857. #endif
  2858. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2859. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  2860. uint32_t quota)
  2861. {
  2862. void *tx_comp_hal_desc;
  2863. uint8_t buffer_src;
  2864. uint8_t pool_id;
  2865. uint32_t tx_desc_id;
  2866. struct dp_tx_desc_s *tx_desc = NULL;
  2867. struct dp_tx_desc_s *head_desc = NULL;
  2868. struct dp_tx_desc_s *tail_desc = NULL;
  2869. uint32_t num_processed = 0;
  2870. uint32_t count = 0;
  2871. bool force_break = false;
  2872. DP_HIST_INIT();
  2873. more_data:
  2874. /* Re-initialize local variables to be re-used */
  2875. head_desc = NULL;
  2876. tail_desc = NULL;
  2877. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  2878. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2879. "%s %d : HAL RING Access Failed -- %pK",
  2880. __func__, __LINE__, hal_ring_hdl);
  2881. return 0;
  2882. }
  2883. /* Find head descriptor from completion ring */
  2884. while (qdf_likely(tx_comp_hal_desc =
  2885. hal_srng_dst_get_next(soc->hal_soc, hal_ring_hdl))) {
  2886. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2887. /* If this buffer was not released by TQM or FW, then it is not
  2888. * Tx completion indication, assert */
  2889. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2890. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2891. QDF_TRACE(QDF_MODULE_ID_DP,
  2892. QDF_TRACE_LEVEL_FATAL,
  2893. "Tx comp release_src != TQM | FW but from %d",
  2894. buffer_src);
  2895. hal_dump_comp_desc(tx_comp_hal_desc);
  2896. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2897. qdf_assert_always(0);
  2898. }
  2899. /* Get descriptor id */
  2900. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2901. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2902. DP_TX_DESC_ID_POOL_OS;
  2903. /* Find Tx descriptor */
  2904. tx_desc = dp_tx_desc_find(soc, pool_id,
  2905. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2906. DP_TX_DESC_ID_PAGE_OS,
  2907. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2908. DP_TX_DESC_ID_OFFSET_OS);
  2909. /*
  2910. * If the descriptor is already freed in vdev_detach,
  2911. * continue to next descriptor
  2912. */
  2913. if (!tx_desc->vdev && !tx_desc->flags) {
  2914. QDF_TRACE(QDF_MODULE_ID_DP,
  2915. QDF_TRACE_LEVEL_INFO,
  2916. "Descriptor freed in vdev_detach %d",
  2917. tx_desc_id);
  2918. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2919. count++;
  2920. continue;
  2921. }
  2922. /*
  2923. * If the release source is FW, process the HTT status
  2924. */
  2925. if (qdf_unlikely(buffer_src ==
  2926. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2927. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2928. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2929. htt_tx_status);
  2930. dp_tx_process_htt_completion(tx_desc,
  2931. htt_tx_status, ring_id);
  2932. } else {
  2933. /* Pool id is not matching. Error */
  2934. if (tx_desc->pool_id != pool_id) {
  2935. QDF_TRACE(QDF_MODULE_ID_DP,
  2936. QDF_TRACE_LEVEL_FATAL,
  2937. "Tx Comp pool id %d not matched %d",
  2938. pool_id, tx_desc->pool_id);
  2939. qdf_assert_always(0);
  2940. }
  2941. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2942. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2943. QDF_TRACE(QDF_MODULE_ID_DP,
  2944. QDF_TRACE_LEVEL_FATAL,
  2945. "Txdesc invalid, flgs = %x,id = %d",
  2946. tx_desc->flags, tx_desc_id);
  2947. qdf_assert_always(0);
  2948. }
  2949. /* First ring descriptor on the cycle */
  2950. if (!head_desc) {
  2951. head_desc = tx_desc;
  2952. tail_desc = tx_desc;
  2953. }
  2954. tail_desc->next = tx_desc;
  2955. tx_desc->next = NULL;
  2956. tail_desc = tx_desc;
  2957. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  2958. /* Collect hw completion contents */
  2959. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2960. &tx_desc->comp, 1);
  2961. }
  2962. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2963. /*
  2964. * Processed packet count is more than given quota
  2965. * stop to processing
  2966. */
  2967. if (num_processed >= quota) {
  2968. force_break = true;
  2969. break;
  2970. }
  2971. count++;
  2972. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  2973. break;
  2974. }
  2975. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  2976. /* Process the reaped descriptors */
  2977. if (head_desc)
  2978. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  2979. if (dp_tx_comp_enable_eol_data_check(soc)) {
  2980. if (!force_break &&
  2981. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  2982. hal_ring_hdl)) {
  2983. DP_STATS_INC(soc, tx.hp_oos2, 1);
  2984. if (!hif_exec_should_yield(soc->hif_handle,
  2985. int_ctx->dp_intr_id))
  2986. goto more_data;
  2987. }
  2988. }
  2989. DP_TX_HIST_STATS_PER_PDEV();
  2990. return num_processed;
  2991. }
  2992. #ifdef FEATURE_WLAN_TDLS
  2993. /**
  2994. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2995. *
  2996. * @data_vdev - which vdev should transmit the tx data frames
  2997. * @tx_spec - what non-standard handling to apply to the tx data frames
  2998. * @msdu_list - NULL-terminated list of tx MSDUs
  2999. *
  3000. * Return: NULL on success,
  3001. * nbuf when it fails to send
  3002. */
  3003. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  3004. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3005. {
  3006. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3007. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3008. vdev->is_tdls_frame = true;
  3009. return dp_tx_send(vdev_handle, msdu_list);
  3010. }
  3011. #endif
  3012. /**
  3013. * dp_tx_vdev_attach() - attach vdev to dp tx
  3014. * @vdev: virtual device instance
  3015. *
  3016. * Return: QDF_STATUS_SUCCESS: success
  3017. * QDF_STATUS_E_RESOURCES: Error return
  3018. */
  3019. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3020. {
  3021. /*
  3022. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3023. */
  3024. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3025. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3026. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3027. vdev->vdev_id);
  3028. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3029. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3030. /*
  3031. * Set HTT Extension Valid bit to 0 by default
  3032. */
  3033. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3034. dp_tx_vdev_update_search_flags(vdev);
  3035. return QDF_STATUS_SUCCESS;
  3036. }
  3037. #ifndef FEATURE_WDS
  3038. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3039. {
  3040. return false;
  3041. }
  3042. #endif
  3043. /**
  3044. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3045. * @vdev: virtual device instance
  3046. *
  3047. * Return: void
  3048. *
  3049. */
  3050. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3051. {
  3052. struct dp_soc *soc = vdev->pdev->soc;
  3053. /*
  3054. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3055. * for TDLS link
  3056. *
  3057. * Enable AddrY (SA based search) only for non-WDS STA and
  3058. * ProxySTA VAP (in HKv1) modes.
  3059. *
  3060. * In all other VAP modes, only DA based search should be
  3061. * enabled
  3062. */
  3063. if (vdev->opmode == wlan_op_mode_sta &&
  3064. vdev->tdls_link_connected)
  3065. vdev->hal_desc_addr_search_flags =
  3066. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3067. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3068. !dp_tx_da_search_override(vdev))
  3069. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3070. else
  3071. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3072. /* Set search type only when peer map v2 messaging is enabled
  3073. * as we will have the search index (AST hash) only when v2 is
  3074. * enabled
  3075. */
  3076. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3077. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3078. else
  3079. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3080. }
  3081. static inline bool
  3082. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3083. struct dp_vdev *vdev,
  3084. struct dp_tx_desc_s *tx_desc)
  3085. {
  3086. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3087. return false;
  3088. /*
  3089. * if vdev is given, then only check whether desc
  3090. * vdev match. if vdev is NULL, then check whether
  3091. * desc pdev match.
  3092. */
  3093. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3094. }
  3095. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3096. /**
  3097. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3098. *
  3099. * @soc: Handle to DP SoC structure
  3100. * @tx_desc: pointer of one TX desc
  3101. * @desc_pool_id: TX Desc pool id
  3102. */
  3103. static inline void
  3104. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3105. uint8_t desc_pool_id)
  3106. {
  3107. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3108. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3109. tx_desc->vdev = NULL;
  3110. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3111. }
  3112. /**
  3113. * dp_tx_desc_flush() - release resources associated
  3114. * to TX Desc
  3115. *
  3116. * @dp_pdev: Handle to DP pdev structure
  3117. * @vdev: virtual device instance
  3118. * NULL: no specific Vdev is required and check all allcated TX desc
  3119. * on this pdev.
  3120. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3121. *
  3122. * @force_free:
  3123. * true: flush the TX desc.
  3124. * false: only reset the Vdev in each allocated TX desc
  3125. * that associated to current Vdev.
  3126. *
  3127. * This function will go through the TX desc pool to flush
  3128. * the outstanding TX data or reset Vdev to NULL in associated TX
  3129. * Desc.
  3130. */
  3131. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3132. struct dp_vdev *vdev,
  3133. bool force_free)
  3134. {
  3135. uint8_t i;
  3136. uint32_t j;
  3137. uint32_t num_desc, page_id, offset;
  3138. uint16_t num_desc_per_page;
  3139. struct dp_soc *soc = pdev->soc;
  3140. struct dp_tx_desc_s *tx_desc = NULL;
  3141. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3142. if (!vdev && !force_free) {
  3143. dp_err("Reset TX desc vdev, Vdev param is required!");
  3144. return;
  3145. }
  3146. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3147. tx_desc_pool = &soc->tx_desc[i];
  3148. if (!(tx_desc_pool->pool_size) ||
  3149. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3150. !(tx_desc_pool->desc_pages.cacheable_pages))
  3151. continue;
  3152. num_desc = tx_desc_pool->pool_size;
  3153. num_desc_per_page =
  3154. tx_desc_pool->desc_pages.num_element_per_page;
  3155. for (j = 0; j < num_desc; j++) {
  3156. page_id = j / num_desc_per_page;
  3157. offset = j % num_desc_per_page;
  3158. if (qdf_unlikely(!(tx_desc_pool->
  3159. desc_pages.cacheable_pages)))
  3160. break;
  3161. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3162. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3163. /*
  3164. * Free TX desc if force free is
  3165. * required, otherwise only reset vdev
  3166. * in this TX desc.
  3167. */
  3168. if (force_free) {
  3169. dp_tx_comp_free_buf(soc, tx_desc);
  3170. dp_tx_desc_release(tx_desc, i);
  3171. } else {
  3172. dp_tx_desc_reset_vdev(soc, tx_desc,
  3173. i);
  3174. }
  3175. }
  3176. }
  3177. }
  3178. }
  3179. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3180. static inline void
  3181. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3182. uint8_t desc_pool_id)
  3183. {
  3184. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3185. tx_desc->vdev = NULL;
  3186. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3187. }
  3188. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3189. struct dp_vdev *vdev,
  3190. bool force_free)
  3191. {
  3192. uint8_t i, num_pool;
  3193. uint32_t j;
  3194. uint32_t num_desc, page_id, offset;
  3195. uint16_t num_desc_per_page;
  3196. struct dp_soc *soc = pdev->soc;
  3197. struct dp_tx_desc_s *tx_desc = NULL;
  3198. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3199. if (!vdev && !force_free) {
  3200. dp_err("Reset TX desc vdev, Vdev param is required!");
  3201. return;
  3202. }
  3203. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3204. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3205. for (i = 0; i < num_pool; i++) {
  3206. tx_desc_pool = &soc->tx_desc[i];
  3207. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3208. continue;
  3209. num_desc_per_page =
  3210. tx_desc_pool->desc_pages.num_element_per_page;
  3211. for (j = 0; j < num_desc; j++) {
  3212. page_id = j / num_desc_per_page;
  3213. offset = j % num_desc_per_page;
  3214. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3215. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3216. if (force_free) {
  3217. dp_tx_comp_free_buf(soc, tx_desc);
  3218. dp_tx_desc_release(tx_desc, i);
  3219. } else {
  3220. dp_tx_desc_reset_vdev(soc, tx_desc,
  3221. i);
  3222. }
  3223. }
  3224. }
  3225. }
  3226. }
  3227. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3228. /**
  3229. * dp_tx_vdev_detach() - detach vdev from dp tx
  3230. * @vdev: virtual device instance
  3231. *
  3232. * Return: QDF_STATUS_SUCCESS: success
  3233. * QDF_STATUS_E_RESOURCES: Error return
  3234. */
  3235. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3236. {
  3237. struct dp_pdev *pdev = vdev->pdev;
  3238. /* Reset TX desc associated to this Vdev as NULL */
  3239. dp_tx_desc_flush(pdev, vdev, false);
  3240. return QDF_STATUS_SUCCESS;
  3241. }
  3242. /**
  3243. * dp_tx_pdev_attach() - attach pdev to dp tx
  3244. * @pdev: physical device instance
  3245. *
  3246. * Return: QDF_STATUS_SUCCESS: success
  3247. * QDF_STATUS_E_RESOURCES: Error return
  3248. */
  3249. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3250. {
  3251. struct dp_soc *soc = pdev->soc;
  3252. /* Initialize Flow control counters */
  3253. qdf_atomic_init(&pdev->num_tx_exception);
  3254. qdf_atomic_init(&pdev->num_tx_outstanding);
  3255. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3256. /* Initialize descriptors in TCL Ring */
  3257. hal_tx_init_data_ring(soc->hal_soc,
  3258. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3259. }
  3260. return QDF_STATUS_SUCCESS;
  3261. }
  3262. /**
  3263. * dp_tx_pdev_detach() - detach pdev from dp tx
  3264. * @pdev: physical device instance
  3265. *
  3266. * Return: QDF_STATUS_SUCCESS: success
  3267. * QDF_STATUS_E_RESOURCES: Error return
  3268. */
  3269. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3270. {
  3271. /* flush TX outstanding data per pdev */
  3272. dp_tx_desc_flush(pdev, NULL, true);
  3273. dp_tx_me_exit(pdev);
  3274. return QDF_STATUS_SUCCESS;
  3275. }
  3276. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3277. /* Pools will be allocated dynamically */
  3278. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3279. int num_desc)
  3280. {
  3281. uint8_t i;
  3282. for (i = 0; i < num_pool; i++) {
  3283. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3284. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3285. }
  3286. return 0;
  3287. }
  3288. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3289. {
  3290. uint8_t i;
  3291. for (i = 0; i < num_pool; i++)
  3292. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3293. }
  3294. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3295. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3296. int num_desc)
  3297. {
  3298. uint8_t i;
  3299. /* Allocate software Tx descriptor pools */
  3300. for (i = 0; i < num_pool; i++) {
  3301. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3302. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3303. "%s Tx Desc Pool alloc %d failed %pK",
  3304. __func__, i, soc);
  3305. return ENOMEM;
  3306. }
  3307. }
  3308. return 0;
  3309. }
  3310. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3311. {
  3312. uint8_t i;
  3313. for (i = 0; i < num_pool; i++) {
  3314. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3315. if (dp_tx_desc_pool_free(soc, i)) {
  3316. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3317. "%s Tx Desc Pool Free failed", __func__);
  3318. }
  3319. }
  3320. }
  3321. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3322. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3323. /**
  3324. * dp_tso_attach_wifi3() - TSO attach handler
  3325. * @txrx_soc: Opaque Dp handle
  3326. *
  3327. * Reserve TSO descriptor buffers
  3328. *
  3329. * Return: QDF_STATUS_E_FAILURE on failure or
  3330. * QDF_STATUS_SUCCESS on success
  3331. */
  3332. static
  3333. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3334. {
  3335. return dp_tso_soc_attach(txrx_soc);
  3336. }
  3337. /**
  3338. * dp_tso_detach_wifi3() - TSO Detach handler
  3339. * @txrx_soc: Opaque Dp handle
  3340. *
  3341. * Deallocate TSO descriptor buffers
  3342. *
  3343. * Return: QDF_STATUS_E_FAILURE on failure or
  3344. * QDF_STATUS_SUCCESS on success
  3345. */
  3346. static
  3347. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3348. {
  3349. return dp_tso_soc_detach(txrx_soc);
  3350. }
  3351. #else
  3352. static
  3353. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3354. {
  3355. return QDF_STATUS_SUCCESS;
  3356. }
  3357. static
  3358. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3359. {
  3360. return QDF_STATUS_SUCCESS;
  3361. }
  3362. #endif
  3363. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3364. {
  3365. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3366. uint8_t i;
  3367. uint8_t num_pool;
  3368. uint32_t num_desc;
  3369. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3370. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3371. for (i = 0; i < num_pool; i++)
  3372. dp_tx_tso_desc_pool_free(soc, i);
  3373. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3374. __func__, num_pool, num_desc);
  3375. for (i = 0; i < num_pool; i++)
  3376. dp_tx_tso_num_seg_pool_free(soc, i);
  3377. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3378. __func__, num_pool, num_desc);
  3379. return QDF_STATUS_SUCCESS;
  3380. }
  3381. /**
  3382. * dp_tso_attach() - TSO attach handler
  3383. * @txrx_soc: Opaque Dp handle
  3384. *
  3385. * Reserve TSO descriptor buffers
  3386. *
  3387. * Return: QDF_STATUS_E_FAILURE on failure or
  3388. * QDF_STATUS_SUCCESS on success
  3389. */
  3390. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3391. {
  3392. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3393. uint8_t i;
  3394. uint8_t num_pool;
  3395. uint32_t num_desc;
  3396. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3397. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3398. for (i = 0; i < num_pool; i++) {
  3399. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3400. dp_err("TSO Desc Pool alloc %d failed %pK",
  3401. i, soc);
  3402. return QDF_STATUS_E_FAILURE;
  3403. }
  3404. }
  3405. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3406. __func__, num_pool, num_desc);
  3407. for (i = 0; i < num_pool; i++) {
  3408. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3409. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3410. i, soc);
  3411. return QDF_STATUS_E_FAILURE;
  3412. }
  3413. }
  3414. return QDF_STATUS_SUCCESS;
  3415. }
  3416. /**
  3417. * dp_tx_soc_detach() - detach soc from dp tx
  3418. * @soc: core txrx main context
  3419. *
  3420. * This function will detach dp tx into main device context
  3421. * will free dp tx resource and initialize resources
  3422. *
  3423. * Return: QDF_STATUS_SUCCESS: success
  3424. * QDF_STATUS_E_RESOURCES: Error return
  3425. */
  3426. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3427. {
  3428. uint8_t num_pool;
  3429. uint16_t num_desc;
  3430. uint16_t num_ext_desc;
  3431. uint8_t i;
  3432. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3433. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3434. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3435. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3436. dp_tx_flow_control_deinit(soc);
  3437. dp_tx_delete_static_pools(soc, num_pool);
  3438. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3439. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3440. __func__, num_pool, num_desc);
  3441. for (i = 0; i < num_pool; i++) {
  3442. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3443. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3444. "%s Tx Ext Desc Pool Free failed",
  3445. __func__);
  3446. return QDF_STATUS_E_RESOURCES;
  3447. }
  3448. }
  3449. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3450. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3451. __func__, num_pool, num_ext_desc);
  3452. status = dp_tso_detach_wifi3(soc);
  3453. if (status != QDF_STATUS_SUCCESS)
  3454. return status;
  3455. return QDF_STATUS_SUCCESS;
  3456. }
  3457. /**
  3458. * dp_tx_soc_attach() - attach soc to dp tx
  3459. * @soc: core txrx main context
  3460. *
  3461. * This function will attach dp tx into main device context
  3462. * will allocate dp tx resource and initialize resources
  3463. *
  3464. * Return: QDF_STATUS_SUCCESS: success
  3465. * QDF_STATUS_E_RESOURCES: Error return
  3466. */
  3467. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3468. {
  3469. uint8_t i;
  3470. uint8_t num_pool;
  3471. uint32_t num_desc;
  3472. uint32_t num_ext_desc;
  3473. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3474. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3475. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3476. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3477. if (num_pool > MAX_TXDESC_POOLS)
  3478. goto fail;
  3479. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3480. goto fail;
  3481. dp_tx_flow_control_init(soc);
  3482. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3483. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3484. __func__, num_pool, num_desc);
  3485. /* Allocate extension tx descriptor pools */
  3486. for (i = 0; i < num_pool; i++) {
  3487. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3488. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3489. "MSDU Ext Desc Pool alloc %d failed %pK",
  3490. i, soc);
  3491. goto fail;
  3492. }
  3493. }
  3494. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3495. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3496. __func__, num_pool, num_ext_desc);
  3497. status = dp_tso_attach_wifi3((void *)soc);
  3498. if (status != QDF_STATUS_SUCCESS)
  3499. goto fail;
  3500. /* Initialize descriptors in TCL Rings */
  3501. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3502. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3503. hal_tx_init_data_ring(soc->hal_soc,
  3504. soc->tcl_data_ring[i].hal_srng);
  3505. }
  3506. }
  3507. /*
  3508. * todo - Add a runtime config option to enable this.
  3509. */
  3510. /*
  3511. * Due to multiple issues on NPR EMU, enable it selectively
  3512. * only for NPR EMU, should be removed, once NPR platforms
  3513. * are stable.
  3514. */
  3515. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3516. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3517. "%s HAL Tx init Success", __func__);
  3518. return QDF_STATUS_SUCCESS;
  3519. fail:
  3520. /* Detach will take care of freeing only allocated resources */
  3521. dp_tx_soc_detach(soc);
  3522. return QDF_STATUS_E_RESOURCES;
  3523. }