wcd939x.c 163 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <linux/stringify.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include <soc/soundwire.h>
  18. #include <linux/regmap.h>
  19. #include <sound/soc.h>
  20. #include <sound/soc-dapm.h>
  21. #include <asoc/wcdcal-hwdep.h>
  22. #include <asoc/msm-cdc-pinctrl.h>
  23. #include <asoc/msm-cdc-supply.h>
  24. #include <asoc/wcd-mbhc-v2-api.h>
  25. #include <bindings/audio-codec-port-types.h>
  26. #include <linux/qti-regmap-debugfs.h>
  27. #include "wcd939x-registers.h"
  28. #include "wcd939x.h"
  29. #include "internal.h"
  30. #include "asoc/bolero-slave-internal.h"
  31. #include "wcd939x-reg-masks.h"
  32. #include "wcd939x-reg-shifts.h"
  33. #if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
  34. #include <linux/soc/qcom/wcd939x-i2c.h>
  35. #endif
  36. #define NUM_SWRS_DT_PARAMS 5
  37. #define WCD939X_VARIANT_ENTRY_SIZE 32
  38. #define WCD939X_VERSION_ENTRY_SIZE 32
  39. #define ADC_MODE_VAL_HIFI 0x01
  40. #define ADC_MODE_VAL_LO_HIF 0x02
  41. #define ADC_MODE_VAL_NORMAL 0x03
  42. #define ADC_MODE_VAL_LP 0x05
  43. #define ADC_MODE_VAL_ULP1 0x09
  44. #define ADC_MODE_VAL_ULP2 0x0B
  45. #define HPH_IMPEDANCE_2VPK_MODE_OHMS 260
  46. #define XTALK_L_CH_NUM 0
  47. #define XTALK_R_CH_NUM 1
  48. #define NUM_ATTEMPTS 5
  49. #define COMP_MAX_COEFF 25
  50. #define HPH_MODE_MAX 4
  51. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  52. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  53. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  54. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  55. #define WCD939X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  56. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  57. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  58. SNDRV_PCM_RATE_384000)
  59. /* Fractional Rates */
  60. #define WCD939X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  61. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  62. #define WCD939X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  63. SNDRV_PCM_FMTBIT_S24_LE |\
  64. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  65. #define REG_FIELD_VALUE(register_name, field_name, value) \
  66. WCD939X_##register_name, FIELD_MASK(register_name, field_name), \
  67. value << FIELD_SHIFT(register_name, field_name)
  68. #define WCD939X_COMP_OFFSET \
  69. (WCD939X_R_BASE - WCD939X_COMPANDER_HPHL_BASE)
  70. #define WCD939X_XTALK_OFFSET \
  71. (WCD939X_HPHR_RX_PATH_SEC0 - WCD939X_HPHL_RX_PATH_SEC0)
  72. enum {
  73. CODEC_TX = 0,
  74. CODEC_RX,
  75. };
  76. enum {
  77. WCD_ADC1 = 0,
  78. WCD_ADC2,
  79. WCD_ADC3,
  80. WCD_ADC4,
  81. ALLOW_BUCK_DISABLE,
  82. HPH_COMP_DELAY,
  83. HPH_PA_DELAY,
  84. AMIC2_BCS_ENABLE,
  85. WCD_SUPPLIES_LPM_MODE,
  86. WCD_ADC1_MODE,
  87. WCD_ADC2_MODE,
  88. WCD_ADC3_MODE,
  89. WCD_ADC4_MODE,
  90. };
  91. enum {
  92. ADC_MODE_INVALID = 0,
  93. ADC_MODE_HIFI,
  94. ADC_MODE_LO_HIF,
  95. ADC_MODE_NORMAL,
  96. ADC_MODE_LP,
  97. ADC_MODE_ULP1,
  98. ADC_MODE_ULP2,
  99. };
  100. enum {
  101. SUPPLY_LEVEL_2VPK,
  102. REGULATOR_MODE_2VPK,
  103. SET_HPH_GAIN_2VPK,
  104. };
  105. static u8 tx_mode_bit[] = {
  106. [ADC_MODE_INVALID] = 0x00,
  107. [ADC_MODE_HIFI] = 0x01,
  108. [ADC_MODE_LO_HIF] = 0x02,
  109. [ADC_MODE_NORMAL] = 0x04,
  110. [ADC_MODE_LP] = 0x08,
  111. [ADC_MODE_ULP1] = 0x10,
  112. [ADC_MODE_ULP2] = 0x20,
  113. };
  114. extern const u8 wcd939x_reg_access[WCD939X_NUM_REGISTERS];
  115. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(hph_analog_gain, 600, -3000);
  116. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  117. /* Will be set by reading the registers during bind()*/
  118. static int wcd939x_version = WCD939X_VERSION_2_0;
  119. static int wcd939x_handle_post_irq(void *data);
  120. static int wcd939x_reset(struct device *dev);
  121. static int wcd939x_reset_low(struct device *dev);
  122. static int wcd939x_get_adc_mode(int val);
  123. static void wcd939x_config_2Vpk_mode(struct snd_soc_component *component,
  124. struct wcd939x_priv *wcd939x, int mode_2vpk);
  125. static const struct regmap_irq wcd939x_irqs[WCD939X_NUM_IRQS] = {
  126. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  127. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  128. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  129. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  130. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_SW_DET, 0, 0x10),
  131. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_OCP_INT, 0, 0x20),
  132. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_CNP_INT, 0, 0x40),
  133. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_OCP_INT, 0, 0x80),
  134. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_CNP_INT, 1, 0x01),
  135. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_CNP_INT, 1, 0x02),
  136. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_SCD_INT, 1, 0x04),
  137. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  138. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  139. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_PDM_WD_INT, 1, 0x80),
  140. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  141. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  142. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  143. };
  144. static struct regmap_irq_chip wcd939x_regmap_irq_chip = {
  145. .name = "wcd939x",
  146. .irqs = wcd939x_irqs,
  147. .num_irqs = ARRAY_SIZE(wcd939x_irqs),
  148. .num_regs = 3,
  149. .status_base = WCD939X_INTR_STATUS_0,
  150. .mask_base = WCD939X_INTR_MASK_0,
  151. .type_base = WCD939X_INTR_LEVEL_0,
  152. .ack_base = WCD939X_INTR_CLEAR_0,
  153. .use_ack = 1,
  154. .runtime_pm = false,
  155. .handle_post_irq = wcd939x_handle_post_irq,
  156. .irq_drv_data = NULL,
  157. };
  158. static bool wcd939x_readable_register(struct device *dev, unsigned int reg)
  159. {
  160. if (reg <= WCD939X_BASE + 1)
  161. return 0;
  162. if (reg >= WCD939X_FLYBACK_NEW_CTRL_2 && reg <= WCD939X_FLYBACK_NEW_CTRL_4) {
  163. if (wcd939x_version == WCD939X_VERSION_1_0)
  164. return 0;
  165. }
  166. return wcd939x_reg_access[WCD939X_REG(reg)] & RD_REG;
  167. }
  168. static int wcd939x_handle_post_irq(void *data)
  169. {
  170. struct wcd939x_priv *wcd939x = data;
  171. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  172. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_0, &sts1);
  173. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_1, &sts2);
  174. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_2, &sts3);
  175. wcd939x->tx_swr_dev->slave_irq_pending =
  176. ((sts1 || sts2 || sts3) ? true : false);
  177. return IRQ_HANDLED;
  178. }
  179. static int wcd939x_hph_compander_get(struct snd_kcontrol *kcontrol,
  180. struct snd_ctl_elem_value *ucontrol)
  181. {
  182. struct snd_soc_component *component =
  183. snd_soc_kcontrol_component(kcontrol);
  184. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  185. int compander = ((struct soc_multi_mixer_control *)
  186. kcontrol->private_value)->shift;
  187. ucontrol->value.integer.value[0] = wcd939x->compander_enabled[compander];
  188. return 0;
  189. }
  190. static int wcd939x_hph_compander_put(struct snd_kcontrol *kcontrol,
  191. struct snd_ctl_elem_value *ucontrol)
  192. {
  193. struct snd_soc_component *component =
  194. snd_soc_kcontrol_component(kcontrol);
  195. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  196. int compander = ((struct soc_multi_mixer_control *)
  197. kcontrol->private_value)->shift;
  198. int value = ucontrol->value.integer.value[0];
  199. if (value < WCD939X_HPH_MAX && value >= 0)
  200. wcd939x->compander_enabled[compander] = value;
  201. else {
  202. dev_err(component->dev, "%s: Invalid comp value = %d\n", __func__, value);
  203. return -EINVAL;
  204. }
  205. dev_dbg(component->dev, "%s: Compander %d value %d\n",
  206. __func__, wcd939x->compander_enabled[compander], value);
  207. return 0;
  208. }
  209. static int wcd939x_hph_xtalk_put(struct snd_kcontrol *kcontrol,
  210. struct snd_ctl_elem_value *ucontrol)
  211. {
  212. struct snd_soc_component *component =
  213. snd_soc_kcontrol_component(kcontrol);
  214. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  215. int xtalk = ((struct soc_multi_mixer_control *)
  216. kcontrol->private_value)->shift;
  217. int value = ucontrol->value.integer.value[0];
  218. if (value < WCD939X_HPH_MAX && value >= 0)
  219. wcd939x->xtalk_enabled[xtalk] = value;
  220. else {
  221. dev_err(component->dev, "%s: Invalid xtalk value = %d\n", __func__, value);
  222. return -EINVAL;
  223. }
  224. dev_dbg(component->dev, "%s: xtalk %d value %d\n",
  225. __func__, wcd939x->xtalk_enabled[xtalk], value);
  226. return 0;
  227. }
  228. static int wcd939x_hph_xtalk_get(struct snd_kcontrol *kcontrol,
  229. struct snd_ctl_elem_value *ucontrol)
  230. {
  231. struct snd_soc_component *component =
  232. snd_soc_kcontrol_component(kcontrol);
  233. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  234. int xtalk = ((struct soc_multi_mixer_control *)
  235. kcontrol->private_value)->shift;
  236. ucontrol->value.integer.value[0] = wcd939x->xtalk_enabled[xtalk];
  237. return 0;
  238. }
  239. static int wcd939x_hph_pcm_enable_put(struct snd_kcontrol *kcontrol,
  240. struct snd_ctl_elem_value *ucontrol)
  241. {
  242. struct snd_soc_component *component =
  243. snd_soc_kcontrol_component(kcontrol);
  244. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  245. wcd939x->hph_pcm_enabled = ucontrol->value.integer.value[0];
  246. dev_dbg(component->dev, "%s: pcm enabled %d \n",
  247. __func__, wcd939x->hph_pcm_enabled);
  248. return 0;
  249. }
  250. static int wcd939x_hph_pcm_enable_get(struct snd_kcontrol *kcontrol,
  251. struct snd_ctl_elem_value *ucontrol)
  252. {
  253. struct snd_soc_component *component =
  254. snd_soc_kcontrol_component(kcontrol);
  255. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  256. ucontrol->value.integer.value[0] = wcd939x->hph_pcm_enabled;
  257. return 0;
  258. }
  259. static int wcd939x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  260. {
  261. int ret = 0;
  262. int bank = 0;
  263. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  264. if (ret)
  265. return -EINVAL;
  266. return ((bank & 0x40) ? 1: 0);
  267. }
  268. static int wcd939x_get_clk_rate(int mode)
  269. {
  270. int rate;
  271. switch (mode) {
  272. case ADC_MODE_ULP2:
  273. rate = SWR_CLK_RATE_0P6MHZ;
  274. break;
  275. case ADC_MODE_ULP1:
  276. rate = SWR_CLK_RATE_1P2MHZ;
  277. break;
  278. case ADC_MODE_LP:
  279. rate = SWR_CLK_RATE_4P8MHZ;
  280. break;
  281. case ADC_MODE_NORMAL:
  282. case ADC_MODE_LO_HIF:
  283. case ADC_MODE_HIFI:
  284. case ADC_MODE_INVALID:
  285. default:
  286. rate = SWR_CLK_RATE_9P6MHZ;
  287. break;
  288. }
  289. return rate;
  290. }
  291. static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component,
  292. int rate, int bank)
  293. {
  294. u8 mask = (bank ? 0xF0 : 0x0F);
  295. u8 val = 0;
  296. switch (rate) {
  297. case SWR_CLK_RATE_0P6MHZ:
  298. val = (bank ? 0x60 : 0x06);
  299. break;
  300. case SWR_CLK_RATE_1P2MHZ:
  301. val = (bank ? 0x50 : 0x05);
  302. break;
  303. case SWR_CLK_RATE_2P4MHZ:
  304. val = (bank ? 0x30 : 0x03);
  305. break;
  306. case SWR_CLK_RATE_4P8MHZ:
  307. val = (bank ? 0x10 : 0x01);
  308. break;
  309. case SWR_CLK_RATE_9P6MHZ:
  310. default:
  311. val = 0x00;
  312. break;
  313. }
  314. snd_soc_component_update_bits(component,
  315. WCD939X_SWR_TX_CLK_RATE,
  316. mask, val);
  317. return 0;
  318. }
  319. static int wcd939x_init_reg(struct snd_soc_component *component)
  320. {
  321. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  322. snd_soc_component_update_bits(component,
  323. REG_FIELD_VALUE(BIAS, ANALOG_BIAS_EN, 0x01));
  324. snd_soc_component_update_bits(component,
  325. REG_FIELD_VALUE(BIAS, PRECHRG_EN, 0x01));
  326. /* 10 msec delay as per HW requirement */
  327. usleep_range(10000, 10010);
  328. snd_soc_component_update_bits(component,
  329. REG_FIELD_VALUE(BIAS, PRECHRG_EN, 0x00));
  330. snd_soc_component_update_bits(component,
  331. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x15));
  332. snd_soc_component_update_bits(component,
  333. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x15));
  334. snd_soc_component_update_bits(component,
  335. REG_FIELD_VALUE(CDC_DMIC_CTL, CLK_SCALE_EN, 0x01));
  336. snd_soc_component_update_bits(component,
  337. REG_FIELD_VALUE(TXFE_ICTRL_STG2CASC_ULP, ICTRL_SCBIAS_ULP0P6M, 0x1));
  338. snd_soc_component_update_bits(component,
  339. REG_FIELD_VALUE(TXFE_ICTRL_STG2CASC_ULP, ICTRL_STG2CASC_ULP, 0x4));
  340. snd_soc_component_update_bits(component,
  341. REG_FIELD_VALUE(TXFE_ICTRL_STG2MAIN_ULP, ICTRL_STG2MAIN_ULP, 0x08));
  342. snd_soc_component_update_bits(component,
  343. REG_FIELD_VALUE(TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  344. snd_soc_component_update_bits(component,
  345. REG_FIELD_VALUE(MICB2_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  346. snd_soc_component_update_bits(component,
  347. REG_FIELD_VALUE(MICB3_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  348. snd_soc_component_update_bits(component,
  349. REG_FIELD_VALUE(MICB4_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  350. snd_soc_component_update_bits(component,
  351. REG_FIELD_VALUE(TEST_BLK_EN2, TXFE2_MBHC_CLKRST_EN, 0x00));
  352. if (of_find_property(component->card->dev->of_node, "qcom,wcd-disable-legacy-surge", NULL)) {
  353. snd_soc_component_update_bits(component,
  354. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHL, 0x00));
  355. snd_soc_component_update_bits(component,
  356. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHR, 0x00));
  357. }
  358. else {
  359. snd_soc_component_update_bits(component,
  360. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHL, 0x01));
  361. snd_soc_component_update_bits(component,
  362. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHR, 0x01));
  363. }
  364. snd_soc_component_update_bits(component,
  365. REG_FIELD_VALUE(HPH_OCP_CTL, OCP_FSM_EN, 0x01));
  366. snd_soc_component_update_bits(component,
  367. REG_FIELD_VALUE(HPH_OCP_CTL, SCD_OP_EN, 0x01));
  368. if (wcd939x->version != WCD939X_VERSION_2_0)
  369. snd_soc_component_write(component, WCD939X_CFG0, 0x05);
  370. return 0;
  371. }
  372. static int wcd939x_set_port_params(struct snd_soc_component *component,
  373. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  374. u8 *ch_mask, u32 *ch_rate,
  375. u8 *port_type, u8 path)
  376. {
  377. int i, j;
  378. u8 num_ports = 0;
  379. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  380. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  381. switch (path) {
  382. case CODEC_RX:
  383. map = &wcd939x->rx_port_mapping;
  384. num_ports = wcd939x->num_rx_ports;
  385. break;
  386. case CODEC_TX:
  387. map = &wcd939x->tx_port_mapping;
  388. num_ports = wcd939x->num_tx_ports;
  389. break;
  390. default:
  391. dev_err_ratelimited(component->dev, "%s Invalid path selected %u\n",
  392. __func__, path);
  393. return -EINVAL;
  394. }
  395. for (i = 0; i <= num_ports; i++) {
  396. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  397. if ((*map)[i][j].slave_port_type == slv_prt_type)
  398. goto found;
  399. }
  400. }
  401. found:
  402. if (i > num_ports || j == MAX_CH_PER_PORT) {
  403. dev_err_ratelimited(component->dev, "%s Failed to find slave port for type %u\n",
  404. __func__, slv_prt_type);
  405. return -EINVAL;
  406. }
  407. *port_id = i;
  408. *num_ch = (*map)[i][j].num_ch;
  409. *ch_mask = (*map)[i][j].ch_mask;
  410. *ch_rate = (*map)[i][j].ch_rate;
  411. *port_type = (*map)[i][j].master_port_type;
  412. return 0;
  413. }
  414. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  415. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  416. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  417. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  418. static int wcd939x_parse_port_params(struct device *dev,
  419. char *prop, u8 path)
  420. {
  421. u32 *dt_array, map_size, max_uc;
  422. int ret = 0;
  423. u32 cnt = 0;
  424. u32 i, j;
  425. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  426. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  427. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  428. switch (path) {
  429. case CODEC_TX:
  430. map = &wcd939x->tx_port_params;
  431. map_uc = &wcd939x->swr_tx_port_params;
  432. break;
  433. default:
  434. ret = -EINVAL;
  435. goto err_port_map;
  436. }
  437. if (!of_find_property(dev->of_node, prop,
  438. &map_size)) {
  439. dev_err(dev, "missing port mapping prop %s\n", prop);
  440. ret = -EINVAL;
  441. goto err_port_map;
  442. }
  443. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  444. if (max_uc != SWR_UC_MAX) {
  445. dev_err(dev, "%s: port params not provided for all usecases\n",
  446. __func__);
  447. ret = -EINVAL;
  448. goto err_port_map;
  449. }
  450. dt_array = kzalloc(map_size, GFP_KERNEL);
  451. if (!dt_array) {
  452. ret = -ENOMEM;
  453. goto err_alloc;
  454. }
  455. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  456. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  457. if (ret) {
  458. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  459. __func__, prop);
  460. goto err_pdata_fail;
  461. }
  462. for (i = 0; i < max_uc; i++) {
  463. for (j = 0; j < SWR_NUM_PORTS; j++) {
  464. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  465. (*map)[i][j].offset1 = dt_array[cnt];
  466. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  467. }
  468. (*map_uc)[i].pp = &(*map)[i][0];
  469. }
  470. kfree(dt_array);
  471. return 0;
  472. err_pdata_fail:
  473. kfree(dt_array);
  474. err_alloc:
  475. err_port_map:
  476. return ret;
  477. }
  478. static int wcd939x_parse_port_mapping(struct device *dev,
  479. char *prop, u8 path)
  480. {
  481. u32 *dt_array, map_size, map_length;
  482. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  483. u32 slave_port_type, master_port_type;
  484. u32 i, ch_iter = 0;
  485. int ret = 0;
  486. u8 *num_ports = NULL;
  487. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  488. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  489. switch (path) {
  490. case CODEC_RX:
  491. map = &wcd939x->rx_port_mapping;
  492. num_ports = &wcd939x->num_rx_ports;
  493. break;
  494. case CODEC_TX:
  495. map = &wcd939x->tx_port_mapping;
  496. num_ports = &wcd939x->num_tx_ports;
  497. break;
  498. default:
  499. dev_err(dev, "%s Invalid path selected %u\n",
  500. __func__, path);
  501. return -EINVAL;
  502. }
  503. if (!of_find_property(dev->of_node, prop,
  504. &map_size)) {
  505. dev_err(dev, "missing port mapping prop %s\n", prop);
  506. ret = -EINVAL;
  507. goto err_port_map;
  508. }
  509. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  510. dt_array = kzalloc(map_size, GFP_KERNEL);
  511. if (!dt_array) {
  512. ret = -ENOMEM;
  513. goto err_alloc;
  514. }
  515. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  516. NUM_SWRS_DT_PARAMS * map_length);
  517. if (ret) {
  518. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  519. __func__, prop);
  520. goto err_pdata_fail;
  521. }
  522. for (i = 0; i < map_length; i++) {
  523. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  524. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  525. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  526. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  527. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  528. if (port_num != old_port_num)
  529. ch_iter = 0;
  530. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  531. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  532. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  533. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  534. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  535. old_port_num = port_num;
  536. }
  537. *num_ports = port_num;
  538. kfree(dt_array);
  539. return 0;
  540. err_pdata_fail:
  541. kfree(dt_array);
  542. err_alloc:
  543. err_port_map:
  544. return ret;
  545. }
  546. static int wcd939x_tx_connect_port(struct snd_soc_component *component,
  547. u8 slv_port_type, int clk_rate,
  548. u8 enable)
  549. {
  550. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  551. u8 port_id, num_ch, ch_mask;
  552. u8 ch_type = 0;
  553. u32 ch_rate;
  554. int slave_ch_idx;
  555. u8 num_port = 1;
  556. int ret = 0;
  557. ret = wcd939x_set_port_params(component, slv_port_type, &port_id,
  558. &num_ch, &ch_mask, &ch_rate,
  559. &ch_type, CODEC_TX);
  560. if (ret)
  561. return ret;
  562. if (clk_rate)
  563. ch_rate = clk_rate;
  564. slave_ch_idx = wcd939x_slave_get_slave_ch_val(slv_port_type);
  565. if (slave_ch_idx != -EINVAL)
  566. ch_type = wcd939x->tx_master_ch_map[slave_ch_idx];
  567. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  568. __func__, slave_ch_idx, ch_type);
  569. if (enable)
  570. ret = swr_connect_port(wcd939x->tx_swr_dev, &port_id,
  571. num_port, &ch_mask, &ch_rate,
  572. &num_ch, &ch_type);
  573. else
  574. ret = swr_disconnect_port(wcd939x->tx_swr_dev, &port_id,
  575. num_port, &ch_mask, &ch_type);
  576. return ret;
  577. }
  578. static int wcd939x_rx_connect_port(struct snd_soc_component *component,
  579. u8 slv_port_type, u8 enable)
  580. {
  581. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  582. u8 port_id, num_ch, ch_mask, port_type;
  583. u32 ch_rate;
  584. u8 num_port = 1;
  585. int ret = 0;
  586. ret = wcd939x_set_port_params(component, slv_port_type, &port_id,
  587. &num_ch, &ch_mask, &ch_rate,
  588. &port_type, CODEC_RX);
  589. if (ret)
  590. return ret;
  591. if (enable)
  592. ret = swr_connect_port(wcd939x->rx_swr_dev, &port_id,
  593. num_port, &ch_mask, &ch_rate,
  594. &num_ch, &port_type);
  595. else
  596. ret = swr_disconnect_port(wcd939x->rx_swr_dev, &port_id,
  597. num_port, &ch_mask, &port_type);
  598. return ret;
  599. }
  600. static int wcd939x_rx_clk_enable(struct snd_soc_component *component, int rx_num)
  601. {
  602. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  603. dev_dbg(component->dev, "%s rx_clk_cnt: %d\n", __func__, wcd939x->rx_clk_cnt);
  604. if (wcd939x->rx_clk_cnt == 0) {
  605. snd_soc_component_update_bits(component,
  606. REG_FIELD_VALUE(RX_SUPPLIES, RX_BIAS_ENABLE, 0x01));
  607. /*Analog path clock controls*/
  608. snd_soc_component_update_bits(component,
  609. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_CLK_EN, 0x01));
  610. snd_soc_component_update_bits(component,
  611. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV2_CLK_EN, 0x01));
  612. snd_soc_component_update_bits(component,
  613. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV4_CLK_EN, 0x01));
  614. /*Digital path clock controls*/
  615. snd_soc_component_update_bits(component,
  616. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x01));
  617. snd_soc_component_update_bits(component,
  618. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD1_CLK_EN, 0x01));
  619. snd_soc_component_update_bits(component,
  620. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD2_CLK_EN, 0x01));
  621. }
  622. wcd939x->rx_clk_cnt++;
  623. return 0;
  624. }
  625. static int wcd939x_rx_clk_disable(struct snd_soc_component *component)
  626. {
  627. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  628. dev_dbg(component->dev, "%s rx_clk_cnt: %d\n", __func__, wcd939x->rx_clk_cnt);
  629. if (wcd939x->rx_clk_cnt == 0)
  630. return 0;
  631. wcd939x->rx_clk_cnt--;
  632. if (wcd939x->rx_clk_cnt == 0) {
  633. snd_soc_component_update_bits(component,
  634. REG_FIELD_VALUE(RX_SUPPLIES, VNEG_EN, 0x00));
  635. snd_soc_component_update_bits(component,
  636. REG_FIELD_VALUE(RX_SUPPLIES, VPOS_EN, 0x00));
  637. snd_soc_component_update_bits(component,
  638. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD2_CLK_EN, 0x00));
  639. snd_soc_component_update_bits(component,
  640. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD1_CLK_EN, 0x00));
  641. snd_soc_component_update_bits(component,
  642. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x00));
  643. snd_soc_component_update_bits(component,
  644. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV4_CLK_EN, 0x00));
  645. snd_soc_component_update_bits(component,
  646. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV2_CLK_EN, 0x00));
  647. snd_soc_component_update_bits(component,
  648. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_CLK_EN, 0x00));
  649. snd_soc_component_update_bits(component,
  650. REG_FIELD_VALUE(RX_SUPPLIES, RX_BIAS_ENABLE, 0x00));
  651. }
  652. return 0;
  653. }
  654. /*
  655. * wcd939x_soc_get_mbhc: get wcd939x_mbhc handle of corresponding component
  656. * @component: handle to snd_soc_component *
  657. *
  658. * return wcd939x_mbhc handle or error code in case of failure
  659. */
  660. struct wcd939x_mbhc *wcd939x_soc_get_mbhc(struct snd_soc_component *component)
  661. {
  662. struct wcd939x_priv *wcd939x;
  663. if (!component) {
  664. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  665. return NULL;
  666. }
  667. wcd939x = snd_soc_component_get_drvdata(component);
  668. if (!wcd939x) {
  669. pr_err_ratelimited("%s: wcd939x is NULL\n", __func__);
  670. return NULL;
  671. }
  672. return wcd939x->mbhc;
  673. }
  674. EXPORT_SYMBOL(wcd939x_soc_get_mbhc);
  675. static int wcd939x_config_power_mode(struct snd_soc_component *component,
  676. int event, int index, int mode)
  677. {
  678. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  679. switch (event) {
  680. case SND_SOC_DAPM_PRE_PMU:
  681. if (mode == CLS_H_ULP) {
  682. snd_soc_component_update_bits(component,
  683. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFP_IOUT_CTL, 0x1));
  684. snd_soc_component_update_bits(component,
  685. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFN_IOUT_CTL, 0x1));
  686. if (wcd939x->compander_enabled[index]) {
  687. if (index == WCD939X_HPHL) {
  688. snd_soc_component_update_bits(component,
  689. REG_FIELD_VALUE(CTL12, ZONE3_RMS, 0x21));
  690. snd_soc_component_update_bits(component,
  691. REG_FIELD_VALUE(CTL13, ZONE4_RMS, 0x30));
  692. snd_soc_component_update_bits(component,
  693. REG_FIELD_VALUE(CTL14, ZONE5_RMS, 0x3F));
  694. snd_soc_component_update_bits(component,
  695. REG_FIELD_VALUE(CTL15, ZONE6_RMS, 0x48));
  696. snd_soc_component_update_bits(component,
  697. REG_FIELD_VALUE(CTL17, PATH_GAIN, 0x0C));
  698. } else if (index == WCD939X_HPHR) {
  699. snd_soc_component_update_bits(component,
  700. REG_FIELD_VALUE(R_CTL12, ZONE3_RMS, 0x21));
  701. snd_soc_component_update_bits(component,
  702. REG_FIELD_VALUE(R_CTL13, ZONE4_RMS, 0x30));
  703. snd_soc_component_update_bits(component,
  704. REG_FIELD_VALUE(R_CTL14, ZONE5_RMS, 0x3F));
  705. snd_soc_component_update_bits(component,
  706. REG_FIELD_VALUE(R_CTL15, ZONE6_RMS, 0x48));
  707. snd_soc_component_update_bits(component,
  708. REG_FIELD_VALUE(R_CTL17, PATH_GAIN, 0x0C));
  709. }
  710. }
  711. } else {
  712. if (wcd939x->compander_enabled[index]) {
  713. if (index == WCD939X_HPHL) {
  714. snd_soc_component_update_bits(component,
  715. REG_FIELD_VALUE(CTL12, ZONE3_RMS, 0x1E));
  716. snd_soc_component_update_bits(component,
  717. REG_FIELD_VALUE(CTL13, ZONE4_RMS, 0x2A));
  718. snd_soc_component_update_bits(component,
  719. REG_FIELD_VALUE(CTL14, ZONE5_RMS, 0x36));
  720. snd_soc_component_update_bits(component,
  721. REG_FIELD_VALUE(CTL15, ZONE6_RMS, 0x3C));
  722. snd_soc_component_update_bits(component,
  723. REG_FIELD_VALUE(CTL17, PATH_GAIN, 0x00));
  724. } else if (index == WCD939X_HPHR) {
  725. snd_soc_component_update_bits(component,
  726. REG_FIELD_VALUE(R_CTL12, ZONE3_RMS, 0x1E));
  727. snd_soc_component_update_bits(component,
  728. REG_FIELD_VALUE(R_CTL13, ZONE4_RMS, 0x2A));
  729. snd_soc_component_update_bits(component,
  730. REG_FIELD_VALUE(R_CTL14, ZONE5_RMS, 0x36));
  731. snd_soc_component_update_bits(component,
  732. REG_FIELD_VALUE(R_CTL15, ZONE6_RMS, 0x3C));
  733. snd_soc_component_update_bits(component,
  734. REG_FIELD_VALUE(R_CTL17, PATH_GAIN, 0x00));
  735. }
  736. }
  737. }
  738. break;
  739. case SND_SOC_DAPM_POST_PMD:
  740. if (mode == CLS_H_ULP) {
  741. snd_soc_component_update_bits(component,
  742. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFN_IOUT_CTL, 0x0));
  743. snd_soc_component_update_bits(component,
  744. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFP_IOUT_CTL, 0x0));
  745. }
  746. break;
  747. }
  748. return 0;
  749. }
  750. static int wcd939x_get_usbss_hph_power_mode(int hph_mode)
  751. {
  752. switch (hph_mode) {
  753. case CLS_H_HIFI:
  754. case CLS_H_LOHIFI:
  755. return 0x4;
  756. default:
  757. /* set default mode to ULP */
  758. return 0x2;
  759. }
  760. }
  761. static int wcd939x_enable_hph_pcm_index(struct snd_soc_component *component,
  762. int event, int hph)
  763. {
  764. struct wcd939x_priv *wcd939x = NULL;
  765. if (!component) {
  766. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  767. return -EINVAL;
  768. }
  769. wcd939x = snd_soc_component_get_drvdata(component);
  770. if (!wcd939x->hph_pcm_enabled)
  771. return 0;
  772. switch (event) {
  773. case SND_SOC_DAPM_POST_PMU:
  774. if (hph == WCD939X_HPHL) {
  775. if (wcd939x->rx_clk_config == RX_CLK_11P2896MHZ)
  776. snd_soc_component_update_bits(component,
  777. REG_FIELD_VALUE(HPHL_RX_PATH_CFG1,
  778. RX_DC_DROOP_COEFF_SEL, 0x2));
  779. else if (wcd939x->rx_clk_config == RX_CLK_9P6MHZ)
  780. snd_soc_component_update_bits(component,
  781. REG_FIELD_VALUE(HPHL_RX_PATH_CFG1,
  782. RX_DC_DROOP_COEFF_SEL, 0x3));
  783. snd_soc_component_update_bits(component,
  784. REG_FIELD_VALUE(HPHL_RX_PATH_CFG0,
  785. DLY_ZN_EN, 0x1));
  786. snd_soc_component_update_bits(component,
  787. REG_FIELD_VALUE(HPHL_RX_PATH_CFG0,
  788. INT_EN, 0x3));
  789. } else if (hph == WCD939X_HPHR) {
  790. if (wcd939x->rx_clk_config == RX_CLK_11P2896MHZ)
  791. snd_soc_component_update_bits(component,
  792. REG_FIELD_VALUE(HPHR_RX_PATH_CFG1,
  793. RX_DC_DROOP_COEFF_SEL, 0x2));
  794. else if (wcd939x->rx_clk_config == RX_CLK_9P6MHZ)
  795. snd_soc_component_update_bits(component,
  796. REG_FIELD_VALUE(HPHR_RX_PATH_CFG1,
  797. RX_DC_DROOP_COEFF_SEL, 0x3));
  798. snd_soc_component_update_bits(component,
  799. REG_FIELD_VALUE(HPHR_RX_PATH_CFG0,
  800. DLY_ZN_EN, 0x1));
  801. snd_soc_component_update_bits(component,
  802. REG_FIELD_VALUE(HPHR_RX_PATH_CFG0,
  803. INT_EN, 0x3));
  804. }
  805. break;
  806. case SND_SOC_DAPM_POST_PMD:
  807. break;
  808. }
  809. return 0;
  810. }
  811. static int wcd939x_config_compander(struct snd_soc_component *component,
  812. int event, int compander_indx)
  813. {
  814. u16 comp_ctl7_reg = 0, comp_ctl0_reg = 0;
  815. u16 comp_en_mask_val = 0, gain_source_sel = 0;
  816. struct wcd939x_priv *wcd939x;
  817. if (compander_indx >= WCD939X_HPH_MAX || compander_indx < 0) {
  818. pr_err_ratelimited("%s: Invalid compander value: %d\n",
  819. __func__, compander_indx);
  820. return -EINVAL;
  821. }
  822. if (!component) {
  823. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  824. return -EINVAL;
  825. }
  826. wcd939x = snd_soc_component_get_drvdata(component);
  827. if (!wcd939x->hph_pcm_enabled)
  828. return 0;
  829. dev_dbg(component->dev, "%s compander_index = %d\n", __func__, compander_indx);
  830. if (!wcd939x->compander_enabled[compander_indx]) {
  831. if (SND_SOC_DAPM_EVENT_ON(event))
  832. gain_source_sel = 0x01;
  833. else
  834. gain_source_sel = 0x00;
  835. if (compander_indx == WCD939X_HPHL) {
  836. snd_soc_component_update_bits(component,
  837. REG_FIELD_VALUE(L_EN, GAIN_SOURCE_SEL, gain_source_sel));
  838. } else if (compander_indx == WCD939X_HPHR) {
  839. snd_soc_component_update_bits(component,
  840. REG_FIELD_VALUE(R_EN, GAIN_SOURCE_SEL, gain_source_sel));
  841. }
  842. wcd939x_config_2Vpk_mode(component, wcd939x, SET_HPH_GAIN_2VPK);
  843. return 0;
  844. }
  845. if (compander_indx == WCD939X_HPHL)
  846. comp_en_mask_val = 1 << 1;
  847. else if (compander_indx == WCD939X_HPHR)
  848. comp_en_mask_val = 1 << 0;
  849. else
  850. return 0;
  851. comp_ctl0_reg = WCD939X_CTL0 + (compander_indx * WCD939X_COMP_OFFSET);
  852. comp_ctl7_reg = WCD939X_CTL7 + (compander_indx * WCD939X_COMP_OFFSET);
  853. if (SND_SOC_DAPM_EVENT_ON(event)) {
  854. snd_soc_component_update_bits(component,
  855. comp_ctl7_reg, 0x1E, 0x00);
  856. /* Enable compander clock*/
  857. snd_soc_component_update_bits(component,
  858. comp_ctl0_reg , 0x01, 0x01);
  859. /* 250us sleep required as per HW Sequence */
  860. usleep_range(250, 260);
  861. snd_soc_component_update_bits(component,
  862. comp_ctl0_reg, 0x02, 0x02);
  863. snd_soc_component_update_bits(component,
  864. comp_ctl0_reg, 0x02, 0x00);
  865. /* Enable compander*/
  866. snd_soc_component_update_bits(component,
  867. WCD939X_CDC_COMP_CTL_0, comp_en_mask_val, comp_en_mask_val);
  868. } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
  869. snd_soc_component_update_bits(component,
  870. WCD939X_CDC_COMP_CTL_0, comp_en_mask_val, 0x00);
  871. snd_soc_component_update_bits(component,
  872. comp_ctl0_reg , 0x01, 0x00);
  873. if (compander_indx == WCD939X_HPHL)
  874. snd_soc_component_update_bits(component,
  875. REG_FIELD_VALUE(L_EN, GAIN_SOURCE_SEL, 0x0));
  876. if (compander_indx == WCD939X_HPHR)
  877. snd_soc_component_update_bits(component,
  878. REG_FIELD_VALUE(R_EN, GAIN_SOURCE_SEL, 0x0));
  879. }
  880. return 0;
  881. }
  882. static int wcd939x_config_xtalk(struct snd_soc_component *component,
  883. int event, int xtalk_indx)
  884. {
  885. u16 xtalk_sec0 = 0, xtalk_sec1 = 0, xtalk_sec2 = 0, xtalk_sec3 = 0;
  886. struct wcd939x_priv *wcd939x = NULL;
  887. struct wcd939x_pdata *pdata = NULL;
  888. if (!component) {
  889. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  890. return -EINVAL;
  891. }
  892. wcd939x = snd_soc_component_get_drvdata(component);
  893. if (!wcd939x->xtalk_enabled[xtalk_indx])
  894. return 0;
  895. pdata = dev_get_platdata(wcd939x->dev);
  896. dev_dbg(component->dev, "%s xtalk_indx = %d event = %d\n",
  897. __func__, xtalk_indx, event);
  898. switch(event) {
  899. case SND_SOC_DAPM_PRE_PMU:
  900. xtalk_sec0 = WCD939X_HPHL_RX_PATH_SEC0 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  901. xtalk_sec1 = WCD939X_HPHL_RX_PATH_SEC1 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  902. xtalk_sec2 = WCD939X_HPHL_RX_PATH_SEC2 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  903. xtalk_sec3 = WCD939X_HPHL_RX_PATH_SEC3 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  904. /* Write scale and alpha based on channel */
  905. if (xtalk_indx == XTALK_L_CH_NUM) {
  906. snd_soc_component_update_bits(component, xtalk_sec1, 0xFF,
  907. pdata->usbcss_hs.alpha_l);
  908. snd_soc_component_update_bits(component, xtalk_sec0, 0x1F,
  909. pdata->usbcss_hs.scale_l);
  910. } else if (xtalk_indx == XTALK_R_CH_NUM) {
  911. snd_soc_component_update_bits(component, xtalk_sec1, 0xFF,
  912. pdata->usbcss_hs.alpha_r);
  913. snd_soc_component_update_bits(component, xtalk_sec0, 0x1F,
  914. pdata->usbcss_hs.scale_r);
  915. } else {
  916. snd_soc_component_update_bits(component, xtalk_sec1, 0xFF, MIN_XTALK_ALPHA);
  917. snd_soc_component_update_bits(component, xtalk_sec0, 0x1F, MAX_XTALK_SCALE);
  918. }
  919. dev_dbg(component->dev, "%s Scale = 0x%x, Alpha = 0x%x\n", __func__,
  920. snd_soc_component_read(component, xtalk_sec0),
  921. snd_soc_component_read(component, xtalk_sec1));
  922. snd_soc_component_update_bits(component, xtalk_sec3, 0xFF, 0x4F);
  923. snd_soc_component_update_bits(component, xtalk_sec2, 0x1F, 0x11);
  924. break;
  925. case SND_SOC_DAPM_POST_PMU:
  926. /* enable xtalk for L and R channels*/
  927. snd_soc_component_update_bits(component, WCD939X_RX_PATH_CFG2,
  928. 0x0F, 0x0F);
  929. break;
  930. case SND_SOC_DAPM_POST_PMD:
  931. /* Disable Xtalk for L and R channels*/
  932. snd_soc_component_update_bits(component, WCD939X_RX_PATH_CFG2,
  933. 0x00, 0x00);
  934. break;
  935. }
  936. return 0;
  937. }
  938. static int wcd939x_rx3_mux(struct snd_soc_dapm_widget *w,
  939. struct snd_kcontrol *kcontrol, int event)
  940. {
  941. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  942. dev_dbg(component->dev, "%s event: %d wshift: %d wname: %s\n",
  943. __func__, event, w->shift, w->name);
  944. switch (event) {
  945. case SND_SOC_DAPM_PRE_PMU:
  946. wcd939x_rx_clk_enable(component, w->shift);
  947. break;
  948. case SND_SOC_DAPM_POST_PMD:
  949. wcd939x_rx_clk_disable(component);
  950. break;
  951. }
  952. return 0;
  953. }
  954. static int wcd939x_rx_mux(struct snd_soc_dapm_widget *w,
  955. struct snd_kcontrol *kcontrol,
  956. int event)
  957. {
  958. int hph_mode = 0;
  959. struct wcd939x_priv *wcd939x = NULL;
  960. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  961. wcd939x = snd_soc_component_get_drvdata(component);
  962. hph_mode = wcd939x->hph_mode;
  963. dev_dbg(component->dev, "%s event: %d wshift: %d wname: %s\n",
  964. __func__, event, w->shift, w->name);
  965. switch (event) {
  966. case SND_SOC_DAPM_PRE_PMU:
  967. wcd939x_rx_clk_enable(component, w->shift);
  968. if (wcd939x->hph_pcm_enabled)
  969. wcd939x_config_power_mode(component, event, w->shift, hph_mode);
  970. wcd939x_config_compander(component, event, w->shift);
  971. wcd939x_config_xtalk(component, event, w->shift);
  972. break;
  973. case SND_SOC_DAPM_POST_PMU:
  974. wcd939x_config_xtalk(component, event, w->shift);
  975. /*TBD: need to revisit , for both L & R we are updating, but in QCRG only once*/
  976. if (wcd939x->hph_pcm_enabled) {
  977. if (hph_mode == CLS_H_HIFI || hph_mode == CLS_AB_HIFI)
  978. snd_soc_component_update_bits(component,
  979. REG_FIELD_VALUE(TOP_CFG0, HPH_DAC_RATE_SEL, 0x1));
  980. else
  981. snd_soc_component_update_bits(component,
  982. REG_FIELD_VALUE(TOP_CFG0, HPH_DAC_RATE_SEL, 0x0));
  983. }
  984. wcd939x_enable_hph_pcm_index(component, event, w->shift);
  985. break;
  986. case SND_SOC_DAPM_POST_PMD:
  987. wcd939x_config_xtalk(component, event, w->shift);
  988. wcd939x_config_compander(component, event, w->shift);
  989. if (wcd939x->hph_pcm_enabled)
  990. wcd939x_config_power_mode(component, event, w->shift, hph_mode);
  991. wcd939x_rx_clk_disable(component);
  992. break;
  993. }
  994. return 0;
  995. }
  996. static void wcd939x_config_2Vpk_mode(struct snd_soc_component *component,
  997. struct wcd939x_priv *wcd939x, int mode_2vpk)
  998. {
  999. uint32_t zl = 0, zr = 0;
  1000. int rc;
  1001. if (!wcd939x->in_2Vpk_mode)
  1002. return;
  1003. rc = wcd_mbhc_get_impedance(&wcd939x->mbhc->wcd_mbhc, &zl, &zr);
  1004. if (rc) {
  1005. dev_err_ratelimited(component->dev, "%s: Unable to get impedance for 2Vpk mode", __func__);
  1006. return;
  1007. }
  1008. switch (mode_2vpk) {
  1009. case SUPPLY_LEVEL_2VPK:
  1010. snd_soc_component_update_bits(component,
  1011. REG_FIELD_VALUE(PA_GAIN_CTL_L, RX_SUPPLY_LEVEL, 0x01));
  1012. if (zl < HPH_IMPEDANCE_2VPK_MODE_OHMS)
  1013. snd_soc_component_update_bits(component,
  1014. REG_FIELD_VALUE(PA_GAIN_CTL_L, EN_HPHPA_2VPK, 0x00));
  1015. else
  1016. snd_soc_component_update_bits(component,
  1017. REG_FIELD_VALUE(PA_GAIN_CTL_L, EN_HPHPA_2VPK, 0x01));
  1018. break;
  1019. case REGULATOR_MODE_2VPK:
  1020. if (zl >= HPH_IMPEDANCE_2VPK_MODE_OHMS) {
  1021. snd_soc_component_update_bits(component,
  1022. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1023. snd_soc_component_update_bits(component, WCD939X_FLYBACK_TEST_CTL,
  1024. 0x0F, 0x02);
  1025. } else {
  1026. snd_soc_component_update_bits(component, WCD939X_FLYBACK_TEST_CTL,
  1027. 0x0F, 0x0D);
  1028. }
  1029. break;
  1030. case SET_HPH_GAIN_2VPK:
  1031. if (zl >= HPH_IMPEDANCE_2VPK_MODE_OHMS) {
  1032. snd_soc_component_update_bits(component, WCD939X_PA_GAIN_CTL_L, 0x1F, 0x02);
  1033. snd_soc_component_update_bits(component, WCD939X_PA_GAIN_CTL_R, 0x1F, 0x02);
  1034. }
  1035. break;
  1036. }
  1037. }
  1038. static int wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  1039. struct snd_kcontrol *kcontrol,
  1040. int event)
  1041. {
  1042. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1043. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1044. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1045. w->name, event);
  1046. switch (event) {
  1047. case SND_SOC_DAPM_PRE_PMU:
  1048. if (!wcd939x->hph_pcm_enabled)
  1049. snd_soc_component_update_bits(component,
  1050. REG_FIELD_VALUE(RDAC_CLK_CTL1, OPAMP_CHOP_CLK_EN, 0x00));
  1051. wcd939x_config_2Vpk_mode(component, wcd939x, SUPPLY_LEVEL_2VPK);
  1052. snd_soc_component_update_bits(component,
  1053. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHL_RX_EN, 0x01));
  1054. break;
  1055. case SND_SOC_DAPM_POST_PMU:
  1056. snd_soc_component_update_bits(component,
  1057. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x1D));
  1058. if (!wcd939x->hph_pcm_enabled) {
  1059. if (wcd939x->comp1_enable) {
  1060. snd_soc_component_update_bits(component,
  1061. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x01));
  1062. /* 5msec compander delay as per HW requirement */
  1063. if (!wcd939x->comp2_enable ||
  1064. (snd_soc_component_read(component,
  1065. WCD939X_CDC_COMP_CTL_0) & 0x01))
  1066. usleep_range(5000, 5010);
  1067. snd_soc_component_update_bits(component,
  1068. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  1069. } else {
  1070. snd_soc_component_update_bits(component,
  1071. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x00));
  1072. snd_soc_component_update_bits(component,
  1073. REG_FIELD_VALUE(L_EN, GAIN_SOURCE_SEL, 0x01));
  1074. }
  1075. }
  1076. if (wcd939x->hph_pcm_enabled) {
  1077. snd_soc_component_update_bits(component,
  1078. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  1079. snd_soc_component_write(component, WCD939X_VNEG_CTRL_1, 0xEB);
  1080. if (wcd939x->hph_mode == CLS_H_LOHIFI)
  1081. snd_soc_component_write(component,
  1082. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x52);
  1083. else
  1084. snd_soc_component_write(component,
  1085. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x64);
  1086. }
  1087. break;
  1088. case SND_SOC_DAPM_POST_PMD:
  1089. snd_soc_component_update_bits(component,
  1090. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x01));
  1091. snd_soc_component_update_bits(component,
  1092. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHL_RX_EN, 0x00));
  1093. break;
  1094. }
  1095. return 0;
  1096. }
  1097. static int wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1098. struct snd_kcontrol *kcontrol,
  1099. int event)
  1100. {
  1101. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1102. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1103. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1104. w->name, event);
  1105. switch (event) {
  1106. case SND_SOC_DAPM_PRE_PMU:
  1107. if (!wcd939x->hph_pcm_enabled)
  1108. snd_soc_component_update_bits(component,
  1109. REG_FIELD_VALUE(RDAC_CLK_CTL1, OPAMP_CHOP_CLK_EN, 0x00));
  1110. wcd939x_config_2Vpk_mode(component, wcd939x, SUPPLY_LEVEL_2VPK);
  1111. snd_soc_component_update_bits(component,
  1112. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHR_RX_EN, 0x01));
  1113. break;
  1114. case SND_SOC_DAPM_POST_PMU:
  1115. snd_soc_component_update_bits(component,
  1116. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x1D));
  1117. if (!wcd939x->hph_pcm_enabled) {
  1118. if (wcd939x->comp1_enable) {
  1119. snd_soc_component_update_bits(component,
  1120. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHR_COMP_EN, 0x01));
  1121. /* 5msec compander delay as per HW requirement */
  1122. if (!wcd939x->comp2_enable ||
  1123. (snd_soc_component_read(component,
  1124. WCD939X_CDC_COMP_CTL_0) & 0x02))
  1125. usleep_range(5000, 5010);
  1126. snd_soc_component_update_bits(component,
  1127. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  1128. } else {
  1129. snd_soc_component_update_bits(component,
  1130. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHR_COMP_EN, 0x00));
  1131. snd_soc_component_update_bits(component,
  1132. REG_FIELD_VALUE(R_EN, GAIN_SOURCE_SEL, 0x01));
  1133. }
  1134. }
  1135. if (wcd939x->hph_pcm_enabled) {
  1136. snd_soc_component_write(component, WCD939X_VNEG_CTRL_1, 0xEB);
  1137. if (wcd939x->hph_mode == CLS_H_LOHIFI)
  1138. snd_soc_component_write(component,
  1139. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x52);
  1140. else
  1141. snd_soc_component_write(component,
  1142. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x64);
  1143. }
  1144. break;
  1145. case SND_SOC_DAPM_POST_PMD:
  1146. snd_soc_component_update_bits(component,
  1147. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x01));
  1148. snd_soc_component_update_bits(component,
  1149. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHR_RX_EN, 0x00));
  1150. break;
  1151. }
  1152. return 0;
  1153. }
  1154. static int wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1155. struct snd_kcontrol *kcontrol,
  1156. int event)
  1157. {
  1158. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1159. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1160. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1161. w->name, event);
  1162. switch (event) {
  1163. case SND_SOC_DAPM_PRE_PMU:
  1164. snd_soc_component_update_bits(component,
  1165. REG_FIELD_VALUE(CDC_EAR_GAIN_CTL, EAR_EN, 0x01));
  1166. snd_soc_component_update_bits(component,
  1167. REG_FIELD_VALUE(EAR_DAC_CON, DAC_SAMPLE_EDGE_SEL, 0x00));
  1168. /* 5 msec delay as per HW requirement */
  1169. usleep_range(5000, 5010);
  1170. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1171. WCD_CLSH_EVENT_PRE_DAC,
  1172. WCD_CLSH_STATE_EAR,
  1173. CLS_AB_HIFI);
  1174. snd_soc_component_update_bits(component,
  1175. REG_FIELD_VALUE(VNEG_CTRL_4, ILIM_SEL, 0xD));
  1176. break;
  1177. case SND_SOC_DAPM_POST_PMD:
  1178. snd_soc_component_update_bits(component,
  1179. REG_FIELD_VALUE(EAR_DAC_CON, DAC_SAMPLE_EDGE_SEL, 0x01));
  1180. break;
  1181. };
  1182. return 0;
  1183. }
  1184. static int wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1185. struct snd_kcontrol *kcontrol,
  1186. int event)
  1187. {
  1188. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1189. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1190. int ret = 0;
  1191. int hph_mode = wcd939x->hph_mode;
  1192. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1193. w->name, event);
  1194. switch (event) {
  1195. case SND_SOC_DAPM_PRE_PMU:
  1196. if (wcd939x->ldoh)
  1197. snd_soc_component_update_bits(component,
  1198. REG_FIELD_VALUE(MODE, LDOH_EN, 0x01));
  1199. if (wcd939x->update_wcd_event)
  1200. wcd939x->update_wcd_event(wcd939x->handle,
  1201. SLV_BOLERO_EVT_RX_MUTE,
  1202. (WCD_RX2 << 0x10 | 0x1));
  1203. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1204. wcd939x->rx_swr_dev->dev_num,
  1205. true);
  1206. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1207. WCD_CLSH_EVENT_PRE_DAC,
  1208. WCD_CLSH_STATE_HPHR,
  1209. hph_mode);
  1210. wcd939x_config_2Vpk_mode(component, wcd939x, REGULATOR_MODE_2VPK);
  1211. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  1212. hph_mode == CLS_H_ULP) {
  1213. if (!wcd939x->hph_pcm_enabled)
  1214. snd_soc_component_update_bits(component,
  1215. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x01));
  1216. }
  1217. /* update Mode for LOHIFI */
  1218. if (hph_mode == CLS_H_LOHIFI) {
  1219. snd_soc_component_update_bits(component,
  1220. REG_FIELD_VALUE(HPH, PWR_LEVEL, 0x00));
  1221. }
  1222. /* update USBSS power mode for AATC */
  1223. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog)
  1224. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE,
  1225. wcd939x_get_usbss_hph_power_mode(hph_mode));
  1226. snd_soc_component_update_bits(component,
  1227. REG_FIELD_VALUE(VNEG_CTRL_4, ILIM_SEL, 0xD));
  1228. snd_soc_component_update_bits(component,
  1229. REG_FIELD_VALUE(HPH, HPHR_REF_ENABLE, 0x01));
  1230. if ((snd_soc_component_read(component, WCD939X_HPH) & 0x30) == 0x30)
  1231. usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
  1232. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1233. if (!wcd939x->hph_pcm_enabled)
  1234. snd_soc_component_update_bits(component,
  1235. REG_FIELD_VALUE(PDM_WD_CTL1, PDM_WD_EN, 0x03));
  1236. break;
  1237. case SND_SOC_DAPM_POST_PMU:
  1238. /*
  1239. * 7ms sleep is required if compander is enabled as per
  1240. * HW requirement. If compander is disabled, then
  1241. * 20ms delay is required.
  1242. */
  1243. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1244. if (!wcd939x->comp2_enable)
  1245. usleep_range(20000, 20100);
  1246. else
  1247. usleep_range(7000, 7100);
  1248. if (hph_mode == CLS_H_LP ||
  1249. hph_mode == CLS_H_LOHIFI ||
  1250. hph_mode == CLS_H_ULP)
  1251. if (!wcd939x->hph_pcm_enabled)
  1252. snd_soc_component_update_bits(component,
  1253. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x00));
  1254. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1255. }
  1256. snd_soc_component_update_bits(component,
  1257. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x01));
  1258. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1259. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1260. snd_soc_component_update_bits(component,
  1261. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1262. if (wcd939x->update_wcd_event)
  1263. wcd939x->update_wcd_event(wcd939x->handle,
  1264. SLV_BOLERO_EVT_RX_MUTE,
  1265. (WCD_RX2 << 0x10));
  1266. /*Enable PDM INT for PDM data path only*/
  1267. if (!wcd939x->hph_pcm_enabled)
  1268. wcd_enable_irq(&wcd939x->irq_info,
  1269. WCD939X_IRQ_HPHR_PDM_WD_INT);
  1270. break;
  1271. case SND_SOC_DAPM_PRE_PMD:
  1272. if (wcd939x->update_wcd_event)
  1273. wcd939x->update_wcd_event(wcd939x->handle,
  1274. SLV_BOLERO_EVT_RX_MUTE,
  1275. (WCD_RX2 << 0x10 | 0x1));
  1276. wcd_disable_irq(&wcd939x->irq_info,
  1277. WCD939X_IRQ_HPHR_PDM_WD_INT);
  1278. if (wcd939x->update_wcd_event && wcd939x->comp2_enable)
  1279. wcd939x->update_wcd_event(wcd939x->handle,
  1280. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1281. (WCD_RX2 << 0x10));
  1282. /*
  1283. * 7ms sleep is required if compander is enabled as per
  1284. * HW requirement. If compander is disabled, then
  1285. * 20ms delay is required.
  1286. */
  1287. if (!wcd939x->comp2_enable)
  1288. usleep_range(20000, 20100);
  1289. else
  1290. usleep_range(7000, 7100);
  1291. snd_soc_component_update_bits(component,
  1292. REG_FIELD_VALUE(HPH, HPHR_ENABLE, 0x00));
  1293. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1294. WCD_EVENT_PRE_HPHR_PA_OFF,
  1295. &wcd939x->mbhc->wcd_mbhc);
  1296. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1297. break;
  1298. case SND_SOC_DAPM_POST_PMD:
  1299. /*
  1300. * 7ms sleep is required if compander is enabled as per
  1301. * HW requirement. If compander is disabled, then
  1302. * 20ms delay is required.
  1303. */
  1304. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1305. if (!wcd939x->comp2_enable)
  1306. usleep_range(20000, 20100);
  1307. else
  1308. usleep_range(7000, 7100);
  1309. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1310. }
  1311. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1312. WCD_EVENT_POST_HPHR_PA_OFF,
  1313. &wcd939x->mbhc->wcd_mbhc);
  1314. snd_soc_component_update_bits(component,
  1315. REG_FIELD_VALUE(HPH, HPHR_REF_ENABLE, 0x00));
  1316. snd_soc_component_update_bits(component,
  1317. REG_FIELD_VALUE(PDM_WD_CTL1, PDM_WD_EN, 0x00));
  1318. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog &&
  1319. !(snd_soc_component_read(component, WCD939X_HPH) & 0XC0))
  1320. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE, 1);
  1321. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1322. WCD_CLSH_EVENT_POST_PA,
  1323. WCD_CLSH_STATE_HPHR,
  1324. hph_mode);
  1325. if (wcd939x->ldoh)
  1326. snd_soc_component_update_bits(component,
  1327. REG_FIELD_VALUE(MODE, LDOH_EN, 0x00));
  1328. break;
  1329. };
  1330. return ret;
  1331. }
  1332. static int wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1333. struct snd_kcontrol *kcontrol,
  1334. int event)
  1335. {
  1336. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1337. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1338. int ret = 0;
  1339. int hph_mode = wcd939x->hph_mode;
  1340. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1341. w->name, event);
  1342. switch (event) {
  1343. case SND_SOC_DAPM_PRE_PMU:
  1344. if (wcd939x->ldoh)
  1345. snd_soc_component_update_bits(component,
  1346. REG_FIELD_VALUE(MODE, LDOH_EN, 0x01));
  1347. if (wcd939x->update_wcd_event)
  1348. wcd939x->update_wcd_event(wcd939x->handle,
  1349. SLV_BOLERO_EVT_RX_MUTE,
  1350. (WCD_RX1 << 0x10 | 0x01));
  1351. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1352. wcd939x->rx_swr_dev->dev_num,
  1353. true);
  1354. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1355. WCD_CLSH_EVENT_PRE_DAC,
  1356. WCD_CLSH_STATE_HPHL,
  1357. hph_mode);
  1358. wcd939x_config_2Vpk_mode(component, wcd939x, REGULATOR_MODE_2VPK);
  1359. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  1360. hph_mode == CLS_H_ULP) {
  1361. if (!wcd939x->hph_pcm_enabled)
  1362. snd_soc_component_update_bits(component,
  1363. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x01));
  1364. }
  1365. /* update Mode for LOHIFI */
  1366. if (hph_mode == CLS_H_LOHIFI) {
  1367. snd_soc_component_update_bits(component,
  1368. REG_FIELD_VALUE(HPH, PWR_LEVEL, 0x00));
  1369. }
  1370. /* update USBSS power mode for AATC */
  1371. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog)
  1372. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE,
  1373. wcd939x_get_usbss_hph_power_mode(hph_mode));
  1374. snd_soc_component_update_bits(component,
  1375. REG_FIELD_VALUE(VNEG_CTRL_4, ILIM_SEL, 0xD));
  1376. snd_soc_component_update_bits(component,
  1377. REG_FIELD_VALUE(HPH, HPHL_REF_ENABLE, 0x01));
  1378. if ((snd_soc_component_read(component, WCD939X_HPH) & 0x30) == 0x30)
  1379. usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
  1380. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1381. if (!wcd939x->hph_pcm_enabled)
  1382. snd_soc_component_update_bits(component,
  1383. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x03));
  1384. break;
  1385. case SND_SOC_DAPM_POST_PMU:
  1386. /*
  1387. * 7ms sleep is required if compander is enabled as per
  1388. * HW requirement. If compander is disabled, then
  1389. * 20ms delay is required.
  1390. */
  1391. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1392. if (!wcd939x->comp1_enable)
  1393. usleep_range(20000, 20100);
  1394. else
  1395. usleep_range(7000, 7100);
  1396. if (hph_mode == CLS_H_LP ||
  1397. hph_mode == CLS_H_LOHIFI ||
  1398. hph_mode == CLS_H_ULP)
  1399. if (!wcd939x->hph_pcm_enabled)
  1400. snd_soc_component_update_bits(component,
  1401. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x00));
  1402. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1403. }
  1404. snd_soc_component_update_bits(component,
  1405. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x01));
  1406. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1407. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1408. snd_soc_component_update_bits(component,
  1409. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1410. if (wcd939x->update_wcd_event)
  1411. wcd939x->update_wcd_event(wcd939x->handle,
  1412. SLV_BOLERO_EVT_RX_MUTE,
  1413. (WCD_RX1 << 0x10));
  1414. /*Enable PDM INT for PDM data path only*/
  1415. if (!wcd939x->hph_pcm_enabled)
  1416. wcd_enable_irq(&wcd939x->irq_info,
  1417. WCD939X_IRQ_HPHL_PDM_WD_INT);
  1418. break;
  1419. case SND_SOC_DAPM_PRE_PMD:
  1420. if (wcd939x->update_wcd_event)
  1421. wcd939x->update_wcd_event(wcd939x->handle,
  1422. SLV_BOLERO_EVT_RX_MUTE,
  1423. (WCD_RX1 << 0x10 | 0x1));
  1424. wcd_disable_irq(&wcd939x->irq_info,
  1425. WCD939X_IRQ_HPHL_PDM_WD_INT);
  1426. if (wcd939x->update_wcd_event && wcd939x->comp1_enable)
  1427. wcd939x->update_wcd_event(wcd939x->handle,
  1428. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1429. (WCD_RX1 << 0x10));
  1430. /*
  1431. * 7ms sleep is required if compander is enabled as per
  1432. * HW requirement. If compander is disabled, then
  1433. * 20ms delay is required.
  1434. */
  1435. if (!wcd939x->comp1_enable)
  1436. usleep_range(20000, 20100);
  1437. else
  1438. usleep_range(7000, 7100);
  1439. snd_soc_component_update_bits(component,
  1440. REG_FIELD_VALUE(HPH, HPHL_ENABLE, 0x00));
  1441. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1442. WCD_EVENT_PRE_HPHL_PA_OFF,
  1443. &wcd939x->mbhc->wcd_mbhc);
  1444. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1445. break;
  1446. case SND_SOC_DAPM_POST_PMD:
  1447. /*
  1448. * 7ms sleep is required if compander is enabled as per
  1449. * HW requirement. If compander is disabled, then
  1450. * 20ms delay is required.
  1451. */
  1452. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1453. if (!wcd939x->comp1_enable)
  1454. usleep_range(21000, 21100);
  1455. else
  1456. usleep_range(7000, 7100);
  1457. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1458. }
  1459. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1460. WCD_EVENT_POST_HPHL_PA_OFF,
  1461. &wcd939x->mbhc->wcd_mbhc);
  1462. snd_soc_component_update_bits(component,
  1463. REG_FIELD_VALUE(HPH, HPHL_REF_ENABLE, 0x00));
  1464. snd_soc_component_update_bits(component,
  1465. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x00));
  1466. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog &&
  1467. !(snd_soc_component_read(component, WCD939X_HPH) & 0XC0))
  1468. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE, 1);
  1469. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1470. WCD_CLSH_EVENT_POST_PA,
  1471. WCD_CLSH_STATE_HPHL,
  1472. hph_mode);
  1473. if (wcd939x->ldoh)
  1474. snd_soc_component_update_bits(component,
  1475. REG_FIELD_VALUE(MODE, LDOH_EN, 0x00));
  1476. break;
  1477. };
  1478. return ret;
  1479. }
  1480. static int wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1481. struct snd_kcontrol *kcontrol,
  1482. int event)
  1483. {
  1484. struct snd_soc_component *component =
  1485. snd_soc_dapm_to_component(w->dapm);
  1486. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1487. int ret = 0;
  1488. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1489. w->name, event);
  1490. switch (event) {
  1491. case SND_SOC_DAPM_PRE_PMU:
  1492. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1493. wcd939x->rx_swr_dev->dev_num,
  1494. true);
  1495. /*
  1496. * Enable watchdog interrupt for HPHL
  1497. */
  1498. snd_soc_component_update_bits(component,
  1499. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x03));
  1500. /* For EAR, use CLASS_AB regulator mode */
  1501. snd_soc_component_update_bits(component,
  1502. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1503. snd_soc_component_update_bits(component,
  1504. REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x01));
  1505. break;
  1506. case SND_SOC_DAPM_POST_PMU:
  1507. /* 6 msec delay as per HW requirement */
  1508. usleep_range(6000, 6010);
  1509. if (wcd939x->update_wcd_event)
  1510. wcd939x->update_wcd_event(wcd939x->handle,
  1511. SLV_BOLERO_EVT_RX_MUTE,
  1512. (WCD_RX3 << 0x10));
  1513. wcd_enable_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT);
  1514. break;
  1515. case SND_SOC_DAPM_PRE_PMD:
  1516. wcd_disable_irq(&wcd939x->irq_info,
  1517. WCD939X_IRQ_EAR_PDM_WD_INT);
  1518. if (wcd939x->update_wcd_event)
  1519. wcd939x->update_wcd_event(wcd939x->handle,
  1520. SLV_BOLERO_EVT_RX_MUTE,
  1521. (WCD_RX3 << 0x10 | 0x1));
  1522. break;
  1523. case SND_SOC_DAPM_POST_PMD:
  1524. snd_soc_component_update_bits(component,
  1525. REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x00));
  1526. /* 7 msec delay as per HW requirement */
  1527. usleep_range(7000, 7010);
  1528. snd_soc_component_update_bits(component,
  1529. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x00));
  1530. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1531. WCD_CLSH_EVENT_POST_PA,
  1532. WCD_CLSH_STATE_EAR,
  1533. CLS_AB_HIFI);
  1534. break;
  1535. };
  1536. return ret;
  1537. }
  1538. static int wcd939x_clsh_dummy(struct snd_soc_dapm_widget *w,
  1539. struct snd_kcontrol *kcontrol,
  1540. int event)
  1541. {
  1542. struct snd_soc_component *component =
  1543. snd_soc_dapm_to_component(w->dapm);
  1544. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1545. int ret = 0;
  1546. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1547. w->name, event);
  1548. if (SND_SOC_DAPM_EVENT_OFF(event))
  1549. ret = swr_slvdev_datapath_control(
  1550. wcd939x->rx_swr_dev,
  1551. wcd939x->rx_swr_dev->dev_num,
  1552. false);
  1553. return ret;
  1554. }
  1555. static int wcd939x_enable_clsh(struct snd_soc_dapm_widget *w,
  1556. struct snd_kcontrol *kcontrol,
  1557. int event)
  1558. {
  1559. struct snd_soc_component *component =
  1560. snd_soc_dapm_to_component(w->dapm);
  1561. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1562. int mode = wcd939x->hph_mode;
  1563. int ret = 0;
  1564. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1565. w->name, event);
  1566. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1567. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1568. wcd939x_rx_connect_port(component, CLSH,
  1569. SND_SOC_DAPM_EVENT_ON(event));
  1570. }
  1571. if (SND_SOC_DAPM_EVENT_OFF(event))
  1572. ret = swr_slvdev_datapath_control(
  1573. wcd939x->rx_swr_dev,
  1574. wcd939x->rx_swr_dev->dev_num,
  1575. false);
  1576. return ret;
  1577. }
  1578. static int wcd939x_enable_rx1(struct snd_soc_dapm_widget *w,
  1579. struct snd_kcontrol *kcontrol,
  1580. int event)
  1581. {
  1582. struct snd_soc_component *component =
  1583. snd_soc_dapm_to_component(w->dapm);
  1584. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1585. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1586. w->name, event);
  1587. switch (event) {
  1588. case SND_SOC_DAPM_PRE_PMU:
  1589. if (wcd939x->hph_pcm_enabled)
  1590. wcd939x_rx_connect_port(component, HIFI_PCM_L, true);
  1591. else {
  1592. wcd939x_rx_connect_port(component, HPH_L, true);
  1593. if (wcd939x->comp1_enable)
  1594. wcd939x_rx_connect_port(component, COMP_L, true);
  1595. }
  1596. break;
  1597. case SND_SOC_DAPM_POST_PMD:
  1598. if (wcd939x->hph_pcm_enabled)
  1599. wcd939x_rx_connect_port(component, HIFI_PCM_L, false);
  1600. else {
  1601. wcd939x_rx_connect_port(component, HPH_L, false);
  1602. if (wcd939x->comp1_enable)
  1603. wcd939x_rx_connect_port(component, COMP_L, false);
  1604. }
  1605. break;
  1606. };
  1607. return 0;
  1608. }
  1609. static int wcd939x_enable_rx2(struct snd_soc_dapm_widget *w,
  1610. struct snd_kcontrol *kcontrol, int event)
  1611. {
  1612. struct snd_soc_component *component =
  1613. snd_soc_dapm_to_component(w->dapm);
  1614. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1615. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1616. w->name, event);
  1617. switch (event) {
  1618. case SND_SOC_DAPM_PRE_PMU:
  1619. if (wcd939x->hph_pcm_enabled)
  1620. wcd939x_rx_connect_port(component, HIFI_PCM_R, true);
  1621. else {
  1622. wcd939x_rx_connect_port(component, HPH_R, true);
  1623. if (wcd939x->comp2_enable)
  1624. wcd939x_rx_connect_port(component, COMP_R, true);
  1625. }
  1626. break;
  1627. case SND_SOC_DAPM_POST_PMD:
  1628. if (wcd939x->hph_pcm_enabled)
  1629. wcd939x_rx_connect_port(component, HIFI_PCM_R, false);
  1630. else {
  1631. wcd939x_rx_connect_port(component, HPH_R, false);
  1632. if (wcd939x->comp2_enable)
  1633. wcd939x_rx_connect_port(component, COMP_R, false);
  1634. }
  1635. break;
  1636. };
  1637. return 0;
  1638. }
  1639. static int wcd939x_enable_rx3(struct snd_soc_dapm_widget *w,
  1640. struct snd_kcontrol *kcontrol,
  1641. int event)
  1642. {
  1643. struct snd_soc_component *component =
  1644. snd_soc_dapm_to_component(w->dapm);
  1645. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1646. w->name, event);
  1647. switch (event) {
  1648. case SND_SOC_DAPM_PRE_PMU:
  1649. wcd939x_rx_connect_port(component, LO, true);
  1650. break;
  1651. case SND_SOC_DAPM_POST_PMD:
  1652. wcd939x_rx_connect_port(component, LO, false);
  1653. /* 6 msec delay as per HW requirement */
  1654. usleep_range(6000, 6010);
  1655. break;
  1656. }
  1657. return 0;
  1658. }
  1659. static int wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1660. struct snd_kcontrol *kcontrol,
  1661. int event)
  1662. {
  1663. struct snd_soc_component *component =
  1664. snd_soc_dapm_to_component(w->dapm);
  1665. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1666. u16 dmic_clk_reg, dmic_clk_en_reg;
  1667. s32 *dmic_clk_cnt;
  1668. u8 dmic_ctl_shift = 0;
  1669. u8 dmic_clk_shift = 0;
  1670. u8 dmic_clk_mask = 0;
  1671. u16 dmic2_left_en = 0;
  1672. int ret = 0;
  1673. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1674. w->name, event);
  1675. switch (w->shift) {
  1676. case 0:
  1677. case 1:
  1678. dmic_clk_cnt = &(wcd939x->dmic_0_1_clk_cnt);
  1679. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_1_2;
  1680. dmic_clk_en_reg = WCD939X_CDC_DMIC1_CTL;
  1681. dmic_clk_mask = 0x0F;
  1682. dmic_clk_shift = 0x00;
  1683. dmic_ctl_shift = 0x00;
  1684. break;
  1685. case 2:
  1686. dmic2_left_en = WCD939X_CDC_DMIC2_CTL;
  1687. fallthrough;
  1688. case 3:
  1689. dmic_clk_cnt = &(wcd939x->dmic_2_3_clk_cnt);
  1690. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_1_2;
  1691. dmic_clk_en_reg = WCD939X_CDC_DMIC2_CTL;
  1692. dmic_clk_mask = 0xF0;
  1693. dmic_clk_shift = 0x04;
  1694. dmic_ctl_shift = 0x01;
  1695. break;
  1696. case 4:
  1697. case 5:
  1698. dmic_clk_cnt = &(wcd939x->dmic_4_5_clk_cnt);
  1699. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_3_4;
  1700. dmic_clk_en_reg = WCD939X_CDC_DMIC3_CTL;
  1701. dmic_clk_mask = 0x0F;
  1702. dmic_clk_shift = 0x00;
  1703. dmic_ctl_shift = 0x02;
  1704. break;
  1705. case 6:
  1706. case 7:
  1707. dmic_clk_cnt = &(wcd939x->dmic_6_7_clk_cnt);
  1708. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_3_4;
  1709. dmic_clk_en_reg = WCD939X_CDC_DMIC4_CTL;
  1710. dmic_clk_mask = 0xF0;
  1711. dmic_clk_shift = 0x04;
  1712. dmic_ctl_shift = 0x03;
  1713. break;
  1714. default:
  1715. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  1716. __func__);
  1717. return -EINVAL;
  1718. };
  1719. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1720. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1721. switch (event) {
  1722. case SND_SOC_DAPM_PRE_PMU:
  1723. snd_soc_component_update_bits(component,
  1724. WCD939X_CDC_AMIC_CTL,
  1725. (0x01 << dmic_ctl_shift), 0x00);
  1726. /* 250us sleep as per HW requirement */
  1727. usleep_range(250, 260);
  1728. if (dmic2_left_en)
  1729. snd_soc_component_update_bits(component,
  1730. dmic2_left_en, 0x80, 0x80);
  1731. /* Setting DMIC clock rate to 2.4MHz */
  1732. snd_soc_component_update_bits(component,
  1733. dmic_clk_reg, dmic_clk_mask,
  1734. (0x03 << dmic_clk_shift));
  1735. snd_soc_component_update_bits(component,
  1736. dmic_clk_en_reg, 0x08, 0x08);
  1737. /* enable clock scaling */
  1738. snd_soc_component_update_bits(component,
  1739. REG_FIELD_VALUE(CDC_DMIC_CTL, CLK_SCALE_EN, 0x01));
  1740. snd_soc_component_update_bits(component,
  1741. REG_FIELD_VALUE(CDC_DMIC_CTL, DMIC_DIV_BAK_EN, 0x01));
  1742. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  1743. wcd939x->tx_swr_dev->dev_num,
  1744. true);
  1745. break;
  1746. case SND_SOC_DAPM_POST_PMD:
  1747. wcd939x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1748. false);
  1749. snd_soc_component_update_bits(component,
  1750. WCD939X_CDC_AMIC_CTL,
  1751. (0x01 << dmic_ctl_shift),
  1752. (0x01 << dmic_ctl_shift));
  1753. if (dmic2_left_en)
  1754. snd_soc_component_update_bits(component,
  1755. dmic2_left_en, 0x80, 0x00);
  1756. snd_soc_component_update_bits(component,
  1757. dmic_clk_en_reg, 0x08, 0x00);
  1758. break;
  1759. };
  1760. return ret;
  1761. }
  1762. /*
  1763. * wcd939x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1764. * @micb_mv: micbias in mv
  1765. *
  1766. * return register value converted
  1767. */
  1768. int wcd939x_get_micb_vout_ctl_val(u32 micb_mv)
  1769. {
  1770. /* min micbias voltage is 1V and maximum is 2.85V */
  1771. if (micb_mv < 1000 || micb_mv > 2850) {
  1772. pr_err_ratelimited("%s: unsupported micbias voltage\n", __func__);
  1773. return -EINVAL;
  1774. }
  1775. return (micb_mv - 1000) / 50;
  1776. }
  1777. EXPORT_SYMBOL(wcd939x_get_micb_vout_ctl_val);
  1778. /*
  1779. * wcd939x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1780. * @component: handle to snd_soc_component *
  1781. * @req_volt: micbias voltage to be set
  1782. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1783. *
  1784. * return 0 if adjustment is success or error code in case of failure
  1785. */
  1786. int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1787. int req_volt, int micb_num)
  1788. {
  1789. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1790. int cur_vout_ctl, req_vout_ctl;
  1791. int micb_reg, micb_val, micb_en;
  1792. int ret = 0;
  1793. switch (micb_num) {
  1794. case MIC_BIAS_1:
  1795. micb_reg = WCD939X_MICB1;
  1796. break;
  1797. case MIC_BIAS_2:
  1798. micb_reg = WCD939X_MICB2;
  1799. break;
  1800. case MIC_BIAS_3:
  1801. micb_reg = WCD939X_MICB3;
  1802. break;
  1803. case MIC_BIAS_4:
  1804. micb_reg = WCD939X_MICB4;
  1805. break;
  1806. default:
  1807. return -EINVAL;
  1808. }
  1809. mutex_lock(&wcd939x->micb_lock);
  1810. /*
  1811. * If requested micbias voltage is same as current micbias
  1812. * voltage, then just return. Otherwise, adjust voltage as
  1813. * per requested value. If micbias is already enabled, then
  1814. * to avoid slow micbias ramp-up or down enable pull-up
  1815. * momentarily, change the micbias value and then re-enable
  1816. * micbias.
  1817. */
  1818. micb_val = snd_soc_component_read(component, micb_reg);
  1819. micb_en = (micb_val & 0xC0) >> 6;
  1820. cur_vout_ctl = micb_val & 0x3F;
  1821. req_vout_ctl = wcd939x_get_micb_vout_ctl_val(req_volt);
  1822. if (req_vout_ctl < 0) {
  1823. ret = -EINVAL;
  1824. goto exit;
  1825. }
  1826. if (cur_vout_ctl == req_vout_ctl) {
  1827. ret = 0;
  1828. goto exit;
  1829. }
  1830. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1831. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1832. req_volt, micb_en);
  1833. if (micb_en == 0x1)
  1834. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1835. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1836. if (micb_en == 0x1) {
  1837. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1838. /*
  1839. * Add 2ms delay as per HW requirement after enabling
  1840. * micbias
  1841. */
  1842. usleep_range(2000, 2100);
  1843. }
  1844. exit:
  1845. mutex_unlock(&wcd939x->micb_lock);
  1846. return ret;
  1847. }
  1848. EXPORT_SYMBOL(wcd939x_mbhc_micb_adjust_voltage);
  1849. static int wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1850. struct snd_kcontrol *kcontrol,
  1851. int event)
  1852. {
  1853. struct snd_soc_component *component =
  1854. snd_soc_dapm_to_component(w->dapm);
  1855. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1856. int ret = 0;
  1857. int bank = 0;
  1858. u8 mode = 0;
  1859. int i = 0;
  1860. int rate = 0;
  1861. bank = (wcd939x_swr_slv_get_current_bank(wcd939x->tx_swr_dev,
  1862. wcd939x->tx_swr_dev->dev_num) ? 0 : 1);
  1863. /* power mode is applicable only to analog mics */
  1864. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1865. /* Get channel rate */
  1866. rate = wcd939x_get_clk_rate(wcd939x->tx_mode[w->shift - ADC1]);
  1867. }
  1868. switch (event) {
  1869. case SND_SOC_DAPM_PRE_PMU:
  1870. /* Check AMIC2 is connected to ADC2 to take an action on BCS */
  1871. if (w->shift == ADC2 &&
  1872. (((snd_soc_component_read(component, WCD939X_TX_CH12_MUX) &
  1873. 0x38) >> 3) == 0x2)) {
  1874. if (!wcd939x->bcs_dis) {
  1875. wcd939x_tx_connect_port(component, MBHC,
  1876. SWR_CLK_RATE_4P8MHZ, true);
  1877. set_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask);
  1878. }
  1879. }
  1880. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1881. set_bit(w->shift - ADC1, &wcd939x->status_mask);
  1882. wcd939x_tx_connect_port(component, w->shift, rate,
  1883. true);
  1884. } else {
  1885. wcd939x_tx_connect_port(component, w->shift,
  1886. SWR_CLK_RATE_2P4MHZ, true);
  1887. }
  1888. break;
  1889. case SND_SOC_DAPM_POST_PMD:
  1890. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1891. if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
  1892. clear_bit(WCD_ADC1, &wcd939x->status_mask);
  1893. clear_bit(WCD_ADC1_MODE, &wcd939x->status_mask);
  1894. } else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
  1895. clear_bit(WCD_ADC2, &wcd939x->status_mask);
  1896. clear_bit(WCD_ADC2_MODE, &wcd939x->status_mask);
  1897. } else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
  1898. clear_bit(WCD_ADC3, &wcd939x->status_mask);
  1899. clear_bit(WCD_ADC3_MODE, &wcd939x->status_mask);
  1900. } else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
  1901. clear_bit(WCD_ADC4, &wcd939x->status_mask);
  1902. clear_bit(WCD_ADC4_MODE, &wcd939x->status_mask);
  1903. }
  1904. }
  1905. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1906. if (test_bit(WCD_ADC1, &wcd939x->status_mask) ||
  1907. test_bit(WCD_ADC1_MODE, &wcd939x->status_mask))
  1908. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
  1909. if (test_bit(WCD_ADC2, &wcd939x->status_mask) ||
  1910. test_bit(WCD_ADC2_MODE, &wcd939x->status_mask))
  1911. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
  1912. if (test_bit(WCD_ADC3, &wcd939x->status_mask) ||
  1913. test_bit(WCD_ADC3_MODE, &wcd939x->status_mask))
  1914. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
  1915. if (test_bit(WCD_ADC4, &wcd939x->status_mask) ||
  1916. test_bit(WCD_ADC4_MODE, &wcd939x->status_mask))
  1917. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
  1918. if (mode != 0) {
  1919. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1920. if (mode & (1 << i)) {
  1921. i++;
  1922. break;
  1923. }
  1924. }
  1925. }
  1926. rate = wcd939x_get_clk_rate(i);
  1927. if (wcd939x->adc_count) {
  1928. rate = (wcd939x->adc_count * rate);
  1929. if (rate > SWR_CLK_RATE_9P6MHZ)
  1930. rate = SWR_CLK_RATE_9P6MHZ;
  1931. }
  1932. wcd939x_set_swr_clk_rate(component, rate, bank);
  1933. }
  1934. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  1935. wcd939x->tx_swr_dev->dev_num,
  1936. false);
  1937. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1938. wcd939x_set_swr_clk_rate(component, rate, !bank);
  1939. break;
  1940. };
  1941. return ret;
  1942. }
  1943. static int wcd939x_get_adc_mode(int val)
  1944. {
  1945. int ret = 0;
  1946. switch (val) {
  1947. case ADC_MODE_INVALID:
  1948. ret = ADC_MODE_VAL_NORMAL;
  1949. break;
  1950. case ADC_MODE_HIFI:
  1951. ret = ADC_MODE_VAL_HIFI;
  1952. break;
  1953. case ADC_MODE_LO_HIF:
  1954. ret = ADC_MODE_VAL_LO_HIF;
  1955. break;
  1956. case ADC_MODE_NORMAL:
  1957. ret = ADC_MODE_VAL_NORMAL;
  1958. break;
  1959. case ADC_MODE_LP:
  1960. ret = ADC_MODE_VAL_LP;
  1961. break;
  1962. case ADC_MODE_ULP1:
  1963. ret = ADC_MODE_VAL_ULP1;
  1964. break;
  1965. case ADC_MODE_ULP2:
  1966. ret = ADC_MODE_VAL_ULP2;
  1967. break;
  1968. default:
  1969. ret = -EINVAL;
  1970. pr_err_ratelimited("%s: invalid ADC mode value %d\n", __func__, val);
  1971. break;
  1972. }
  1973. return ret;
  1974. }
  1975. int wcd939x_tx_channel_config(struct snd_soc_component *component,
  1976. int channel, int mode)
  1977. {
  1978. int reg = WCD939X_TX_CH2, mask = 0, val = 0;
  1979. int ret = 0;
  1980. switch (channel) {
  1981. case 0:
  1982. reg = WCD939X_TX_CH2;
  1983. mask = 0x40;
  1984. break;
  1985. case 1:
  1986. reg = WCD939X_TX_CH2;
  1987. mask = 0x20;
  1988. break;
  1989. case 2:
  1990. reg = WCD939X_TX_CH4;
  1991. mask = 0x40;
  1992. break;
  1993. case 3:
  1994. reg = WCD939X_TX_CH4;
  1995. mask = 0x20;
  1996. break;
  1997. default:
  1998. pr_err_ratelimited("%s: Invalid channel num %d\n", __func__, channel);
  1999. ret = -EINVAL;
  2000. break;
  2001. }
  2002. if (!mode)
  2003. val = 0x00;
  2004. else
  2005. val = mask;
  2006. if (!ret)
  2007. snd_soc_component_update_bits(component, reg, mask, val);
  2008. return ret;
  2009. }
  2010. static int wcd939x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  2011. struct snd_kcontrol *kcontrol,
  2012. int event){
  2013. struct snd_soc_component *component =
  2014. snd_soc_dapm_to_component(w->dapm);
  2015. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2016. int clk_rate = 0, ret = 0;
  2017. int mode = 0, i = 0, bank = 0;
  2018. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2019. w->name, event);
  2020. bank = (wcd939x_swr_slv_get_current_bank(wcd939x->tx_swr_dev,
  2021. wcd939x->tx_swr_dev->dev_num) ? 0 : 1);
  2022. switch (event) {
  2023. case SND_SOC_DAPM_PRE_PMU:
  2024. wcd939x->adc_count++;
  2025. if (test_bit(WCD_ADC1, &wcd939x->status_mask) ||
  2026. test_bit(WCD_ADC1_MODE, &wcd939x->status_mask))
  2027. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
  2028. if (test_bit(WCD_ADC2, &wcd939x->status_mask) ||
  2029. test_bit(WCD_ADC2_MODE, &wcd939x->status_mask))
  2030. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
  2031. if (test_bit(WCD_ADC3, &wcd939x->status_mask) ||
  2032. test_bit(WCD_ADC3_MODE, &wcd939x->status_mask))
  2033. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
  2034. if (test_bit(WCD_ADC4, &wcd939x->status_mask) ||
  2035. test_bit(WCD_ADC4_MODE, &wcd939x->status_mask))
  2036. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
  2037. if (mode != 0) {
  2038. for (i = 0; i < ADC_MODE_ULP2; i++) {
  2039. if (mode & (1 << i)) {
  2040. i++;
  2041. break;
  2042. }
  2043. }
  2044. }
  2045. clk_rate = wcd939x_get_clk_rate(i);
  2046. /* clk_rate depends on number of paths getting enabled */
  2047. clk_rate = (wcd939x->adc_count * clk_rate);
  2048. if (clk_rate > SWR_CLK_RATE_9P6MHZ)
  2049. clk_rate = SWR_CLK_RATE_9P6MHZ;
  2050. wcd939x_set_swr_clk_rate(component, clk_rate, bank);
  2051. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  2052. wcd939x->tx_swr_dev->dev_num,
  2053. true);
  2054. wcd939x_set_swr_clk_rate(component, clk_rate, !bank);
  2055. break;
  2056. case SND_SOC_DAPM_POST_PMD:
  2057. wcd939x->adc_count--;
  2058. if (wcd939x->adc_count < 0)
  2059. wcd939x->adc_count = 0;
  2060. wcd939x_tx_connect_port(component, ADC1 + w->shift, 0, false);
  2061. if (w->shift + ADC1 == ADC2 &&
  2062. test_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask)) {
  2063. wcd939x_tx_connect_port(component, MBHC, 0,
  2064. false);
  2065. clear_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask);
  2066. }
  2067. break;
  2068. };
  2069. return ret;
  2070. }
  2071. void wcd939x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  2072. bool bcs_disable)
  2073. {
  2074. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2075. if (wcd939x->update_wcd_event) {
  2076. if (bcs_disable)
  2077. wcd939x->update_wcd_event(wcd939x->handle,
  2078. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  2079. else
  2080. wcd939x->update_wcd_event(wcd939x->handle,
  2081. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  2082. }
  2083. }
  2084. static int wcd939x_enable_req(struct snd_soc_dapm_widget *w,
  2085. struct snd_kcontrol *kcontrol, int event)
  2086. {
  2087. struct snd_soc_component *component =
  2088. snd_soc_dapm_to_component(w->dapm);
  2089. struct wcd939x_priv *wcd939x =
  2090. snd_soc_component_get_drvdata(component);
  2091. int ret = 0;
  2092. u8 mode = 0;
  2093. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2094. w->name, event);
  2095. switch (event) {
  2096. case SND_SOC_DAPM_PRE_PMU:
  2097. snd_soc_component_update_bits(component,
  2098. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_CLK_EN, 0x01));
  2099. snd_soc_component_update_bits(component,
  2100. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x01));
  2101. snd_soc_component_update_bits(component,
  2102. REG_FIELD_VALUE(CDC_REQ_CTL, FS_RATE_4P8, 0x01));
  2103. snd_soc_component_update_bits(component,
  2104. REG_FIELD_VALUE(CDC_REQ_CTL, NO_NOTCH, 0x00));
  2105. ret = wcd939x_tx_channel_config(component, w->shift, 1);
  2106. mode = wcd939x_get_adc_mode(wcd939x->tx_mode[w->shift]);
  2107. if (mode < 0) {
  2108. dev_info_ratelimited(component->dev,
  2109. "%s: invalid mode, setting to normal mode\n",
  2110. __func__);
  2111. mode = ADC_MODE_VAL_NORMAL;
  2112. }
  2113. switch (w->shift) {
  2114. case 0:
  2115. snd_soc_component_update_bits(component,
  2116. WCD939X_CDC_TX_ANA_MODE_0_1, 0x0F,
  2117. mode);
  2118. snd_soc_component_update_bits(component,
  2119. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD0_CLK_EN, 0x01));
  2120. break;
  2121. case 1:
  2122. snd_soc_component_update_bits(component,
  2123. WCD939X_CDC_TX_ANA_MODE_0_1, 0xF0,
  2124. mode << 4);
  2125. snd_soc_component_update_bits(component,
  2126. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD1_CLK_EN, 0x01));
  2127. break;
  2128. case 2:
  2129. snd_soc_component_update_bits(component,
  2130. WCD939X_CDC_TX_ANA_MODE_2_3, 0x0F,
  2131. mode);
  2132. snd_soc_component_update_bits(component,
  2133. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD2_CLK_EN, 0x01));
  2134. break;
  2135. case 3:
  2136. snd_soc_component_update_bits(component,
  2137. WCD939X_CDC_TX_ANA_MODE_2_3, 0xF0,
  2138. mode << 4);
  2139. snd_soc_component_update_bits(component,
  2140. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD3_CLK_EN, 0x01));
  2141. break;
  2142. default:
  2143. break;
  2144. }
  2145. ret |= wcd939x_tx_channel_config(component, w->shift, 0);
  2146. break;
  2147. case SND_SOC_DAPM_POST_PMD:
  2148. switch (w->shift) {
  2149. case 0:
  2150. snd_soc_component_update_bits(component,
  2151. REG_FIELD_VALUE(CDC_TX_ANA_MODE_0_1, TXD0_MODE, 0x00));
  2152. snd_soc_component_update_bits(component,
  2153. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD0_CLK_EN, 0x00));
  2154. break;
  2155. case 1:
  2156. snd_soc_component_update_bits(component,
  2157. REG_FIELD_VALUE(CDC_TX_ANA_MODE_0_1, TXD1_MODE, 0x00));
  2158. snd_soc_component_update_bits(component,
  2159. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD1_CLK_EN, 0x00));
  2160. break;
  2161. case 2:
  2162. snd_soc_component_update_bits(component,
  2163. REG_FIELD_VALUE(CDC_TX_ANA_MODE_2_3, TXD2_MODE, 0x00));
  2164. snd_soc_component_update_bits(component,
  2165. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD2_CLK_EN, 0x00));
  2166. break;
  2167. case 3:
  2168. snd_soc_component_update_bits(component,
  2169. REG_FIELD_VALUE(CDC_TX_ANA_MODE_2_3, TXD3_MODE, 0x00));
  2170. snd_soc_component_update_bits(component,
  2171. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD3_CLK_EN, 0x00));
  2172. break;
  2173. default:
  2174. break;
  2175. }
  2176. if (wcd939x->adc_count == 0) {
  2177. snd_soc_component_update_bits(component,
  2178. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x00));
  2179. snd_soc_component_update_bits(component,
  2180. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_CLK_EN, 0x00));
  2181. }
  2182. break;
  2183. };
  2184. return ret;
  2185. }
  2186. int wcd939x_micbias_control(struct snd_soc_component *component,
  2187. int micb_num, int req, bool is_dapm)
  2188. {
  2189. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2190. int micb_index = micb_num - 1;
  2191. u16 micb_reg;
  2192. int pre_off_event = 0, post_off_event = 0;
  2193. int post_on_event = 0, post_dapm_off = 0;
  2194. int post_dapm_on = 0;
  2195. int ret = 0;
  2196. if ((micb_index < 0) || (micb_index > WCD939X_MAX_MICBIAS - 1)) {
  2197. dev_err_ratelimited(component->dev,
  2198. "%s: Invalid micbias index, micb_ind:%d\n",
  2199. __func__, micb_index);
  2200. return -EINVAL;
  2201. }
  2202. if (NULL == wcd939x) {
  2203. dev_err_ratelimited(component->dev,
  2204. "%s: wcd939x private data is NULL\n", __func__);
  2205. return -EINVAL;
  2206. }
  2207. switch (micb_num) {
  2208. case MIC_BIAS_1:
  2209. micb_reg = WCD939X_MICB1;
  2210. break;
  2211. case MIC_BIAS_2:
  2212. micb_reg = WCD939X_MICB2;
  2213. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  2214. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  2215. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  2216. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  2217. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  2218. break;
  2219. case MIC_BIAS_3:
  2220. micb_reg = WCD939X_MICB3;
  2221. break;
  2222. case MIC_BIAS_4:
  2223. micb_reg = WCD939X_MICB4;
  2224. break;
  2225. default:
  2226. dev_err_ratelimited(component->dev, "%s: Invalid micbias number: %d\n",
  2227. __func__, micb_num);
  2228. return -EINVAL;
  2229. };
  2230. mutex_lock(&wcd939x->micb_lock);
  2231. switch (req) {
  2232. case MICB_PULLUP_ENABLE:
  2233. if (!wcd939x->dev_up) {
  2234. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2235. __func__, req);
  2236. ret = -ENODEV;
  2237. goto done;
  2238. }
  2239. wcd939x->pullup_ref[micb_index]++;
  2240. if ((wcd939x->pullup_ref[micb_index] == 1) &&
  2241. (wcd939x->micb_ref[micb_index] == 0))
  2242. snd_soc_component_update_bits(component, micb_reg,
  2243. 0xC0, 0x80);
  2244. break;
  2245. case MICB_PULLUP_DISABLE:
  2246. if (wcd939x->pullup_ref[micb_index] > 0)
  2247. wcd939x->pullup_ref[micb_index]--;
  2248. if (!wcd939x->dev_up) {
  2249. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2250. __func__, req);
  2251. ret = -ENODEV;
  2252. goto done;
  2253. }
  2254. if ((wcd939x->pullup_ref[micb_index] == 0) &&
  2255. (wcd939x->micb_ref[micb_index] == 0))
  2256. snd_soc_component_update_bits(component, micb_reg,
  2257. 0xC0, 0x00);
  2258. break;
  2259. case MICB_ENABLE:
  2260. if (!wcd939x->dev_up) {
  2261. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2262. __func__, req);
  2263. ret = -ENODEV;
  2264. goto done;
  2265. }
  2266. wcd939x->micb_ref[micb_index]++;
  2267. if (wcd939x->micb_ref[micb_index] == 1) {
  2268. snd_soc_component_update_bits(component,
  2269. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD3_CLK_EN, 0x01));
  2270. snd_soc_component_update_bits(component,
  2271. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD2_CLK_EN, 0x01));
  2272. snd_soc_component_update_bits(component,
  2273. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD1_CLK_EN, 0x01));
  2274. snd_soc_component_update_bits(component,
  2275. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD0_CLK_EN, 0x01));
  2276. snd_soc_component_update_bits(component,
  2277. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x01));
  2278. snd_soc_component_update_bits(component,
  2279. REG_FIELD_VALUE(CDC_ANA_TX_CLK_CTL, ANA_TXSCBIAS_CLK_EN, 0x01));
  2280. snd_soc_component_update_bits(component,
  2281. REG_FIELD_VALUE(TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2282. snd_soc_component_update_bits(component,
  2283. REG_FIELD_VALUE(MICB2_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2284. snd_soc_component_update_bits(component,
  2285. REG_FIELD_VALUE(MICB3_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2286. snd_soc_component_update_bits(component,
  2287. REG_FIELD_VALUE(MICB4_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2288. snd_soc_component_update_bits(component,
  2289. micb_reg, 0xC0, 0x40);
  2290. if (post_on_event)
  2291. blocking_notifier_call_chain(
  2292. &wcd939x->mbhc->notifier,
  2293. post_on_event,
  2294. &wcd939x->mbhc->wcd_mbhc);
  2295. }
  2296. if (is_dapm && post_dapm_on && wcd939x->mbhc)
  2297. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  2298. post_dapm_on,
  2299. &wcd939x->mbhc->wcd_mbhc);
  2300. break;
  2301. case MICB_DISABLE:
  2302. if (wcd939x->micb_ref[micb_index] > 0)
  2303. wcd939x->micb_ref[micb_index]--;
  2304. if (!wcd939x->dev_up) {
  2305. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2306. __func__, req);
  2307. ret = -ENODEV;
  2308. goto done;
  2309. }
  2310. if ((wcd939x->micb_ref[micb_index] == 0) &&
  2311. (wcd939x->pullup_ref[micb_index] > 0))
  2312. snd_soc_component_update_bits(component, micb_reg,
  2313. 0xC0, 0x80);
  2314. else if ((wcd939x->micb_ref[micb_index] == 0) &&
  2315. (wcd939x->pullup_ref[micb_index] == 0)) {
  2316. if (pre_off_event && wcd939x->mbhc)
  2317. blocking_notifier_call_chain(
  2318. &wcd939x->mbhc->notifier,
  2319. pre_off_event,
  2320. &wcd939x->mbhc->wcd_mbhc);
  2321. snd_soc_component_update_bits(component, micb_reg,
  2322. 0xC0, 0x00);
  2323. if (post_off_event && wcd939x->mbhc)
  2324. blocking_notifier_call_chain(
  2325. &wcd939x->mbhc->notifier,
  2326. post_off_event,
  2327. &wcd939x->mbhc->wcd_mbhc);
  2328. }
  2329. if (is_dapm && post_dapm_off && wcd939x->mbhc)
  2330. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  2331. post_dapm_off,
  2332. &wcd939x->mbhc->wcd_mbhc);
  2333. break;
  2334. };
  2335. dev_dbg(component->dev,
  2336. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  2337. __func__, micb_num, wcd939x->micb_ref[micb_index],
  2338. wcd939x->pullup_ref[micb_index]);
  2339. done:
  2340. mutex_unlock(&wcd939x->micb_lock);
  2341. return ret;
  2342. }
  2343. EXPORT_SYMBOL(wcd939x_micbias_control);
  2344. static int wcd939x_get_logical_addr(struct swr_device *swr_dev)
  2345. {
  2346. int ret = 0;
  2347. uint8_t devnum = 0;
  2348. int num_retry = NUM_ATTEMPTS;
  2349. do {
  2350. /* retry after 1ms */
  2351. usleep_range(1000, 1010);
  2352. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  2353. } while (ret && --num_retry);
  2354. if (ret)
  2355. dev_err_ratelimited(&swr_dev->dev,
  2356. "%s get devnum %d for dev addr %llx failed\n",
  2357. __func__, devnum, swr_dev->addr);
  2358. swr_dev->dev_num = devnum;
  2359. return 0;
  2360. }
  2361. static bool get_usbc_hs_status(struct snd_soc_component *component,
  2362. struct wcd_mbhc_config *mbhc_cfg)
  2363. {
  2364. if (mbhc_cfg->enable_usbc_analog) {
  2365. if (!(snd_soc_component_read(component, WCD939X_MBHC_MECH)
  2366. & 0x20))
  2367. return true;
  2368. }
  2369. return false;
  2370. }
  2371. int wcd939x_swr_dmic_register_notifier(struct snd_soc_component *component,
  2372. struct notifier_block *nblock,
  2373. bool enable)
  2374. {
  2375. struct wcd939x_priv *wcd939x_priv;
  2376. if(NULL == component) {
  2377. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2378. return -EINVAL;
  2379. }
  2380. wcd939x_priv = snd_soc_component_get_drvdata(component);
  2381. wcd939x_priv->notify_swr_dmic = enable;
  2382. if (enable)
  2383. return blocking_notifier_chain_register(&wcd939x_priv->notifier,
  2384. nblock);
  2385. else
  2386. return blocking_notifier_chain_unregister(
  2387. &wcd939x_priv->notifier, nblock);
  2388. }
  2389. EXPORT_SYMBOL(wcd939x_swr_dmic_register_notifier);
  2390. static int wcd939x_event_notify(struct notifier_block *block,
  2391. unsigned long val,
  2392. void *data)
  2393. {
  2394. u16 event = (val & 0xffff);
  2395. int ret = 0;
  2396. int rx_clk_type;
  2397. struct wcd939x_priv *wcd939x = dev_get_drvdata((struct device *)data);
  2398. struct snd_soc_component *component = wcd939x->component;
  2399. struct wcd_mbhc *mbhc;
  2400. switch (event) {
  2401. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2402. if (test_bit(WCD_ADC1, &wcd939x->status_mask)) {
  2403. snd_soc_component_update_bits(component,
  2404. REG_FIELD_VALUE(TX_CH2, HPF1_INIT, 0x00));
  2405. set_bit(WCD_ADC1_MODE, &wcd939x->status_mask);
  2406. clear_bit(WCD_ADC1, &wcd939x->status_mask);
  2407. }
  2408. if (test_bit(WCD_ADC2, &wcd939x->status_mask)) {
  2409. snd_soc_component_update_bits(component,
  2410. REG_FIELD_VALUE(TX_CH2, HPF2_INIT, 0x00));
  2411. set_bit(WCD_ADC2_MODE, &wcd939x->status_mask);
  2412. clear_bit(WCD_ADC2, &wcd939x->status_mask);
  2413. }
  2414. if (test_bit(WCD_ADC3, &wcd939x->status_mask)) {
  2415. snd_soc_component_update_bits(component,
  2416. REG_FIELD_VALUE(TX_CH4, HPF3_INIT, 0x00));
  2417. set_bit(WCD_ADC3_MODE, &wcd939x->status_mask);
  2418. clear_bit(WCD_ADC3, &wcd939x->status_mask);
  2419. }
  2420. if (test_bit(WCD_ADC4, &wcd939x->status_mask)) {
  2421. snd_soc_component_update_bits(component,
  2422. REG_FIELD_VALUE(TX_CH4, HPF4_INIT, 0x00));
  2423. set_bit(WCD_ADC4_MODE, &wcd939x->status_mask);
  2424. clear_bit(WCD_ADC4, &wcd939x->status_mask);
  2425. }
  2426. break;
  2427. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2428. snd_soc_component_update_bits(component,
  2429. REG_FIELD_VALUE(HPH, HPHL_ENABLE, 0x00));
  2430. snd_soc_component_update_bits(component,
  2431. REG_FIELD_VALUE(HPH, HPHR_ENABLE , 0x00));
  2432. snd_soc_component_update_bits(component,
  2433. REG_FIELD_VALUE(EAR, ENABLE, 0x00));
  2434. break;
  2435. case BOLERO_SLV_EVT_SSR_DOWN:
  2436. wcd939x->dev_up = false;
  2437. if(wcd939x->notify_swr_dmic)
  2438. blocking_notifier_call_chain(&wcd939x->notifier,
  2439. WCD939X_EVT_SSR_DOWN,
  2440. NULL);
  2441. wcd939x->mbhc->wcd_mbhc.deinit_in_progress = true;
  2442. mbhc = &wcd939x->mbhc->wcd_mbhc;
  2443. wcd939x->usbc_hs_status = get_usbc_hs_status(component,
  2444. mbhc->mbhc_cfg);
  2445. wcd939x_mbhc_ssr_down(wcd939x->mbhc, component);
  2446. wcd939x_reset_low(wcd939x->dev);
  2447. break;
  2448. case BOLERO_SLV_EVT_SSR_UP:
  2449. wcd939x_reset(wcd939x->dev);
  2450. /* allow reset to take effect */
  2451. usleep_range(10000, 10010);
  2452. wcd939x_get_logical_addr(wcd939x->tx_swr_dev);
  2453. wcd939x_get_logical_addr(wcd939x->rx_swr_dev);
  2454. wcd939x_init_reg(component);
  2455. regcache_mark_dirty(wcd939x->regmap);
  2456. regcache_sync(wcd939x->regmap);
  2457. /* Initialize MBHC module */
  2458. mbhc = &wcd939x->mbhc->wcd_mbhc;
  2459. ret = wcd939x_mbhc_post_ssr_init(wcd939x->mbhc, component);
  2460. if (ret) {
  2461. dev_err_ratelimited(component->dev, "%s: mbhc initialization failed\n",
  2462. __func__);
  2463. } else {
  2464. wcd939x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2465. }
  2466. wcd939x->mbhc->wcd_mbhc.deinit_in_progress = false;
  2467. wcd939x->dev_up = true;
  2468. if(wcd939x->notify_swr_dmic)
  2469. blocking_notifier_call_chain(&wcd939x->notifier,
  2470. WCD939X_EVT_SSR_UP,
  2471. NULL);
  2472. if (wcd939x->usbc_hs_status)
  2473. mdelay(500);
  2474. break;
  2475. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2476. snd_soc_component_update_bits(component,
  2477. WCD939X_TOP_CLK_CFG, 0x06,
  2478. ((val >> 0x10) << 0x01));
  2479. rx_clk_type = (val >> 0x10);
  2480. switch(rx_clk_type) {
  2481. case RX_CLK_12P288MHZ:
  2482. wcd939x->rx_clk_config = RX_CLK_12P288MHZ;
  2483. break;
  2484. case RX_CLK_11P2896MHZ:
  2485. wcd939x->rx_clk_config = RX_CLK_11P2896MHZ;
  2486. break;
  2487. default:
  2488. wcd939x->rx_clk_config = RX_CLK_9P6MHZ;
  2489. break;
  2490. }
  2491. dev_dbg(component->dev, "%s: rx clk config %d\n", __func__, wcd939x->rx_clk_config);
  2492. break;
  2493. default:
  2494. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2495. break;
  2496. }
  2497. return 0;
  2498. }
  2499. static int __wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2500. int event)
  2501. {
  2502. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2503. int micb_num;
  2504. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2505. __func__, w->name, event);
  2506. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2507. micb_num = MIC_BIAS_1;
  2508. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2509. micb_num = MIC_BIAS_2;
  2510. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2511. micb_num = MIC_BIAS_3;
  2512. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2513. micb_num = MIC_BIAS_4;
  2514. else
  2515. return -EINVAL;
  2516. switch (event) {
  2517. case SND_SOC_DAPM_PRE_PMU:
  2518. wcd939x_micbias_control(component, micb_num,
  2519. MICB_ENABLE, true);
  2520. break;
  2521. case SND_SOC_DAPM_POST_PMU:
  2522. /* 1 msec delay as per HW requirement */
  2523. usleep_range(1000, 1100);
  2524. break;
  2525. case SND_SOC_DAPM_POST_PMD:
  2526. wcd939x_micbias_control(component, micb_num,
  2527. MICB_DISABLE, true);
  2528. break;
  2529. };
  2530. return 0;
  2531. }
  2532. static int wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2533. struct snd_kcontrol *kcontrol,
  2534. int event)
  2535. {
  2536. return __wcd939x_codec_enable_micbias(w, event);
  2537. }
  2538. static int __wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2539. int event)
  2540. {
  2541. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2542. int micb_num;
  2543. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2544. __func__, w->name, event);
  2545. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2546. micb_num = MIC_BIAS_1;
  2547. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2548. micb_num = MIC_BIAS_2;
  2549. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2550. micb_num = MIC_BIAS_3;
  2551. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2552. micb_num = MIC_BIAS_4;
  2553. else
  2554. return -EINVAL;
  2555. switch (event) {
  2556. case SND_SOC_DAPM_PRE_PMU:
  2557. wcd939x_micbias_control(component, micb_num,
  2558. MICB_PULLUP_ENABLE, true);
  2559. break;
  2560. case SND_SOC_DAPM_POST_PMU:
  2561. /* 1 msec delay as per HW requirement */
  2562. usleep_range(1000, 1100);
  2563. break;
  2564. case SND_SOC_DAPM_POST_PMD:
  2565. wcd939x_micbias_control(component, micb_num,
  2566. MICB_PULLUP_DISABLE, true);
  2567. break;
  2568. };
  2569. return 0;
  2570. }
  2571. static int wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2572. struct snd_kcontrol *kcontrol,
  2573. int event)
  2574. {
  2575. return __wcd939x_codec_enable_micbias_pullup(w, event);
  2576. }
  2577. static int wcd939x_wakeup(void *handle, bool enable)
  2578. {
  2579. struct wcd939x_priv *priv;
  2580. int ret = 0;
  2581. if (!handle) {
  2582. pr_err_ratelimited("%s: NULL handle\n", __func__);
  2583. return -EINVAL;
  2584. }
  2585. priv = (struct wcd939x_priv *)handle;
  2586. if (!priv->tx_swr_dev) {
  2587. pr_err_ratelimited("%s: tx swr dev is NULL\n", __func__);
  2588. return -EINVAL;
  2589. }
  2590. mutex_lock(&priv->wakeup_lock);
  2591. if (enable)
  2592. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2593. else
  2594. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2595. mutex_unlock(&priv->wakeup_lock);
  2596. return ret;
  2597. }
  2598. static int wcd939x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2599. struct snd_kcontrol *kcontrol,
  2600. int event)
  2601. {
  2602. int ret = 0;
  2603. struct snd_soc_component *component =
  2604. snd_soc_dapm_to_component(w->dapm);
  2605. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2606. switch (event) {
  2607. case SND_SOC_DAPM_PRE_PMU:
  2608. wcd939x_wakeup(wcd939x, true);
  2609. ret = __wcd939x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2610. wcd939x_wakeup(wcd939x, false);
  2611. break;
  2612. case SND_SOC_DAPM_POST_PMD:
  2613. wcd939x_wakeup(wcd939x, true);
  2614. ret = __wcd939x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2615. wcd939x_wakeup(wcd939x, false);
  2616. break;
  2617. }
  2618. return ret;
  2619. }
  2620. static int wcd939x_enable_micbias(struct wcd939x_priv *wcd939x,
  2621. int micb_num, int req)
  2622. {
  2623. int micb_index = micb_num - 1;
  2624. u16 micb_reg;
  2625. if (NULL == wcd939x) {
  2626. pr_err_ratelimited("%s: wcd939x private data is NULL\n", __func__);
  2627. return -EINVAL;
  2628. }
  2629. switch (micb_num) {
  2630. case MIC_BIAS_1:
  2631. micb_reg = WCD939X_MICB1;
  2632. break;
  2633. case MIC_BIAS_2:
  2634. micb_reg = WCD939X_MICB2;
  2635. break;
  2636. case MIC_BIAS_3:
  2637. micb_reg = WCD939X_MICB3;
  2638. break;
  2639. case MIC_BIAS_4:
  2640. micb_reg = WCD939X_MICB4;
  2641. break;
  2642. default:
  2643. pr_err_ratelimited("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2644. return -EINVAL;
  2645. };
  2646. pr_debug("%s: req: %d micb_num: %d micb_ref: %d pullup_ref: %d\n",
  2647. __func__, req, micb_num, wcd939x->micb_ref[micb_index],
  2648. wcd939x->pullup_ref[micb_index]);
  2649. mutex_lock(&wcd939x->micb_lock);
  2650. switch (req) {
  2651. case MICB_ENABLE:
  2652. wcd939x->micb_ref[micb_index]++;
  2653. if (wcd939x->micb_ref[micb_index] == 1) {
  2654. regmap_update_bits(wcd939x->regmap,
  2655. WCD939X_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2656. regmap_update_bits(wcd939x->regmap,
  2657. WCD939X_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2658. regmap_update_bits(wcd939x->regmap,
  2659. WCD939X_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2660. regmap_update_bits(wcd939x->regmap,
  2661. WCD939X_TEST_CTL_2, 0x01, 0x01);
  2662. regmap_update_bits(wcd939x->regmap,
  2663. WCD939X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2664. regmap_update_bits(wcd939x->regmap,
  2665. WCD939X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2666. regmap_update_bits(wcd939x->regmap,
  2667. WCD939X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2668. regmap_update_bits(wcd939x->regmap,
  2669. micb_reg, 0xC0, 0x40);
  2670. regmap_update_bits(wcd939x->regmap, micb_reg, 0x3F, 0x10);
  2671. }
  2672. break;
  2673. case MICB_PULLUP_ENABLE:
  2674. wcd939x->pullup_ref[micb_index]++;
  2675. if ((wcd939x->pullup_ref[micb_index] == 1) &&
  2676. (wcd939x->micb_ref[micb_index] == 0))
  2677. regmap_update_bits(wcd939x->regmap, micb_reg,
  2678. 0xC0, 0x80);
  2679. break;
  2680. case MICB_PULLUP_DISABLE:
  2681. if (wcd939x->pullup_ref[micb_index] > 0)
  2682. wcd939x->pullup_ref[micb_index]--;
  2683. if ((wcd939x->pullup_ref[micb_index] == 0) &&
  2684. (wcd939x->micb_ref[micb_index] == 0))
  2685. regmap_update_bits(wcd939x->regmap, micb_reg,
  2686. 0xC0, 0x00);
  2687. break;
  2688. case MICB_DISABLE:
  2689. if (wcd939x->micb_ref[micb_index] > 0)
  2690. wcd939x->micb_ref[micb_index]--;
  2691. if ((wcd939x->micb_ref[micb_index] == 0) &&
  2692. (wcd939x->pullup_ref[micb_index] > 0))
  2693. regmap_update_bits(wcd939x->regmap, micb_reg,
  2694. 0xC0, 0x80);
  2695. else if ((wcd939x->micb_ref[micb_index] == 0) &&
  2696. (wcd939x->pullup_ref[micb_index] == 0))
  2697. regmap_update_bits(wcd939x->regmap, micb_reg,
  2698. 0xC0, 0x00);
  2699. break;
  2700. };
  2701. mutex_unlock(&wcd939x->micb_lock);
  2702. return 0;
  2703. }
  2704. int wcd939x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2705. int event, int micb_num)
  2706. {
  2707. struct wcd939x_priv *wcd939x_priv = NULL;
  2708. int ret = 0;
  2709. int micb_index = micb_num - 1;
  2710. if(NULL == component) {
  2711. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2712. return -EINVAL;
  2713. }
  2714. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2715. pr_err_ratelimited("%s: invalid event: %d\n", __func__, event);
  2716. return -EINVAL;
  2717. }
  2718. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2719. pr_err_ratelimited("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2720. return -EINVAL;
  2721. }
  2722. wcd939x_priv = snd_soc_component_get_drvdata(component);
  2723. if (!wcd939x_priv->dev_up) {
  2724. if ((wcd939x_priv->pullup_ref[micb_index] > 0) &&
  2725. (event == SND_SOC_DAPM_POST_PMD)) {
  2726. wcd939x_priv->pullup_ref[micb_index]--;
  2727. ret = -ENODEV;
  2728. goto done;
  2729. }
  2730. }
  2731. switch (event) {
  2732. case SND_SOC_DAPM_PRE_PMU:
  2733. wcd939x_wakeup(wcd939x_priv, true);
  2734. wcd939x_enable_micbias(wcd939x_priv, micb_num, MICB_PULLUP_ENABLE);
  2735. wcd939x_wakeup(wcd939x_priv, false);
  2736. break;
  2737. case SND_SOC_DAPM_POST_PMD:
  2738. wcd939x_wakeup(wcd939x_priv, true);
  2739. wcd939x_enable_micbias(wcd939x_priv, micb_num, MICB_PULLUP_DISABLE);
  2740. wcd939x_wakeup(wcd939x_priv, false);
  2741. break;
  2742. }
  2743. done:
  2744. return ret;
  2745. }
  2746. EXPORT_SYMBOL(wcd939x_codec_force_enable_micbias_v2);
  2747. static inline int wcd939x_tx_path_get(const char *wname,
  2748. unsigned int *path_num)
  2749. {
  2750. int ret = 0;
  2751. char *widget_name = NULL;
  2752. char *w_name = NULL;
  2753. char *path_num_char = NULL;
  2754. char *path_name = NULL;
  2755. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2756. if (!widget_name)
  2757. return -EINVAL;
  2758. w_name = widget_name;
  2759. path_name = strsep(&widget_name, " ");
  2760. if (!path_name) {
  2761. pr_err_ratelimited("%s: Invalid widget name = %s\n",
  2762. __func__, widget_name);
  2763. ret = -EINVAL;
  2764. goto err;
  2765. }
  2766. path_num_char = strpbrk(path_name, "0123");
  2767. if (!path_num_char) {
  2768. pr_err_ratelimited("%s: tx path index not found\n",
  2769. __func__);
  2770. ret = -EINVAL;
  2771. goto err;
  2772. }
  2773. ret = kstrtouint(path_num_char, 10, path_num);
  2774. if (ret < 0)
  2775. pr_err_ratelimited("%s: Invalid tx path = %s\n",
  2776. __func__, w_name);
  2777. err:
  2778. kfree(w_name);
  2779. return ret;
  2780. }
  2781. static int wcd939x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2782. struct snd_ctl_elem_value *ucontrol)
  2783. {
  2784. struct snd_soc_component *component =
  2785. snd_soc_kcontrol_component(kcontrol);
  2786. struct wcd939x_priv *wcd939x = NULL;
  2787. int ret = 0;
  2788. unsigned int path = 0;
  2789. if (!component)
  2790. return -EINVAL;
  2791. wcd939x = snd_soc_component_get_drvdata(component);
  2792. if (!wcd939x)
  2793. return -EINVAL;
  2794. ret = wcd939x_tx_path_get(kcontrol->id.name, &path);
  2795. if (ret < 0)
  2796. return ret;
  2797. ucontrol->value.integer.value[0] = wcd939x->tx_mode[path];
  2798. return 0;
  2799. }
  2800. static int wcd939x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2801. struct snd_ctl_elem_value *ucontrol)
  2802. {
  2803. struct snd_soc_component *component =
  2804. snd_soc_kcontrol_component(kcontrol);
  2805. struct wcd939x_priv *wcd939x = NULL;
  2806. u32 mode_val;
  2807. unsigned int path = 0;
  2808. int ret = 0;
  2809. if (!component)
  2810. return -EINVAL;
  2811. wcd939x = snd_soc_component_get_drvdata(component);
  2812. if (!wcd939x)
  2813. return -EINVAL;
  2814. ret = wcd939x_tx_path_get(kcontrol->id.name, &path);
  2815. if (ret)
  2816. return ret;
  2817. mode_val = ucontrol->value.enumerated.item[0];
  2818. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2819. wcd939x->tx_mode[path] = mode_val;
  2820. return 0;
  2821. }
  2822. static int wcd939x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2823. struct snd_ctl_elem_value *ucontrol)
  2824. {
  2825. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2826. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2827. ucontrol->value.integer.value[0] = wcd939x->hph_mode;
  2828. return 0;
  2829. }
  2830. static int wcd939x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2831. struct snd_ctl_elem_value *ucontrol)
  2832. {
  2833. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2834. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2835. u32 mode_val;
  2836. mode_val = ucontrol->value.enumerated.item[0];
  2837. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2838. if (wcd939x->variant == WCD9390) {
  2839. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2840. dev_info_ratelimited(component->dev,
  2841. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2842. __func__);
  2843. mode_val = CLS_H_ULP;
  2844. }
  2845. }
  2846. if (mode_val == CLS_H_NORMAL) {
  2847. dev_info_ratelimited(component->dev,
  2848. "%s:Invalid HPH Mode, default to class_AB\n",
  2849. __func__);
  2850. mode_val = CLS_H_ULP;
  2851. }
  2852. wcd939x->hph_mode = mode_val;
  2853. return 0;
  2854. }
  2855. static int wcd939x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2856. struct snd_ctl_elem_value *ucontrol)
  2857. {
  2858. u8 ear_pa_gain = 0;
  2859. struct snd_soc_component *component =
  2860. snd_soc_kcontrol_component(kcontrol);
  2861. ear_pa_gain = snd_soc_component_read(component,
  2862. WCD939X_EAR_COMPANDER_CTL);
  2863. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2864. ucontrol->value.integer.value[0] = ear_pa_gain;
  2865. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2866. ear_pa_gain);
  2867. return 0;
  2868. }
  2869. static int wcd939x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2870. struct snd_ctl_elem_value *ucontrol)
  2871. {
  2872. u8 ear_pa_gain = 0;
  2873. struct snd_soc_component *component =
  2874. snd_soc_kcontrol_component(kcontrol);
  2875. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2876. __func__, ucontrol->value.integer.value[0]);
  2877. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2878. snd_soc_component_update_bits(component,
  2879. WCD939X_EAR_COMPANDER_CTL,
  2880. 0x7C, ear_pa_gain);
  2881. return 0;
  2882. }
  2883. /* wcd939x_codec_get_dev_num - returns swr device number
  2884. * @component: Codec instance
  2885. *
  2886. * Return: swr device number on success or negative error
  2887. * code on failure.
  2888. */
  2889. int wcd939x_codec_get_dev_num(struct snd_soc_component *component)
  2890. {
  2891. struct wcd939x_priv *wcd939x;
  2892. if (!component)
  2893. return -EINVAL;
  2894. wcd939x = snd_soc_component_get_drvdata(component);
  2895. if (!wcd939x || !wcd939x->rx_swr_dev) {
  2896. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2897. return -EINVAL;
  2898. }
  2899. return wcd939x->rx_swr_dev->dev_num;
  2900. }
  2901. EXPORT_SYMBOL(wcd939x_codec_get_dev_num);
  2902. static int wcd939x_get_compander(struct snd_kcontrol *kcontrol,
  2903. struct snd_ctl_elem_value *ucontrol)
  2904. {
  2905. struct snd_soc_component *component =
  2906. snd_soc_kcontrol_component(kcontrol);
  2907. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2908. bool hphr;
  2909. struct soc_multi_mixer_control *mc;
  2910. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2911. hphr = mc->shift;
  2912. ucontrol->value.integer.value[0] = hphr ? wcd939x->comp2_enable :
  2913. wcd939x->comp1_enable;
  2914. return 0;
  2915. }
  2916. static int wcd939x_set_compander(struct snd_kcontrol *kcontrol,
  2917. struct snd_ctl_elem_value *ucontrol)
  2918. {
  2919. struct snd_soc_component *component =
  2920. snd_soc_kcontrol_component(kcontrol);
  2921. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2922. int value = ucontrol->value.integer.value[0];
  2923. bool hphr;
  2924. struct soc_multi_mixer_control *mc;
  2925. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2926. hphr = mc->shift;
  2927. if (hphr)
  2928. wcd939x->comp2_enable = value;
  2929. else
  2930. wcd939x->comp1_enable = value;
  2931. return 0;
  2932. }
  2933. static int wcd939x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2934. struct snd_kcontrol *kcontrol,
  2935. int event)
  2936. {
  2937. struct snd_soc_component *component =
  2938. snd_soc_dapm_to_component(w->dapm);
  2939. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2940. struct wcd939x_pdata *pdata = NULL;
  2941. int ret = 0;
  2942. pdata = dev_get_platdata(wcd939x->dev);
  2943. if (!pdata) {
  2944. dev_err_ratelimited(component->dev, "%s: pdata is NULL\n", __func__);
  2945. return -EINVAL;
  2946. }
  2947. if (!msm_cdc_is_ondemand_supply(wcd939x->dev,
  2948. wcd939x->supplies,
  2949. pdata->regulator,
  2950. pdata->num_supplies,
  2951. "cdc-vdd-buck"))
  2952. return 0;
  2953. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2954. w->name, event);
  2955. switch (event) {
  2956. case SND_SOC_DAPM_PRE_PMU:
  2957. if (test_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask)) {
  2958. dev_dbg(component->dev,
  2959. "%s: buck already in enabled state\n",
  2960. __func__);
  2961. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2962. return 0;
  2963. }
  2964. ret = msm_cdc_enable_ondemand_supply(wcd939x->dev,
  2965. wcd939x->supplies,
  2966. pdata->regulator,
  2967. pdata->num_supplies,
  2968. "cdc-vdd-buck");
  2969. if (ret == -EINVAL) {
  2970. dev_err_ratelimited(component->dev, "%s: vdd buck is not enabled\n",
  2971. __func__);
  2972. return ret;
  2973. }
  2974. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2975. /*
  2976. * 200us sleep is required after LDO is enabled as per
  2977. * HW requirement
  2978. */
  2979. usleep_range(200, 250);
  2980. break;
  2981. case SND_SOC_DAPM_POST_PMD:
  2982. set_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2983. break;
  2984. }
  2985. return 0;
  2986. }
  2987. static int wcd939x_ldoh_get(struct snd_kcontrol *kcontrol,
  2988. struct snd_ctl_elem_value *ucontrol)
  2989. {
  2990. struct snd_soc_component *component =
  2991. snd_soc_kcontrol_component(kcontrol);
  2992. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2993. ucontrol->value.integer.value[0] = wcd939x->ldoh;
  2994. return 0;
  2995. }
  2996. static int wcd939x_ldoh_put(struct snd_kcontrol *kcontrol,
  2997. struct snd_ctl_elem_value *ucontrol)
  2998. {
  2999. struct snd_soc_component *component =
  3000. snd_soc_kcontrol_component(kcontrol);
  3001. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3002. wcd939x->ldoh = ucontrol->value.integer.value[0];
  3003. return 0;
  3004. }
  3005. const char * const tx_master_ch_text[] = {
  3006. "ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
  3007. "SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
  3008. "SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
  3009. "SWRM_TX3_CH4", "SWRM_PCM_IN",
  3010. };
  3011. const struct soc_enum tx_master_ch_enum =
  3012. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  3013. tx_master_ch_text);
  3014. static void wcd939x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  3015. {
  3016. u8 ch_type = 0;
  3017. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  3018. ch_type = ADC1;
  3019. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  3020. ch_type = ADC2;
  3021. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  3022. ch_type = ADC3;
  3023. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  3024. ch_type = ADC4;
  3025. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  3026. ch_type = DMIC0;
  3027. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  3028. ch_type = DMIC1;
  3029. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  3030. ch_type = MBHC;
  3031. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  3032. ch_type = DMIC2;
  3033. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  3034. ch_type = DMIC3;
  3035. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  3036. ch_type = DMIC4;
  3037. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  3038. ch_type = DMIC5;
  3039. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  3040. ch_type = DMIC6;
  3041. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  3042. ch_type = DMIC7;
  3043. else
  3044. pr_err_ratelimited("%s: port name: %s is not listed\n", __func__, wname);
  3045. if (ch_type)
  3046. *ch_idx = wcd939x_slave_get_slave_ch_val(ch_type);
  3047. else
  3048. *ch_idx = -EINVAL;
  3049. }
  3050. static int wcd939x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  3051. struct snd_ctl_elem_value *ucontrol)
  3052. {
  3053. struct snd_soc_component *component =
  3054. snd_soc_kcontrol_component(kcontrol);
  3055. struct wcd939x_priv *wcd939x = NULL;
  3056. int slave_ch_idx = -EINVAL;
  3057. if (component == NULL)
  3058. return -EINVAL;
  3059. wcd939x = snd_soc_component_get_drvdata(component);
  3060. if (wcd939x == NULL)
  3061. return -EINVAL;
  3062. wcd939x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  3063. if (slave_ch_idx < 0 || slave_ch_idx >= WCD939X_MAX_SLAVE_CH_TYPES)
  3064. return -EINVAL;
  3065. ucontrol->value.integer.value[0] = wcd939x_slave_get_master_ch_val(
  3066. wcd939x->tx_master_ch_map[slave_ch_idx]);
  3067. return 0;
  3068. }
  3069. static int wcd939x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  3070. struct snd_ctl_elem_value *ucontrol)
  3071. {
  3072. struct snd_soc_component *component =
  3073. snd_soc_kcontrol_component(kcontrol);
  3074. struct wcd939x_priv *wcd939x = NULL;
  3075. int slave_ch_idx = -EINVAL, idx = 0;
  3076. if (component == NULL)
  3077. return -EINVAL;
  3078. wcd939x = snd_soc_component_get_drvdata(component);
  3079. if (wcd939x == NULL)
  3080. return -EINVAL;
  3081. wcd939x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  3082. if (slave_ch_idx < 0 || slave_ch_idx >= WCD939X_MAX_SLAVE_CH_TYPES)
  3083. return -EINVAL;
  3084. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  3085. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  3086. __func__, ucontrol->value.enumerated.item[0]);
  3087. idx = ucontrol->value.enumerated.item[0];
  3088. if (idx < 0 || idx >= ARRAY_SIZE(swr_master_ch_map))
  3089. return -EINVAL;
  3090. wcd939x->tx_master_ch_map[slave_ch_idx] = wcd939x_slave_get_master_ch(idx);
  3091. return 0;
  3092. }
  3093. static int wcd939x_bcs_get(struct snd_kcontrol *kcontrol,
  3094. struct snd_ctl_elem_value *ucontrol)
  3095. {
  3096. struct snd_soc_component *component =
  3097. snd_soc_kcontrol_component(kcontrol);
  3098. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3099. ucontrol->value.integer.value[0] = wcd939x->bcs_dis;
  3100. return 0;
  3101. }
  3102. static int wcd939x_bcs_put(struct snd_kcontrol *kcontrol,
  3103. struct snd_ctl_elem_value *ucontrol)
  3104. {
  3105. struct snd_soc_component *component =
  3106. snd_soc_kcontrol_component(kcontrol);
  3107. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3108. wcd939x->bcs_dis = ucontrol->value.integer.value[0];
  3109. return 0;
  3110. }
  3111. static const char * const tx_mode_mux_text_wcd9390[] = {
  3112. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  3113. };
  3114. static const struct soc_enum tx_mode_mux_enum_wcd9390 =
  3115. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9390),
  3116. tx_mode_mux_text_wcd9390);
  3117. static const char * const tx_mode_mux_text[] = {
  3118. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  3119. "ADC_ULP1", "ADC_ULP2",
  3120. };
  3121. static const struct soc_enum tx_mode_mux_enum =
  3122. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  3123. tx_mode_mux_text);
  3124. static const char * const rx_hph_mode_mux_text_wcd9390[] = {
  3125. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  3126. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  3127. "CLS_AB_LOHIFI",
  3128. };
  3129. static const char * const wcd939x_ear_pa_gain_text[] = {
  3130. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  3131. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  3132. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  3133. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  3134. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  3135. };
  3136. static const struct soc_enum rx_hph_mode_mux_enum_wcd9390 =
  3137. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9390),
  3138. rx_hph_mode_mux_text_wcd9390);
  3139. static SOC_ENUM_SINGLE_EXT_DECL(wcd939x_ear_pa_gain_enum,
  3140. wcd939x_ear_pa_gain_text);
  3141. static const char * const rx_hph_mode_mux_text[] = {
  3142. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  3143. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  3144. };
  3145. static const struct soc_enum rx_hph_mode_mux_enum =
  3146. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  3147. rx_hph_mode_mux_text);
  3148. static const struct snd_kcontrol_new wcd9390_snd_controls[] = {
  3149. SOC_ENUM_EXT("EAR PA GAIN", wcd939x_ear_pa_gain_enum,
  3150. wcd939x_ear_pa_gain_get, wcd939x_ear_pa_gain_put),
  3151. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9390,
  3152. wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
  3153. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9390,
  3154. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3155. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9390,
  3156. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3157. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9390,
  3158. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3159. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9390,
  3160. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3161. };
  3162. static const struct snd_kcontrol_new wcd9395_snd_controls[] = {
  3163. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  3164. wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
  3165. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  3166. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3167. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  3168. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3169. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  3170. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3171. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  3172. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3173. };
  3174. static const struct snd_kcontrol_new wcd939x_snd_controls[] = {
  3175. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  3176. wcd939x_get_compander, wcd939x_set_compander),
  3177. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  3178. wcd939x_get_compander, wcd939x_set_compander),
  3179. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  3180. wcd939x_ldoh_get, wcd939x_ldoh_put),
  3181. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  3182. wcd939x_bcs_get, wcd939x_bcs_put),
  3183. SOC_SINGLE_TLV("HPHL Volume", WCD939X_PA_GAIN_CTL_L, 0, 0x18, 0, hph_analog_gain),
  3184. SOC_SINGLE_TLV("HPHR Volume", WCD939X_PA_GAIN_CTL_R, 0, 0x18, 0, hph_analog_gain),
  3185. SOC_SINGLE_TLV("ADC1 Volume", WCD939X_TX_CH1, 0, 20, 0,
  3186. analog_gain),
  3187. SOC_SINGLE_TLV("ADC2 Volume", WCD939X_TX_CH2, 0, 20, 0,
  3188. analog_gain),
  3189. SOC_SINGLE_TLV("ADC3 Volume", WCD939X_TX_CH3, 0, 20, 0,
  3190. analog_gain),
  3191. SOC_SINGLE_TLV("ADC4 Volume", WCD939X_TX_CH4, 0, 20, 0,
  3192. analog_gain),
  3193. SOC_SINGLE_EXT("HPHL Compander", SND_SOC_NOPM, WCD939X_HPHL, 1, 0,
  3194. wcd939x_hph_compander_get, wcd939x_hph_compander_put),
  3195. SOC_SINGLE_EXT("HPHR Compander", SND_SOC_NOPM, WCD939X_HPHR, 1, 0,
  3196. wcd939x_hph_compander_get, wcd939x_hph_compander_put),
  3197. SOC_SINGLE_EXT("HPHL XTALK", SND_SOC_NOPM, WCD939X_HPHL, 1, 0,
  3198. wcd939x_hph_xtalk_get, wcd939x_hph_xtalk_put),
  3199. SOC_SINGLE_EXT("HPHR XTALK", SND_SOC_NOPM, WCD939X_HPHR, 1, 0,
  3200. wcd939x_hph_xtalk_get, wcd939x_hph_xtalk_put),
  3201. SOC_SINGLE_EXT("HPH PCM Enable", SND_SOC_NOPM, 0, 1, 0,
  3202. wcd939x_hph_pcm_enable_get, wcd939x_hph_pcm_enable_put),
  3203. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  3204. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3205. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  3206. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3207. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  3208. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3209. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  3210. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3211. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  3212. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3213. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  3214. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3215. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  3216. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3217. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  3218. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3219. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  3220. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3221. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  3222. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3223. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  3224. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3225. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  3226. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3227. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  3228. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3229. };
  3230. static const struct snd_kcontrol_new adc1_switch[] = {
  3231. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3232. };
  3233. static const struct snd_kcontrol_new adc2_switch[] = {
  3234. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3235. };
  3236. static const struct snd_kcontrol_new adc3_switch[] = {
  3237. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3238. };
  3239. static const struct snd_kcontrol_new adc4_switch[] = {
  3240. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3241. };
  3242. static const struct snd_kcontrol_new amic1_switch[] = {
  3243. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3244. };
  3245. static const struct snd_kcontrol_new amic2_switch[] = {
  3246. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3247. };
  3248. static const struct snd_kcontrol_new amic3_switch[] = {
  3249. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3250. };
  3251. static const struct snd_kcontrol_new amic4_switch[] = {
  3252. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3253. };
  3254. static const struct snd_kcontrol_new amic5_switch[] = {
  3255. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3256. };
  3257. static const struct snd_kcontrol_new va_amic1_switch[] = {
  3258. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3259. };
  3260. static const struct snd_kcontrol_new va_amic2_switch[] = {
  3261. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3262. };
  3263. static const struct snd_kcontrol_new va_amic3_switch[] = {
  3264. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3265. };
  3266. static const struct snd_kcontrol_new va_amic4_switch[] = {
  3267. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3268. };
  3269. static const struct snd_kcontrol_new va_amic5_switch[] = {
  3270. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3271. };
  3272. static const struct snd_kcontrol_new dmic1_switch[] = {
  3273. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3274. };
  3275. static const struct snd_kcontrol_new dmic2_switch[] = {
  3276. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3277. };
  3278. static const struct snd_kcontrol_new dmic3_switch[] = {
  3279. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3280. };
  3281. static const struct snd_kcontrol_new dmic4_switch[] = {
  3282. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3283. };
  3284. static const struct snd_kcontrol_new dmic5_switch[] = {
  3285. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3286. };
  3287. static const struct snd_kcontrol_new dmic6_switch[] = {
  3288. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3289. };
  3290. static const struct snd_kcontrol_new dmic7_switch[] = {
  3291. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3292. };
  3293. static const struct snd_kcontrol_new dmic8_switch[] = {
  3294. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3295. };
  3296. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  3297. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3298. };
  3299. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  3300. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3301. };
  3302. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  3303. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3304. };
  3305. static const char * const adc1_mux_text[] = {
  3306. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4", "CH1_AMIC5"
  3307. };
  3308. static const struct soc_enum adc1_enum =
  3309. SOC_ENUM_SINGLE(WCD939X_TX_CH12_MUX, WCD939X_TX_CH12_MUX_CH1_SEL_SHIFT,
  3310. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  3311. static const struct snd_kcontrol_new tx_adc1_mux =
  3312. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  3313. static const char * const adc2_mux_text[] = {
  3314. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4", "CH2_AMIC5"
  3315. };
  3316. static const struct soc_enum adc2_enum =
  3317. SOC_ENUM_SINGLE(WCD939X_TX_CH12_MUX, WCD939X_TX_CH12_MUX_CH2_SEL_SHIFT,
  3318. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  3319. static const struct snd_kcontrol_new tx_adc2_mux =
  3320. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  3321. static const char * const adc3_mux_text[] = {
  3322. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4", "CH3_AMIC5"
  3323. };
  3324. static const struct soc_enum adc3_enum =
  3325. SOC_ENUM_SINGLE(WCD939X_TX_CH34_MUX, WCD939X_TX_CH34_MUX_CH3_SEL_SHIFT,
  3326. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  3327. static const struct snd_kcontrol_new tx_adc3_mux =
  3328. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  3329. static const char * const adc4_mux_text[] = {
  3330. "CH4_AMIC_DISABLE", "CH4_AMIC1", "CH4_AMIC3", "CH4_AMIC4", "CH4_AMIC5"
  3331. };
  3332. static const struct soc_enum adc4_enum =
  3333. SOC_ENUM_SINGLE(WCD939X_TX_CH34_MUX, WCD939X_TX_CH34_MUX_CH4_SEL_SHIFT,
  3334. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  3335. static const struct snd_kcontrol_new tx_adc4_mux =
  3336. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  3337. static const char * const rdac3_mux_text[] = {
  3338. "RX3", "RX1"
  3339. };
  3340. static const struct soc_enum rdac3_enum =
  3341. SOC_ENUM_SINGLE(WCD939X_CDC_EAR_PATH_CTL, 0,
  3342. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  3343. static const struct snd_kcontrol_new rx_rdac3_mux =
  3344. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  3345. static const char * const rx1_mux_text[] = {
  3346. "ZERO", "RX1 MUX"
  3347. };
  3348. static const struct soc_enum rx1_enum =
  3349. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 0, rx1_mux_text);
  3350. static const struct snd_kcontrol_new rx1_mux =
  3351. SOC_DAPM_ENUM("RX1 MUX Mux", rx1_enum);
  3352. static const char * const rx2_mux_text[] = {
  3353. "ZERO", "RX2 MUX"
  3354. };
  3355. static const struct soc_enum rx2_enum =
  3356. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 0, rx2_mux_text);
  3357. static const struct snd_kcontrol_new rx2_mux =
  3358. SOC_DAPM_ENUM("RX2 MUX Mux", rx2_enum);
  3359. static const char * const rx3_mux_text[] = {
  3360. "ZERO", "RX3 MUX"
  3361. };
  3362. static const struct soc_enum rx3_enum =
  3363. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 0, rx3_mux_text);
  3364. static const struct snd_kcontrol_new rx3_mux =
  3365. SOC_DAPM_ENUM("RX3 MUX Mux", rx3_enum);
  3366. static const struct snd_soc_dapm_widget wcd939x_dapm_widgets[] = {
  3367. /*input widgets*/
  3368. SND_SOC_DAPM_INPUT("AMIC1"),
  3369. SND_SOC_DAPM_INPUT("AMIC2"),
  3370. SND_SOC_DAPM_INPUT("AMIC3"),
  3371. SND_SOC_DAPM_INPUT("AMIC4"),
  3372. SND_SOC_DAPM_INPUT("AMIC5"),
  3373. SND_SOC_DAPM_INPUT("VA AMIC1"),
  3374. SND_SOC_DAPM_INPUT("VA AMIC2"),
  3375. SND_SOC_DAPM_INPUT("VA AMIC3"),
  3376. SND_SOC_DAPM_INPUT("VA AMIC4"),
  3377. SND_SOC_DAPM_INPUT("VA AMIC5"),
  3378. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  3379. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  3380. SND_SOC_DAPM_INPUT("IN3_EAR"),
  3381. /*
  3382. * These dummy widgets are null connected to WCD939x dapm input and
  3383. * output widgets which are not actual path endpoints. This ensures
  3384. * dapm doesnt set these dapm input and output widgets as endpoints.
  3385. */
  3386. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  3387. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  3388. /*tx widgets*/
  3389. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  3390. wcd939x_codec_enable_adc,
  3391. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3392. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  3393. wcd939x_codec_enable_adc,
  3394. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3395. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  3396. wcd939x_codec_enable_adc,
  3397. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3398. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  3399. wcd939x_codec_enable_adc,
  3400. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3401. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  3402. wcd939x_codec_enable_dmic,
  3403. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3404. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  3405. wcd939x_codec_enable_dmic,
  3406. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3407. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  3408. wcd939x_codec_enable_dmic,
  3409. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3410. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  3411. wcd939x_codec_enable_dmic,
  3412. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3413. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  3414. wcd939x_codec_enable_dmic,
  3415. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3416. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  3417. wcd939x_codec_enable_dmic,
  3418. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3419. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  3420. wcd939x_codec_enable_dmic,
  3421. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3422. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  3423. wcd939x_codec_enable_dmic,
  3424. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3425. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  3426. NULL, 0, wcd939x_enable_req,
  3427. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3428. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  3429. NULL, 0, wcd939x_enable_req,
  3430. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3431. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  3432. NULL, 0, wcd939x_enable_req,
  3433. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3434. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  3435. NULL, 0, wcd939x_enable_req,
  3436. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3437. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3438. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3439. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3440. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3441. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3442. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3443. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3444. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3445. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3446. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3447. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3448. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3449. SND_SOC_DAPM_MIXER_E("AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3450. amic5_switch, ARRAY_SIZE(amic5_switch), NULL,
  3451. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3452. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3453. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3454. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3455. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3456. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3457. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3458. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3459. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3460. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3461. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3462. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3463. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3464. SND_SOC_DAPM_MIXER_E("VA_AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3465. va_amic5_switch, ARRAY_SIZE(va_amic5_switch), NULL,
  3466. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3467. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  3468. &tx_adc1_mux),
  3469. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  3470. &tx_adc2_mux),
  3471. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  3472. &tx_adc3_mux),
  3473. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  3474. &tx_adc4_mux),
  3475. /*tx mixers*/
  3476. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  3477. adc1_switch, ARRAY_SIZE(adc1_switch),
  3478. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3479. SND_SOC_DAPM_POST_PMD),
  3480. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  3481. adc2_switch, ARRAY_SIZE(adc2_switch),
  3482. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3483. SND_SOC_DAPM_POST_PMD),
  3484. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  3485. ARRAY_SIZE(adc3_switch), wcd939x_tx_swr_ctrl,
  3486. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3487. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  3488. ARRAY_SIZE(adc4_switch), wcd939x_tx_swr_ctrl,
  3489. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3490. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3491. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3492. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3493. SND_SOC_DAPM_POST_PMD),
  3494. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3495. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3496. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3497. SND_SOC_DAPM_POST_PMD),
  3498. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3499. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3500. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3501. SND_SOC_DAPM_POST_PMD),
  3502. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3503. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3504. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3505. SND_SOC_DAPM_POST_PMD),
  3506. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3507. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3508. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3509. SND_SOC_DAPM_POST_PMD),
  3510. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3511. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3512. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3513. SND_SOC_DAPM_POST_PMD),
  3514. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  3515. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  3516. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3517. SND_SOC_DAPM_POST_PMD),
  3518. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  3519. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  3520. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3521. SND_SOC_DAPM_POST_PMD),
  3522. /* micbias widgets*/
  3523. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3524. wcd939x_codec_enable_micbias,
  3525. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3526. SND_SOC_DAPM_POST_PMD),
  3527. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3528. wcd939x_codec_enable_micbias,
  3529. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3530. SND_SOC_DAPM_POST_PMD),
  3531. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3532. wcd939x_codec_enable_micbias,
  3533. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3534. SND_SOC_DAPM_POST_PMD),
  3535. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3536. wcd939x_codec_enable_micbias,
  3537. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3538. SND_SOC_DAPM_POST_PMD),
  3539. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  3540. wcd939x_codec_force_enable_micbias,
  3541. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3542. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  3543. wcd939x_codec_force_enable_micbias,
  3544. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3545. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  3546. wcd939x_codec_force_enable_micbias,
  3547. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3548. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  3549. wcd939x_codec_force_enable_micbias,
  3550. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3551. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3552. wcd939x_codec_enable_vdd_buck,
  3553. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3554. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3555. wcd939x_enable_clsh,
  3556. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3557. SND_SOC_DAPM_SUPPLY_S("CLS_H_DUMMY", 1, SND_SOC_NOPM, 0, 0,
  3558. wcd939x_clsh_dummy, SND_SOC_DAPM_POST_PMD),
  3559. /*rx widgets*/
  3560. SND_SOC_DAPM_PGA_E("EAR PGA", WCD939X_EAR, 7, 0, NULL, 0,
  3561. wcd939x_codec_enable_ear_pa,
  3562. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3563. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3564. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD939X_HPH, 7, 0, NULL, 0,
  3565. wcd939x_codec_enable_hphl_pa,
  3566. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3567. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3568. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD939X_HPH, 6, 0, NULL, 0,
  3569. wcd939x_codec_enable_hphr_pa,
  3570. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3571. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3572. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3573. wcd939x_codec_hphl_dac_event,
  3574. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3575. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3576. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3577. wcd939x_codec_hphr_dac_event,
  3578. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3579. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3580. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  3581. wcd939x_codec_ear_dac_event,
  3582. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3583. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3584. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  3585. SND_SOC_DAPM_MUX_E("RX1 MUX", SND_SOC_NOPM, WCD_RX1, 0, &rx1_mux,
  3586. wcd939x_rx_mux, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU
  3587. | SND_SOC_DAPM_POST_PMD),
  3588. SND_SOC_DAPM_MUX_E("RX2 MUX", SND_SOC_NOPM, WCD_RX2, 0, &rx2_mux,
  3589. wcd939x_rx_mux, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU
  3590. | SND_SOC_DAPM_POST_PMD),
  3591. SND_SOC_DAPM_MUX_E("RX3 MUX", SND_SOC_NOPM, WCD_RX3, 0, &rx3_mux,
  3592. wcd939x_rx3_mux, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3593. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  3594. wcd939x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  3595. SND_SOC_DAPM_POST_PMD),
  3596. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  3597. wcd939x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  3598. SND_SOC_DAPM_POST_PMD),
  3599. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  3600. wcd939x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  3601. SND_SOC_DAPM_POST_PMD),
  3602. /* rx mixer widgets*/
  3603. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  3604. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  3605. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3606. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3607. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3608. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3609. /*output widgets tx*/
  3610. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  3611. /*output widgets rx*/
  3612. SND_SOC_DAPM_OUTPUT("EAR"),
  3613. SND_SOC_DAPM_OUTPUT("HPHL"),
  3614. SND_SOC_DAPM_OUTPUT("HPHR"),
  3615. /* micbias pull up widgets*/
  3616. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3617. wcd939x_codec_enable_micbias_pullup,
  3618. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3619. SND_SOC_DAPM_POST_PMD),
  3620. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3621. wcd939x_codec_enable_micbias_pullup,
  3622. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3623. SND_SOC_DAPM_POST_PMD),
  3624. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3625. wcd939x_codec_enable_micbias_pullup,
  3626. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3627. SND_SOC_DAPM_POST_PMD),
  3628. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3629. wcd939x_codec_enable_micbias_pullup,
  3630. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3631. SND_SOC_DAPM_POST_PMD),
  3632. };
  3633. static const struct snd_soc_dapm_route wcd939x_audio_map[] = {
  3634. /*ADC-1 (channel-1)*/
  3635. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3636. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  3637. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  3638. {"ADC1 REQ", NULL, "ADC1"},
  3639. {"ADC1", NULL, "ADC1 MUX"},
  3640. {"ADC1 MUX", "CH1_AMIC1", "AMIC1_MIXER"},
  3641. {"ADC1 MUX", "CH1_AMIC2", "AMIC2_MIXER"},
  3642. {"ADC1 MUX", "CH1_AMIC3", "AMIC3_MIXER"},
  3643. {"ADC1 MUX", "CH1_AMIC4", "AMIC4_MIXER"},
  3644. {"ADC1 MUX", "CH1_AMIC5", "AMIC5_MIXER"},
  3645. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3646. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3647. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3648. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3649. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3650. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3651. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3652. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3653. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3654. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3655. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3656. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3657. {"AMIC5_MIXER", "Switch", "AMIC5"},
  3658. {"AMIC5_MIXER", NULL, "VA_AMIC5_MIXER"},
  3659. {"VA_AMIC5_MIXER", "Switch", "VA AMIC5"},
  3660. /*ADC-2 (channel-2)*/
  3661. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3662. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  3663. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  3664. {"ADC2 REQ", NULL, "ADC2"},
  3665. {"ADC2", NULL, "ADC2 MUX"},
  3666. {"ADC2 MUX", "CH2_AMIC1", "AMIC1_MIXER"},
  3667. {"ADC2 MUX", "CH2_AMIC2", "AMIC2_MIXER"},
  3668. {"ADC2 MUX", "CH2_AMIC3", "AMIC3_MIXER"},
  3669. {"ADC2 MUX", "CH2_AMIC4", "AMIC4_MIXER"},
  3670. {"ADC2 MUX", "CH2_AMIC5", "AMIC5_MIXER"},
  3671. /*ADC-3 (channel-3)*/
  3672. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3673. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  3674. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  3675. {"ADC3 REQ", NULL, "ADC3"},
  3676. {"ADC3", NULL, "ADC3 MUX"},
  3677. {"ADC3 MUX", "CH3_AMIC1", "AMIC1_MIXER"},
  3678. {"ADC3 MUX", "CH3_AMIC3", "AMIC3_MIXER"},
  3679. {"ADC3 MUX", "CH3_AMIC4", "AMIC4_MIXER"},
  3680. {"ADC3 MUX", "CH3_AMIC5", "AMIC5_MIXER"},
  3681. /*ADC-4 (channel-4)*/
  3682. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3683. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  3684. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  3685. {"ADC4 REQ", NULL, "ADC4"},
  3686. {"ADC4", NULL, "ADC4 MUX"},
  3687. {"ADC4 MUX", "CH4_AMIC1", "AMIC1_MIXER"},
  3688. {"ADC4 MUX", "CH4_AMIC3", "AMIC3_MIXER"},
  3689. {"ADC4 MUX", "CH4_AMIC4", "AMIC4_MIXER"},
  3690. {"ADC4 MUX", "CH4_AMIC5", "AMIC5_MIXER"},
  3691. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3692. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3693. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3694. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3695. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3696. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3697. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3698. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3699. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3700. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3701. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3702. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3703. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3704. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3705. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3706. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3707. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3708. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3709. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3710. {"RX1 MUX", NULL, "IN1_HPHL"},
  3711. {"RX1", NULL, "RX1 MUX"},
  3712. {"RDAC1", NULL, "RX1"},
  3713. {"HPHL_RDAC", "Switch", "RDAC1"},
  3714. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3715. {"HPHL", NULL, "HPHL PGA"},
  3716. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3717. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3718. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3719. {"RX2 MUX", NULL, "IN2_HPHR"},
  3720. {"RX2", NULL, "RX2 MUX"},
  3721. {"RDAC2", NULL, "RX2"},
  3722. {"HPHR_RDAC", "Switch", "RDAC2"},
  3723. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3724. {"HPHR", NULL, "HPHR PGA"},
  3725. {"IN3_EAR", NULL, "WCD_RX_DUMMY"},
  3726. {"IN3_EAR", NULL, "VDD_BUCK"},
  3727. {"IN3_EAR", NULL, "CLS_H_DUMMY"},
  3728. {"RX3 MUX", NULL, "IN3_EAR"},
  3729. {"RX3", NULL, "RX3 MUX"},
  3730. {"RDAC3_MUX", "RX3", "RX3"},
  3731. {"RDAC3_MUX", "RX1", "RX1"},
  3732. {"RDAC3", NULL, "RDAC3_MUX"},
  3733. {"EAR_RDAC", "Switch", "RDAC3"},
  3734. {"EAR PGA", NULL, "EAR_RDAC"},
  3735. {"EAR", NULL, "EAR PGA"},
  3736. };
  3737. static ssize_t wcd939x_version_read(struct snd_info_entry *entry,
  3738. void *file_private_data,
  3739. struct file *file,
  3740. char __user *buf, size_t count,
  3741. loff_t pos)
  3742. {
  3743. struct wcd939x_priv *priv;
  3744. char buffer[WCD939X_VERSION_ENTRY_SIZE];
  3745. int len = 0;
  3746. priv = (struct wcd939x_priv *) entry->private_data;
  3747. if (!priv) {
  3748. pr_err_ratelimited("%s: wcd939x priv is null\n", __func__);
  3749. return -EINVAL;
  3750. }
  3751. switch (priv->version) {
  3752. case WCD939X_VERSION_1_0:
  3753. case WCD939X_VERSION_1_1:
  3754. len = snprintf(buffer, sizeof(buffer), "WCD939X_1_0\n");
  3755. break;
  3756. case WCD939X_VERSION_2_0:
  3757. len = snprintf(buffer, sizeof(buffer), "WCD939X_2_0\n");
  3758. break;
  3759. default:
  3760. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3761. }
  3762. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3763. }
  3764. static struct snd_info_entry_ops wcd939x_info_ops = {
  3765. .read = wcd939x_version_read,
  3766. };
  3767. static ssize_t wcd939x_variant_read(struct snd_info_entry *entry,
  3768. void *file_private_data,
  3769. struct file *file,
  3770. char __user *buf, size_t count,
  3771. loff_t pos)
  3772. {
  3773. struct wcd939x_priv *priv;
  3774. char buffer[WCD939X_VARIANT_ENTRY_SIZE];
  3775. int len = 0;
  3776. priv = (struct wcd939x_priv *) entry->private_data;
  3777. if (!priv) {
  3778. pr_err_ratelimited("%s: wcd939x priv is null\n", __func__);
  3779. return -EINVAL;
  3780. }
  3781. switch (priv->variant) {
  3782. case WCD9390:
  3783. len = snprintf(buffer, sizeof(buffer), "WCD9390\n");
  3784. break;
  3785. case WCD9395:
  3786. len = snprintf(buffer, sizeof(buffer), "WCD9395\n");
  3787. break;
  3788. default:
  3789. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3790. }
  3791. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3792. }
  3793. static struct snd_info_entry_ops wcd939x_variant_ops = {
  3794. .read = wcd939x_variant_read,
  3795. };
  3796. /*
  3797. * wcd939x_get_codec_variant
  3798. * @component: component instance
  3799. *
  3800. * Return: codec variant or -EINVAL in error.
  3801. */
  3802. int wcd939x_get_codec_variant(struct snd_soc_component *component)
  3803. {
  3804. struct wcd939x_priv *priv = NULL;
  3805. if (!component)
  3806. return -EINVAL;
  3807. priv = snd_soc_component_get_drvdata(component);
  3808. if (!priv) {
  3809. dev_err(component->dev,
  3810. "%s:wcd939x not probed\n", __func__);
  3811. return 0;
  3812. }
  3813. return priv->variant;
  3814. }
  3815. EXPORT_SYMBOL(wcd939x_get_codec_variant);
  3816. /*
  3817. * wcd939x_info_create_codec_entry - creates wcd939x module
  3818. * @codec_root: The parent directory
  3819. * @component: component instance
  3820. *
  3821. * Creates wcd939x module, variant and version entry under the given
  3822. * parent directory.
  3823. *
  3824. * Return: 0 on success or negative error code on failure.
  3825. */
  3826. int wcd939x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3827. struct snd_soc_component *component)
  3828. {
  3829. struct snd_info_entry *version_entry;
  3830. struct snd_info_entry *variant_entry;
  3831. struct wcd939x_priv *priv;
  3832. struct snd_soc_card *card;
  3833. if (!codec_root || !component)
  3834. return -EINVAL;
  3835. priv = snd_soc_component_get_drvdata(component);
  3836. if (priv->entry) {
  3837. dev_dbg(priv->dev,
  3838. "%s:wcd939x module already created\n", __func__);
  3839. return 0;
  3840. }
  3841. card = component->card;
  3842. priv->entry = snd_info_create_module_entry(codec_root->module,
  3843. "wcd939x", codec_root);
  3844. if (!priv->entry) {
  3845. dev_dbg(component->dev, "%s: failed to create wcd939x entry\n",
  3846. __func__);
  3847. return -ENOMEM;
  3848. }
  3849. priv->entry->mode = S_IFDIR | 0555;
  3850. if (snd_info_register(priv->entry) < 0) {
  3851. snd_info_free_entry(priv->entry);
  3852. return -ENOMEM;
  3853. }
  3854. version_entry = snd_info_create_card_entry(card->snd_card,
  3855. "version",
  3856. priv->entry);
  3857. if (!version_entry) {
  3858. dev_dbg(component->dev, "%s: failed to create wcd939x version entry\n",
  3859. __func__);
  3860. snd_info_free_entry(priv->entry);
  3861. return -ENOMEM;
  3862. }
  3863. version_entry->private_data = priv;
  3864. version_entry->size = WCD939X_VERSION_ENTRY_SIZE;
  3865. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3866. version_entry->c.ops = &wcd939x_info_ops;
  3867. if (snd_info_register(version_entry) < 0) {
  3868. snd_info_free_entry(version_entry);
  3869. snd_info_free_entry(priv->entry);
  3870. return -ENOMEM;
  3871. }
  3872. priv->version_entry = version_entry;
  3873. variant_entry = snd_info_create_card_entry(card->snd_card,
  3874. "variant",
  3875. priv->entry);
  3876. if (!variant_entry) {
  3877. dev_dbg(component->dev, "%s: failed to create wcd939x variant entry\n",
  3878. __func__);
  3879. snd_info_free_entry(version_entry);
  3880. snd_info_free_entry(priv->entry);
  3881. return -ENOMEM;
  3882. }
  3883. variant_entry->private_data = priv;
  3884. variant_entry->size = WCD939X_VARIANT_ENTRY_SIZE;
  3885. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3886. variant_entry->c.ops = &wcd939x_variant_ops;
  3887. if (snd_info_register(variant_entry) < 0) {
  3888. snd_info_free_entry(variant_entry);
  3889. snd_info_free_entry(version_entry);
  3890. snd_info_free_entry(priv->entry);
  3891. return -ENOMEM;
  3892. }
  3893. priv->variant_entry = variant_entry;
  3894. return 0;
  3895. }
  3896. EXPORT_SYMBOL(wcd939x_info_create_codec_entry);
  3897. static int wcd939x_set_micbias_data(struct wcd939x_priv *wcd939x,
  3898. struct wcd939x_pdata *pdata)
  3899. {
  3900. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3901. int rc = 0;
  3902. if (!pdata) {
  3903. dev_err(wcd939x->dev, "%s: NULL pdata\n", __func__);
  3904. return -ENODEV;
  3905. }
  3906. /* set micbias voltage */
  3907. vout_ctl_1 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3908. vout_ctl_2 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3909. vout_ctl_3 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3910. vout_ctl_4 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3911. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3912. vout_ctl_4 < 0) {
  3913. rc = -EINVAL;
  3914. goto done;
  3915. }
  3916. regmap_update_bits(wcd939x->regmap, WCD939X_MICB1, 0x3F,
  3917. vout_ctl_1);
  3918. regmap_update_bits(wcd939x->regmap, WCD939X_MICB2, 0x3F,
  3919. vout_ctl_2);
  3920. regmap_update_bits(wcd939x->regmap, WCD939X_MICB3, 0x3F,
  3921. vout_ctl_3);
  3922. regmap_update_bits(wcd939x->regmap, WCD939X_MICB4, 0x3F,
  3923. vout_ctl_4);
  3924. done:
  3925. return rc;
  3926. }
  3927. static int wcd939x_soc_codec_probe(struct snd_soc_component *component)
  3928. {
  3929. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3930. struct snd_soc_dapm_context *dapm =
  3931. snd_soc_component_get_dapm(component);
  3932. int ret = -EINVAL;
  3933. dev_info(component->dev, "%s()\n", __func__);
  3934. wcd939x = snd_soc_component_get_drvdata(component);
  3935. if (!wcd939x)
  3936. return -EINVAL;
  3937. wcd939x->component = component;
  3938. snd_soc_component_init_regmap(component, wcd939x->regmap);
  3939. devm_regmap_qti_debugfs_register(&wcd939x->tx_swr_dev->dev, wcd939x->regmap);
  3940. /*Harmonium contains only one variant i.e wcd9395*/
  3941. wcd939x->variant = WCD9395;
  3942. /* Check device tree to see if 2Vpk flag is enabled, this value should not be changed */
  3943. wcd939x->in_2Vpk_mode = of_find_property(wcd939x->dev->of_node,
  3944. "qcom,hph-2p15v-mode", NULL) != NULL;
  3945. wcd939x->fw_data = devm_kzalloc(component->dev,
  3946. sizeof(*(wcd939x->fw_data)),
  3947. GFP_KERNEL);
  3948. if (!wcd939x->fw_data) {
  3949. dev_err(component->dev, "Failed to allocate fw_data\n");
  3950. ret = -ENOMEM;
  3951. goto err;
  3952. }
  3953. set_bit(WCD9XXX_MBHC_CAL, wcd939x->fw_data->cal_bit);
  3954. ret = wcd_cal_create_hwdep(wcd939x->fw_data,
  3955. WCD9XXX_CODEC_HWDEP_NODE, component);
  3956. if (ret < 0) {
  3957. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3958. goto err_hwdep;
  3959. }
  3960. ret = wcd939x_mbhc_init(&wcd939x->mbhc, component, wcd939x->fw_data);
  3961. if (ret) {
  3962. pr_err("%s: mbhc initialization failed\n", __func__);
  3963. goto err_hwdep;
  3964. }
  3965. snd_soc_dapm_ignore_suspend(dapm, "WCD939X_AIF Playback");
  3966. snd_soc_dapm_ignore_suspend(dapm, "WCD939X_AIF Capture");
  3967. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3968. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3969. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3970. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3971. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3972. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3973. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3974. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3975. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3976. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC5");
  3977. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3978. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3979. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3980. snd_soc_dapm_ignore_suspend(dapm, "IN3_EAR");
  3981. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3982. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3983. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3984. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3985. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3986. snd_soc_dapm_sync(dapm);
  3987. wcd_cls_h_init(&wcd939x->clsh_info);
  3988. wcd939x_init_reg(component);
  3989. if (wcd939x->variant == WCD9390) {
  3990. ret = snd_soc_add_component_controls(component, wcd9390_snd_controls,
  3991. ARRAY_SIZE(wcd9390_snd_controls));
  3992. if (ret < 0) {
  3993. dev_err(component->dev,
  3994. "%s: Failed to add snd ctrls for variant: %d\n",
  3995. __func__, wcd939x->variant);
  3996. goto err_hwdep;
  3997. }
  3998. }
  3999. if (wcd939x->variant == WCD9395) {
  4000. ret = snd_soc_add_component_controls(component, wcd9395_snd_controls,
  4001. ARRAY_SIZE(wcd9395_snd_controls));
  4002. if (ret < 0) {
  4003. dev_err(component->dev,
  4004. "%s: Failed to add snd ctrls for variant: %d\n",
  4005. __func__, wcd939x->variant);
  4006. goto err_hwdep;
  4007. }
  4008. }
  4009. /* Register event notifier */
  4010. wcd939x->nblock.notifier_call = wcd939x_event_notify;
  4011. if (wcd939x->register_notifier) {
  4012. ret = wcd939x->register_notifier(wcd939x->handle,
  4013. &wcd939x->nblock,
  4014. true);
  4015. if (ret) {
  4016. dev_err(component->dev,
  4017. "%s: Failed to register notifier %d\n",
  4018. __func__, ret);
  4019. return ret;
  4020. }
  4021. }
  4022. return ret;
  4023. err_hwdep:
  4024. wcd939x->fw_data = NULL;
  4025. err:
  4026. return ret;
  4027. }
  4028. static void wcd939x_soc_codec_remove(struct snd_soc_component *component)
  4029. {
  4030. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  4031. if (!wcd939x) {
  4032. dev_err(component->dev, "%s: wcd939x is already NULL\n",
  4033. __func__);
  4034. return;
  4035. }
  4036. if (wcd939x->register_notifier)
  4037. wcd939x->register_notifier(wcd939x->handle,
  4038. &wcd939x->nblock,
  4039. false);
  4040. }
  4041. static int wcd939x_soc_codec_suspend(struct snd_soc_component *component)
  4042. {
  4043. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  4044. if (!wcd939x)
  4045. return 0;
  4046. wcd939x->dapm_bias_off = true;
  4047. return 0;
  4048. }
  4049. static int wcd939x_soc_codec_resume(struct snd_soc_component *component)
  4050. {
  4051. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  4052. if (!wcd939x)
  4053. return 0;
  4054. wcd939x->dapm_bias_off = false;
  4055. return 0;
  4056. }
  4057. static struct snd_soc_component_driver soc_codec_dev_wcd939x = {
  4058. .name = WCD939X_DRV_NAME,
  4059. .probe = wcd939x_soc_codec_probe,
  4060. .remove = wcd939x_soc_codec_remove,
  4061. .controls = wcd939x_snd_controls,
  4062. .num_controls = ARRAY_SIZE(wcd939x_snd_controls),
  4063. .dapm_widgets = wcd939x_dapm_widgets,
  4064. .num_dapm_widgets = ARRAY_SIZE(wcd939x_dapm_widgets),
  4065. .dapm_routes = wcd939x_audio_map,
  4066. .num_dapm_routes = ARRAY_SIZE(wcd939x_audio_map),
  4067. .suspend = wcd939x_soc_codec_suspend,
  4068. .resume = wcd939x_soc_codec_resume,
  4069. };
  4070. static int wcd939x_reset(struct device *dev)
  4071. {
  4072. struct wcd939x_priv *wcd939x = NULL;
  4073. int rc = 0;
  4074. int value = 0;
  4075. if (!dev)
  4076. return -ENODEV;
  4077. wcd939x = dev_get_drvdata(dev);
  4078. if (!wcd939x)
  4079. return -EINVAL;
  4080. if (!wcd939x->rst_np) {
  4081. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  4082. __func__);
  4083. return -EINVAL;
  4084. }
  4085. value = msm_cdc_pinctrl_get_state(wcd939x->rst_np);
  4086. if (value > 0)
  4087. return 0;
  4088. rc = msm_cdc_pinctrl_select_sleep_state(wcd939x->rst_np);
  4089. if (rc) {
  4090. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  4091. __func__);
  4092. return rc;
  4093. }
  4094. /* 20us sleep required after pulling the reset gpio to LOW */
  4095. usleep_range(20, 30);
  4096. rc = msm_cdc_pinctrl_select_active_state(wcd939x->rst_np);
  4097. if (rc) {
  4098. dev_err_ratelimited(dev, "%s: wcd active state request fail!\n",
  4099. __func__);
  4100. return rc;
  4101. }
  4102. /* 20us sleep required after pulling the reset gpio to HIGH */
  4103. usleep_range(20, 30);
  4104. return rc;
  4105. }
  4106. static int wcd939x_read_of_property_u32(struct device *dev, const char *name,
  4107. u32 *val)
  4108. {
  4109. int rc = 0;
  4110. rc = of_property_read_u32(dev->of_node, name, val);
  4111. if (rc)
  4112. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  4113. __func__, name, dev->of_node->full_name);
  4114. return rc;
  4115. }
  4116. static int wcd939x_read_of_property_s32(struct device *dev, const char *name,
  4117. s32 *val)
  4118. {
  4119. int rc = 0;
  4120. rc = of_property_read_s32(dev->of_node, name, val);
  4121. if (rc)
  4122. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  4123. __func__, name, dev->of_node->full_name);
  4124. return rc;
  4125. }
  4126. static void wcd939x_dt_parse_micbias_info(struct device *dev,
  4127. struct wcd939x_micbias_setting *mb)
  4128. {
  4129. u32 prop_val = 0;
  4130. int rc = 0;
  4131. /* MB1 */
  4132. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  4133. NULL)) {
  4134. rc = wcd939x_read_of_property_u32(dev,
  4135. "qcom,cdc-micbias1-mv",
  4136. &prop_val);
  4137. if (!rc)
  4138. mb->micb1_mv = prop_val;
  4139. } else {
  4140. dev_info(dev, "%s: Micbias1 DT property not found\n",
  4141. __func__);
  4142. }
  4143. /* MB2 */
  4144. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  4145. NULL)) {
  4146. rc = wcd939x_read_of_property_u32(dev,
  4147. "qcom,cdc-micbias2-mv",
  4148. &prop_val);
  4149. if (!rc)
  4150. mb->micb2_mv = prop_val;
  4151. } else {
  4152. dev_info(dev, "%s: Micbias2 DT property not found\n",
  4153. __func__);
  4154. }
  4155. /* MB3 */
  4156. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  4157. NULL)) {
  4158. rc = wcd939x_read_of_property_u32(dev,
  4159. "qcom,cdc-micbias3-mv",
  4160. &prop_val);
  4161. if (!rc)
  4162. mb->micb3_mv = prop_val;
  4163. } else {
  4164. dev_info(dev, "%s: Micbias3 DT property not found\n",
  4165. __func__);
  4166. }
  4167. /* MB4 */
  4168. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  4169. NULL)) {
  4170. rc = wcd939x_read_of_property_u32(dev,
  4171. "qcom,cdc-micbias4-mv",
  4172. &prop_val);
  4173. if (!rc)
  4174. mb->micb4_mv = prop_val;
  4175. } else {
  4176. dev_info(dev, "%s: Micbias4 DT property not found\n",
  4177. __func__);
  4178. }
  4179. }
  4180. static void init_usbcss_hs_params(struct wcd939x_usbcss_hs_params *usbcss_hs)
  4181. {
  4182. usbcss_hs->r_gnd_sbu1_int_fet_mohms = 145;
  4183. usbcss_hs->r_gnd_sbu2_int_fet_mohms = 185;
  4184. usbcss_hs->r_gnd_ext_fet_customer_mohms = 0;
  4185. usbcss_hs->r_gnd_ext_fet_mohms = 0; /* to be computed during MBHC zdet */
  4186. usbcss_hs->r_gnd_par_route1_mohms = 5;
  4187. usbcss_hs->r_gnd_par_route2_mohms = 330;
  4188. usbcss_hs->r_gnd_par_tot_mohms = 0;
  4189. usbcss_hs->r_gnd_sbu1_res_tot_mohms = 0;
  4190. usbcss_hs->r_gnd_sbu2_res_tot_mohms = 0;
  4191. usbcss_hs->r_conn_par_load_pos_mohms = 7550;
  4192. usbcss_hs->r_aud_int_fet_l_mohms = 303;
  4193. usbcss_hs->r_aud_int_fet_r_mohms = 275;
  4194. usbcss_hs->r_aud_ext_fet_l_mohms = 0; /* to be computed during MBHC zdet */
  4195. usbcss_hs->r_aud_ext_fet_r_mohms = 0; /* to be computed during MBHC zdet */
  4196. usbcss_hs->r_aud_res_tot_l_mohms = 0;
  4197. usbcss_hs->r_aud_res_tot_r_mohms = 0;
  4198. usbcss_hs->r_surge_mohms = 272;
  4199. usbcss_hs->r_load_eff_l_mohms = 0; /* to be computed during MBHC zdet */
  4200. usbcss_hs->r_load_eff_r_mohms = 0; /* to be computed during MBHC zdet */
  4201. usbcss_hs->r3 = 1;
  4202. usbcss_hs->r4 = 330;
  4203. usbcss_hs->r5 = 5;
  4204. usbcss_hs->r6 = 1;
  4205. usbcss_hs->r7 = 5;
  4206. usbcss_hs->k_aud_times_100 = 13;
  4207. usbcss_hs->k_gnd_times_100 = 13;
  4208. usbcss_hs->aud_tap_offset = 0;
  4209. usbcss_hs->gnd_tap_offset = 0;
  4210. usbcss_hs->scale_l = MAX_XTALK_SCALE;
  4211. usbcss_hs->alpha_l = MIN_XTALK_ALPHA;
  4212. usbcss_hs->scale_r = MAX_XTALK_SCALE;
  4213. usbcss_hs->alpha_r = MIN_XTALK_ALPHA;
  4214. usbcss_hs->xtalk_config = XTALK_NONE;
  4215. }
  4216. static void parse_xtalk_param(struct device *dev, u32 default_val, u32 *prop_val_p,
  4217. char *prop)
  4218. {
  4219. int rc = 0;
  4220. if (of_find_property(dev->of_node, prop, NULL)) {
  4221. rc = wcd939x_read_of_property_u32(dev, prop, prop_val_p);
  4222. if ((!rc) && (*prop_val_p <= MAX_USBCSS_HS_IMPEDANCE_MOHMS) && (*prop_val_p > 0))
  4223. return;
  4224. *prop_val_p = default_val;
  4225. dev_dbg(dev, "%s: %s OOB. Default value of %d will be used.\n", __func__, prop,
  4226. default_val);
  4227. } else {
  4228. *prop_val_p = default_val;
  4229. dev_dbg(dev, "%s: %s property not found. Default value of %d will be used.\n",
  4230. __func__, prop, default_val);
  4231. }
  4232. }
  4233. static void wcd939x_dt_parse_usbcss_hs_info(struct device *dev,
  4234. struct wcd939x_usbcss_hs_params *usbcss_hs)
  4235. {
  4236. u32 prop_val = 0;
  4237. s32 prop_val_signed = 0;
  4238. int rc = 0;
  4239. /* Default values for parameters */
  4240. init_usbcss_hs_params(usbcss_hs);
  4241. /* xtalk_config: Determine type of crosstalk: none (0), digital (1), or analog (2) */
  4242. if (of_find_property(dev->of_node, "qcom,usbcss-hs-xtalk-config", NULL)) {
  4243. rc = wcd939x_read_of_property_u32(dev, "qcom,usbcss-hs-xtalk-config", &prop_val);
  4244. if ((!rc) && (prop_val == XTALK_NONE || prop_val == XTALK_DIGITAL
  4245. || prop_val == XTALK_ANALOG)) {
  4246. usbcss_hs->xtalk_config = (enum xtalk_mode) prop_val;
  4247. } else
  4248. dev_dbg(dev, "%s: %s OOB. Default value of %s used.\n",
  4249. __func__, "qcom,usbcss-hs-xtalk-config", "XTALK_NONE");
  4250. } else
  4251. dev_dbg(dev, "%s: %s property not found. Default value of %s used.\n",
  4252. __func__, "qcom,usbcss-hs-xtalk-config", "XTALK_NONE");
  4253. /* k values for linearizer */
  4254. if (of_find_property(dev->of_node, "qcom,usbcss-hs-lin-k-aud", NULL)) {
  4255. rc = wcd939x_read_of_property_s32(dev, "qcom,usbcss-hs-lin-k-aud",
  4256. &prop_val);
  4257. if ((!rc) && (prop_val <= MAX_K_TIMES_100) && (prop_val >= MIN_K_TIMES_100))
  4258. usbcss_hs->k_aud_times_100 = prop_val;
  4259. dev_dbg(dev, "%s: %s OOB. Default value of %d will be used.\n",
  4260. __func__, "qcom,usbcss-hs-lin-k-aud",
  4261. usbcss_hs->k_aud_times_100);
  4262. } else {
  4263. dev_dbg(dev, "%s: %s property not found. Default value of %d will be used.\n",
  4264. __func__, "qcom,usbcss-hs-lin-k-aud",
  4265. usbcss_hs->k_aud_times_100);
  4266. }
  4267. if (of_find_property(dev->of_node, "qcom,usbcss-hs-lin-k-gnd", NULL)) {
  4268. rc = wcd939x_read_of_property_s32(dev, "qcom,usbcss-hs-lin-k-gnd",
  4269. &prop_val_signed);
  4270. if ((!rc) && (prop_val_signed <= MAX_K_TIMES_100) &&
  4271. (prop_val_signed >= MIN_K_TIMES_100))
  4272. usbcss_hs->k_gnd_times_100 = prop_val_signed;
  4273. dev_dbg(dev, "%s: %s OOB. Default value of %d will be used.\n",
  4274. __func__, "qcom,usbcss-hs-lin-k-gnd",
  4275. usbcss_hs->k_gnd_times_100);
  4276. } else {
  4277. dev_dbg(dev, "%s: %s property not found. Default value of %d will be used.\n",
  4278. __func__, "qcom,usbcss-hs-lin-k-gnd",
  4279. usbcss_hs->k_gnd_times_100);
  4280. }
  4281. /* r_gnd_ext_fet_customer_mohms */
  4282. parse_xtalk_param(dev, usbcss_hs->r_gnd_ext_fet_customer_mohms, &prop_val,
  4283. "qcom,usbcss-hs-rdson");
  4284. usbcss_hs->r_gnd_ext_fet_customer_mohms = prop_val;
  4285. /* r_conn_par_load_pos_mohm */
  4286. parse_xtalk_param(dev, usbcss_hs->r_conn_par_load_pos_mohms, &prop_val,
  4287. "qcom,usbcss-hs-r2");
  4288. usbcss_hs->r_conn_par_load_pos_mohms = prop_val;
  4289. /* r3 */
  4290. parse_xtalk_param(dev, usbcss_hs->r3, &prop_val,
  4291. "qcom,usbcss-hs-r3");
  4292. usbcss_hs->r3 = prop_val;
  4293. /* r4 */
  4294. parse_xtalk_param(dev, usbcss_hs->r4, &prop_val,
  4295. "qcom,usbcss-hs-r4");
  4296. usbcss_hs->r4 = prop_val;
  4297. /* r_gnd_par_route1_mohms and r_gnd_par_route2_mohms */
  4298. if (usbcss_hs->xtalk_config == XTALK_ANALOG) {
  4299. parse_xtalk_param(dev, usbcss_hs->r5, &prop_val,
  4300. "qcom,usbcss-hs-r5");
  4301. usbcss_hs->r5 = prop_val;
  4302. usbcss_hs->r_gnd_par_route1_mohms = usbcss_hs->r5 + usbcss_hs->r4;
  4303. usbcss_hs->r_gnd_par_route2_mohms = 125;
  4304. } else if (usbcss_hs->xtalk_config == XTALK_DIGITAL) {
  4305. parse_xtalk_param(dev, usbcss_hs->r6, &prop_val,
  4306. "qcom,usbcss-hs-r6");
  4307. usbcss_hs->r6 = prop_val;
  4308. usbcss_hs->r_gnd_par_route2_mohms = usbcss_hs->r6 + usbcss_hs->r4;
  4309. parse_xtalk_param(dev, usbcss_hs->r_gnd_par_route1_mohms, &prop_val,
  4310. "qcom,usbcss-hs-r7");
  4311. usbcss_hs->r7 = prop_val;
  4312. usbcss_hs->r_gnd_par_route1_mohms = prop_val;
  4313. }
  4314. /* Compute total resistances */
  4315. usbcss_hs->r_gnd_par_tot_mohms = usbcss_hs->r_gnd_par_route1_mohms +
  4316. usbcss_hs->r_gnd_par_route2_mohms;
  4317. usbcss_hs->r_gnd_sbu1_res_tot_mohms = get_r_gnd_res_tot_mohms(
  4318. usbcss_hs->r_gnd_sbu1_int_fet_mohms,
  4319. usbcss_hs->r_gnd_ext_fet_mohms,
  4320. usbcss_hs->r_gnd_par_tot_mohms);
  4321. usbcss_hs->r_gnd_sbu2_res_tot_mohms = get_r_gnd_res_tot_mohms(
  4322. usbcss_hs->r_gnd_sbu2_int_fet_mohms,
  4323. usbcss_hs->r_gnd_ext_fet_mohms,
  4324. usbcss_hs->r_gnd_par_tot_mohms);
  4325. usbcss_hs->r_aud_res_tot_l_mohms = get_r_aud_res_tot_mohms(
  4326. usbcss_hs->r_aud_int_fet_l_mohms,
  4327. usbcss_hs->r_aud_ext_fet_l_mohms);
  4328. usbcss_hs->r_aud_res_tot_r_mohms = get_r_aud_res_tot_mohms(
  4329. usbcss_hs->r_aud_int_fet_r_mohms,
  4330. usbcss_hs->r_aud_ext_fet_r_mohms);
  4331. /* Set linearizer calibration codes to be sourced from SW */
  4332. wcd_usbss_linearizer_rdac_cal_code_select(LINEARIZER_SOURCE_SW);
  4333. }
  4334. static int wcd939x_reset_low(struct device *dev)
  4335. {
  4336. struct wcd939x_priv *wcd939x = NULL;
  4337. int rc = 0;
  4338. if (!dev)
  4339. return -ENODEV;
  4340. wcd939x = dev_get_drvdata(dev);
  4341. if (!wcd939x)
  4342. return -EINVAL;
  4343. if (!wcd939x->rst_np) {
  4344. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  4345. __func__);
  4346. return -EINVAL;
  4347. }
  4348. rc = msm_cdc_pinctrl_select_sleep_state(wcd939x->rst_np);
  4349. if (rc) {
  4350. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  4351. __func__);
  4352. return rc;
  4353. }
  4354. /* 20us sleep required after pulling the reset gpio to LOW */
  4355. usleep_range(20, 30);
  4356. return rc;
  4357. }
  4358. struct wcd939x_pdata *wcd939x_populate_dt_data(struct device *dev)
  4359. {
  4360. struct wcd939x_pdata *pdata = NULL;
  4361. pdata = devm_kzalloc(dev, sizeof(struct wcd939x_pdata),
  4362. GFP_KERNEL);
  4363. if (!pdata)
  4364. return NULL;
  4365. pdata->rst_np = of_parse_phandle(dev->of_node,
  4366. "qcom,wcd-rst-gpio-node", 0);
  4367. if (!pdata->rst_np) {
  4368. dev_err_ratelimited(dev, "%s: Looking up %s property in node %s failed\n",
  4369. __func__, "qcom,wcd-rst-gpio-node",
  4370. dev->of_node->full_name);
  4371. return NULL;
  4372. }
  4373. /* Parse power supplies */
  4374. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  4375. &pdata->num_supplies);
  4376. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  4377. dev_err_ratelimited(dev, "%s: no power supplies defined for codec\n",
  4378. __func__);
  4379. return NULL;
  4380. }
  4381. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  4382. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  4383. wcd939x_dt_parse_micbias_info(dev, &pdata->micbias);
  4384. wcd939x_dt_parse_usbcss_hs_info(dev, &pdata->usbcss_hs);
  4385. return pdata;
  4386. }
  4387. static irqreturn_t wcd939x_wd_handle_irq(int irq, void *data)
  4388. {
  4389. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  4390. __func__, irq);
  4391. return IRQ_HANDLED;
  4392. }
  4393. static struct snd_soc_dai_driver wcd939x_dai[] = {
  4394. {
  4395. .name = "wcd939x_cdc",
  4396. .playback = {
  4397. .stream_name = "WCD939X_AIF Playback",
  4398. .rates = WCD939X_RATES | WCD939X_FRAC_RATES,
  4399. .formats = WCD939X_FORMATS,
  4400. .rate_max = 384000,
  4401. .rate_min = 8000,
  4402. .channels_min = 1,
  4403. .channels_max = 4,
  4404. },
  4405. .capture = {
  4406. .stream_name = "WCD939X_AIF Capture",
  4407. .rates = WCD939X_RATES | WCD939X_FRAC_RATES,
  4408. .formats = WCD939X_FORMATS,
  4409. .rate_max = 384000,
  4410. .rate_min = 8000,
  4411. .channels_min = 1,
  4412. .channels_max = 4,
  4413. },
  4414. },
  4415. };
  4416. static const struct reg_default reg_def_1_1[] = {
  4417. {WCD939X_VBG_FINE_ADJ, 0xA5},
  4418. {WCD939X_FLYBACK_NEW_CTRL_2, 0x0},
  4419. {WCD939X_FLYBACK_NEW_CTRL_3, 0x0},
  4420. {WCD939X_FLYBACK_NEW_CTRL_4, 0x44},
  4421. {WCD939X_PA_GAIN_CTL_R, 0x80},
  4422. };
  4423. static const struct reg_default reg_def_2_0[] = {
  4424. {WCD939X_INTR_MASK_2, 0x3E},
  4425. };
  4426. static const char *version_to_str(u32 version)
  4427. {
  4428. switch (version) {
  4429. case WCD939X_VERSION_1_0:
  4430. return __stringify(WCD939X_1_0);
  4431. case WCD939X_VERSION_1_1:
  4432. return __stringify(WCD939X_1_1);
  4433. case WCD939X_VERSION_2_0:
  4434. return __stringify(WCD939X_2_0);
  4435. }
  4436. return NULL;
  4437. }
  4438. static void wcd939x_update_regmap_cache(struct wcd939x_priv *wcd939x)
  4439. {
  4440. if (wcd939x->version == WCD939X_VERSION_1_0)
  4441. return;
  4442. if (wcd939x->version >= WCD939X_VERSION_1_1) {
  4443. for (int i = 0; i < ARRAY_SIZE(reg_def_1_1); ++i)
  4444. regmap_write(wcd939x->regmap, reg_def_1_1[i].reg, reg_def_1_1[i].def);
  4445. }
  4446. if (wcd939x->version == WCD939X_VERSION_2_0) {
  4447. for (int i = 0; i < ARRAY_SIZE(reg_def_2_0); ++i)
  4448. regmap_write(wcd939x->regmap, reg_def_2_0[i].reg, reg_def_2_0[i].def);
  4449. }
  4450. }
  4451. static int wcd939x_bind(struct device *dev)
  4452. {
  4453. int ret = 0, i = 0, val = 0;
  4454. struct wcd939x_pdata *pdata = dev_get_platdata(dev);
  4455. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  4456. u8 id1 = 0, status1 = 0;
  4457. /*
  4458. * Add 5msec delay to provide sufficient time for
  4459. * soundwire auto enumeration of slave devices as
  4460. * as per HW requirement.
  4461. */
  4462. usleep_range(5000, 5010);
  4463. ret = component_bind_all(dev, wcd939x);
  4464. if (ret) {
  4465. dev_err_ratelimited(dev, "%s: Slave bind failed, ret = %d\n",
  4466. __func__, ret);
  4467. return ret;
  4468. }
  4469. wcd939x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  4470. if (!wcd939x->rx_swr_dev) {
  4471. dev_err_ratelimited(dev, "%s: Could not find RX swr slave device\n",
  4472. __func__);
  4473. ret = -ENODEV;
  4474. goto err;
  4475. }
  4476. wcd939x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  4477. if (!wcd939x->tx_swr_dev) {
  4478. dev_err_ratelimited(dev, "%s: Could not find TX swr slave device\n",
  4479. __func__);
  4480. ret = -ENODEV;
  4481. goto err;
  4482. }
  4483. swr_init_port_params(wcd939x->tx_swr_dev, SWR_NUM_PORTS,
  4484. wcd939x->swr_tx_port_params);
  4485. /* Check WCD9395 version */
  4486. swr_read(wcd939x->tx_swr_dev, wcd939x->tx_swr_dev->dev_num,
  4487. WCD939X_CHIP_ID1, &id1, 1);
  4488. swr_read(wcd939x->tx_swr_dev, wcd939x->tx_swr_dev->dev_num,
  4489. WCD939X_STATUS_REG_1, &status1, 1);
  4490. if (id1 == 0)
  4491. wcd939x->version = ((status1 & 0x3) ? WCD939X_VERSION_1_1 : WCD939X_VERSION_1_0);
  4492. else if (id1 == 1)
  4493. wcd939x->version = WCD939X_VERSION_2_0;
  4494. wcd939x_version = wcd939x->version;
  4495. dev_info(dev, "%s: wcd9395 version: %s\n", __func__,
  4496. version_to_str(wcd939x->version));
  4497. wcd939x_regmap_config.readable_reg = wcd939x_readable_register;
  4498. wcd939x->regmap = devm_regmap_init_swr(wcd939x->tx_swr_dev,
  4499. &wcd939x_regmap_config);
  4500. if (!wcd939x->regmap) {
  4501. dev_err_ratelimited(dev, "%s: Regmap init failed\n",
  4502. __func__);
  4503. goto err;
  4504. }
  4505. #if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
  4506. regmap_read(wcd939x->regmap, WCD939X_EFUSE_REG_17, &val);
  4507. if (wcd939x_version == WCD939X_VERSION_2_0 && val < 3)
  4508. wcd_usbss_update_default_trim();
  4509. #endif
  4510. wcd939x_update_regmap_cache(wcd939x);
  4511. /* Set all interupts as edge triggered */
  4512. for (i = 0; i < wcd939x_regmap_irq_chip.num_regs; i++)
  4513. regmap_write(wcd939x->regmap,
  4514. (WCD939X_INTR_LEVEL_0 + i), 0);
  4515. wcd939x_regmap_irq_chip.irq_drv_data = wcd939x;
  4516. wcd939x->irq_info.wcd_regmap_irq_chip = &wcd939x_regmap_irq_chip;
  4517. wcd939x->irq_info.codec_name = "WCD939X";
  4518. wcd939x->irq_info.regmap = wcd939x->regmap;
  4519. wcd939x->irq_info.dev = dev;
  4520. ret = wcd_irq_init(&wcd939x->irq_info, &wcd939x->virq);
  4521. if (ret) {
  4522. dev_err_ratelimited(wcd939x->dev, "%s: IRQ init failed: %d\n",
  4523. __func__, ret);
  4524. goto err;
  4525. }
  4526. wcd939x->tx_swr_dev->slave_irq = wcd939x->virq;
  4527. ret = wcd939x_set_micbias_data(wcd939x, pdata);
  4528. if (ret < 0) {
  4529. dev_err_ratelimited(dev, "%s: bad micbias pdata\n", __func__);
  4530. goto err_irq;
  4531. }
  4532. /* Request for watchdog interrupt */
  4533. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT,
  4534. "HPHR PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4535. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT,
  4536. "HPHL PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4537. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT,
  4538. "EAR PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4539. /* Disable watchdog interrupt for HPH and EAR */
  4540. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT);
  4541. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT);
  4542. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT);
  4543. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd939x,
  4544. wcd939x_dai, ARRAY_SIZE(wcd939x_dai));
  4545. if (ret) {
  4546. dev_err_ratelimited(dev, "%s: Codec registration failed\n",
  4547. __func__);
  4548. goto err_irq;
  4549. }
  4550. wcd939x->dev_up = true;
  4551. return ret;
  4552. err_irq:
  4553. wcd_irq_exit(&wcd939x->irq_info, wcd939x->virq);
  4554. err:
  4555. component_unbind_all(dev, wcd939x);
  4556. return ret;
  4557. }
  4558. static void wcd939x_unbind(struct device *dev)
  4559. {
  4560. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  4561. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT, NULL);
  4562. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT, NULL);
  4563. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT, NULL);
  4564. wcd_irq_exit(&wcd939x->irq_info, wcd939x->virq);
  4565. snd_soc_unregister_component(dev);
  4566. component_unbind_all(dev, wcd939x);
  4567. }
  4568. static const struct of_device_id wcd939x_dt_match[] = {
  4569. { .compatible = "qcom,wcd939x-codec", .data = "wcd939x"},
  4570. {}
  4571. };
  4572. static const struct component_master_ops wcd939x_comp_ops = {
  4573. .bind = wcd939x_bind,
  4574. .unbind = wcd939x_unbind,
  4575. };
  4576. static int wcd939x_compare_of(struct device *dev, void *data)
  4577. {
  4578. return dev->of_node == data;
  4579. }
  4580. static void wcd939x_release_of(struct device *dev, void *data)
  4581. {
  4582. of_node_put(data);
  4583. }
  4584. static int wcd939x_add_slave_components(struct device *dev,
  4585. struct component_match **matchptr)
  4586. {
  4587. struct device_node *np, *rx_node, *tx_node;
  4588. np = dev->of_node;
  4589. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  4590. if (!rx_node) {
  4591. dev_err_ratelimited(dev, "%s: Rx-slave node not defined\n", __func__);
  4592. return -ENODEV;
  4593. }
  4594. of_node_get(rx_node);
  4595. component_match_add_release(dev, matchptr,
  4596. wcd939x_release_of,
  4597. wcd939x_compare_of,
  4598. rx_node);
  4599. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  4600. if (!tx_node) {
  4601. dev_err_ratelimited(dev, "%s: Tx-slave node not defined\n", __func__);
  4602. return -ENODEV;
  4603. }
  4604. of_node_get(tx_node);
  4605. component_match_add_release(dev, matchptr,
  4606. wcd939x_release_of,
  4607. wcd939x_compare_of,
  4608. tx_node);
  4609. return 0;
  4610. }
  4611. static int wcd939x_probe(struct platform_device *pdev)
  4612. {
  4613. struct component_match *match = NULL;
  4614. struct wcd939x_priv *wcd939x = NULL;
  4615. struct wcd939x_pdata *pdata = NULL;
  4616. struct wcd_ctrl_platform_data *plat_data = NULL;
  4617. struct device *dev = &pdev->dev;
  4618. int ret;
  4619. wcd939x = devm_kzalloc(dev, sizeof(struct wcd939x_priv),
  4620. GFP_KERNEL);
  4621. if (!wcd939x)
  4622. return -ENOMEM;
  4623. dev_set_drvdata(dev, wcd939x);
  4624. wcd939x->dev = dev;
  4625. pdata = wcd939x_populate_dt_data(dev);
  4626. if (!pdata) {
  4627. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  4628. return -EINVAL;
  4629. }
  4630. dev->platform_data = pdata;
  4631. wcd939x->rst_np = pdata->rst_np;
  4632. ret = msm_cdc_init_supplies(dev, &wcd939x->supplies,
  4633. pdata->regulator, pdata->num_supplies);
  4634. if (!wcd939x->supplies) {
  4635. dev_err(dev, "%s: Cannot init wcd supplies\n",
  4636. __func__);
  4637. return ret;
  4638. }
  4639. plat_data = dev_get_platdata(dev->parent);
  4640. if (!plat_data) {
  4641. dev_err(dev, "%s: platform data from parent is NULL\n",
  4642. __func__);
  4643. return -EINVAL;
  4644. }
  4645. wcd939x->handle = (void *)plat_data->handle;
  4646. if (!wcd939x->handle) {
  4647. dev_err(dev, "%s: handle is NULL\n", __func__);
  4648. return -EINVAL;
  4649. }
  4650. wcd939x->update_wcd_event = plat_data->update_wcd_event;
  4651. if (!wcd939x->update_wcd_event) {
  4652. dev_err(dev, "%s: update_wcd_event api is null!\n",
  4653. __func__);
  4654. return -EINVAL;
  4655. }
  4656. wcd939x->register_notifier = plat_data->register_notifier;
  4657. if (!wcd939x->register_notifier) {
  4658. dev_err(dev, "%s: register_notifier api is null!\n",
  4659. __func__);
  4660. return -EINVAL;
  4661. }
  4662. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd939x->supplies,
  4663. pdata->regulator,
  4664. pdata->num_supplies);
  4665. if (ret) {
  4666. dev_err(dev, "%s: wcd static supply enable failed!\n",
  4667. __func__);
  4668. return ret;
  4669. }
  4670. if (msm_cdc_is_ondemand_supply(wcd939x->dev, wcd939x->supplies,
  4671. pdata->regulator, pdata->num_supplies, "cdc-vdd-px")) {
  4672. ret = msm_cdc_enable_ondemand_supply(wcd939x->dev,
  4673. wcd939x->supplies, pdata->regulator,
  4674. pdata->num_supplies, "cdc-vdd-px");
  4675. if (ret) {
  4676. dev_err(dev, "%s: vdd px supply enable failed!\n",
  4677. __func__);
  4678. return ret;
  4679. }
  4680. }
  4681. ret = wcd939x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  4682. CODEC_RX);
  4683. ret |= wcd939x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  4684. CODEC_TX);
  4685. if (ret) {
  4686. dev_err(dev, "Failed to read port mapping\n");
  4687. goto err;
  4688. }
  4689. ret = wcd939x_parse_port_params(dev, "qcom,swr-tx-port-params",
  4690. CODEC_TX);
  4691. if (ret) {
  4692. dev_err(dev, "Failed to read port params\n");
  4693. goto err;
  4694. }
  4695. mutex_init(&wcd939x->wakeup_lock);
  4696. mutex_init(&wcd939x->micb_lock);
  4697. ret = wcd939x_add_slave_components(dev, &match);
  4698. if (ret)
  4699. goto err_lock_init;
  4700. wcd939x_reset(dev);
  4701. wcd939x->wakeup = wcd939x_wakeup;
  4702. return component_master_add_with_match(dev,
  4703. &wcd939x_comp_ops, match);
  4704. err_lock_init:
  4705. mutex_destroy(&wcd939x->micb_lock);
  4706. mutex_destroy(&wcd939x->wakeup_lock);
  4707. err:
  4708. return ret;
  4709. }
  4710. static int wcd939x_remove(struct platform_device *pdev)
  4711. {
  4712. struct wcd939x_priv *wcd939x = NULL;
  4713. wcd939x = platform_get_drvdata(pdev);
  4714. component_master_del(&pdev->dev, &wcd939x_comp_ops);
  4715. mutex_destroy(&wcd939x->micb_lock);
  4716. mutex_destroy(&wcd939x->wakeup_lock);
  4717. dev_set_drvdata(&pdev->dev, NULL);
  4718. return 0;
  4719. }
  4720. #ifdef CONFIG_PM_SLEEP
  4721. static int wcd939x_suspend(struct device *dev)
  4722. {
  4723. struct wcd939x_priv *wcd939x = NULL;
  4724. int ret = 0;
  4725. struct wcd939x_pdata *pdata = NULL;
  4726. if (!dev)
  4727. return -ENODEV;
  4728. wcd939x = dev_get_drvdata(dev);
  4729. if (!wcd939x)
  4730. return -EINVAL;
  4731. pdata = dev_get_platdata(wcd939x->dev);
  4732. if (!pdata) {
  4733. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4734. return -EINVAL;
  4735. }
  4736. if (test_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask)) {
  4737. ret = msm_cdc_disable_ondemand_supply(wcd939x->dev,
  4738. wcd939x->supplies,
  4739. pdata->regulator,
  4740. pdata->num_supplies,
  4741. "cdc-vdd-buck");
  4742. if (ret == -EINVAL) {
  4743. dev_err_ratelimited(dev, "%s: vdd buck is not disabled\n",
  4744. __func__);
  4745. return 0;
  4746. }
  4747. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  4748. }
  4749. if (wcd939x->dapm_bias_off ||
  4750. (wcd939x->component &&
  4751. (snd_soc_component_get_bias_level(wcd939x->component) ==
  4752. SND_SOC_BIAS_OFF))) {
  4753. msm_cdc_set_supplies_lpm_mode(wcd939x->dev,
  4754. wcd939x->supplies,
  4755. pdata->regulator,
  4756. pdata->num_supplies,
  4757. true);
  4758. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask);
  4759. if (msm_cdc_is_ondemand_supply(wcd939x->dev, wcd939x->supplies, pdata->regulator,
  4760. pdata->num_supplies, "cdc-vdd-px")) {
  4761. if (msm_cdc_supply_supports_retention_mode(wcd939x->dev, wcd939x->supplies,
  4762. pdata->regulator, pdata->num_supplies, "cdc-vdd-px") &&
  4763. msm_cdc_check_supply_vote(wcd939x->dev, wcd939x->supplies,
  4764. pdata->regulator, pdata->num_supplies, "cdc-vdd-px")) {
  4765. ret = msm_cdc_disable_ondemand_supply(wcd939x->dev,
  4766. wcd939x->supplies, pdata->regulator,
  4767. pdata->num_supplies, "cdc-vdd-px");
  4768. if (ret) {
  4769. dev_dbg(dev, "%s: vdd px supply suspend failed!\n",
  4770. __func__);
  4771. }
  4772. }
  4773. }
  4774. }
  4775. return 0;
  4776. }
  4777. static int wcd939x_resume(struct device *dev)
  4778. {
  4779. int ret = 0;
  4780. struct wcd939x_priv *wcd939x = NULL;
  4781. struct wcd939x_pdata *pdata = NULL;
  4782. if (!dev)
  4783. return -ENODEV;
  4784. wcd939x = dev_get_drvdata(dev);
  4785. if (!wcd939x)
  4786. return -EINVAL;
  4787. pdata = dev_get_platdata(wcd939x->dev);
  4788. if (!pdata) {
  4789. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4790. return -EINVAL;
  4791. }
  4792. if (msm_cdc_is_ondemand_supply(wcd939x->dev, wcd939x->supplies, pdata->regulator,
  4793. pdata->num_supplies, "cdc-vdd-px")) {
  4794. if (msm_cdc_supply_supports_retention_mode(wcd939x->dev, wcd939x->supplies,
  4795. pdata->regulator, pdata->num_supplies, "cdc-vdd-px") &&
  4796. !msm_cdc_check_supply_vote(wcd939x->dev, wcd939x->supplies,
  4797. pdata->regulator, pdata->num_supplies, "cdc-vdd-px")) {
  4798. ret = msm_cdc_enable_ondemand_supply(wcd939x->dev, wcd939x->supplies,
  4799. pdata->regulator, pdata->num_supplies, "cdc-vdd-px");
  4800. if (ret) {
  4801. dev_dbg(dev, "%s: vdd px supply resume failed!\n",
  4802. __func__);
  4803. }
  4804. }
  4805. }
  4806. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask)) {
  4807. msm_cdc_set_supplies_lpm_mode(wcd939x->dev,
  4808. wcd939x->supplies,
  4809. pdata->regulator,
  4810. pdata->num_supplies,
  4811. false);
  4812. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask);
  4813. }
  4814. return 0;
  4815. }
  4816. static const struct dev_pm_ops wcd939x_dev_pm_ops = {
  4817. .suspend_late = wcd939x_suspend,
  4818. .resume_early = wcd939x_resume,
  4819. };
  4820. #endif
  4821. static struct platform_driver wcd939x_codec_driver = {
  4822. .probe = wcd939x_probe,
  4823. .remove = wcd939x_remove,
  4824. .driver = {
  4825. .name = "wcd939x_codec",
  4826. .owner = THIS_MODULE,
  4827. .of_match_table = of_match_ptr(wcd939x_dt_match),
  4828. #ifdef CONFIG_PM_SLEEP
  4829. .pm = &wcd939x_dev_pm_ops,
  4830. #endif
  4831. .suppress_bind_attrs = true,
  4832. },
  4833. };
  4834. module_platform_driver(wcd939x_codec_driver);
  4835. MODULE_DESCRIPTION("WCD939X Codec driver");
  4836. MODULE_LICENSE("GPL v2");