All gen III chipsets use Direct-DMA mechanism to copy Spectral reports to
the Host for further processing. This mechanism involves ring and buffer
management in the Host, FW, and uCode, where improper/incomplete DMA and
improper tail update issues are seen. DBR framework provides support to
debug such issues. Add Spectral control path support to facilitate the
configuration of these debug options.
CRs-Fixed: 2478596 2478595
Change-Id: I094616c4137145389b6984ccab933e5ebd0aa1ab
8db4b4ac32