lpass-cdc-va-macro.c 78 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/init.h>
  7. #include <linux/clk.h>
  8. #include <linux/io.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/regmap.h>
  11. #include <linux/regulator/consumer.h>
  12. #include <sound/soc.h>
  13. #include <sound/soc-dapm.h>
  14. #include <sound/tlv.h>
  15. #include <linux/pm_runtime.h>
  16. #include <asoc/msm-cdc-pinctrl.h>
  17. #include <soc/swr-common.h>
  18. #include <soc/swr-wcd.h>
  19. #include <dsp/digital-cdc-rsc-mgr.h>
  20. #include "lpass-cdc.h"
  21. #include "lpass-cdc-registers.h"
  22. #include "lpass-cdc-clk-rsc.h"
  23. /* pm runtime auto suspend timer in msecs */
  24. #define VA_AUTO_SUSPEND_DELAY 100 /* delay in msec */
  25. #define LPASS_CDC_VA_MACRO_MAX_OFFSET 0x1000
  26. #define LPASS_CDC_VA_MACRO_NUM_DECIMATORS 4
  27. #define LPASS_CDC_VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  28. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  29. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  30. #define LPASS_CDC_VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  31. SNDRV_PCM_FMTBIT_S24_LE |\
  32. SNDRV_PCM_FMTBIT_S24_3LE)
  33. #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
  34. #define CF_MIN_3DB_4HZ 0x0
  35. #define CF_MIN_3DB_75HZ 0x1
  36. #define CF_MIN_3DB_150HZ 0x2
  37. #define LPASS_CDC_VA_MACRO_DMIC_SAMPLE_RATE_UNDEFINED 0
  38. #define LPASS_CDC_VA_MACRO_MCLK_FREQ 9600000
  39. #define LPASS_CDC_VA_MACRO_TX_PATH_OFFSET \
  40. (LPASS_CDC_VA_TX1_TX_PATH_CTL - LPASS_CDC_VA_TX0_TX_PATH_CTL)
  41. #define LPASS_CDC_VA_MACRO_TX_DMIC_CLK_DIV_MASK 0x0E
  42. #define LPASS_CDC_VA_MACRO_TX_DMIC_CLK_DIV_SHFT 0x01
  43. #define LPASS_CDC_VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF
  44. #define LPASS_CDC_VA_MACRO_ADC_MUX_CFG_OFFSET 0x8
  45. #define LPASS_CDC_VA_MACRO_ADC_MODE_CFG0_SHIFT 1
  46. #define LPASS_CDC_VA_TX_DMIC_UNMUTE_DELAY_MS 40
  47. #define LPASS_CDC_VA_TX_AMIC_UNMUTE_DELAY_MS 100
  48. #define LPASS_CDC_VA_TX_DMIC_HPF_DELAY_MS 300
  49. #define LPASS_CDC_VA_TX_AMIC_HPF_DELAY_MS 300
  50. #define MAX_RETRY_ATTEMPTS 500
  51. #define LPASS_CDC_VA_MACRO_SWR_STRING_LEN 80
  52. #define LPASS_CDC_VA_MACRO_CHILD_DEVICES_MAX 3
  53. static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
  54. static int va_tx_unmute_delay = LPASS_CDC_VA_TX_DMIC_UNMUTE_DELAY_MS;
  55. module_param(va_tx_unmute_delay, int, 0664);
  56. MODULE_PARM_DESC(va_tx_unmute_delay, "delay to unmute the tx path");
  57. static int lpass_cdc_va_macro_core_vote(void *handle, bool enable);
  58. enum {
  59. LPASS_CDC_VA_MACRO_AIF_INVALID = 0,
  60. LPASS_CDC_VA_MACRO_AIF1_CAP,
  61. LPASS_CDC_VA_MACRO_AIF2_CAP,
  62. LPASS_CDC_VA_MACRO_AIF3_CAP,
  63. LPASS_CDC_VA_MACRO_MAX_DAIS,
  64. };
  65. enum {
  66. LPASS_CDC_VA_MACRO_DEC0,
  67. LPASS_CDC_VA_MACRO_DEC1,
  68. LPASS_CDC_VA_MACRO_DEC2,
  69. LPASS_CDC_VA_MACRO_DEC3,
  70. LPASS_CDC_VA_MACRO_DEC_MAX,
  71. };
  72. enum {
  73. LPASS_CDC_VA_MACRO_CLK_DIV_2,
  74. LPASS_CDC_VA_MACRO_CLK_DIV_3,
  75. LPASS_CDC_VA_MACRO_CLK_DIV_4,
  76. LPASS_CDC_VA_MACRO_CLK_DIV_6,
  77. LPASS_CDC_VA_MACRO_CLK_DIV_8,
  78. LPASS_CDC_VA_MACRO_CLK_DIV_16,
  79. };
  80. enum {
  81. MSM_DMIC,
  82. SWR_MIC,
  83. };
  84. enum {
  85. TX_MCLK,
  86. VA_MCLK,
  87. };
  88. struct va_mute_work {
  89. struct lpass_cdc_va_macro_priv *va_priv;
  90. u32 decimator;
  91. struct delayed_work dwork;
  92. };
  93. struct hpf_work {
  94. struct lpass_cdc_va_macro_priv *va_priv;
  95. u8 decimator;
  96. u8 hpf_cut_off_freq;
  97. struct delayed_work dwork;
  98. };
  99. /* Hold instance to soundwire platform device */
  100. struct lpass_cdc_va_macro_swr_ctrl_data {
  101. struct platform_device *va_swr_pdev;
  102. };
  103. struct lpass_cdc_va_macro_swr_ctrl_platform_data {
  104. void *handle; /* holds codec private data */
  105. int (*read)(void *handle, int reg);
  106. int (*write)(void *handle, int reg, int val);
  107. int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
  108. int (*clk)(void *handle, bool enable);
  109. int (*core_vote)(void *handle, bool enable);
  110. int (*handle_irq)(void *handle,
  111. irqreturn_t (*swrm_irq_handler)(int irq,
  112. void *data),
  113. void *swrm_handle,
  114. int action);
  115. };
  116. struct lpass_cdc_va_macro_priv {
  117. struct device *dev;
  118. bool dec_active[LPASS_CDC_VA_MACRO_NUM_DECIMATORS];
  119. bool va_without_decimation;
  120. struct clk *lpass_audio_hw_vote;
  121. struct mutex mclk_lock;
  122. struct mutex swr_clk_lock;
  123. struct mutex wlock;
  124. struct snd_soc_component *component;
  125. struct hpf_work va_hpf_work[LPASS_CDC_VA_MACRO_NUM_DECIMATORS];
  126. struct va_mute_work va_mute_dwork[LPASS_CDC_VA_MACRO_NUM_DECIMATORS];
  127. unsigned long active_ch_mask[LPASS_CDC_VA_MACRO_MAX_DAIS];
  128. unsigned long active_ch_cnt[LPASS_CDC_VA_MACRO_MAX_DAIS];
  129. u16 dmic_clk_div;
  130. u16 va_mclk_users;
  131. int swr_clk_users;
  132. bool reset_swr;
  133. struct device_node *va_swr_gpio_p;
  134. struct lpass_cdc_va_macro_swr_ctrl_data *swr_ctrl_data;
  135. struct lpass_cdc_va_macro_swr_ctrl_platform_data swr_plat_data;
  136. struct work_struct lpass_cdc_va_macro_add_child_devices_work;
  137. int child_count;
  138. u16 mclk_mux_sel;
  139. char __iomem *va_io_base;
  140. char __iomem *va_island_mode_muxsel;
  141. struct platform_device *pdev_child_devices
  142. [LPASS_CDC_VA_MACRO_CHILD_DEVICES_MAX];
  143. struct regulator *micb_supply;
  144. u32 micb_voltage;
  145. u32 micb_current;
  146. u32 version;
  147. u32 is_used_va_swr_gpio;
  148. int micb_users;
  149. u16 default_clk_id;
  150. u16 clk_id;
  151. int tx_swr_clk_cnt;
  152. int va_swr_clk_cnt;
  153. int va_clk_status;
  154. int tx_clk_status;
  155. bool lpi_enable;
  156. bool clk_div_switch;
  157. int dec_mode[LPASS_CDC_VA_MACRO_NUM_DECIMATORS];
  158. int pcm_rate[LPASS_CDC_VA_MACRO_NUM_DECIMATORS];
  159. int dapm_tx_clk_status;
  160. u16 current_clk_id;
  161. bool dev_up;
  162. bool pre_dev_up;
  163. bool swr_dmic_enable;
  164. bool use_lpi_mixer_control;
  165. int wlock_holders;
  166. };
  167. static int lpass_cdc_va_macro_wake_enable(struct lpass_cdc_va_macro_priv *va_priv,
  168. bool wake_enable)
  169. {
  170. int ret = 0;
  171. mutex_lock(&va_priv->wlock);
  172. if (wake_enable) {
  173. if (va_priv->wlock_holders++ == 0) {
  174. dev_dbg(va_priv->dev, "%s: pm wake\n", __func__);
  175. pm_stay_awake(va_priv->dev);
  176. }
  177. } else {
  178. if (--va_priv->wlock_holders == 0) {
  179. dev_dbg(va_priv->dev, "%s: pm release\n", __func__);
  180. pm_relax(va_priv->dev);
  181. }
  182. if (va_priv->wlock_holders < 0)
  183. va_priv->wlock_holders = 0;
  184. }
  185. mutex_unlock(&va_priv->wlock);
  186. return ret;
  187. }
  188. static bool lpass_cdc_va_macro_get_data(struct snd_soc_component *component,
  189. struct device **va_dev,
  190. struct lpass_cdc_va_macro_priv **va_priv,
  191. const char *func_name)
  192. {
  193. *va_dev = lpass_cdc_get_device_ptr(component->dev, VA_MACRO);
  194. if (!(*va_dev)) {
  195. dev_err_ratelimited(component->dev,
  196. "%s: null device for macro!\n", func_name);
  197. return false;
  198. }
  199. *va_priv = dev_get_drvdata((*va_dev));
  200. if (!(*va_priv) || !(*va_priv)->component) {
  201. dev_err_ratelimited(component->dev,
  202. "%s: priv is null for macro!\n", func_name);
  203. return false;
  204. }
  205. return true;
  206. }
  207. static int lpass_cdc_va_macro_clk_div_get(struct snd_soc_component *component)
  208. {
  209. struct device *va_dev = NULL;
  210. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  211. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  212. &va_priv, __func__))
  213. return -EINVAL;
  214. if (va_priv->clk_div_switch &&
  215. (va_priv->dmic_clk_div == LPASS_CDC_VA_MACRO_CLK_DIV_16))
  216. return LPASS_CDC_VA_MACRO_CLK_DIV_4;
  217. return (int)va_priv->dmic_clk_div;
  218. }
  219. static int lpass_cdc_va_macro_mclk_enable(
  220. struct lpass_cdc_va_macro_priv *va_priv,
  221. bool mclk_enable, bool dapm)
  222. {
  223. struct regmap *regmap = dev_get_regmap(va_priv->dev->parent, NULL);
  224. int ret = 0;
  225. if (regmap == NULL) {
  226. dev_err_ratelimited(va_priv->dev, "%s: regmap is NULL\n", __func__);
  227. return -EINVAL;
  228. }
  229. dev_dbg(va_priv->dev, "%s: mclk_enable = %u, dapm = %d clk_users= %d\n",
  230. __func__, mclk_enable, dapm, va_priv->va_mclk_users);
  231. mutex_lock(&va_priv->mclk_lock);
  232. if (mclk_enable) {
  233. ret = lpass_cdc_va_macro_core_vote(va_priv, true);
  234. if (ret < 0) {
  235. dev_err_ratelimited(va_priv->dev,
  236. "%s: va request core vote failed\n",
  237. __func__);
  238. goto exit;
  239. }
  240. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  241. va_priv->default_clk_id,
  242. va_priv->clk_id,
  243. true);
  244. lpass_cdc_va_macro_core_vote(va_priv, false);
  245. if (ret < 0) {
  246. dev_err_ratelimited(va_priv->dev,
  247. "%s: va request clock en failed\n",
  248. __func__);
  249. goto exit;
  250. }
  251. lpass_cdc_clk_rsc_fs_gen_request(va_priv->dev,
  252. true);
  253. if (va_priv->va_mclk_users == 0) {
  254. regcache_mark_dirty(regmap);
  255. regcache_sync_region(regmap,
  256. VA_START_OFFSET,
  257. VA_MAX_OFFSET);
  258. }
  259. va_priv->va_mclk_users++;
  260. } else {
  261. if (va_priv->va_mclk_users <= 0) {
  262. dev_err_ratelimited(va_priv->dev, "%s: clock already disabled\n",
  263. __func__);
  264. va_priv->va_mclk_users = 0;
  265. goto exit;
  266. }
  267. va_priv->va_mclk_users--;
  268. lpass_cdc_clk_rsc_fs_gen_request(va_priv->dev,
  269. false);
  270. ret = lpass_cdc_va_macro_core_vote(va_priv, true);
  271. if (ret < 0) {
  272. dev_err_ratelimited(va_priv->dev,
  273. "%s: va request core vote failed\n",
  274. __func__);
  275. }
  276. lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  277. va_priv->default_clk_id,
  278. va_priv->clk_id,
  279. false);
  280. if (!ret)
  281. lpass_cdc_va_macro_core_vote(va_priv, false);
  282. }
  283. exit:
  284. mutex_unlock(&va_priv->mclk_lock);
  285. return ret;
  286. }
  287. static int lpass_cdc_va_macro_event_handler(struct snd_soc_component *component,
  288. u16 event, u32 data)
  289. {
  290. struct device *va_dev = NULL;
  291. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  292. int retry_cnt = MAX_RETRY_ATTEMPTS;
  293. int ret = 0;
  294. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  295. &va_priv, __func__))
  296. return -EINVAL;
  297. switch (event) {
  298. case LPASS_CDC_MACRO_EVT_WAIT_VA_CLK_RESET:
  299. while ((va_priv->va_mclk_users != 0) && (retry_cnt != 0)) {
  300. dev_dbg_ratelimited(va_dev, "%s:retry_cnt: %d\n",
  301. __func__, retry_cnt);
  302. /*
  303. * Userspace takes 10 seconds to close
  304. * the session when pcm_start fails due to concurrency
  305. * with PDR/SSR. Loop and check every 20ms till 10
  306. * seconds for va_mclk user count to get reset to 0
  307. * which ensures userspace teardown is done and SSR
  308. * powerup seq can proceed.
  309. */
  310. msleep(20);
  311. retry_cnt--;
  312. }
  313. if (retry_cnt == 0)
  314. dev_err_ratelimited(va_dev,
  315. "%s: va_mclk_users non-zero, SSR fail!!\n",
  316. __func__);
  317. break;
  318. case LPASS_CDC_MACRO_EVT_PRE_SSR_UP:
  319. va_priv->pre_dev_up = true;
  320. /* enable&disable VA_CORE_CLK to reset GFMUX reg */
  321. ret = lpass_cdc_va_macro_core_vote(va_priv, true);
  322. if (ret < 0) {
  323. dev_err_ratelimited(va_priv->dev,
  324. "%s: va request core vote failed\n",
  325. __func__);
  326. break;
  327. }
  328. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  329. va_priv->default_clk_id,
  330. va_priv->clk_id, true);
  331. if (ret < 0)
  332. dev_err_ratelimited(va_priv->dev,
  333. "%s, failed to enable clk, ret:%d\n",
  334. __func__, ret);
  335. else
  336. lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  337. va_priv->default_clk_id,
  338. va_priv->clk_id, false);
  339. lpass_cdc_va_macro_core_vote(va_priv, false);
  340. break;
  341. case LPASS_CDC_MACRO_EVT_SSR_UP:
  342. /* reset swr after ssr/pdr */
  343. va_priv->reset_swr = true;
  344. va_priv->dev_up = true;
  345. if (va_priv->swr_ctrl_data)
  346. swrm_wcd_notify(
  347. va_priv->swr_ctrl_data[0].va_swr_pdev,
  348. SWR_DEVICE_SSR_UP, NULL);
  349. break;
  350. case LPASS_CDC_MACRO_EVT_CLK_RESET:
  351. lpass_cdc_rsc_clk_reset(va_dev, VA_CORE_CLK);
  352. break;
  353. case LPASS_CDC_MACRO_EVT_SSR_DOWN:
  354. va_priv->pre_dev_up = false;
  355. va_priv->dev_up = false;
  356. if (va_priv->swr_ctrl_data) {
  357. swrm_wcd_notify(
  358. va_priv->swr_ctrl_data[0].va_swr_pdev,
  359. SWR_DEVICE_SSR_DOWN, NULL);
  360. }
  361. if ((!pm_runtime_enabled(va_dev) ||
  362. !pm_runtime_suspended(va_dev))) {
  363. ret = lpass_cdc_runtime_suspend(va_dev);
  364. if (!ret) {
  365. pm_runtime_disable(va_dev);
  366. pm_runtime_set_suspended(va_dev);
  367. pm_runtime_enable(va_dev);
  368. }
  369. }
  370. break;
  371. default:
  372. break;
  373. }
  374. return 0;
  375. }
  376. static int lpass_cdc_va_macro_swr_clk_event(struct snd_soc_dapm_widget *w,
  377. struct snd_kcontrol *kcontrol, int event)
  378. {
  379. struct snd_soc_component *component =
  380. snd_soc_dapm_to_component(w->dapm);
  381. struct device *va_dev = NULL;
  382. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  383. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  384. &va_priv, __func__))
  385. return -EINVAL;
  386. dev_dbg(va_dev, "%s: event = %d\n", __func__, event);
  387. switch (event) {
  388. case SND_SOC_DAPM_PRE_PMU:
  389. va_priv->va_swr_clk_cnt++;
  390. break;
  391. case SND_SOC_DAPM_POST_PMD:
  392. va_priv->va_swr_clk_cnt--;
  393. break;
  394. default:
  395. break;
  396. }
  397. return 0;
  398. }
  399. static int lpass_cdc_va_macro_swr_pwr_event(struct snd_soc_dapm_widget *w,
  400. struct snd_kcontrol *kcontrol, int event)
  401. {
  402. struct snd_soc_component *component =
  403. snd_soc_dapm_to_component(w->dapm);
  404. int ret = 0;
  405. struct device *va_dev = NULL;
  406. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  407. bool vote_err = false;
  408. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  409. &va_priv, __func__))
  410. return -EINVAL;
  411. dev_dbg(va_dev, "%s: event = %d\n",__func__, event);
  412. switch (event) {
  413. case SND_SOC_DAPM_PRE_PMU:
  414. dev_dbg(component->dev,
  415. "%s: va_swr_clk_cnt %d, tx_swr_clk_cnt %d, tx_clk_status %d\n",
  416. __func__, va_priv->va_swr_clk_cnt,
  417. va_priv->tx_swr_clk_cnt, va_priv->tx_clk_status);
  418. if (va_priv->current_clk_id == VA_CORE_CLK) {
  419. return 0;
  420. } else if ( va_priv->va_swr_clk_cnt != 0 &&
  421. va_priv->tx_clk_status) {
  422. ret = lpass_cdc_va_macro_core_vote(va_priv, true);
  423. if (ret < 0) {
  424. dev_err_ratelimited(va_priv->dev,
  425. "%s: va request core vote failed\n",
  426. __func__);
  427. break;
  428. }
  429. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  430. va_priv->default_clk_id,
  431. VA_CORE_CLK,
  432. true);
  433. lpass_cdc_va_macro_core_vote(va_priv, false);
  434. if (ret) {
  435. dev_dbg(component->dev,
  436. "%s: request clock VA_CLK enable failed\n",
  437. __func__);
  438. break;
  439. }
  440. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  441. va_priv->default_clk_id,
  442. TX_CORE_CLK,
  443. false);
  444. if (ret) {
  445. dev_dbg(component->dev,
  446. "%s: request clock TX_CLK disable failed\n",
  447. __func__);
  448. lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  449. va_priv->default_clk_id,
  450. VA_CORE_CLK,
  451. false);
  452. break;
  453. }
  454. va_priv->current_clk_id = VA_CORE_CLK;
  455. }
  456. break;
  457. case SND_SOC_DAPM_POST_PMD:
  458. if (va_priv->current_clk_id == VA_CORE_CLK) {
  459. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  460. va_priv->default_clk_id,
  461. TX_CORE_CLK,
  462. true);
  463. if (ret) {
  464. dev_err_ratelimited(component->dev,
  465. "%s: request clock TX_CLK enable failed\n",
  466. __func__);
  467. if (va_priv->dev_up)
  468. break;
  469. }
  470. ret = lpass_cdc_va_macro_core_vote(va_priv, true);
  471. if (ret < 0) {
  472. dev_err_ratelimited(va_priv->dev,
  473. "%s: va request core vote failed\n",
  474. __func__);
  475. if (va_priv->dev_up)
  476. break;
  477. vote_err = true;
  478. }
  479. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  480. va_priv->default_clk_id,
  481. VA_CORE_CLK,
  482. false);
  483. if (!vote_err)
  484. lpass_cdc_va_macro_core_vote(va_priv, false);
  485. if (ret) {
  486. dev_err_ratelimited(component->dev,
  487. "%s: request clock VA_CLK disable failed\n",
  488. __func__);
  489. if (va_priv->dev_up)
  490. lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  491. va_priv->default_clk_id,
  492. TX_CORE_CLK,
  493. false);
  494. break;
  495. }
  496. va_priv->current_clk_id = TX_CORE_CLK;
  497. }
  498. break;
  499. default:
  500. dev_err_ratelimited(va_priv->dev,
  501. "%s: invalid DAPM event %d\n", __func__, event);
  502. ret = -EINVAL;
  503. }
  504. return ret;
  505. }
  506. static int lpass_cdc_va_macro_tx_swr_clk_event(struct snd_soc_dapm_widget *w,
  507. struct snd_kcontrol *kcontrol, int event)
  508. {
  509. struct device *va_dev = NULL;
  510. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  511. struct snd_soc_component *component =
  512. snd_soc_dapm_to_component(w->dapm);
  513. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  514. &va_priv, __func__))
  515. return -EINVAL;
  516. if (SND_SOC_DAPM_EVENT_ON(event))
  517. ++va_priv->tx_swr_clk_cnt;
  518. if (SND_SOC_DAPM_EVENT_OFF(event))
  519. --va_priv->tx_swr_clk_cnt;
  520. return 0;
  521. }
  522. static int lpass_cdc_va_macro_mclk_event(struct snd_soc_dapm_widget *w,
  523. struct snd_kcontrol *kcontrol, int event)
  524. {
  525. struct snd_soc_component *component =
  526. snd_soc_dapm_to_component(w->dapm);
  527. int ret = 0;
  528. struct device *va_dev = NULL;
  529. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  530. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  531. &va_priv, __func__))
  532. return -EINVAL;
  533. dev_dbg(va_dev, "%s: event = %d\n", __func__, event);
  534. switch (event) {
  535. case SND_SOC_DAPM_PRE_PMU:
  536. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  537. va_priv->default_clk_id,
  538. TX_CORE_CLK,
  539. true);
  540. if (!ret)
  541. va_priv->dapm_tx_clk_status++;
  542. if (!va_priv->use_lpi_mixer_control) {
  543. ret = lpass_cdc_va_macro_mclk_enable(va_priv, 1, true);
  544. } else {
  545. if (va_priv->lpi_enable)
  546. ret = lpass_cdc_va_macro_mclk_enable(va_priv, 1, true);
  547. else
  548. ret = lpass_cdc_tx_mclk_enable(component, 1);
  549. }
  550. break;
  551. case SND_SOC_DAPM_POST_PMD:
  552. if (!va_priv->use_lpi_mixer_control) {
  553. lpass_cdc_va_macro_mclk_enable(va_priv, 0, true);
  554. } else {
  555. if (va_priv->lpi_enable)
  556. lpass_cdc_va_macro_mclk_enable(va_priv, 0, true);
  557. else
  558. lpass_cdc_tx_mclk_enable(component, 0);
  559. }
  560. if (va_priv->dapm_tx_clk_status > 0) {
  561. lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  562. va_priv->default_clk_id,
  563. TX_CORE_CLK,
  564. false);
  565. va_priv->dapm_tx_clk_status--;
  566. }
  567. break;
  568. default:
  569. dev_err_ratelimited(va_priv->dev,
  570. "%s: invalid DAPM event %d\n", __func__, event);
  571. ret = -EINVAL;
  572. }
  573. return ret;
  574. }
  575. static int lpass_cdc_va_macro_tx_va_mclk_enable(
  576. struct lpass_cdc_va_macro_priv *va_priv,
  577. struct regmap *regmap, int clk_type,
  578. bool enable)
  579. {
  580. int ret = 0, clk_tx_ret = 0;
  581. dev_dbg(va_priv->dev,
  582. "%s: clock type %s, enable: %s tx_mclk_users: %d\n",
  583. __func__, (clk_type ? "VA_MCLK" : "TX_MCLK"),
  584. (enable ? "enable" : "disable"), va_priv->va_mclk_users);
  585. if (enable) {
  586. if (va_priv->swr_clk_users == 0) {
  587. msm_cdc_pinctrl_select_active_state(
  588. va_priv->va_swr_gpio_p);
  589. msm_cdc_pinctrl_set_wakeup_capable(
  590. va_priv->va_swr_gpio_p, false);
  591. }
  592. clk_tx_ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  593. TX_CORE_CLK,
  594. TX_CORE_CLK,
  595. true);
  596. if (clk_type == TX_MCLK) {
  597. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  598. TX_CORE_CLK,
  599. TX_CORE_CLK,
  600. true);
  601. if (ret < 0) {
  602. if (va_priv->swr_clk_users == 0)
  603. msm_cdc_pinctrl_select_sleep_state(
  604. va_priv->va_swr_gpio_p);
  605. dev_err_ratelimited(va_priv->dev,
  606. "%s: swr request clk failed\n",
  607. __func__);
  608. goto done;
  609. }
  610. lpass_cdc_clk_rsc_fs_gen_request(va_priv->dev,
  611. true);
  612. }
  613. if (clk_type == VA_MCLK) {
  614. ret = lpass_cdc_va_macro_mclk_enable(va_priv, 1, true);
  615. if (ret < 0) {
  616. if (va_priv->swr_clk_users == 0)
  617. msm_cdc_pinctrl_select_sleep_state(
  618. va_priv->va_swr_gpio_p);
  619. dev_err_ratelimited(va_priv->dev,
  620. "%s: request clock enable failed\n",
  621. __func__);
  622. goto done;
  623. }
  624. }
  625. if (va_priv->swr_clk_users == 0) {
  626. dev_dbg(va_priv->dev, "%s: reset_swr: %d\n",
  627. __func__, va_priv->reset_swr);
  628. if (va_priv->reset_swr)
  629. regmap_update_bits(regmap,
  630. LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
  631. 0x02, 0x02);
  632. regmap_update_bits(regmap,
  633. LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
  634. 0x01, 0x01);
  635. if (va_priv->reset_swr)
  636. regmap_update_bits(regmap,
  637. LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
  638. 0x02, 0x00);
  639. va_priv->reset_swr = false;
  640. }
  641. if (!clk_tx_ret)
  642. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  643. TX_CORE_CLK,
  644. TX_CORE_CLK,
  645. false);
  646. va_priv->swr_clk_users++;
  647. } else {
  648. if (va_priv->swr_clk_users <= 0) {
  649. dev_err_ratelimited(va_priv->dev,
  650. "va swrm clock users already 0\n");
  651. va_priv->swr_clk_users = 0;
  652. return 0;
  653. }
  654. clk_tx_ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  655. TX_CORE_CLK,
  656. TX_CORE_CLK,
  657. true);
  658. va_priv->swr_clk_users--;
  659. if (va_priv->swr_clk_users == 0)
  660. regmap_update_bits(regmap,
  661. LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
  662. 0x01, 0x00);
  663. if (clk_type == VA_MCLK)
  664. lpass_cdc_va_macro_mclk_enable(va_priv, 0, true);
  665. if (clk_type == TX_MCLK) {
  666. lpass_cdc_clk_rsc_fs_gen_request(va_priv->dev,
  667. false);
  668. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  669. TX_CORE_CLK,
  670. TX_CORE_CLK,
  671. false);
  672. if (ret < 0) {
  673. if (va_priv->swr_clk_users == 0) {
  674. msm_cdc_pinctrl_select_sleep_state(
  675. va_priv->va_swr_gpio_p);
  676. }
  677. dev_err_ratelimited(va_priv->dev,
  678. "%s: swr request clk failed\n",
  679. __func__);
  680. goto done;
  681. }
  682. }
  683. if (!clk_tx_ret)
  684. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  685. TX_CORE_CLK,
  686. TX_CORE_CLK,
  687. false);
  688. if (va_priv->swr_clk_users == 0) {
  689. msm_cdc_pinctrl_select_sleep_state(
  690. va_priv->va_swr_gpio_p);
  691. msm_cdc_pinctrl_set_wakeup_capable(
  692. va_priv->va_swr_gpio_p, true);
  693. }
  694. }
  695. return 0;
  696. done:
  697. if (!clk_tx_ret)
  698. lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  699. TX_CORE_CLK,
  700. TX_CORE_CLK,
  701. false);
  702. return ret;
  703. }
  704. static int lpass_cdc_va_macro_core_vote(void *handle, bool enable)
  705. {
  706. int rc = 0;
  707. struct lpass_cdc_va_macro_priv *va_priv =
  708. (struct lpass_cdc_va_macro_priv *) handle;
  709. if (va_priv == NULL) {
  710. pr_err_ratelimited("%s: va priv data is NULL\n", __func__);
  711. return -EINVAL;
  712. }
  713. if (!va_priv->pre_dev_up && enable) {
  714. pr_err("%s: adsp is not up\n", __func__);
  715. return -EINVAL;
  716. }
  717. if (enable) {
  718. pm_runtime_get_sync(va_priv->dev);
  719. if (lpass_cdc_check_core_votes(va_priv->dev)) {
  720. rc = 0;
  721. } else {
  722. rc = -ENOTSYNC;
  723. }
  724. } else {
  725. pm_runtime_put_autosuspend(va_priv->dev);
  726. pm_runtime_mark_last_busy(va_priv->dev);
  727. }
  728. return rc;
  729. }
  730. static int lpass_cdc_va_macro_swrm_clock(void *handle, bool enable)
  731. {
  732. struct lpass_cdc_va_macro_priv *va_priv =
  733. (struct lpass_cdc_va_macro_priv *) handle;
  734. struct regmap *regmap = dev_get_regmap(va_priv->dev->parent, NULL);
  735. int ret = 0;
  736. if (regmap == NULL) {
  737. dev_err_ratelimited(va_priv->dev, "%s: regmap is NULL\n", __func__);
  738. return -EINVAL;
  739. }
  740. mutex_lock(&va_priv->swr_clk_lock);
  741. dev_dbg(va_priv->dev,
  742. "%s: swrm clock %s tx_swr_clk_cnt: %d va_swr_clk_cnt: %d\n",
  743. __func__, (enable ? "enable" : "disable"),
  744. va_priv->tx_swr_clk_cnt, va_priv->va_swr_clk_cnt);
  745. if (enable) {
  746. pm_runtime_get_sync(va_priv->dev);
  747. if (va_priv->va_swr_clk_cnt && !va_priv->tx_swr_clk_cnt) {
  748. ret = lpass_cdc_va_macro_tx_va_mclk_enable(va_priv,
  749. regmap, VA_MCLK, enable);
  750. if (ret) {
  751. pm_runtime_mark_last_busy(va_priv->dev);
  752. pm_runtime_put_autosuspend(va_priv->dev);
  753. goto done;
  754. }
  755. va_priv->va_clk_status++;
  756. } else {
  757. ret = lpass_cdc_va_macro_tx_va_mclk_enable(va_priv,
  758. regmap, TX_MCLK, enable);
  759. if (ret) {
  760. pm_runtime_mark_last_busy(va_priv->dev);
  761. pm_runtime_put_autosuspend(va_priv->dev);
  762. goto done;
  763. }
  764. va_priv->tx_clk_status++;
  765. }
  766. pm_runtime_mark_last_busy(va_priv->dev);
  767. pm_runtime_put_autosuspend(va_priv->dev);
  768. } else {
  769. if (va_priv->va_clk_status && !va_priv->tx_clk_status) {
  770. ret = lpass_cdc_va_macro_tx_va_mclk_enable(va_priv,
  771. regmap,
  772. VA_MCLK, enable);
  773. if (ret)
  774. goto done;
  775. --va_priv->va_clk_status;
  776. } else if (!va_priv->va_clk_status && va_priv->tx_clk_status) {
  777. ret = lpass_cdc_va_macro_tx_va_mclk_enable(va_priv,
  778. regmap,
  779. TX_MCLK, enable);
  780. if (ret)
  781. goto done;
  782. --va_priv->tx_clk_status;
  783. } else if (va_priv->va_clk_status && va_priv->tx_clk_status) {
  784. if (!va_priv->va_swr_clk_cnt &&
  785. va_priv->tx_swr_clk_cnt) {
  786. ret = lpass_cdc_va_macro_tx_va_mclk_enable(
  787. va_priv, regmap,
  788. VA_MCLK, enable);
  789. if (ret)
  790. goto done;
  791. --va_priv->va_clk_status;
  792. } else {
  793. ret = lpass_cdc_va_macro_tx_va_mclk_enable(
  794. va_priv, regmap,
  795. TX_MCLK, enable);
  796. if (ret)
  797. goto done;
  798. --va_priv->tx_clk_status;
  799. }
  800. } else {
  801. dev_dbg(va_priv->dev,
  802. "%s: Both clocks are disabled\n", __func__);
  803. }
  804. }
  805. dev_dbg(va_priv->dev,
  806. "%s: swrm clock usr %d tx_clk_sts_cnt: %d va_clk_sts_cnt: %d\n",
  807. __func__, va_priv->swr_clk_users, va_priv->tx_clk_status,
  808. va_priv->va_clk_status);
  809. done:
  810. mutex_unlock(&va_priv->swr_clk_lock);
  811. return ret;
  812. }
  813. static bool is_amic_enabled(struct snd_soc_component *component, int decimator)
  814. {
  815. u16 adc_mux_reg = 0;
  816. bool ret = false;
  817. struct device *va_dev = NULL;
  818. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  819. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  820. &va_priv, __func__))
  821. return ret;
  822. adc_mux_reg = LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1 +
  823. LPASS_CDC_VA_MACRO_ADC_MUX_CFG_OFFSET * decimator;
  824. if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
  825. if (!va_priv->swr_dmic_enable)
  826. return true;
  827. }
  828. return ret;
  829. }
  830. static void lpass_cdc_va_macro_tx_hpf_corner_freq_callback(
  831. struct work_struct *work)
  832. {
  833. struct delayed_work *hpf_delayed_work;
  834. struct hpf_work *hpf_work;
  835. struct lpass_cdc_va_macro_priv *va_priv;
  836. struct snd_soc_component *component;
  837. u16 dec_cfg_reg, hpf_gate_reg;
  838. u8 hpf_cut_off_freq;
  839. u16 adc_reg = 0, adc_n = 0;
  840. hpf_delayed_work = to_delayed_work(work);
  841. hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
  842. va_priv = hpf_work->va_priv;
  843. component = va_priv->component;
  844. hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
  845. dec_cfg_reg = LPASS_CDC_VA_TX0_TX_PATH_CFG0 +
  846. LPASS_CDC_VA_MACRO_TX_PATH_OFFSET * hpf_work->decimator;
  847. hpf_gate_reg = LPASS_CDC_VA_TX0_TX_PATH_SEC2 +
  848. LPASS_CDC_VA_MACRO_TX_PATH_OFFSET * hpf_work->decimator;
  849. dev_dbg(va_priv->dev, "%s: decimator %u hpf_cut_of_freq 0x%x\n",
  850. __func__, hpf_work->decimator, hpf_cut_off_freq);
  851. if (is_amic_enabled(component, hpf_work->decimator)) {
  852. adc_reg = LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0 +
  853. LPASS_CDC_VA_MACRO_ADC_MUX_CFG_OFFSET *
  854. hpf_work->decimator;
  855. adc_n = snd_soc_component_read(component, adc_reg) &
  856. LPASS_CDC_VA_MACRO_SWR_MIC_MUX_SEL_MASK;
  857. /* analog mic clear TX hold */
  858. lpass_cdc_clear_amic_tx_hold(component->dev, adc_n);
  859. snd_soc_component_update_bits(component,
  860. dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,
  861. hpf_cut_off_freq << 5);
  862. snd_soc_component_update_bits(component, hpf_gate_reg,
  863. 0x03, 0x02);
  864. /* Add delay between toggle hpf gate based on sample rate */
  865. switch (va_priv->pcm_rate[hpf_work->decimator]) {
  866. case 0:
  867. usleep_range(125, 130);
  868. break;
  869. case 1:
  870. usleep_range(62, 65);
  871. break;
  872. case 3:
  873. usleep_range(31, 32);
  874. break;
  875. case 4:
  876. usleep_range(20, 21);
  877. break;
  878. case 5:
  879. usleep_range(10, 11);
  880. break;
  881. case 6:
  882. usleep_range(5, 6);
  883. break;
  884. default:
  885. usleep_range(125, 130);
  886. }
  887. snd_soc_component_update_bits(component, hpf_gate_reg,
  888. 0x03, 0x01);
  889. } else {
  890. snd_soc_component_update_bits(component,
  891. dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,
  892. hpf_cut_off_freq << 5);
  893. snd_soc_component_update_bits(component, hpf_gate_reg,
  894. 0x02, 0x02);
  895. /* Minimum 1 clk cycle delay is required as per HW spec */
  896. usleep_range(1000, 1010);
  897. snd_soc_component_update_bits(component, hpf_gate_reg,
  898. 0x02, 0x00);
  899. }
  900. lpass_cdc_va_macro_wake_enable(va_priv, 0);
  901. }
  902. static void lpass_cdc_va_macro_mute_update_callback(struct work_struct *work)
  903. {
  904. struct va_mute_work *va_mute_dwork;
  905. struct snd_soc_component *component = NULL;
  906. struct lpass_cdc_va_macro_priv *va_priv;
  907. struct delayed_work *delayed_work;
  908. u16 tx_vol_ctl_reg, decimator;
  909. delayed_work = to_delayed_work(work);
  910. va_mute_dwork = container_of(delayed_work, struct va_mute_work, dwork);
  911. va_priv = va_mute_dwork->va_priv;
  912. component = va_priv->component;
  913. decimator = va_mute_dwork->decimator;
  914. tx_vol_ctl_reg =
  915. LPASS_CDC_VA_TX0_TX_PATH_CTL +
  916. LPASS_CDC_VA_MACRO_TX_PATH_OFFSET * decimator;
  917. snd_soc_component_update_bits(component, tx_vol_ctl_reg, 0x10, 0x00);
  918. dev_dbg(va_priv->dev, "%s: decimator %u unmute\n",
  919. __func__, decimator);
  920. lpass_cdc_va_macro_wake_enable(va_priv, 0);
  921. }
  922. static int lpass_cdc_va_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
  923. struct snd_ctl_elem_value *ucontrol)
  924. {
  925. struct snd_soc_dapm_widget *widget =
  926. snd_soc_dapm_kcontrol_widget(kcontrol);
  927. struct snd_soc_component *component =
  928. snd_soc_dapm_to_component(widget->dapm);
  929. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  930. unsigned int val;
  931. u16 mic_sel_reg, dmic_clk_reg;
  932. struct device *va_dev = NULL;
  933. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  934. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  935. &va_priv, __func__))
  936. return -EINVAL;
  937. val = ucontrol->value.enumerated.item[0];
  938. if (val > e->items - 1)
  939. return -EINVAL;
  940. dev_dbg(component->dev, "%s: wname: %s, val: 0x%x\n", __func__,
  941. widget->name, val);
  942. switch (e->reg) {
  943. case LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0:
  944. mic_sel_reg = LPASS_CDC_VA_TX0_TX_PATH_CFG0;
  945. break;
  946. case LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0:
  947. mic_sel_reg = LPASS_CDC_VA_TX1_TX_PATH_CFG0;
  948. break;
  949. case LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0:
  950. mic_sel_reg = LPASS_CDC_VA_TX2_TX_PATH_CFG0;
  951. break;
  952. case LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0:
  953. mic_sel_reg = LPASS_CDC_VA_TX3_TX_PATH_CFG0;
  954. break;
  955. default:
  956. dev_err_ratelimited(component->dev, "%s: e->reg: 0x%x not expected\n",
  957. __func__, e->reg);
  958. return -EINVAL;
  959. }
  960. if (strnstr(widget->name, "SMIC", strlen(widget->name))) {
  961. if (val != 0) {
  962. if (!va_priv->swr_dmic_enable) {
  963. snd_soc_component_update_bits(component,
  964. mic_sel_reg,
  965. 1 << 7, 0x0 << 7);
  966. } else {
  967. snd_soc_component_update_bits(component,
  968. mic_sel_reg,
  969. 1 << 7, 0x1 << 7);
  970. snd_soc_component_update_bits(component,
  971. LPASS_CDC_VA_TOP_CSR_DMIC_CFG,
  972. 0x80, 0x00);
  973. dmic_clk_reg =
  974. LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0 +
  975. ((val - 5)/2) * 4;
  976. snd_soc_component_update_bits(component,
  977. dmic_clk_reg,
  978. 0x0E, va_priv->dmic_clk_div << 0x1);
  979. }
  980. }
  981. } else {
  982. /* DMIC selected */
  983. if (val != 0)
  984. snd_soc_component_update_bits(component, mic_sel_reg,
  985. 1 << 7, 1 << 7);
  986. }
  987. return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
  988. }
  989. static int lpass_cdc_va_macro_lpi_get(struct snd_kcontrol *kcontrol,
  990. struct snd_ctl_elem_value *ucontrol)
  991. {
  992. struct snd_soc_component *component =
  993. snd_soc_kcontrol_component(kcontrol);
  994. struct device *va_dev = NULL;
  995. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  996. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  997. &va_priv, __func__))
  998. return -EINVAL;
  999. ucontrol->value.integer.value[0] = va_priv->lpi_enable;
  1000. return 0;
  1001. }
  1002. static int lpass_cdc_va_macro_lpi_put(struct snd_kcontrol *kcontrol,
  1003. struct snd_ctl_elem_value *ucontrol)
  1004. {
  1005. struct snd_soc_component *component =
  1006. snd_soc_kcontrol_component(kcontrol);
  1007. struct device *va_dev = NULL;
  1008. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  1009. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  1010. &va_priv, __func__))
  1011. return -EINVAL;
  1012. va_priv->lpi_enable = ucontrol->value.integer.value[0];
  1013. return 0;
  1014. }
  1015. static int lpass_cdc_va_macro_swr_dmic_get(struct snd_kcontrol *kcontrol,
  1016. struct snd_ctl_elem_value *ucontrol)
  1017. {
  1018. struct snd_soc_component *component =
  1019. snd_soc_kcontrol_component(kcontrol);
  1020. struct device *va_dev = NULL;
  1021. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  1022. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  1023. &va_priv, __func__))
  1024. return -EINVAL;
  1025. ucontrol->value.integer.value[0] = va_priv->swr_dmic_enable;
  1026. return 0;
  1027. }
  1028. static int lpass_cdc_va_macro_swr_dmic_put(struct snd_kcontrol *kcontrol,
  1029. struct snd_ctl_elem_value *ucontrol)
  1030. {
  1031. struct snd_soc_component *component =
  1032. snd_soc_kcontrol_component(kcontrol);
  1033. struct device *va_dev = NULL;
  1034. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  1035. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  1036. &va_priv, __func__))
  1037. return -EINVAL;
  1038. va_priv->swr_dmic_enable = ucontrol->value.integer.value[0];
  1039. return 0;
  1040. }
  1041. static int lpass_cdc_va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
  1042. struct snd_ctl_elem_value *ucontrol)
  1043. {
  1044. struct snd_soc_dapm_widget *widget =
  1045. snd_soc_dapm_kcontrol_widget(kcontrol);
  1046. struct snd_soc_component *component =
  1047. snd_soc_dapm_to_component(widget->dapm);
  1048. struct soc_multi_mixer_control *mixer =
  1049. ((struct soc_multi_mixer_control *)kcontrol->private_value);
  1050. u32 dai_id = widget->shift;
  1051. u32 dec_id = mixer->shift;
  1052. struct device *va_dev = NULL;
  1053. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  1054. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  1055. &va_priv, __func__))
  1056. return -EINVAL;
  1057. if (test_bit(dec_id, &va_priv->active_ch_mask[dai_id]))
  1058. ucontrol->value.integer.value[0] = 1;
  1059. else
  1060. ucontrol->value.integer.value[0] = 0;
  1061. return 0;
  1062. }
  1063. static int lpass_cdc_va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
  1064. struct snd_ctl_elem_value *ucontrol)
  1065. {
  1066. struct snd_soc_dapm_widget *widget =
  1067. snd_soc_dapm_kcontrol_widget(kcontrol);
  1068. struct snd_soc_component *component =
  1069. snd_soc_dapm_to_component(widget->dapm);
  1070. struct snd_soc_dapm_update *update = NULL;
  1071. struct soc_multi_mixer_control *mixer =
  1072. ((struct soc_multi_mixer_control *)kcontrol->private_value);
  1073. u32 dai_id = widget->shift;
  1074. u32 dec_id = mixer->shift;
  1075. u32 enable = ucontrol->value.integer.value[0];
  1076. struct device *va_dev = NULL;
  1077. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  1078. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  1079. &va_priv, __func__))
  1080. return -EINVAL;
  1081. if (enable) {
  1082. if (test_bit(dec_id, &va_priv->active_ch_mask[dai_id])) {
  1083. dev_err_ratelimited(component->dev, "%s: channel is already enabled, dec_id = %d, dai_id = %d\n",
  1084. __func__, dec_id, dai_id);
  1085. } else {
  1086. set_bit(dec_id, &va_priv->active_ch_mask[dai_id]);
  1087. va_priv->active_ch_cnt[dai_id]++;
  1088. }
  1089. } else {
  1090. if (!test_bit(dec_id, &va_priv->active_ch_mask[dai_id])) {
  1091. dev_err_ratelimited(component->dev, "%s: channel is already disabled, dec_id = %d, dai_id = %d\n",
  1092. __func__, dec_id, dai_id);
  1093. } else {
  1094. va_priv->active_ch_cnt[dai_id]--;
  1095. clear_bit(dec_id, &va_priv->active_ch_mask[dai_id]);
  1096. }
  1097. }
  1098. snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
  1099. return 0;
  1100. }
  1101. static int lpass_cdc_va_macro_enable_dmic(struct snd_soc_dapm_widget *w,
  1102. struct snd_kcontrol *kcontrol, int event, u16 adc_mux0_cfg)
  1103. {
  1104. struct snd_soc_component *component =
  1105. snd_soc_dapm_to_component(w->dapm);
  1106. unsigned int dmic = 0;
  1107. dmic = (snd_soc_component_read(component, adc_mux0_cfg) >> 4) - 1;
  1108. dev_dbg(component->dev, "%s: event %d DMIC%d\n",
  1109. __func__, event, dmic);
  1110. switch (event) {
  1111. case SND_SOC_DAPM_PRE_PMU:
  1112. lpass_cdc_dmic_clk_enable(component, (u32)dmic, (u32)DMIC_VA, true);
  1113. break;
  1114. case SND_SOC_DAPM_POST_PMD:
  1115. lpass_cdc_dmic_clk_enable(component, (u32)dmic, (u32)DMIC_VA, false);
  1116. break;
  1117. }
  1118. return 0;
  1119. }
  1120. static int lpass_cdc_va_macro_enable_dec(struct snd_soc_dapm_widget *w,
  1121. struct snd_kcontrol *kcontrol, int event)
  1122. {
  1123. struct snd_soc_component *component =
  1124. snd_soc_dapm_to_component(w->dapm);
  1125. unsigned int decimator;
  1126. u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg;
  1127. u16 tx_gain_ctl_reg;
  1128. u8 hpf_cut_off_freq;
  1129. u16 adc_mux_reg = 0;
  1130. u16 adc_mux0_reg = 0;
  1131. u16 tx_fs_reg = 0;
  1132. struct device *va_dev = NULL;
  1133. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  1134. int hpf_delay = LPASS_CDC_VA_TX_DMIC_HPF_DELAY_MS;
  1135. int unmute_delay = LPASS_CDC_VA_TX_DMIC_UNMUTE_DELAY_MS;
  1136. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  1137. &va_priv, __func__))
  1138. return -EINVAL;
  1139. decimator = w->shift;
  1140. dev_dbg(va_dev, "%s(): widget = %s decimator = %u\n", __func__,
  1141. w->name, decimator);
  1142. tx_vol_ctl_reg = LPASS_CDC_VA_TX0_TX_PATH_CTL +
  1143. LPASS_CDC_VA_MACRO_TX_PATH_OFFSET * decimator;
  1144. hpf_gate_reg = LPASS_CDC_VA_TX0_TX_PATH_SEC2 +
  1145. LPASS_CDC_VA_MACRO_TX_PATH_OFFSET * decimator;
  1146. dec_cfg_reg = LPASS_CDC_VA_TX0_TX_PATH_CFG0 +
  1147. LPASS_CDC_VA_MACRO_TX_PATH_OFFSET * decimator;
  1148. tx_gain_ctl_reg = LPASS_CDC_VA_TX0_TX_VOL_CTL +
  1149. LPASS_CDC_VA_MACRO_TX_PATH_OFFSET * decimator;
  1150. adc_mux_reg = LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1 +
  1151. LPASS_CDC_VA_MACRO_ADC_MUX_CFG_OFFSET * decimator;
  1152. adc_mux0_reg = LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0 +
  1153. LPASS_CDC_VA_MACRO_ADC_MUX_CFG_OFFSET * decimator;
  1154. tx_fs_reg = LPASS_CDC_VA_TX0_TX_PATH_CTL +
  1155. LPASS_CDC_VA_MACRO_TX_PATH_OFFSET * decimator;
  1156. va_priv->pcm_rate[decimator] = (snd_soc_component_read(component,
  1157. tx_fs_reg) & 0x0F);
  1158. if(!is_amic_enabled(component, decimator))
  1159. lpass_cdc_va_macro_enable_dmic(w, kcontrol, event, adc_mux0_reg);
  1160. switch (event) {
  1161. case SND_SOC_DAPM_PRE_PMU:
  1162. snd_soc_component_update_bits(component,
  1163. dec_cfg_reg, 0x06, va_priv->dec_mode[decimator] <<
  1164. LPASS_CDC_VA_MACRO_ADC_MODE_CFG0_SHIFT);
  1165. /* Enable TX PGA Mute */
  1166. snd_soc_component_update_bits(component,
  1167. tx_vol_ctl_reg, 0x10, 0x10);
  1168. break;
  1169. case SND_SOC_DAPM_POST_PMU:
  1170. /* Enable TX CLK */
  1171. snd_soc_component_update_bits(component,
  1172. tx_vol_ctl_reg, 0x20, 0x20);
  1173. if (!is_amic_enabled(component, decimator)) {
  1174. snd_soc_component_update_bits(component,
  1175. hpf_gate_reg, 0x01, 0x00);
  1176. /*
  1177. * Minimum 1 clk cycle delay is required as per HW spec
  1178. */
  1179. usleep_range(1000, 1010);
  1180. }
  1181. hpf_cut_off_freq = (snd_soc_component_read(
  1182. component, dec_cfg_reg) &
  1183. TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
  1184. va_priv->va_hpf_work[decimator].hpf_cut_off_freq =
  1185. hpf_cut_off_freq;
  1186. if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
  1187. snd_soc_component_update_bits(component, dec_cfg_reg,
  1188. TX_HPF_CUT_OFF_FREQ_MASK,
  1189. CF_MIN_3DB_150HZ << 5);
  1190. }
  1191. if (is_amic_enabled(component, decimator)) {
  1192. hpf_delay = LPASS_CDC_VA_TX_AMIC_HPF_DELAY_MS;
  1193. unmute_delay = LPASS_CDC_VA_TX_AMIC_UNMUTE_DELAY_MS;
  1194. if (va_tx_unmute_delay < unmute_delay)
  1195. va_tx_unmute_delay = unmute_delay;
  1196. }
  1197. snd_soc_component_update_bits(component,
  1198. hpf_gate_reg, 0x03, 0x02);
  1199. if (!is_amic_enabled(component, decimator))
  1200. snd_soc_component_update_bits(component,
  1201. hpf_gate_reg, 0x03, 0x00);
  1202. /*
  1203. * Minimum 1 clk cycle delay is required as per HW spec
  1204. */
  1205. usleep_range(1000, 1010);
  1206. snd_soc_component_update_bits(component,
  1207. hpf_gate_reg, 0x03, 0x01);
  1208. /*
  1209. * 6ms delay is required as per HW spec
  1210. */
  1211. usleep_range(6000, 6010);
  1212. /* schedule work queue to Remove Mute */
  1213. lpass_cdc_va_macro_wake_enable(va_priv, 1);
  1214. queue_delayed_work(system_freezable_wq,
  1215. &va_priv->va_mute_dwork[decimator].dwork,
  1216. msecs_to_jiffies(va_tx_unmute_delay));
  1217. if (va_priv->va_hpf_work[decimator].hpf_cut_off_freq !=
  1218. CF_MIN_3DB_150HZ) {
  1219. lpass_cdc_va_macro_wake_enable(va_priv, 1);
  1220. queue_delayed_work(system_freezable_wq,
  1221. &va_priv->va_hpf_work[decimator].dwork,
  1222. msecs_to_jiffies(hpf_delay));
  1223. }
  1224. /* apply gain after decimator is enabled */
  1225. snd_soc_component_write(component, tx_gain_ctl_reg,
  1226. snd_soc_component_read(component, tx_gain_ctl_reg));
  1227. break;
  1228. case SND_SOC_DAPM_PRE_PMD:
  1229. hpf_cut_off_freq =
  1230. va_priv->va_hpf_work[decimator].hpf_cut_off_freq;
  1231. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  1232. 0x10, 0x10);
  1233. if (cancel_delayed_work_sync(
  1234. &va_priv->va_hpf_work[decimator].dwork)) {
  1235. if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
  1236. snd_soc_component_update_bits(component,
  1237. dec_cfg_reg,
  1238. TX_HPF_CUT_OFF_FREQ_MASK,
  1239. hpf_cut_off_freq << 5);
  1240. if (is_amic_enabled(component, decimator))
  1241. snd_soc_component_update_bits(component,
  1242. hpf_gate_reg,
  1243. 0x03, 0x02);
  1244. else
  1245. snd_soc_component_update_bits(component,
  1246. hpf_gate_reg,
  1247. 0x03, 0x03);
  1248. /*
  1249. * Minimum 1 clk cycle delay is required
  1250. * as per HW spec
  1251. */
  1252. usleep_range(1000, 1010);
  1253. snd_soc_component_update_bits(component,
  1254. hpf_gate_reg,
  1255. 0x03, 0x01);
  1256. }
  1257. }
  1258. lpass_cdc_va_macro_wake_enable(va_priv, 0);
  1259. cancel_delayed_work_sync(
  1260. &va_priv->va_mute_dwork[decimator].dwork);
  1261. lpass_cdc_va_macro_wake_enable(va_priv, 0);
  1262. break;
  1263. case SND_SOC_DAPM_POST_PMD:
  1264. /* Disable TX CLK */
  1265. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  1266. 0x20, 0x00);
  1267. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  1268. 0x40, 0x40);
  1269. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  1270. 0x40, 0x00);
  1271. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  1272. 0x10, 0x00);
  1273. break;
  1274. }
  1275. return 0;
  1276. }
  1277. static int lpass_cdc_va_macro_enable_tx(struct snd_soc_dapm_widget *w,
  1278. struct snd_kcontrol *kcontrol, int event)
  1279. {
  1280. struct snd_soc_component *component =
  1281. snd_soc_dapm_to_component(w->dapm);
  1282. struct device *va_dev = NULL;
  1283. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  1284. int ret = 0;
  1285. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  1286. &va_priv, __func__))
  1287. return -EINVAL;
  1288. dev_dbg(va_dev, "%s: event = %d\n", __func__, event);
  1289. switch (event) {
  1290. case SND_SOC_DAPM_POST_PMU:
  1291. if (va_priv->dapm_tx_clk_status > 0) {
  1292. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  1293. va_priv->default_clk_id,
  1294. TX_CORE_CLK,
  1295. false);
  1296. va_priv->dapm_tx_clk_status--;
  1297. }
  1298. break;
  1299. case SND_SOC_DAPM_PRE_PMD:
  1300. ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
  1301. va_priv->default_clk_id,
  1302. TX_CORE_CLK,
  1303. true);
  1304. if (!ret)
  1305. va_priv->dapm_tx_clk_status++;
  1306. break;
  1307. default:
  1308. dev_err_ratelimited(va_priv->dev,
  1309. "%s: invalid DAPM event %d\n", __func__, event);
  1310. ret = -EINVAL;
  1311. break;
  1312. }
  1313. return ret;
  1314. }
  1315. static int lpass_cdc_va_macro_enable_micbias(struct snd_soc_dapm_widget *w,
  1316. struct snd_kcontrol *kcontrol, int event)
  1317. {
  1318. struct snd_soc_component *component =
  1319. snd_soc_dapm_to_component(w->dapm);
  1320. struct device *va_dev = NULL;
  1321. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  1322. int ret = 0;
  1323. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  1324. &va_priv, __func__))
  1325. return -EINVAL;
  1326. if (!va_priv->micb_supply) {
  1327. dev_err_ratelimited(va_dev,
  1328. "%s:regulator not provided in dtsi\n", __func__);
  1329. return -EINVAL;
  1330. }
  1331. switch (event) {
  1332. case SND_SOC_DAPM_PRE_PMU:
  1333. if (va_priv->micb_users++ > 0)
  1334. return 0;
  1335. ret = regulator_set_voltage(va_priv->micb_supply,
  1336. va_priv->micb_voltage,
  1337. va_priv->micb_voltage);
  1338. if (ret) {
  1339. dev_err_ratelimited(va_dev, "%s: Setting voltage failed, err = %d\n",
  1340. __func__, ret);
  1341. return ret;
  1342. }
  1343. ret = regulator_set_load(va_priv->micb_supply,
  1344. va_priv->micb_current);
  1345. if (ret) {
  1346. dev_err_ratelimited(va_dev, "%s: Setting current failed, err = %d\n",
  1347. __func__, ret);
  1348. return ret;
  1349. }
  1350. ret = regulator_enable(va_priv->micb_supply);
  1351. if (ret) {
  1352. dev_err_ratelimited(va_dev, "%s: regulator enable failed, err = %d\n",
  1353. __func__, ret);
  1354. return ret;
  1355. }
  1356. break;
  1357. case SND_SOC_DAPM_POST_PMD:
  1358. if (--va_priv->micb_users > 0)
  1359. return 0;
  1360. if (va_priv->micb_users < 0) {
  1361. va_priv->micb_users = 0;
  1362. dev_dbg(va_dev, "%s: regulator already disabled\n",
  1363. __func__);
  1364. return 0;
  1365. }
  1366. ret = regulator_disable(va_priv->micb_supply);
  1367. if (ret) {
  1368. dev_err_ratelimited(va_dev, "%s: regulator disable failed, err = %d\n",
  1369. __func__, ret);
  1370. return ret;
  1371. }
  1372. regulator_set_voltage(va_priv->micb_supply, 0,
  1373. va_priv->micb_voltage);
  1374. regulator_set_load(va_priv->micb_supply, 0);
  1375. break;
  1376. }
  1377. return 0;
  1378. }
  1379. static inline int lpass_cdc_va_macro_path_get(const char *wname,
  1380. unsigned int *path_num)
  1381. {
  1382. int ret = 0;
  1383. char *widget_name = NULL;
  1384. char *w_name = NULL;
  1385. char *path_num_char = NULL;
  1386. char *path_name = NULL;
  1387. widget_name = kstrndup(wname, 10, GFP_KERNEL);
  1388. if (!widget_name)
  1389. return -EINVAL;
  1390. w_name = widget_name;
  1391. path_name = strsep(&widget_name, " ");
  1392. if (!path_name) {
  1393. pr_err_ratelimited("%s: Invalid widget name = %s\n",
  1394. __func__, widget_name);
  1395. ret = -EINVAL;
  1396. goto err;
  1397. }
  1398. path_num_char = strpbrk(path_name, "01234567");
  1399. if (!path_num_char) {
  1400. pr_err_ratelimited("%s: va path index not found\n",
  1401. __func__);
  1402. ret = -EINVAL;
  1403. goto err;
  1404. }
  1405. ret = kstrtouint(path_num_char, 10, path_num);
  1406. if (ret < 0)
  1407. pr_err_ratelimited("%s: Invalid tx path = %s\n",
  1408. __func__, w_name);
  1409. err:
  1410. kfree(w_name);
  1411. return ret;
  1412. }
  1413. static int lpass_cdc_va_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
  1414. struct snd_ctl_elem_value *ucontrol)
  1415. {
  1416. struct snd_soc_component *component =
  1417. snd_soc_kcontrol_component(kcontrol);
  1418. struct lpass_cdc_va_macro_priv *priv = NULL;
  1419. struct device *va_dev = NULL;
  1420. int ret = 0;
  1421. int path = 0;
  1422. if (!lpass_cdc_va_macro_get_data(component, &va_dev, &priv, __func__))
  1423. return -EINVAL;
  1424. ret = lpass_cdc_va_macro_path_get(kcontrol->id.name, &path);
  1425. if (ret)
  1426. return ret;
  1427. ucontrol->value.integer.value[0] = priv->dec_mode[path];
  1428. return 0;
  1429. }
  1430. static int lpass_cdc_va_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
  1431. struct snd_ctl_elem_value *ucontrol)
  1432. {
  1433. struct snd_soc_component *component =
  1434. snd_soc_kcontrol_component(kcontrol);
  1435. struct lpass_cdc_va_macro_priv *priv = NULL;
  1436. struct device *va_dev = NULL;
  1437. int value = ucontrol->value.integer.value[0];
  1438. int ret = 0;
  1439. int path = 0;
  1440. if (!lpass_cdc_va_macro_get_data(component, &va_dev, &priv, __func__))
  1441. return -EINVAL;
  1442. ret = lpass_cdc_va_macro_path_get(kcontrol->id.name, &path);
  1443. if (ret)
  1444. return ret;
  1445. priv->dec_mode[path] = value;
  1446. return 0;
  1447. }
  1448. static int lpass_cdc_va_macro_hw_params(struct snd_pcm_substream *substream,
  1449. struct snd_pcm_hw_params *params,
  1450. struct snd_soc_dai *dai)
  1451. {
  1452. int tx_fs_rate = -EINVAL;
  1453. struct snd_soc_component *component = dai->component;
  1454. u32 decimator, sample_rate;
  1455. u16 tx_fs_reg = 0;
  1456. struct device *va_dev = NULL;
  1457. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  1458. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  1459. &va_priv, __func__))
  1460. return -EINVAL;
  1461. dev_dbg(va_dev,
  1462. "%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__,
  1463. dai->name, dai->id, params_rate(params),
  1464. params_channels(params));
  1465. sample_rate = params_rate(params);
  1466. if (sample_rate > 16000)
  1467. va_priv->clk_div_switch = true;
  1468. else
  1469. va_priv->clk_div_switch = false;
  1470. switch (sample_rate) {
  1471. case 8000:
  1472. tx_fs_rate = 0;
  1473. break;
  1474. case 16000:
  1475. tx_fs_rate = 1;
  1476. break;
  1477. case 32000:
  1478. tx_fs_rate = 3;
  1479. break;
  1480. case 48000:
  1481. tx_fs_rate = 4;
  1482. break;
  1483. case 96000:
  1484. tx_fs_rate = 5;
  1485. break;
  1486. case 192000:
  1487. tx_fs_rate = 6;
  1488. break;
  1489. case 384000:
  1490. tx_fs_rate = 7;
  1491. break;
  1492. default:
  1493. dev_err_ratelimited(va_dev, "%s: Invalid TX sample rate: %d\n",
  1494. __func__, params_rate(params));
  1495. return -EINVAL;
  1496. }
  1497. for_each_set_bit(decimator, &va_priv->active_ch_mask[dai->id],
  1498. LPASS_CDC_VA_MACRO_DEC_MAX) {
  1499. if (decimator >= 0) {
  1500. tx_fs_reg = LPASS_CDC_VA_TX0_TX_PATH_CTL +
  1501. LPASS_CDC_VA_MACRO_TX_PATH_OFFSET * decimator;
  1502. dev_dbg(va_dev, "%s: set DEC%u rate to %u\n",
  1503. __func__, decimator, sample_rate);
  1504. snd_soc_component_update_bits(component, tx_fs_reg,
  1505. 0x0F, tx_fs_rate);
  1506. } else {
  1507. dev_err_ratelimited(va_dev,
  1508. "%s: ERROR: Invalid decimator: %d\n",
  1509. __func__, decimator);
  1510. return -EINVAL;
  1511. }
  1512. }
  1513. return 0;
  1514. }
  1515. static int lpass_cdc_va_macro_get_channel_map(struct snd_soc_dai *dai,
  1516. unsigned int *tx_num, unsigned int *tx_slot,
  1517. unsigned int *rx_num, unsigned int *rx_slot)
  1518. {
  1519. struct snd_soc_component *component = dai->component;
  1520. struct device *va_dev = NULL;
  1521. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  1522. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  1523. &va_priv, __func__))
  1524. return -EINVAL;
  1525. switch (dai->id) {
  1526. case LPASS_CDC_VA_MACRO_AIF1_CAP:
  1527. case LPASS_CDC_VA_MACRO_AIF2_CAP:
  1528. case LPASS_CDC_VA_MACRO_AIF3_CAP:
  1529. *tx_slot = va_priv->active_ch_mask[dai->id];
  1530. *tx_num = va_priv->active_ch_cnt[dai->id];
  1531. break;
  1532. default:
  1533. dev_err_ratelimited(va_dev, "%s: Invalid AIF\n", __func__);
  1534. break;
  1535. }
  1536. return 0;
  1537. }
  1538. static struct snd_soc_dai_ops lpass_cdc_va_macro_dai_ops = {
  1539. .hw_params = lpass_cdc_va_macro_hw_params,
  1540. .get_channel_map = lpass_cdc_va_macro_get_channel_map,
  1541. };
  1542. static struct snd_soc_dai_driver lpass_cdc_va_macro_dai[] = {
  1543. {
  1544. .name = "va_macro_tx1",
  1545. .id = LPASS_CDC_VA_MACRO_AIF1_CAP,
  1546. .capture = {
  1547. .stream_name = "VA_AIF1 Capture",
  1548. .rates = LPASS_CDC_VA_MACRO_RATES,
  1549. .formats = LPASS_CDC_VA_MACRO_FORMATS,
  1550. .rate_max = 192000,
  1551. .rate_min = 8000,
  1552. .channels_min = 1,
  1553. .channels_max = 8,
  1554. },
  1555. .ops = &lpass_cdc_va_macro_dai_ops,
  1556. },
  1557. {
  1558. .name = "va_macro_tx2",
  1559. .id = LPASS_CDC_VA_MACRO_AIF2_CAP,
  1560. .capture = {
  1561. .stream_name = "VA_AIF2 Capture",
  1562. .rates = LPASS_CDC_VA_MACRO_RATES,
  1563. .formats = LPASS_CDC_VA_MACRO_FORMATS,
  1564. .rate_max = 192000,
  1565. .rate_min = 8000,
  1566. .channels_min = 1,
  1567. .channels_max = 8,
  1568. },
  1569. .ops = &lpass_cdc_va_macro_dai_ops,
  1570. },
  1571. {
  1572. .name = "va_macro_tx3",
  1573. .id = LPASS_CDC_VA_MACRO_AIF3_CAP,
  1574. .capture = {
  1575. .stream_name = "VA_AIF3 Capture",
  1576. .rates = LPASS_CDC_VA_MACRO_RATES,
  1577. .formats = LPASS_CDC_VA_MACRO_FORMATS,
  1578. .rate_max = 192000,
  1579. .rate_min = 8000,
  1580. .channels_min = 1,
  1581. .channels_max = 8,
  1582. },
  1583. .ops = &lpass_cdc_va_macro_dai_ops,
  1584. },
  1585. };
  1586. #define STRING(name) #name
  1587. #define LPASS_CDC_VA_MACRO_DAPM_ENUM(name, reg, offset, text) \
  1588. static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
  1589. static const struct snd_kcontrol_new name##_mux = \
  1590. SOC_DAPM_ENUM(STRING(name), name##_enum)
  1591. #define LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(name, reg, offset, text, getname, putname) \
  1592. static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
  1593. static const struct snd_kcontrol_new name##_mux = \
  1594. SOC_DAPM_ENUM_EXT(STRING(name), name##_enum, getname, putname)
  1595. #define LPASS_CDC_VA_MACRO_DAPM_MUX(name, shift, kctl) \
  1596. SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, shift, 0, &kctl##_mux)
  1597. static const char * const adc_mux_text[] = {
  1598. "MSM_DMIC", "SWR_MIC"
  1599. };
  1600. LPASS_CDC_VA_MACRO_DAPM_ENUM(va_dec0, LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1,
  1601. 0, adc_mux_text);
  1602. LPASS_CDC_VA_MACRO_DAPM_ENUM(va_dec1, LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1,
  1603. 0, adc_mux_text);
  1604. LPASS_CDC_VA_MACRO_DAPM_ENUM(va_dec2, LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1,
  1605. 0, adc_mux_text);
  1606. LPASS_CDC_VA_MACRO_DAPM_ENUM(va_dec3, LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1,
  1607. 0, adc_mux_text);
  1608. static const char * const dmic_mux_text[] = {
  1609. "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
  1610. "DMIC4", "DMIC5", "DMIC6", "DMIC7"
  1611. };
  1612. LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_dmic0, LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0,
  1613. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1614. lpass_cdc_va_macro_put_dec_enum);
  1615. LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_dmic1, LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0,
  1616. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1617. lpass_cdc_va_macro_put_dec_enum);
  1618. LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_dmic2, LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0,
  1619. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1620. lpass_cdc_va_macro_put_dec_enum);
  1621. LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_dmic3, LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0,
  1622. 4, dmic_mux_text, snd_soc_dapm_get_enum_double,
  1623. lpass_cdc_va_macro_put_dec_enum);
  1624. static const char * const smic_mux_text[] = {
  1625. "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3",
  1626. "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7",
  1627. "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11"
  1628. };
  1629. LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic0, LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0,
  1630. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1631. lpass_cdc_va_macro_put_dec_enum);
  1632. LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic1, LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0,
  1633. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1634. lpass_cdc_va_macro_put_dec_enum);
  1635. LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic2, LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0,
  1636. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1637. lpass_cdc_va_macro_put_dec_enum);
  1638. LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic3, LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0,
  1639. 0, smic_mux_text, snd_soc_dapm_get_enum_double,
  1640. lpass_cdc_va_macro_put_dec_enum);
  1641. static const struct snd_kcontrol_new va_aif1_cap_mixer[] = {
  1642. SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 1, 0,
  1643. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1644. SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC1, 1, 0,
  1645. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1646. SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC2, 1, 0,
  1647. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1648. SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC3, 1, 0,
  1649. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1650. };
  1651. static const struct snd_kcontrol_new va_aif2_cap_mixer[] = {
  1652. SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 1, 0,
  1653. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1654. SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC1, 1, 0,
  1655. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1656. SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC2, 1, 0,
  1657. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1658. SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC3, 1, 0,
  1659. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1660. };
  1661. static const struct snd_kcontrol_new va_aif3_cap_mixer[] = {
  1662. SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 1, 0,
  1663. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1664. SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC1, 1, 0,
  1665. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1666. SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC2, 1, 0,
  1667. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1668. SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC3, 1, 0,
  1669. lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put),
  1670. };
  1671. static const struct snd_soc_dapm_widget lpass_cdc_va_macro_dapm_widgets[] = {
  1672. SND_SOC_DAPM_AIF_OUT_E("VA_AIF1 CAP", "VA_AIF1 Capture", 0,
  1673. SND_SOC_NOPM, LPASS_CDC_VA_MACRO_AIF1_CAP, 0,
  1674. lpass_cdc_va_macro_enable_tx, SND_SOC_DAPM_POST_PMU |
  1675. SND_SOC_DAPM_PRE_PMD),
  1676. SND_SOC_DAPM_AIF_OUT_E("VA_AIF2 CAP", "VA_AIF2 Capture", 0,
  1677. SND_SOC_NOPM, LPASS_CDC_VA_MACRO_AIF2_CAP, 0,
  1678. lpass_cdc_va_macro_enable_tx, SND_SOC_DAPM_POST_PMU |
  1679. SND_SOC_DAPM_PRE_PMD),
  1680. SND_SOC_DAPM_AIF_OUT_E("VA_AIF3 CAP", "VA_AIF3 Capture", 0,
  1681. SND_SOC_NOPM, LPASS_CDC_VA_MACRO_AIF3_CAP, 0,
  1682. lpass_cdc_va_macro_enable_tx, SND_SOC_DAPM_POST_PMU |
  1683. SND_SOC_DAPM_PRE_PMD),
  1684. SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM,
  1685. LPASS_CDC_VA_MACRO_AIF1_CAP, 0,
  1686. va_aif1_cap_mixer, ARRAY_SIZE(va_aif1_cap_mixer)),
  1687. SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM,
  1688. LPASS_CDC_VA_MACRO_AIF2_CAP, 0,
  1689. va_aif2_cap_mixer, ARRAY_SIZE(va_aif2_cap_mixer)),
  1690. SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM,
  1691. LPASS_CDC_VA_MACRO_AIF3_CAP, 0,
  1692. va_aif3_cap_mixer, ARRAY_SIZE(va_aif3_cap_mixer)),
  1693. LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX0", 0, va_dmic0),
  1694. LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX1", 0, va_dmic1),
  1695. LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX2", 0, va_dmic2),
  1696. LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX3", 0, va_dmic3),
  1697. LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX0", 0, va_smic0),
  1698. LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX1", 0, va_smic1),
  1699. LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX2", 0, va_smic2),
  1700. LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX3", 0, va_smic3),
  1701. SND_SOC_DAPM_INPUT("VA SWR_INPUT"),
  1702. SND_SOC_DAPM_SUPPLY("VA MIC BIAS", SND_SOC_NOPM, 0, 0,
  1703. lpass_cdc_va_macro_enable_micbias,
  1704. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1705. SND_SOC_DAPM_ADC("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0),
  1706. SND_SOC_DAPM_ADC("VA DMIC1", NULL, SND_SOC_NOPM, 0, 0),
  1707. SND_SOC_DAPM_ADC("VA DMIC2", NULL, SND_SOC_NOPM, 0, 0),
  1708. SND_SOC_DAPM_ADC("VA DMIC3", NULL, SND_SOC_NOPM, 0, 0),
  1709. SND_SOC_DAPM_ADC("VA DMIC4", NULL, SND_SOC_NOPM, 0, 0),
  1710. SND_SOC_DAPM_ADC("VA DMIC5", NULL, SND_SOC_NOPM, 0, 0),
  1711. SND_SOC_DAPM_ADC("VA DMIC6", NULL, SND_SOC_NOPM, 0, 0),
  1712. SND_SOC_DAPM_ADC("VA DMIC7", NULL, SND_SOC_NOPM, 0, 0),
  1713. SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 0,
  1714. &va_dec0_mux, lpass_cdc_va_macro_enable_dec,
  1715. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1716. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1717. SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC1, 0,
  1718. &va_dec1_mux, lpass_cdc_va_macro_enable_dec,
  1719. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1720. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1721. SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC2, 0,
  1722. &va_dec2_mux, lpass_cdc_va_macro_enable_dec,
  1723. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1724. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1725. SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC3, 0,
  1726. &va_dec3_mux, lpass_cdc_va_macro_enable_dec,
  1727. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1728. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1729. SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0,
  1730. lpass_cdc_va_macro_mclk_event,
  1731. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1732. SND_SOC_DAPM_SUPPLY_S("VA_SWR_PWR", 0, SND_SOC_NOPM, 0, 0,
  1733. lpass_cdc_va_macro_swr_pwr_event,
  1734. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1735. SND_SOC_DAPM_SUPPLY_S("VA_TX_SWR_CLK", -1, SND_SOC_NOPM, 0, 0,
  1736. lpass_cdc_va_macro_tx_swr_clk_event,
  1737. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1738. SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", -1, SND_SOC_NOPM, 0, 0,
  1739. lpass_cdc_va_macro_swr_clk_event,
  1740. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1741. };
  1742. static const struct snd_soc_dapm_route va_audio_map[] = {
  1743. {"VA_AIF1 CAP", NULL, "VA_MCLK"},
  1744. {"VA_AIF2 CAP", NULL, "VA_MCLK"},
  1745. {"VA_AIF3 CAP", NULL, "VA_MCLK"},
  1746. {"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"},
  1747. {"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"},
  1748. {"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"},
  1749. {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"},
  1750. {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"},
  1751. {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"},
  1752. {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"},
  1753. {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"},
  1754. {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"},
  1755. {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"},
  1756. {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"},
  1757. {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"},
  1758. {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"},
  1759. {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"},
  1760. {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"},
  1761. {"VA DEC0 MUX", "MSM_DMIC", "VA DMIC MUX0"},
  1762. {"VA DMIC MUX0", "DMIC0", "VA DMIC0"},
  1763. {"VA DMIC MUX0", "DMIC1", "VA DMIC1"},
  1764. {"VA DMIC MUX0", "DMIC2", "VA DMIC2"},
  1765. {"VA DMIC MUX0", "DMIC3", "VA DMIC3"},
  1766. {"VA DMIC MUX0", "DMIC4", "VA DMIC4"},
  1767. {"VA DMIC MUX0", "DMIC5", "VA DMIC5"},
  1768. {"VA DMIC MUX0", "DMIC6", "VA DMIC6"},
  1769. {"VA DMIC MUX0", "DMIC7", "VA DMIC7"},
  1770. {"VA DEC0 MUX", "SWR_MIC", "VA SMIC MUX0"},
  1771. {"VA SMIC MUX0", "SWR_MIC0", "VA SWR_INPUT"},
  1772. {"VA SMIC MUX0", "SWR_MIC1", "VA SWR_INPUT"},
  1773. {"VA SMIC MUX0", "SWR_MIC2", "VA SWR_INPUT"},
  1774. {"VA SMIC MUX0", "SWR_MIC3", "VA SWR_INPUT"},
  1775. {"VA SMIC MUX0", "SWR_MIC4", "VA SWR_INPUT"},
  1776. {"VA SMIC MUX0", "SWR_MIC5", "VA SWR_INPUT"},
  1777. {"VA SMIC MUX0", "SWR_MIC6", "VA SWR_INPUT"},
  1778. {"VA SMIC MUX0", "SWR_MIC7", "VA SWR_INPUT"},
  1779. {"VA SMIC MUX0", "SWR_MIC8", "VA SWR_INPUT"},
  1780. {"VA SMIC MUX0", "SWR_MIC9", "VA SWR_INPUT"},
  1781. {"VA SMIC MUX0", "SWR_MIC10", "VA SWR_INPUT"},
  1782. {"VA SMIC MUX0", "SWR_MIC11", "VA SWR_INPUT"},
  1783. {"VA DEC1 MUX", "MSM_DMIC", "VA DMIC MUX1"},
  1784. {"VA DMIC MUX1", "DMIC0", "VA DMIC0"},
  1785. {"VA DMIC MUX1", "DMIC1", "VA DMIC1"},
  1786. {"VA DMIC MUX1", "DMIC2", "VA DMIC2"},
  1787. {"VA DMIC MUX1", "DMIC3", "VA DMIC3"},
  1788. {"VA DMIC MUX1", "DMIC4", "VA DMIC4"},
  1789. {"VA DMIC MUX1", "DMIC5", "VA DMIC5"},
  1790. {"VA DMIC MUX1", "DMIC6", "VA DMIC6"},
  1791. {"VA DMIC MUX1", "DMIC7", "VA DMIC7"},
  1792. {"VA DEC1 MUX", "SWR_MIC", "VA SMIC MUX1"},
  1793. {"VA SMIC MUX1", "SWR_MIC0", "VA SWR_INPUT"},
  1794. {"VA SMIC MUX1", "SWR_MIC1", "VA SWR_INPUT"},
  1795. {"VA SMIC MUX1", "SWR_MIC2", "VA SWR_INPUT"},
  1796. {"VA SMIC MUX1", "SWR_MIC3", "VA SWR_INPUT"},
  1797. {"VA SMIC MUX1", "SWR_MIC4", "VA SWR_INPUT"},
  1798. {"VA SMIC MUX1", "SWR_MIC5", "VA SWR_INPUT"},
  1799. {"VA SMIC MUX1", "SWR_MIC6", "VA SWR_INPUT"},
  1800. {"VA SMIC MUX1", "SWR_MIC7", "VA SWR_INPUT"},
  1801. {"VA SMIC MUX1", "SWR_MIC8", "VA SWR_INPUT"},
  1802. {"VA SMIC MUX1", "SWR_MIC9", "VA SWR_INPUT"},
  1803. {"VA SMIC MUX1", "SWR_MIC10", "VA SWR_INPUT"},
  1804. {"VA SMIC MUX1", "SWR_MIC11", "VA SWR_INPUT"},
  1805. {"VA DEC2 MUX", "MSM_DMIC", "VA DMIC MUX2"},
  1806. {"VA DMIC MUX2", "DMIC0", "VA DMIC0"},
  1807. {"VA DMIC MUX2", "DMIC1", "VA DMIC1"},
  1808. {"VA DMIC MUX2", "DMIC2", "VA DMIC2"},
  1809. {"VA DMIC MUX2", "DMIC3", "VA DMIC3"},
  1810. {"VA DMIC MUX2", "DMIC4", "VA DMIC4"},
  1811. {"VA DMIC MUX2", "DMIC5", "VA DMIC5"},
  1812. {"VA DMIC MUX2", "DMIC6", "VA DMIC6"},
  1813. {"VA DMIC MUX2", "DMIC7", "VA DMIC7"},
  1814. {"VA DEC2 MUX", "SWR_MIC", "VA SMIC MUX2"},
  1815. {"VA SMIC MUX2", "SWR_MIC0", "VA SWR_INPUT"},
  1816. {"VA SMIC MUX2", "SWR_MIC1", "VA SWR_INPUT"},
  1817. {"VA SMIC MUX2", "SWR_MIC2", "VA SWR_INPUT"},
  1818. {"VA SMIC MUX2", "SWR_MIC3", "VA SWR_INPUT"},
  1819. {"VA SMIC MUX2", "SWR_MIC4", "VA SWR_INPUT"},
  1820. {"VA SMIC MUX2", "SWR_MIC5", "VA SWR_INPUT"},
  1821. {"VA SMIC MUX2", "SWR_MIC6", "VA SWR_INPUT"},
  1822. {"VA SMIC MUX2", "SWR_MIC7", "VA SWR_INPUT"},
  1823. {"VA SMIC MUX2", "SWR_MIC8", "VA SWR_INPUT"},
  1824. {"VA SMIC MUX2", "SWR_MIC9", "VA SWR_INPUT"},
  1825. {"VA SMIC MUX2", "SWR_MIC10", "VA SWR_INPUT"},
  1826. {"VA SMIC MUX2", "SWR_MIC11", "VA SWR_INPUT"},
  1827. {"VA DEC3 MUX", "MSM_DMIC", "VA DMIC MUX3"},
  1828. {"VA DMIC MUX3", "DMIC0", "VA DMIC0"},
  1829. {"VA DMIC MUX3", "DMIC1", "VA DMIC1"},
  1830. {"VA DMIC MUX3", "DMIC2", "VA DMIC2"},
  1831. {"VA DMIC MUX3", "DMIC3", "VA DMIC3"},
  1832. {"VA DMIC MUX3", "DMIC4", "VA DMIC4"},
  1833. {"VA DMIC MUX3", "DMIC5", "VA DMIC5"},
  1834. {"VA DMIC MUX3", "DMIC6", "VA DMIC6"},
  1835. {"VA DMIC MUX3", "DMIC7", "VA DMIC7"},
  1836. {"VA DEC3 MUX", "SWR_MIC", "VA SMIC MUX3"},
  1837. {"VA SMIC MUX3", "SWR_MIC0", "VA SWR_INPUT"},
  1838. {"VA SMIC MUX3", "SWR_MIC1", "VA SWR_INPUT"},
  1839. {"VA SMIC MUX3", "SWR_MIC2", "VA SWR_INPUT"},
  1840. {"VA SMIC MUX3", "SWR_MIC3", "VA SWR_INPUT"},
  1841. {"VA SMIC MUX3", "SWR_MIC4", "VA SWR_INPUT"},
  1842. {"VA SMIC MUX3", "SWR_MIC5", "VA SWR_INPUT"},
  1843. {"VA SMIC MUX3", "SWR_MIC6", "VA SWR_INPUT"},
  1844. {"VA SMIC MUX3", "SWR_MIC7", "VA SWR_INPUT"},
  1845. {"VA SMIC MUX3", "SWR_MIC8", "VA SWR_INPUT"},
  1846. {"VA SMIC MUX3", "SWR_MIC9", "VA SWR_INPUT"},
  1847. {"VA SMIC MUX3", "SWR_MIC10", "VA SWR_INPUT"},
  1848. {"VA SMIC MUX3", "SWR_MIC11", "VA SWR_INPUT"},
  1849. {"VA SWR_INPUT", NULL, "VA_SWR_PWR"},
  1850. {"VA SWR_INPUT", NULL, "VA_SWR_CLK"},
  1851. };
  1852. static const char * const dec_mode_mux_text[] = {
  1853. "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
  1854. };
  1855. static const struct soc_enum dec_mode_mux_enum =
  1856. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dec_mode_mux_text),
  1857. dec_mode_mux_text);
  1858. static const struct snd_kcontrol_new lpass_cdc_va_macro_snd_controls[] = {
  1859. SOC_SINGLE_S8_TLV("VA_DEC0 Volume",
  1860. LPASS_CDC_VA_TX0_TX_VOL_CTL,
  1861. -84, 40, digital_gain),
  1862. SOC_SINGLE_S8_TLV("VA_DEC1 Volume",
  1863. LPASS_CDC_VA_TX1_TX_VOL_CTL,
  1864. -84, 40, digital_gain),
  1865. SOC_SINGLE_S8_TLV("VA_DEC2 Volume",
  1866. LPASS_CDC_VA_TX2_TX_VOL_CTL,
  1867. -84, 40, digital_gain),
  1868. SOC_SINGLE_S8_TLV("VA_DEC3 Volume",
  1869. LPASS_CDC_VA_TX3_TX_VOL_CTL,
  1870. -84, 40, digital_gain),
  1871. SOC_SINGLE_EXT("LPI Enable", 0, 0, 1, 0,
  1872. lpass_cdc_va_macro_lpi_get, lpass_cdc_va_macro_lpi_put),
  1873. SOC_SINGLE_EXT("VA_SWR_DMIC Enable", 0, 0, 1, 0,
  1874. lpass_cdc_va_macro_swr_dmic_get, lpass_cdc_va_macro_swr_dmic_put),
  1875. SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode_mux_enum,
  1876. lpass_cdc_va_macro_dec_mode_get, lpass_cdc_va_macro_dec_mode_put),
  1877. SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode_mux_enum,
  1878. lpass_cdc_va_macro_dec_mode_get, lpass_cdc_va_macro_dec_mode_put),
  1879. SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode_mux_enum,
  1880. lpass_cdc_va_macro_dec_mode_get, lpass_cdc_va_macro_dec_mode_put),
  1881. SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode_mux_enum,
  1882. lpass_cdc_va_macro_dec_mode_get, lpass_cdc_va_macro_dec_mode_put),
  1883. };
  1884. static int lpass_cdc_va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,
  1885. struct lpass_cdc_va_macro_priv *va_priv)
  1886. {
  1887. u32 div_factor;
  1888. u32 mclk_rate = LPASS_CDC_VA_MACRO_MCLK_FREQ;
  1889. if (dmic_sample_rate == LPASS_CDC_VA_MACRO_DMIC_SAMPLE_RATE_UNDEFINED ||
  1890. mclk_rate % dmic_sample_rate != 0)
  1891. goto undefined_rate;
  1892. div_factor = mclk_rate / dmic_sample_rate;
  1893. switch (div_factor) {
  1894. case 2:
  1895. va_priv->dmic_clk_div = LPASS_CDC_VA_MACRO_CLK_DIV_2;
  1896. break;
  1897. case 3:
  1898. va_priv->dmic_clk_div = LPASS_CDC_VA_MACRO_CLK_DIV_3;
  1899. break;
  1900. case 4:
  1901. va_priv->dmic_clk_div = LPASS_CDC_VA_MACRO_CLK_DIV_4;
  1902. break;
  1903. case 6:
  1904. va_priv->dmic_clk_div = LPASS_CDC_VA_MACRO_CLK_DIV_6;
  1905. break;
  1906. case 8:
  1907. va_priv->dmic_clk_div = LPASS_CDC_VA_MACRO_CLK_DIV_8;
  1908. break;
  1909. case 16:
  1910. va_priv->dmic_clk_div = LPASS_CDC_VA_MACRO_CLK_DIV_16;
  1911. break;
  1912. default:
  1913. /* Any other DIV factor is invalid */
  1914. goto undefined_rate;
  1915. }
  1916. /* Valid dmic DIV factors */
  1917. dev_dbg(va_priv->dev, "%s: DMIC_DIV = %u, mclk_rate = %u\n",
  1918. __func__, div_factor, mclk_rate);
  1919. return dmic_sample_rate;
  1920. undefined_rate:
  1921. dev_dbg(va_priv->dev, "%s: Invalid rate %d, for mclk %d\n",
  1922. __func__, dmic_sample_rate, mclk_rate);
  1923. dmic_sample_rate = LPASS_CDC_VA_MACRO_DMIC_SAMPLE_RATE_UNDEFINED;
  1924. return dmic_sample_rate;
  1925. }
  1926. static int lpass_cdc_va_macro_init(struct snd_soc_component *component)
  1927. {
  1928. struct snd_soc_dapm_context *dapm =
  1929. snd_soc_component_get_dapm(component);
  1930. int ret, i;
  1931. struct device *va_dev = NULL;
  1932. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  1933. va_dev = lpass_cdc_get_device_ptr(component->dev, VA_MACRO);
  1934. if (!va_dev) {
  1935. dev_err(component->dev,
  1936. "%s: null device for macro!\n", __func__);
  1937. return -EINVAL;
  1938. }
  1939. va_priv = dev_get_drvdata(va_dev);
  1940. if (!va_priv) {
  1941. dev_err(component->dev,
  1942. "%s: priv is null for macro!\n", __func__);
  1943. return -EINVAL;
  1944. }
  1945. va_priv->lpi_enable = false;
  1946. va_priv->swr_dmic_enable = false;
  1947. //va_priv->register_event_listener = false;
  1948. va_priv->version = lpass_cdc_get_version(va_dev);
  1949. ret = snd_soc_dapm_new_controls(dapm,
  1950. lpass_cdc_va_macro_dapm_widgets,
  1951. ARRAY_SIZE(lpass_cdc_va_macro_dapm_widgets));
  1952. if (ret < 0) {
  1953. dev_err(va_dev, "%s: Failed to add controls\n",
  1954. __func__);
  1955. return ret;
  1956. }
  1957. ret = snd_soc_dapm_add_routes(dapm, va_audio_map,
  1958. ARRAY_SIZE(va_audio_map));
  1959. if (ret < 0) {
  1960. dev_err(va_dev, "%s: Failed to add routes\n",
  1961. __func__);
  1962. return ret;
  1963. }
  1964. ret = snd_soc_dapm_new_widgets(dapm->card);
  1965. if (ret < 0) {
  1966. dev_err(va_dev, "%s: Failed to add widgets\n", __func__);
  1967. return ret;
  1968. }
  1969. ret = snd_soc_add_component_controls(component,
  1970. lpass_cdc_va_macro_snd_controls,
  1971. ARRAY_SIZE(lpass_cdc_va_macro_snd_controls));
  1972. if (ret < 0) {
  1973. dev_err(va_dev, "%s: Failed to add snd_ctls\n",
  1974. __func__);
  1975. return ret;
  1976. }
  1977. snd_soc_dapm_ignore_suspend(dapm, "VA_AIF1 Capture");
  1978. snd_soc_dapm_ignore_suspend(dapm, "VA_AIF2 Capture");
  1979. snd_soc_dapm_ignore_suspend(dapm, "VA_AIF3 Capture");
  1980. snd_soc_dapm_ignore_suspend(dapm, "VA SWR_INPUT");
  1981. snd_soc_dapm_sync(dapm);
  1982. va_priv->dev_up = true;
  1983. for (i = 0; i < LPASS_CDC_VA_MACRO_NUM_DECIMATORS; i++) {
  1984. va_priv->va_hpf_work[i].va_priv = va_priv;
  1985. va_priv->va_hpf_work[i].decimator = i;
  1986. INIT_DELAYED_WORK(&va_priv->va_hpf_work[i].dwork,
  1987. lpass_cdc_va_macro_tx_hpf_corner_freq_callback);
  1988. }
  1989. for (i = 0; i < LPASS_CDC_VA_MACRO_NUM_DECIMATORS; i++) {
  1990. va_priv->va_mute_dwork[i].va_priv = va_priv;
  1991. va_priv->va_mute_dwork[i].decimator = i;
  1992. INIT_DELAYED_WORK(&va_priv->va_mute_dwork[i].dwork,
  1993. lpass_cdc_va_macro_mute_update_callback);
  1994. }
  1995. va_priv->component = component;
  1996. snd_soc_component_update_bits(component,
  1997. LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE, 0xCC);
  1998. snd_soc_component_update_bits(component,
  1999. LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE, 0xCC);
  2000. snd_soc_component_update_bits(component,
  2001. LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE, 0xCC);
  2002. return 0;
  2003. }
  2004. static int lpass_cdc_va_macro_deinit(struct snd_soc_component *component)
  2005. {
  2006. struct device *va_dev = NULL;
  2007. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  2008. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  2009. &va_priv, __func__))
  2010. return -EINVAL;
  2011. va_priv->component = NULL;
  2012. return 0;
  2013. }
  2014. static void lpass_cdc_va_macro_add_child_devices(struct work_struct *work)
  2015. {
  2016. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  2017. struct platform_device *pdev = NULL;
  2018. struct device_node *node = NULL;
  2019. struct lpass_cdc_va_macro_swr_ctrl_data *swr_ctrl_data = NULL;
  2020. struct lpass_cdc_va_macro_swr_ctrl_data *temp = NULL;
  2021. int ret = 0;
  2022. u16 count = 0, ctrl_num = 0;
  2023. struct lpass_cdc_va_macro_swr_ctrl_platform_data *platdata = NULL;
  2024. char plat_dev_name[LPASS_CDC_VA_MACRO_SWR_STRING_LEN] = "";
  2025. bool va_swr_master_node = false;
  2026. va_priv = container_of(work, struct lpass_cdc_va_macro_priv,
  2027. lpass_cdc_va_macro_add_child_devices_work);
  2028. if (!va_priv) {
  2029. pr_err("%s: Memory for va_priv does not exist\n",
  2030. __func__);
  2031. return;
  2032. }
  2033. if (!va_priv->dev) {
  2034. pr_err("%s: VA dev does not exist\n", __func__);
  2035. return;
  2036. }
  2037. if (!va_priv->dev->of_node) {
  2038. dev_err(va_priv->dev,
  2039. "%s: DT node for va_priv does not exist\n", __func__);
  2040. return;
  2041. }
  2042. platdata = &va_priv->swr_plat_data;
  2043. va_priv->child_count = 0;
  2044. for_each_available_child_of_node(va_priv->dev->of_node, node) {
  2045. va_swr_master_node = false;
  2046. if (strnstr(node->name, "va_swr_master",
  2047. strlen("va_swr_master")) != NULL)
  2048. va_swr_master_node = true;
  2049. if (va_swr_master_node)
  2050. strlcpy(plat_dev_name, "va_swr_ctrl",
  2051. (LPASS_CDC_VA_MACRO_SWR_STRING_LEN - 1));
  2052. else
  2053. strlcpy(plat_dev_name, node->name,
  2054. (LPASS_CDC_VA_MACRO_SWR_STRING_LEN - 1));
  2055. pdev = platform_device_alloc(plat_dev_name, -1);
  2056. if (!pdev) {
  2057. dev_err(va_priv->dev, "%s: pdev memory alloc failed\n",
  2058. __func__);
  2059. ret = -ENOMEM;
  2060. goto err;
  2061. }
  2062. pdev->dev.parent = va_priv->dev;
  2063. pdev->dev.of_node = node;
  2064. if (va_swr_master_node) {
  2065. ret = platform_device_add_data(pdev, platdata,
  2066. sizeof(*platdata));
  2067. if (ret) {
  2068. dev_err(&pdev->dev,
  2069. "%s: cannot add plat data ctrl:%d\n",
  2070. __func__, ctrl_num);
  2071. goto fail_pdev_add;
  2072. }
  2073. temp = krealloc(swr_ctrl_data,
  2074. (ctrl_num + 1) * sizeof(
  2075. struct lpass_cdc_va_macro_swr_ctrl_data),
  2076. GFP_KERNEL);
  2077. if (!temp) {
  2078. ret = -ENOMEM;
  2079. goto fail_pdev_add;
  2080. }
  2081. swr_ctrl_data = temp;
  2082. swr_ctrl_data[ctrl_num].va_swr_pdev = pdev;
  2083. ctrl_num++;
  2084. dev_dbg(&pdev->dev,
  2085. "%s: Adding soundwire ctrl device(s)\n",
  2086. __func__);
  2087. va_priv->swr_ctrl_data = swr_ctrl_data;
  2088. }
  2089. ret = platform_device_add(pdev);
  2090. if (ret) {
  2091. dev_err(&pdev->dev,
  2092. "%s: Cannot add platform device\n",
  2093. __func__);
  2094. goto fail_pdev_add;
  2095. }
  2096. if (va_priv->child_count < LPASS_CDC_VA_MACRO_CHILD_DEVICES_MAX)
  2097. va_priv->pdev_child_devices[
  2098. va_priv->child_count++] = pdev;
  2099. else
  2100. goto err;
  2101. }
  2102. return;
  2103. fail_pdev_add:
  2104. for (count = 0; count < va_priv->child_count; count++)
  2105. platform_device_put(va_priv->pdev_child_devices[count]);
  2106. err:
  2107. return;
  2108. }
  2109. static int lpass_cdc_va_macro_set_port_map(struct snd_soc_component *component,
  2110. u32 usecase, u32 size, void *data)
  2111. {
  2112. struct device *va_dev = NULL;
  2113. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  2114. struct swrm_port_config port_cfg;
  2115. int ret = 0;
  2116. if (!lpass_cdc_va_macro_get_data(component, &va_dev, &va_priv, __func__))
  2117. return -EINVAL;
  2118. memset(&port_cfg, 0, sizeof(port_cfg));
  2119. port_cfg.uc = usecase;
  2120. port_cfg.size = size;
  2121. port_cfg.params = data;
  2122. if (va_priv->swr_ctrl_data)
  2123. ret = swrm_wcd_notify(
  2124. va_priv->swr_ctrl_data[0].va_swr_pdev,
  2125. SWR_SET_PORT_MAP, &port_cfg);
  2126. return ret;
  2127. }
  2128. static int lpass_cdc_va_macro_reg_wake_irq(struct snd_soc_component *component,
  2129. u32 data)
  2130. {
  2131. struct device *va_dev = NULL;
  2132. struct lpass_cdc_va_macro_priv *va_priv = NULL;
  2133. u32 ipc_wakeup = data;
  2134. int ret = 0;
  2135. if (!lpass_cdc_va_macro_get_data(component, &va_dev,
  2136. &va_priv, __func__))
  2137. return -EINVAL;
  2138. if (va_priv->swr_ctrl_data)
  2139. ret = swrm_wcd_notify(
  2140. va_priv->swr_ctrl_data[0].va_swr_pdev,
  2141. SWR_REGISTER_WAKE_IRQ, &ipc_wakeup);
  2142. return ret;
  2143. }
  2144. static void lpass_cdc_va_macro_init_ops(struct macro_ops *ops,
  2145. char __iomem *va_io_base)
  2146. {
  2147. memset(ops, 0, sizeof(struct macro_ops));
  2148. ops->dai_ptr = lpass_cdc_va_macro_dai;
  2149. ops->num_dais = ARRAY_SIZE(lpass_cdc_va_macro_dai);
  2150. ops->init = lpass_cdc_va_macro_init;
  2151. ops->exit = lpass_cdc_va_macro_deinit;
  2152. ops->io_base = va_io_base;
  2153. ops->event_handler = lpass_cdc_va_macro_event_handler;
  2154. ops->set_port_map = lpass_cdc_va_macro_set_port_map;
  2155. ops->reg_wake_irq = lpass_cdc_va_macro_reg_wake_irq;
  2156. ops->clk_div_get = lpass_cdc_va_macro_clk_div_get;
  2157. }
  2158. static int lpass_cdc_va_macro_probe(struct platform_device *pdev)
  2159. {
  2160. struct macro_ops ops;
  2161. struct lpass_cdc_va_macro_priv *va_priv;
  2162. u32 va_base_addr, sample_rate = 0;
  2163. char __iomem *va_io_base;
  2164. const char *micb_supply_str = "va-vdd-micb-supply";
  2165. const char *micb_supply_str1 = "va-vdd-micb";
  2166. const char *micb_voltage_str = "qcom,va-vdd-micb-voltage";
  2167. const char *micb_current_str = "qcom,va-vdd-micb-current";
  2168. int ret = 0;
  2169. const char *dmic_sample_rate = "qcom,va-dmic-sample-rate";
  2170. u32 default_clk_id = 0, use_clk_id = 0;
  2171. struct clk *lpass_audio_hw_vote = NULL;
  2172. u32 is_used_va_swr_gpio = 0;
  2173. const char *is_used_va_swr_gpio_dt = "qcom,is-used-swr-gpio";
  2174. va_priv = devm_kzalloc(&pdev->dev, sizeof(struct lpass_cdc_va_macro_priv),
  2175. GFP_KERNEL);
  2176. if (!va_priv)
  2177. return -ENOMEM;
  2178. va_priv->dev = &pdev->dev;
  2179. ret = of_property_read_u32(pdev->dev.of_node, "reg",
  2180. &va_base_addr);
  2181. if (ret) {
  2182. dev_err(&pdev->dev, "%s: could not find %s entry in dt\n",
  2183. __func__, "reg");
  2184. return ret;
  2185. }
  2186. ret = of_property_read_u32(pdev->dev.of_node, dmic_sample_rate,
  2187. &sample_rate);
  2188. if (ret) {
  2189. dev_err(&pdev->dev, "%s: could not find %d entry in dt\n",
  2190. __func__, sample_rate);
  2191. va_priv->dmic_clk_div = LPASS_CDC_VA_MACRO_CLK_DIV_2;
  2192. } else {
  2193. if (lpass_cdc_va_macro_validate_dmic_sample_rate(
  2194. sample_rate, va_priv) ==
  2195. LPASS_CDC_VA_MACRO_DMIC_SAMPLE_RATE_UNDEFINED)
  2196. return -EINVAL;
  2197. }
  2198. if (of_find_property(pdev->dev.of_node, is_used_va_swr_gpio_dt,
  2199. NULL)) {
  2200. ret = of_property_read_u32(pdev->dev.of_node,
  2201. is_used_va_swr_gpio_dt,
  2202. &is_used_va_swr_gpio);
  2203. if (ret) {
  2204. dev_err(&pdev->dev, "%s: error reading %s in dt\n",
  2205. __func__, is_used_va_swr_gpio_dt);
  2206. is_used_va_swr_gpio = 0;
  2207. }
  2208. }
  2209. va_priv->va_swr_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2210. "qcom,va-swr-gpios", 0);
  2211. if (!va_priv->va_swr_gpio_p && is_used_va_swr_gpio) {
  2212. dev_err(&pdev->dev, "%s: swr_gpios handle not provided!\n",
  2213. __func__);
  2214. return -EINVAL;
  2215. }
  2216. if ((msm_cdc_pinctrl_get_state(va_priv->va_swr_gpio_p) < 0) &&
  2217. is_used_va_swr_gpio) {
  2218. dev_err(&pdev->dev, "%s: failed to get swr pin state\n",
  2219. __func__);
  2220. return -EPROBE_DEFER;
  2221. }
  2222. va_io_base = devm_ioremap(&pdev->dev, va_base_addr,
  2223. LPASS_CDC_VA_MACRO_MAX_OFFSET);
  2224. if (!va_io_base) {
  2225. dev_err(&pdev->dev, "%s: ioremap failed\n", __func__);
  2226. return -EINVAL;
  2227. }
  2228. va_priv->va_io_base = va_io_base;
  2229. lpass_audio_hw_vote = devm_clk_get(&pdev->dev, "lpass_audio_hw_vote");
  2230. if (IS_ERR(lpass_audio_hw_vote)) {
  2231. ret = PTR_ERR(lpass_audio_hw_vote);
  2232. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  2233. __func__, "lpass_audio_hw_vote", ret);
  2234. lpass_audio_hw_vote = NULL;
  2235. ret = 0;
  2236. }
  2237. va_priv->lpass_audio_hw_vote = lpass_audio_hw_vote;
  2238. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  2239. va_priv->micb_supply = devm_regulator_get(&pdev->dev,
  2240. micb_supply_str1);
  2241. if (IS_ERR(va_priv->micb_supply)) {
  2242. ret = PTR_ERR(va_priv->micb_supply);
  2243. dev_err(&pdev->dev,
  2244. "%s:Failed to get micbias supply for VA Mic %d\n",
  2245. __func__, ret);
  2246. return ret;
  2247. }
  2248. ret = of_property_read_u32(pdev->dev.of_node,
  2249. micb_voltage_str,
  2250. &va_priv->micb_voltage);
  2251. if (ret) {
  2252. dev_err(&pdev->dev,
  2253. "%s:Looking up %s property in node %s failed\n",
  2254. __func__, micb_voltage_str,
  2255. pdev->dev.of_node->full_name);
  2256. return ret;
  2257. }
  2258. ret = of_property_read_u32(pdev->dev.of_node,
  2259. micb_current_str,
  2260. &va_priv->micb_current);
  2261. if (ret) {
  2262. dev_err(&pdev->dev,
  2263. "%s:Looking up %s property in node %s failed\n",
  2264. __func__, micb_current_str,
  2265. pdev->dev.of_node->full_name);
  2266. return ret;
  2267. }
  2268. }
  2269. use_clk_id = VA_CORE_CLK; /* default to using VA CORE CLK */
  2270. if (of_find_property(pdev->dev.of_node, "qcom,use-clk-id", NULL)) {
  2271. ret = of_property_read_u32(pdev->dev.of_node, "qcom,use-clk-id",
  2272. &use_clk_id);
  2273. if (ret) {
  2274. dev_dbg(&pdev->dev, "%s: could not find %s entry in dt\n",
  2275. __func__, "qcom,use-clk-id");
  2276. use_clk_id = VA_CORE_CLK;
  2277. }
  2278. }
  2279. va_priv->clk_id = use_clk_id;
  2280. ret = of_property_read_u32(pdev->dev.of_node, "qcom,default-clk-id",
  2281. &default_clk_id);
  2282. if (ret) {
  2283. dev_err(&pdev->dev, "%s: could not find %s entry in dt\n",
  2284. __func__, "qcom,default-clk-id");
  2285. default_clk_id = use_clk_id;
  2286. }
  2287. va_priv->default_clk_id = default_clk_id;
  2288. va_priv->current_clk_id = TX_CORE_CLK;
  2289. va_priv->wlock_holders = 0;
  2290. va_priv->use_lpi_mixer_control = false;
  2291. if (of_find_property(pdev->dev.of_node, "use-lpi-control", NULL)) {
  2292. dev_dbg(&pdev->dev, "%s(): Usage of LPI Enable mixer control is enabled\n",
  2293. __func__);
  2294. va_priv->use_lpi_mixer_control = true;
  2295. }
  2296. if (is_used_va_swr_gpio) {
  2297. va_priv->reset_swr = true;
  2298. INIT_WORK(&va_priv->lpass_cdc_va_macro_add_child_devices_work,
  2299. lpass_cdc_va_macro_add_child_devices);
  2300. va_priv->swr_plat_data.handle = (void *) va_priv;
  2301. va_priv->swr_plat_data.read = NULL;
  2302. va_priv->swr_plat_data.write = NULL;
  2303. va_priv->swr_plat_data.bulk_write = NULL;
  2304. va_priv->swr_plat_data.clk = lpass_cdc_va_macro_swrm_clock;
  2305. va_priv->swr_plat_data.core_vote = lpass_cdc_va_macro_core_vote;
  2306. va_priv->swr_plat_data.handle_irq = NULL;
  2307. mutex_init(&va_priv->swr_clk_lock);
  2308. }
  2309. va_priv->is_used_va_swr_gpio = is_used_va_swr_gpio;
  2310. va_priv->pre_dev_up = true;
  2311. mutex_init(&va_priv->mclk_lock);
  2312. mutex_init(&va_priv->wlock);
  2313. dev_set_drvdata(&pdev->dev, va_priv);
  2314. lpass_cdc_va_macro_init_ops(&ops, va_io_base);
  2315. ops.clk_id_req = va_priv->default_clk_id;
  2316. ops.default_clk_id = va_priv->default_clk_id;
  2317. ret = lpass_cdc_register_macro(&pdev->dev, VA_MACRO, &ops);
  2318. if (ret < 0) {
  2319. dev_err(&pdev->dev, "%s: register macro failed\n", __func__);
  2320. goto reg_macro_fail;
  2321. }
  2322. pm_runtime_set_autosuspend_delay(&pdev->dev, VA_AUTO_SUSPEND_DELAY);
  2323. pm_runtime_use_autosuspend(&pdev->dev);
  2324. pm_runtime_set_suspended(&pdev->dev);
  2325. pm_suspend_ignore_children(&pdev->dev, true);
  2326. pm_runtime_enable(&pdev->dev);
  2327. if (is_used_va_swr_gpio)
  2328. schedule_work(&va_priv->lpass_cdc_va_macro_add_child_devices_work);
  2329. return ret;
  2330. reg_macro_fail:
  2331. mutex_destroy(&va_priv->mclk_lock);
  2332. mutex_destroy(&va_priv->wlock);
  2333. if (is_used_va_swr_gpio)
  2334. mutex_destroy(&va_priv->swr_clk_lock);
  2335. return ret;
  2336. }
  2337. static int lpass_cdc_va_macro_remove(struct platform_device *pdev)
  2338. {
  2339. struct lpass_cdc_va_macro_priv *va_priv;
  2340. int count = 0;
  2341. va_priv = dev_get_drvdata(&pdev->dev);
  2342. if (!va_priv)
  2343. return -EINVAL;
  2344. if (va_priv->is_used_va_swr_gpio) {
  2345. if (va_priv->swr_ctrl_data)
  2346. kfree(va_priv->swr_ctrl_data);
  2347. for (count = 0; count < va_priv->child_count &&
  2348. count < LPASS_CDC_VA_MACRO_CHILD_DEVICES_MAX; count++)
  2349. platform_device_unregister(
  2350. va_priv->pdev_child_devices[count]);
  2351. }
  2352. pm_runtime_disable(&pdev->dev);
  2353. pm_runtime_set_suspended(&pdev->dev);
  2354. lpass_cdc_unregister_macro(&pdev->dev, VA_MACRO);
  2355. mutex_destroy(&va_priv->mclk_lock);
  2356. mutex_destroy(&va_priv->wlock);
  2357. if (va_priv->is_used_va_swr_gpio)
  2358. mutex_destroy(&va_priv->swr_clk_lock);
  2359. return 0;
  2360. }
  2361. static const struct of_device_id lpass_cdc_va_macro_dt_match[] = {
  2362. {.compatible = "qcom,lpass-cdc-va-macro"},
  2363. {}
  2364. };
  2365. static const struct dev_pm_ops lpass_cdc_dev_pm_ops = {
  2366. SET_SYSTEM_SLEEP_PM_OPS(
  2367. pm_runtime_force_suspend,
  2368. pm_runtime_force_resume
  2369. )
  2370. SET_RUNTIME_PM_OPS(
  2371. lpass_cdc_runtime_suspend,
  2372. lpass_cdc_runtime_resume,
  2373. NULL
  2374. )
  2375. };
  2376. static struct platform_driver lpass_cdc_va_macro_driver = {
  2377. .driver = {
  2378. .name = "lpass_cdc_va_macro",
  2379. .owner = THIS_MODULE,
  2380. .pm = &lpass_cdc_dev_pm_ops,
  2381. .of_match_table = lpass_cdc_va_macro_dt_match,
  2382. .suppress_bind_attrs = true,
  2383. },
  2384. .probe = lpass_cdc_va_macro_probe,
  2385. .remove = lpass_cdc_va_macro_remove,
  2386. };
  2387. module_platform_driver(lpass_cdc_va_macro_driver);
  2388. MODULE_DESCRIPTION("LPASS codec VA macro driver");
  2389. MODULE_LICENSE("GPL v2");