wcd938x.c 81 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #define WCD938X_DRV_NAME "wcd938x_codec"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VERSION_1_0 1
  27. #define WCD938X_VERSION_ENTRY_SIZE 32
  28. #define ADC_MODE_VAL_HIFI 0x01
  29. #define ADC_MODE_VAL_LO_HIF 0x02
  30. #define ADC_MODE_VAL_NORMAL 0x03
  31. #define ADC_MODE_VAL_LP 0x05
  32. #define ADC_MODE_VAL_ULP1 0x09
  33. #define ADC_MODE_VAL_ULP2 0x0B
  34. enum {
  35. WCD9380 = 0,
  36. WCD9385,
  37. WCD9385FX,
  38. };
  39. enum {
  40. CODEC_TX = 0,
  41. CODEC_RX,
  42. };
  43. enum {
  44. WCD_ADC1 = 0,
  45. WCD_ADC2,
  46. WCD_ADC3,
  47. WCD_ADC4,
  48. ALLOW_BUCK_DISABLE,
  49. HPH_COMP_DELAY,
  50. HPH_PA_DELAY,
  51. };
  52. enum {
  53. ADC_MODE_INVALID = 0,
  54. ADC_MODE_HIFI,
  55. ADC_MODE_LO_HIF,
  56. ADC_MODE_NORMAL,
  57. ADC_MODE_LP,
  58. ADC_MODE_ULP1,
  59. ADC_MODE_ULP2,
  60. };
  61. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  62. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  63. static int wcd938x_handle_post_irq(void *data);
  64. static int wcd938x_reset(struct device *dev);
  65. static int wcd938x_reset_low(struct device *dev);
  66. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  67. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  68. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  69. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  70. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  71. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  86. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  87. };
  88. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  89. .name = "wcd938x",
  90. .irqs = wcd938x_irqs,
  91. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  92. .num_regs = 3,
  93. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  94. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  95. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  96. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  97. .use_ack = 1,
  98. .runtime_pm = false,
  99. .handle_post_irq = wcd938x_handle_post_irq,
  100. .irq_drv_data = NULL,
  101. };
  102. static int wcd938x_handle_post_irq(void *data)
  103. {
  104. struct wcd938x_priv *wcd938x = data;
  105. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  106. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  107. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  108. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  109. wcd938x->tx_swr_dev->slave_irq_pending =
  110. ((sts1 || sts2 || sts3) ? true : false);
  111. return IRQ_HANDLED;
  112. }
  113. static int wcd938x_init_reg(struct snd_soc_component *component)
  114. {
  115. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  116. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  117. /* 1 msec delay as per HW requirement */
  118. usleep_range(1000, 1010);
  119. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  120. /* 1 msec delay as per HW requirement */
  121. usleep_range(1000, 1010);
  122. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  123. 0x10, 0x00);
  124. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  125. 0xF0, 0x80);
  126. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  127. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  128. /* 10 msec delay as per HW requirement */
  129. usleep_range(10000, 10010);
  130. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  131. snd_soc_component_update_bits(component, WCD938X_HPH_OCP_CTL,
  132. 0xFF, 0x3A);
  133. snd_soc_component_update_bits(component, WCD938X_RX_OCP_CTL,
  134. 0x0F, 0x02);
  135. snd_soc_component_update_bits(component, WCD938X_HPH_R_TEST,
  136. 0x01, 0x01);
  137. snd_soc_component_update_bits(component, WCD938X_HPH_L_TEST,
  138. 0x01, 0x01);
  139. snd_soc_component_update_bits(component,
  140. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  141. 0xF0, 0x00);
  142. snd_soc_component_update_bits(component,
  143. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  144. 0x1F, 0x15);
  145. snd_soc_component_update_bits(component,
  146. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  147. 0x1F, 0x15);
  148. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  149. 0xC0, 0x80);
  150. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  151. 0x02, 0x02);
  152. return 0;
  153. }
  154. static int wcd938x_set_port_params(struct snd_soc_component *component,
  155. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  156. u8 *ch_mask, u32 *ch_rate,
  157. u8 *port_type, u8 path)
  158. {
  159. int i, j;
  160. u8 num_ports;
  161. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  162. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  163. switch (path) {
  164. case CODEC_RX:
  165. map = &wcd938x->rx_port_mapping;
  166. num_ports = wcd938x->num_rx_ports;
  167. break;
  168. case CODEC_TX:
  169. map = &wcd938x->tx_port_mapping;
  170. num_ports = wcd938x->num_tx_ports;
  171. break;
  172. }
  173. for (i = 0; i <= num_ports; i++) {
  174. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  175. if ((*map)[i][j].slave_port_type == slv_prt_type)
  176. goto found;
  177. }
  178. }
  179. found:
  180. if (i > num_ports || j == MAX_CH_PER_PORT) {
  181. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  182. __func__, slv_prt_type);
  183. return -EINVAL;
  184. }
  185. *port_id = i;
  186. *num_ch = (*map)[i][j].num_ch;
  187. *ch_mask = (*map)[i][j].ch_mask;
  188. *ch_rate = (*map)[i][j].ch_rate;
  189. *port_type = (*map)[i][j].master_port_type;
  190. return 0;
  191. }
  192. static int wcd938x_parse_port_mapping(struct device *dev,
  193. char *prop, u8 path)
  194. {
  195. u32 *dt_array, map_size, map_length;
  196. u32 port_num, ch_mask, ch_rate, old_port_num = 0;
  197. u32 slave_port_type, master_port_type;
  198. u32 i, ch_iter = 0;
  199. int ret = 0;
  200. u8 *num_ports;
  201. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  202. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  203. switch (path) {
  204. case CODEC_RX:
  205. map = &wcd938x->rx_port_mapping;
  206. num_ports = &wcd938x->num_rx_ports;
  207. break;
  208. case CODEC_TX:
  209. map = &wcd938x->tx_port_mapping;
  210. num_ports = &wcd938x->num_tx_ports;
  211. break;
  212. }
  213. if (!of_find_property(dev->of_node, prop,
  214. &map_size)) {
  215. dev_err(dev, "missing port mapping prop %s\n", prop);
  216. ret = -EINVAL;
  217. goto err_port_map;
  218. }
  219. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  220. dt_array = kzalloc(map_size, GFP_KERNEL);
  221. if (!dt_array) {
  222. ret = -ENOMEM;
  223. goto err_alloc;
  224. }
  225. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  226. NUM_SWRS_DT_PARAMS * map_length);
  227. if (ret) {
  228. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  229. __func__, prop);
  230. goto err_pdata_fail;
  231. }
  232. for (i = 0; i < map_length; i++) {
  233. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  234. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  235. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  236. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  237. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  238. if (port_num != old_port_num)
  239. ch_iter = 0;
  240. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  241. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  242. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  243. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  244. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  245. old_port_num = port_num;
  246. }
  247. *num_ports = port_num;
  248. kfree(dt_array);
  249. return 0;
  250. err_pdata_fail:
  251. kfree(dt_array);
  252. err_alloc:
  253. err_port_map:
  254. return ret;
  255. }
  256. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  257. u8 slv_port_type, u8 enable)
  258. {
  259. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  260. u8 port_id, num_ch, ch_mask, port_type;
  261. u32 ch_rate;
  262. u8 num_port = 1;
  263. int ret = 0;
  264. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  265. &num_ch, &ch_mask, &ch_rate,
  266. &port_type, CODEC_TX);
  267. if (ret)
  268. return ret;
  269. if (enable)
  270. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  271. num_port, &ch_mask, &ch_rate,
  272. &num_ch, &port_type);
  273. else
  274. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  275. num_port, &ch_mask, &port_type);
  276. return ret;
  277. }
  278. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  279. u8 slv_port_type, u8 enable)
  280. {
  281. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  282. u8 port_id, num_ch, ch_mask, port_type;
  283. u32 ch_rate;
  284. u8 num_port = 1;
  285. int ret = 0;
  286. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  287. &num_ch, &ch_mask, &ch_rate,
  288. &port_type, CODEC_RX);
  289. if (ret)
  290. return ret;
  291. if (enable)
  292. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  293. num_port, &ch_mask, &ch_rate,
  294. &num_ch, &port_type);
  295. else
  296. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  297. num_port, &ch_mask, &port_type);
  298. return ret;
  299. }
  300. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  301. {
  302. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  303. if (wcd938x->rx_clk_cnt == 0) {
  304. snd_soc_component_update_bits(component,
  305. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  306. snd_soc_component_update_bits(component,
  307. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  308. snd_soc_component_update_bits(component,
  309. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  310. snd_soc_component_update_bits(component,
  311. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  312. snd_soc_component_update_bits(component,
  313. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  314. snd_soc_component_update_bits(component,
  315. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  316. }
  317. wcd938x->rx_clk_cnt++;
  318. return 0;
  319. }
  320. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  321. {
  322. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  323. wcd938x->rx_clk_cnt--;
  324. if (wcd938x->rx_clk_cnt == 0) {
  325. snd_soc_component_update_bits(component,
  326. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  327. snd_soc_component_update_bits(component,
  328. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  329. snd_soc_component_update_bits(component,
  330. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  331. snd_soc_component_update_bits(component,
  332. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  333. snd_soc_component_update_bits(component,
  334. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  335. }
  336. return 0;
  337. }
  338. /*
  339. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  340. * @component: handle to snd_soc_component *
  341. *
  342. * return wcd938x_mbhc handle or error code in case of failure
  343. */
  344. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  345. {
  346. struct wcd938x_priv *wcd938x;
  347. if (!component) {
  348. pr_err("%s: Invalid params, NULL component\n", __func__);
  349. return NULL;
  350. }
  351. wcd938x = snd_soc_component_get_drvdata(component);
  352. if (!wcd938x) {
  353. pr_err("%s: wcd938x is NULL\n", __func__);
  354. return NULL;
  355. }
  356. return wcd938x->mbhc;
  357. }
  358. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  359. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  360. struct snd_kcontrol *kcontrol,
  361. int event)
  362. {
  363. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  364. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  365. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  366. w->name, event);
  367. switch (event) {
  368. case SND_SOC_DAPM_PRE_PMU:
  369. wcd938x_rx_clk_enable(component);
  370. snd_soc_component_update_bits(component,
  371. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  372. snd_soc_component_update_bits(component,
  373. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  374. snd_soc_component_update_bits(component,
  375. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  376. break;
  377. case SND_SOC_DAPM_POST_PMU:
  378. snd_soc_component_update_bits(component,
  379. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  380. if (wcd938x->comp1_enable) {
  381. snd_soc_component_update_bits(component,
  382. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  383. /* 5msec compander delay as per HW requirement */
  384. if (!wcd938x->comp2_enable ||
  385. (snd_soc_component_read32(component,
  386. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  387. usleep_range(5000, 5010);
  388. snd_soc_component_update_bits(component,
  389. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  390. } else {
  391. snd_soc_component_update_bits(component,
  392. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  393. 0x02, 0x00);
  394. snd_soc_component_update_bits(component,
  395. WCD938X_HPH_L_EN, 0x20, 0x20);
  396. }
  397. break;
  398. case SND_SOC_DAPM_POST_PMD:
  399. snd_soc_component_update_bits(component,
  400. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  401. 0x0F, 0x01);
  402. break;
  403. }
  404. return 0;
  405. }
  406. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  407. struct snd_kcontrol *kcontrol,
  408. int event)
  409. {
  410. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  411. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  412. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  413. w->name, event);
  414. switch (event) {
  415. case SND_SOC_DAPM_PRE_PMU:
  416. wcd938x_rx_clk_enable(component);
  417. snd_soc_component_update_bits(component,
  418. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  419. snd_soc_component_update_bits(component,
  420. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  421. snd_soc_component_update_bits(component,
  422. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  423. break;
  424. case SND_SOC_DAPM_POST_PMU:
  425. snd_soc_component_update_bits(component,
  426. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  427. if (wcd938x->comp2_enable) {
  428. snd_soc_component_update_bits(component,
  429. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  430. /* 5msec compander delay as per HW requirement */
  431. if (!wcd938x->comp1_enable ||
  432. (snd_soc_component_read32(component,
  433. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  434. usleep_range(5000, 5010);
  435. snd_soc_component_update_bits(component,
  436. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  437. } else {
  438. snd_soc_component_update_bits(component,
  439. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  440. 0x01, 0x00);
  441. snd_soc_component_update_bits(component,
  442. WCD938X_HPH_R_EN, 0x20, 0x20);
  443. }
  444. break;
  445. case SND_SOC_DAPM_POST_PMD:
  446. snd_soc_component_update_bits(component,
  447. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  448. 0x0F, 0x01);
  449. break;
  450. }
  451. return 0;
  452. }
  453. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  454. struct snd_kcontrol *kcontrol,
  455. int event)
  456. {
  457. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  458. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  459. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  460. w->name, event);
  461. switch (event) {
  462. case SND_SOC_DAPM_PRE_PMU:
  463. wcd938x_rx_clk_enable(component);
  464. snd_soc_component_update_bits(component,
  465. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  466. snd_soc_component_update_bits(component,
  467. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  468. snd_soc_component_update_bits(component,
  469. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  470. /* 5 msec delay as per HW requirement */
  471. usleep_range(5000, 5010);
  472. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  473. WCD_CLSH_EVENT_PRE_DAC,
  474. WCD_CLSH_STATE_EAR,
  475. wcd938x->hph_mode);
  476. break;
  477. case SND_SOC_DAPM_POST_PMD:
  478. break;
  479. };
  480. return 0;
  481. }
  482. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  483. struct snd_kcontrol *kcontrol,
  484. int event)
  485. {
  486. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  487. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  488. int ret = 0;
  489. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  490. w->name, event);
  491. switch (event) {
  492. case SND_SOC_DAPM_PRE_PMU:
  493. wcd938x_rx_clk_enable(component);
  494. snd_soc_component_update_bits(component,
  495. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  496. snd_soc_component_update_bits(component,
  497. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  498. snd_soc_component_update_bits(component,
  499. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  500. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  501. WCD_CLSH_EVENT_PRE_DAC,
  502. WCD_CLSH_STATE_AUX,
  503. wcd938x->hph_mode);
  504. break;
  505. case SND_SOC_DAPM_POST_PMD:
  506. wcd938x_rx_clk_disable(component);
  507. snd_soc_component_update_bits(component,
  508. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  509. break;
  510. };
  511. return ret;
  512. }
  513. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  514. struct snd_kcontrol *kcontrol,
  515. int event)
  516. {
  517. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  518. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  519. int ret = 0;
  520. int hph_mode = wcd938x->hph_mode;
  521. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  522. w->name, event);
  523. switch (event) {
  524. case SND_SOC_DAPM_PRE_PMU:
  525. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  526. wcd938x->rx_swr_dev->dev_num,
  527. true);
  528. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  529. WCD_CLSH_EVENT_PRE_DAC,
  530. WCD_CLSH_STATE_HPHR,
  531. hph_mode);
  532. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  533. 0x10, 0x10);
  534. /* 100 usec delay as per HW requirement */
  535. usleep_range(100, 110);
  536. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  537. break;
  538. case SND_SOC_DAPM_POST_PMU:
  539. /*
  540. * 7ms sleep is required if compander is enabled as per
  541. * HW requirement. If compander is disabled, then
  542. * 20ms delay is required.
  543. */
  544. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  545. if (!wcd938x->comp2_enable)
  546. usleep_range(20000, 20100);
  547. else
  548. usleep_range(7000, 7100);
  549. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  550. }
  551. snd_soc_component_update_bits(component,
  552. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  553. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  554. snd_soc_component_update_bits(component,
  555. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  556. if (wcd938x->update_wcd_event)
  557. wcd938x->update_wcd_event(wcd938x->handle,
  558. WCD_BOLERO_EVT_RX_MUTE,
  559. (WCD_RX2 << 0x10));
  560. break;
  561. case SND_SOC_DAPM_PRE_PMD:
  562. if (wcd938x->update_wcd_event)
  563. wcd938x->update_wcd_event(wcd938x->handle,
  564. WCD_BOLERO_EVT_RX_MUTE,
  565. (WCD_RX2 << 0x10 | 0x1));
  566. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  567. WCD_EVENT_PRE_HPHR_PA_OFF,
  568. &wcd938x->mbhc->wcd_mbhc);
  569. break;
  570. case SND_SOC_DAPM_POST_PMD:
  571. /* 7 msec delay as per HW requirement */
  572. usleep_range(7000, 7010);
  573. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  574. WCD_EVENT_POST_HPHR_PA_OFF,
  575. &wcd938x->mbhc->wcd_mbhc);
  576. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  577. 0x10, 0x00);
  578. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  579. WCD_CLSH_EVENT_POST_PA,
  580. WCD_CLSH_STATE_HPHR,
  581. hph_mode);
  582. break;
  583. };
  584. return ret;
  585. }
  586. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  587. struct snd_kcontrol *kcontrol,
  588. int event)
  589. {
  590. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  591. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  592. int ret = 0;
  593. int hph_mode = wcd938x->hph_mode;
  594. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  595. w->name, event);
  596. switch (event) {
  597. case SND_SOC_DAPM_PRE_PMU:
  598. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  599. wcd938x->rx_swr_dev->dev_num,
  600. true);
  601. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  602. WCD_CLSH_EVENT_PRE_DAC,
  603. WCD_CLSH_STATE_HPHL,
  604. hph_mode);
  605. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  606. 0x20, 0x20);
  607. /* 100 usec delay as per HW requirement */
  608. usleep_range(100, 110);
  609. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  610. break;
  611. case SND_SOC_DAPM_POST_PMU:
  612. /*
  613. * 7ms sleep is required if compander is enabled as per
  614. * HW requirement. If compander is disabled, then
  615. * 20ms delay is required.
  616. */
  617. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  618. if (!wcd938x->comp1_enable)
  619. usleep_range(20000, 20100);
  620. else
  621. usleep_range(7000, 7100);
  622. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  623. }
  624. snd_soc_component_update_bits(component,
  625. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  626. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  627. snd_soc_component_update_bits(component,
  628. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  629. if (wcd938x->update_wcd_event)
  630. wcd938x->update_wcd_event(wcd938x->handle,
  631. WCD_BOLERO_EVT_RX_MUTE,
  632. (WCD_RX1 << 0x10));
  633. break;
  634. case SND_SOC_DAPM_PRE_PMD:
  635. if (wcd938x->update_wcd_event)
  636. wcd938x->update_wcd_event(wcd938x->handle,
  637. WCD_BOLERO_EVT_RX_MUTE,
  638. (WCD_RX1 << 0x10 | 0x1));
  639. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  640. WCD_EVENT_PRE_HPHL_PA_OFF,
  641. &wcd938x->mbhc->wcd_mbhc);
  642. break;
  643. case SND_SOC_DAPM_POST_PMD:
  644. /* 7 msec delay as per HW requirement */
  645. usleep_range(7000, 7010);
  646. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  647. WCD_EVENT_POST_HPHL_PA_OFF,
  648. &wcd938x->mbhc->wcd_mbhc);
  649. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  650. 0x20, 0x00);
  651. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  652. WCD_CLSH_EVENT_POST_PA,
  653. WCD_CLSH_STATE_HPHL,
  654. hph_mode);
  655. break;
  656. };
  657. return ret;
  658. }
  659. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  660. struct snd_kcontrol *kcontrol,
  661. int event)
  662. {
  663. struct snd_soc_component *component =
  664. snd_soc_dapm_to_component(w->dapm);
  665. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  666. int hph_mode = wcd938x->hph_mode;
  667. int ret = 0;
  668. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  669. w->name, event);
  670. switch (event) {
  671. case SND_SOC_DAPM_PRE_PMU:
  672. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  673. wcd938x->rx_swr_dev->dev_num,
  674. true);
  675. break;
  676. case SND_SOC_DAPM_POST_PMU:
  677. /* 1 msec delay as per HW requirement */
  678. usleep_range(1000, 1010);
  679. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  680. snd_soc_component_update_bits(component,
  681. WCD938X_ANA_RX_SUPPLIES,
  682. 0x20, 0x20);
  683. if (wcd938x->update_wcd_event)
  684. wcd938x->update_wcd_event(wcd938x->handle,
  685. WCD_BOLERO_EVT_RX_MUTE,
  686. (WCD_RX3 << 0x10));
  687. break;
  688. case SND_SOC_DAPM_PRE_PMD:
  689. if (wcd938x->update_wcd_event)
  690. wcd938x->update_wcd_event(wcd938x->handle,
  691. WCD_BOLERO_EVT_RX_MUTE,
  692. (WCD_RX3 << 0x10 | 0x1));
  693. break;
  694. case SND_SOC_DAPM_POST_PMD:
  695. /* 1 msec delay as per HW requirement */
  696. usleep_range(1000, 1010);
  697. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  698. WCD_CLSH_EVENT_POST_PA,
  699. WCD_CLSH_STATE_AUX,
  700. hph_mode);
  701. break;
  702. };
  703. return ret;
  704. }
  705. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  706. struct snd_kcontrol *kcontrol,
  707. int event)
  708. {
  709. struct snd_soc_component *component =
  710. snd_soc_dapm_to_component(w->dapm);
  711. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  712. int hph_mode = wcd938x->hph_mode;
  713. int ret = 0;
  714. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  715. w->name, event);
  716. switch (event) {
  717. case SND_SOC_DAPM_PRE_PMU:
  718. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  719. wcd938x->rx_swr_dev->dev_num,
  720. true);
  721. break;
  722. case SND_SOC_DAPM_POST_PMU:
  723. /* 6 msec delay as per HW requirement */
  724. usleep_range(6000, 6010);
  725. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  726. snd_soc_component_update_bits(component,
  727. WCD938X_ANA_RX_SUPPLIES,
  728. 0x02, 0x02);
  729. if (wcd938x->update_wcd_event)
  730. wcd938x->update_wcd_event(wcd938x->handle,
  731. WCD_BOLERO_EVT_RX_MUTE,
  732. (WCD_RX1 << 0x10));
  733. break;
  734. case SND_SOC_DAPM_PRE_PMD:
  735. if (wcd938x->update_wcd_event)
  736. wcd938x->update_wcd_event(wcd938x->handle,
  737. WCD_BOLERO_EVT_RX_MUTE,
  738. (WCD_RX1 << 0x10 | 0x1));
  739. break;
  740. case SND_SOC_DAPM_POST_PMD:
  741. /* 7 msec delay as per HW requirement */
  742. usleep_range(7000, 7010);
  743. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  744. WCD_CLSH_EVENT_POST_PA,
  745. WCD_CLSH_STATE_EAR,
  746. hph_mode);
  747. break;
  748. };
  749. return ret;
  750. }
  751. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  752. struct snd_kcontrol *kcontrol,
  753. int event)
  754. {
  755. struct snd_soc_component *component =
  756. snd_soc_dapm_to_component(w->dapm);
  757. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  758. int mode = wcd938x->hph_mode;
  759. int ret = 0;
  760. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  761. w->name, event);
  762. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  763. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  764. wcd938x_rx_connect_port(component, CLSH,
  765. SND_SOC_DAPM_EVENT_ON(event));
  766. }
  767. if (SND_SOC_DAPM_EVENT_OFF(event))
  768. ret = swr_slvdev_datapath_control(
  769. wcd938x->rx_swr_dev,
  770. wcd938x->rx_swr_dev->dev_num,
  771. false);
  772. return ret;
  773. }
  774. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  775. struct snd_kcontrol *kcontrol,
  776. int event)
  777. {
  778. struct snd_soc_component *component =
  779. snd_soc_dapm_to_component(w->dapm);
  780. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  781. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  782. w->name, event);
  783. switch (event) {
  784. case SND_SOC_DAPM_PRE_PMU:
  785. wcd938x_rx_connect_port(component, HPH_L, true);
  786. if (wcd938x->comp1_enable)
  787. wcd938x_rx_connect_port(component, COMP_L, true);
  788. break;
  789. case SND_SOC_DAPM_POST_PMD:
  790. wcd938x_rx_connect_port(component, HPH_L, false);
  791. if (wcd938x->comp1_enable)
  792. wcd938x_rx_connect_port(component, COMP_L, false);
  793. wcd938x_rx_clk_disable(component);
  794. snd_soc_component_update_bits(component,
  795. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  796. 0x01, 0x00);
  797. break;
  798. };
  799. return 0;
  800. }
  801. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  802. struct snd_kcontrol *kcontrol, int event)
  803. {
  804. struct snd_soc_component *component =
  805. snd_soc_dapm_to_component(w->dapm);
  806. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  807. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  808. w->name, event);
  809. switch (event) {
  810. case SND_SOC_DAPM_PRE_PMU:
  811. wcd938x_rx_connect_port(component, HPH_R, true);
  812. if (wcd938x->comp2_enable)
  813. wcd938x_rx_connect_port(component, COMP_R, true);
  814. break;
  815. case SND_SOC_DAPM_POST_PMD:
  816. wcd938x_rx_connect_port(component, HPH_R, false);
  817. if (wcd938x->comp2_enable)
  818. wcd938x_rx_connect_port(component, COMP_R, false);
  819. wcd938x_rx_clk_disable(component);
  820. snd_soc_component_update_bits(component,
  821. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  822. 0x02, 0x00);
  823. break;
  824. };
  825. return 0;
  826. }
  827. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  828. struct snd_kcontrol *kcontrol,
  829. int event)
  830. {
  831. struct snd_soc_component *component =
  832. snd_soc_dapm_to_component(w->dapm);
  833. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  834. w->name, event);
  835. switch (event) {
  836. case SND_SOC_DAPM_PRE_PMU:
  837. wcd938x_rx_connect_port(component, LO, true);
  838. break;
  839. case SND_SOC_DAPM_POST_PMD:
  840. wcd938x_rx_connect_port(component, LO, false);
  841. /* 6 msec delay as per HW requirement */
  842. usleep_range(6000, 6010);
  843. wcd938x_rx_clk_disable(component);
  844. snd_soc_component_update_bits(component,
  845. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  846. break;
  847. }
  848. return 0;
  849. }
  850. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  851. struct snd_kcontrol *kcontrol,
  852. int event)
  853. {
  854. struct snd_soc_component *component =
  855. snd_soc_dapm_to_component(w->dapm);
  856. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  857. u16 dmic_clk_reg;
  858. s32 *dmic_clk_cnt;
  859. unsigned int dmic;
  860. char *wname;
  861. int ret = 0;
  862. wname = strpbrk(w->name, "012345");
  863. if (!wname) {
  864. dev_err(component->dev, "%s: widget not found\n", __func__);
  865. return -EINVAL;
  866. }
  867. ret = kstrtouint(wname, 10, &dmic);
  868. if (ret < 0) {
  869. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  870. __func__);
  871. return -EINVAL;
  872. }
  873. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  874. w->name, event);
  875. switch (dmic) {
  876. case 0:
  877. case 1:
  878. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  879. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  880. break;
  881. case 2:
  882. case 3:
  883. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  884. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  885. break;
  886. case 4:
  887. case 5:
  888. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  889. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  890. break;
  891. case 6:
  892. case 7:
  893. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  894. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  895. break;
  896. default:
  897. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  898. __func__);
  899. return -EINVAL;
  900. };
  901. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  902. __func__, event, dmic, *dmic_clk_cnt);
  903. switch (event) {
  904. case SND_SOC_DAPM_PRE_PMU:
  905. snd_soc_component_update_bits(component,
  906. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  907. /* enable clock scaling */
  908. snd_soc_component_update_bits(component,
  909. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  910. snd_soc_component_update_bits(component,
  911. dmic_clk_reg, 0x07, 0x02);
  912. snd_soc_component_update_bits(component,
  913. dmic_clk_reg, 0x08, 0x08);
  914. snd_soc_component_update_bits(component,
  915. dmic_clk_reg, 0x70, 0x20);
  916. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  917. break;
  918. case SND_SOC_DAPM_POST_PMD:
  919. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  920. break;
  921. };
  922. return 0;
  923. }
  924. /*
  925. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  926. * @micb_mv: micbias in mv
  927. *
  928. * return register value converted
  929. */
  930. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  931. {
  932. /* min micbias voltage is 1V and maximum is 2.85V */
  933. if (micb_mv < 1000 || micb_mv > 2850) {
  934. pr_err("%s: unsupported micbias voltage\n", __func__);
  935. return -EINVAL;
  936. }
  937. return (micb_mv - 1000) / 50;
  938. }
  939. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  940. /*
  941. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  942. * @component: handle to snd_soc_component *
  943. * @req_volt: micbias voltage to be set
  944. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  945. *
  946. * return 0 if adjustment is success or error code in case of failure
  947. */
  948. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  949. int req_volt, int micb_num)
  950. {
  951. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  952. int cur_vout_ctl, req_vout_ctl;
  953. int micb_reg, micb_val, micb_en;
  954. int ret = 0;
  955. switch (micb_num) {
  956. case MIC_BIAS_1:
  957. micb_reg = WCD938X_ANA_MICB1;
  958. break;
  959. case MIC_BIAS_2:
  960. micb_reg = WCD938X_ANA_MICB2;
  961. break;
  962. case MIC_BIAS_3:
  963. micb_reg = WCD938X_ANA_MICB3;
  964. break;
  965. case MIC_BIAS_4:
  966. micb_reg = WCD938X_ANA_MICB4;
  967. break;
  968. default:
  969. return -EINVAL;
  970. }
  971. mutex_lock(&wcd938x->micb_lock);
  972. /*
  973. * If requested micbias voltage is same as current micbias
  974. * voltage, then just return. Otherwise, adjust voltage as
  975. * per requested value. If micbias is already enabled, then
  976. * to avoid slow micbias ramp-up or down enable pull-up
  977. * momentarily, change the micbias value and then re-enable
  978. * micbias.
  979. */
  980. micb_val = snd_soc_component_read32(component, micb_reg);
  981. micb_en = (micb_val & 0xC0) >> 6;
  982. cur_vout_ctl = micb_val & 0x3F;
  983. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  984. if (req_vout_ctl < 0) {
  985. ret = -EINVAL;
  986. goto exit;
  987. }
  988. if (cur_vout_ctl == req_vout_ctl) {
  989. ret = 0;
  990. goto exit;
  991. }
  992. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  993. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  994. req_volt, micb_en);
  995. if (micb_en == 0x1)
  996. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  997. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  998. if (micb_en == 0x1) {
  999. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1000. /*
  1001. * Add 2ms delay as per HW requirement after enabling
  1002. * micbias
  1003. */
  1004. usleep_range(2000, 2100);
  1005. }
  1006. exit:
  1007. mutex_unlock(&wcd938x->micb_lock);
  1008. return ret;
  1009. }
  1010. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1011. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1012. struct snd_kcontrol *kcontrol,
  1013. int event)
  1014. {
  1015. struct snd_soc_component *component =
  1016. snd_soc_dapm_to_component(w->dapm);
  1017. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1018. int ret = 0;
  1019. switch (event) {
  1020. case SND_SOC_DAPM_PRE_PMU:
  1021. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1022. wcd938x->tx_swr_dev->dev_num,
  1023. true);
  1024. break;
  1025. case SND_SOC_DAPM_POST_PMD:
  1026. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1027. wcd938x->tx_swr_dev->dev_num,
  1028. false);
  1029. break;
  1030. };
  1031. return ret;
  1032. }
  1033. static int wcd938x_get_adc_mode(int val)
  1034. {
  1035. int ret = 0;
  1036. switch (val) {
  1037. case ADC_MODE_INVALID:
  1038. ret = ADC_MODE_VAL_NORMAL;
  1039. break;
  1040. case ADC_MODE_HIFI:
  1041. ret = ADC_MODE_VAL_HIFI;
  1042. break;
  1043. case ADC_MODE_LO_HIF:
  1044. ret = ADC_MODE_VAL_LO_HIF;
  1045. break;
  1046. case ADC_MODE_NORMAL:
  1047. ret = ADC_MODE_VAL_NORMAL;
  1048. break;
  1049. case ADC_MODE_LP:
  1050. ret = ADC_MODE_VAL_LP;
  1051. break;
  1052. case ADC_MODE_ULP1:
  1053. ret = ADC_MODE_VAL_ULP1;
  1054. break;
  1055. case ADC_MODE_ULP2:
  1056. ret = ADC_MODE_VAL_ULP2;
  1057. break;
  1058. default:
  1059. ret = -EINVAL;
  1060. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1061. break;
  1062. }
  1063. return ret;
  1064. }
  1065. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1066. struct snd_kcontrol *kcontrol,
  1067. int event){
  1068. int mode;
  1069. struct snd_soc_component *component =
  1070. snd_soc_dapm_to_component(w->dapm);
  1071. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1072. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1073. w->name, event);
  1074. switch (event) {
  1075. case SND_SOC_DAPM_PRE_PMU:
  1076. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1077. if (mode < 0) {
  1078. dev_info(component->dev,
  1079. "%s: invalid mode, setting to normal mode\n",
  1080. __func__);
  1081. mode = ADC_MODE_VAL_NORMAL;
  1082. }
  1083. snd_soc_component_update_bits(component,
  1084. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1085. snd_soc_component_update_bits(component,
  1086. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1087. snd_soc_component_update_bits(component,
  1088. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1089. switch (w->shift) {
  1090. case 0:
  1091. snd_soc_component_update_bits(component,
  1092. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1093. mode);
  1094. break;
  1095. case 1:
  1096. snd_soc_component_update_bits(component,
  1097. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1098. mode << 4);
  1099. break;
  1100. case 2:
  1101. snd_soc_component_update_bits(component,
  1102. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1103. mode);
  1104. break;
  1105. case 3:
  1106. snd_soc_component_update_bits(component,
  1107. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1108. mode << 4);
  1109. break;
  1110. default:
  1111. break;
  1112. }
  1113. set_bit(w->shift, &wcd938x->status_mask);
  1114. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1115. break;
  1116. case SND_SOC_DAPM_POST_PMD:
  1117. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1118. snd_soc_component_update_bits(component,
  1119. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1120. clear_bit(w->shift, &wcd938x->status_mask);
  1121. break;
  1122. };
  1123. return 0;
  1124. }
  1125. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1126. int channel, int mode)
  1127. {
  1128. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1129. int ret = 0;
  1130. switch (channel) {
  1131. case 0:
  1132. reg = WCD938X_ANA_TX_CH2;
  1133. mask = 0x40;
  1134. break;
  1135. case 1:
  1136. reg = WCD938X_ANA_TX_CH2;
  1137. mask = 0x20;
  1138. break;
  1139. case 2:
  1140. reg = WCD938X_ANA_TX_CH4;
  1141. mask = 0x40;
  1142. break;
  1143. case 3:
  1144. reg = WCD938X_ANA_TX_CH4;
  1145. mask = 0x20;
  1146. break;
  1147. default:
  1148. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1149. ret = -EINVAL;
  1150. break;
  1151. }
  1152. if (!mode)
  1153. val = 0x00;
  1154. else
  1155. val = mask;
  1156. if (!ret)
  1157. snd_soc_component_update_bits(component, reg, mask, val);
  1158. return ret;
  1159. }
  1160. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1161. struct snd_kcontrol *kcontrol, int event)
  1162. {
  1163. struct snd_soc_component *component =
  1164. snd_soc_dapm_to_component(w->dapm);
  1165. int ret = 0;
  1166. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1167. w->name, event);
  1168. switch (event) {
  1169. case SND_SOC_DAPM_PRE_PMU:
  1170. snd_soc_component_update_bits(component,
  1171. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1172. snd_soc_component_update_bits(component,
  1173. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1174. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1175. snd_soc_component_update_bits(component,
  1176. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1177. snd_soc_component_update_bits(component,
  1178. WCD938X_ANA_TX_CH1, 0x80, 0x80);
  1179. snd_soc_component_update_bits(component,
  1180. WCD938X_ANA_TX_CH2, 0x80, 0x80);
  1181. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1182. break;
  1183. case SND_SOC_DAPM_POST_PMD:
  1184. snd_soc_component_update_bits(component,
  1185. WCD938X_ANA_TX_CH1, 0x80, 0x00);
  1186. snd_soc_component_update_bits(component,
  1187. WCD938X_ANA_TX_CH2, 0x80, 0x00);
  1188. snd_soc_component_update_bits(component,
  1189. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1190. snd_soc_component_update_bits(component,
  1191. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1192. snd_soc_component_update_bits(component,
  1193. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1194. break;
  1195. };
  1196. return ret;
  1197. }
  1198. int wcd938x_micbias_control(struct snd_soc_component *component,
  1199. int micb_num, int req, bool is_dapm)
  1200. {
  1201. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1202. int micb_index = micb_num - 1;
  1203. u16 micb_reg;
  1204. int pre_off_event = 0, post_off_event = 0;
  1205. int post_on_event = 0, post_dapm_off = 0;
  1206. int post_dapm_on = 0;
  1207. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1208. dev_err(component->dev,
  1209. "%s: Invalid micbias index, micb_ind:%d\n",
  1210. __func__, micb_index);
  1211. return -EINVAL;
  1212. }
  1213. switch (micb_num) {
  1214. case MIC_BIAS_1:
  1215. micb_reg = WCD938X_ANA_MICB1;
  1216. break;
  1217. case MIC_BIAS_2:
  1218. micb_reg = WCD938X_ANA_MICB2;
  1219. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1220. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1221. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1222. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1223. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1224. break;
  1225. case MIC_BIAS_3:
  1226. micb_reg = WCD938X_ANA_MICB3;
  1227. break;
  1228. case MIC_BIAS_4:
  1229. micb_reg = WCD938X_ANA_MICB4;
  1230. break;
  1231. default:
  1232. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1233. __func__, micb_num);
  1234. return -EINVAL;
  1235. };
  1236. mutex_lock(&wcd938x->micb_lock);
  1237. switch (req) {
  1238. case MICB_PULLUP_ENABLE:
  1239. wcd938x->pullup_ref[micb_index]++;
  1240. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1241. (wcd938x->micb_ref[micb_index] == 0))
  1242. snd_soc_component_update_bits(component, micb_reg,
  1243. 0xC0, 0x80);
  1244. break;
  1245. case MICB_PULLUP_DISABLE:
  1246. if (wcd938x->pullup_ref[micb_index] > 0)
  1247. wcd938x->pullup_ref[micb_index]--;
  1248. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1249. (wcd938x->micb_ref[micb_index] == 0))
  1250. snd_soc_component_update_bits(component, micb_reg,
  1251. 0xC0, 0x00);
  1252. break;
  1253. case MICB_ENABLE:
  1254. wcd938x->micb_ref[micb_index]++;
  1255. if (wcd938x->micb_ref[micb_index] == 1) {
  1256. snd_soc_component_update_bits(component,
  1257. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1258. snd_soc_component_update_bits(component,
  1259. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1260. snd_soc_component_update_bits(component,
  1261. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1262. snd_soc_component_update_bits(component,
  1263. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1264. snd_soc_component_update_bits(component,
  1265. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1266. snd_soc_component_update_bits(component,
  1267. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1268. snd_soc_component_update_bits(component,
  1269. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1270. snd_soc_component_update_bits(component,
  1271. micb_reg, 0xC0, 0x40);
  1272. if (post_on_event)
  1273. blocking_notifier_call_chain(
  1274. &wcd938x->mbhc->notifier,
  1275. post_on_event,
  1276. &wcd938x->mbhc->wcd_mbhc);
  1277. }
  1278. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1279. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1280. post_dapm_on,
  1281. &wcd938x->mbhc->wcd_mbhc);
  1282. break;
  1283. case MICB_DISABLE:
  1284. if (wcd938x->micb_ref[micb_index] > 0)
  1285. wcd938x->micb_ref[micb_index]--;
  1286. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1287. (wcd938x->pullup_ref[micb_index] > 0))
  1288. snd_soc_component_update_bits(component, micb_reg,
  1289. 0xC0, 0x80);
  1290. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1291. (wcd938x->pullup_ref[micb_index] == 0)) {
  1292. if (pre_off_event && wcd938x->mbhc)
  1293. blocking_notifier_call_chain(
  1294. &wcd938x->mbhc->notifier,
  1295. pre_off_event,
  1296. &wcd938x->mbhc->wcd_mbhc);
  1297. snd_soc_component_update_bits(component, micb_reg,
  1298. 0xC0, 0x00);
  1299. if (post_off_event && wcd938x->mbhc)
  1300. blocking_notifier_call_chain(
  1301. &wcd938x->mbhc->notifier,
  1302. post_off_event,
  1303. &wcd938x->mbhc->wcd_mbhc);
  1304. }
  1305. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1306. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1307. post_dapm_off,
  1308. &wcd938x->mbhc->wcd_mbhc);
  1309. break;
  1310. };
  1311. dev_dbg(component->dev,
  1312. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1313. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1314. wcd938x->pullup_ref[micb_index]);
  1315. mutex_unlock(&wcd938x->micb_lock);
  1316. return 0;
  1317. }
  1318. EXPORT_SYMBOL(wcd938x_micbias_control);
  1319. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1320. {
  1321. int ret = 0;
  1322. uint8_t devnum = 0;
  1323. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1324. if (ret) {
  1325. dev_err(&swr_dev->dev,
  1326. "%s get devnum %d for dev addr %lx failed\n",
  1327. __func__, devnum, swr_dev->addr);
  1328. swr_remove_device(swr_dev);
  1329. return ret;
  1330. }
  1331. swr_dev->dev_num = devnum;
  1332. return 0;
  1333. }
  1334. static int wcd938x_event_notify(struct notifier_block *block,
  1335. unsigned long val,
  1336. void *data)
  1337. {
  1338. u16 event = (val & 0xffff);
  1339. int ret = 0;
  1340. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1341. struct snd_soc_component *component = wcd938x->component;
  1342. struct wcd_mbhc *mbhc;
  1343. switch (event) {
  1344. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1345. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1346. snd_soc_component_update_bits(component,
  1347. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1348. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1349. }
  1350. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1351. snd_soc_component_update_bits(component,
  1352. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1353. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1354. }
  1355. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1356. snd_soc_component_update_bits(component,
  1357. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1358. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1359. }
  1360. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1361. snd_soc_component_update_bits(component,
  1362. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1363. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1364. }
  1365. break;
  1366. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1367. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1368. 0xC0, 0x00);
  1369. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1370. 0x80, 0x00);
  1371. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1372. 0x80, 0x00);
  1373. break;
  1374. case BOLERO_WCD_EVT_SSR_DOWN:
  1375. wcd938x_reset_low(wcd938x->dev);
  1376. break;
  1377. case BOLERO_WCD_EVT_SSR_UP:
  1378. wcd938x_reset(wcd938x->dev);
  1379. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1380. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1381. regcache_mark_dirty(wcd938x->regmap);
  1382. regcache_sync(wcd938x->regmap);
  1383. /* Initialize MBHC module */
  1384. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1385. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1386. if (ret) {
  1387. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1388. __func__);
  1389. } else {
  1390. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1391. }
  1392. break;
  1393. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1394. snd_soc_component_update_bits(component,
  1395. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1396. ((val >> 0x10) << 0x01));
  1397. break;
  1398. default:
  1399. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1400. break;
  1401. }
  1402. return 0;
  1403. }
  1404. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1405. int event)
  1406. {
  1407. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1408. int micb_num;
  1409. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1410. __func__, w->name, event);
  1411. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1412. micb_num = MIC_BIAS_1;
  1413. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1414. micb_num = MIC_BIAS_2;
  1415. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1416. micb_num = MIC_BIAS_3;
  1417. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1418. micb_num = MIC_BIAS_4;
  1419. else
  1420. return -EINVAL;
  1421. switch (event) {
  1422. case SND_SOC_DAPM_PRE_PMU:
  1423. wcd938x_micbias_control(component, micb_num,
  1424. MICB_ENABLE, true);
  1425. break;
  1426. case SND_SOC_DAPM_POST_PMU:
  1427. /* 1 msec delay as per HW requirement */
  1428. usleep_range(1000, 1100);
  1429. break;
  1430. case SND_SOC_DAPM_POST_PMD:
  1431. wcd938x_micbias_control(component, micb_num,
  1432. MICB_DISABLE, true);
  1433. break;
  1434. };
  1435. return 0;
  1436. }
  1437. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1438. struct snd_kcontrol *kcontrol,
  1439. int event)
  1440. {
  1441. return __wcd938x_codec_enable_micbias(w, event);
  1442. }
  1443. static inline int wcd938x_tx_path_get(const char *wname)
  1444. {
  1445. int ret = 0;
  1446. unsigned int path_num;
  1447. char *widget_name = NULL;
  1448. char *w_name = NULL;
  1449. char *path_num_char = NULL;
  1450. char *path_name = NULL;
  1451. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1452. if (!widget_name)
  1453. return -EINVAL;
  1454. w_name = widget_name;
  1455. path_name = strsep(&widget_name, " ");
  1456. if (!path_name) {
  1457. pr_err("%s: Invalid widget name = %s\n",
  1458. __func__, widget_name);
  1459. ret = -EINVAL;
  1460. goto err;
  1461. }
  1462. path_name = widget_name;
  1463. path_num_char = strpbrk(path_name, "0123");
  1464. if (!path_num_char) {
  1465. pr_err("%s: tx path index not found\n",
  1466. __func__);
  1467. ret = -EINVAL;
  1468. goto err;
  1469. }
  1470. ret = kstrtouint(path_num_char, 10, &path_num);
  1471. if (ret < 0)
  1472. pr_err("%s: Invalid tx path = %s\n",
  1473. __func__, w_name);
  1474. err:
  1475. kfree(w_name);
  1476. return ret;
  1477. }
  1478. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1479. struct snd_ctl_elem_value *ucontrol)
  1480. {
  1481. struct snd_soc_dapm_widget *widget =
  1482. snd_soc_dapm_kcontrol_widget(kcontrol);
  1483. struct snd_soc_component *component =
  1484. snd_soc_kcontrol_component(kcontrol);
  1485. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1486. u32 path = 0;
  1487. if (!widget || !widget->name || !wcd938x || !component)
  1488. return -EINVAL;
  1489. path = wcd938x_tx_path_get(widget->name);
  1490. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1491. return 0;
  1492. }
  1493. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1494. struct snd_ctl_elem_value *ucontrol)
  1495. {
  1496. struct snd_soc_dapm_widget *widget =
  1497. snd_soc_dapm_kcontrol_widget(kcontrol);
  1498. struct snd_soc_component *component =
  1499. snd_soc_kcontrol_component(kcontrol);
  1500. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1501. u32 mode_val;
  1502. u32 path = 0;
  1503. if (!widget || !widget->name || !wcd938x || !component)
  1504. return -EINVAL;
  1505. path = wcd938x_tx_path_get(widget->name);
  1506. mode_val = ucontrol->value.enumerated.item[0];
  1507. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1508. wcd938x->tx_mode[path] = mode_val;
  1509. return 0;
  1510. }
  1511. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1512. struct snd_ctl_elem_value *ucontrol)
  1513. {
  1514. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1515. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1516. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1517. return 0;
  1518. }
  1519. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1520. struct snd_ctl_elem_value *ucontrol)
  1521. {
  1522. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1523. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1524. u32 mode_val;
  1525. mode_val = ucontrol->value.enumerated.item[0];
  1526. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1527. if (mode_val == 0) {
  1528. dev_info(component->dev,
  1529. "%s:Invalid HPH Mode, default to class_AB\n",
  1530. __func__);
  1531. mode_val = 3; /* enum will be updated later */
  1532. }
  1533. wcd938x->hph_mode = mode_val;
  1534. return 0;
  1535. }
  1536. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1537. struct snd_ctl_elem_value *ucontrol)
  1538. {
  1539. struct snd_soc_component *component =
  1540. snd_soc_kcontrol_component(kcontrol);
  1541. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1542. bool hphr;
  1543. struct soc_multi_mixer_control *mc;
  1544. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1545. hphr = mc->shift;
  1546. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1547. wcd938x->comp1_enable;
  1548. return 0;
  1549. }
  1550. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1551. struct snd_ctl_elem_value *ucontrol)
  1552. {
  1553. struct snd_soc_component *component =
  1554. snd_soc_kcontrol_component(kcontrol);
  1555. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1556. int value = ucontrol->value.integer.value[0];
  1557. bool hphr;
  1558. struct soc_multi_mixer_control *mc;
  1559. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1560. hphr = mc->shift;
  1561. if (hphr)
  1562. wcd938x->comp2_enable = value;
  1563. else
  1564. wcd938x->comp1_enable = value;
  1565. return 0;
  1566. }
  1567. static const char * const tx_mode_mux_text[] = {
  1568. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1569. "ADC_ULP1", "ADC_ULP2",
  1570. };
  1571. static const struct soc_enum tx_mode_mux_enum =
  1572. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  1573. tx_mode_mux_text);
  1574. static const char * const rx_hph_mode_mux_text[] = {
  1575. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1576. "CLS_H_ULP", "CLS_AB_HIFI",
  1577. };
  1578. static const struct soc_enum rx_hph_mode_mux_enum =
  1579. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1580. rx_hph_mode_mux_text);
  1581. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  1582. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1583. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1584. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  1585. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1586. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  1587. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1588. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  1589. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1590. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  1591. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1592. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1593. wcd938x_get_compander, wcd938x_set_compander),
  1594. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1595. wcd938x_get_compander, wcd938x_set_compander),
  1596. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  1597. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  1598. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  1599. analog_gain),
  1600. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  1601. analog_gain),
  1602. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  1603. analog_gain),
  1604. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  1605. analog_gain),
  1606. };
  1607. static const struct snd_kcontrol_new adc1_switch[] = {
  1608. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1609. };
  1610. static const struct snd_kcontrol_new adc2_switch[] = {
  1611. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1612. };
  1613. static const struct snd_kcontrol_new adc3_switch[] = {
  1614. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1615. };
  1616. static const struct snd_kcontrol_new adc4_switch[] = {
  1617. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1618. };
  1619. static const struct snd_kcontrol_new dmic1_switch[] = {
  1620. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1621. };
  1622. static const struct snd_kcontrol_new dmic2_switch[] = {
  1623. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1624. };
  1625. static const struct snd_kcontrol_new dmic3_switch[] = {
  1626. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1627. };
  1628. static const struct snd_kcontrol_new dmic4_switch[] = {
  1629. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1630. };
  1631. static const struct snd_kcontrol_new dmic5_switch[] = {
  1632. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1633. };
  1634. static const struct snd_kcontrol_new dmic6_switch[] = {
  1635. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1636. };
  1637. static const struct snd_kcontrol_new dmic7_switch[] = {
  1638. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1639. };
  1640. static const struct snd_kcontrol_new dmic8_switch[] = {
  1641. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1642. };
  1643. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1644. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1645. };
  1646. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1647. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1648. };
  1649. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1650. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1651. };
  1652. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1653. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1654. };
  1655. static const char * const adc2_mux_text[] = {
  1656. "INP2", "INP3"
  1657. };
  1658. static const struct soc_enum adc2_enum =
  1659. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  1660. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1661. static const struct snd_kcontrol_new tx_adc2_mux =
  1662. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1663. static const char * const adc3_mux_text[] = {
  1664. "INP4", "INP6"
  1665. };
  1666. static const struct soc_enum adc3_enum =
  1667. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  1668. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  1669. static const struct snd_kcontrol_new tx_adc3_mux =
  1670. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  1671. static const char * const adc4_mux_text[] = {
  1672. "INP5", "INP7"
  1673. };
  1674. static const struct soc_enum adc4_enum =
  1675. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  1676. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  1677. static const struct snd_kcontrol_new tx_adc4_mux =
  1678. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  1679. static const char * const rdac3_mux_text[] = {
  1680. "RX1", "RX3"
  1681. };
  1682. static const char * const hdr12_mux_text[] = {
  1683. "NO_HDR12", "HDR12"
  1684. };
  1685. static const struct soc_enum hdr12_enum =
  1686. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  1687. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  1688. static const struct snd_kcontrol_new tx_hdr12_mux =
  1689. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  1690. static const char * const hdr34_mux_text[] = {
  1691. "NO_HDR34", "HDR34"
  1692. };
  1693. static const struct soc_enum hdr34_enum =
  1694. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  1695. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  1696. static const struct snd_kcontrol_new tx_hdr34_mux =
  1697. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  1698. static const struct soc_enum rdac3_enum =
  1699. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1700. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1701. static const struct snd_kcontrol_new rx_rdac3_mux =
  1702. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1703. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  1704. /*input widgets*/
  1705. SND_SOC_DAPM_INPUT("AMIC1"),
  1706. SND_SOC_DAPM_INPUT("AMIC2"),
  1707. SND_SOC_DAPM_INPUT("AMIC3"),
  1708. SND_SOC_DAPM_INPUT("AMIC4"),
  1709. SND_SOC_DAPM_INPUT("AMIC5"),
  1710. SND_SOC_DAPM_INPUT("AMIC6"),
  1711. SND_SOC_DAPM_INPUT("AMIC7"),
  1712. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1713. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1714. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1715. /*tx widgets*/
  1716. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1717. wcd938x_codec_enable_adc,
  1718. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1719. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1720. wcd938x_codec_enable_adc,
  1721. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1722. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1723. wcd938x_codec_enable_adc,
  1724. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1725. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  1726. wcd938x_codec_enable_adc,
  1727. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1728. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1729. wcd938x_codec_enable_dmic,
  1730. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1731. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1732. wcd938x_codec_enable_dmic,
  1733. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1734. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1735. wcd938x_codec_enable_dmic,
  1736. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1737. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1738. wcd938x_codec_enable_dmic,
  1739. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1740. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1741. wcd938x_codec_enable_dmic,
  1742. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1743. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1744. wcd938x_codec_enable_dmic,
  1745. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1746. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  1747. wcd938x_codec_enable_dmic,
  1748. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1749. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  1750. wcd938x_codec_enable_dmic,
  1751. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1752. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1753. NULL, 0, wcd938x_enable_req,
  1754. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1755. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  1756. NULL, 0, wcd938x_enable_req,
  1757. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1758. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  1759. NULL, 0, wcd938x_enable_req,
  1760. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1761. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  1762. NULL, 0, wcd938x_enable_req,
  1763. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1764. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1765. &tx_adc2_mux),
  1766. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  1767. &tx_adc3_mux),
  1768. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  1769. &tx_adc4_mux),
  1770. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  1771. &tx_hdr12_mux),
  1772. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  1773. &tx_hdr34_mux),
  1774. /*tx mixers*/
  1775. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1776. adc1_switch, ARRAY_SIZE(adc1_switch),
  1777. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1778. SND_SOC_DAPM_POST_PMD),
  1779. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1780. adc2_switch, ARRAY_SIZE(adc2_switch),
  1781. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1782. SND_SOC_DAPM_POST_PMD),
  1783. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1784. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  1785. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1786. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  1787. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  1788. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1789. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1790. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1791. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1792. SND_SOC_DAPM_POST_PMD),
  1793. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1794. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1795. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1796. SND_SOC_DAPM_POST_PMD),
  1797. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1798. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1799. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1800. SND_SOC_DAPM_POST_PMD),
  1801. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1802. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1803. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1804. SND_SOC_DAPM_POST_PMD),
  1805. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1806. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1807. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1808. SND_SOC_DAPM_POST_PMD),
  1809. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1810. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1811. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1812. SND_SOC_DAPM_POST_PMD),
  1813. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  1814. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  1815. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1816. SND_SOC_DAPM_POST_PMD),
  1817. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  1818. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  1819. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1820. SND_SOC_DAPM_POST_PMD),
  1821. /* micbias widgets*/
  1822. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1823. wcd938x_codec_enable_micbias,
  1824. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1825. SND_SOC_DAPM_POST_PMD),
  1826. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1827. wcd938x_codec_enable_micbias,
  1828. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1829. SND_SOC_DAPM_POST_PMD),
  1830. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1831. wcd938x_codec_enable_micbias,
  1832. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1833. SND_SOC_DAPM_POST_PMD),
  1834. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  1835. wcd938x_codec_enable_micbias,
  1836. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1837. SND_SOC_DAPM_POST_PMD),
  1838. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1839. wcd938x_enable_clsh,
  1840. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1841. /*rx widgets*/
  1842. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  1843. wcd938x_codec_enable_ear_pa,
  1844. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1845. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1846. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  1847. wcd938x_codec_enable_aux_pa,
  1848. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1849. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1850. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  1851. wcd938x_codec_enable_hphl_pa,
  1852. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1853. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1854. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  1855. wcd938x_codec_enable_hphr_pa,
  1856. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1857. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1858. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1859. wcd938x_codec_hphl_dac_event,
  1860. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1861. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1862. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1863. wcd938x_codec_hphr_dac_event,
  1864. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1865. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1866. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1867. wcd938x_codec_ear_dac_event,
  1868. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1869. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1870. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1871. wcd938x_codec_aux_dac_event,
  1872. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1873. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1874. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1875. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1876. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1877. SND_SOC_DAPM_POST_PMD),
  1878. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1879. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1880. SND_SOC_DAPM_POST_PMD),
  1881. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1882. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1883. SND_SOC_DAPM_POST_PMD),
  1884. /* rx mixer widgets*/
  1885. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1886. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1887. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1888. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1889. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1890. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1891. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1892. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1893. /*output widgets tx*/
  1894. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1895. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1896. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1897. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  1898. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1899. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1900. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1901. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1902. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1903. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1904. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  1905. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  1906. /*output widgets rx*/
  1907. SND_SOC_DAPM_OUTPUT("EAR"),
  1908. SND_SOC_DAPM_OUTPUT("AUX"),
  1909. SND_SOC_DAPM_OUTPUT("HPHL"),
  1910. SND_SOC_DAPM_OUTPUT("HPHR"),
  1911. };
  1912. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  1913. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1914. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1915. {"ADC1 REQ", NULL, "ADC1"},
  1916. {"ADC1", NULL, "AMIC1"},
  1917. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1918. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1919. {"ADC2 REQ", NULL, "ADC2"},
  1920. {"ADC2", NULL, "HDR12 MUX"},
  1921. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  1922. {"HDR12 MUX", "HDR12", "AMIC1"},
  1923. {"ADC2 MUX", "INP3", "AMIC3"},
  1924. {"ADC2 MUX", "INP2", "AMIC2"},
  1925. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1926. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1927. {"ADC3 REQ", NULL, "ADC3"},
  1928. {"ADC3", NULL, "HDR34 MUX"},
  1929. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  1930. {"HDR34 MUX", "HDR34", "AMIC5"},
  1931. {"ADC3 MUX", "INP4", "AMIC4"},
  1932. {"ADC3 MUX", "INP6", "AMIC6"},
  1933. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  1934. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  1935. {"ADC4 REQ", NULL, "ADC4"},
  1936. {"ADC4", NULL, "ADC4 MUX"},
  1937. {"ADC4 MUX", "INP5", "AMIC5"},
  1938. {"ADC4 MUX", "INP7", "AMIC7"},
  1939. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1940. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1941. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1942. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1943. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1944. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1945. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1946. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1947. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1948. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1949. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1950. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1951. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  1952. {"DMIC7_MIXER", "Switch", "DMIC7"},
  1953. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  1954. {"DMIC8_MIXER", "Switch", "DMIC8"},
  1955. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1956. {"RX1", NULL, "IN1_HPHL"},
  1957. {"RDAC1", NULL, "RX1"},
  1958. {"HPHL_RDAC", "Switch", "RDAC1"},
  1959. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1960. {"HPHL", NULL, "HPHL PGA"},
  1961. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1962. {"RX2", NULL, "IN2_HPHR"},
  1963. {"RDAC2", NULL, "RX2"},
  1964. {"HPHR_RDAC", "Switch", "RDAC2"},
  1965. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1966. {"HPHR", NULL, "HPHR PGA"},
  1967. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1968. {"RX3", NULL, "IN3_AUX"},
  1969. {"RDAC4", NULL, "RX3"},
  1970. {"AUX_RDAC", "Switch", "RDAC4"},
  1971. {"AUX PGA", NULL, "AUX_RDAC"},
  1972. {"AUX", NULL, "AUX PGA"},
  1973. {"RDAC3_MUX", "RX3", "RX3"},
  1974. {"RDAC3_MUX", "RX1", "RX1"},
  1975. {"RDAC3", NULL, "RDAC3_MUX"},
  1976. {"EAR_RDAC", "Switch", "RDAC3"},
  1977. {"EAR PGA", NULL, "EAR_RDAC"},
  1978. {"EAR", NULL, "EAR PGA"},
  1979. };
  1980. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  1981. void *file_private_data,
  1982. struct file *file,
  1983. char __user *buf, size_t count,
  1984. loff_t pos)
  1985. {
  1986. struct wcd938x_priv *priv;
  1987. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  1988. int len = 0;
  1989. priv = (struct wcd938x_priv *) entry->private_data;
  1990. if (!priv) {
  1991. pr_err("%s: wcd938x priv is null\n", __func__);
  1992. return -EINVAL;
  1993. }
  1994. switch (priv->version) {
  1995. case WCD938X_VERSION_1_0:
  1996. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  1997. break;
  1998. default:
  1999. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2000. }
  2001. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2002. }
  2003. static struct snd_info_entry_ops wcd938x_info_ops = {
  2004. .read = wcd938x_version_read,
  2005. };
  2006. /*
  2007. * wcd938x_info_create_codec_entry - creates wcd938x module
  2008. * @codec_root: The parent directory
  2009. * @component: component instance
  2010. *
  2011. * Creates wcd938x module and version entry under the given
  2012. * parent directory.
  2013. *
  2014. * Return: 0 on success or negative error code on failure.
  2015. */
  2016. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2017. struct snd_soc_component *component)
  2018. {
  2019. struct snd_info_entry *version_entry;
  2020. struct wcd938x_priv *priv;
  2021. struct snd_soc_card *card;
  2022. if (!codec_root || !component)
  2023. return -EINVAL;
  2024. priv = snd_soc_component_get_drvdata(component);
  2025. if (priv->entry) {
  2026. dev_dbg(priv->dev,
  2027. "%s:wcd938x module already created\n", __func__);
  2028. return 0;
  2029. }
  2030. card = component->card;
  2031. priv->entry = snd_info_create_subdir(codec_root->module,
  2032. "wcd938x", codec_root);
  2033. if (!priv->entry) {
  2034. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2035. __func__);
  2036. return -ENOMEM;
  2037. }
  2038. version_entry = snd_info_create_card_entry(card->snd_card,
  2039. "version",
  2040. priv->entry);
  2041. if (!version_entry) {
  2042. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2043. __func__);
  2044. return -ENOMEM;
  2045. }
  2046. version_entry->private_data = priv;
  2047. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2048. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2049. version_entry->c.ops = &wcd938x_info_ops;
  2050. if (snd_info_register(version_entry) < 0) {
  2051. snd_info_free_entry(version_entry);
  2052. return -ENOMEM;
  2053. }
  2054. priv->version_entry = version_entry;
  2055. return 0;
  2056. }
  2057. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2058. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2059. {
  2060. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2061. struct snd_soc_dapm_context *dapm =
  2062. snd_soc_component_get_dapm(component);
  2063. int variant;
  2064. int ret = -EINVAL;
  2065. dev_info(component->dev, "%s()\n", __func__);
  2066. wcd938x = snd_soc_component_get_drvdata(component);
  2067. if (!wcd938x)
  2068. return -EINVAL;
  2069. wcd938x->component = component;
  2070. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2071. variant = (snd_soc_component_read32(component,
  2072. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2073. wcd938x->variant = variant;
  2074. wcd938x->fw_data = devm_kzalloc(component->dev,
  2075. sizeof(*(wcd938x->fw_data)),
  2076. GFP_KERNEL);
  2077. if (!wcd938x->fw_data) {
  2078. dev_err(component->dev, "Failed to allocate fw_data\n");
  2079. ret = -ENOMEM;
  2080. goto err;
  2081. }
  2082. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2083. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2084. WCD9XXX_CODEC_HWDEP_NODE, component);
  2085. if (ret < 0) {
  2086. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2087. goto err_hwdep;
  2088. }
  2089. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2090. if (ret) {
  2091. pr_err("%s: mbhc initialization failed\n", __func__);
  2092. goto err_hwdep;
  2093. }
  2094. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2095. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2096. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2097. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2098. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2099. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2100. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2101. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2102. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2103. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2104. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2105. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2106. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2107. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  2108. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  2109. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2110. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2111. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2112. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  2113. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2114. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2115. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2116. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2117. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2118. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2119. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2120. snd_soc_dapm_sync(dapm);
  2121. wcd_cls_h_init(&wcd938x->clsh_info);
  2122. wcd938x_init_reg(component);
  2123. wcd938x->version = WCD938X_VERSION_1_0;
  2124. /* Register event notifier */
  2125. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2126. if (wcd938x->register_notifier) {
  2127. ret = wcd938x->register_notifier(wcd938x->handle,
  2128. &wcd938x->nblock,
  2129. true);
  2130. if (ret) {
  2131. dev_err(component->dev,
  2132. "%s: Failed to register notifier %d\n",
  2133. __func__, ret);
  2134. return ret;
  2135. }
  2136. }
  2137. return ret;
  2138. err_hwdep:
  2139. wcd938x->fw_data = NULL;
  2140. err:
  2141. return ret;
  2142. }
  2143. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2144. {
  2145. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2146. if (!wcd938x) {
  2147. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2148. __func__);
  2149. return;
  2150. }
  2151. if (wcd938x->register_notifier)
  2152. wcd938x->register_notifier(wcd938x->handle,
  2153. &wcd938x->nblock,
  2154. false);
  2155. }
  2156. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2157. .name = WCD938X_DRV_NAME,
  2158. .probe = wcd938x_soc_codec_probe,
  2159. .remove = wcd938x_soc_codec_remove,
  2160. .controls = wcd938x_snd_controls,
  2161. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2162. .dapm_widgets = wcd938x_dapm_widgets,
  2163. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2164. .dapm_routes = wcd938x_audio_map,
  2165. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2166. };
  2167. static int wcd938x_reset(struct device *dev)
  2168. {
  2169. struct wcd938x_priv *wcd938x = NULL;
  2170. int rc = 0;
  2171. int value = 0;
  2172. if (!dev)
  2173. return -ENODEV;
  2174. wcd938x = dev_get_drvdata(dev);
  2175. if (!wcd938x)
  2176. return -EINVAL;
  2177. if (!wcd938x->rst_np) {
  2178. dev_err(dev, "%s: reset gpio device node not specified\n",
  2179. __func__);
  2180. return -EINVAL;
  2181. }
  2182. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2183. if (value > 0)
  2184. return 0;
  2185. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2186. if (rc) {
  2187. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2188. __func__);
  2189. return rc;
  2190. }
  2191. /* 20us sleep required after pulling the reset gpio to LOW */
  2192. usleep_range(20, 30);
  2193. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2194. if (rc) {
  2195. dev_err(dev, "%s: wcd active state request fail!\n",
  2196. __func__);
  2197. return rc;
  2198. }
  2199. /* 20us sleep required after pulling the reset gpio to HIGH */
  2200. usleep_range(20, 30);
  2201. return rc;
  2202. }
  2203. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2204. u32 *val)
  2205. {
  2206. int rc = 0;
  2207. rc = of_property_read_u32(dev->of_node, name, val);
  2208. if (rc)
  2209. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2210. __func__, name, dev->of_node->full_name);
  2211. return rc;
  2212. }
  2213. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2214. struct wcd938x_micbias_setting *mb)
  2215. {
  2216. u32 prop_val = 0;
  2217. int rc = 0;
  2218. /* MB1 */
  2219. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2220. NULL)) {
  2221. rc = wcd938x_read_of_property_u32(dev,
  2222. "qcom,cdc-micbias1-mv",
  2223. &prop_val);
  2224. if (!rc)
  2225. mb->micb1_mv = prop_val;
  2226. } else {
  2227. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2228. __func__);
  2229. }
  2230. /* MB2 */
  2231. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2232. NULL)) {
  2233. rc = wcd938x_read_of_property_u32(dev,
  2234. "qcom,cdc-micbias2-mv",
  2235. &prop_val);
  2236. if (!rc)
  2237. mb->micb2_mv = prop_val;
  2238. } else {
  2239. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2240. __func__);
  2241. }
  2242. /* MB3 */
  2243. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2244. NULL)) {
  2245. rc = wcd938x_read_of_property_u32(dev,
  2246. "qcom,cdc-micbias3-mv",
  2247. &prop_val);
  2248. if (!rc)
  2249. mb->micb3_mv = prop_val;
  2250. } else {
  2251. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2252. __func__);
  2253. }
  2254. }
  2255. static int wcd938x_reset_low(struct device *dev)
  2256. {
  2257. struct wcd938x_priv *wcd938x = NULL;
  2258. int rc = 0;
  2259. if (!dev)
  2260. return -ENODEV;
  2261. wcd938x = dev_get_drvdata(dev);
  2262. if (!wcd938x)
  2263. return -EINVAL;
  2264. if (!wcd938x->rst_np) {
  2265. dev_err(dev, "%s: reset gpio device node not specified\n",
  2266. __func__);
  2267. return -EINVAL;
  2268. }
  2269. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2270. if (rc) {
  2271. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2272. __func__);
  2273. return rc;
  2274. }
  2275. /* 20us sleep required after pulling the reset gpio to LOW */
  2276. usleep_range(20, 30);
  2277. return rc;
  2278. }
  2279. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2280. {
  2281. struct wcd938x_pdata *pdata = NULL;
  2282. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2283. GFP_KERNEL);
  2284. if (!pdata)
  2285. return NULL;
  2286. pdata->rst_np = of_parse_phandle(dev->of_node,
  2287. "qcom,wcd-rst-gpio-node", 0);
  2288. if (!pdata->rst_np) {
  2289. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2290. __func__, "qcom,wcd-rst-gpio-node",
  2291. dev->of_node->full_name);
  2292. return NULL;
  2293. }
  2294. /* Parse power supplies */
  2295. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2296. &pdata->num_supplies);
  2297. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2298. dev_err(dev, "%s: no power supplies defined for codec\n",
  2299. __func__);
  2300. return NULL;
  2301. }
  2302. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2303. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2304. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2305. return pdata;
  2306. }
  2307. static int wcd938x_bind(struct device *dev)
  2308. {
  2309. int ret = 0, i = 0;
  2310. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2311. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2312. /*
  2313. * Add 5msec delay to provide sufficient time for
  2314. * soundwire auto enumeration of slave devices as
  2315. * as per HW requirement.
  2316. */
  2317. usleep_range(5000, 5010);
  2318. ret = component_bind_all(dev, wcd938x);
  2319. if (ret) {
  2320. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2321. __func__, ret);
  2322. return ret;
  2323. }
  2324. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2325. if (!wcd938x->rx_swr_dev) {
  2326. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2327. __func__);
  2328. ret = -ENODEV;
  2329. goto err;
  2330. }
  2331. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2332. if (!wcd938x->tx_swr_dev) {
  2333. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2334. __func__);
  2335. ret = -ENODEV;
  2336. goto err;
  2337. }
  2338. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2339. &wcd938x_regmap_config);
  2340. if (!wcd938x->regmap) {
  2341. dev_err(dev, "%s: Regmap init failed\n",
  2342. __func__);
  2343. goto err;
  2344. }
  2345. /* Set all interupts as edge triggered */
  2346. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2347. regmap_write(wcd938x->regmap,
  2348. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2349. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2350. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2351. wcd938x->irq_info.codec_name = "WCD938X";
  2352. wcd938x->irq_info.regmap = wcd938x->regmap;
  2353. wcd938x->irq_info.dev = dev;
  2354. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2355. if (ret) {
  2356. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2357. __func__, ret);
  2358. goto err;
  2359. }
  2360. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2361. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2362. NULL, 0);
  2363. if (ret) {
  2364. dev_err(dev, "%s: Codec registration failed\n",
  2365. __func__);
  2366. goto err_irq;
  2367. }
  2368. return ret;
  2369. err_irq:
  2370. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2371. err:
  2372. component_unbind_all(dev, wcd938x);
  2373. return ret;
  2374. }
  2375. static void wcd938x_unbind(struct device *dev)
  2376. {
  2377. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2378. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2379. snd_soc_unregister_component(dev);
  2380. component_unbind_all(dev, wcd938x);
  2381. }
  2382. static const struct of_device_id wcd938x_dt_match[] = {
  2383. { .compatible = "qcom,wcd938x-codec" },
  2384. {}
  2385. };
  2386. static const struct component_master_ops wcd938x_comp_ops = {
  2387. .bind = wcd938x_bind,
  2388. .unbind = wcd938x_unbind,
  2389. };
  2390. static int wcd938x_compare_of(struct device *dev, void *data)
  2391. {
  2392. return dev->of_node == data;
  2393. }
  2394. static void wcd938x_release_of(struct device *dev, void *data)
  2395. {
  2396. of_node_put(data);
  2397. }
  2398. static int wcd938x_add_slave_components(struct device *dev,
  2399. struct component_match **matchptr)
  2400. {
  2401. struct device_node *np, *rx_node, *tx_node;
  2402. np = dev->of_node;
  2403. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2404. if (!rx_node) {
  2405. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2406. return -ENODEV;
  2407. }
  2408. of_node_get(rx_node);
  2409. component_match_add_release(dev, matchptr,
  2410. wcd938x_release_of,
  2411. wcd938x_compare_of,
  2412. rx_node);
  2413. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2414. if (!tx_node) {
  2415. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2416. return -ENODEV;
  2417. }
  2418. of_node_get(tx_node);
  2419. component_match_add_release(dev, matchptr,
  2420. wcd938x_release_of,
  2421. wcd938x_compare_of,
  2422. tx_node);
  2423. return 0;
  2424. }
  2425. static int wcd938x_wakeup(void *handle, bool enable)
  2426. {
  2427. struct wcd938x_priv *priv;
  2428. if (!handle) {
  2429. pr_err("%s: NULL handle\n", __func__);
  2430. return -EINVAL;
  2431. }
  2432. priv = (struct wcd938x_priv *)handle;
  2433. if (!priv->tx_swr_dev) {
  2434. pr_err("%s: tx swr dev is NULL\n", __func__);
  2435. return -EINVAL;
  2436. }
  2437. if (enable)
  2438. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2439. else
  2440. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2441. }
  2442. static int wcd938x_probe(struct platform_device *pdev)
  2443. {
  2444. struct component_match *match = NULL;
  2445. struct wcd938x_priv *wcd938x = NULL;
  2446. struct wcd938x_pdata *pdata = NULL;
  2447. struct wcd_ctrl_platform_data *plat_data = NULL;
  2448. struct device *dev = &pdev->dev;
  2449. int ret;
  2450. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  2451. GFP_KERNEL);
  2452. if (!wcd938x)
  2453. return -ENOMEM;
  2454. dev_set_drvdata(dev, wcd938x);
  2455. pdata = wcd938x_populate_dt_data(dev);
  2456. if (!pdata) {
  2457. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2458. return -EINVAL;
  2459. }
  2460. dev->platform_data = pdata;
  2461. wcd938x->rst_np = pdata->rst_np;
  2462. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  2463. pdata->regulator, pdata->num_supplies);
  2464. if (!wcd938x->supplies) {
  2465. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2466. __func__);
  2467. return ret;
  2468. }
  2469. plat_data = dev_get_platdata(dev->parent);
  2470. if (!plat_data) {
  2471. dev_err(dev, "%s: platform data from parent is NULL\n",
  2472. __func__);
  2473. return -EINVAL;
  2474. }
  2475. wcd938x->handle = (void *)plat_data->handle;
  2476. if (!wcd938x->handle) {
  2477. dev_err(dev, "%s: handle is NULL\n", __func__);
  2478. return -EINVAL;
  2479. }
  2480. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  2481. if (!wcd938x->update_wcd_event) {
  2482. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2483. __func__);
  2484. return -EINVAL;
  2485. }
  2486. wcd938x->register_notifier = plat_data->register_notifier;
  2487. if (!wcd938x->register_notifier) {
  2488. dev_err(dev, "%s: register_notifier api is null!\n",
  2489. __func__);
  2490. return -EINVAL;
  2491. }
  2492. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  2493. pdata->regulator,
  2494. pdata->num_supplies);
  2495. if (ret) {
  2496. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2497. __func__);
  2498. return ret;
  2499. }
  2500. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  2501. CODEC_RX);
  2502. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  2503. CODEC_TX);
  2504. if (ret) {
  2505. dev_err(dev, "Failed to read port mapping\n");
  2506. goto err;
  2507. }
  2508. ret = wcd938x_add_slave_components(dev, &match);
  2509. if (ret)
  2510. goto err;
  2511. wcd938x_reset(dev);
  2512. wcd938x->wakeup = wcd938x_wakeup;
  2513. return component_master_add_with_match(dev,
  2514. &wcd938x_comp_ops, match);
  2515. err:
  2516. return ret;
  2517. }
  2518. static int wcd938x_remove(struct platform_device *pdev)
  2519. {
  2520. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  2521. dev_set_drvdata(&pdev->dev, NULL);
  2522. return 0;
  2523. }
  2524. #ifdef CONFIG_PM_SLEEP
  2525. static int wcd938x_suspend(struct device *dev)
  2526. {
  2527. return 0;
  2528. }
  2529. static int wcd938x_resume(struct device *dev)
  2530. {
  2531. return 0;
  2532. }
  2533. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  2534. SET_SYSTEM_SLEEP_PM_OPS(
  2535. wcd938x_suspend,
  2536. wcd938x_resume
  2537. )
  2538. };
  2539. #endif
  2540. static struct platform_driver wcd938x_codec_driver = {
  2541. .probe = wcd938x_probe,
  2542. .remove = wcd938x_remove,
  2543. .driver = {
  2544. .name = "wcd938x_codec",
  2545. .owner = THIS_MODULE,
  2546. .of_match_table = of_match_ptr(wcd938x_dt_match),
  2547. #ifdef CONFIG_PM_SLEEP
  2548. .pm = &wcd938x_dev_pm_ops,
  2549. #endif
  2550. },
  2551. };
  2552. module_platform_driver(wcd938x_codec_driver);
  2553. MODULE_DESCRIPTION("WCD938X Codec driver");
  2554. MODULE_LICENSE("GPL v2");