dp_tx.c 72 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include <wlan_cfg.h>
  27. #ifdef MESH_MODE_SUPPORT
  28. #include "if_meta_hdr.h"
  29. #endif
  30. #ifdef TX_PER_PDEV_DESC_POOL
  31. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  32. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  33. #else
  34. #ifdef TX_PER_VDEV_DESC_POOL
  35. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  36. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  37. #else
  38. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  39. #define DP_TX_GET_RING_ID(vdev) qdf_get_cpu()
  40. #endif /* TX_PER_VDEV_DESC_POOL */
  41. #endif /* TX_PER_PDEV_DESC_POOL */
  42. /* TODO Add support in TSO */
  43. #define DP_DESC_NUM_FRAG(x) 0
  44. /* disable TQM_BYPASS */
  45. #define TQM_BYPASS_WAR 0
  46. /**
  47. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  48. * @vdev: DP Virtual device handle
  49. * @nbuf: Buffer pointer
  50. * @queue: queue ids container for nbuf
  51. *
  52. * TX packet queue has 2 instances, software descriptors id and dma ring id
  53. * Based on tx feature and hardware configuration queue id combination could be
  54. * different.
  55. * For example -
  56. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  57. * With no XPS,lock based resource protection, Descriptor pool ids are different
  58. * for each vdev, dma ring id will be same as single pdev id
  59. *
  60. * Return: None
  61. */
  62. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  63. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  64. {
  65. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  66. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  67. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  68. "%s, pool_id:%d ring_id: %d\n",
  69. __func__, queue->desc_pool_id, queue->ring_id);
  70. return;
  71. }
  72. #if defined(FEATURE_TSO)
  73. /**
  74. * dp_tx_tso_desc_release() - Release the tso segment
  75. * after unmapping all the fragments
  76. *
  77. * @pdev - physical device handle
  78. * @tx_desc - Tx software descriptor
  79. */
  80. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  81. struct dp_tx_desc_s *tx_desc)
  82. {
  83. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  84. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  85. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  86. "%s %d TSO desc is NULL!",
  87. __func__, __LINE__);
  88. qdf_assert(0);
  89. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  90. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  91. "%s %d TSO common info is NULL!",
  92. __func__, __LINE__);
  93. qdf_assert(0);
  94. } else {
  95. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  96. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  97. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  98. tso_num_desc->num_seg.tso_cmn_num_seg--;
  99. qdf_nbuf_unmap_tso_segment(soc->osdev,
  100. tx_desc->tso_desc, false);
  101. } else {
  102. tso_num_desc->num_seg.tso_cmn_num_seg--;
  103. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  104. qdf_nbuf_unmap_tso_segment(soc->osdev,
  105. tx_desc->tso_desc, true);
  106. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  107. tx_desc->tso_num_desc);
  108. tx_desc->tso_num_desc = NULL;
  109. }
  110. dp_tx_tso_desc_free(soc,
  111. tx_desc->pool_id, tx_desc->tso_desc);
  112. tx_desc->tso_desc = NULL;
  113. }
  114. }
  115. #else
  116. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  117. struct dp_tx_desc_s *tx_desc)
  118. {
  119. return;
  120. }
  121. #endif
  122. /**
  123. * dp_tx_desc_release() - Release Tx Descriptor
  124. * @tx_desc : Tx Descriptor
  125. * @desc_pool_id: Descriptor Pool ID
  126. *
  127. * Deallocate all resources attached to Tx descriptor and free the Tx
  128. * descriptor.
  129. *
  130. * Return:
  131. */
  132. static void
  133. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  134. {
  135. struct dp_pdev *pdev = tx_desc->pdev;
  136. struct dp_soc *soc;
  137. uint8_t comp_status = 0;
  138. qdf_assert(pdev);
  139. soc = pdev->soc;
  140. if (tx_desc->frm_type == dp_tx_frm_tso)
  141. dp_tx_tso_desc_release(soc, tx_desc);
  142. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  143. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  144. qdf_atomic_dec(&pdev->num_tx_outstanding);
  145. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  146. qdf_atomic_dec(&pdev->num_tx_exception);
  147. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  148. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  149. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  150. else
  151. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  152. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  153. "Tx Completion Release desc %d status %d outstanding %d\n",
  154. tx_desc->id, comp_status,
  155. qdf_atomic_read(&pdev->num_tx_outstanding));
  156. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  157. return;
  158. }
  159. /**
  160. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  161. * @vdev: DP vdev Handle
  162. * @nbuf: skb
  163. *
  164. * Prepares and fills HTT metadata in the frame pre-header for special frames
  165. * that should be transmitted using varying transmit parameters.
  166. * There are 2 VDEV modes that currently needs this special metadata -
  167. * 1) Mesh Mode
  168. * 2) DSRC Mode
  169. *
  170. * Return: HTT metadata size
  171. *
  172. */
  173. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  174. uint32_t *meta_data)
  175. {
  176. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  177. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  178. uint8_t htt_desc_size;
  179. /* Size rounded of multiple of 8 bytes */
  180. uint8_t htt_desc_size_aligned;
  181. uint8_t *hdr = NULL;
  182. qdf_nbuf_unshare(nbuf);
  183. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  184. /*
  185. * Metadata - HTT MSDU Extension header
  186. */
  187. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  188. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  189. if (vdev->mesh_vdev) {
  190. /* Fill and add HTT metaheader */
  191. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  192. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  193. } else if (vdev->opmode == wlan_op_mode_ocb) {
  194. /* Todo - Add support for DSRC */
  195. }
  196. return htt_desc_size_aligned;
  197. }
  198. /**
  199. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  200. * @tso_seg: TSO segment to process
  201. * @ext_desc: Pointer to MSDU extension descriptor
  202. *
  203. * Return: void
  204. */
  205. #if defined(FEATURE_TSO)
  206. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  207. void *ext_desc)
  208. {
  209. uint8_t num_frag;
  210. uint32_t tso_flags;
  211. /*
  212. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  213. * tcp_flag_mask
  214. *
  215. * Checksum enable flags are set in TCL descriptor and not in Extension
  216. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  217. */
  218. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  219. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  220. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  221. tso_seg->tso_flags.ip_len);
  222. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  223. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  224. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  225. uint32_t lo = 0;
  226. uint32_t hi = 0;
  227. qdf_dmaaddr_to_32s(
  228. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  229. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  230. tso_seg->tso_frags[num_frag].length);
  231. }
  232. return;
  233. }
  234. #else
  235. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  236. void *ext_desc)
  237. {
  238. return;
  239. }
  240. #endif
  241. #if defined(FEATURE_TSO)
  242. /**
  243. * dp_tx_free_tso_seg() - Loop through the tso segments
  244. * allocated and free them
  245. *
  246. * @soc: soc handle
  247. * @free_seg: list of tso segments
  248. * @msdu_info: msdu descriptor
  249. *
  250. * Return - void
  251. */
  252. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  253. struct qdf_tso_seg_elem_t *free_seg,
  254. struct dp_tx_msdu_info_s *msdu_info)
  255. {
  256. struct qdf_tso_seg_elem_t *next_seg;
  257. while (free_seg) {
  258. next_seg = free_seg->next;
  259. dp_tx_tso_desc_free(soc,
  260. msdu_info->tx_queue.desc_pool_id,
  261. free_seg);
  262. free_seg = next_seg;
  263. }
  264. }
  265. /**
  266. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  267. * allocated and free them
  268. *
  269. * @soc: soc handle
  270. * @free_seg: list of tso segments
  271. * @msdu_info: msdu descriptor
  272. * Return - void
  273. */
  274. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  275. struct qdf_tso_num_seg_elem_t *free_seg,
  276. struct dp_tx_msdu_info_s *msdu_info)
  277. {
  278. struct qdf_tso_num_seg_elem_t *next_seg;
  279. while (free_seg) {
  280. next_seg = free_seg->next;
  281. dp_tso_num_seg_free(soc,
  282. msdu_info->tx_queue.desc_pool_id,
  283. free_seg);
  284. free_seg = next_seg;
  285. }
  286. }
  287. /**
  288. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  289. * @vdev: virtual device handle
  290. * @msdu: network buffer
  291. * @msdu_info: meta data associated with the msdu
  292. *
  293. * Return: QDF_STATUS_SUCCESS success
  294. */
  295. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  296. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  297. {
  298. struct qdf_tso_seg_elem_t *tso_seg;
  299. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  300. struct dp_soc *soc = vdev->pdev->soc;
  301. struct qdf_tso_info_t *tso_info;
  302. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  303. tso_info = &msdu_info->u.tso_info;
  304. tso_info->curr_seg = NULL;
  305. tso_info->tso_seg_list = NULL;
  306. tso_info->num_segs = num_seg;
  307. msdu_info->frm_type = dp_tx_frm_tso;
  308. tso_info->tso_num_seg_list = NULL;
  309. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  310. while (num_seg) {
  311. tso_seg = dp_tx_tso_desc_alloc(
  312. soc, msdu_info->tx_queue.desc_pool_id);
  313. if (tso_seg) {
  314. tso_seg->next = tso_info->tso_seg_list;
  315. tso_info->tso_seg_list = tso_seg;
  316. num_seg--;
  317. } else {
  318. struct qdf_tso_seg_elem_t *free_seg =
  319. tso_info->tso_seg_list;
  320. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  321. return QDF_STATUS_E_NOMEM;
  322. }
  323. }
  324. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  325. tso_num_seg = dp_tso_num_seg_alloc(soc,
  326. msdu_info->tx_queue.desc_pool_id);
  327. if (tso_num_seg) {
  328. tso_num_seg->next = tso_info->tso_num_seg_list;
  329. tso_info->tso_num_seg_list = tso_num_seg;
  330. } else {
  331. /* Bug: free tso_num_seg and tso_seg */
  332. /* Free the already allocated num of segments */
  333. struct qdf_tso_seg_elem_t *free_seg =
  334. tso_info->tso_seg_list;
  335. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  336. __func__);
  337. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  338. return QDF_STATUS_E_NOMEM;
  339. }
  340. msdu_info->num_seg =
  341. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  342. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  343. msdu_info->num_seg);
  344. if (!(msdu_info->num_seg)) {
  345. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  346. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  347. msdu_info);
  348. return QDF_STATUS_E_INVAL;
  349. }
  350. tso_info->curr_seg = tso_info->tso_seg_list;
  351. return QDF_STATUS_SUCCESS;
  352. }
  353. #else
  354. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  355. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  356. {
  357. return QDF_STATUS_E_NOMEM;
  358. }
  359. #endif
  360. /**
  361. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  362. * @vdev: DP Vdev handle
  363. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  364. * @desc_pool_id: Descriptor Pool ID
  365. *
  366. * Return:
  367. */
  368. static
  369. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  370. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  371. {
  372. uint8_t i;
  373. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  374. struct dp_tx_seg_info_s *seg_info;
  375. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  376. struct dp_soc *soc = vdev->pdev->soc;
  377. /* Allocate an extension descriptor */
  378. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  379. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  380. if (!msdu_ext_desc) {
  381. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  382. return NULL;
  383. }
  384. if (qdf_unlikely(vdev->mesh_vdev)) {
  385. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  386. &msdu_info->meta_data[0],
  387. sizeof(struct htt_tx_msdu_desc_ext2_t));
  388. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  389. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  390. }
  391. switch (msdu_info->frm_type) {
  392. case dp_tx_frm_sg:
  393. case dp_tx_frm_me:
  394. case dp_tx_frm_raw:
  395. seg_info = msdu_info->u.sg_info.curr_seg;
  396. /* Update the buffer pointers in MSDU Extension Descriptor */
  397. for (i = 0; i < seg_info->frag_cnt; i++) {
  398. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  399. seg_info->frags[i].paddr_lo,
  400. seg_info->frags[i].paddr_hi,
  401. seg_info->frags[i].len);
  402. }
  403. break;
  404. case dp_tx_frm_tso:
  405. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  406. &cached_ext_desc[0]);
  407. break;
  408. default:
  409. break;
  410. }
  411. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  412. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  413. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  414. msdu_ext_desc->vaddr);
  415. return msdu_ext_desc;
  416. }
  417. /**
  418. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  419. * @vdev: DP vdev handle
  420. * @nbuf: skb
  421. * @desc_pool_id: Descriptor pool ID
  422. * Allocate and prepare Tx descriptor with msdu information.
  423. *
  424. * Return: Pointer to Tx Descriptor on success,
  425. * NULL on failure
  426. */
  427. static
  428. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  429. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  430. uint32_t *meta_data)
  431. {
  432. QDF_STATUS status;
  433. uint8_t align_pad;
  434. uint8_t is_exception = 0;
  435. uint8_t htt_hdr_size;
  436. struct ether_header *eh;
  437. struct dp_tx_desc_s *tx_desc;
  438. struct dp_pdev *pdev = vdev->pdev;
  439. struct dp_soc *soc = pdev->soc;
  440. /* Flow control/Congestion Control processing */
  441. status = dp_tx_flow_control(vdev);
  442. if (QDF_STATUS_E_RESOURCES == status) {
  443. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  444. "%s Tx Resource Full\n", __func__);
  445. DP_STATS_INC(vdev, tx_i.dropped.res_full, 1);
  446. /* TODO Stop Tx Queues */
  447. }
  448. /* Allocate software Tx descriptor */
  449. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  450. if (qdf_unlikely(!tx_desc)) {
  451. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  452. "%s Tx Desc Alloc Failed\n", __func__);
  453. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  454. return NULL;
  455. }
  456. /* Flow control/Congestion Control counters */
  457. qdf_atomic_inc(&pdev->num_tx_outstanding);
  458. /* Initialize the SW tx descriptor */
  459. tx_desc->nbuf = nbuf;
  460. tx_desc->frm_type = dp_tx_frm_std;
  461. tx_desc->tx_encap_type = vdev->tx_encap_type;
  462. tx_desc->vdev = vdev;
  463. tx_desc->pdev = pdev;
  464. tx_desc->msdu_ext_desc = NULL;
  465. /**
  466. * For non-scatter regular frames, buffer pointer is directly
  467. * programmed in TCL input descriptor instead of using an MSDU
  468. * extension descriptor.For this cass, HW requirement is that
  469. * descriptor should always point to a 8-byte aligned address.
  470. *
  471. * So we add alignment pad to start of buffer, and specify the actual
  472. * start of data through pkt_offset
  473. */
  474. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  475. qdf_nbuf_push_head(nbuf, align_pad);
  476. tx_desc->pkt_offset = align_pad;
  477. /*
  478. * For special modes (vdev_type == ocb or mesh), data frames should be
  479. * transmitted using varying transmit parameters (tx spec) which include
  480. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  481. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  482. * These frames are sent as exception packets to firmware.
  483. *
  484. * HTT Metadata should be ensured to be multiple of 8-bytes,
  485. * to get 8-byte aligned start address along with align_pad added above
  486. *
  487. * |-----------------------------|
  488. * | |
  489. * |-----------------------------| <-----Buffer Pointer Address given
  490. * | | ^ in HW descriptor (aligned)
  491. * | HTT Metadata | |
  492. * | | |
  493. * | | | Packet Offset given in descriptor
  494. * | | |
  495. * |-----------------------------| |
  496. * | Alignment Pad | v
  497. * |-----------------------------| <----- Actual buffer start address
  498. * | SKB Data | (Unaligned)
  499. * | |
  500. * | |
  501. * | |
  502. * | |
  503. * | |
  504. * |-----------------------------|
  505. */
  506. if (qdf_unlikely(vdev->mesh_vdev ||
  507. (vdev->opmode == wlan_op_mode_ocb))) {
  508. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  509. meta_data);
  510. tx_desc->pkt_offset += htt_hdr_size;
  511. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  512. is_exception = 1;
  513. }
  514. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  515. qdf_nbuf_map(soc->osdev, nbuf,
  516. QDF_DMA_TO_DEVICE))) {
  517. /* Handle failure */
  518. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  519. "qdf_nbuf_map failed\n");
  520. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  521. goto failure;
  522. }
  523. if (qdf_unlikely(vdev->nawds_enabled)) {
  524. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  525. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  526. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  527. is_exception = 1;
  528. }
  529. }
  530. #if !TQM_BYPASS_WAR
  531. if (is_exception)
  532. #endif
  533. {
  534. /* Temporary WAR due to TQM VP issues */
  535. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  536. qdf_atomic_inc(&pdev->num_tx_exception);
  537. }
  538. return tx_desc;
  539. failure:
  540. dp_tx_desc_release(tx_desc, desc_pool_id);
  541. return NULL;
  542. }
  543. /**
  544. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  545. * @vdev: DP vdev handle
  546. * @nbuf: skb
  547. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  548. * @desc_pool_id : Descriptor Pool ID
  549. *
  550. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  551. * information. For frames wth fragments, allocate and prepare
  552. * an MSDU extension descriptor
  553. *
  554. * Return: Pointer to Tx Descriptor on success,
  555. * NULL on failure
  556. */
  557. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  558. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  559. uint8_t desc_pool_id)
  560. {
  561. struct dp_tx_desc_s *tx_desc;
  562. QDF_STATUS status;
  563. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  564. struct dp_pdev *pdev = vdev->pdev;
  565. struct dp_soc *soc = pdev->soc;
  566. /* Flow control/Congestion Control processing */
  567. status = dp_tx_flow_control(vdev);
  568. if (QDF_STATUS_E_RESOURCES == status) {
  569. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  570. "%s Tx Resource Full\n", __func__);
  571. DP_STATS_INC(vdev, tx_i.dropped.res_full, 1);
  572. /* TODO Stop Tx Queues */
  573. }
  574. /* Allocate software Tx descriptor */
  575. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  576. if (!tx_desc) {
  577. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  578. return NULL;
  579. }
  580. /* Flow control/Congestion Control counters */
  581. qdf_atomic_inc(&pdev->num_tx_outstanding);
  582. /* Initialize the SW tx descriptor */
  583. tx_desc->nbuf = nbuf;
  584. tx_desc->frm_type = msdu_info->frm_type;
  585. tx_desc->tx_encap_type = vdev->tx_encap_type;
  586. tx_desc->vdev = vdev;
  587. tx_desc->pdev = pdev;
  588. tx_desc->pkt_offset = 0;
  589. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  590. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  591. /* Handle scattered frames - TSO/SG/ME */
  592. /* Allocate and prepare an extension descriptor for scattered frames */
  593. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  594. if (!msdu_ext_desc) {
  595. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  596. "%s Tx Extension Descriptor Alloc Fail\n",
  597. __func__);
  598. goto failure;
  599. }
  600. #if TQM_BYPASS_WAR
  601. /* Temporary WAR due to TQM VP issues */
  602. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  603. qdf_atomic_inc(&pdev->num_tx_exception);
  604. #endif
  605. if (qdf_unlikely(vdev->mesh_vdev))
  606. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  607. tx_desc->msdu_ext_desc = msdu_ext_desc;
  608. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  609. return tx_desc;
  610. failure:
  611. if (qdf_unlikely(tx_desc->flags & DP_TX_DESC_FLAG_ME))
  612. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  613. dp_tx_desc_release(tx_desc, desc_pool_id);
  614. return NULL;
  615. }
  616. /**
  617. * dp_tx_prepare_raw() - Prepare RAW packet TX
  618. * @vdev: DP vdev handle
  619. * @nbuf: buffer pointer
  620. * @seg_info: Pointer to Segment info Descriptor to be prepared
  621. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  622. * descriptor
  623. *
  624. * Return:
  625. */
  626. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  627. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  628. {
  629. qdf_nbuf_t curr_nbuf = NULL;
  630. uint16_t total_len = 0;
  631. int32_t i;
  632. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  633. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  634. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  635. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  636. if ((qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  637. && (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU)) {
  638. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  639. }
  640. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  641. QDF_DMA_TO_DEVICE)) {
  642. qdf_print("dma map error\n");
  643. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  644. qdf_nbuf_free(nbuf);
  645. return NULL;
  646. }
  647. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  648. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  649. seg_info->frags[i].paddr_lo =
  650. qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  651. seg_info->frags[i].paddr_hi = 0x0;
  652. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  653. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  654. total_len += qdf_nbuf_len(curr_nbuf);
  655. }
  656. seg_info->frag_cnt = i;
  657. seg_info->total_len = total_len;
  658. seg_info->next = NULL;
  659. sg_info->curr_seg = seg_info;
  660. msdu_info->frm_type = dp_tx_frm_raw;
  661. msdu_info->num_seg = 1;
  662. return nbuf;
  663. }
  664. /**
  665. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  666. * @soc: DP Soc Handle
  667. * @vdev: DP vdev handle
  668. * @tx_desc: Tx Descriptor Handle
  669. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  670. * @fw_metadata: Metadata to send to Target Firmware along with frame
  671. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  672. *
  673. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  674. * from software Tx descriptor
  675. *
  676. * Return:
  677. */
  678. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  679. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  680. uint16_t fw_metadata, uint8_t ring_id)
  681. {
  682. uint8_t type;
  683. uint16_t length;
  684. void *hal_tx_desc, *hal_tx_desc_cached;
  685. qdf_dma_addr_t dma_addr;
  686. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  687. /* Return Buffer Manager ID */
  688. uint8_t bm_id = ring_id;
  689. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  690. hal_tx_desc_cached = (void *) cached_desc;
  691. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  692. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  693. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  694. type = HAL_TX_BUF_TYPE_EXT_DESC;
  695. dma_addr = tx_desc->msdu_ext_desc->paddr;
  696. } else {
  697. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  698. type = HAL_TX_BUF_TYPE_BUFFER;
  699. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  700. }
  701. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  702. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  703. dma_addr , bm_id, tx_desc->id, type);
  704. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  705. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  706. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  707. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  708. vdev->dscp_tid_map_id);
  709. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  710. "%s length:%d , type = %d, dma_addr %llx, offset %d\n",
  711. __func__, length, type, (uint64_t)dma_addr,
  712. tx_desc->pkt_offset);
  713. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  714. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  715. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  716. vdev->hal_desc_addr_search_flags);
  717. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  718. || qdf_nbuf_is_tso(tx_desc->nbuf)) {
  719. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  720. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  721. }
  722. if (tid != HTT_TX_EXT_TID_INVALID)
  723. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  724. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  725. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  726. /* Sync cached descriptor with HW */
  727. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  728. if (!hal_tx_desc) {
  729. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  730. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  731. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  732. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  733. hal_srng_access_end(soc->hal_soc,
  734. soc->tcl_data_ring[ring_id].hal_srng);
  735. return QDF_STATUS_E_RESOURCES;
  736. }
  737. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  738. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  739. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  740. return QDF_STATUS_SUCCESS;
  741. }
  742. /**
  743. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  744. * @vdev: DP vdev handle
  745. * @nbuf: skb
  746. *
  747. * Extract the DSCP or PCP information from frame and map into TID value.
  748. * Software based TID classification is required when more than 2 DSCP-TID
  749. * mapping tables are needed.
  750. * Hardware supports 2 DSCP-TID mapping tables
  751. *
  752. * Return: void
  753. */
  754. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  755. struct dp_tx_msdu_info_s *msdu_info)
  756. {
  757. uint8_t tos = 0, dscp_tid_override = 0;
  758. uint8_t *hdr_ptr, *L3datap;
  759. uint8_t is_mcast = 0;
  760. struct ether_header *eh = NULL;
  761. qdf_ethervlan_header_t *evh = NULL;
  762. uint16_t ether_type;
  763. qdf_llc_t *llcHdr;
  764. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  765. /* for mesh packets don't do any classification */
  766. if (qdf_unlikely(vdev->mesh_vdev))
  767. return;
  768. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  769. eh = (struct ether_header *) nbuf->data;
  770. hdr_ptr = eh->ether_dhost;
  771. L3datap = hdr_ptr + sizeof(struct ether_header);
  772. } else {
  773. qdf_dot3_qosframe_t *qos_wh =
  774. (qdf_dot3_qosframe_t *) nbuf->data;
  775. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  776. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  777. return;
  778. }
  779. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  780. ether_type = eh->ether_type;
  781. /*
  782. * Check if packet is dot3 or eth2 type.
  783. */
  784. if (IS_LLC_PRESENT(ether_type)) {
  785. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  786. sizeof(*llcHdr));
  787. if (ether_type == htons(ETHERTYPE_8021Q)) {
  788. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  789. sizeof(*llcHdr);
  790. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  791. + sizeof(*llcHdr) +
  792. sizeof(qdf_net_vlanhdr_t));
  793. } else {
  794. L3datap = hdr_ptr + sizeof(struct ether_header) +
  795. sizeof(*llcHdr);
  796. }
  797. } else {
  798. if (ether_type == htons(ETHERTYPE_8021Q)) {
  799. evh = (qdf_ethervlan_header_t *) eh;
  800. ether_type = evh->ether_type;
  801. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  802. }
  803. }
  804. /*
  805. * Find priority from IP TOS DSCP field
  806. */
  807. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  808. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  809. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  810. /* Only for unicast frames */
  811. if (!is_mcast) {
  812. /* send it on VO queue */
  813. msdu_info->tid = DP_VO_TID;
  814. }
  815. } else {
  816. /*
  817. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  818. * from TOS byte.
  819. */
  820. tos = ip->ip_tos;
  821. dscp_tid_override = 1;
  822. }
  823. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  824. /* TODO
  825. * use flowlabel
  826. *igmpmld cases to be handled in phase 2
  827. */
  828. unsigned long ver_pri_flowlabel;
  829. unsigned long pri;
  830. ver_pri_flowlabel = *(unsigned long *) L3datap;
  831. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  832. DP_IPV6_PRIORITY_SHIFT;
  833. tos = pri;
  834. dscp_tid_override = 1;
  835. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  836. msdu_info->tid = DP_VO_TID;
  837. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  838. /* Only for unicast frames */
  839. if (!is_mcast) {
  840. /* send ucast arp on VO queue */
  841. msdu_info->tid = DP_VO_TID;
  842. }
  843. }
  844. /*
  845. * Assign all MCAST packets to BE
  846. */
  847. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  848. if (is_mcast) {
  849. tos = 0;
  850. dscp_tid_override = 1;
  851. }
  852. }
  853. if (dscp_tid_override == 1) {
  854. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  855. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  856. }
  857. return;
  858. }
  859. /**
  860. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  861. * @vdev: DP vdev handle
  862. * @nbuf: skb
  863. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  864. * @tx_q: Tx queue to be used for this Tx frame
  865. * @peer_id: peer_id of the peer in case of NAWDS frames
  866. *
  867. * Return: NULL on success,
  868. * nbuf when it fails to send
  869. */
  870. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  871. uint8_t tid, struct dp_tx_queue *tx_q,
  872. uint32_t *meta_data, uint16_t peer_id)
  873. {
  874. struct dp_pdev *pdev = vdev->pdev;
  875. struct dp_soc *soc = pdev->soc;
  876. struct dp_tx_desc_s *tx_desc;
  877. QDF_STATUS status;
  878. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  879. uint16_t htt_tcl_metadata = 0;
  880. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 0);
  881. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  882. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id, meta_data);
  883. if (!tx_desc) {
  884. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  885. "%s Tx_desc prepare Fail vdev %p queue %d\n",
  886. __func__, vdev, tx_q->desc_pool_id);
  887. goto fail_return;
  888. }
  889. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  890. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  891. "%s %d : HAL RING Access Failed -- %p\n",
  892. __func__, __LINE__, hal_srng);
  893. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  894. goto fail_return;
  895. }
  896. if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  897. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  898. HTT_TCL_METADATA_TYPE_PEER_BASED);
  899. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  900. peer_id);
  901. } else
  902. htt_tcl_metadata = vdev->htt_tcl_metadata;
  903. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  904. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  905. htt_tcl_metadata, tx_q->ring_id);
  906. if (status != QDF_STATUS_SUCCESS) {
  907. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  908. "%s Tx_hw_enqueue Fail tx_desc %p queue %d\n",
  909. __func__, tx_desc, tx_q->ring_id);
  910. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  911. goto fail_return;
  912. }
  913. hal_srng_access_end(soc->hal_soc, hal_srng);
  914. return NULL;
  915. fail_return:
  916. return nbuf;
  917. }
  918. /**
  919. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  920. * @vdev: DP vdev handle
  921. * @nbuf: skb
  922. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  923. *
  924. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  925. *
  926. * Return: NULL on success,
  927. * nbuf when it fails to send
  928. */
  929. #if QDF_LOCK_STATS
  930. static noinline
  931. #else
  932. static
  933. #endif
  934. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  935. struct dp_tx_msdu_info_s *msdu_info)
  936. {
  937. uint8_t i;
  938. struct dp_pdev *pdev = vdev->pdev;
  939. struct dp_soc *soc = pdev->soc;
  940. struct dp_tx_desc_s *tx_desc;
  941. QDF_STATUS status;
  942. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  943. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  944. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  945. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  946. "%s %d : HAL RING Access Failed -- %p\n",
  947. __func__, __LINE__, hal_srng);
  948. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  949. return nbuf;
  950. }
  951. if (msdu_info->frm_type == dp_tx_frm_me)
  952. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  953. i = 0;
  954. /* Print statement to track i and num_seg */
  955. /*
  956. * For each segment (maps to 1 MSDU) , prepare software and hardware
  957. * descriptors using information in msdu_info
  958. */
  959. while (i < msdu_info->num_seg) {
  960. /*
  961. * Setup Tx descriptor for an MSDU, and MSDU extension
  962. * descriptor
  963. */
  964. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  965. tx_q->desc_pool_id);
  966. if (msdu_info->frm_type == dp_tx_frm_me) {
  967. tx_desc->me_buffer =
  968. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  969. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  970. }
  971. if (!tx_desc) {
  972. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  973. "%s Tx_desc prepare Fail vdev %p queue %d\n",
  974. __func__, vdev, tx_q->desc_pool_id);
  975. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  976. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  977. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  978. goto done;
  979. }
  980. /*
  981. * Enqueue the Tx MSDU descriptor to HW for transmit
  982. */
  983. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  984. vdev->htt_tcl_metadata, tx_q->ring_id);
  985. if (status != QDF_STATUS_SUCCESS) {
  986. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  987. "%s Tx_hw_enqueue Fail tx_desc %p queue %d\n",
  988. __func__, tx_desc, tx_q->ring_id);
  989. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  990. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  991. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  992. goto done;
  993. }
  994. /*
  995. * TODO
  996. * if tso_info structure can be modified to have curr_seg
  997. * as first element, following 2 blocks of code (for TSO and SG)
  998. * can be combined into 1
  999. */
  1000. /*
  1001. * For frames with multiple segments (TSO, ME), jump to next
  1002. * segment.
  1003. */
  1004. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1005. if (msdu_info->u.tso_info.curr_seg->next) {
  1006. msdu_info->u.tso_info.curr_seg =
  1007. msdu_info->u.tso_info.curr_seg->next;
  1008. /*
  1009. * If this is a jumbo nbuf, then increment the number of
  1010. * nbuf users for each additional segment of the msdu.
  1011. * This will ensure that the skb is freed only after
  1012. * receiving tx completion for all segments of an nbuf
  1013. */
  1014. qdf_nbuf_inc_users(nbuf);
  1015. /* Check with MCL if this is needed */
  1016. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1017. }
  1018. }
  1019. /*
  1020. * For Multicast-Unicast converted packets,
  1021. * each converted frame (for a client) is represented as
  1022. * 1 segment
  1023. */
  1024. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1025. (msdu_info->frm_type == dp_tx_frm_me)) {
  1026. if (msdu_info->u.sg_info.curr_seg->next) {
  1027. msdu_info->u.sg_info.curr_seg =
  1028. msdu_info->u.sg_info.curr_seg->next;
  1029. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1030. }
  1031. }
  1032. i++;
  1033. }
  1034. nbuf = NULL;
  1035. done:
  1036. hal_srng_access_end(soc->hal_soc, hal_srng);
  1037. return nbuf;
  1038. }
  1039. /**
  1040. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1041. * for SG frames
  1042. * @vdev: DP vdev handle
  1043. * @nbuf: skb
  1044. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1045. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1046. *
  1047. * Return: NULL on success,
  1048. * nbuf when it fails to send
  1049. */
  1050. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1051. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1052. {
  1053. uint32_t cur_frag, nr_frags;
  1054. qdf_dma_addr_t paddr;
  1055. struct dp_tx_sg_info_s *sg_info;
  1056. sg_info = &msdu_info->u.sg_info;
  1057. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1058. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1059. QDF_DMA_TO_DEVICE)) {
  1060. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1061. "dma map error\n");
  1062. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1063. qdf_nbuf_free(nbuf);
  1064. return NULL;
  1065. }
  1066. seg_info->frags[0].paddr_lo = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1067. seg_info->frags[0].paddr_hi = 0;
  1068. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1069. seg_info->frags[0].vaddr = (void *) nbuf;
  1070. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1071. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1072. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1073. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1074. "frag dma map error\n");
  1075. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1076. qdf_nbuf_free(nbuf);
  1077. return NULL;
  1078. }
  1079. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1080. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1081. seg_info->frags[cur_frag + 1].paddr_hi =
  1082. ((uint64_t) paddr) >> 32;
  1083. seg_info->frags[cur_frag + 1].len =
  1084. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1085. }
  1086. seg_info->frag_cnt = (cur_frag + 1);
  1087. seg_info->total_len = qdf_nbuf_len(nbuf);
  1088. seg_info->next = NULL;
  1089. sg_info->curr_seg = seg_info;
  1090. msdu_info->frm_type = dp_tx_frm_sg;
  1091. msdu_info->num_seg = 1;
  1092. return nbuf;
  1093. }
  1094. #ifdef MESH_MODE_SUPPORT
  1095. /**
  1096. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1097. and prepare msdu_info for mesh frames.
  1098. * @vdev: DP vdev handle
  1099. * @nbuf: skb
  1100. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1101. *
  1102. * Return: void
  1103. */
  1104. static
  1105. void dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1106. struct dp_tx_msdu_info_s *msdu_info)
  1107. {
  1108. struct meta_hdr_s *mhdr;
  1109. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1110. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1111. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1112. qdf_mem_set(meta_data, 0, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1113. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1114. meta_data->power = mhdr->power;
  1115. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1116. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1117. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1118. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1119. meta_data->dyn_bw = 1;
  1120. meta_data->valid_pwr = 1;
  1121. meta_data->valid_mcs_mask = 1;
  1122. meta_data->valid_nss_mask = 1;
  1123. meta_data->valid_preamble_type = 1;
  1124. meta_data->valid_retries = 1;
  1125. meta_data->valid_bw_info = 1;
  1126. }
  1127. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1128. meta_data->encrypt_type = 0;
  1129. meta_data->valid_encrypt_type = 1;
  1130. }
  1131. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1132. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1133. else
  1134. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1135. meta_data->valid_key_flags = 1;
  1136. meta_data->key_flags = (mhdr->keyix & 0x3);
  1137. qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s));
  1138. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1139. "%s , Meta hdr %0x %0x %0x %0x %0x\n",
  1140. __func__, msdu_info->meta_data[0],
  1141. msdu_info->meta_data[1],
  1142. msdu_info->meta_data[2],
  1143. msdu_info->meta_data[3],
  1144. msdu_info->meta_data[4]);
  1145. return;
  1146. }
  1147. #else
  1148. static
  1149. void dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1150. struct dp_tx_msdu_info_s *msdu_info)
  1151. {
  1152. }
  1153. #endif
  1154. /**
  1155. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1156. * @vdev: dp_vdev handle
  1157. * @nbuf: skb
  1158. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1159. * @tx_q: Tx queue to be used for this Tx frame
  1160. * @meta_data: Meta date for mesh
  1161. * @peer_id: peer_id of the peer in case of NAWDS frames
  1162. *
  1163. * return: NULL on success nbuf on failure
  1164. */
  1165. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1166. uint8_t tid, struct dp_tx_queue *tx_q, uint32_t *meta_data,
  1167. uint32_t peer_id)
  1168. {
  1169. struct dp_peer *peer = NULL;
  1170. qdf_nbuf_t nbuf_copy;
  1171. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1172. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1173. (peer->nawds_enabled || peer->bss_peer)) {
  1174. nbuf_copy = qdf_nbuf_copy(nbuf);
  1175. if (!nbuf_copy) {
  1176. QDF_TRACE(QDF_MODULE_ID_DP,
  1177. QDF_TRACE_LEVEL_ERROR,
  1178. "nbuf copy failed");
  1179. }
  1180. peer_id = peer->peer_ids[0];
  1181. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy, tid,
  1182. tx_q, meta_data, peer_id);
  1183. if (nbuf_copy != NULL) {
  1184. qdf_nbuf_free(nbuf);
  1185. return nbuf_copy;
  1186. }
  1187. }
  1188. }
  1189. if (peer_id == HTT_INVALID_PEER)
  1190. return nbuf;
  1191. qdf_nbuf_free(nbuf);
  1192. return NULL;
  1193. }
  1194. /**
  1195. * dp_tx_send() - Transmit a frame on a given VAP
  1196. * @vap_dev: DP vdev handle
  1197. * @nbuf: skb
  1198. *
  1199. * Entry point for Core Tx layer (DP_TX) invoked from
  1200. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1201. * cases
  1202. *
  1203. * Return: NULL on success,
  1204. * nbuf when it fails to send
  1205. */
  1206. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1207. {
  1208. struct ether_header *eh = NULL;
  1209. struct dp_tx_msdu_info_s msdu_info;
  1210. struct dp_tx_seg_info_s seg_info;
  1211. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1212. uint16_t peer_id = HTT_INVALID_PEER;
  1213. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1214. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1215. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1216. "%s , skb %0x:%0x:%0x:%0x:%0x:%0x\n",
  1217. __func__, nbuf->data[0], nbuf->data[1], nbuf->data[2],
  1218. nbuf->data[3], nbuf->data[4], nbuf->data[5]);
  1219. /*
  1220. * Set Default Host TID value to invalid TID
  1221. * (TID override disabled)
  1222. */
  1223. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1224. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1225. if (qdf_unlikely(vdev->mesh_vdev))
  1226. dp_tx_extract_mesh_meta_data(vdev, nbuf, &msdu_info);
  1227. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1228. "%s , skb %0x:%0x:%0x:%0x:%0x:%0x\n",
  1229. __func__, nbuf->data[0], nbuf->data[1], nbuf->data[2],
  1230. nbuf->data[3], nbuf->data[4], nbuf->data[5]);
  1231. /*
  1232. * Get HW Queue to use for this frame.
  1233. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1234. * dedicated for data and 1 for command.
  1235. * "queue_id" maps to one hardware ring.
  1236. * With each ring, we also associate a unique Tx descriptor pool
  1237. * to minimize lock contention for these resources.
  1238. */
  1239. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1240. /*
  1241. * TCL H/W supports 2 DSCP-TID mapping tables.
  1242. * Table 1 - Default DSCP-TID mapping table
  1243. * Table 2 - 1 DSCP-TID override table
  1244. *
  1245. * If we need a different DSCP-TID mapping for this vap,
  1246. * call tid_classify to extract DSCP/ToS from frame and
  1247. * map to a TID and store in msdu_info. This is later used
  1248. * to fill in TCL Input descriptor (per-packet TID override).
  1249. */
  1250. if (vdev->dscp_tid_map_id > 1)
  1251. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1252. /* Reset the control block */
  1253. qdf_nbuf_reset_ctxt(nbuf);
  1254. /*
  1255. * Classify the frame and call corresponding
  1256. * "prepare" function which extracts the segment (TSO)
  1257. * and fragmentation information (for TSO , SG, ME, or Raw)
  1258. * into MSDU_INFO structure which is later used to fill
  1259. * SW and HW descriptors.
  1260. */
  1261. if (qdf_nbuf_is_tso(nbuf)) {
  1262. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1263. "%s TSO frame %p\n", __func__, vdev);
  1264. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1265. qdf_nbuf_len(nbuf));
  1266. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1267. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1268. "%s tso_prepare fail vdev_id:%d\n",
  1269. __func__, vdev->vdev_id);
  1270. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1271. return nbuf;
  1272. }
  1273. goto send_multiple;
  1274. }
  1275. /* SG */
  1276. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1277. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1278. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1279. "%s non-TSO SG frame %p\n", __func__, vdev);
  1280. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1281. qdf_nbuf_len(nbuf));
  1282. goto send_multiple;
  1283. }
  1284. #ifdef ATH_SUPPORT_IQUE
  1285. /* Mcast to Ucast Conversion*/
  1286. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1287. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1288. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1289. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1290. "%s Mcast frm for ME %p\n", __func__, vdev);
  1291. DP_STATS_INC_PKT(vdev,
  1292. tx_i.mcast_en.mcast_pkt, 1,
  1293. qdf_nbuf_len(nbuf));
  1294. if (dp_tx_prepare_send_me(vdev, nbuf)) {
  1295. qdf_nbuf_free(nbuf);
  1296. return NULL;
  1297. }
  1298. return nbuf;
  1299. }
  1300. }
  1301. #endif
  1302. /* RAW */
  1303. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1304. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1305. if (nbuf == NULL)
  1306. return NULL;
  1307. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1308. "%s Raw frame %p\n", __func__, vdev);
  1309. goto send_multiple;
  1310. }
  1311. if (vdev->nawds_enabled) {
  1312. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1313. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1314. nbuf = dp_tx_prepare_nawds(vdev, nbuf, msdu_info.tid,
  1315. &msdu_info.tx_queue,
  1316. msdu_info.meta_data, peer_id);
  1317. return nbuf;
  1318. }
  1319. }
  1320. /* Single linear frame */
  1321. /*
  1322. * If nbuf is a simple linear frame, use send_single function to
  1323. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1324. * SRNG. There is no need to setup a MSDU extension descriptor.
  1325. */
  1326. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info.tid,
  1327. &msdu_info.tx_queue, msdu_info.meta_data, peer_id);
  1328. return nbuf;
  1329. send_multiple:
  1330. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1331. return nbuf;
  1332. }
  1333. /**
  1334. * dp_tx_reinject_handler() - Tx Reinject Handler
  1335. * @tx_desc: software descriptor head pointer
  1336. * @status : Tx completion status from HTT descriptor
  1337. *
  1338. * This function reinjects frames back to Target.
  1339. * Todo - Host queue needs to be added
  1340. *
  1341. * Return: none
  1342. */
  1343. static
  1344. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1345. {
  1346. struct dp_vdev *vdev;
  1347. struct dp_peer *peer = NULL;
  1348. uint32_t peer_id = HTT_INVALID_PEER;
  1349. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1350. qdf_nbuf_t nbuf_copy = NULL;
  1351. struct dp_tx_msdu_info_s msdu_info;
  1352. vdev = tx_desc->vdev;
  1353. qdf_assert(vdev);
  1354. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1355. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1356. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1357. "%s Tx reinject path\n", __func__);
  1358. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1359. qdf_nbuf_len(tx_desc->nbuf));
  1360. if (!vdev->osif_proxy_arp) {
  1361. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1362. "function pointer to proxy arp not present\n");
  1363. return;
  1364. }
  1365. if (qdf_unlikely(vdev->mesh_vdev)) {
  1366. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1367. } else {
  1368. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1369. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1370. (peer->bss_peer || peer->nawds_enabled)
  1371. && !(vdev->osif_proxy_arp(
  1372. vdev->osif_vdev,
  1373. nbuf))) {
  1374. nbuf_copy = qdf_nbuf_copy(nbuf);
  1375. if (!nbuf_copy) {
  1376. QDF_TRACE(QDF_MODULE_ID_DP,
  1377. QDF_TRACE_LEVEL_ERROR,
  1378. FL("nbuf copy failed"));
  1379. break;
  1380. }
  1381. if (peer->nawds_enabled)
  1382. peer_id = peer->peer_ids[0];
  1383. else
  1384. peer_id = HTT_INVALID_PEER;
  1385. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1386. nbuf_copy, msdu_info.tid,
  1387. &msdu_info.tx_queue,
  1388. msdu_info.meta_data, peer_id);
  1389. if (nbuf_copy) {
  1390. QDF_TRACE(QDF_MODULE_ID_DP,
  1391. QDF_TRACE_LEVEL_ERROR,
  1392. FL("pkt send failed"));
  1393. qdf_nbuf_free(nbuf_copy);
  1394. }
  1395. }
  1396. }
  1397. }
  1398. qdf_nbuf_free(nbuf);
  1399. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1400. }
  1401. /**
  1402. * dp_tx_inspect_handler() - Tx Inspect Handler
  1403. * @tx_desc: software descriptor head pointer
  1404. * @status : Tx completion status from HTT descriptor
  1405. *
  1406. * Handles Tx frames sent back to Host for inspection
  1407. * (ProxyARP)
  1408. *
  1409. * Return: none
  1410. */
  1411. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1412. {
  1413. struct dp_soc *soc;
  1414. struct dp_pdev *pdev = tx_desc->pdev;
  1415. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1416. "%s Tx inspect path\n",
  1417. __func__);
  1418. qdf_assert(pdev);
  1419. soc = pdev->soc;
  1420. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1421. qdf_nbuf_len(tx_desc->nbuf));
  1422. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1423. }
  1424. /**
  1425. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  1426. * @tx_desc: software descriptor head pointer
  1427. * @status : Tx completion status from HTT descriptor
  1428. *
  1429. * This function will process HTT Tx indication messages from Target
  1430. *
  1431. * Return: none
  1432. */
  1433. static
  1434. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1435. {
  1436. uint8_t tx_status;
  1437. struct dp_pdev *pdev;
  1438. struct dp_soc *soc;
  1439. uint32_t *htt_status_word = (uint32_t *) status;
  1440. qdf_assert(tx_desc->pdev);
  1441. pdev = tx_desc->pdev;
  1442. soc = pdev->soc;
  1443. tx_status = HTT_TX_WBM_COMPLETION_TX_STATUS_GET(htt_status_word[0]);
  1444. switch (tx_status) {
  1445. case HTT_TX_FW2WBM_TX_STATUS_OK:
  1446. {
  1447. qdf_atomic_dec(&pdev->num_tx_exception);
  1448. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1449. break;
  1450. }
  1451. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  1452. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  1453. {
  1454. qdf_atomic_dec(&pdev->num_tx_exception);
  1455. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1456. break;
  1457. }
  1458. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  1459. {
  1460. dp_tx_reinject_handler(tx_desc, status);
  1461. break;
  1462. }
  1463. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  1464. {
  1465. dp_tx_inspect_handler(tx_desc, status);
  1466. break;
  1467. }
  1468. default:
  1469. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1470. "%s Invalid HTT tx_status %d\n",
  1471. __func__, tx_status);
  1472. break;
  1473. }
  1474. }
  1475. #ifdef MESH_MODE_SUPPORT
  1476. /**
  1477. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  1478. * in mesh meta header
  1479. * @tx_desc: software descriptor head pointer
  1480. * @ts: pointer to tx completion stats
  1481. * Return: none
  1482. */
  1483. static
  1484. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1485. struct hal_tx_completion_status *ts)
  1486. {
  1487. struct meta_hdr_s *mhdr;
  1488. qdf_nbuf_t netbuf = tx_desc->nbuf;
  1489. if (!tx_desc->msdu_ext_desc) {
  1490. qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset);
  1491. }
  1492. qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s));
  1493. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  1494. mhdr->rssi = ts->ack_frame_rssi;
  1495. }
  1496. #else
  1497. static
  1498. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1499. struct hal_tx_completion_status *ts)
  1500. {
  1501. }
  1502. #endif
  1503. /**
  1504. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  1505. * @tx_desc: software descriptor head pointer
  1506. * @length: packet length
  1507. *
  1508. * Return: none
  1509. */
  1510. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  1511. uint32_t length)
  1512. {
  1513. struct hal_tx_completion_status ts;
  1514. struct dp_soc *soc = NULL;
  1515. struct dp_vdev *vdev = tx_desc->vdev;
  1516. struct dp_peer *peer = NULL;
  1517. uint8_t comp_status = 0;
  1518. qdf_mem_zero(&ts, sizeof(struct hal_tx_completion_status));
  1519. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1520. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1521. "-------------------- \n"
  1522. "Tx Completion Stats: \n"
  1523. "-------------------- \n"
  1524. "ack_frame_rssi = %d \n"
  1525. "first_msdu = %d \n"
  1526. "last_msdu = %d \n"
  1527. "msdu_part_of_amsdu = %d \n"
  1528. "rate_stats valid = %d \n"
  1529. "bw = %d \n"
  1530. "pkt_type = %d \n"
  1531. "stbc = %d \n"
  1532. "ldpc = %d \n"
  1533. "sgi = %d \n"
  1534. "mcs = %d \n"
  1535. "ofdma = %d \n"
  1536. "tones_in_ru = %d \n"
  1537. "tsf = %d \n"
  1538. "ppdu_id = %d \n"
  1539. "transmit_cnt = %d \n"
  1540. "tid = %d \n"
  1541. "peer_id = %d \n",
  1542. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  1543. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  1544. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  1545. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  1546. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  1547. ts.peer_id);
  1548. if (qdf_unlikely(tx_desc->vdev->mesh_vdev))
  1549. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  1550. if (!vdev) {
  1551. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1552. "invalid peer");
  1553. goto fail;
  1554. }
  1555. soc = tx_desc->vdev->pdev->soc;
  1556. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1557. if (!peer) {
  1558. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1559. "invalid peer");
  1560. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  1561. goto out;
  1562. }
  1563. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  1564. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  1565. hal_tx_comp_get_buffer_source(&tx_desc->comp)) {
  1566. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  1567. DP_STATS_INCC(peer, tx.dropped.mpdu_age_out, 1,
  1568. (comp_status == HAL_TX_TQM_RR_REM_CMD_AGED));
  1569. DP_STATS_INCC(peer, tx.dropped.fw_discard_reason1, 1,
  1570. (comp_status == HAL_TX_TQM_RR_FW_REASON1));
  1571. DP_STATS_INCC(peer, tx.dropped.fw_discard_reason2, 1,
  1572. (comp_status == HAL_TX_TQM_RR_FW_REASON2));
  1573. DP_STATS_INCC(peer, tx.dropped.fw_discard_reason3, 1,
  1574. (comp_status == HAL_TX_TQM_RR_FW_REASON3));
  1575. DP_STATS_INCC(peer, tx.tx_failed, 1,
  1576. comp_status != HAL_TX_TQM_RR_FRAME_ACKED);
  1577. if (comp_status == HAL_TX_TQM_RR_FRAME_ACKED) {
  1578. DP_STATS_INCC(peer, tx.pkt_type[ts.pkt_type].
  1579. mcs_count[MAX_MCS], 1,
  1580. ((ts.mcs >= MAX_MCS_11A) && (ts.pkt_type
  1581. == DOT11_A)));
  1582. DP_STATS_INCC(peer, tx.pkt_type[ts.pkt_type].
  1583. mcs_count[ts.mcs], 1,
  1584. ((ts.mcs <= MAX_MCS_11A) && (ts.pkt_type
  1585. == DOT11_A)));
  1586. DP_STATS_INCC(peer, tx.pkt_type[ts.pkt_type].
  1587. mcs_count[MAX_MCS], 1,
  1588. ((ts.mcs >= MAX_MCS_11B)
  1589. && (ts.pkt_type == DOT11_B)));
  1590. DP_STATS_INCC(peer, tx.pkt_type[ts.pkt_type].
  1591. mcs_count[ts.mcs], 1,
  1592. ((ts.mcs <= MAX_MCS_11B)
  1593. && (ts.pkt_type == DOT11_B)));
  1594. DP_STATS_INCC(peer, tx.pkt_type[ts.pkt_type].
  1595. mcs_count[MAX_MCS], 1,
  1596. ((ts.mcs >= MAX_MCS_11A)
  1597. && (ts.pkt_type == DOT11_N)));
  1598. DP_STATS_INCC(peer, tx.pkt_type[ts.pkt_type].
  1599. mcs_count[ts.mcs], 1,
  1600. ((ts.mcs <= MAX_MCS_11A)
  1601. && (ts.pkt_type == DOT11_N)));
  1602. DP_STATS_INCC(peer, tx.pkt_type[ts.pkt_type].
  1603. mcs_count[MAX_MCS], 1,
  1604. ((ts.mcs >= MAX_MCS_11AC)
  1605. && (ts.pkt_type == DOT11_AC)));
  1606. DP_STATS_INCC(peer, tx.pkt_type[ts.pkt_type].
  1607. mcs_count[ts.mcs], 1,
  1608. ((ts.mcs <= MAX_MCS_11AC)
  1609. && (ts.pkt_type == DOT11_AC)));
  1610. DP_STATS_INCC(peer, tx.pkt_type[ts.pkt_type].
  1611. mcs_count[MAX_MCS], 1,
  1612. ((ts.mcs >= MAX_MCS)
  1613. && (ts.pkt_type == DOT11_AX)));
  1614. DP_STATS_INCC(peer, tx.pkt_type[ts.pkt_type].
  1615. mcs_count[ts.mcs], 1,
  1616. ((ts.mcs <= MAX_MCS)
  1617. && (ts.pkt_type == DOT11_AX)));
  1618. DP_STATS_INC(peer, tx.sgi_count[ts.sgi], 1);
  1619. DP_STATS_INC(peer, tx.bw[ts.bw], 1);
  1620. DP_STATS_UPD(peer, tx.last_ack_rssi, ts.ack_frame_rssi);
  1621. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts.tid)]
  1622. , 1);
  1623. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  1624. DP_STATS_INCC(peer, tx.stbc, 1, ts.stbc);
  1625. DP_STATS_INCC(peer, tx.ofdma, 1, ts.ofdma);
  1626. DP_STATS_INCC(peer, tx.ldpc, 1, ts.ldpc);
  1627. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1,
  1628. (ts.first_msdu && ts.last_msdu));
  1629. DP_STATS_INCC(peer, tx.amsdu_cnt, 1,
  1630. !(ts.first_msdu && ts.last_msdu));
  1631. DP_STATS_INCC(peer, tx.retries, 1, ts.transmit_cnt > 1);
  1632. }
  1633. }
  1634. /* TODO: This call is temporary.
  1635. * Stats update has to be attached to the HTT PPDU message
  1636. */
  1637. if (soc->cdp_soc.ol_ops->update_dp_stats)
  1638. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  1639. &peer->stats, ts.peer_id, UPDATE_PEER_STATS);
  1640. out:
  1641. dp_aggregate_vdev_stats(tx_desc->vdev);
  1642. if (soc->cdp_soc.ol_ops->update_dp_stats)
  1643. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  1644. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  1645. fail:
  1646. return;
  1647. }
  1648. /**
  1649. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  1650. * @soc: core txrx main context
  1651. * @comp_head: software descriptor head pointer
  1652. *
  1653. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  1654. * and release the software descriptors after processing is complete
  1655. *
  1656. * Return: none
  1657. */
  1658. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  1659. struct dp_tx_desc_s *comp_head)
  1660. {
  1661. struct dp_tx_desc_s *desc;
  1662. struct dp_tx_desc_s *next;
  1663. struct hal_tx_completion_status ts = {0};
  1664. uint32_t length;
  1665. struct dp_peer *peer;
  1666. DP_HIST_INIT();
  1667. desc = comp_head;
  1668. while (desc) {
  1669. hal_tx_comp_get_status(&desc->comp, &ts);
  1670. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1671. length = qdf_nbuf_len(desc->nbuf);
  1672. /* Error Handling */
  1673. if (hal_tx_comp_get_buffer_source(&desc->comp) ==
  1674. HAL_TX_COMP_RELEASE_SOURCE_FW) {
  1675. dp_tx_comp_process_exception(desc);
  1676. desc = desc->next;
  1677. continue;
  1678. }
  1679. /* Process Tx status in descriptor */
  1680. if (soc->process_tx_status ||
  1681. (desc->vdev && desc->vdev->mesh_vdev))
  1682. dp_tx_comp_process_tx_status(desc, length);
  1683. /* 0 : MSDU buffer, 1 : MLE */
  1684. if (desc->msdu_ext_desc) {
  1685. /* TSO free */
  1686. if (hal_tx_ext_desc_get_tso_enable(
  1687. desc->msdu_ext_desc->vaddr)) {
  1688. /* If remaining number of segment is 0
  1689. * actual TSO may unmap and free */
  1690. if (!DP_DESC_NUM_FRAG(desc)) {
  1691. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  1692. QDF_DMA_TO_DEVICE);
  1693. qdf_nbuf_free(desc->nbuf);
  1694. }
  1695. } else {
  1696. /* SG free */
  1697. /* Free buffer */
  1698. DP_TX_FREE_DMA_TO_DEVICE(soc, desc->vdev,
  1699. desc->nbuf);
  1700. }
  1701. } else {
  1702. /* Free buffer */
  1703. DP_TX_FREE_DMA_TO_DEVICE(soc, desc->vdev, desc->nbuf);
  1704. }
  1705. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  1706. next = desc->next;
  1707. if (desc->flags & DP_TX_DESC_FLAG_ME)
  1708. dp_tx_me_free_buf(desc->pdev, desc->me_buffer);
  1709. dp_tx_desc_release(desc, desc->pool_id);
  1710. desc = next;
  1711. }
  1712. DP_TX_HIST_STATS_PER_PDEV();
  1713. }
  1714. /**
  1715. * dp_tx_comp_handler() - Tx completion handler
  1716. * @soc: core txrx main context
  1717. * @ring_id: completion ring id
  1718. * @budget: No. of packets/descriptors that can be serviced in one loop
  1719. *
  1720. * This function will collect hardware release ring element contents and
  1721. * handle descriptor contents. Based on contents, free packet or handle error
  1722. * conditions
  1723. *
  1724. * Return: none
  1725. */
  1726. uint32_t dp_tx_comp_handler(struct dp_soc *soc, uint32_t ring_id,
  1727. uint32_t budget)
  1728. {
  1729. void *tx_comp_hal_desc;
  1730. uint8_t buffer_src;
  1731. uint8_t pool_id;
  1732. uint32_t tx_desc_id;
  1733. struct dp_tx_desc_s *tx_desc = NULL;
  1734. struct dp_tx_desc_s *head_desc = NULL;
  1735. struct dp_tx_desc_s *tail_desc = NULL;
  1736. uint32_t num_processed;
  1737. void *hal_srng = soc->tx_comp_ring[ring_id].hal_srng;
  1738. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1739. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1740. "%s %d : HAL RING Access Failed -- %p\n",
  1741. __func__, __LINE__, hal_srng);
  1742. return 0;
  1743. }
  1744. num_processed = 0;
  1745. /* Find head descriptor from completion ring */
  1746. while (qdf_likely(tx_comp_hal_desc =
  1747. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  1748. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  1749. /* If this buffer was not released by TQM or FW, then it is not
  1750. * Tx completion indication, skip to next descriptor */
  1751. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  1752. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1753. QDF_TRACE(QDF_MODULE_ID_DP,
  1754. QDF_TRACE_LEVEL_ERROR,
  1755. "Tx comp release_src != TQM | FW");
  1756. /* TODO Handle Freeing of the buffer in descriptor */
  1757. continue;
  1758. }
  1759. /* Get descriptor id */
  1760. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  1761. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  1762. DP_TX_DESC_ID_POOL_OS;
  1763. /* Pool ID is out of limit. Error */
  1764. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  1765. soc->wlan_cfg_ctx)) {
  1766. QDF_TRACE(QDF_MODULE_ID_DP,
  1767. QDF_TRACE_LEVEL_FATAL,
  1768. "TX COMP pool id %d not valid",
  1769. pool_id);
  1770. /* Check if assert aborts execution, if not handle
  1771. * return here */
  1772. QDF_ASSERT(0);
  1773. }
  1774. /* Find Tx descriptor */
  1775. tx_desc = dp_tx_desc_find(soc, pool_id,
  1776. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  1777. DP_TX_DESC_ID_PAGE_OS,
  1778. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  1779. DP_TX_DESC_ID_OFFSET_OS);
  1780. /* Pool id is not matching. Error */
  1781. if (tx_desc && (tx_desc->pool_id != pool_id)) {
  1782. QDF_TRACE(QDF_MODULE_ID_DP,
  1783. QDF_TRACE_LEVEL_FATAL,
  1784. "Tx Comp pool id %d not matched %d",
  1785. pool_id, tx_desc->pool_id);
  1786. /* Check if assert aborts execution, if not handle
  1787. * return here */
  1788. QDF_ASSERT(0);
  1789. }
  1790. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  1791. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  1792. QDF_TRACE(QDF_MODULE_ID_DP,
  1793. QDF_TRACE_LEVEL_FATAL,
  1794. "Txdesc invalid, flgs = %x,id = %d",
  1795. tx_desc->flags, tx_desc_id);
  1796. /* TODO Handle Freeing of the buffer in this invalid
  1797. * descriptor */
  1798. continue;
  1799. }
  1800. /*
  1801. * If the release source is FW, process the HTT
  1802. * status
  1803. */
  1804. if (qdf_unlikely(buffer_src ==
  1805. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1806. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1807. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  1808. htt_tx_status);
  1809. dp_tx_process_htt_completion(tx_desc,
  1810. htt_tx_status);
  1811. } else {
  1812. tx_desc->next = NULL;
  1813. /* First ring descriptor on the cycle */
  1814. if (!head_desc) {
  1815. head_desc = tx_desc;
  1816. } else {
  1817. tail_desc->next = tx_desc;
  1818. }
  1819. tail_desc = tx_desc;
  1820. /* Collect hw completion contents */
  1821. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1822. &tx_desc->comp, soc->process_tx_status);
  1823. }
  1824. num_processed++;
  1825. /*
  1826. * Processed packet count is more than given quota
  1827. * stop to processing
  1828. */
  1829. if (num_processed >= budget)
  1830. break;
  1831. }
  1832. hal_srng_access_end(soc->hal_soc, hal_srng);
  1833. /* Process the reaped descriptors */
  1834. if (head_desc)
  1835. dp_tx_comp_process_desc(soc, head_desc);
  1836. return num_processed;
  1837. }
  1838. /**
  1839. * dp_tx_vdev_attach() - attach vdev to dp tx
  1840. * @vdev: virtual device instance
  1841. *
  1842. * Return: QDF_STATUS_SUCCESS: success
  1843. * QDF_STATUS_E_RESOURCES: Error return
  1844. */
  1845. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  1846. {
  1847. /*
  1848. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  1849. */
  1850. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  1851. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  1852. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  1853. vdev->vdev_id);
  1854. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  1855. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  1856. /*
  1857. * Set HTT Extension Valid bit to 0 by default
  1858. */
  1859. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  1860. dp_tx_vdev_update_search_flags(vdev);
  1861. return QDF_STATUS_SUCCESS;
  1862. }
  1863. /**
  1864. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  1865. * @vdev: virtual device instance
  1866. *
  1867. * Return: void
  1868. *
  1869. */
  1870. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  1871. {
  1872. /*
  1873. * Enable both AddrY (SA based search) and AddrX (Da based search)
  1874. * for TDLS link
  1875. *
  1876. * Enable AddrY (SA based search) only for non-WDS STA and
  1877. * ProxySTA VAP modes.
  1878. *
  1879. * In all other VAP modes, only DA based search should be
  1880. * enabled
  1881. */
  1882. if (vdev->opmode == wlan_op_mode_sta &&
  1883. vdev->tdls_link_connected)
  1884. vdev->hal_desc_addr_search_flags =
  1885. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  1886. else if ((vdev->opmode == wlan_op_mode_sta &&
  1887. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  1888. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  1889. else
  1890. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  1891. }
  1892. /**
  1893. * dp_tx_vdev_detach() - detach vdev from dp tx
  1894. * @vdev: virtual device instance
  1895. *
  1896. * Return: QDF_STATUS_SUCCESS: success
  1897. * QDF_STATUS_E_RESOURCES: Error return
  1898. */
  1899. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  1900. {
  1901. return QDF_STATUS_SUCCESS;
  1902. }
  1903. /**
  1904. * dp_tx_pdev_attach() - attach pdev to dp tx
  1905. * @pdev: physical device instance
  1906. *
  1907. * Return: QDF_STATUS_SUCCESS: success
  1908. * QDF_STATUS_E_RESOURCES: Error return
  1909. */
  1910. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  1911. {
  1912. struct dp_soc *soc = pdev->soc;
  1913. /* Initialize Flow control counters */
  1914. qdf_atomic_init(&pdev->num_tx_exception);
  1915. qdf_atomic_init(&pdev->num_tx_outstanding);
  1916. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1917. /* Initialize descriptors in TCL Ring */
  1918. hal_tx_init_data_ring(soc->hal_soc,
  1919. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  1920. }
  1921. return QDF_STATUS_SUCCESS;
  1922. }
  1923. /**
  1924. * dp_tx_pdev_detach() - detach pdev from dp tx
  1925. * @pdev: physical device instance
  1926. *
  1927. * Return: QDF_STATUS_SUCCESS: success
  1928. * QDF_STATUS_E_RESOURCES: Error return
  1929. */
  1930. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  1931. {
  1932. /* What should do here? */
  1933. return QDF_STATUS_SUCCESS;
  1934. }
  1935. /**
  1936. * dp_tx_soc_detach() - detach soc from dp tx
  1937. * @soc: core txrx main context
  1938. *
  1939. * This function will detach dp tx into main device context
  1940. * will free dp tx resource and initialize resources
  1941. *
  1942. * Return: QDF_STATUS_SUCCESS: success
  1943. * QDF_STATUS_E_RESOURCES: Error return
  1944. */
  1945. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  1946. {
  1947. uint8_t num_pool;
  1948. uint16_t num_desc;
  1949. uint16_t num_ext_desc;
  1950. uint8_t i;
  1951. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  1952. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  1953. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  1954. for (i = 0; i < num_pool; i++) {
  1955. if (dp_tx_desc_pool_free(soc, i)) {
  1956. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1957. "%s Tx Desc Pool Free failed\n",
  1958. __func__);
  1959. return QDF_STATUS_E_RESOURCES;
  1960. }
  1961. }
  1962. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1963. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  1964. __func__, num_pool, num_desc);
  1965. for (i = 0; i < num_pool; i++) {
  1966. if (dp_tx_ext_desc_pool_free(soc, i)) {
  1967. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1968. "%s Tx Ext Desc Pool Free failed\n",
  1969. __func__);
  1970. return QDF_STATUS_E_RESOURCES;
  1971. }
  1972. }
  1973. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1974. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  1975. __func__, num_pool, num_ext_desc);
  1976. for (i = 0; i < num_pool; i++) {
  1977. dp_tx_tso_desc_pool_free(soc, i);
  1978. }
  1979. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1980. "%s TSO Desc Pool %d Free descs = %d\n",
  1981. __func__, num_pool, num_desc);
  1982. for (i = 0; i < num_pool; i++)
  1983. dp_tx_tso_num_seg_pool_free(soc, i);
  1984. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1985. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  1986. __func__, num_pool, num_desc);
  1987. return QDF_STATUS_SUCCESS;
  1988. }
  1989. /**
  1990. * dp_tx_soc_attach() - attach soc to dp tx
  1991. * @soc: core txrx main context
  1992. *
  1993. * This function will attach dp tx into main device context
  1994. * will allocate dp tx resource and initialize resources
  1995. *
  1996. * Return: QDF_STATUS_SUCCESS: success
  1997. * QDF_STATUS_E_RESOURCES: Error return
  1998. */
  1999. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2000. {
  2001. uint8_t num_pool;
  2002. uint32_t num_desc;
  2003. uint32_t num_ext_desc;
  2004. uint8_t i;
  2005. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2006. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2007. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2008. /* Allocate software Tx descriptor pools */
  2009. for (i = 0; i < num_pool; i++) {
  2010. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2011. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2012. "%s Tx Desc Pool alloc %d failed %p\n",
  2013. __func__, i, soc);
  2014. goto fail;
  2015. }
  2016. }
  2017. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2018. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2019. __func__, num_pool, num_desc);
  2020. /* Allocate extension tx descriptor pools */
  2021. for (i = 0; i < num_pool; i++) {
  2022. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2023. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2024. "MSDU Ext Desc Pool alloc %d failed %p\n",
  2025. i, soc);
  2026. goto fail;
  2027. }
  2028. }
  2029. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2030. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2031. __func__, num_pool, num_ext_desc);
  2032. for (i = 0; i < num_pool; i++) {
  2033. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2034. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2035. "TSO Desc Pool alloc %d failed %p\n",
  2036. i, soc);
  2037. goto fail;
  2038. }
  2039. }
  2040. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2041. "%s TSO Desc Alloc %d, descs = %d\n",
  2042. __func__, num_pool, num_desc);
  2043. for (i = 0; i < num_pool; i++) {
  2044. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2045. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2046. "TSO Num of seg Pool alloc %d failed %p\n",
  2047. i, soc);
  2048. goto fail;
  2049. }
  2050. }
  2051. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2052. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2053. __func__, num_pool, num_desc);
  2054. /* Initialize descriptors in TCL Rings */
  2055. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2056. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2057. hal_tx_init_data_ring(soc->hal_soc,
  2058. soc->tcl_data_ring[i].hal_srng);
  2059. }
  2060. }
  2061. /*
  2062. * todo - Add a runtime config option to enable this.
  2063. */
  2064. /*
  2065. * Due to multiple issues on NPR EMU, enable it selectively
  2066. * only for NPR EMU, should be removed, once NPR platforms
  2067. * are stable.
  2068. */
  2069. soc->process_tx_status = 1;
  2070. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2071. "%s HAL Tx init Success\n", __func__);
  2072. return QDF_STATUS_SUCCESS;
  2073. fail:
  2074. /* Detach will take care of freeing only allocated resources */
  2075. dp_tx_soc_detach(soc);
  2076. return QDF_STATUS_E_RESOURCES;
  2077. }
  2078. /*
  2079. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2080. * pdev: pointer to DP PDEV structure
  2081. * seg_info_head: Pointer to the head of list
  2082. *
  2083. * return: void
  2084. */
  2085. static inline void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2086. struct dp_tx_seg_info_s *seg_info_head)
  2087. {
  2088. struct dp_tx_me_buf_t *mc_uc_buf;
  2089. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2090. qdf_nbuf_t nbuf = NULL;
  2091. uint64_t phy_addr;
  2092. while (seg_info_head) {
  2093. nbuf = seg_info_head->nbuf;
  2094. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2095. seg_info_new->frags[0].vaddr;
  2096. phy_addr = seg_info_head->frags[0].paddr_hi;
  2097. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2098. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2099. phy_addr,
  2100. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2101. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2102. qdf_nbuf_free(nbuf);
  2103. seg_info_new = seg_info_head;
  2104. seg_info_head = seg_info_head->next;
  2105. qdf_mem_free(seg_info_new);
  2106. }
  2107. }
  2108. /**
  2109. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2110. * @vdev: DP VDEV handle
  2111. * @nbuf: Multicast nbuf
  2112. * @newmac: Table of the clients to which packets have to be sent
  2113. * @new_mac_cnt: No of clients
  2114. *
  2115. * return: no of converted packets
  2116. */
  2117. uint16_t
  2118. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2119. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2120. {
  2121. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2122. struct dp_pdev *pdev = vdev->pdev;
  2123. struct ether_header *eh;
  2124. uint8_t *data;
  2125. uint16_t len;
  2126. /* reference to frame dst addr */
  2127. uint8_t *dstmac;
  2128. /* copy of original frame src addr */
  2129. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2130. /* local index into newmac */
  2131. uint8_t new_mac_idx = 0;
  2132. struct dp_tx_me_buf_t *mc_uc_buf;
  2133. qdf_nbuf_t nbuf_clone;
  2134. struct dp_tx_msdu_info_s msdu_info;
  2135. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2136. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2137. struct dp_tx_seg_info_s *seg_info_new;
  2138. struct dp_tx_frag_info_s data_frag;
  2139. qdf_dma_addr_t paddr_data;
  2140. qdf_dma_addr_t paddr_mcbuf = 0;
  2141. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2142. QDF_STATUS status;
  2143. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2144. eh = (struct ether_header *) nbuf;
  2145. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2146. len = qdf_nbuf_len(nbuf);
  2147. data = qdf_nbuf_data(nbuf);
  2148. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2149. QDF_DMA_TO_DEVICE);
  2150. if (status) {
  2151. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2152. "Mapping failure Error:%d", status);
  2153. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2154. return 0;
  2155. }
  2156. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2157. /*preparing data fragment*/
  2158. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2159. data_frag.paddr_lo = (uint32_t)paddr_data;
  2160. data_frag.paddr_hi = ((uint64_t)paddr_data & 0xffffffff00000000) >> 32;
  2161. data_frag.len = len - DP_MAC_ADDR_LEN;
  2162. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2163. dstmac = newmac[new_mac_idx];
  2164. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2165. "added mac addr (%pM)", dstmac);
  2166. /* Check for NULL Mac Address */
  2167. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2168. continue;
  2169. /* frame to self mac. skip */
  2170. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2171. continue;
  2172. /*
  2173. * TODO: optimize to avoid malloc in per-packet path
  2174. * For eg. seg_pool can be made part of vdev structure
  2175. */
  2176. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2177. if (!seg_info_new) {
  2178. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2179. "alloc failed");
  2180. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2181. goto fail_seg_alloc;
  2182. }
  2183. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2184. if (mc_uc_buf == NULL)
  2185. goto fail_buf_alloc;
  2186. /*
  2187. * TODO: Check if we need to clone the nbuf
  2188. * Or can we just use the reference for all cases
  2189. */
  2190. if (new_mac_idx < (new_mac_cnt - 1)) {
  2191. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2192. if (nbuf_clone == NULL) {
  2193. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2194. goto fail_clone;
  2195. }
  2196. } else {
  2197. /*
  2198. * Update the ref
  2199. * to account for frame sent without cloning
  2200. */
  2201. qdf_nbuf_ref(nbuf);
  2202. nbuf_clone = nbuf;
  2203. }
  2204. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2205. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2206. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2207. &paddr_mcbuf);
  2208. if (status) {
  2209. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2210. "Mapping failure Error:%d", status);
  2211. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2212. goto fail_map;
  2213. }
  2214. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2215. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2216. seg_info_new->frags[0].paddr_hi =
  2217. ((u64)paddr_mcbuf & 0xffffffff00000000) >> 32;
  2218. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2219. seg_info_new->frags[1] = data_frag;
  2220. seg_info_new->nbuf = nbuf_clone;
  2221. seg_info_new->frag_cnt = 2;
  2222. seg_info_new->total_len = len;
  2223. seg_info_new->next = NULL;
  2224. if (seg_info_head == NULL)
  2225. seg_info_head = seg_info_new;
  2226. else
  2227. seg_info_tail->next = seg_info_new;
  2228. seg_info_tail = seg_info_new;
  2229. }
  2230. if (!seg_info_head)
  2231. return 0;
  2232. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2233. msdu_info.num_seg = new_mac_cnt;
  2234. msdu_info.frm_type = dp_tx_frm_me;
  2235. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2236. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2237. while (seg_info_head->next) {
  2238. seg_info_new = seg_info_head;
  2239. seg_info_head = seg_info_head->next;
  2240. qdf_mem_free(seg_info_new);
  2241. }
  2242. qdf_mem_free(seg_info_head);
  2243. return new_mac_cnt;
  2244. fail_map:
  2245. qdf_nbuf_free(nbuf_clone);
  2246. fail_clone:
  2247. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2248. fail_buf_alloc:
  2249. qdf_mem_free(seg_info_new);
  2250. fail_seg_alloc:
  2251. dp_tx_me_mem_free(pdev, seg_info_head);
  2252. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2253. return 0;
  2254. }