dsi_drm.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <drm/drm_atomic_helper.h>
  7. #include <drm/drm_atomic.h>
  8. #include "msm_kms.h"
  9. #include "sde_connector.h"
  10. #include "dsi_drm.h"
  11. #include "sde_trace.h"
  12. #include "sde_dbg.h"
  13. #include "msm_drv.h"
  14. #include "sde_encoder.h"
  15. #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
  16. #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
  17. #define DEFAULT_PANEL_JITTER_NUMERATOR 2
  18. #define DEFAULT_PANEL_JITTER_DENOMINATOR 1
  19. #define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
  20. #define DEFAULT_PANEL_PREFILL_LINES 25
  21. static struct dsi_display_mode_priv_info default_priv_info = {
  22. .panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR,
  23. .panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR,
  24. .panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES,
  25. .dsc_enabled = false,
  26. };
  27. static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
  28. struct dsi_display_mode *dsi_mode)
  29. {
  30. memset(dsi_mode, 0, sizeof(*dsi_mode));
  31. dsi_mode->timing.h_active = drm_mode->hdisplay;
  32. dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
  33. dsi_mode->timing.h_sync_width = drm_mode->htotal -
  34. (drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
  35. dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
  36. drm_mode->hdisplay;
  37. dsi_mode->timing.h_skew = drm_mode->hskew;
  38. dsi_mode->timing.v_active = drm_mode->vdisplay;
  39. dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
  40. dsi_mode->timing.v_sync_width = drm_mode->vtotal -
  41. (drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
  42. dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
  43. drm_mode->vdisplay;
  44. dsi_mode->timing.refresh_rate = drm_mode_vrefresh(drm_mode);
  45. dsi_mode->timing.h_sync_polarity =
  46. !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC);
  47. dsi_mode->timing.v_sync_polarity =
  48. !!(drm_mode->flags & DRM_MODE_FLAG_PVSYNC);
  49. }
  50. static void msm_parse_mode_priv_info(const struct msm_display_mode *msm_mode,
  51. struct dsi_display_mode *dsi_mode)
  52. {
  53. dsi_mode->priv_info =
  54. (struct dsi_display_mode_priv_info *)msm_mode->private;
  55. if (dsi_mode->priv_info) {
  56. dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;
  57. dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;
  58. dsi_mode->timing.vdc_enabled = dsi_mode->priv_info->vdc_enabled;
  59. dsi_mode->timing.vdc = &dsi_mode->priv_info->vdc;
  60. dsi_mode->timing.pclk_scale = dsi_mode->priv_info->pclk_scale;
  61. dsi_mode->timing.clk_rate_hz = dsi_mode->priv_info->clk_rate_hz;
  62. }
  63. if (msm_is_mode_seamless(msm_mode))
  64. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
  65. if (msm_is_mode_dynamic_fps(msm_mode))
  66. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS;
  67. if (msm_needs_vblank_pre_modeset(msm_mode))
  68. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  69. if (msm_is_mode_seamless_dms(msm_mode))
  70. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  71. if (msm_is_mode_seamless_vrr(msm_mode))
  72. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  73. if (msm_is_mode_seamless_poms_to_vid(msm_mode))
  74. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_VID;
  75. if (msm_is_mode_seamless_poms_to_cmd(msm_mode))
  76. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_CMD;
  77. if (msm_is_mode_seamless_dyn_clk(msm_mode))
  78. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK;
  79. }
  80. void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
  81. struct drm_display_mode *drm_mode)
  82. {
  83. char *panel_caps = "vid";
  84. if ((dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE) &&
  85. (dsi_mode->panel_mode_caps & DSI_OP_CMD_MODE))
  86. panel_caps = "vid_cmd";
  87. else if (dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE)
  88. panel_caps = "vid";
  89. else if (dsi_mode->panel_mode_caps & DSI_OP_CMD_MODE)
  90. panel_caps = "cmd";
  91. memset(drm_mode, 0, sizeof(*drm_mode));
  92. drm_mode->hdisplay = dsi_mode->timing.h_active;
  93. drm_mode->hsync_start = drm_mode->hdisplay +
  94. dsi_mode->timing.h_front_porch;
  95. drm_mode->hsync_end = drm_mode->hsync_start +
  96. dsi_mode->timing.h_sync_width;
  97. drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
  98. drm_mode->hskew = dsi_mode->timing.h_skew;
  99. drm_mode->vdisplay = dsi_mode->timing.v_active;
  100. drm_mode->vsync_start = drm_mode->vdisplay +
  101. dsi_mode->timing.v_front_porch;
  102. drm_mode->vsync_end = drm_mode->vsync_start +
  103. dsi_mode->timing.v_sync_width;
  104. drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
  105. drm_mode->clock = drm_mode->htotal * drm_mode->vtotal * dsi_mode->timing.refresh_rate;
  106. drm_mode->clock /= 1000;
  107. if (dsi_mode->timing.h_sync_polarity)
  108. drm_mode->flags |= DRM_MODE_FLAG_PHSYNC;
  109. if (dsi_mode->timing.v_sync_polarity)
  110. drm_mode->flags |= DRM_MODE_FLAG_PVSYNC;
  111. /* set mode name */
  112. snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%d%s",
  113. drm_mode->hdisplay, drm_mode->vdisplay,
  114. drm_mode_vrefresh(drm_mode), panel_caps);
  115. }
  116. static void dsi_convert_to_msm_mode(const struct dsi_display_mode *dsi_mode,
  117. struct msm_display_mode *msm_mode)
  118. {
  119. msm_mode->private_flags = 0;
  120. msm_mode->private = (int *)dsi_mode->priv_info;
  121. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
  122. msm_mode->private_flags |= DRM_MODE_FLAG_SEAMLESS;
  123. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
  124. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
  125. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
  126. msm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
  127. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
  128. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS;
  129. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)
  130. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR;
  131. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)
  132. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS_VID;
  133. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)
  134. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS_CMD;
  135. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)
  136. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK;
  137. }
  138. static int dsi_bridge_attach(struct drm_bridge *bridge,
  139. enum drm_bridge_attach_flags flags)
  140. {
  141. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  142. if (!bridge) {
  143. DSI_ERR("Invalid params\n");
  144. return -EINVAL;
  145. }
  146. DSI_DEBUG("[%d] attached\n", c_bridge->id);
  147. return 0;
  148. }
  149. static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
  150. {
  151. int rc = 0;
  152. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  153. if (!bridge) {
  154. DSI_ERR("Invalid params\n");
  155. return;
  156. }
  157. if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
  158. DSI_ERR("Incorrect bridge details\n");
  159. return;
  160. }
  161. atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
  162. /* By this point mode should have been validated through mode_fixup */
  163. rc = dsi_display_set_mode(c_bridge->display,
  164. &(c_bridge->dsi_mode), 0x0);
  165. if (rc) {
  166. DSI_ERR("[%d] failed to perform a mode set, rc=%d\n",
  167. c_bridge->id, rc);
  168. return;
  169. }
  170. if (c_bridge->dsi_mode.dsi_mode_flags &
  171. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  172. DSI_MODE_FLAG_DYN_CLK)) {
  173. DSI_DEBUG("[%d] seamless pre-enable\n", c_bridge->id);
  174. return;
  175. }
  176. SDE_ATRACE_BEGIN("dsi_display_prepare");
  177. rc = dsi_display_prepare(c_bridge->display);
  178. if (rc) {
  179. DSI_ERR("[%d] DSI display prepare failed, rc=%d\n",
  180. c_bridge->id, rc);
  181. SDE_ATRACE_END("dsi_display_prepare");
  182. return;
  183. }
  184. SDE_ATRACE_END("dsi_display_prepare");
  185. SDE_ATRACE_BEGIN("dsi_display_enable");
  186. rc = dsi_display_enable(c_bridge->display);
  187. if (rc) {
  188. DSI_ERR("[%d] DSI display enable failed, rc=%d\n",
  189. c_bridge->id, rc);
  190. (void)dsi_display_unprepare(c_bridge->display);
  191. }
  192. SDE_ATRACE_END("dsi_display_enable");
  193. rc = dsi_display_splash_res_cleanup(c_bridge->display);
  194. if (rc)
  195. DSI_ERR("Continuous splash pipeline cleanup failed, rc=%d\n",
  196. rc);
  197. }
  198. static void dsi_bridge_enable(struct drm_bridge *bridge)
  199. {
  200. int rc = 0;
  201. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  202. struct dsi_display *display;
  203. if (!bridge) {
  204. DSI_ERR("Invalid params\n");
  205. return;
  206. }
  207. if (c_bridge->dsi_mode.dsi_mode_flags &
  208. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  209. DSI_MODE_FLAG_DYN_CLK)) {
  210. DSI_DEBUG("[%d] seamless enable\n", c_bridge->id);
  211. return;
  212. }
  213. display = c_bridge->display;
  214. rc = dsi_display_post_enable(display);
  215. if (rc)
  216. DSI_ERR("[%d] DSI display post enabled failed, rc=%d\n",
  217. c_bridge->id, rc);
  218. if (display)
  219. display->enabled = true;
  220. if (display && display->drm_conn) {
  221. sde_connector_helper_bridge_enable(display->drm_conn);
  222. if (display->poms_pending) {
  223. display->poms_pending = false;
  224. sde_connector_schedule_status_work(display->drm_conn,
  225. true);
  226. }
  227. }
  228. }
  229. static void dsi_bridge_disable(struct drm_bridge *bridge)
  230. {
  231. int rc = 0;
  232. struct dsi_display *display;
  233. struct sde_connector_state *conn_state;
  234. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  235. if (!bridge) {
  236. DSI_ERR("Invalid params\n");
  237. return;
  238. }
  239. display = c_bridge->display;
  240. if (display)
  241. display->enabled = false;
  242. if (display && display->drm_conn) {
  243. conn_state = to_sde_connector_state(display->drm_conn->state);
  244. if (!conn_state) {
  245. DSI_ERR("invalid params\n");
  246. return;
  247. }
  248. display->poms_pending = msm_is_mode_seamless_poms(
  249. &conn_state->msm_mode);
  250. sde_connector_helper_bridge_disable(display->drm_conn);
  251. }
  252. rc = dsi_display_pre_disable(c_bridge->display);
  253. if (rc) {
  254. DSI_ERR("[%d] DSI display pre disable failed, rc=%d\n",
  255. c_bridge->id, rc);
  256. }
  257. }
  258. static void dsi_bridge_post_disable(struct drm_bridge *bridge)
  259. {
  260. int rc = 0;
  261. struct dsi_display *display;
  262. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  263. if (!bridge) {
  264. DSI_ERR("Invalid params\n");
  265. return;
  266. }
  267. display = c_bridge->display;
  268. SDE_ATRACE_BEGIN("dsi_bridge_post_disable");
  269. SDE_ATRACE_BEGIN("dsi_display_disable");
  270. rc = dsi_display_disable(c_bridge->display);
  271. if (rc) {
  272. DSI_ERR("[%d] DSI display disable failed, rc=%d\n",
  273. c_bridge->id, rc);
  274. SDE_ATRACE_END("dsi_display_disable");
  275. return;
  276. }
  277. SDE_ATRACE_END("dsi_display_disable");
  278. if (display && display->drm_conn)
  279. sde_connector_helper_bridge_post_disable(display->drm_conn);
  280. rc = dsi_display_unprepare(c_bridge->display);
  281. if (rc) {
  282. DSI_ERR("[%d] DSI display unprepare failed, rc=%d\n",
  283. c_bridge->id, rc);
  284. SDE_ATRACE_END("dsi_bridge_post_disable");
  285. return;
  286. }
  287. SDE_ATRACE_END("dsi_bridge_post_disable");
  288. }
  289. static void dsi_bridge_mode_set(struct drm_bridge *bridge,
  290. const struct drm_display_mode *mode,
  291. const struct drm_display_mode *adjusted_mode)
  292. {
  293. int rc = 0;
  294. struct dsi_bridge *c_bridge = NULL;
  295. struct dsi_display *display;
  296. struct drm_connector *conn;
  297. struct sde_connector_state *conn_state;
  298. if (!bridge || !mode || !adjusted_mode) {
  299. DSI_ERR("Invalid params\n");
  300. return;
  301. }
  302. c_bridge = to_dsi_bridge(bridge);
  303. if (!c_bridge) {
  304. DSI_ERR("invalid dsi bridge\n");
  305. return;
  306. }
  307. display = c_bridge->display;
  308. if (!display || !display->drm_conn || !display->drm_conn->state) {
  309. DSI_ERR("invalid display\n");
  310. return;
  311. }
  312. memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
  313. convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
  314. conn = sde_encoder_get_connector(bridge->dev, bridge->encoder);
  315. if (!conn)
  316. return;
  317. conn_state = to_sde_connector_state(conn->state);
  318. if (!conn_state) {
  319. DSI_ERR("invalid connector state\n");
  320. return;
  321. }
  322. msm_parse_mode_priv_info(&conn_state->msm_mode,
  323. &(c_bridge->dsi_mode));
  324. rc = dsi_display_restore_bit_clk(display, &c_bridge->dsi_mode);
  325. if (rc) {
  326. DSI_ERR("[%s] bit clk rate cannot be restored\n", display->name);
  327. return;
  328. }
  329. DSI_DEBUG("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz);
  330. }
  331. static bool _dsi_bridge_mode_validate_and_fixup(struct drm_bridge *bridge,
  332. struct drm_crtc_state *crtc_state, struct dsi_display *display,
  333. struct dsi_display_mode *adj_mode)
  334. {
  335. int rc = 0;
  336. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  337. struct dsi_display_mode cur_dsi_mode;
  338. struct sde_connector_state *old_conn_state;
  339. struct drm_display_mode *cur_mode;
  340. if (!bridge->encoder || !bridge->encoder->crtc || !crtc_state->crtc) {
  341. DSI_ERR("invalid params\n");
  342. return -EINVAL;
  343. }
  344. cur_mode = &crtc_state->crtc->state->mode;
  345. old_conn_state = to_sde_connector_state(display->drm_conn->state);
  346. convert_to_dsi_mode(cur_mode, &cur_dsi_mode);
  347. msm_parse_mode_priv_info(&old_conn_state->msm_mode, &cur_dsi_mode);
  348. rc = dsi_display_validate_mode_change(c_bridge->display, &cur_dsi_mode, adj_mode);
  349. if (rc) {
  350. DSI_ERR("[%s] seamless mode mismatch failure rc=%d\n", c_bridge->display->name, rc);
  351. return rc;
  352. }
  353. /*
  354. * DMS Flag if set during active changed condition cannot be
  355. * treated as seamless. Hence, removing DMS flag in such cases.
  356. */
  357. if ((adj_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  358. crtc_state->active_changed)
  359. adj_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS;
  360. /* No DMS/VRR when drm pipeline is changing */
  361. if (!dsi_display_mode_match(&cur_dsi_mode, adj_mode,
  362. DSI_MODE_MATCH_FULL_TIMINGS) &&
  363. (!(adj_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  364. (!(adj_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
  365. (!(adj_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)) &&
  366. (!(adj_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)) &&
  367. (!crtc_state->active_changed ||
  368. display->is_cont_splash_enabled)) {
  369. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  370. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2,
  371. adj_mode->timing.h_active,
  372. adj_mode->timing.v_active,
  373. adj_mode->timing.refresh_rate,
  374. adj_mode->pixel_clk_khz,
  375. adj_mode->panel_mode_caps);
  376. }
  377. return rc;
  378. }
  379. static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
  380. const struct drm_display_mode *mode,
  381. struct drm_display_mode *adjusted_mode)
  382. {
  383. int rc = 0;
  384. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  385. struct dsi_display *display;
  386. struct dsi_display_mode dsi_mode, *panel_dsi_mode;
  387. struct drm_crtc_state *crtc_state;
  388. struct drm_connector_state *drm_conn_state;
  389. struct sde_connector_state *conn_state;
  390. struct msm_sub_mode new_sub_mode;
  391. crtc_state = container_of(mode, struct drm_crtc_state, mode);
  392. if (!bridge || !mode || !adjusted_mode) {
  393. DSI_ERR("invalid params\n");
  394. return false;
  395. }
  396. display = c_bridge->display;
  397. if (!display || !display->drm_conn || !display->drm_conn->state) {
  398. DSI_ERR("invalid params\n");
  399. return false;
  400. }
  401. drm_conn_state = drm_atomic_get_new_connector_state(crtc_state->state,
  402. display->drm_conn);
  403. conn_state = to_sde_connector_state(drm_conn_state);
  404. if (!conn_state) {
  405. DSI_ERR("invalid params\n");
  406. return false;
  407. }
  408. /*
  409. * if no timing defined in panel, it must be external mode
  410. * and we'll use empty priv info to populate the mode
  411. */
  412. if (display->panel && !display->panel->num_timing_nodes) {
  413. *adjusted_mode = *mode;
  414. conn_state->msm_mode.base = adjusted_mode;
  415. conn_state->msm_mode.private = (int *)&default_priv_info;
  416. conn_state->msm_mode.private_flags = 0;
  417. return true;
  418. }
  419. convert_to_dsi_mode(mode, &dsi_mode);
  420. msm_parse_mode_priv_info(&conn_state->msm_mode, &dsi_mode);
  421. new_sub_mode.dsc_mode = sde_connector_get_property(drm_conn_state,
  422. CONNECTOR_PROP_DSC_MODE);
  423. /*
  424. * retrieve dsi mode from dsi driver's cache since not safe to take
  425. * the drm mode config mutex in all paths
  426. */
  427. rc = dsi_display_find_mode(display, &dsi_mode, &new_sub_mode,
  428. &panel_dsi_mode);
  429. if (rc)
  430. return rc;
  431. /* propagate the private info to the adjusted_mode derived dsi mode */
  432. dsi_mode.priv_info = panel_dsi_mode->priv_info;
  433. dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;
  434. dsi_mode.panel_mode_caps = panel_dsi_mode->panel_mode_caps;
  435. dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;
  436. dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  437. rc = dsi_display_restore_bit_clk(display, &dsi_mode);
  438. if (rc) {
  439. DSI_ERR("[%s] bit clk rate cannot be restored\n", display->name);
  440. return false;
  441. }
  442. rc = dsi_display_update_dyn_bit_clk(display, &dsi_mode);
  443. if (rc) {
  444. DSI_ERR("[%s] failed to update bit clock\n", display->name);
  445. return false;
  446. }
  447. rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
  448. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  449. if (rc) {
  450. DSI_ERR("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
  451. return false;
  452. }
  453. rc = _dsi_bridge_mode_validate_and_fixup(bridge, crtc_state, display, &dsi_mode);
  454. if (rc) {
  455. DSI_ERR("[%s] failed to validate dsi bridge mode.\n", display->name);
  456. return false;
  457. }
  458. /* Reject seamless transition when active changed */
  459. if (crtc_state->active_changed &&
  460. ((dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) ||
  461. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) ||
  462. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID) ||
  463. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD))) {
  464. DSI_INFO("seamless upon active changed 0x%x %d\n",
  465. dsi_mode.dsi_mode_flags, crtc_state->active_changed);
  466. return false;
  467. }
  468. /* convert back to drm mode, propagating the private info & flags */
  469. dsi_convert_to_drm_mode(&dsi_mode, adjusted_mode);
  470. dsi_convert_to_msm_mode(&dsi_mode, &conn_state->msm_mode);
  471. return true;
  472. }
  473. u32 dsi_drm_get_dfps_maxfps(void *display)
  474. {
  475. u32 dfps_maxfps = 0;
  476. struct dsi_display *dsi_display = display;
  477. /*
  478. * The time of SDE transmitting one frame active data
  479. * will not be changed, if frame rate is adjusted with
  480. * VFP method.
  481. * So only return max fps of DFPS for UIDLE update, if DFPS
  482. * is enabled with VFP.
  483. */
  484. if (dsi_display && dsi_display->panel &&
  485. dsi_display->panel->panel_mode == DSI_OP_VIDEO_MODE &&
  486. dsi_display->panel->dfps_caps.type ==
  487. DSI_DFPS_IMMEDIATE_VFP)
  488. dfps_maxfps =
  489. dsi_display->panel->dfps_caps.max_refresh_rate;
  490. return dfps_maxfps;
  491. }
  492. int dsi_conn_get_lm_from_mode(void *display, const struct drm_display_mode *drm_mode)
  493. {
  494. struct dsi_display *dsi_display = display;
  495. struct dsi_display_mode dsi_mode, *panel_dsi_mode;
  496. int rc = -EINVAL;
  497. if (!dsi_display || !drm_mode) {
  498. DSI_ERR("Invalid params %d %d\n", !display, !drm_mode);
  499. return rc;
  500. }
  501. convert_to_dsi_mode(drm_mode, &dsi_mode);
  502. rc = dsi_display_find_mode(dsi_display, &dsi_mode, NULL, &panel_dsi_mode);
  503. if (rc) {
  504. DSI_ERR("mode not found %d\n", rc);
  505. drm_mode_debug_printmodeline(drm_mode);
  506. return rc;
  507. }
  508. return panel_dsi_mode->priv_info->topology.num_lm;
  509. }
  510. int dsi_conn_get_mode_info(struct drm_connector *connector,
  511. const struct drm_display_mode *drm_mode,
  512. struct msm_sub_mode *sub_mode,
  513. struct msm_mode_info *mode_info,
  514. void *display, const struct msm_resource_caps_info *avail_res)
  515. {
  516. struct dsi_display_mode partial_dsi_mode, *dsi_mode = NULL;
  517. struct dsi_mode_info *timing;
  518. int src_bpp, tar_bpp, rc = 0;
  519. struct dsi_display *dsi_display = (struct dsi_display *) display;
  520. if (!drm_mode || !mode_info)
  521. return -EINVAL;
  522. convert_to_dsi_mode(drm_mode, &partial_dsi_mode);
  523. rc = dsi_display_find_mode(dsi_display, &partial_dsi_mode, sub_mode, &dsi_mode);
  524. if (rc || !dsi_mode->priv_info)
  525. return -EINVAL;
  526. memset(mode_info, 0, sizeof(*mode_info));
  527. timing = &dsi_mode->timing;
  528. mode_info->frame_rate = dsi_mode->timing.refresh_rate;
  529. mode_info->vtotal = DSI_V_TOTAL(timing);
  530. mode_info->prefill_lines = dsi_mode->priv_info->panel_prefill_lines;
  531. mode_info->jitter_numer = dsi_mode->priv_info->panel_jitter_numer;
  532. mode_info->jitter_denom = dsi_mode->priv_info->panel_jitter_denom;
  533. mode_info->dfps_maxfps = dsi_drm_get_dfps_maxfps(display);
  534. mode_info->panel_mode_caps = dsi_mode->panel_mode_caps;
  535. mode_info->mdp_transfer_time_us =
  536. dsi_mode->priv_info->mdp_transfer_time_us;
  537. mode_info->disable_rsc_solver = dsi_mode->priv_info->disable_rsc_solver;
  538. mode_info->qsync_min_fps = dsi_mode->timing.qsync_min_fps;
  539. memcpy(&mode_info->topology, &dsi_mode->priv_info->topology,
  540. sizeof(struct msm_display_topology));
  541. if (dsi_mode->priv_info->bit_clk_list.count) {
  542. struct msm_dyn_clk_list *dyn_clk_list = &mode_info->dyn_clk_list;
  543. dyn_clk_list->rates = dsi_mode->priv_info->bit_clk_list.rates;
  544. dyn_clk_list->count = dsi_mode->priv_info->bit_clk_list.count;
  545. dyn_clk_list->type = dsi_display->panel->dyn_clk_caps.type;
  546. dyn_clk_list->front_porches = dsi_mode->priv_info->bit_clk_list.front_porches;
  547. dyn_clk_list->pixel_clks_khz = dsi_mode->priv_info->bit_clk_list.pixel_clks_khz;
  548. rc = dsi_display_restore_bit_clk(dsi_display, dsi_mode);
  549. if (rc) {
  550. DSI_ERR("[%s] bit clk rate cannot be restored\n", dsi_display->name);
  551. return rc;
  552. }
  553. }
  554. mode_info->clk_rate = dsi_mode->timing.clk_rate_hz;
  555. if (dsi_mode->priv_info->dsc_enabled) {
  556. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  557. mode_info->topology.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  558. memcpy(&mode_info->comp_info.dsc_info, &dsi_mode->priv_info->dsc,
  559. sizeof(dsi_mode->priv_info->dsc));
  560. } else if (dsi_mode->priv_info->vdc_enabled) {
  561. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_VDC;
  562. mode_info->topology.comp_type = MSM_DISPLAY_COMPRESSION_VDC;
  563. memcpy(&mode_info->comp_info.vdc_info, &dsi_mode->priv_info->vdc,
  564. sizeof(dsi_mode->priv_info->vdc));
  565. }
  566. if (mode_info->comp_info.comp_type) {
  567. tar_bpp = dsi_mode->priv_info->pclk_scale.numer;
  568. src_bpp = dsi_mode->priv_info->pclk_scale.denom;
  569. mode_info->comp_info.comp_ratio = mult_frac(1, src_bpp,
  570. tar_bpp);
  571. mode_info->wide_bus_en = dsi_mode->priv_info->widebus_support;
  572. }
  573. if (dsi_mode->priv_info->roi_caps.enabled) {
  574. memcpy(&mode_info->roi_caps, &dsi_mode->priv_info->roi_caps,
  575. sizeof(dsi_mode->priv_info->roi_caps));
  576. }
  577. mode_info->allowed_mode_switches =
  578. dsi_mode->priv_info->allowed_mode_switch;
  579. return 0;
  580. }
  581. static const struct drm_bridge_funcs dsi_bridge_ops = {
  582. .attach = dsi_bridge_attach,
  583. .mode_fixup = dsi_bridge_mode_fixup,
  584. .pre_enable = dsi_bridge_pre_enable,
  585. .enable = dsi_bridge_enable,
  586. .disable = dsi_bridge_disable,
  587. .post_disable = dsi_bridge_post_disable,
  588. .mode_set = dsi_bridge_mode_set,
  589. };
  590. int dsi_conn_set_avr_step_info(struct dsi_panel *panel, void *info)
  591. {
  592. u32 i;
  593. int idx = 0;
  594. size_t buff_sz = PAGE_SIZE;
  595. char *buff;
  596. buff = kzalloc(buff_sz, GFP_KERNEL);
  597. if (!buff)
  598. return -ENOMEM;
  599. for (i = 0; i < panel->avr_caps.avr_step_fps_list_len && (idx < (buff_sz - 1)); i++)
  600. idx += scnprintf(&buff[idx], buff_sz - idx, "%u@%u ",
  601. panel->avr_caps.avr_step_fps_list[i],
  602. panel->dfps_caps.dfps_list[i]);
  603. sde_kms_info_add_keystr(info, "avr step requirement", buff);
  604. kfree(buff);
  605. return 0;
  606. }
  607. int dsi_conn_get_qsync_min_fps(struct drm_connector_state *conn_state)
  608. {
  609. struct sde_connector_state *sde_conn_state = to_sde_connector_state(conn_state);
  610. struct msm_display_mode *msm_mode;
  611. struct dsi_display_mode_priv_info *priv_info;
  612. if (!sde_conn_state)
  613. return -EINVAL;
  614. msm_mode = &sde_conn_state->msm_mode;
  615. if (!msm_mode || !msm_mode->private)
  616. return -EINVAL;
  617. priv_info = (struct dsi_display_mode_priv_info *)(msm_mode->private);
  618. return priv_info->qsync_min_fps;
  619. }
  620. int dsi_conn_set_info_blob(struct drm_connector *connector,
  621. void *info, void *display, struct msm_mode_info *mode_info)
  622. {
  623. struct dsi_display *dsi_display = display;
  624. struct dsi_panel *panel;
  625. enum dsi_pixel_format fmt;
  626. u32 bpp;
  627. if (!info || !dsi_display)
  628. return -EINVAL;
  629. dsi_display->drm_conn = connector;
  630. sde_kms_info_add_keystr(info,
  631. "display type", dsi_display->display_type);
  632. switch (dsi_display->type) {
  633. case DSI_DISPLAY_SINGLE:
  634. sde_kms_info_add_keystr(info, "display config",
  635. "single display");
  636. break;
  637. case DSI_DISPLAY_EXT_BRIDGE:
  638. sde_kms_info_add_keystr(info, "display config", "ext bridge");
  639. break;
  640. case DSI_DISPLAY_SPLIT:
  641. sde_kms_info_add_keystr(info, "display config",
  642. "split display");
  643. break;
  644. case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
  645. sde_kms_info_add_keystr(info, "display config",
  646. "split ext bridge");
  647. break;
  648. default:
  649. DSI_DEBUG("invalid display type:%d\n", dsi_display->type);
  650. break;
  651. }
  652. if (!dsi_display->panel) {
  653. DSI_DEBUG("invalid panel data\n");
  654. goto end;
  655. }
  656. panel = dsi_display->panel;
  657. sde_kms_info_add_keystr(info, "panel name", panel->name);
  658. switch (panel->panel_mode) {
  659. case DSI_OP_VIDEO_MODE:
  660. sde_kms_info_add_keystr(info, "panel mode", "video");
  661. if (panel->avr_caps.avr_step_fps_list_len)
  662. dsi_conn_set_avr_step_info(panel, info);
  663. break;
  664. case DSI_OP_CMD_MODE:
  665. sde_kms_info_add_keystr(info, "panel mode", "command");
  666. sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
  667. mode_info->mdp_transfer_time_us);
  668. break;
  669. default:
  670. DSI_DEBUG("invalid panel type:%d\n", panel->panel_mode);
  671. break;
  672. }
  673. sde_kms_info_add_keystr(info, "qsync support",
  674. panel->qsync_caps.qsync_support ?
  675. "true" : "false");
  676. if (panel->qsync_caps.qsync_min_fps)
  677. sde_kms_info_add_keyint(info, "qsync_fps",
  678. panel->qsync_caps.qsync_min_fps);
  679. sde_kms_info_add_keystr(info, "dfps support",
  680. panel->dfps_caps.dfps_support ? "true" : "false");
  681. if (panel->dfps_caps.dfps_support) {
  682. sde_kms_info_add_keyint(info, "min_fps",
  683. panel->dfps_caps.min_refresh_rate);
  684. sde_kms_info_add_keyint(info, "max_fps",
  685. panel->dfps_caps.max_refresh_rate);
  686. }
  687. sde_kms_info_add_keystr(info, "dyn bitclk support",
  688. panel->dyn_clk_caps.dyn_clk_support ? "true" : "false");
  689. switch (panel->phy_props.rotation) {
  690. case DSI_PANEL_ROTATE_NONE:
  691. sde_kms_info_add_keystr(info, "panel orientation", "none");
  692. break;
  693. case DSI_PANEL_ROTATE_H_FLIP:
  694. sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
  695. break;
  696. case DSI_PANEL_ROTATE_V_FLIP:
  697. sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
  698. break;
  699. case DSI_PANEL_ROTATE_HV_FLIP:
  700. sde_kms_info_add_keystr(info, "panel orientation",
  701. "horz & vert flip");
  702. break;
  703. default:
  704. DSI_DEBUG("invalid panel rotation:%d\n",
  705. panel->phy_props.rotation);
  706. break;
  707. }
  708. switch (panel->bl_config.type) {
  709. case DSI_BACKLIGHT_PWM:
  710. sde_kms_info_add_keystr(info, "backlight type", "pwm");
  711. break;
  712. case DSI_BACKLIGHT_WLED:
  713. sde_kms_info_add_keystr(info, "backlight type", "wled");
  714. break;
  715. case DSI_BACKLIGHT_DCS:
  716. sde_kms_info_add_keystr(info, "backlight type", "dcs");
  717. break;
  718. default:
  719. DSI_DEBUG("invalid panel backlight type:%d\n",
  720. panel->bl_config.type);
  721. break;
  722. }
  723. sde_kms_info_add_keyint(info, "max os brightness", panel->bl_config.brightness_max_level);
  724. sde_kms_info_add_keyint(info, "max panel backlight", panel->bl_config.bl_max_level);
  725. if (panel->spr_info.enable)
  726. sde_kms_info_add_keystr(info, "spr_pack_type",
  727. msm_spr_pack_type_str[panel->spr_info.pack_type]);
  728. if (mode_info && mode_info->roi_caps.enabled) {
  729. sde_kms_info_add_keyint(info, "partial_update_num_roi",
  730. mode_info->roi_caps.num_roi);
  731. sde_kms_info_add_keyint(info, "partial_update_xstart",
  732. mode_info->roi_caps.align.xstart_pix_align);
  733. sde_kms_info_add_keyint(info, "partial_update_walign",
  734. mode_info->roi_caps.align.width_pix_align);
  735. sde_kms_info_add_keyint(info, "partial_update_wmin",
  736. mode_info->roi_caps.align.min_width);
  737. sde_kms_info_add_keyint(info, "partial_update_ystart",
  738. mode_info->roi_caps.align.ystart_pix_align);
  739. sde_kms_info_add_keyint(info, "partial_update_halign",
  740. mode_info->roi_caps.align.height_pix_align);
  741. sde_kms_info_add_keyint(info, "partial_update_hmin",
  742. mode_info->roi_caps.align.min_height);
  743. sde_kms_info_add_keyint(info, "partial_update_roimerge",
  744. mode_info->roi_caps.merge_rois);
  745. }
  746. fmt = dsi_display->config.common_config.dst_format;
  747. bpp = dsi_ctrl_pixel_format_to_bpp(fmt);
  748. sde_kms_info_add_keyint(info, "bit_depth", bpp);
  749. end:
  750. return 0;
  751. }
  752. void dsi_conn_set_submode_blob_info(struct drm_connector *conn,
  753. void *info, void *display, struct drm_display_mode *drm_mode)
  754. {
  755. struct dsi_display *dsi_display = display;
  756. struct dsi_display_mode partial_dsi_mode;
  757. int count, i;
  758. int preferred_submode_idx = -EINVAL;
  759. enum dsi_dyn_clk_feature_type dyn_clk_type;
  760. char *dyn_clk_types[DSI_DYN_CLK_TYPE_MAX] = {
  761. [DSI_DYN_CLK_TYPE_LEGACY] = "none",
  762. [DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP] = "hfp",
  763. [DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP] = "vfp",
  764. };
  765. if (!conn || !display || !drm_mode) {
  766. DSI_ERR("Invalid params\n");
  767. return;
  768. }
  769. convert_to_dsi_mode(drm_mode, &partial_dsi_mode);
  770. mutex_lock(&dsi_display->display_lock);
  771. count = dsi_display->panel->num_display_modes;
  772. for (i = 0; i < count; i++) {
  773. struct dsi_display_mode *dsi_mode = &dsi_display->modes[i];
  774. u32 panel_mode_caps = 0;
  775. const char *topo_name = NULL;
  776. if (!dsi_display_mode_match(&partial_dsi_mode, dsi_mode,
  777. DSI_MODE_MATCH_FULL_TIMINGS))
  778. continue;
  779. sde_kms_info_add_keyint(info, "submode_idx", i);
  780. if (dsi_mode->is_preferred)
  781. preferred_submode_idx = i;
  782. if (dsi_mode->panel_mode_caps & DSI_OP_CMD_MODE)
  783. panel_mode_caps |= DRM_MODE_FLAG_CMD_MODE_PANEL;
  784. if (dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE)
  785. panel_mode_caps |= DRM_MODE_FLAG_VID_MODE_PANEL;
  786. sde_kms_info_add_keyint(info, "panel_mode_capabilities",
  787. panel_mode_caps);
  788. sde_kms_info_add_keyint(info, "dsc_mode",
  789. dsi_mode->priv_info->dsc_enabled ? MSM_DISPLAY_DSC_MODE_ENABLED :
  790. MSM_DISPLAY_DSC_MODE_DISABLED);
  791. topo_name = sde_conn_get_topology_name(conn,
  792. dsi_mode->priv_info->topology);
  793. if (topo_name)
  794. sde_kms_info_add_keystr(info, "topology", topo_name);
  795. if (!dsi_mode->priv_info->bit_clk_list.count)
  796. continue;
  797. dyn_clk_type = dsi_display->panel->dyn_clk_caps.type;
  798. sde_kms_info_add_list(info, "dyn_bitclk_list",
  799. dsi_mode->priv_info->bit_clk_list.rates,
  800. dsi_mode->priv_info->bit_clk_list.count);
  801. sde_kms_info_add_keystr(info, "dyn_fp_type",
  802. dyn_clk_types[dyn_clk_type]);
  803. sde_kms_info_add_list(info, "dyn_fp_list",
  804. dsi_mode->priv_info->bit_clk_list.front_porches,
  805. dsi_mode->priv_info->bit_clk_list.count);
  806. sde_kms_info_add_list(info, "dyn_pclk_list",
  807. dsi_mode->priv_info->bit_clk_list.pixel_clks_khz,
  808. dsi_mode->priv_info->bit_clk_list.count);
  809. }
  810. if (preferred_submode_idx >= 0)
  811. sde_kms_info_add_keyint(info, "preferred_submode_idx",
  812. preferred_submode_idx);
  813. mutex_unlock(&dsi_display->display_lock);
  814. }
  815. enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
  816. bool force,
  817. void *display)
  818. {
  819. enum drm_connector_status status = connector_status_unknown;
  820. struct msm_display_info info;
  821. int rc;
  822. if (!conn || !display)
  823. return status;
  824. /* get display dsi_info */
  825. memset(&info, 0x0, sizeof(info));
  826. rc = dsi_display_get_info(conn, &info, display);
  827. if (rc) {
  828. DSI_ERR("failed to get display info, rc=%d\n", rc);
  829. return connector_status_disconnected;
  830. }
  831. if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
  832. status = (info.is_connected ? connector_status_connected :
  833. connector_status_disconnected);
  834. else
  835. status = connector_status_connected;
  836. conn->display_info.width_mm = info.width_mm;
  837. conn->display_info.height_mm = info.height_mm;
  838. return status;
  839. }
  840. void dsi_connector_put_modes(struct drm_connector *connector,
  841. void *display)
  842. {
  843. struct dsi_display *dsi_display;
  844. int count, i;
  845. if (!connector || !display)
  846. return;
  847. dsi_display = display;
  848. count = dsi_display->panel->num_display_modes;
  849. for (i = 0; i < count; i++) {
  850. struct dsi_display_mode *dsi_mode = &dsi_display->modes[i];
  851. dsi_display_put_mode(dsi_display, dsi_mode);
  852. }
  853. /* free the display structure modes also */
  854. kfree(dsi_display->modes);
  855. dsi_display->modes = NULL;
  856. }
  857. static int dsi_drm_update_edid_name(struct edid *edid, const char *name)
  858. {
  859. u8 *dtd = (u8 *)&edid->detailed_timings[3];
  860. u8 standard_header[] = {0x00, 0x00, 0x00, 0xFE, 0x00};
  861. u32 dtd_size = 18;
  862. u32 header_size = sizeof(standard_header);
  863. if (!name)
  864. return -EINVAL;
  865. /* Fill standard header */
  866. memcpy(dtd, standard_header, header_size);
  867. dtd_size -= header_size;
  868. dtd_size = min_t(u32, dtd_size, strlen(name));
  869. memcpy(dtd + header_size, name, dtd_size);
  870. return 0;
  871. }
  872. static void dsi_drm_update_dtd(struct edid *edid,
  873. struct dsi_display_mode *modes, u32 modes_count)
  874. {
  875. u32 i;
  876. u32 count = min_t(u32, modes_count, 3);
  877. for (i = 0; i < count; i++) {
  878. struct detailed_timing *dtd = &edid->detailed_timings[i];
  879. struct dsi_display_mode *mode = &modes[i];
  880. struct dsi_mode_info *timing = &mode->timing;
  881. struct detailed_pixel_timing *pd = &dtd->data.pixel_data;
  882. u32 h_blank = timing->h_front_porch + timing->h_sync_width +
  883. timing->h_back_porch;
  884. u32 v_blank = timing->v_front_porch + timing->v_sync_width +
  885. timing->v_back_porch;
  886. u32 h_img = 0, v_img = 0;
  887. dtd->pixel_clock = mode->pixel_clk_khz / 10;
  888. pd->hactive_lo = timing->h_active & 0xFF;
  889. pd->hblank_lo = h_blank & 0xFF;
  890. pd->hactive_hblank_hi = ((h_blank >> 8) & 0xF) |
  891. ((timing->h_active >> 8) & 0xF) << 4;
  892. pd->vactive_lo = timing->v_active & 0xFF;
  893. pd->vblank_lo = v_blank & 0xFF;
  894. pd->vactive_vblank_hi = ((v_blank >> 8) & 0xF) |
  895. ((timing->v_active >> 8) & 0xF) << 4;
  896. pd->hsync_offset_lo = timing->h_front_porch & 0xFF;
  897. pd->hsync_pulse_width_lo = timing->h_sync_width & 0xFF;
  898. pd->vsync_offset_pulse_width_lo =
  899. ((timing->v_front_porch & 0xF) << 4) |
  900. (timing->v_sync_width & 0xF);
  901. pd->hsync_vsync_offset_pulse_width_hi =
  902. (((timing->h_front_porch >> 8) & 0x3) << 6) |
  903. (((timing->h_sync_width >> 8) & 0x3) << 4) |
  904. (((timing->v_front_porch >> 4) & 0x3) << 2) |
  905. (((timing->v_sync_width >> 4) & 0x3) << 0);
  906. pd->width_mm_lo = h_img & 0xFF;
  907. pd->height_mm_lo = v_img & 0xFF;
  908. pd->width_height_mm_hi = (((h_img >> 8) & 0xF) << 4) |
  909. ((v_img >> 8) & 0xF);
  910. pd->hborder = 0;
  911. pd->vborder = 0;
  912. pd->misc = 0;
  913. }
  914. }
  915. static void dsi_drm_update_checksum(struct edid *edid)
  916. {
  917. u8 *data = (u8 *)edid;
  918. u32 i, sum = 0;
  919. for (i = 0; i < EDID_LENGTH - 1; i++)
  920. sum += data[i];
  921. edid->checksum = 0x100 - (sum & 0xFF);
  922. }
  923. int dsi_connector_get_modes(struct drm_connector *connector, void *data,
  924. const struct msm_resource_caps_info *avail_res)
  925. {
  926. int rc, i;
  927. u32 count = 0, edid_size;
  928. struct dsi_display_mode *modes = NULL;
  929. struct drm_display_mode drm_mode;
  930. struct dsi_display *display = data;
  931. struct edid edid;
  932. unsigned int width_mm = connector->display_info.width_mm;
  933. unsigned int height_mm = connector->display_info.height_mm;
  934. const u8 edid_buf[EDID_LENGTH] = {
  935. 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x44, 0x6D,
  936. 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1B, 0x10, 0x01, 0x03,
  937. 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47,
  938. 0x98, 0x27, 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  939. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  940. 0x01, 0x01, 0x01, 0x01,
  941. };
  942. edid_size = min_t(u32, sizeof(edid), EDID_LENGTH);
  943. memcpy(&edid, edid_buf, edid_size);
  944. rc = dsi_display_get_mode_count(display, &count);
  945. if (rc) {
  946. DSI_ERR("failed to get num of modes, rc=%d\n", rc);
  947. goto end;
  948. }
  949. rc = dsi_display_get_modes(display, &modes);
  950. if (rc) {
  951. DSI_ERR("failed to get modes, rc=%d\n", rc);
  952. count = 0;
  953. goto end;
  954. }
  955. for (i = 0; i < count; i++) {
  956. struct drm_display_mode *m;
  957. memset(&drm_mode, 0x0, sizeof(drm_mode));
  958. dsi_convert_to_drm_mode(&modes[i], &drm_mode);
  959. m = drm_mode_duplicate(connector->dev, &drm_mode);
  960. if (!m) {
  961. DSI_ERR("failed to add mode %ux%u\n",
  962. drm_mode.hdisplay,
  963. drm_mode.vdisplay);
  964. count = -ENOMEM;
  965. goto end;
  966. }
  967. m->width_mm = connector->display_info.width_mm;
  968. m->height_mm = connector->display_info.height_mm;
  969. if (display->cmdline_timing != NO_OVERRIDE) {
  970. /* get the preferred mode from dsi display mode */
  971. if (modes[i].is_preferred)
  972. m->type |= DRM_MODE_TYPE_PREFERRED;
  973. } else if (modes[i].mode_idx == 0) {
  974. /* set the first mode in device tree list as preferred */
  975. m->type |= DRM_MODE_TYPE_PREFERRED;
  976. }
  977. drm_mode_probed_add(connector, m);
  978. }
  979. rc = dsi_drm_update_edid_name(&edid, display->panel->name);
  980. if (rc) {
  981. count = 0;
  982. goto end;
  983. }
  984. edid.width_cm = (connector->display_info.width_mm) / 10;
  985. edid.height_cm = (connector->display_info.height_mm) / 10;
  986. dsi_drm_update_dtd(&edid, modes, count);
  987. dsi_drm_update_checksum(&edid);
  988. rc = drm_connector_update_edid_property(connector, &edid);
  989. if (rc)
  990. count = 0;
  991. /*
  992. * DRM EDID structure maintains panel physical dimensions in
  993. * centimeters, we will be losing the precision anything below cm.
  994. * Changing DRM framework will effect other clients at this
  995. * moment, overriding the values back to millimeter.
  996. */
  997. connector->display_info.width_mm = width_mm;
  998. connector->display_info.height_mm = height_mm;
  999. end:
  1000. DSI_DEBUG("MODE COUNT =%d\n\n", count);
  1001. return count;
  1002. }
  1003. enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
  1004. struct drm_display_mode *mode,
  1005. void *display, const struct msm_resource_caps_info *avail_res)
  1006. {
  1007. struct dsi_display_mode dsi_mode;
  1008. struct dsi_display_mode *full_dsi_mode = NULL;
  1009. struct sde_connector_state *conn_state;
  1010. int rc;
  1011. if (!connector || !mode) {
  1012. DSI_ERR("Invalid params\n");
  1013. return MODE_ERROR;
  1014. }
  1015. convert_to_dsi_mode(mode, &dsi_mode);
  1016. conn_state = to_sde_connector_state(connector->state);
  1017. if (conn_state)
  1018. msm_parse_mode_priv_info(&conn_state->msm_mode, &dsi_mode);
  1019. rc = dsi_display_find_mode(display, &dsi_mode, NULL, &full_dsi_mode);
  1020. if (rc) {
  1021. DSI_ERR("could not find mode %s\n", mode->name);
  1022. return MODE_ERROR;
  1023. }
  1024. rc = dsi_display_validate_mode(display, full_dsi_mode,
  1025. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  1026. if (rc) {
  1027. DSI_ERR("mode not supported, rc=%d\n", rc);
  1028. return MODE_BAD;
  1029. }
  1030. return MODE_OK;
  1031. }
  1032. int dsi_conn_pre_kickoff(struct drm_connector *connector,
  1033. void *display,
  1034. struct msm_display_kickoff_params *params)
  1035. {
  1036. if (!connector || !display || !params) {
  1037. DSI_ERR("Invalid params\n");
  1038. return -EINVAL;
  1039. }
  1040. return dsi_display_pre_kickoff(connector, display, params);
  1041. }
  1042. int dsi_conn_prepare_commit(void *display,
  1043. struct msm_display_conn_params *params)
  1044. {
  1045. if (!display || !params) {
  1046. pr_err("Invalid params\n");
  1047. return -EINVAL;
  1048. }
  1049. return dsi_display_pre_commit(display, params);
  1050. }
  1051. void dsi_conn_enable_event(struct drm_connector *connector,
  1052. uint32_t event_idx, bool enable, void *display)
  1053. {
  1054. struct dsi_event_cb_info event_info;
  1055. memset(&event_info, 0, sizeof(event_info));
  1056. event_info.event_cb = sde_connector_trigger_event;
  1057. event_info.event_usr_ptr = connector;
  1058. dsi_display_enable_event(connector, display,
  1059. event_idx, &event_info, enable);
  1060. }
  1061. int dsi_conn_post_kickoff(struct drm_connector *connector,
  1062. struct msm_display_conn_params *params)
  1063. {
  1064. struct drm_encoder *encoder;
  1065. struct drm_bridge *bridge;
  1066. struct dsi_bridge *c_bridge;
  1067. struct dsi_display_mode adj_mode;
  1068. struct dsi_display *display;
  1069. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1070. int i, rc = 0, ctrl_version;
  1071. bool enable;
  1072. struct dsi_dyn_clk_caps *dyn_clk_caps;
  1073. if (!connector || !connector->state) {
  1074. DSI_ERR("invalid connector or connector state\n");
  1075. return -EINVAL;
  1076. }
  1077. encoder = connector->state->best_encoder;
  1078. if (!encoder) {
  1079. DSI_DEBUG("best encoder is not available\n");
  1080. return 0;
  1081. }
  1082. bridge = drm_bridge_chain_get_first_bridge(encoder);
  1083. if (!bridge) {
  1084. DSI_DEBUG("bridge is not available\n");
  1085. return 0;
  1086. }
  1087. c_bridge = to_dsi_bridge(bridge);
  1088. adj_mode = c_bridge->dsi_mode;
  1089. display = c_bridge->display;
  1090. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  1091. if (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) {
  1092. m_ctrl = &display->ctrl[display->clk_master_idx];
  1093. ctrl_version = m_ctrl->ctrl->version;
  1094. rc = dsi_ctrl_timing_db_update(m_ctrl->ctrl, false);
  1095. if (rc) {
  1096. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  1097. display->name, rc);
  1098. return -EINVAL;
  1099. }
  1100. /*
  1101. * When both DFPS and dynamic clock switch with constant
  1102. * fps features are enabled, wait for dynamic refresh done
  1103. * only in case of clock switch.
  1104. * In case where only fps changes, clock remains same.
  1105. * So, wait for dynamic refresh done is not required.
  1106. */
  1107. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  1108. (dyn_clk_caps->maintain_const_fps) &&
  1109. (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) {
  1110. display_for_each_ctrl(i, display) {
  1111. ctrl = &display->ctrl[i];
  1112. rc = dsi_ctrl_wait4dynamic_refresh_done(
  1113. ctrl->ctrl);
  1114. if (rc)
  1115. DSI_ERR("wait4dfps refresh failed\n");
  1116. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  1117. dsi_clk_disable_unprepare(&display->clock_info.pll_clks);
  1118. }
  1119. }
  1120. /* Update the rest of the controllers */
  1121. display_for_each_ctrl(i, display) {
  1122. ctrl = &display->ctrl[i];
  1123. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1124. continue;
  1125. rc = dsi_ctrl_timing_db_update(ctrl->ctrl, false);
  1126. if (rc) {
  1127. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  1128. display->name, rc);
  1129. return -EINVAL;
  1130. }
  1131. }
  1132. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR;
  1133. }
  1134. /* ensure dynamic clk switch flag is reset */
  1135. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK;
  1136. if (params->qsync_update) {
  1137. enable = (params->qsync_mode > 0) ? true : false;
  1138. display_for_each_ctrl(i, display)
  1139. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  1140. }
  1141. return 0;
  1142. }
  1143. struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
  1144. struct drm_device *dev,
  1145. struct drm_encoder *encoder)
  1146. {
  1147. int rc = 0;
  1148. struct dsi_bridge *bridge;
  1149. bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
  1150. if (!bridge) {
  1151. rc = -ENOMEM;
  1152. goto error;
  1153. }
  1154. bridge->display = display;
  1155. bridge->base.funcs = &dsi_bridge_ops;
  1156. bridge->base.encoder = encoder;
  1157. rc = drm_bridge_attach(encoder, &bridge->base, NULL, 0);
  1158. if (rc) {
  1159. DSI_ERR("failed to attach bridge, rc=%d\n", rc);
  1160. goto error_free_bridge;
  1161. }
  1162. return bridge;
  1163. error_free_bridge:
  1164. kfree(bridge);
  1165. error:
  1166. return ERR_PTR(rc);
  1167. }
  1168. void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
  1169. {
  1170. kfree(bridge);
  1171. }
  1172. static bool is_valid_poms_switch(struct dsi_display_mode *mode_a,
  1173. struct dsi_display_mode *mode_b)
  1174. {
  1175. /*
  1176. * POMS cannot happen in conjunction with any other type of mode set.
  1177. * Check to ensure FPS remains same between the modes and also
  1178. * resolution.
  1179. */
  1180. return((mode_a->timing.refresh_rate == mode_b->timing.refresh_rate) &&
  1181. (mode_a->timing.v_active == mode_b->timing.v_active) &&
  1182. (mode_a->timing.h_active == mode_b->timing.h_active));
  1183. }
  1184. void dsi_conn_set_allowed_mode_switch(struct drm_connector *connector,
  1185. void *display)
  1186. {
  1187. u32 mode_idx = 0, cmp_mode_idx = 0;
  1188. u32 common_mode_caps = 0;
  1189. struct drm_display_mode *drm_mode, *cmp_drm_mode;
  1190. struct dsi_display_mode dsi_mode, *panel_dsi_mode, *cmp_panel_dsi_mode;
  1191. struct list_head *mode_list = &connector->modes;
  1192. struct dsi_display *disp = display;
  1193. struct dsi_panel *panel;
  1194. int mode_count = 0, rc = 0;
  1195. struct dsi_display_mode_priv_info *dsi_mode_info, *cmp_dsi_mode_info;
  1196. bool allow_switch = false;
  1197. if (!disp || !disp->panel) {
  1198. DSI_ERR("invalid parameters");
  1199. return;
  1200. }
  1201. panel = disp->panel;
  1202. list_for_each_entry(drm_mode, &connector->modes, head)
  1203. mode_count++;
  1204. list_for_each_entry(drm_mode, &connector->modes, head) {
  1205. convert_to_dsi_mode(drm_mode, &dsi_mode);
  1206. rc = dsi_display_find_mode(display, &dsi_mode, NULL, &panel_dsi_mode);
  1207. if (rc)
  1208. return;
  1209. dsi_mode_info = panel_dsi_mode->priv_info;
  1210. dsi_mode_info->allowed_mode_switch |= BIT(mode_idx);
  1211. if (mode_idx == mode_count - 1)
  1212. break;
  1213. mode_list = mode_list->next;
  1214. cmp_mode_idx = 1;
  1215. list_for_each_entry(cmp_drm_mode, mode_list, head) {
  1216. if (&cmp_drm_mode->head == &connector->modes)
  1217. continue;
  1218. convert_to_dsi_mode(cmp_drm_mode, &dsi_mode);
  1219. rc = dsi_display_find_mode(display, &dsi_mode,
  1220. NULL, &cmp_panel_dsi_mode);
  1221. if (rc)
  1222. return;
  1223. cmp_dsi_mode_info = cmp_panel_dsi_mode->priv_info;
  1224. allow_switch = false;
  1225. common_mode_caps = (panel_dsi_mode->panel_mode_caps &
  1226. cmp_panel_dsi_mode->panel_mode_caps);
  1227. /*
  1228. * FPS switch among video modes, is only supported
  1229. * if DFPS or dynamic clocks are specified.
  1230. * Reject any mode switches between video mode timing
  1231. * nodes if support for those features is not present.
  1232. */
  1233. if (common_mode_caps & DSI_OP_CMD_MODE) {
  1234. allow_switch = true;
  1235. } else if ((common_mode_caps & DSI_OP_VIDEO_MODE) &&
  1236. (panel->dfps_caps.dfps_support ||
  1237. panel->dyn_clk_caps.dyn_clk_support)) {
  1238. allow_switch = true;
  1239. } else {
  1240. if (is_valid_poms_switch(panel_dsi_mode,
  1241. cmp_panel_dsi_mode))
  1242. allow_switch = true;
  1243. }
  1244. if (allow_switch) {
  1245. dsi_mode_info->allowed_mode_switch |=
  1246. BIT(mode_idx + cmp_mode_idx);
  1247. cmp_dsi_mode_info->allowed_mode_switch |=
  1248. BIT(mode_idx);
  1249. }
  1250. if ((mode_idx + cmp_mode_idx) >= mode_count - 1)
  1251. break;
  1252. cmp_mode_idx++;
  1253. }
  1254. mode_idx++;
  1255. }
  1256. }
  1257. int dsi_conn_set_dyn_bit_clk(struct drm_connector *connector, uint64_t value)
  1258. {
  1259. struct sde_connector *c_conn = NULL;
  1260. struct dsi_display *display;
  1261. if (!connector) {
  1262. DSI_ERR("invalid connector\n");
  1263. return -EINVAL;
  1264. }
  1265. c_conn = to_sde_connector(connector);
  1266. display = (struct dsi_display *) c_conn->display;
  1267. display->dyn_bit_clk = value;
  1268. display->dyn_bit_clk_pending = true;
  1269. SDE_EVT32(display->dyn_bit_clk);
  1270. DSI_DEBUG("update dynamic bit clock rate to %llu\n", display->dyn_bit_clk);
  1271. return 0;
  1272. }