dp_tx.c 133 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023
  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  44. #include <dp_swlm.h>
  45. #endif
  46. /* Flag to skip CCE classify when mesh or tid override enabled */
  47. #define DP_TX_SKIP_CCE_CLASSIFY \
  48. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  49. /* TODO Add support in TSO */
  50. #define DP_DESC_NUM_FRAG(x) 0
  51. /* disable TQM_BYPASS */
  52. #define TQM_BYPASS_WAR 0
  53. /* invalid peer id for reinject*/
  54. #define DP_INVALID_PEER 0XFFFE
  55. /*mapping between hal encrypt type and cdp_sec_type*/
  56. #define MAX_CDP_SEC_TYPE 12
  57. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  58. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  59. HAL_TX_ENCRYPT_TYPE_WEP_128,
  60. HAL_TX_ENCRYPT_TYPE_WEP_104,
  61. HAL_TX_ENCRYPT_TYPE_WEP_40,
  62. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  63. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_WAPI,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  70. #ifdef QCA_TX_LIMIT_CHECK
  71. /**
  72. * dp_tx_limit_check - Check if allocated tx descriptors reached
  73. * soc max limit and pdev max limit
  74. * @vdev: DP vdev handle
  75. *
  76. * Return: true if allocated tx descriptors reached max configured value, else
  77. * false
  78. */
  79. static inline bool
  80. dp_tx_limit_check(struct dp_vdev *vdev)
  81. {
  82. struct dp_pdev *pdev = vdev->pdev;
  83. struct dp_soc *soc = pdev->soc;
  84. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  85. soc->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  93. pdev->num_tx_allowed) {
  94. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  95. "%s: queued packets are more than max tx, drop the frame",
  96. __func__);
  97. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  98. return true;
  99. }
  100. return false;
  101. }
  102. /**
  103. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  104. * reached soc max limit
  105. * @vdev: DP vdev handle
  106. *
  107. * Return: true if allocated tx descriptors reached max configured value, else
  108. * false
  109. */
  110. static inline bool
  111. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  112. {
  113. struct dp_pdev *pdev = vdev->pdev;
  114. struct dp_soc *soc = pdev->soc;
  115. if (qdf_atomic_read(&soc->num_tx_exception) >=
  116. soc->num_msdu_exception_desc) {
  117. dp_info("exc packets are more than max drop the exc pkt");
  118. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  119. return true;
  120. }
  121. return false;
  122. }
  123. /**
  124. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  125. * @vdev: DP pdev handle
  126. *
  127. * Return: void
  128. */
  129. static inline void
  130. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  131. {
  132. struct dp_soc *soc = pdev->soc;
  133. qdf_atomic_inc(&pdev->num_tx_outstanding);
  134. qdf_atomic_inc(&soc->num_tx_outstanding);
  135. }
  136. /**
  137. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  138. * @vdev: DP pdev handle
  139. *
  140. * Return: void
  141. */
  142. static inline void
  143. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  144. {
  145. struct dp_soc *soc = pdev->soc;
  146. qdf_atomic_dec(&pdev->num_tx_outstanding);
  147. qdf_atomic_dec(&soc->num_tx_outstanding);
  148. }
  149. #else //QCA_TX_LIMIT_CHECK
  150. static inline bool
  151. dp_tx_limit_check(struct dp_vdev *vdev)
  152. {
  153. return false;
  154. }
  155. static inline bool
  156. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  157. {
  158. return false;
  159. }
  160. static inline void
  161. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  162. {
  163. qdf_atomic_inc(&pdev->num_tx_outstanding);
  164. }
  165. static inline void
  166. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  167. {
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. }
  170. #endif //QCA_TX_LIMIT_CHECK
  171. #if defined(FEATURE_TSO)
  172. /**
  173. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  174. *
  175. * @soc - core txrx main context
  176. * @seg_desc - tso segment descriptor
  177. * @num_seg_desc - tso number segment descriptor
  178. */
  179. static void dp_tx_tso_unmap_segment(
  180. struct dp_soc *soc,
  181. struct qdf_tso_seg_elem_t *seg_desc,
  182. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  183. {
  184. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  185. if (qdf_unlikely(!seg_desc)) {
  186. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  187. __func__, __LINE__);
  188. qdf_assert(0);
  189. } else if (qdf_unlikely(!num_seg_desc)) {
  190. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  191. __func__, __LINE__);
  192. qdf_assert(0);
  193. } else {
  194. bool is_last_seg;
  195. /* no tso segment left to do dma unmap */
  196. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  197. return;
  198. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  199. true : false;
  200. qdf_nbuf_unmap_tso_segment(soc->osdev,
  201. seg_desc, is_last_seg);
  202. num_seg_desc->num_seg.tso_cmn_num_seg--;
  203. }
  204. }
  205. /**
  206. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  207. * back to the freelist
  208. *
  209. * @soc - soc device handle
  210. * @tx_desc - Tx software descriptor
  211. */
  212. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  213. struct dp_tx_desc_s *tx_desc)
  214. {
  215. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  216. if (qdf_unlikely(!tx_desc->tso_desc)) {
  217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  218. "%s %d TSO desc is NULL!",
  219. __func__, __LINE__);
  220. qdf_assert(0);
  221. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  222. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  223. "%s %d TSO num desc is NULL!",
  224. __func__, __LINE__);
  225. qdf_assert(0);
  226. } else {
  227. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  228. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  229. /* Add the tso num segment into the free list */
  230. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  231. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  232. tx_desc->tso_num_desc);
  233. tx_desc->tso_num_desc = NULL;
  234. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  235. }
  236. /* Add the tso segment into the free list*/
  237. dp_tx_tso_desc_free(soc,
  238. tx_desc->pool_id, tx_desc->tso_desc);
  239. tx_desc->tso_desc = NULL;
  240. }
  241. }
  242. #else
  243. static void dp_tx_tso_unmap_segment(
  244. struct dp_soc *soc,
  245. struct qdf_tso_seg_elem_t *seg_desc,
  246. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  247. {
  248. }
  249. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  250. struct dp_tx_desc_s *tx_desc)
  251. {
  252. }
  253. #endif
  254. /**
  255. * dp_tx_desc_release() - Release Tx Descriptor
  256. * @tx_desc : Tx Descriptor
  257. * @desc_pool_id: Descriptor Pool ID
  258. *
  259. * Deallocate all resources attached to Tx descriptor and free the Tx
  260. * descriptor.
  261. *
  262. * Return:
  263. */
  264. static void
  265. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  266. {
  267. struct dp_pdev *pdev = tx_desc->pdev;
  268. struct dp_soc *soc;
  269. uint8_t comp_status = 0;
  270. qdf_assert(pdev);
  271. soc = pdev->soc;
  272. dp_tx_outstanding_dec(pdev);
  273. if (tx_desc->frm_type == dp_tx_frm_tso)
  274. dp_tx_tso_desc_release(soc, tx_desc);
  275. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  276. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  277. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  278. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  279. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  280. qdf_atomic_dec(&soc->num_tx_exception);
  281. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  282. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  283. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  284. soc->hal_soc);
  285. else
  286. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  287. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  288. "Tx Completion Release desc %d status %d outstanding %d",
  289. tx_desc->id, comp_status,
  290. qdf_atomic_read(&pdev->num_tx_outstanding));
  291. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  292. return;
  293. }
  294. /**
  295. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  296. * @vdev: DP vdev Handle
  297. * @nbuf: skb
  298. * @msdu_info: msdu_info required to create HTT metadata
  299. *
  300. * Prepares and fills HTT metadata in the frame pre-header for special frames
  301. * that should be transmitted using varying transmit parameters.
  302. * There are 2 VDEV modes that currently needs this special metadata -
  303. * 1) Mesh Mode
  304. * 2) DSRC Mode
  305. *
  306. * Return: HTT metadata size
  307. *
  308. */
  309. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  310. struct dp_tx_msdu_info_s *msdu_info)
  311. {
  312. uint32_t *meta_data = msdu_info->meta_data;
  313. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  314. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  315. uint8_t htt_desc_size;
  316. /* Size rounded of multiple of 8 bytes */
  317. uint8_t htt_desc_size_aligned;
  318. uint8_t *hdr = NULL;
  319. /*
  320. * Metadata - HTT MSDU Extension header
  321. */
  322. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  323. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  324. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  325. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  326. meta_data[0])) {
  327. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  328. htt_desc_size_aligned)) {
  329. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  330. htt_desc_size_aligned);
  331. if (!nbuf) {
  332. /*
  333. * qdf_nbuf_realloc_headroom won't do skb_clone
  334. * as skb_realloc_headroom does. so, no free is
  335. * needed here.
  336. */
  337. DP_STATS_INC(vdev,
  338. tx_i.dropped.headroom_insufficient,
  339. 1);
  340. qdf_print(" %s[%d] skb_realloc_headroom failed",
  341. __func__, __LINE__);
  342. return 0;
  343. }
  344. }
  345. /* Fill and add HTT metaheader */
  346. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  347. if (!hdr) {
  348. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  349. "Error in filling HTT metadata");
  350. return 0;
  351. }
  352. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  353. } else if (vdev->opmode == wlan_op_mode_ocb) {
  354. /* Todo - Add support for DSRC */
  355. }
  356. return htt_desc_size_aligned;
  357. }
  358. /**
  359. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  360. * @tso_seg: TSO segment to process
  361. * @ext_desc: Pointer to MSDU extension descriptor
  362. *
  363. * Return: void
  364. */
  365. #if defined(FEATURE_TSO)
  366. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  367. void *ext_desc)
  368. {
  369. uint8_t num_frag;
  370. uint32_t tso_flags;
  371. /*
  372. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  373. * tcp_flag_mask
  374. *
  375. * Checksum enable flags are set in TCL descriptor and not in Extension
  376. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  377. */
  378. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  379. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  380. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  381. tso_seg->tso_flags.ip_len);
  382. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  383. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  384. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  385. uint32_t lo = 0;
  386. uint32_t hi = 0;
  387. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  388. (tso_seg->tso_frags[num_frag].length));
  389. qdf_dmaaddr_to_32s(
  390. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  391. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  392. tso_seg->tso_frags[num_frag].length);
  393. }
  394. return;
  395. }
  396. #else
  397. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  398. void *ext_desc)
  399. {
  400. return;
  401. }
  402. #endif
  403. #if defined(FEATURE_TSO)
  404. /**
  405. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  406. * allocated and free them
  407. *
  408. * @soc: soc handle
  409. * @free_seg: list of tso segments
  410. * @msdu_info: msdu descriptor
  411. *
  412. * Return - void
  413. */
  414. static void dp_tx_free_tso_seg_list(
  415. struct dp_soc *soc,
  416. struct qdf_tso_seg_elem_t *free_seg,
  417. struct dp_tx_msdu_info_s *msdu_info)
  418. {
  419. struct qdf_tso_seg_elem_t *next_seg;
  420. while (free_seg) {
  421. next_seg = free_seg->next;
  422. dp_tx_tso_desc_free(soc,
  423. msdu_info->tx_queue.desc_pool_id,
  424. free_seg);
  425. free_seg = next_seg;
  426. }
  427. }
  428. /**
  429. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  430. * allocated and free them
  431. *
  432. * @soc: soc handle
  433. * @free_num_seg: list of tso number segments
  434. * @msdu_info: msdu descriptor
  435. * Return - void
  436. */
  437. static void dp_tx_free_tso_num_seg_list(
  438. struct dp_soc *soc,
  439. struct qdf_tso_num_seg_elem_t *free_num_seg,
  440. struct dp_tx_msdu_info_s *msdu_info)
  441. {
  442. struct qdf_tso_num_seg_elem_t *next_num_seg;
  443. while (free_num_seg) {
  444. next_num_seg = free_num_seg->next;
  445. dp_tso_num_seg_free(soc,
  446. msdu_info->tx_queue.desc_pool_id,
  447. free_num_seg);
  448. free_num_seg = next_num_seg;
  449. }
  450. }
  451. /**
  452. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  453. * do dma unmap for each segment
  454. *
  455. * @soc: soc handle
  456. * @free_seg: list of tso segments
  457. * @num_seg_desc: tso number segment descriptor
  458. *
  459. * Return - void
  460. */
  461. static void dp_tx_unmap_tso_seg_list(
  462. struct dp_soc *soc,
  463. struct qdf_tso_seg_elem_t *free_seg,
  464. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  465. {
  466. struct qdf_tso_seg_elem_t *next_seg;
  467. if (qdf_unlikely(!num_seg_desc)) {
  468. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  469. return;
  470. }
  471. while (free_seg) {
  472. next_seg = free_seg->next;
  473. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  474. free_seg = next_seg;
  475. }
  476. }
  477. #ifdef FEATURE_TSO_STATS
  478. /**
  479. * dp_tso_get_stats_idx: Retrieve the tso packet id
  480. * @pdev - pdev handle
  481. *
  482. * Return: id
  483. */
  484. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  485. {
  486. uint32_t stats_idx;
  487. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  488. % CDP_MAX_TSO_PACKETS);
  489. return stats_idx;
  490. }
  491. #else
  492. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  493. {
  494. return 0;
  495. }
  496. #endif /* FEATURE_TSO_STATS */
  497. /**
  498. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  499. * free the tso segments descriptor and
  500. * tso num segments descriptor
  501. *
  502. * @soc: soc handle
  503. * @msdu_info: msdu descriptor
  504. * @tso_seg_unmap: flag to show if dma unmap is necessary
  505. *
  506. * Return - void
  507. */
  508. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  509. struct dp_tx_msdu_info_s *msdu_info,
  510. bool tso_seg_unmap)
  511. {
  512. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  513. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  514. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  515. tso_info->tso_num_seg_list;
  516. /* do dma unmap for each segment */
  517. if (tso_seg_unmap)
  518. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  519. /* free all tso number segment descriptor though looks only have 1 */
  520. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  521. /* free all tso segment descriptor */
  522. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  523. }
  524. /**
  525. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  526. * @vdev: virtual device handle
  527. * @msdu: network buffer
  528. * @msdu_info: meta data associated with the msdu
  529. *
  530. * Return: QDF_STATUS_SUCCESS success
  531. */
  532. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  533. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  534. {
  535. struct qdf_tso_seg_elem_t *tso_seg;
  536. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  537. struct dp_soc *soc = vdev->pdev->soc;
  538. struct dp_pdev *pdev = vdev->pdev;
  539. struct qdf_tso_info_t *tso_info;
  540. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  541. tso_info = &msdu_info->u.tso_info;
  542. tso_info->curr_seg = NULL;
  543. tso_info->tso_seg_list = NULL;
  544. tso_info->num_segs = num_seg;
  545. msdu_info->frm_type = dp_tx_frm_tso;
  546. tso_info->tso_num_seg_list = NULL;
  547. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  548. while (num_seg) {
  549. tso_seg = dp_tx_tso_desc_alloc(
  550. soc, msdu_info->tx_queue.desc_pool_id);
  551. if (tso_seg) {
  552. tso_seg->next = tso_info->tso_seg_list;
  553. tso_info->tso_seg_list = tso_seg;
  554. num_seg--;
  555. } else {
  556. dp_err_rl("Failed to alloc tso seg desc");
  557. DP_STATS_INC_PKT(vdev->pdev,
  558. tso_stats.tso_no_mem_dropped, 1,
  559. qdf_nbuf_len(msdu));
  560. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  561. return QDF_STATUS_E_NOMEM;
  562. }
  563. }
  564. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  565. tso_num_seg = dp_tso_num_seg_alloc(soc,
  566. msdu_info->tx_queue.desc_pool_id);
  567. if (tso_num_seg) {
  568. tso_num_seg->next = tso_info->tso_num_seg_list;
  569. tso_info->tso_num_seg_list = tso_num_seg;
  570. } else {
  571. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  572. __func__);
  573. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  574. return QDF_STATUS_E_NOMEM;
  575. }
  576. msdu_info->num_seg =
  577. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  578. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  579. msdu_info->num_seg);
  580. if (!(msdu_info->num_seg)) {
  581. /*
  582. * Free allocated TSO seg desc and number seg desc,
  583. * do unmap for segments if dma map has done.
  584. */
  585. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  586. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  587. return QDF_STATUS_E_INVAL;
  588. }
  589. tso_info->curr_seg = tso_info->tso_seg_list;
  590. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  591. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  592. msdu, msdu_info->num_seg);
  593. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  594. tso_info->msdu_stats_idx);
  595. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  596. return QDF_STATUS_SUCCESS;
  597. }
  598. #else
  599. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  600. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  601. {
  602. return QDF_STATUS_E_NOMEM;
  603. }
  604. #endif
  605. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  606. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  607. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  608. /**
  609. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  610. * @vdev: DP Vdev handle
  611. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  612. * @desc_pool_id: Descriptor Pool ID
  613. *
  614. * Return:
  615. */
  616. static
  617. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  618. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  619. {
  620. uint8_t i;
  621. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  622. struct dp_tx_seg_info_s *seg_info;
  623. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  624. struct dp_soc *soc = vdev->pdev->soc;
  625. /* Allocate an extension descriptor */
  626. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  627. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  628. if (!msdu_ext_desc) {
  629. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  630. return NULL;
  631. }
  632. if (msdu_info->exception_fw &&
  633. qdf_unlikely(vdev->mesh_vdev)) {
  634. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  635. &msdu_info->meta_data[0],
  636. sizeof(struct htt_tx_msdu_desc_ext2_t));
  637. qdf_atomic_inc(&soc->num_tx_exception);
  638. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  639. }
  640. switch (msdu_info->frm_type) {
  641. case dp_tx_frm_sg:
  642. case dp_tx_frm_me:
  643. case dp_tx_frm_raw:
  644. seg_info = msdu_info->u.sg_info.curr_seg;
  645. /* Update the buffer pointers in MSDU Extension Descriptor */
  646. for (i = 0; i < seg_info->frag_cnt; i++) {
  647. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  648. seg_info->frags[i].paddr_lo,
  649. seg_info->frags[i].paddr_hi,
  650. seg_info->frags[i].len);
  651. }
  652. break;
  653. case dp_tx_frm_tso:
  654. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  655. &cached_ext_desc[0]);
  656. break;
  657. default:
  658. break;
  659. }
  660. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  661. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  662. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  663. msdu_ext_desc->vaddr);
  664. return msdu_ext_desc;
  665. }
  666. /**
  667. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  668. *
  669. * @skb: skb to be traced
  670. * @msdu_id: msdu_id of the packet
  671. * @vdev_id: vdev_id of the packet
  672. *
  673. * Return: None
  674. */
  675. #ifdef DP_DISABLE_TX_PKT_TRACE
  676. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  677. uint8_t vdev_id)
  678. {
  679. }
  680. #else
  681. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  682. uint8_t vdev_id)
  683. {
  684. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  685. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  686. DPTRACE(qdf_dp_trace_ptr(skb,
  687. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  688. QDF_TRACE_DEFAULT_PDEV_ID,
  689. qdf_nbuf_data_addr(skb),
  690. sizeof(qdf_nbuf_data(skb)),
  691. msdu_id, vdev_id));
  692. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  693. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  694. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  695. msdu_id, QDF_TX));
  696. }
  697. #endif
  698. /**
  699. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  700. * @vdev: DP vdev handle
  701. * @nbuf: skb
  702. * @desc_pool_id: Descriptor pool ID
  703. * @meta_data: Metadata to the fw
  704. * @tx_exc_metadata: Handle that holds exception path metadata
  705. * Allocate and prepare Tx descriptor with msdu information.
  706. *
  707. * Return: Pointer to Tx Descriptor on success,
  708. * NULL on failure
  709. */
  710. static
  711. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  712. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  713. struct dp_tx_msdu_info_s *msdu_info,
  714. struct cdp_tx_exception_metadata *tx_exc_metadata)
  715. {
  716. uint8_t align_pad;
  717. uint8_t is_exception = 0;
  718. uint8_t htt_hdr_size;
  719. struct dp_tx_desc_s *tx_desc;
  720. struct dp_pdev *pdev = vdev->pdev;
  721. struct dp_soc *soc = pdev->soc;
  722. if (dp_tx_limit_check(vdev))
  723. return NULL;
  724. /* Allocate software Tx descriptor */
  725. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  726. if (qdf_unlikely(!tx_desc)) {
  727. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  728. return NULL;
  729. }
  730. dp_tx_outstanding_inc(pdev);
  731. /* Initialize the SW tx descriptor */
  732. tx_desc->nbuf = nbuf;
  733. tx_desc->frm_type = dp_tx_frm_std;
  734. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  735. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  736. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  737. tx_desc->vdev_id = vdev->vdev_id;
  738. tx_desc->pdev = pdev;
  739. tx_desc->msdu_ext_desc = NULL;
  740. tx_desc->pkt_offset = 0;
  741. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  742. if (qdf_unlikely(vdev->multipass_en)) {
  743. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  744. goto failure;
  745. }
  746. /*
  747. * For special modes (vdev_type == ocb or mesh), data frames should be
  748. * transmitted using varying transmit parameters (tx spec) which include
  749. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  750. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  751. * These frames are sent as exception packets to firmware.
  752. *
  753. * HW requirement is that metadata should always point to a
  754. * 8-byte aligned address. So we add alignment pad to start of buffer.
  755. * HTT Metadata should be ensured to be multiple of 8-bytes,
  756. * to get 8-byte aligned start address along with align_pad added
  757. *
  758. * |-----------------------------|
  759. * | |
  760. * |-----------------------------| <-----Buffer Pointer Address given
  761. * | | ^ in HW descriptor (aligned)
  762. * | HTT Metadata | |
  763. * | | |
  764. * | | | Packet Offset given in descriptor
  765. * | | |
  766. * |-----------------------------| |
  767. * | Alignment Pad | v
  768. * |-----------------------------| <----- Actual buffer start address
  769. * | SKB Data | (Unaligned)
  770. * | |
  771. * | |
  772. * | |
  773. * | |
  774. * | |
  775. * |-----------------------------|
  776. */
  777. if (qdf_unlikely((msdu_info->exception_fw)) ||
  778. (vdev->opmode == wlan_op_mode_ocb) ||
  779. (tx_exc_metadata &&
  780. tx_exc_metadata->is_tx_sniffer)) {
  781. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  782. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  783. DP_STATS_INC(vdev,
  784. tx_i.dropped.headroom_insufficient, 1);
  785. goto failure;
  786. }
  787. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  788. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  789. "qdf_nbuf_push_head failed");
  790. goto failure;
  791. }
  792. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  793. msdu_info);
  794. if (htt_hdr_size == 0)
  795. goto failure;
  796. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  797. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  798. is_exception = 1;
  799. }
  800. #if !TQM_BYPASS_WAR
  801. if (is_exception || tx_exc_metadata)
  802. #endif
  803. {
  804. /* Temporary WAR due to TQM VP issues */
  805. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  806. qdf_atomic_inc(&soc->num_tx_exception);
  807. }
  808. return tx_desc;
  809. failure:
  810. dp_tx_desc_release(tx_desc, desc_pool_id);
  811. return NULL;
  812. }
  813. /**
  814. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  815. * @vdev: DP vdev handle
  816. * @nbuf: skb
  817. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  818. * @desc_pool_id : Descriptor Pool ID
  819. *
  820. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  821. * information. For frames wth fragments, allocate and prepare
  822. * an MSDU extension descriptor
  823. *
  824. * Return: Pointer to Tx Descriptor on success,
  825. * NULL on failure
  826. */
  827. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  828. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  829. uint8_t desc_pool_id)
  830. {
  831. struct dp_tx_desc_s *tx_desc;
  832. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  833. struct dp_pdev *pdev = vdev->pdev;
  834. struct dp_soc *soc = pdev->soc;
  835. if (dp_tx_limit_check(vdev))
  836. return NULL;
  837. /* Allocate software Tx descriptor */
  838. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  839. if (!tx_desc) {
  840. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  841. return NULL;
  842. }
  843. dp_tx_outstanding_inc(pdev);
  844. /* Initialize the SW tx descriptor */
  845. tx_desc->nbuf = nbuf;
  846. tx_desc->frm_type = msdu_info->frm_type;
  847. tx_desc->tx_encap_type = vdev->tx_encap_type;
  848. tx_desc->vdev_id = vdev->vdev_id;
  849. tx_desc->pdev = pdev;
  850. tx_desc->pkt_offset = 0;
  851. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  852. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  853. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  854. /* Handle scattered frames - TSO/SG/ME */
  855. /* Allocate and prepare an extension descriptor for scattered frames */
  856. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  857. if (!msdu_ext_desc) {
  858. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  859. "%s Tx Extension Descriptor Alloc Fail",
  860. __func__);
  861. goto failure;
  862. }
  863. #if TQM_BYPASS_WAR
  864. /* Temporary WAR due to TQM VP issues */
  865. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  866. qdf_atomic_inc(&soc->num_tx_exception);
  867. #endif
  868. if (qdf_unlikely(msdu_info->exception_fw))
  869. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  870. tx_desc->msdu_ext_desc = msdu_ext_desc;
  871. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  872. return tx_desc;
  873. failure:
  874. dp_tx_desc_release(tx_desc, desc_pool_id);
  875. return NULL;
  876. }
  877. /**
  878. * dp_tx_prepare_raw() - Prepare RAW packet TX
  879. * @vdev: DP vdev handle
  880. * @nbuf: buffer pointer
  881. * @seg_info: Pointer to Segment info Descriptor to be prepared
  882. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  883. * descriptor
  884. *
  885. * Return:
  886. */
  887. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  888. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  889. {
  890. qdf_nbuf_t curr_nbuf = NULL;
  891. uint16_t total_len = 0;
  892. qdf_dma_addr_t paddr;
  893. int32_t i;
  894. int32_t mapped_buf_num = 0;
  895. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  896. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  897. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  898. /* Continue only if frames are of DATA type */
  899. if (!DP_FRAME_IS_DATA(qos_wh)) {
  900. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  901. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  902. "Pkt. recd is of not data type");
  903. goto error;
  904. }
  905. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  906. if (vdev->raw_mode_war &&
  907. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  908. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  909. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  910. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  911. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  912. if (QDF_STATUS_SUCCESS !=
  913. qdf_nbuf_map_nbytes_single(vdev->osdev,
  914. curr_nbuf,
  915. QDF_DMA_TO_DEVICE,
  916. curr_nbuf->len)) {
  917. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  918. "%s dma map error ", __func__);
  919. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  920. mapped_buf_num = i;
  921. goto error;
  922. }
  923. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  924. seg_info->frags[i].paddr_lo = paddr;
  925. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  926. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  927. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  928. total_len += qdf_nbuf_len(curr_nbuf);
  929. }
  930. seg_info->frag_cnt = i;
  931. seg_info->total_len = total_len;
  932. seg_info->next = NULL;
  933. sg_info->curr_seg = seg_info;
  934. msdu_info->frm_type = dp_tx_frm_raw;
  935. msdu_info->num_seg = 1;
  936. return nbuf;
  937. error:
  938. i = 0;
  939. while (nbuf) {
  940. curr_nbuf = nbuf;
  941. if (i < mapped_buf_num) {
  942. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  943. QDF_DMA_TO_DEVICE,
  944. curr_nbuf->len);
  945. i++;
  946. }
  947. nbuf = qdf_nbuf_next(nbuf);
  948. qdf_nbuf_free(curr_nbuf);
  949. }
  950. return NULL;
  951. }
  952. /**
  953. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  954. * @soc: DP soc handle
  955. * @nbuf: Buffer pointer
  956. *
  957. * unmap the chain of nbufs that belong to this RAW frame.
  958. *
  959. * Return: None
  960. */
  961. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  962. qdf_nbuf_t nbuf)
  963. {
  964. qdf_nbuf_t cur_nbuf = nbuf;
  965. do {
  966. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  967. QDF_DMA_TO_DEVICE,
  968. cur_nbuf->len);
  969. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  970. } while (cur_nbuf);
  971. }
  972. #ifdef VDEV_PEER_PROTOCOL_COUNT
  973. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  974. { \
  975. qdf_nbuf_t nbuf_local; \
  976. struct dp_vdev *vdev_local = vdev_hdl; \
  977. do { \
  978. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  979. break; \
  980. nbuf_local = nbuf; \
  981. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  982. htt_cmn_pkt_type_raw)) \
  983. break; \
  984. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  985. break; \
  986. else if (qdf_nbuf_is_tso((nbuf_local))) \
  987. break; \
  988. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  989. (nbuf_local), \
  990. NULL, 1, 0); \
  991. } while (0); \
  992. }
  993. #else
  994. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  995. #endif
  996. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  997. /**
  998. * dp_tx_update_stats() - Update soc level tx stats
  999. * @soc: DP soc handle
  1000. * @nbuf: packet being transmitted
  1001. *
  1002. * Returns: none
  1003. */
  1004. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1005. qdf_nbuf_t nbuf)
  1006. {
  1007. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1008. }
  1009. /**
  1010. * dp_tx_attempt_coalescing() - Check and attempt TCL register write coalescing
  1011. * @soc: Datapath soc handle
  1012. * @tx_desc: tx packet descriptor
  1013. * @tid: TID for pkt transmission
  1014. *
  1015. * Returns: 1, if coalescing is to be done
  1016. * 0, if coalescing is not to be done
  1017. */
  1018. static inline int
  1019. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1020. struct dp_tx_desc_s *tx_desc,
  1021. uint8_t tid)
  1022. {
  1023. struct dp_swlm *swlm = &soc->swlm;
  1024. union swlm_data swlm_query_data;
  1025. struct dp_swlm_tcl_data tcl_data;
  1026. QDF_STATUS status;
  1027. int ret;
  1028. if (qdf_unlikely(!swlm->is_enabled))
  1029. return 0;
  1030. tcl_data.nbuf = tx_desc->nbuf;
  1031. tcl_data.tid = tid;
  1032. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1033. swlm_query_data.tcl_data = &tcl_data;
  1034. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1035. if (QDF_IS_STATUS_ERROR(status)) {
  1036. dp_swlm_tcl_reset_session_data(soc);
  1037. return 0;
  1038. }
  1039. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1040. if (ret) {
  1041. DP_STATS_INC(swlm, tcl.coalesc_success, 1);
  1042. } else {
  1043. DP_STATS_INC(swlm, tcl.coalesc_fail, 1);
  1044. }
  1045. return ret;
  1046. }
  1047. /**
  1048. * dp_tx_ring_access_end() - HAL ring access end for data transmission
  1049. * @soc: Datapath soc handle
  1050. * @hal_ring_hdl: HAL ring handle
  1051. * @coalesc: Coalesc the current write or not
  1052. *
  1053. * Returns: none
  1054. */
  1055. static inline void
  1056. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1057. int coalesc)
  1058. {
  1059. if (coalesc)
  1060. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1061. else
  1062. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1063. }
  1064. #else
  1065. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1066. qdf_nbuf_t nbuf)
  1067. {
  1068. }
  1069. static inline int
  1070. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1071. struct dp_tx_desc_s *tx_desc,
  1072. uint8_t tid)
  1073. {
  1074. return 0;
  1075. }
  1076. static inline void
  1077. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1078. int coalesc)
  1079. {
  1080. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1081. }
  1082. #endif
  1083. /**
  1084. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1085. * @soc: DP Soc Handle
  1086. * @vdev: DP vdev handle
  1087. * @tx_desc: Tx Descriptor Handle
  1088. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1089. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1090. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1091. * @tx_exc_metadata: Handle that holds exception path meta data
  1092. *
  1093. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1094. * from software Tx descriptor
  1095. *
  1096. * Return: QDF_STATUS_SUCCESS: success
  1097. * QDF_STATUS_E_RESOURCES: Error return
  1098. */
  1099. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1100. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  1101. uint16_t fw_metadata, uint8_t ring_id,
  1102. struct cdp_tx_exception_metadata
  1103. *tx_exc_metadata)
  1104. {
  1105. uint8_t type;
  1106. void *hal_tx_desc;
  1107. uint32_t *hal_tx_desc_cached;
  1108. int coalesc = 0;
  1109. /*
  1110. * Setting it initialization statically here to avoid
  1111. * a memset call jump with qdf_mem_set call
  1112. */
  1113. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1114. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1115. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1116. tx_exc_metadata->sec_type : vdev->sec_type);
  1117. /* Return Buffer Manager ID */
  1118. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1119. hal_ring_handle_t hal_ring_hdl = NULL;
  1120. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1121. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1122. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1123. return QDF_STATUS_E_RESOURCES;
  1124. }
  1125. hal_tx_desc_cached = (void *) cached_desc;
  1126. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1127. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1128. tx_desc->dma_addr = tx_desc->msdu_ext_desc->paddr;
  1129. if (tx_desc->msdu_ext_desc->flags &
  1130. DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1131. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1132. else
  1133. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1134. } else {
  1135. tx_desc->length = qdf_nbuf_len(tx_desc->nbuf) -
  1136. tx_desc->pkt_offset;
  1137. type = HAL_TX_BUF_TYPE_BUFFER;
  1138. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1139. }
  1140. qdf_assert_always(tx_desc->dma_addr);
  1141. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1142. tx_desc->dma_addr, bm_id, tx_desc->id,
  1143. type);
  1144. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1145. vdev->lmac_id);
  1146. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1147. vdev->search_type);
  1148. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1149. vdev->bss_ast_idx);
  1150. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1151. vdev->dscp_tid_map_id);
  1152. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1153. sec_type_map[sec_type]);
  1154. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1155. (vdev->bss_ast_hash & 0xF));
  1156. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1157. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1158. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1159. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1160. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1161. vdev->hal_desc_addr_search_flags);
  1162. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1163. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1164. /* verify checksum offload configuration*/
  1165. if (vdev->csum_enabled &&
  1166. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1167. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1168. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1169. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1170. }
  1171. if (tid != HTT_TX_EXT_TID_INVALID)
  1172. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1173. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1174. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1175. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1176. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1177. soc->wlan_cfg_ctx)))
  1178. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1179. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1180. tx_desc->length, type, (uint64_t)tx_desc->dma_addr,
  1181. tx_desc->pkt_offset, tx_desc->id);
  1182. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1183. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1184. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1185. "%s %d : HAL RING Access Failed -- %pK",
  1186. __func__, __LINE__, hal_ring_hdl);
  1187. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1188. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1189. return status;
  1190. }
  1191. /* Sync cached descriptor with HW */
  1192. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1193. if (qdf_unlikely(!hal_tx_desc)) {
  1194. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1195. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1196. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1197. goto ring_access_fail;
  1198. }
  1199. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1200. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1201. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1202. coalesc = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
  1203. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1204. dp_tx_update_stats(soc, tx_desc->nbuf);
  1205. status = QDF_STATUS_SUCCESS;
  1206. ring_access_fail:
  1207. if (hif_pm_runtime_get(soc->hif_handle,
  1208. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1209. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesc);
  1210. hif_pm_runtime_put(soc->hif_handle,
  1211. RTPM_ID_DW_TX_HW_ENQUEUE);
  1212. } else {
  1213. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1214. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1215. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1216. }
  1217. return status;
  1218. }
  1219. /**
  1220. * dp_cce_classify() - Classify the frame based on CCE rules
  1221. * @vdev: DP vdev handle
  1222. * @nbuf: skb
  1223. *
  1224. * Classify frames based on CCE rules
  1225. * Return: bool( true if classified,
  1226. * else false)
  1227. */
  1228. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1229. {
  1230. qdf_ether_header_t *eh = NULL;
  1231. uint16_t ether_type;
  1232. qdf_llc_t *llcHdr;
  1233. qdf_nbuf_t nbuf_clone = NULL;
  1234. qdf_dot3_qosframe_t *qos_wh = NULL;
  1235. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1236. /*
  1237. * In case of mesh packets or hlos tid override enabled,
  1238. * don't do any classification
  1239. */
  1240. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1241. & DP_TX_SKIP_CCE_CLASSIFY))
  1242. return false;
  1243. }
  1244. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1245. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1246. ether_type = eh->ether_type;
  1247. llcHdr = (qdf_llc_t *)(nbuf->data +
  1248. sizeof(qdf_ether_header_t));
  1249. } else {
  1250. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1251. /* For encrypted packets don't do any classification */
  1252. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1253. return false;
  1254. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1255. if (qdf_unlikely(
  1256. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1257. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1258. ether_type = *(uint16_t *)(nbuf->data
  1259. + QDF_IEEE80211_4ADDR_HDR_LEN
  1260. + sizeof(qdf_llc_t)
  1261. - sizeof(ether_type));
  1262. llcHdr = (qdf_llc_t *)(nbuf->data +
  1263. QDF_IEEE80211_4ADDR_HDR_LEN);
  1264. } else {
  1265. ether_type = *(uint16_t *)(nbuf->data
  1266. + QDF_IEEE80211_3ADDR_HDR_LEN
  1267. + sizeof(qdf_llc_t)
  1268. - sizeof(ether_type));
  1269. llcHdr = (qdf_llc_t *)(nbuf->data +
  1270. QDF_IEEE80211_3ADDR_HDR_LEN);
  1271. }
  1272. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1273. && (ether_type ==
  1274. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1275. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1276. return true;
  1277. }
  1278. }
  1279. return false;
  1280. }
  1281. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1282. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1283. sizeof(*llcHdr));
  1284. nbuf_clone = qdf_nbuf_clone(nbuf);
  1285. if (qdf_unlikely(nbuf_clone)) {
  1286. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1287. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1288. qdf_nbuf_pull_head(nbuf_clone,
  1289. sizeof(qdf_net_vlanhdr_t));
  1290. }
  1291. }
  1292. } else {
  1293. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1294. nbuf_clone = qdf_nbuf_clone(nbuf);
  1295. if (qdf_unlikely(nbuf_clone)) {
  1296. qdf_nbuf_pull_head(nbuf_clone,
  1297. sizeof(qdf_net_vlanhdr_t));
  1298. }
  1299. }
  1300. }
  1301. if (qdf_unlikely(nbuf_clone))
  1302. nbuf = nbuf_clone;
  1303. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1304. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1305. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1306. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1307. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1308. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1309. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1310. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1311. if (qdf_unlikely(nbuf_clone))
  1312. qdf_nbuf_free(nbuf_clone);
  1313. return true;
  1314. }
  1315. if (qdf_unlikely(nbuf_clone))
  1316. qdf_nbuf_free(nbuf_clone);
  1317. return false;
  1318. }
  1319. /**
  1320. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1321. * @vdev: DP vdev handle
  1322. * @nbuf: skb
  1323. *
  1324. * Extract the DSCP or PCP information from frame and map into TID value.
  1325. *
  1326. * Return: void
  1327. */
  1328. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1329. struct dp_tx_msdu_info_s *msdu_info)
  1330. {
  1331. uint8_t tos = 0, dscp_tid_override = 0;
  1332. uint8_t *hdr_ptr, *L3datap;
  1333. uint8_t is_mcast = 0;
  1334. qdf_ether_header_t *eh = NULL;
  1335. qdf_ethervlan_header_t *evh = NULL;
  1336. uint16_t ether_type;
  1337. qdf_llc_t *llcHdr;
  1338. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1339. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1340. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1341. eh = (qdf_ether_header_t *)nbuf->data;
  1342. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1343. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1344. } else {
  1345. qdf_dot3_qosframe_t *qos_wh =
  1346. (qdf_dot3_qosframe_t *) nbuf->data;
  1347. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1348. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1349. return;
  1350. }
  1351. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1352. ether_type = eh->ether_type;
  1353. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1354. /*
  1355. * Check if packet is dot3 or eth2 type.
  1356. */
  1357. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1358. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1359. sizeof(*llcHdr));
  1360. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1361. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1362. sizeof(*llcHdr);
  1363. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1364. + sizeof(*llcHdr) +
  1365. sizeof(qdf_net_vlanhdr_t));
  1366. } else {
  1367. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1368. sizeof(*llcHdr);
  1369. }
  1370. } else {
  1371. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1372. evh = (qdf_ethervlan_header_t *) eh;
  1373. ether_type = evh->ether_type;
  1374. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1375. }
  1376. }
  1377. /*
  1378. * Find priority from IP TOS DSCP field
  1379. */
  1380. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1381. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1382. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1383. /* Only for unicast frames */
  1384. if (!is_mcast) {
  1385. /* send it on VO queue */
  1386. msdu_info->tid = DP_VO_TID;
  1387. }
  1388. } else {
  1389. /*
  1390. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1391. * from TOS byte.
  1392. */
  1393. tos = ip->ip_tos;
  1394. dscp_tid_override = 1;
  1395. }
  1396. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1397. /* TODO
  1398. * use flowlabel
  1399. *igmpmld cases to be handled in phase 2
  1400. */
  1401. unsigned long ver_pri_flowlabel;
  1402. unsigned long pri;
  1403. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1404. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1405. DP_IPV6_PRIORITY_SHIFT;
  1406. tos = pri;
  1407. dscp_tid_override = 1;
  1408. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1409. msdu_info->tid = DP_VO_TID;
  1410. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1411. /* Only for unicast frames */
  1412. if (!is_mcast) {
  1413. /* send ucast arp on VO queue */
  1414. msdu_info->tid = DP_VO_TID;
  1415. }
  1416. }
  1417. /*
  1418. * Assign all MCAST packets to BE
  1419. */
  1420. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1421. if (is_mcast) {
  1422. tos = 0;
  1423. dscp_tid_override = 1;
  1424. }
  1425. }
  1426. if (dscp_tid_override == 1) {
  1427. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1428. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1429. }
  1430. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1431. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1432. return;
  1433. }
  1434. /**
  1435. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1436. * @vdev: DP vdev handle
  1437. * @nbuf: skb
  1438. *
  1439. * Software based TID classification is required when more than 2 DSCP-TID
  1440. * mapping tables are needed.
  1441. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1442. *
  1443. * Return: void
  1444. */
  1445. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1446. struct dp_tx_msdu_info_s *msdu_info)
  1447. {
  1448. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1449. /*
  1450. * skip_sw_tid_classification flag will set in below cases-
  1451. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1452. * 2. hlos_tid_override enabled for vdev
  1453. * 3. mesh mode enabled for vdev
  1454. */
  1455. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1456. /* Update tid in msdu_info from skb priority */
  1457. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1458. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1459. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1460. return;
  1461. }
  1462. return;
  1463. }
  1464. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1465. }
  1466. #ifdef FEATURE_WLAN_TDLS
  1467. /**
  1468. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1469. * @soc: datapath SOC
  1470. * @vdev: datapath vdev
  1471. * @tx_desc: TX descriptor
  1472. *
  1473. * Return: None
  1474. */
  1475. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1476. struct dp_vdev *vdev,
  1477. struct dp_tx_desc_s *tx_desc)
  1478. {
  1479. if (vdev) {
  1480. if (vdev->is_tdls_frame) {
  1481. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1482. vdev->is_tdls_frame = false;
  1483. }
  1484. }
  1485. }
  1486. /**
  1487. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1488. * @soc: dp_soc handle
  1489. * @tx_desc: TX descriptor
  1490. * @vdev: datapath vdev handle
  1491. *
  1492. * Return: None
  1493. */
  1494. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1495. struct dp_tx_desc_s *tx_desc)
  1496. {
  1497. struct hal_tx_completion_status ts = {0};
  1498. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1499. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1500. DP_MOD_ID_TDLS);
  1501. if (qdf_unlikely(!vdev)) {
  1502. dp_err_rl("vdev is null!");
  1503. goto error;
  1504. }
  1505. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1506. if (vdev->tx_non_std_data_callback.func) {
  1507. qdf_nbuf_set_next(nbuf, NULL);
  1508. vdev->tx_non_std_data_callback.func(
  1509. vdev->tx_non_std_data_callback.ctxt,
  1510. nbuf, ts.status);
  1511. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1512. return;
  1513. } else {
  1514. dp_err_rl("callback func is null");
  1515. }
  1516. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1517. error:
  1518. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1519. qdf_nbuf_free(nbuf);
  1520. }
  1521. /**
  1522. * dp_tx_msdu_single_map() - do nbuf map
  1523. * @vdev: DP vdev handle
  1524. * @tx_desc: DP TX descriptor pointer
  1525. * @nbuf: skb pointer
  1526. *
  1527. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1528. * operation done in other component.
  1529. *
  1530. * Return: QDF_STATUS
  1531. */
  1532. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1533. struct dp_tx_desc_s *tx_desc,
  1534. qdf_nbuf_t nbuf)
  1535. {
  1536. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1537. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1538. nbuf,
  1539. QDF_DMA_TO_DEVICE,
  1540. nbuf->len);
  1541. else
  1542. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1543. QDF_DMA_TO_DEVICE);
  1544. }
  1545. #else
  1546. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1547. struct dp_vdev *vdev,
  1548. struct dp_tx_desc_s *tx_desc)
  1549. {
  1550. }
  1551. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1552. struct dp_tx_desc_s *tx_desc)
  1553. {
  1554. }
  1555. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1556. struct dp_tx_desc_s *tx_desc,
  1557. qdf_nbuf_t nbuf)
  1558. {
  1559. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1560. nbuf,
  1561. QDF_DMA_TO_DEVICE,
  1562. nbuf->len);
  1563. }
  1564. #endif
  1565. #ifdef MESH_MODE_SUPPORT
  1566. /**
  1567. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1568. * @soc: datapath SOC
  1569. * @vdev: datapath vdev
  1570. * @tx_desc: TX descriptor
  1571. *
  1572. * Return: None
  1573. */
  1574. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1575. struct dp_vdev *vdev,
  1576. struct dp_tx_desc_s *tx_desc)
  1577. {
  1578. if (qdf_unlikely(vdev->mesh_vdev))
  1579. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1580. }
  1581. /**
  1582. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1583. * @soc: dp_soc handle
  1584. * @tx_desc: TX descriptor
  1585. * @vdev: datapath vdev handle
  1586. *
  1587. * Return: None
  1588. */
  1589. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1590. struct dp_tx_desc_s *tx_desc)
  1591. {
  1592. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1593. struct dp_vdev *vdev = NULL;
  1594. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1595. qdf_nbuf_free(nbuf);
  1596. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1597. } else {
  1598. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1599. DP_MOD_ID_MESH);
  1600. if (vdev && vdev->osif_tx_free_ext)
  1601. vdev->osif_tx_free_ext((nbuf));
  1602. else
  1603. qdf_nbuf_free(nbuf);
  1604. if (vdev)
  1605. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1606. }
  1607. }
  1608. #else
  1609. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1610. struct dp_vdev *vdev,
  1611. struct dp_tx_desc_s *tx_desc)
  1612. {
  1613. }
  1614. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1615. struct dp_tx_desc_s *tx_desc)
  1616. {
  1617. }
  1618. #endif
  1619. /**
  1620. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1621. * @vdev: DP vdev handle
  1622. * @nbuf: skb
  1623. *
  1624. * Return: 1 if frame needs to be dropped else 0
  1625. */
  1626. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1627. {
  1628. struct dp_pdev *pdev = NULL;
  1629. struct dp_ast_entry *src_ast_entry = NULL;
  1630. struct dp_ast_entry *dst_ast_entry = NULL;
  1631. struct dp_soc *soc = NULL;
  1632. qdf_assert(vdev);
  1633. pdev = vdev->pdev;
  1634. qdf_assert(pdev);
  1635. soc = pdev->soc;
  1636. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1637. (soc, dstmac, vdev->pdev->pdev_id);
  1638. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1639. (soc, srcmac, vdev->pdev->pdev_id);
  1640. if (dst_ast_entry && src_ast_entry) {
  1641. if (dst_ast_entry->peer_id ==
  1642. src_ast_entry->peer_id)
  1643. return 1;
  1644. }
  1645. return 0;
  1646. }
  1647. /**
  1648. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1649. * @vdev: DP vdev handle
  1650. * @nbuf: skb
  1651. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1652. * @meta_data: Metadata to the fw
  1653. * @tx_q: Tx queue to be used for this Tx frame
  1654. * @peer_id: peer_id of the peer in case of NAWDS frames
  1655. * @tx_exc_metadata: Handle that holds exception path metadata
  1656. *
  1657. * Return: NULL on success,
  1658. * nbuf when it fails to send
  1659. */
  1660. qdf_nbuf_t
  1661. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1662. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1663. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1664. {
  1665. struct dp_pdev *pdev = vdev->pdev;
  1666. struct dp_soc *soc = pdev->soc;
  1667. struct dp_tx_desc_s *tx_desc;
  1668. QDF_STATUS status;
  1669. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1670. uint16_t htt_tcl_metadata = 0;
  1671. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1672. uint8_t tid = msdu_info->tid;
  1673. struct cdp_tid_tx_stats *tid_stats = NULL;
  1674. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1675. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1676. msdu_info, tx_exc_metadata);
  1677. if (!tx_desc) {
  1678. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1679. vdev, tx_q->desc_pool_id);
  1680. drop_code = TX_DESC_ERR;
  1681. goto fail_return;
  1682. }
  1683. if (qdf_unlikely(soc->cce_disable)) {
  1684. if (dp_cce_classify(vdev, nbuf) == true) {
  1685. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1686. tid = DP_VO_TID;
  1687. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1688. }
  1689. }
  1690. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1691. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1692. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1693. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1694. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1695. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1696. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1697. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1698. peer_id);
  1699. } else
  1700. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1701. if (msdu_info->exception_fw)
  1702. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1703. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1704. !pdev->enhanced_stats_en);
  1705. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1706. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1707. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1708. /* Handle failure */
  1709. dp_err("qdf_nbuf_map failed");
  1710. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1711. drop_code = TX_DMA_MAP_ERR;
  1712. goto release_desc;
  1713. }
  1714. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1715. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1716. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1717. if (status != QDF_STATUS_SUCCESS) {
  1718. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1719. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1720. __func__, tx_desc, tx_q->ring_id);
  1721. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1722. QDF_DMA_TO_DEVICE,
  1723. nbuf->len);
  1724. drop_code = TX_HW_ENQUEUE;
  1725. goto release_desc;
  1726. }
  1727. return NULL;
  1728. release_desc:
  1729. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1730. fail_return:
  1731. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1732. tid_stats = &pdev->stats.tid_stats.
  1733. tid_tx_stats[tx_q->ring_id][tid];
  1734. tid_stats->swdrop_cnt[drop_code]++;
  1735. return nbuf;
  1736. }
  1737. /**
  1738. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1739. * @vdev: DP vdev handle
  1740. * @nbuf: skb
  1741. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1742. *
  1743. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1744. *
  1745. * Return: NULL on success,
  1746. * nbuf when it fails to send
  1747. */
  1748. #if QDF_LOCK_STATS
  1749. noinline
  1750. #else
  1751. #endif
  1752. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1753. struct dp_tx_msdu_info_s *msdu_info)
  1754. {
  1755. uint32_t i;
  1756. struct dp_pdev *pdev = vdev->pdev;
  1757. struct dp_soc *soc = pdev->soc;
  1758. struct dp_tx_desc_s *tx_desc;
  1759. bool is_cce_classified = false;
  1760. QDF_STATUS status;
  1761. uint16_t htt_tcl_metadata = 0;
  1762. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1763. struct cdp_tid_tx_stats *tid_stats = NULL;
  1764. if (qdf_unlikely(soc->cce_disable)) {
  1765. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1766. if (is_cce_classified) {
  1767. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1768. msdu_info->tid = DP_VO_TID;
  1769. }
  1770. }
  1771. if (msdu_info->frm_type == dp_tx_frm_me)
  1772. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1773. i = 0;
  1774. /* Print statement to track i and num_seg */
  1775. /*
  1776. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1777. * descriptors using information in msdu_info
  1778. */
  1779. while (i < msdu_info->num_seg) {
  1780. /*
  1781. * Setup Tx descriptor for an MSDU, and MSDU extension
  1782. * descriptor
  1783. */
  1784. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1785. tx_q->desc_pool_id);
  1786. if (!tx_desc) {
  1787. if (msdu_info->frm_type == dp_tx_frm_me) {
  1788. dp_tx_me_free_buf(pdev,
  1789. (void *)(msdu_info->u.sg_info
  1790. .curr_seg->frags[0].vaddr));
  1791. i++;
  1792. continue;
  1793. }
  1794. goto done;
  1795. }
  1796. if (msdu_info->frm_type == dp_tx_frm_me) {
  1797. tx_desc->me_buffer =
  1798. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1799. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1800. }
  1801. if (is_cce_classified)
  1802. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1803. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1804. if (msdu_info->exception_fw) {
  1805. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1806. }
  1807. /*
  1808. * Enqueue the Tx MSDU descriptor to HW for transmit
  1809. */
  1810. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1811. htt_tcl_metadata, tx_q->ring_id, NULL);
  1812. if (status != QDF_STATUS_SUCCESS) {
  1813. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1814. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1815. __func__, tx_desc, tx_q->ring_id);
  1816. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1817. tid_stats = &pdev->stats.tid_stats.
  1818. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1819. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1820. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1821. if (msdu_info->frm_type == dp_tx_frm_me) {
  1822. i++;
  1823. continue;
  1824. }
  1825. goto done;
  1826. }
  1827. /*
  1828. * TODO
  1829. * if tso_info structure can be modified to have curr_seg
  1830. * as first element, following 2 blocks of code (for TSO and SG)
  1831. * can be combined into 1
  1832. */
  1833. /*
  1834. * For frames with multiple segments (TSO, ME), jump to next
  1835. * segment.
  1836. */
  1837. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1838. if (msdu_info->u.tso_info.curr_seg->next) {
  1839. msdu_info->u.tso_info.curr_seg =
  1840. msdu_info->u.tso_info.curr_seg->next;
  1841. /*
  1842. * If this is a jumbo nbuf, then increment the number of
  1843. * nbuf users for each additional segment of the msdu.
  1844. * This will ensure that the skb is freed only after
  1845. * receiving tx completion for all segments of an nbuf
  1846. */
  1847. qdf_nbuf_inc_users(nbuf);
  1848. /* Check with MCL if this is needed */
  1849. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1850. }
  1851. }
  1852. /*
  1853. * For Multicast-Unicast converted packets,
  1854. * each converted frame (for a client) is represented as
  1855. * 1 segment
  1856. */
  1857. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1858. (msdu_info->frm_type == dp_tx_frm_me)) {
  1859. if (msdu_info->u.sg_info.curr_seg->next) {
  1860. msdu_info->u.sg_info.curr_seg =
  1861. msdu_info->u.sg_info.curr_seg->next;
  1862. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1863. }
  1864. }
  1865. i++;
  1866. }
  1867. nbuf = NULL;
  1868. done:
  1869. return nbuf;
  1870. }
  1871. /**
  1872. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1873. * for SG frames
  1874. * @vdev: DP vdev handle
  1875. * @nbuf: skb
  1876. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1877. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1878. *
  1879. * Return: NULL on success,
  1880. * nbuf when it fails to send
  1881. */
  1882. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1883. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1884. {
  1885. uint32_t cur_frag, nr_frags;
  1886. qdf_dma_addr_t paddr;
  1887. struct dp_tx_sg_info_s *sg_info;
  1888. sg_info = &msdu_info->u.sg_info;
  1889. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1890. if (QDF_STATUS_SUCCESS !=
  1891. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  1892. QDF_DMA_TO_DEVICE, nbuf->len)) {
  1893. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1894. "dma map error");
  1895. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1896. qdf_nbuf_free(nbuf);
  1897. return NULL;
  1898. }
  1899. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  1900. seg_info->frags[0].paddr_lo = paddr;
  1901. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1902. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1903. seg_info->frags[0].vaddr = (void *) nbuf;
  1904. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1905. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1906. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1907. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1908. "frag dma map error");
  1909. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1910. qdf_nbuf_free(nbuf);
  1911. return NULL;
  1912. }
  1913. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  1914. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1915. seg_info->frags[cur_frag + 1].paddr_hi =
  1916. ((uint64_t) paddr) >> 32;
  1917. seg_info->frags[cur_frag + 1].len =
  1918. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1919. }
  1920. seg_info->frag_cnt = (cur_frag + 1);
  1921. seg_info->total_len = qdf_nbuf_len(nbuf);
  1922. seg_info->next = NULL;
  1923. sg_info->curr_seg = seg_info;
  1924. msdu_info->frm_type = dp_tx_frm_sg;
  1925. msdu_info->num_seg = 1;
  1926. return nbuf;
  1927. }
  1928. /**
  1929. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1930. * @vdev: DP vdev handle
  1931. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1932. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1933. *
  1934. * Return: NULL on failure,
  1935. * nbuf when extracted successfully
  1936. */
  1937. static
  1938. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1939. struct dp_tx_msdu_info_s *msdu_info,
  1940. uint16_t ppdu_cookie)
  1941. {
  1942. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1943. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1944. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1945. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1946. (msdu_info->meta_data[5], 1);
  1947. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1948. (msdu_info->meta_data[5], 1);
  1949. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1950. (msdu_info->meta_data[6], ppdu_cookie);
  1951. msdu_info->exception_fw = 1;
  1952. msdu_info->is_tx_sniffer = 1;
  1953. }
  1954. #ifdef MESH_MODE_SUPPORT
  1955. /**
  1956. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1957. and prepare msdu_info for mesh frames.
  1958. * @vdev: DP vdev handle
  1959. * @nbuf: skb
  1960. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1961. *
  1962. * Return: NULL on failure,
  1963. * nbuf when extracted successfully
  1964. */
  1965. static
  1966. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1967. struct dp_tx_msdu_info_s *msdu_info)
  1968. {
  1969. struct meta_hdr_s *mhdr;
  1970. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1971. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1972. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1973. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1974. msdu_info->exception_fw = 0;
  1975. goto remove_meta_hdr;
  1976. }
  1977. msdu_info->exception_fw = 1;
  1978. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1979. meta_data->host_tx_desc_pool = 1;
  1980. meta_data->update_peer_cache = 1;
  1981. meta_data->learning_frame = 1;
  1982. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1983. meta_data->power = mhdr->power;
  1984. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1985. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1986. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1987. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1988. meta_data->dyn_bw = 1;
  1989. meta_data->valid_pwr = 1;
  1990. meta_data->valid_mcs_mask = 1;
  1991. meta_data->valid_nss_mask = 1;
  1992. meta_data->valid_preamble_type = 1;
  1993. meta_data->valid_retries = 1;
  1994. meta_data->valid_bw_info = 1;
  1995. }
  1996. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1997. meta_data->encrypt_type = 0;
  1998. meta_data->valid_encrypt_type = 1;
  1999. meta_data->learning_frame = 0;
  2000. }
  2001. meta_data->valid_key_flags = 1;
  2002. meta_data->key_flags = (mhdr->keyix & 0x3);
  2003. remove_meta_hdr:
  2004. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2005. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2006. "qdf_nbuf_pull_head failed");
  2007. qdf_nbuf_free(nbuf);
  2008. return NULL;
  2009. }
  2010. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2011. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2012. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  2013. " tid %d to_fw %d",
  2014. __func__, msdu_info->meta_data[0],
  2015. msdu_info->meta_data[1],
  2016. msdu_info->meta_data[2],
  2017. msdu_info->meta_data[3],
  2018. msdu_info->meta_data[4],
  2019. msdu_info->meta_data[5],
  2020. msdu_info->tid, msdu_info->exception_fw);
  2021. return nbuf;
  2022. }
  2023. #else
  2024. static
  2025. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2026. struct dp_tx_msdu_info_s *msdu_info)
  2027. {
  2028. return nbuf;
  2029. }
  2030. #endif
  2031. /**
  2032. * dp_check_exc_metadata() - Checks if parameters are valid
  2033. * @tx_exc - holds all exception path parameters
  2034. *
  2035. * Returns true when all the parameters are valid else false
  2036. *
  2037. */
  2038. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2039. {
  2040. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  2041. HTT_INVALID_TID);
  2042. bool invalid_encap_type =
  2043. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2044. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2045. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2046. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2047. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2048. tx_exc->ppdu_cookie == 0);
  2049. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2050. invalid_cookie) {
  2051. return false;
  2052. }
  2053. return true;
  2054. }
  2055. /**
  2056. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2057. * @soc: DP soc handle
  2058. * @vdev_id: id of DP vdev handle
  2059. * @nbuf: skb
  2060. * @tx_exc_metadata: Handle that holds exception path meta data
  2061. *
  2062. * Entry point for Core Tx layer (DP_TX) invoked from
  2063. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2064. *
  2065. * Return: NULL on success,
  2066. * nbuf when it fails to send
  2067. */
  2068. qdf_nbuf_t
  2069. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2070. qdf_nbuf_t nbuf,
  2071. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2072. {
  2073. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2074. qdf_ether_header_t *eh = NULL;
  2075. struct dp_tx_msdu_info_s msdu_info;
  2076. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2077. DP_MOD_ID_TX_EXCEPTION);
  2078. if (qdf_unlikely(!vdev))
  2079. goto fail;
  2080. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2081. if (!tx_exc_metadata)
  2082. goto fail;
  2083. msdu_info.tid = tx_exc_metadata->tid;
  2084. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2085. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2086. QDF_MAC_ADDR_REF(nbuf->data));
  2087. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2088. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2089. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2090. "Invalid parameters in exception path");
  2091. goto fail;
  2092. }
  2093. /* Basic sanity checks for unsupported packets */
  2094. /* MESH mode */
  2095. if (qdf_unlikely(vdev->mesh_vdev)) {
  2096. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2097. "Mesh mode is not supported in exception path");
  2098. goto fail;
  2099. }
  2100. /* TSO or SG */
  2101. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  2102. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2103. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2104. "TSO and SG are not supported in exception path");
  2105. goto fail;
  2106. }
  2107. /* RAW */
  2108. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2109. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2110. "Raw frame is not supported in exception path");
  2111. goto fail;
  2112. }
  2113. /* Mcast enhancement*/
  2114. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2115. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2116. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2117. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2118. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  2119. }
  2120. }
  2121. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2122. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2123. qdf_nbuf_len(nbuf));
  2124. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2125. tx_exc_metadata->ppdu_cookie);
  2126. }
  2127. /*
  2128. * Get HW Queue to use for this frame.
  2129. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2130. * dedicated for data and 1 for command.
  2131. * "queue_id" maps to one hardware ring.
  2132. * With each ring, we also associate a unique Tx descriptor pool
  2133. * to minimize lock contention for these resources.
  2134. */
  2135. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2136. /*
  2137. * Check exception descriptors
  2138. */
  2139. if (dp_tx_exception_limit_check(vdev))
  2140. goto fail;
  2141. /* Single linear frame */
  2142. /*
  2143. * If nbuf is a simple linear frame, use send_single function to
  2144. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2145. * SRNG. There is no need to setup a MSDU extension descriptor.
  2146. */
  2147. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2148. tx_exc_metadata->peer_id, tx_exc_metadata);
  2149. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2150. return nbuf;
  2151. fail:
  2152. if (vdev)
  2153. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2154. dp_verbose_debug("pkt send failed");
  2155. return nbuf;
  2156. }
  2157. /**
  2158. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2159. * @soc: DP soc handle
  2160. * @vdev_id: DP vdev handle
  2161. * @nbuf: skb
  2162. *
  2163. * Entry point for Core Tx layer (DP_TX) invoked from
  2164. * hard_start_xmit in OSIF/HDD
  2165. *
  2166. * Return: NULL on success,
  2167. * nbuf when it fails to send
  2168. */
  2169. #ifdef MESH_MODE_SUPPORT
  2170. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2171. qdf_nbuf_t nbuf)
  2172. {
  2173. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2174. struct meta_hdr_s *mhdr;
  2175. qdf_nbuf_t nbuf_mesh = NULL;
  2176. qdf_nbuf_t nbuf_clone = NULL;
  2177. struct dp_vdev *vdev;
  2178. uint8_t no_enc_frame = 0;
  2179. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2180. if (!nbuf_mesh) {
  2181. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2182. "qdf_nbuf_unshare failed");
  2183. return nbuf;
  2184. }
  2185. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2186. if (!vdev) {
  2187. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2188. "vdev is NULL for vdev_id %d", vdev_id);
  2189. return nbuf;
  2190. }
  2191. nbuf = nbuf_mesh;
  2192. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2193. if ((vdev->sec_type != cdp_sec_type_none) &&
  2194. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2195. no_enc_frame = 1;
  2196. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2197. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2198. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2199. !no_enc_frame) {
  2200. nbuf_clone = qdf_nbuf_clone(nbuf);
  2201. if (!nbuf_clone) {
  2202. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2203. "qdf_nbuf_clone failed");
  2204. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2205. return nbuf;
  2206. }
  2207. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2208. }
  2209. if (nbuf_clone) {
  2210. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2211. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2212. } else {
  2213. qdf_nbuf_free(nbuf_clone);
  2214. }
  2215. }
  2216. if (no_enc_frame)
  2217. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2218. else
  2219. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2220. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2221. if ((!nbuf) && no_enc_frame) {
  2222. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2223. }
  2224. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2225. return nbuf;
  2226. }
  2227. #else
  2228. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2229. qdf_nbuf_t nbuf)
  2230. {
  2231. return dp_tx_send(soc, vdev_id, nbuf);
  2232. }
  2233. #endif
  2234. /**
  2235. * dp_tx_nawds_handler() - NAWDS handler
  2236. *
  2237. * @soc: DP soc handle
  2238. * @vdev_id: id of DP vdev handle
  2239. * @msdu_info: msdu_info required to create HTT metadata
  2240. * @nbuf: skb
  2241. *
  2242. * This API transfers the multicast frames with the peer id
  2243. * on NAWDS enabled peer.
  2244. * Return: none
  2245. */
  2246. static inline
  2247. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2248. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2249. {
  2250. struct dp_peer *peer = NULL;
  2251. qdf_nbuf_t nbuf_clone = NULL;
  2252. uint16_t peer_id = DP_INVALID_PEER;
  2253. uint16_t sa_peer_id = DP_INVALID_PEER;
  2254. struct dp_ast_entry *ast_entry = NULL;
  2255. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2256. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2257. qdf_spin_lock_bh(&soc->ast_lock);
  2258. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2259. (soc,
  2260. (uint8_t *)(eh->ether_shost),
  2261. vdev->pdev->pdev_id);
  2262. if (ast_entry)
  2263. sa_peer_id = ast_entry->peer_id;
  2264. qdf_spin_unlock_bh(&soc->ast_lock);
  2265. }
  2266. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2267. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2268. if (!peer->bss_peer && peer->nawds_enabled) {
  2269. peer_id = peer->peer_id;
  2270. /* Multicast packets needs to be
  2271. * dropped in case of intra bss forwarding
  2272. */
  2273. if (sa_peer_id == peer->peer_id) {
  2274. QDF_TRACE(QDF_MODULE_ID_DP,
  2275. QDF_TRACE_LEVEL_DEBUG,
  2276. " %s: multicast packet", __func__);
  2277. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2278. continue;
  2279. }
  2280. nbuf_clone = qdf_nbuf_clone(nbuf);
  2281. if (!nbuf_clone) {
  2282. QDF_TRACE(QDF_MODULE_ID_DP,
  2283. QDF_TRACE_LEVEL_ERROR,
  2284. FL("nbuf clone failed"));
  2285. break;
  2286. }
  2287. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2288. msdu_info, peer_id,
  2289. NULL);
  2290. if (nbuf_clone) {
  2291. QDF_TRACE(QDF_MODULE_ID_DP,
  2292. QDF_TRACE_LEVEL_DEBUG,
  2293. FL("pkt send failed"));
  2294. qdf_nbuf_free(nbuf_clone);
  2295. } else {
  2296. if (peer_id != DP_INVALID_PEER)
  2297. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2298. 1, qdf_nbuf_len(nbuf));
  2299. }
  2300. }
  2301. }
  2302. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2303. }
  2304. /**
  2305. * dp_tx_send() - Transmit a frame on a given VAP
  2306. * @soc: DP soc handle
  2307. * @vdev_id: id of DP vdev handle
  2308. * @nbuf: skb
  2309. *
  2310. * Entry point for Core Tx layer (DP_TX) invoked from
  2311. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2312. * cases
  2313. *
  2314. * Return: NULL on success,
  2315. * nbuf when it fails to send
  2316. */
  2317. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2318. qdf_nbuf_t nbuf)
  2319. {
  2320. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2321. uint16_t peer_id = HTT_INVALID_PEER;
  2322. /*
  2323. * doing a memzero is causing additional function call overhead
  2324. * so doing static stack clearing
  2325. */
  2326. struct dp_tx_msdu_info_s msdu_info = {0};
  2327. struct dp_vdev *vdev = NULL;
  2328. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2329. return nbuf;
  2330. /*
  2331. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2332. * this in per packet path.
  2333. *
  2334. * As in this path vdev memory is already protected with netdev
  2335. * tx lock
  2336. */
  2337. vdev = soc->vdev_id_map[vdev_id];
  2338. if (qdf_unlikely(!vdev))
  2339. return nbuf;
  2340. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2341. QDF_MAC_ADDR_REF(nbuf->data));
  2342. /*
  2343. * Set Default Host TID value to invalid TID
  2344. * (TID override disabled)
  2345. */
  2346. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2347. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2348. if (qdf_unlikely(vdev->mesh_vdev)) {
  2349. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2350. &msdu_info);
  2351. if (!nbuf_mesh) {
  2352. dp_verbose_debug("Extracting mesh metadata failed");
  2353. return nbuf;
  2354. }
  2355. nbuf = nbuf_mesh;
  2356. }
  2357. /*
  2358. * Get HW Queue to use for this frame.
  2359. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2360. * dedicated for data and 1 for command.
  2361. * "queue_id" maps to one hardware ring.
  2362. * With each ring, we also associate a unique Tx descriptor pool
  2363. * to minimize lock contention for these resources.
  2364. */
  2365. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2366. /*
  2367. * TCL H/W supports 2 DSCP-TID mapping tables.
  2368. * Table 1 - Default DSCP-TID mapping table
  2369. * Table 2 - 1 DSCP-TID override table
  2370. *
  2371. * If we need a different DSCP-TID mapping for this vap,
  2372. * call tid_classify to extract DSCP/ToS from frame and
  2373. * map to a TID and store in msdu_info. This is later used
  2374. * to fill in TCL Input descriptor (per-packet TID override).
  2375. */
  2376. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2377. /*
  2378. * Classify the frame and call corresponding
  2379. * "prepare" function which extracts the segment (TSO)
  2380. * and fragmentation information (for TSO , SG, ME, or Raw)
  2381. * into MSDU_INFO structure which is later used to fill
  2382. * SW and HW descriptors.
  2383. */
  2384. if (qdf_nbuf_is_tso(nbuf)) {
  2385. dp_verbose_debug("TSO frame %pK", vdev);
  2386. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2387. qdf_nbuf_len(nbuf));
  2388. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2389. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2390. qdf_nbuf_len(nbuf));
  2391. return nbuf;
  2392. }
  2393. goto send_multiple;
  2394. }
  2395. /* SG */
  2396. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2397. struct dp_tx_seg_info_s seg_info = {0};
  2398. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2399. if (!nbuf)
  2400. return NULL;
  2401. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2402. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2403. qdf_nbuf_len(nbuf));
  2404. goto send_multiple;
  2405. }
  2406. #ifdef ATH_SUPPORT_IQUE
  2407. /* Mcast to Ucast Conversion*/
  2408. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2409. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2410. qdf_nbuf_data(nbuf);
  2411. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2412. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2413. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2414. DP_STATS_INC_PKT(vdev,
  2415. tx_i.mcast_en.mcast_pkt, 1,
  2416. qdf_nbuf_len(nbuf));
  2417. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2418. QDF_STATUS_SUCCESS) {
  2419. return NULL;
  2420. }
  2421. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2422. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2423. QDF_STATUS_SUCCESS) {
  2424. return NULL;
  2425. }
  2426. }
  2427. }
  2428. }
  2429. #endif
  2430. /* RAW */
  2431. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2432. struct dp_tx_seg_info_s seg_info = {0};
  2433. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2434. if (!nbuf)
  2435. return NULL;
  2436. dp_verbose_debug("Raw frame %pK", vdev);
  2437. goto send_multiple;
  2438. }
  2439. if (qdf_unlikely(vdev->nawds_enabled)) {
  2440. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2441. qdf_nbuf_data(nbuf);
  2442. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2443. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2444. peer_id = DP_INVALID_PEER;
  2445. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2446. 1, qdf_nbuf_len(nbuf));
  2447. }
  2448. /* Single linear frame */
  2449. /*
  2450. * If nbuf is a simple linear frame, use send_single function to
  2451. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2452. * SRNG. There is no need to setup a MSDU extension descriptor.
  2453. */
  2454. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2455. return nbuf;
  2456. send_multiple:
  2457. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2458. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2459. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2460. return nbuf;
  2461. }
  2462. /**
  2463. * dp_tx_reinject_handler() - Tx Reinject Handler
  2464. * @soc: datapath soc handle
  2465. * @vdev: datapath vdev handle
  2466. * @tx_desc: software descriptor head pointer
  2467. * @status : Tx completion status from HTT descriptor
  2468. *
  2469. * This function reinjects frames back to Target.
  2470. * Todo - Host queue needs to be added
  2471. *
  2472. * Return: none
  2473. */
  2474. static
  2475. void dp_tx_reinject_handler(struct dp_soc *soc,
  2476. struct dp_vdev *vdev,
  2477. struct dp_tx_desc_s *tx_desc,
  2478. uint8_t *status)
  2479. {
  2480. struct dp_peer *peer = NULL;
  2481. uint32_t peer_id = HTT_INVALID_PEER;
  2482. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2483. qdf_nbuf_t nbuf_copy = NULL;
  2484. struct dp_tx_msdu_info_s msdu_info;
  2485. #ifdef WDS_VENDOR_EXTENSION
  2486. int is_mcast = 0, is_ucast = 0;
  2487. int num_peers_3addr = 0;
  2488. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2489. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2490. #endif
  2491. qdf_assert(vdev);
  2492. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2493. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2494. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2495. "%s Tx reinject path", __func__);
  2496. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2497. qdf_nbuf_len(tx_desc->nbuf));
  2498. #ifdef WDS_VENDOR_EXTENSION
  2499. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2500. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2501. } else {
  2502. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2503. }
  2504. is_ucast = !is_mcast;
  2505. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2506. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2507. if (peer->bss_peer)
  2508. continue;
  2509. /* Detect wds peers that use 3-addr framing for mcast.
  2510. * if there are any, the bss_peer is used to send the
  2511. * the mcast frame using 3-addr format. all wds enabled
  2512. * peers that use 4-addr framing for mcast frames will
  2513. * be duplicated and sent as 4-addr frames below.
  2514. */
  2515. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2516. num_peers_3addr = 1;
  2517. break;
  2518. }
  2519. }
  2520. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2521. #endif
  2522. if (qdf_unlikely(vdev->mesh_vdev)) {
  2523. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2524. } else {
  2525. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2526. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2527. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2528. #ifdef WDS_VENDOR_EXTENSION
  2529. /*
  2530. * . if 3-addr STA, then send on BSS Peer
  2531. * . if Peer WDS enabled and accept 4-addr mcast,
  2532. * send mcast on that peer only
  2533. * . if Peer WDS enabled and accept 4-addr ucast,
  2534. * send ucast on that peer only
  2535. */
  2536. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2537. (peer->wds_enabled &&
  2538. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2539. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2540. #else
  2541. ((peer->bss_peer &&
  2542. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2543. #endif
  2544. peer_id = DP_INVALID_PEER;
  2545. nbuf_copy = qdf_nbuf_copy(nbuf);
  2546. if (!nbuf_copy) {
  2547. QDF_TRACE(QDF_MODULE_ID_DP,
  2548. QDF_TRACE_LEVEL_DEBUG,
  2549. FL("nbuf copy failed"));
  2550. break;
  2551. }
  2552. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2553. nbuf_copy,
  2554. &msdu_info,
  2555. peer_id,
  2556. NULL);
  2557. if (nbuf_copy) {
  2558. QDF_TRACE(QDF_MODULE_ID_DP,
  2559. QDF_TRACE_LEVEL_DEBUG,
  2560. FL("pkt send failed"));
  2561. qdf_nbuf_free(nbuf_copy);
  2562. }
  2563. }
  2564. }
  2565. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2566. }
  2567. qdf_nbuf_free(nbuf);
  2568. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2569. }
  2570. /**
  2571. * dp_tx_inspect_handler() - Tx Inspect Handler
  2572. * @soc: datapath soc handle
  2573. * @vdev: datapath vdev handle
  2574. * @tx_desc: software descriptor head pointer
  2575. * @status : Tx completion status from HTT descriptor
  2576. *
  2577. * Handles Tx frames sent back to Host for inspection
  2578. * (ProxyARP)
  2579. *
  2580. * Return: none
  2581. */
  2582. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2583. struct dp_vdev *vdev,
  2584. struct dp_tx_desc_s *tx_desc,
  2585. uint8_t *status)
  2586. {
  2587. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2588. "%s Tx inspect path",
  2589. __func__);
  2590. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2591. qdf_nbuf_len(tx_desc->nbuf));
  2592. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2593. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2594. }
  2595. #ifdef FEATURE_PERPKT_INFO
  2596. /**
  2597. * dp_get_completion_indication_for_stack() - send completion to stack
  2598. * @soc : dp_soc handle
  2599. * @pdev: dp_pdev handle
  2600. * @peer: dp peer handle
  2601. * @ts: transmit completion status structure
  2602. * @netbuf: Buffer pointer for free
  2603. *
  2604. * This function is used for indication whether buffer needs to be
  2605. * sent to stack for freeing or not
  2606. */
  2607. QDF_STATUS
  2608. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2609. struct dp_pdev *pdev,
  2610. struct dp_peer *peer,
  2611. struct hal_tx_completion_status *ts,
  2612. qdf_nbuf_t netbuf,
  2613. uint64_t time_latency)
  2614. {
  2615. struct tx_capture_hdr *ppdu_hdr;
  2616. uint16_t peer_id = ts->peer_id;
  2617. uint32_t ppdu_id = ts->ppdu_id;
  2618. uint8_t first_msdu = ts->first_msdu;
  2619. uint8_t last_msdu = ts->last_msdu;
  2620. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2621. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2622. !pdev->latency_capture_enable))
  2623. return QDF_STATUS_E_NOSUPPORT;
  2624. if (!peer) {
  2625. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2626. FL("Peer Invalid"));
  2627. return QDF_STATUS_E_INVAL;
  2628. }
  2629. if (pdev->mcopy_mode) {
  2630. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2631. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2632. * for each MPDU
  2633. */
  2634. if (pdev->mcopy_mode == M_COPY) {
  2635. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2636. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2637. return QDF_STATUS_E_INVAL;
  2638. }
  2639. }
  2640. if (!first_msdu)
  2641. return QDF_STATUS_E_INVAL;
  2642. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2643. pdev->m_copy_id.tx_peer_id = peer_id;
  2644. }
  2645. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  2646. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  2647. if (!netbuf) {
  2648. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2649. FL("No headroom"));
  2650. return QDF_STATUS_E_NOMEM;
  2651. }
  2652. }
  2653. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  2654. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2655. FL("No headroom"));
  2656. return QDF_STATUS_E_NOMEM;
  2657. }
  2658. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2659. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2660. QDF_MAC_ADDR_SIZE);
  2661. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2662. QDF_MAC_ADDR_SIZE);
  2663. ppdu_hdr->ppdu_id = ppdu_id;
  2664. ppdu_hdr->peer_id = peer_id;
  2665. ppdu_hdr->first_msdu = first_msdu;
  2666. ppdu_hdr->last_msdu = last_msdu;
  2667. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2668. ppdu_hdr->tsf = ts->tsf;
  2669. ppdu_hdr->time_latency = time_latency;
  2670. }
  2671. return QDF_STATUS_SUCCESS;
  2672. }
  2673. /**
  2674. * dp_send_completion_to_stack() - send completion to stack
  2675. * @soc : dp_soc handle
  2676. * @pdev: dp_pdev handle
  2677. * @peer_id: peer_id of the peer for which completion came
  2678. * @ppdu_id: ppdu_id
  2679. * @netbuf: Buffer pointer for free
  2680. *
  2681. * This function is used to send completion to stack
  2682. * to free buffer
  2683. */
  2684. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2685. uint16_t peer_id, uint32_t ppdu_id,
  2686. qdf_nbuf_t netbuf)
  2687. {
  2688. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2689. netbuf, peer_id,
  2690. WDI_NO_VAL, pdev->pdev_id);
  2691. }
  2692. #else
  2693. static QDF_STATUS
  2694. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2695. struct dp_pdev *pdev,
  2696. struct dp_peer *peer,
  2697. struct hal_tx_completion_status *ts,
  2698. qdf_nbuf_t netbuf,
  2699. uint64_t time_latency)
  2700. {
  2701. return QDF_STATUS_E_NOSUPPORT;
  2702. }
  2703. static void
  2704. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2705. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2706. {
  2707. }
  2708. #endif
  2709. /**
  2710. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2711. * @soc: Soc handle
  2712. * @desc: software Tx descriptor to be processed
  2713. *
  2714. * Return: none
  2715. */
  2716. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2717. struct dp_tx_desc_s *desc)
  2718. {
  2719. qdf_nbuf_t nbuf = desc->nbuf;
  2720. /* nbuf already freed in vdev detach path */
  2721. if (!nbuf)
  2722. return;
  2723. /* If it is TDLS mgmt, don't unmap or free the frame */
  2724. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2725. return dp_non_std_tx_comp_free_buff(soc, desc);
  2726. /* 0 : MSDU buffer, 1 : MLE */
  2727. if (desc->msdu_ext_desc) {
  2728. /* TSO free */
  2729. if (hal_tx_ext_desc_get_tso_enable(
  2730. desc->msdu_ext_desc->vaddr)) {
  2731. /* unmap eash TSO seg before free the nbuf */
  2732. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2733. desc->tso_num_desc);
  2734. qdf_nbuf_free(nbuf);
  2735. return;
  2736. }
  2737. }
  2738. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2739. QDF_DMA_TO_DEVICE, nbuf->len);
  2740. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2741. return dp_mesh_tx_comp_free_buff(soc, desc);
  2742. qdf_nbuf_free(nbuf);
  2743. }
  2744. #ifdef MESH_MODE_SUPPORT
  2745. /**
  2746. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2747. * in mesh meta header
  2748. * @tx_desc: software descriptor head pointer
  2749. * @ts: pointer to tx completion stats
  2750. * Return: none
  2751. */
  2752. static
  2753. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2754. struct hal_tx_completion_status *ts)
  2755. {
  2756. struct meta_hdr_s *mhdr;
  2757. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2758. if (!tx_desc->msdu_ext_desc) {
  2759. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2760. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2761. "netbuf %pK offset %d",
  2762. netbuf, tx_desc->pkt_offset);
  2763. return;
  2764. }
  2765. }
  2766. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2767. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2768. "netbuf %pK offset %lu", netbuf,
  2769. sizeof(struct meta_hdr_s));
  2770. return;
  2771. }
  2772. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2773. mhdr->rssi = ts->ack_frame_rssi;
  2774. mhdr->band = tx_desc->pdev->operating_channel.band;
  2775. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2776. }
  2777. #else
  2778. static
  2779. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2780. struct hal_tx_completion_status *ts)
  2781. {
  2782. }
  2783. #endif
  2784. #ifdef QCA_PEER_EXT_STATS
  2785. /*
  2786. * dp_tx_compute_tid_delay() - Compute per TID delay
  2787. * @stats: Per TID delay stats
  2788. * @tx_desc: Software Tx descriptor
  2789. *
  2790. * Compute the software enqueue and hw enqueue delays and
  2791. * update the respective histograms
  2792. *
  2793. * Return: void
  2794. */
  2795. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  2796. struct dp_tx_desc_s *tx_desc)
  2797. {
  2798. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  2799. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2800. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  2801. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2802. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2803. timestamp_hw_enqueue = tx_desc->timestamp;
  2804. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2805. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2806. timestamp_hw_enqueue);
  2807. /*
  2808. * Update the Tx software enqueue delay and HW enque-Completion delay.
  2809. */
  2810. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  2811. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  2812. }
  2813. /*
  2814. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  2815. * @peer: DP peer context
  2816. * @tx_desc: Tx software descriptor
  2817. * @tid: Transmission ID
  2818. * @ring_id: Rx CPU context ID/CPU_ID
  2819. *
  2820. * Update the peer extended stats. These are enhanced other
  2821. * delay stats per msdu level.
  2822. *
  2823. * Return: void
  2824. */
  2825. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2826. struct dp_tx_desc_s *tx_desc,
  2827. uint8_t tid, uint8_t ring_id)
  2828. {
  2829. struct dp_pdev *pdev = peer->vdev->pdev;
  2830. struct dp_soc *soc = NULL;
  2831. struct cdp_peer_ext_stats *pext_stats = NULL;
  2832. soc = pdev->soc;
  2833. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  2834. return;
  2835. pext_stats = peer->pext_stats;
  2836. qdf_assert(pext_stats);
  2837. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  2838. /*
  2839. * For non-TID packets use the TID 9
  2840. */
  2841. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2842. tid = CDP_MAX_DATA_TIDS - 1;
  2843. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  2844. tx_desc);
  2845. }
  2846. #else
  2847. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2848. struct dp_tx_desc_s *tx_desc,
  2849. uint8_t tid, uint8_t ring_id)
  2850. {
  2851. }
  2852. #endif
  2853. /**
  2854. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2855. * to pass in correct fields
  2856. *
  2857. * @vdev: pdev handle
  2858. * @tx_desc: tx descriptor
  2859. * @tid: tid value
  2860. * @ring_id: TCL or WBM ring number for transmit path
  2861. * Return: none
  2862. */
  2863. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2864. struct dp_tx_desc_s *tx_desc,
  2865. uint8_t tid, uint8_t ring_id)
  2866. {
  2867. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2868. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2869. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2870. return;
  2871. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2872. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2873. timestamp_hw_enqueue = tx_desc->timestamp;
  2874. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2875. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2876. timestamp_hw_enqueue);
  2877. interframe_delay = (uint32_t)(timestamp_ingress -
  2878. vdev->prev_tx_enq_tstamp);
  2879. /*
  2880. * Delay in software enqueue
  2881. */
  2882. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2883. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2884. /*
  2885. * Delay between packet enqueued to HW and Tx completion
  2886. */
  2887. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2888. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2889. /*
  2890. * Update interframe delay stats calculated at hardstart receive point.
  2891. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2892. * interframe delay will not be calculate correctly for 1st frame.
  2893. * On the other side, this will help in avoiding extra per packet check
  2894. * of !vdev->prev_tx_enq_tstamp.
  2895. */
  2896. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2897. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2898. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2899. }
  2900. #ifdef DISABLE_DP_STATS
  2901. static
  2902. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2903. {
  2904. }
  2905. #else
  2906. static
  2907. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2908. {
  2909. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  2910. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  2911. if (subtype != QDF_PROTO_INVALID)
  2912. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  2913. }
  2914. #endif
  2915. /**
  2916. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2917. * per wbm ring
  2918. *
  2919. * @tx_desc: software descriptor head pointer
  2920. * @ts: Tx completion status
  2921. * @peer: peer handle
  2922. * @ring_id: ring number
  2923. *
  2924. * Return: None
  2925. */
  2926. static inline void
  2927. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2928. struct hal_tx_completion_status *ts,
  2929. struct dp_peer *peer, uint8_t ring_id)
  2930. {
  2931. struct dp_pdev *pdev = peer->vdev->pdev;
  2932. struct dp_soc *soc = NULL;
  2933. uint8_t mcs, pkt_type;
  2934. uint8_t tid = ts->tid;
  2935. uint32_t length;
  2936. struct cdp_tid_tx_stats *tid_stats;
  2937. if (!pdev)
  2938. return;
  2939. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2940. tid = CDP_MAX_DATA_TIDS - 1;
  2941. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2942. soc = pdev->soc;
  2943. mcs = ts->mcs;
  2944. pkt_type = ts->pkt_type;
  2945. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2946. dp_err("Release source is not from TQM");
  2947. return;
  2948. }
  2949. length = qdf_nbuf_len(tx_desc->nbuf);
  2950. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2951. if (qdf_unlikely(pdev->delay_stats_flag))
  2952. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2953. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2954. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2955. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2956. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2957. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2958. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2959. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2960. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2961. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2962. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2963. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2964. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2965. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2966. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2967. /*
  2968. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2969. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2970. * are no completions for failed cases. Hence updating tx_failed from
  2971. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2972. * then this has to be removed
  2973. */
  2974. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2975. peer->stats.tx.dropped.fw_rem_notx +
  2976. peer->stats.tx.dropped.fw_rem_tx +
  2977. peer->stats.tx.dropped.age_out +
  2978. peer->stats.tx.dropped.fw_reason1 +
  2979. peer->stats.tx.dropped.fw_reason2 +
  2980. peer->stats.tx.dropped.fw_reason3;
  2981. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2982. tid_stats->tqm_status_cnt[ts->status]++;
  2983. }
  2984. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2985. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  2986. return;
  2987. }
  2988. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2989. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2990. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2991. /*
  2992. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2993. * Return from here if HTT PPDU events are enabled.
  2994. */
  2995. if (!(soc->process_tx_status))
  2996. return;
  2997. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2998. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2999. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3000. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3001. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3002. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3003. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3004. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3005. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3006. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3007. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3008. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3009. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3010. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3011. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3012. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3013. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3014. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3015. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3016. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3017. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3018. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3019. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3020. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3021. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3022. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3023. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3024. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3025. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3026. &peer->stats, ts->peer_id,
  3027. UPDATE_PEER_STATS, pdev->pdev_id);
  3028. #endif
  3029. }
  3030. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3031. /**
  3032. * dp_tx_flow_pool_lock() - take flow pool lock
  3033. * @soc: core txrx main context
  3034. * @tx_desc: tx desc
  3035. *
  3036. * Return: None
  3037. */
  3038. static inline
  3039. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3040. struct dp_tx_desc_s *tx_desc)
  3041. {
  3042. struct dp_tx_desc_pool_s *pool;
  3043. uint8_t desc_pool_id;
  3044. desc_pool_id = tx_desc->pool_id;
  3045. pool = &soc->tx_desc[desc_pool_id];
  3046. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3047. }
  3048. /**
  3049. * dp_tx_flow_pool_unlock() - release flow pool lock
  3050. * @soc: core txrx main context
  3051. * @tx_desc: tx desc
  3052. *
  3053. * Return: None
  3054. */
  3055. static inline
  3056. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3057. struct dp_tx_desc_s *tx_desc)
  3058. {
  3059. struct dp_tx_desc_pool_s *pool;
  3060. uint8_t desc_pool_id;
  3061. desc_pool_id = tx_desc->pool_id;
  3062. pool = &soc->tx_desc[desc_pool_id];
  3063. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3064. }
  3065. #else
  3066. static inline
  3067. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3068. {
  3069. }
  3070. static inline
  3071. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3072. {
  3073. }
  3074. #endif
  3075. /**
  3076. * dp_tx_notify_completion() - Notify tx completion for this desc
  3077. * @soc: core txrx main context
  3078. * @vdev: datapath vdev handle
  3079. * @tx_desc: tx desc
  3080. * @netbuf: buffer
  3081. * @status: tx status
  3082. *
  3083. * Return: none
  3084. */
  3085. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3086. struct dp_vdev *vdev,
  3087. struct dp_tx_desc_s *tx_desc,
  3088. qdf_nbuf_t netbuf,
  3089. uint8_t status)
  3090. {
  3091. void *osif_dev;
  3092. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3093. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3094. qdf_assert(tx_desc);
  3095. dp_tx_flow_pool_lock(soc, tx_desc);
  3096. if (!vdev ||
  3097. !vdev->osif_vdev) {
  3098. dp_tx_flow_pool_unlock(soc, tx_desc);
  3099. return;
  3100. }
  3101. osif_dev = vdev->osif_vdev;
  3102. tx_compl_cbk = vdev->tx_comp;
  3103. dp_tx_flow_pool_unlock(soc, tx_desc);
  3104. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3105. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3106. if (tx_compl_cbk)
  3107. tx_compl_cbk(netbuf, osif_dev, flag);
  3108. }
  3109. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3110. * @pdev: pdev handle
  3111. * @tid: tid value
  3112. * @txdesc_ts: timestamp from txdesc
  3113. * @ppdu_id: ppdu id
  3114. *
  3115. * Return: none
  3116. */
  3117. #ifdef FEATURE_PERPKT_INFO
  3118. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3119. struct dp_peer *peer,
  3120. uint8_t tid,
  3121. uint64_t txdesc_ts,
  3122. uint32_t ppdu_id)
  3123. {
  3124. uint64_t delta_ms;
  3125. struct cdp_tx_sojourn_stats *sojourn_stats;
  3126. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3127. return;
  3128. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3129. tid >= CDP_DATA_TID_MAX))
  3130. return;
  3131. if (qdf_unlikely(!pdev->sojourn_buf))
  3132. return;
  3133. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3134. qdf_nbuf_data(pdev->sojourn_buf);
  3135. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3136. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3137. txdesc_ts;
  3138. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3139. delta_ms);
  3140. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3141. sojourn_stats->num_msdus[tid] = 1;
  3142. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3143. peer->avg_sojourn_msdu[tid].internal;
  3144. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3145. pdev->sojourn_buf, HTT_INVALID_PEER,
  3146. WDI_NO_VAL, pdev->pdev_id);
  3147. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3148. sojourn_stats->num_msdus[tid] = 0;
  3149. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3150. }
  3151. #else
  3152. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3153. struct dp_peer *peer,
  3154. uint8_t tid,
  3155. uint64_t txdesc_ts,
  3156. uint32_t ppdu_id)
  3157. {
  3158. }
  3159. #endif
  3160. /**
  3161. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3162. * @soc: DP Soc handle
  3163. * @tx_desc: software Tx descriptor
  3164. * @ts : Tx completion status from HAL/HTT descriptor
  3165. *
  3166. * Return: none
  3167. */
  3168. static inline void
  3169. dp_tx_comp_process_desc(struct dp_soc *soc,
  3170. struct dp_tx_desc_s *desc,
  3171. struct hal_tx_completion_status *ts,
  3172. struct dp_peer *peer)
  3173. {
  3174. uint64_t time_latency = 0;
  3175. /*
  3176. * m_copy/tx_capture modes are not supported for
  3177. * scatter gather packets
  3178. */
  3179. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3180. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3181. desc->timestamp);
  3182. }
  3183. if (!(desc->msdu_ext_desc)) {
  3184. if (QDF_STATUS_SUCCESS ==
  3185. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3186. return;
  3187. }
  3188. if (QDF_STATUS_SUCCESS ==
  3189. dp_get_completion_indication_for_stack(soc,
  3190. desc->pdev,
  3191. peer, ts,
  3192. desc->nbuf,
  3193. time_latency)) {
  3194. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3195. QDF_DMA_TO_DEVICE,
  3196. desc->nbuf->len);
  3197. dp_send_completion_to_stack(soc,
  3198. desc->pdev,
  3199. ts->peer_id,
  3200. ts->ppdu_id,
  3201. desc->nbuf);
  3202. return;
  3203. }
  3204. }
  3205. dp_tx_comp_free_buf(soc, desc);
  3206. }
  3207. #ifdef DISABLE_DP_STATS
  3208. /**
  3209. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3210. * @soc: core txrx main context
  3211. * @tx_desc: tx desc
  3212. * @status: tx status
  3213. *
  3214. * Return: none
  3215. */
  3216. static inline
  3217. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3218. struct dp_vdev *vdev,
  3219. struct dp_tx_desc_s *tx_desc,
  3220. uint8_t status)
  3221. {
  3222. }
  3223. #else
  3224. static inline
  3225. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3226. struct dp_vdev *vdev,
  3227. struct dp_tx_desc_s *tx_desc,
  3228. uint8_t status)
  3229. {
  3230. void *osif_dev;
  3231. ol_txrx_stats_rx_fp stats_cbk;
  3232. uint8_t pkt_type;
  3233. qdf_assert(tx_desc);
  3234. if (!vdev ||
  3235. !vdev->osif_vdev ||
  3236. !vdev->stats_cb)
  3237. return;
  3238. osif_dev = vdev->osif_vdev;
  3239. stats_cbk = vdev->stats_cb;
  3240. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3241. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3242. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3243. &pkt_type);
  3244. }
  3245. #endif
  3246. /**
  3247. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3248. * @soc: DP soc handle
  3249. * @tx_desc: software descriptor head pointer
  3250. * @ts: Tx completion status
  3251. * @peer: peer handle
  3252. * @ring_id: ring number
  3253. *
  3254. * Return: none
  3255. */
  3256. static inline
  3257. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3258. struct dp_tx_desc_s *tx_desc,
  3259. struct hal_tx_completion_status *ts,
  3260. struct dp_peer *peer, uint8_t ring_id)
  3261. {
  3262. uint32_t length;
  3263. qdf_ether_header_t *eh;
  3264. struct dp_vdev *vdev = NULL;
  3265. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3266. uint8_t dp_status;
  3267. if (!nbuf) {
  3268. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3269. goto out;
  3270. }
  3271. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3272. length = qdf_nbuf_len(nbuf);
  3273. dp_status = qdf_dp_get_status_from_htt(ts->status);
  3274. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3275. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3276. QDF_TRACE_DEFAULT_PDEV_ID,
  3277. qdf_nbuf_data_addr(nbuf),
  3278. sizeof(qdf_nbuf_data(nbuf)),
  3279. tx_desc->id,
  3280. dp_status));
  3281. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3282. "-------------------- \n"
  3283. "Tx Completion Stats: \n"
  3284. "-------------------- \n"
  3285. "ack_frame_rssi = %d \n"
  3286. "first_msdu = %d \n"
  3287. "last_msdu = %d \n"
  3288. "msdu_part_of_amsdu = %d \n"
  3289. "rate_stats valid = %d \n"
  3290. "bw = %d \n"
  3291. "pkt_type = %d \n"
  3292. "stbc = %d \n"
  3293. "ldpc = %d \n"
  3294. "sgi = %d \n"
  3295. "mcs = %d \n"
  3296. "ofdma = %d \n"
  3297. "tones_in_ru = %d \n"
  3298. "tsf = %d \n"
  3299. "ppdu_id = %d \n"
  3300. "transmit_cnt = %d \n"
  3301. "tid = %d \n"
  3302. "peer_id = %d\n",
  3303. ts->ack_frame_rssi, ts->first_msdu,
  3304. ts->last_msdu, ts->msdu_part_of_amsdu,
  3305. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3306. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3307. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3308. ts->transmit_cnt, ts->tid, ts->peer_id);
  3309. /* Update SoC level stats */
  3310. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3311. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3312. if (!peer) {
  3313. dp_err_rl("peer is null or deletion in progress");
  3314. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3315. goto out;
  3316. }
  3317. vdev = peer->vdev;
  3318. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3319. /* Update per-packet stats for mesh mode */
  3320. if (qdf_unlikely(vdev->mesh_vdev) &&
  3321. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3322. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3323. /* Update peer level stats */
  3324. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3325. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3326. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3327. if ((peer->vdev->tx_encap_type ==
  3328. htt_cmn_pkt_type_ethernet) &&
  3329. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3330. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3331. }
  3332. }
  3333. } else {
  3334. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3335. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3336. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3337. if (qdf_unlikely(peer->in_twt)) {
  3338. DP_STATS_INC_PKT(peer,
  3339. tx.tx_success_twt,
  3340. 1, length);
  3341. }
  3342. }
  3343. }
  3344. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3345. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3346. #ifdef QCA_SUPPORT_RDK_STATS
  3347. if (soc->rdkstats_enabled)
  3348. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3349. tx_desc->timestamp,
  3350. ts->ppdu_id);
  3351. #endif
  3352. out:
  3353. return;
  3354. }
  3355. /**
  3356. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3357. * @soc: core txrx main context
  3358. * @comp_head: software descriptor head pointer
  3359. * @ring_id: ring number
  3360. *
  3361. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3362. * and release the software descriptors after processing is complete
  3363. *
  3364. * Return: none
  3365. */
  3366. static void
  3367. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3368. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3369. {
  3370. struct dp_tx_desc_s *desc;
  3371. struct dp_tx_desc_s *next;
  3372. struct hal_tx_completion_status ts;
  3373. struct dp_peer *peer = NULL;
  3374. uint16_t peer_id = DP_INVALID_PEER;
  3375. qdf_nbuf_t netbuf;
  3376. desc = comp_head;
  3377. while (desc) {
  3378. if (peer_id != desc->peer_id) {
  3379. if (peer)
  3380. dp_peer_unref_delete(peer,
  3381. DP_MOD_ID_TX_COMP);
  3382. peer_id = desc->peer_id;
  3383. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3384. DP_MOD_ID_TX_COMP);
  3385. }
  3386. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3387. struct dp_pdev *pdev = desc->pdev;
  3388. if (qdf_likely(peer)) {
  3389. /*
  3390. * Increment peer statistics
  3391. * Minimal statistics update done here
  3392. */
  3393. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3394. desc->length);
  3395. if (desc->tx_status !=
  3396. HAL_TX_TQM_RR_FRAME_ACKED)
  3397. DP_STATS_INC(peer, tx.tx_failed, 1);
  3398. }
  3399. qdf_assert(pdev);
  3400. dp_tx_outstanding_dec(pdev);
  3401. /*
  3402. * Calling a QDF WRAPPER here is creating signifcant
  3403. * performance impact so avoided the wrapper call here
  3404. */
  3405. next = desc->next;
  3406. qdf_mem_unmap_nbytes_single(soc->osdev,
  3407. desc->dma_addr,
  3408. QDF_DMA_TO_DEVICE,
  3409. desc->length);
  3410. qdf_nbuf_free(desc->nbuf);
  3411. dp_tx_desc_free(soc, desc, desc->pool_id);
  3412. desc = next;
  3413. continue;
  3414. }
  3415. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3416. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3417. netbuf = desc->nbuf;
  3418. /* check tx complete notification */
  3419. if (peer &&
  3420. QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3421. dp_tx_notify_completion(soc, peer->vdev, desc,
  3422. netbuf, ts.status);
  3423. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3424. next = desc->next;
  3425. dp_tx_desc_release(desc, desc->pool_id);
  3426. desc = next;
  3427. }
  3428. if (peer)
  3429. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3430. }
  3431. /**
  3432. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3433. * @tx_desc: software descriptor head pointer
  3434. * @status : Tx completion status from HTT descriptor
  3435. * @ring_id: ring number
  3436. *
  3437. * This function will process HTT Tx indication messages from Target
  3438. *
  3439. * Return: none
  3440. */
  3441. static
  3442. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3443. uint8_t ring_id)
  3444. {
  3445. uint8_t tx_status;
  3446. struct dp_pdev *pdev;
  3447. struct dp_vdev *vdev;
  3448. struct dp_soc *soc;
  3449. struct hal_tx_completion_status ts = {0};
  3450. uint32_t *htt_desc = (uint32_t *)status;
  3451. struct dp_peer *peer;
  3452. struct cdp_tid_tx_stats *tid_stats = NULL;
  3453. struct htt_soc *htt_handle;
  3454. /*
  3455. * If the descriptor is already freed in vdev_detach,
  3456. * continue to next descriptor
  3457. */
  3458. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3459. QDF_TRACE(QDF_MODULE_ID_DP,
  3460. QDF_TRACE_LEVEL_INFO,
  3461. "Descriptor freed in vdev_detach %d",
  3462. tx_desc->id);
  3463. return;
  3464. }
  3465. pdev = tx_desc->pdev;
  3466. soc = pdev->soc;
  3467. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3468. QDF_TRACE(QDF_MODULE_ID_DP,
  3469. QDF_TRACE_LEVEL_INFO,
  3470. "pdev in down state %d",
  3471. tx_desc->id);
  3472. dp_tx_comp_free_buf(soc, tx_desc);
  3473. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3474. return;
  3475. }
  3476. qdf_assert(tx_desc->pdev);
  3477. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  3478. DP_MOD_ID_HTT_COMP);
  3479. if (!vdev)
  3480. return;
  3481. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3482. htt_handle = (struct htt_soc *)soc->htt_handle;
  3483. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3484. switch (tx_status) {
  3485. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3486. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3487. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3488. {
  3489. uint8_t tid;
  3490. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3491. ts.peer_id =
  3492. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3493. htt_desc[2]);
  3494. ts.tid =
  3495. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3496. htt_desc[2]);
  3497. } else {
  3498. ts.peer_id = HTT_INVALID_PEER;
  3499. ts.tid = HTT_INVALID_TID;
  3500. }
  3501. ts.ppdu_id =
  3502. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3503. htt_desc[1]);
  3504. ts.ack_frame_rssi =
  3505. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3506. htt_desc[1]);
  3507. ts.tsf = htt_desc[3];
  3508. ts.first_msdu = 1;
  3509. ts.last_msdu = 1;
  3510. tid = ts.tid;
  3511. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3512. tid = CDP_MAX_DATA_TIDS - 1;
  3513. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3514. if (qdf_unlikely(pdev->delay_stats_flag))
  3515. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3516. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3517. tid_stats->htt_status_cnt[tx_status]++;
  3518. }
  3519. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3520. DP_MOD_ID_HTT_COMP);
  3521. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3522. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3523. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3524. if (qdf_likely(peer))
  3525. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3526. break;
  3527. }
  3528. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3529. {
  3530. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3531. break;
  3532. }
  3533. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3534. {
  3535. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3536. break;
  3537. }
  3538. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3539. {
  3540. dp_tx_mec_handler(vdev, status);
  3541. break;
  3542. }
  3543. default:
  3544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3545. "%s Invalid HTT tx_status %d\n",
  3546. __func__, tx_status);
  3547. break;
  3548. }
  3549. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3550. }
  3551. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3552. static inline
  3553. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3554. {
  3555. bool limit_hit = false;
  3556. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3557. limit_hit =
  3558. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3559. if (limit_hit)
  3560. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3561. return limit_hit;
  3562. }
  3563. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3564. {
  3565. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3566. }
  3567. #else
  3568. static inline
  3569. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3570. {
  3571. return false;
  3572. }
  3573. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3574. {
  3575. return false;
  3576. }
  3577. #endif
  3578. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3579. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3580. uint32_t quota)
  3581. {
  3582. void *tx_comp_hal_desc;
  3583. uint8_t buffer_src;
  3584. uint8_t pool_id;
  3585. uint32_t tx_desc_id;
  3586. struct dp_tx_desc_s *tx_desc = NULL;
  3587. struct dp_tx_desc_s *head_desc = NULL;
  3588. struct dp_tx_desc_s *tail_desc = NULL;
  3589. uint32_t num_processed = 0;
  3590. uint32_t count;
  3591. uint32_t num_avail_for_reap = 0;
  3592. bool force_break = false;
  3593. DP_HIST_INIT();
  3594. more_data:
  3595. /* Re-initialize local variables to be re-used */
  3596. head_desc = NULL;
  3597. tail_desc = NULL;
  3598. count = 0;
  3599. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3600. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3601. return 0;
  3602. }
  3603. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3604. if (num_avail_for_reap >= quota)
  3605. num_avail_for_reap = quota;
  3606. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3607. /* Find head descriptor from completion ring */
  3608. while (qdf_likely(num_avail_for_reap)) {
  3609. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3610. if (qdf_unlikely(!tx_comp_hal_desc))
  3611. break;
  3612. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3613. /* If this buffer was not released by TQM or FW, then it is not
  3614. * Tx completion indication, assert */
  3615. if (qdf_unlikely(buffer_src !=
  3616. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3617. (qdf_unlikely(buffer_src !=
  3618. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3619. uint8_t wbm_internal_error;
  3620. dp_err_rl(
  3621. "Tx comp release_src != TQM | FW but from %d",
  3622. buffer_src);
  3623. hal_dump_comp_desc(tx_comp_hal_desc);
  3624. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3625. /* When WBM sees NULL buffer_addr_info in any of
  3626. * ingress rings it sends an error indication,
  3627. * with wbm_internal_error=1, to a specific ring.
  3628. * The WBM2SW ring used to indicate these errors is
  3629. * fixed in HW, and that ring is being used as Tx
  3630. * completion ring. These errors are not related to
  3631. * Tx completions, and should just be ignored
  3632. */
  3633. wbm_internal_error = hal_get_wbm_internal_error(
  3634. soc->hal_soc,
  3635. tx_comp_hal_desc);
  3636. if (wbm_internal_error) {
  3637. dp_err_rl("Tx comp wbm_internal_error!!");
  3638. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3639. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3640. buffer_src)
  3641. dp_handle_wbm_internal_error(
  3642. soc,
  3643. tx_comp_hal_desc,
  3644. hal_tx_comp_get_buffer_type(
  3645. tx_comp_hal_desc));
  3646. } else {
  3647. dp_err_rl("Tx comp wbm_internal_error false");
  3648. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3649. }
  3650. continue;
  3651. }
  3652. /* Get descriptor id */
  3653. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3654. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3655. DP_TX_DESC_ID_POOL_OS;
  3656. /* Find Tx descriptor */
  3657. tx_desc = dp_tx_desc_find(soc, pool_id,
  3658. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3659. DP_TX_DESC_ID_PAGE_OS,
  3660. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3661. DP_TX_DESC_ID_OFFSET_OS);
  3662. /*
  3663. * If the release source is FW, process the HTT status
  3664. */
  3665. if (qdf_unlikely(buffer_src ==
  3666. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3667. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3668. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3669. htt_tx_status);
  3670. dp_tx_process_htt_completion(tx_desc,
  3671. htt_tx_status, ring_id);
  3672. } else {
  3673. tx_desc->peer_id =
  3674. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3675. tx_desc->tx_status =
  3676. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3677. /*
  3678. * If the fast completion mode is enabled extended
  3679. * metadata from descriptor is not copied
  3680. */
  3681. if (qdf_likely(tx_desc->flags &
  3682. DP_TX_DESC_FLAG_SIMPLE))
  3683. goto add_to_pool;
  3684. /*
  3685. * If the descriptor is already freed in vdev_detach,
  3686. * continue to next descriptor
  3687. */
  3688. if (qdf_unlikely
  3689. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  3690. !tx_desc->flags)) {
  3691. QDF_TRACE(QDF_MODULE_ID_DP,
  3692. QDF_TRACE_LEVEL_INFO,
  3693. "Descriptor freed in vdev_detach %d",
  3694. tx_desc_id);
  3695. continue;
  3696. }
  3697. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3698. QDF_TRACE(QDF_MODULE_ID_DP,
  3699. QDF_TRACE_LEVEL_INFO,
  3700. "pdev in down state %d",
  3701. tx_desc_id);
  3702. dp_tx_comp_free_buf(soc, tx_desc);
  3703. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3704. goto next_desc;
  3705. }
  3706. /* Pool id is not matching. Error */
  3707. if (tx_desc->pool_id != pool_id) {
  3708. QDF_TRACE(QDF_MODULE_ID_DP,
  3709. QDF_TRACE_LEVEL_FATAL,
  3710. "Tx Comp pool id %d not matched %d",
  3711. pool_id, tx_desc->pool_id);
  3712. qdf_assert_always(0);
  3713. }
  3714. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3715. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3716. QDF_TRACE(QDF_MODULE_ID_DP,
  3717. QDF_TRACE_LEVEL_FATAL,
  3718. "Txdesc invalid, flgs = %x,id = %d",
  3719. tx_desc->flags, tx_desc_id);
  3720. qdf_assert_always(0);
  3721. }
  3722. /* Collect hw completion contents */
  3723. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3724. &tx_desc->comp, 1);
  3725. add_to_pool:
  3726. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3727. /* First ring descriptor on the cycle */
  3728. if (!head_desc) {
  3729. head_desc = tx_desc;
  3730. tail_desc = tx_desc;
  3731. }
  3732. tail_desc->next = tx_desc;
  3733. tx_desc->next = NULL;
  3734. tail_desc = tx_desc;
  3735. }
  3736. next_desc:
  3737. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3738. /*
  3739. * Processed packet count is more than given quota
  3740. * stop to processing
  3741. */
  3742. count++;
  3743. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3744. break;
  3745. }
  3746. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3747. /* Process the reaped descriptors */
  3748. if (head_desc)
  3749. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3750. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3751. if (num_processed >= quota)
  3752. force_break = true;
  3753. if (!force_break &&
  3754. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3755. hal_ring_hdl)) {
  3756. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3757. if (!hif_exec_should_yield(soc->hif_handle,
  3758. int_ctx->dp_intr_id))
  3759. goto more_data;
  3760. }
  3761. }
  3762. DP_TX_HIST_STATS_PER_PDEV();
  3763. return num_processed;
  3764. }
  3765. #ifdef FEATURE_WLAN_TDLS
  3766. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3767. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3768. {
  3769. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3770. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3771. DP_MOD_ID_TDLS);
  3772. if (!vdev) {
  3773. dp_err("vdev handle for id %d is NULL", vdev_id);
  3774. return NULL;
  3775. }
  3776. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3777. vdev->is_tdls_frame = true;
  3778. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  3779. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3780. }
  3781. #endif
  3782. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  3783. {
  3784. struct wlan_cfg_dp_soc_ctxt *cfg;
  3785. struct dp_soc *soc;
  3786. soc = vdev->pdev->soc;
  3787. if (!soc)
  3788. return;
  3789. cfg = soc->wlan_cfg_ctx;
  3790. if (!cfg)
  3791. return;
  3792. if (vdev->opmode == wlan_op_mode_ndi)
  3793. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  3794. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  3795. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  3796. (vdev->subtype == wlan_op_subtype_p2p_go))
  3797. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  3798. else
  3799. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  3800. }
  3801. /**
  3802. * dp_tx_vdev_attach() - attach vdev to dp tx
  3803. * @vdev: virtual device instance
  3804. *
  3805. * Return: QDF_STATUS_SUCCESS: success
  3806. * QDF_STATUS_E_RESOURCES: Error return
  3807. */
  3808. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3809. {
  3810. int pdev_id;
  3811. /*
  3812. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3813. */
  3814. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3815. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3816. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3817. vdev->vdev_id);
  3818. pdev_id =
  3819. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  3820. vdev->pdev->pdev_id);
  3821. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  3822. /*
  3823. * Set HTT Extension Valid bit to 0 by default
  3824. */
  3825. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3826. dp_tx_vdev_update_search_flags(vdev);
  3827. dp_tx_vdev_update_feature_flags(vdev);
  3828. return QDF_STATUS_SUCCESS;
  3829. }
  3830. #ifndef FEATURE_WDS
  3831. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3832. {
  3833. return false;
  3834. }
  3835. #endif
  3836. /**
  3837. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3838. * @vdev: virtual device instance
  3839. *
  3840. * Return: void
  3841. *
  3842. */
  3843. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3844. {
  3845. struct dp_soc *soc = vdev->pdev->soc;
  3846. /*
  3847. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3848. * for TDLS link
  3849. *
  3850. * Enable AddrY (SA based search) only for non-WDS STA and
  3851. * ProxySTA VAP (in HKv1) modes.
  3852. *
  3853. * In all other VAP modes, only DA based search should be
  3854. * enabled
  3855. */
  3856. if (vdev->opmode == wlan_op_mode_sta &&
  3857. vdev->tdls_link_connected)
  3858. vdev->hal_desc_addr_search_flags =
  3859. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3860. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3861. !dp_tx_da_search_override(vdev))
  3862. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3863. else
  3864. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3865. /* Set search type only when peer map v2 messaging is enabled
  3866. * as we will have the search index (AST hash) only when v2 is
  3867. * enabled
  3868. */
  3869. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3870. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3871. else
  3872. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3873. }
  3874. static inline bool
  3875. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3876. struct dp_vdev *vdev,
  3877. struct dp_tx_desc_s *tx_desc)
  3878. {
  3879. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3880. return false;
  3881. /*
  3882. * if vdev is given, then only check whether desc
  3883. * vdev match. if vdev is NULL, then check whether
  3884. * desc pdev match.
  3885. */
  3886. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  3887. (tx_desc->pdev == pdev);
  3888. }
  3889. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3890. /**
  3891. * dp_tx_desc_flush() - release resources associated
  3892. * to TX Desc
  3893. *
  3894. * @dp_pdev: Handle to DP pdev structure
  3895. * @vdev: virtual device instance
  3896. * NULL: no specific Vdev is required and check all allcated TX desc
  3897. * on this pdev.
  3898. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3899. *
  3900. * @force_free:
  3901. * true: flush the TX desc.
  3902. * false: only reset the Vdev in each allocated TX desc
  3903. * that associated to current Vdev.
  3904. *
  3905. * This function will go through the TX desc pool to flush
  3906. * the outstanding TX data or reset Vdev to NULL in associated TX
  3907. * Desc.
  3908. */
  3909. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3910. bool force_free)
  3911. {
  3912. uint8_t i;
  3913. uint32_t j;
  3914. uint32_t num_desc, page_id, offset;
  3915. uint16_t num_desc_per_page;
  3916. struct dp_soc *soc = pdev->soc;
  3917. struct dp_tx_desc_s *tx_desc = NULL;
  3918. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3919. if (!vdev && !force_free) {
  3920. dp_err("Reset TX desc vdev, Vdev param is required!");
  3921. return;
  3922. }
  3923. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3924. tx_desc_pool = &soc->tx_desc[i];
  3925. if (!(tx_desc_pool->pool_size) ||
  3926. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3927. !(tx_desc_pool->desc_pages.cacheable_pages))
  3928. continue;
  3929. /*
  3930. * Add flow pool lock protection in case pool is freed
  3931. * due to all tx_desc is recycled when handle TX completion.
  3932. * this is not necessary when do force flush as:
  3933. * a. double lock will happen if dp_tx_desc_release is
  3934. * also trying to acquire it.
  3935. * b. dp interrupt has been disabled before do force TX desc
  3936. * flush in dp_pdev_deinit().
  3937. */
  3938. if (!force_free)
  3939. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  3940. num_desc = tx_desc_pool->pool_size;
  3941. num_desc_per_page =
  3942. tx_desc_pool->desc_pages.num_element_per_page;
  3943. for (j = 0; j < num_desc; j++) {
  3944. page_id = j / num_desc_per_page;
  3945. offset = j % num_desc_per_page;
  3946. if (qdf_unlikely(!(tx_desc_pool->
  3947. desc_pages.cacheable_pages)))
  3948. break;
  3949. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3950. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3951. /*
  3952. * Free TX desc if force free is
  3953. * required, otherwise only reset vdev
  3954. * in this TX desc.
  3955. */
  3956. if (force_free) {
  3957. dp_tx_comp_free_buf(soc, tx_desc);
  3958. dp_tx_desc_release(tx_desc, i);
  3959. } else {
  3960. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  3961. }
  3962. }
  3963. }
  3964. if (!force_free)
  3965. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  3966. }
  3967. }
  3968. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3969. /**
  3970. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3971. *
  3972. * @soc: Handle to DP soc structure
  3973. * @tx_desc: pointer of one TX desc
  3974. * @desc_pool_id: TX Desc pool id
  3975. */
  3976. static inline void
  3977. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3978. uint8_t desc_pool_id)
  3979. {
  3980. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3981. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  3982. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3983. }
  3984. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3985. bool force_free)
  3986. {
  3987. uint8_t i, num_pool;
  3988. uint32_t j;
  3989. uint32_t num_desc, page_id, offset;
  3990. uint16_t num_desc_per_page;
  3991. struct dp_soc *soc = pdev->soc;
  3992. struct dp_tx_desc_s *tx_desc = NULL;
  3993. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3994. if (!vdev && !force_free) {
  3995. dp_err("Reset TX desc vdev, Vdev param is required!");
  3996. return;
  3997. }
  3998. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3999. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4000. for (i = 0; i < num_pool; i++) {
  4001. tx_desc_pool = &soc->tx_desc[i];
  4002. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4003. continue;
  4004. num_desc_per_page =
  4005. tx_desc_pool->desc_pages.num_element_per_page;
  4006. for (j = 0; j < num_desc; j++) {
  4007. page_id = j / num_desc_per_page;
  4008. offset = j % num_desc_per_page;
  4009. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4010. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4011. if (force_free) {
  4012. dp_tx_comp_free_buf(soc, tx_desc);
  4013. dp_tx_desc_release(tx_desc, i);
  4014. } else {
  4015. dp_tx_desc_reset_vdev(soc, tx_desc,
  4016. i);
  4017. }
  4018. }
  4019. }
  4020. }
  4021. }
  4022. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4023. /**
  4024. * dp_tx_vdev_detach() - detach vdev from dp tx
  4025. * @vdev: virtual device instance
  4026. *
  4027. * Return: QDF_STATUS_SUCCESS: success
  4028. * QDF_STATUS_E_RESOURCES: Error return
  4029. */
  4030. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4031. {
  4032. struct dp_pdev *pdev = vdev->pdev;
  4033. /* Reset TX desc associated to this Vdev as NULL */
  4034. dp_tx_desc_flush(pdev, vdev, false);
  4035. dp_tx_vdev_multipass_deinit(vdev);
  4036. return QDF_STATUS_SUCCESS;
  4037. }
  4038. /**
  4039. * dp_tx_pdev_attach() - attach pdev to dp tx
  4040. * @pdev: physical device instance
  4041. *
  4042. * Return: QDF_STATUS_SUCCESS: success
  4043. * QDF_STATUS_E_RESOURCES: Error return
  4044. */
  4045. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  4046. {
  4047. struct dp_soc *soc = pdev->soc;
  4048. /* Initialize Flow control counters */
  4049. qdf_atomic_init(&pdev->num_tx_outstanding);
  4050. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  4051. /* Initialize descriptors in TCL Ring */
  4052. hal_tx_init_data_ring(soc->hal_soc,
  4053. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  4054. }
  4055. return QDF_STATUS_SUCCESS;
  4056. }
  4057. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4058. /* Pools will be allocated dynamically */
  4059. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4060. int num_desc)
  4061. {
  4062. uint8_t i;
  4063. for (i = 0; i < num_pool; i++) {
  4064. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4065. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4066. }
  4067. return QDF_STATUS_SUCCESS;
  4068. }
  4069. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4070. int num_desc)
  4071. {
  4072. return QDF_STATUS_SUCCESS;
  4073. }
  4074. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4075. {
  4076. }
  4077. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4078. {
  4079. uint8_t i;
  4080. for (i = 0; i < num_pool; i++)
  4081. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4082. }
  4083. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4084. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4085. int num_desc)
  4086. {
  4087. uint8_t i, count;
  4088. /* Allocate software Tx descriptor pools */
  4089. for (i = 0; i < num_pool; i++) {
  4090. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4091. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4092. FL("Tx Desc Pool alloc %d failed %pK"),
  4093. i, soc);
  4094. goto fail;
  4095. }
  4096. }
  4097. return QDF_STATUS_SUCCESS;
  4098. fail:
  4099. for (count = 0; count < i; count++)
  4100. dp_tx_desc_pool_free(soc, count);
  4101. return QDF_STATUS_E_NOMEM;
  4102. }
  4103. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4104. int num_desc)
  4105. {
  4106. uint8_t i;
  4107. for (i = 0; i < num_pool; i++) {
  4108. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4109. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4110. FL("Tx Desc Pool init %d failed %pK"),
  4111. i, soc);
  4112. return QDF_STATUS_E_NOMEM;
  4113. }
  4114. }
  4115. return QDF_STATUS_SUCCESS;
  4116. }
  4117. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4118. {
  4119. uint8_t i;
  4120. for (i = 0; i < num_pool; i++)
  4121. dp_tx_desc_pool_deinit(soc, i);
  4122. }
  4123. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4124. {
  4125. uint8_t i;
  4126. for (i = 0; i < num_pool; i++)
  4127. dp_tx_desc_pool_free(soc, i);
  4128. }
  4129. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4130. /**
  4131. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4132. * @soc: core txrx main context
  4133. * @num_pool: number of pools
  4134. *
  4135. */
  4136. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4137. {
  4138. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4139. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4140. }
  4141. /**
  4142. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4143. * @soc: core txrx main context
  4144. * @num_pool: number of pools
  4145. *
  4146. */
  4147. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4148. {
  4149. dp_tx_tso_desc_pool_free(soc, num_pool);
  4150. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4151. }
  4152. /**
  4153. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4154. * @soc: core txrx main context
  4155. *
  4156. * This function frees all tx related descriptors as below
  4157. * 1. Regular TX descriptors (static pools)
  4158. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4159. * 3. TSO descriptors
  4160. *
  4161. */
  4162. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4163. {
  4164. uint8_t num_pool;
  4165. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4166. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4167. dp_tx_ext_desc_pool_free(soc, num_pool);
  4168. dp_tx_delete_static_pools(soc, num_pool);
  4169. }
  4170. /**
  4171. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4172. * @soc: core txrx main context
  4173. *
  4174. * This function de-initializes all tx related descriptors as below
  4175. * 1. Regular TX descriptors (static pools)
  4176. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4177. * 3. TSO descriptors
  4178. *
  4179. */
  4180. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4181. {
  4182. uint8_t num_pool;
  4183. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4184. dp_tx_flow_control_deinit(soc);
  4185. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4186. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4187. dp_tx_deinit_static_pools(soc, num_pool);
  4188. }
  4189. /**
  4190. * dp_tso_attach() - TSO attach handler
  4191. * @txrx_soc: Opaque Dp handle
  4192. *
  4193. * Reserve TSO descriptor buffers
  4194. *
  4195. * Return: QDF_STATUS_E_FAILURE on failure or
  4196. * QDF_STATUS_SUCCESS on success
  4197. */
  4198. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4199. uint8_t num_pool,
  4200. uint16_t num_desc)
  4201. {
  4202. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4203. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4204. return QDF_STATUS_E_FAILURE;
  4205. }
  4206. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4207. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4208. num_pool, soc);
  4209. return QDF_STATUS_E_FAILURE;
  4210. }
  4211. return QDF_STATUS_SUCCESS;
  4212. }
  4213. /**
  4214. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4215. * @soc: DP soc handle
  4216. * @num_pool: Number of pools
  4217. * @num_desc: Number of descriptors
  4218. *
  4219. * Initialize TSO descriptor pools
  4220. *
  4221. * Return: QDF_STATUS_E_FAILURE on failure or
  4222. * QDF_STATUS_SUCCESS on success
  4223. */
  4224. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4225. uint8_t num_pool,
  4226. uint16_t num_desc)
  4227. {
  4228. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4229. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4230. return QDF_STATUS_E_FAILURE;
  4231. }
  4232. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4233. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4234. num_pool, soc);
  4235. return QDF_STATUS_E_FAILURE;
  4236. }
  4237. return QDF_STATUS_SUCCESS;
  4238. }
  4239. /**
  4240. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4241. * @soc: core txrx main context
  4242. *
  4243. * This function allocates memory for following descriptor pools
  4244. * 1. regular sw tx descriptor pools (static pools)
  4245. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4246. * 3. TSO descriptor pools
  4247. *
  4248. * Return: QDF_STATUS_SUCCESS: success
  4249. * QDF_STATUS_E_RESOURCES: Error return
  4250. */
  4251. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4252. {
  4253. uint8_t num_pool;
  4254. uint32_t num_desc;
  4255. uint32_t num_ext_desc;
  4256. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4257. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4258. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4259. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4260. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4261. __func__, num_pool, num_desc);
  4262. if ((num_pool > MAX_TXDESC_POOLS) ||
  4263. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4264. goto fail1;
  4265. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4266. goto fail1;
  4267. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4268. goto fail2;
  4269. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4270. return QDF_STATUS_SUCCESS;
  4271. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4272. goto fail3;
  4273. return QDF_STATUS_SUCCESS;
  4274. fail3:
  4275. dp_tx_ext_desc_pool_free(soc, num_pool);
  4276. fail2:
  4277. dp_tx_delete_static_pools(soc, num_pool);
  4278. fail1:
  4279. return QDF_STATUS_E_RESOURCES;
  4280. }
  4281. /**
  4282. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4283. * @soc: core txrx main context
  4284. *
  4285. * This function initializes the following TX descriptor pools
  4286. * 1. regular sw tx descriptor pools (static pools)
  4287. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4288. * 3. TSO descriptor pools
  4289. *
  4290. * Return: QDF_STATUS_SUCCESS: success
  4291. * QDF_STATUS_E_RESOURCES: Error return
  4292. */
  4293. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4294. {
  4295. uint8_t num_pool;
  4296. uint32_t num_desc;
  4297. uint32_t num_ext_desc;
  4298. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4299. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4300. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4301. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4302. goto fail1;
  4303. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4304. goto fail2;
  4305. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4306. return QDF_STATUS_SUCCESS;
  4307. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4308. goto fail3;
  4309. dp_tx_flow_control_init(soc);
  4310. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4311. return QDF_STATUS_SUCCESS;
  4312. fail3:
  4313. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4314. fail2:
  4315. dp_tx_deinit_static_pools(soc, num_pool);
  4316. fail1:
  4317. return QDF_STATUS_E_RESOURCES;
  4318. }
  4319. /**
  4320. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4321. * @txrx_soc: dp soc handle
  4322. *
  4323. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4324. * QDF_STATUS_E_FAILURE
  4325. */
  4326. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4327. {
  4328. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4329. uint8_t num_pool;
  4330. uint32_t num_desc;
  4331. uint32_t num_ext_desc;
  4332. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4333. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4334. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4335. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4336. return QDF_STATUS_E_FAILURE;
  4337. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4338. return QDF_STATUS_E_FAILURE;
  4339. return QDF_STATUS_SUCCESS;
  4340. }
  4341. /**
  4342. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4343. * @txrx_soc: dp soc handle
  4344. *
  4345. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4346. */
  4347. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4348. {
  4349. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4350. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4351. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4352. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4353. return QDF_STATUS_SUCCESS;
  4354. }