dsi_drm.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <drm/drm_atomic_helper.h>
  6. #include <drm/drm_atomic.h>
  7. #include "msm_kms.h"
  8. #include "sde_connector.h"
  9. #include "dsi_drm.h"
  10. #include "sde_trace.h"
  11. #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
  12. #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
  13. #define DEFAULT_PANEL_JITTER_NUMERATOR 2
  14. #define DEFAULT_PANEL_JITTER_DENOMINATOR 1
  15. #define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
  16. #define DEFAULT_PANEL_PREFILL_LINES 25
  17. static struct dsi_display_mode_priv_info default_priv_info = {
  18. .panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR,
  19. .panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR,
  20. .panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES,
  21. .dsc_enabled = false,
  22. };
  23. static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
  24. struct dsi_display_mode *dsi_mode)
  25. {
  26. memset(dsi_mode, 0, sizeof(*dsi_mode));
  27. dsi_mode->timing.h_active = drm_mode->hdisplay;
  28. dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
  29. dsi_mode->timing.h_sync_width = drm_mode->htotal -
  30. (drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
  31. dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
  32. drm_mode->hdisplay;
  33. dsi_mode->timing.h_skew = drm_mode->hskew;
  34. dsi_mode->timing.v_active = drm_mode->vdisplay;
  35. dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
  36. dsi_mode->timing.v_sync_width = drm_mode->vtotal -
  37. (drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
  38. dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
  39. drm_mode->vdisplay;
  40. dsi_mode->timing.refresh_rate = drm_mode->vrefresh;
  41. dsi_mode->pixel_clk_khz = drm_mode->clock;
  42. dsi_mode->priv_info =
  43. (struct dsi_display_mode_priv_info *)drm_mode->private;
  44. if (dsi_mode->priv_info) {
  45. dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;
  46. dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;
  47. }
  48. if (msm_is_mode_seamless(drm_mode))
  49. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
  50. if (msm_is_mode_dynamic_fps(drm_mode))
  51. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS;
  52. if (msm_needs_vblank_pre_modeset(drm_mode))
  53. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  54. if (msm_is_mode_seamless_dms(drm_mode))
  55. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  56. if (msm_is_mode_seamless_vrr(drm_mode))
  57. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  58. if (msm_is_mode_seamless_poms(drm_mode))
  59. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  60. if (msm_is_mode_seamless_dyn_clk(drm_mode))
  61. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK;
  62. dsi_mode->timing.h_sync_polarity =
  63. !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC);
  64. dsi_mode->timing.v_sync_polarity =
  65. !!(drm_mode->flags & DRM_MODE_FLAG_PVSYNC);
  66. if (drm_mode->flags & DRM_MODE_FLAG_VID_MODE_PANEL)
  67. dsi_mode->panel_mode = DSI_OP_VIDEO_MODE;
  68. if (drm_mode->flags & DRM_MODE_FLAG_CMD_MODE_PANEL)
  69. dsi_mode->panel_mode = DSI_OP_CMD_MODE;
  70. }
  71. void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
  72. struct drm_display_mode *drm_mode)
  73. {
  74. bool video_mode = (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE);
  75. memset(drm_mode, 0, sizeof(*drm_mode));
  76. drm_mode->hdisplay = dsi_mode->timing.h_active;
  77. drm_mode->hsync_start = drm_mode->hdisplay +
  78. dsi_mode->timing.h_front_porch;
  79. drm_mode->hsync_end = drm_mode->hsync_start +
  80. dsi_mode->timing.h_sync_width;
  81. drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
  82. drm_mode->hskew = dsi_mode->timing.h_skew;
  83. drm_mode->vdisplay = dsi_mode->timing.v_active;
  84. drm_mode->vsync_start = drm_mode->vdisplay +
  85. dsi_mode->timing.v_front_porch;
  86. drm_mode->vsync_end = drm_mode->vsync_start +
  87. dsi_mode->timing.v_sync_width;
  88. drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
  89. drm_mode->vrefresh = dsi_mode->timing.refresh_rate;
  90. drm_mode->clock = dsi_mode->pixel_clk_khz;
  91. drm_mode->private = (int *)dsi_mode->priv_info;
  92. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
  93. drm_mode->flags |= DRM_MODE_FLAG_SEAMLESS;
  94. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
  95. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
  96. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
  97. drm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
  98. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
  99. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS;
  100. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)
  101. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR;
  102. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)
  103. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS;
  104. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)
  105. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK;
  106. if (dsi_mode->timing.h_sync_polarity)
  107. drm_mode->flags |= DRM_MODE_FLAG_PHSYNC;
  108. if (dsi_mode->timing.v_sync_polarity)
  109. drm_mode->flags |= DRM_MODE_FLAG_PVSYNC;
  110. if (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE)
  111. drm_mode->flags |= DRM_MODE_FLAG_VID_MODE_PANEL;
  112. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  113. drm_mode->flags |= DRM_MODE_FLAG_CMD_MODE_PANEL;
  114. /* set mode name */
  115. snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%dx%d%s",
  116. drm_mode->hdisplay, drm_mode->vdisplay,
  117. drm_mode->vrefresh, drm_mode->clock,
  118. video_mode ? "vid" : "cmd");
  119. }
  120. static int dsi_bridge_attach(struct drm_bridge *bridge)
  121. {
  122. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  123. if (!bridge) {
  124. DSI_ERR("Invalid params\n");
  125. return -EINVAL;
  126. }
  127. DSI_DEBUG("[%d] attached\n", c_bridge->id);
  128. return 0;
  129. }
  130. static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
  131. {
  132. int rc = 0;
  133. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  134. if (!bridge) {
  135. DSI_ERR("Invalid params\n");
  136. return;
  137. }
  138. if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
  139. DSI_ERR("Incorrect bridge details\n");
  140. return;
  141. }
  142. atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
  143. /* By this point mode should have been validated through mode_fixup */
  144. rc = dsi_display_set_mode(c_bridge->display,
  145. &(c_bridge->dsi_mode), 0x0);
  146. if (rc) {
  147. DSI_ERR("[%d] failed to perform a mode set, rc=%d\n",
  148. c_bridge->id, rc);
  149. return;
  150. }
  151. if (c_bridge->dsi_mode.dsi_mode_flags &
  152. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  153. DSI_MODE_FLAG_DYN_CLK)) {
  154. DSI_DEBUG("[%d] seamless pre-enable\n", c_bridge->id);
  155. return;
  156. }
  157. SDE_ATRACE_BEGIN("dsi_display_prepare");
  158. rc = dsi_display_prepare(c_bridge->display);
  159. if (rc) {
  160. DSI_ERR("[%d] DSI display prepare failed, rc=%d\n",
  161. c_bridge->id, rc);
  162. SDE_ATRACE_END("dsi_display_prepare");
  163. return;
  164. }
  165. SDE_ATRACE_END("dsi_display_prepare");
  166. SDE_ATRACE_BEGIN("dsi_display_enable");
  167. rc = dsi_display_enable(c_bridge->display);
  168. if (rc) {
  169. DSI_ERR("[%d] DSI display enable failed, rc=%d\n",
  170. c_bridge->id, rc);
  171. (void)dsi_display_unprepare(c_bridge->display);
  172. }
  173. SDE_ATRACE_END("dsi_display_enable");
  174. rc = dsi_display_splash_res_cleanup(c_bridge->display);
  175. if (rc)
  176. DSI_ERR("Continuous splash pipeline cleanup failed, rc=%d\n",
  177. rc);
  178. }
  179. static void dsi_bridge_enable(struct drm_bridge *bridge)
  180. {
  181. int rc = 0;
  182. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  183. struct dsi_display *display;
  184. if (!bridge) {
  185. DSI_ERR("Invalid params\n");
  186. return;
  187. }
  188. if (c_bridge->dsi_mode.dsi_mode_flags &
  189. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  190. DSI_MODE_FLAG_DYN_CLK)) {
  191. DSI_DEBUG("[%d] seamless enable\n", c_bridge->id);
  192. return;
  193. }
  194. display = c_bridge->display;
  195. rc = dsi_display_post_enable(display);
  196. if (rc)
  197. DSI_ERR("[%d] DSI display post enabled failed, rc=%d\n",
  198. c_bridge->id, rc);
  199. if (display && display->drm_conn) {
  200. sde_connector_helper_bridge_enable(display->drm_conn);
  201. if (c_bridge->dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)
  202. sde_connector_schedule_status_work(display->drm_conn,
  203. true);
  204. }
  205. }
  206. static void dsi_bridge_disable(struct drm_bridge *bridge)
  207. {
  208. int rc = 0;
  209. int private_flags;
  210. struct dsi_display *display;
  211. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  212. if (!bridge) {
  213. DSI_ERR("Invalid params\n");
  214. return;
  215. }
  216. display = c_bridge->display;
  217. private_flags =
  218. bridge->encoder->crtc->state->adjusted_mode.private_flags;
  219. if (display && display->drm_conn) {
  220. display->poms_pending =
  221. private_flags & MSM_MODE_FLAG_SEAMLESS_POMS;
  222. sde_connector_helper_bridge_disable(display->drm_conn);
  223. }
  224. rc = dsi_display_pre_disable(c_bridge->display);
  225. if (rc) {
  226. DSI_ERR("[%d] DSI display pre disable failed, rc=%d\n",
  227. c_bridge->id, rc);
  228. }
  229. }
  230. static void dsi_bridge_post_disable(struct drm_bridge *bridge)
  231. {
  232. int rc = 0;
  233. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  234. if (!bridge) {
  235. DSI_ERR("Invalid params\n");
  236. return;
  237. }
  238. SDE_ATRACE_BEGIN("dsi_bridge_post_disable");
  239. SDE_ATRACE_BEGIN("dsi_display_disable");
  240. rc = dsi_display_disable(c_bridge->display);
  241. if (rc) {
  242. DSI_ERR("[%d] DSI display disable failed, rc=%d\n",
  243. c_bridge->id, rc);
  244. SDE_ATRACE_END("dsi_display_disable");
  245. return;
  246. }
  247. SDE_ATRACE_END("dsi_display_disable");
  248. rc = dsi_display_unprepare(c_bridge->display);
  249. if (rc) {
  250. DSI_ERR("[%d] DSI display unprepare failed, rc=%d\n",
  251. c_bridge->id, rc);
  252. SDE_ATRACE_END("dsi_bridge_post_disable");
  253. return;
  254. }
  255. SDE_ATRACE_END("dsi_bridge_post_disable");
  256. }
  257. static void dsi_bridge_mode_set(struct drm_bridge *bridge,
  258. const struct drm_display_mode *mode,
  259. const struct drm_display_mode *adjusted_mode)
  260. {
  261. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  262. if (!bridge || !mode || !adjusted_mode) {
  263. DSI_ERR("Invalid params\n");
  264. return;
  265. }
  266. memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
  267. convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
  268. /* restore bit_clk_rate also for dynamic clk use cases */
  269. c_bridge->dsi_mode.timing.clk_rate_hz =
  270. dsi_drm_find_bit_clk_rate(c_bridge->display, adjusted_mode);
  271. DSI_DEBUG("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz);
  272. }
  273. static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
  274. const struct drm_display_mode *mode,
  275. struct drm_display_mode *adjusted_mode)
  276. {
  277. int rc = 0;
  278. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  279. struct dsi_display *display;
  280. struct dsi_display_mode dsi_mode, cur_dsi_mode, *panel_dsi_mode;
  281. struct drm_crtc_state *crtc_state;
  282. crtc_state = container_of(mode, struct drm_crtc_state, mode);
  283. if (!bridge || !mode || !adjusted_mode) {
  284. DSI_ERR("Invalid params\n");
  285. return false;
  286. }
  287. display = c_bridge->display;
  288. if (!display) {
  289. DSI_ERR("Invalid params\n");
  290. return false;
  291. }
  292. /*
  293. * if no timing defined in panel, it must be external mode
  294. * and we'll use empty priv info to populate the mode
  295. */
  296. if (display->panel && !display->panel->num_timing_nodes) {
  297. *adjusted_mode = *mode;
  298. adjusted_mode->private = (int *)&default_priv_info;
  299. adjusted_mode->private_flags = 0;
  300. return true;
  301. }
  302. convert_to_dsi_mode(mode, &dsi_mode);
  303. /*
  304. * retrieve dsi mode from dsi driver's cache since not safe to take
  305. * the drm mode config mutex in all paths
  306. */
  307. rc = dsi_display_find_mode(display, &dsi_mode, &panel_dsi_mode);
  308. if (rc)
  309. return rc;
  310. /* propagate the private info to the adjusted_mode derived dsi mode */
  311. dsi_mode.priv_info = panel_dsi_mode->priv_info;
  312. dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;
  313. dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;
  314. dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  315. rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
  316. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  317. if (rc) {
  318. DSI_ERR("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
  319. return false;
  320. }
  321. if (bridge->encoder && bridge->encoder->crtc &&
  322. crtc_state->crtc) {
  323. const struct drm_display_mode *cur_mode =
  324. &crtc_state->crtc->state->mode;
  325. convert_to_dsi_mode(cur_mode, &cur_dsi_mode);
  326. cur_dsi_mode.timing.dsc_enabled =
  327. dsi_mode.priv_info->dsc_enabled;
  328. cur_dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  329. rc = dsi_display_validate_mode_change(c_bridge->display,
  330. &cur_dsi_mode, &dsi_mode);
  331. if (rc) {
  332. DSI_ERR("[%s] seamless mode mismatch failure rc=%d\n",
  333. c_bridge->display->name, rc);
  334. return false;
  335. }
  336. /* No panel mode switch when drm pipeline is changing */
  337. if ((dsi_mode.panel_mode != cur_dsi_mode.panel_mode) &&
  338. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  339. (crtc_state->enable ==
  340. crtc_state->crtc->state->enable))
  341. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  342. /* No DMS/VRR when drm pipeline is changing */
  343. if (!drm_mode_equal(cur_mode, adjusted_mode) &&
  344. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  345. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)) &&
  346. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
  347. (!crtc_state->active_changed ||
  348. display->is_cont_splash_enabled))
  349. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  350. }
  351. /* Reject seamless transition when active changed */
  352. if (crtc_state->active_changed &&
  353. ((dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) ||
  354. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS) ||
  355. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))) {
  356. DSI_ERR("seamless upon active changed 0x%x %d\n",
  357. dsi_mode.dsi_mode_flags, crtc_state->active_changed);
  358. return false;
  359. }
  360. /* convert back to drm mode, propagating the private info & flags */
  361. dsi_convert_to_drm_mode(&dsi_mode, adjusted_mode);
  362. return true;
  363. }
  364. u64 dsi_drm_find_bit_clk_rate(void *display,
  365. const struct drm_display_mode *drm_mode)
  366. {
  367. int i = 0, count = 0;
  368. struct dsi_display *dsi_display = display;
  369. struct dsi_display_mode *dsi_mode;
  370. u64 bit_clk_rate = 0;
  371. if (!dsi_display || !drm_mode)
  372. return 0;
  373. dsi_display_get_mode_count(dsi_display, &count);
  374. for (i = 0; i < count; i++) {
  375. dsi_mode = &dsi_display->modes[i];
  376. if ((dsi_mode->timing.v_active == drm_mode->vdisplay) &&
  377. (dsi_mode->timing.h_active == drm_mode->hdisplay) &&
  378. (dsi_mode->pixel_clk_khz == drm_mode->clock) &&
  379. (dsi_mode->timing.refresh_rate == drm_mode->vrefresh)) {
  380. bit_clk_rate = dsi_mode->timing.clk_rate_hz;
  381. break;
  382. }
  383. }
  384. return bit_clk_rate;
  385. }
  386. int dsi_conn_get_mode_info(struct drm_connector *connector,
  387. const struct drm_display_mode *drm_mode,
  388. struct msm_mode_info *mode_info,
  389. void *display, const struct msm_resource_caps_info *avail_res)
  390. {
  391. struct dsi_display_mode dsi_mode;
  392. struct dsi_mode_info *timing;
  393. int chroma_format;
  394. int src_bpp, tar_bpp;
  395. if (!drm_mode || !mode_info)
  396. return -EINVAL;
  397. convert_to_dsi_mode(drm_mode, &dsi_mode);
  398. if (!dsi_mode.priv_info)
  399. return -EINVAL;
  400. memset(mode_info, 0, sizeof(*mode_info));
  401. timing = &dsi_mode.timing;
  402. mode_info->frame_rate = dsi_mode.timing.refresh_rate;
  403. mode_info->vtotal = DSI_V_TOTAL(timing);
  404. mode_info->prefill_lines = dsi_mode.priv_info->panel_prefill_lines;
  405. mode_info->jitter_numer = dsi_mode.priv_info->panel_jitter_numer;
  406. mode_info->jitter_denom = dsi_mode.priv_info->panel_jitter_denom;
  407. mode_info->clk_rate = dsi_drm_find_bit_clk_rate(display, drm_mode);
  408. mode_info->mdp_transfer_time_us =
  409. dsi_mode.priv_info->mdp_transfer_time_us;
  410. memcpy(&mode_info->topology, &dsi_mode.priv_info->topology,
  411. sizeof(struct msm_display_topology));
  412. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  413. if (dsi_mode.priv_info->dsc_enabled) {
  414. chroma_format = dsi_mode.priv_info->dsc.chroma_format;
  415. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  416. memcpy(&mode_info->comp_info.dsc_info, &dsi_mode.priv_info->dsc,
  417. sizeof(dsi_mode.priv_info->dsc));
  418. tar_bpp = dsi_mode.priv_info->dsc.config.bits_per_pixel >> 4;
  419. src_bpp = msm_get_src_bpc(chroma_format,
  420. dsi_mode.priv_info->dsc.config.bits_per_component);
  421. mode_info->comp_info.comp_ratio = mult_frac(1, src_bpp,
  422. tar_bpp);
  423. } else if (dsi_mode.priv_info->vdc_enabled) {
  424. chroma_format = dsi_mode.priv_info->vdc.chroma_format;
  425. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_VDC;
  426. memcpy(&mode_info->comp_info.vdc_info, &dsi_mode.priv_info->vdc,
  427. sizeof(dsi_mode.priv_info->vdc));
  428. tar_bpp = dsi_mode.priv_info->vdc.bits_per_pixel >> 4;
  429. src_bpp = msm_get_src_bpc(chroma_format,
  430. dsi_mode.priv_info->vdc.bits_per_component);
  431. mode_info->comp_info.comp_ratio = mult_frac(1, src_bpp,
  432. tar_bpp);
  433. }
  434. if (dsi_mode.priv_info->roi_caps.enabled) {
  435. memcpy(&mode_info->roi_caps, &dsi_mode.priv_info->roi_caps,
  436. sizeof(dsi_mode.priv_info->roi_caps));
  437. }
  438. return 0;
  439. }
  440. static const struct drm_bridge_funcs dsi_bridge_ops = {
  441. .attach = dsi_bridge_attach,
  442. .mode_fixup = dsi_bridge_mode_fixup,
  443. .pre_enable = dsi_bridge_pre_enable,
  444. .enable = dsi_bridge_enable,
  445. .disable = dsi_bridge_disable,
  446. .post_disable = dsi_bridge_post_disable,
  447. .mode_set = dsi_bridge_mode_set,
  448. };
  449. int dsi_conn_set_info_blob(struct drm_connector *connector,
  450. void *info, void *display, struct msm_mode_info *mode_info)
  451. {
  452. struct dsi_display *dsi_display = display;
  453. struct dsi_panel *panel;
  454. enum dsi_pixel_format fmt;
  455. u32 bpp;
  456. if (!info || !dsi_display)
  457. return -EINVAL;
  458. dsi_display->drm_conn = connector;
  459. sde_kms_info_add_keystr(info,
  460. "display type", dsi_display->display_type);
  461. switch (dsi_display->type) {
  462. case DSI_DISPLAY_SINGLE:
  463. sde_kms_info_add_keystr(info, "display config",
  464. "single display");
  465. break;
  466. case DSI_DISPLAY_EXT_BRIDGE:
  467. sde_kms_info_add_keystr(info, "display config", "ext bridge");
  468. break;
  469. case DSI_DISPLAY_SPLIT:
  470. sde_kms_info_add_keystr(info, "display config",
  471. "split display");
  472. break;
  473. case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
  474. sde_kms_info_add_keystr(info, "display config",
  475. "split ext bridge");
  476. break;
  477. default:
  478. DSI_DEBUG("invalid display type:%d\n", dsi_display->type);
  479. break;
  480. }
  481. if (!dsi_display->panel) {
  482. DSI_DEBUG("invalid panel data\n");
  483. goto end;
  484. }
  485. panel = dsi_display->panel;
  486. sde_kms_info_add_keystr(info, "panel name", panel->name);
  487. switch (panel->panel_mode) {
  488. case DSI_OP_VIDEO_MODE:
  489. sde_kms_info_add_keystr(info, "panel mode", "video");
  490. sde_kms_info_add_keystr(info, "qsync support",
  491. panel->qsync_min_fps ? "true" : "false");
  492. break;
  493. case DSI_OP_CMD_MODE:
  494. sde_kms_info_add_keystr(info, "panel mode", "command");
  495. sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
  496. mode_info->mdp_transfer_time_us);
  497. sde_kms_info_add_keystr(info, "qsync support",
  498. panel->qsync_min_fps ? "true" : "false");
  499. break;
  500. default:
  501. DSI_DEBUG("invalid panel type:%d\n", panel->panel_mode);
  502. break;
  503. }
  504. sde_kms_info_add_keystr(info, "dfps support",
  505. panel->dfps_caps.dfps_support ? "true" : "false");
  506. if (panel->dfps_caps.dfps_support) {
  507. sde_kms_info_add_keyint(info, "min_fps",
  508. panel->dfps_caps.min_refresh_rate);
  509. sde_kms_info_add_keyint(info, "max_fps",
  510. panel->dfps_caps.max_refresh_rate);
  511. }
  512. sde_kms_info_add_keystr(info, "dyn bitclk support",
  513. panel->dyn_clk_caps.dyn_clk_support ? "true" : "false");
  514. switch (panel->phy_props.rotation) {
  515. case DSI_PANEL_ROTATE_NONE:
  516. sde_kms_info_add_keystr(info, "panel orientation", "none");
  517. break;
  518. case DSI_PANEL_ROTATE_H_FLIP:
  519. sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
  520. break;
  521. case DSI_PANEL_ROTATE_V_FLIP:
  522. sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
  523. break;
  524. case DSI_PANEL_ROTATE_HV_FLIP:
  525. sde_kms_info_add_keystr(info, "panel orientation",
  526. "horz & vert flip");
  527. break;
  528. default:
  529. DSI_DEBUG("invalid panel rotation:%d\n",
  530. panel->phy_props.rotation);
  531. break;
  532. }
  533. switch (panel->bl_config.type) {
  534. case DSI_BACKLIGHT_PWM:
  535. sde_kms_info_add_keystr(info, "backlight type", "pwm");
  536. break;
  537. case DSI_BACKLIGHT_WLED:
  538. sde_kms_info_add_keystr(info, "backlight type", "wled");
  539. break;
  540. case DSI_BACKLIGHT_DCS:
  541. sde_kms_info_add_keystr(info, "backlight type", "dcs");
  542. break;
  543. default:
  544. DSI_DEBUG("invalid panel backlight type:%d\n",
  545. panel->bl_config.type);
  546. break;
  547. }
  548. if (panel->spr_info.enable)
  549. sde_kms_info_add_keystr(info, "spr_pack_type",
  550. msm_spr_pack_type_str[panel->spr_info.pack_type]);
  551. if (mode_info && mode_info->roi_caps.enabled) {
  552. sde_kms_info_add_keyint(info, "partial_update_num_roi",
  553. mode_info->roi_caps.num_roi);
  554. sde_kms_info_add_keyint(info, "partial_update_xstart",
  555. mode_info->roi_caps.align.xstart_pix_align);
  556. sde_kms_info_add_keyint(info, "partial_update_walign",
  557. mode_info->roi_caps.align.width_pix_align);
  558. sde_kms_info_add_keyint(info, "partial_update_wmin",
  559. mode_info->roi_caps.align.min_width);
  560. sde_kms_info_add_keyint(info, "partial_update_ystart",
  561. mode_info->roi_caps.align.ystart_pix_align);
  562. sde_kms_info_add_keyint(info, "partial_update_halign",
  563. mode_info->roi_caps.align.height_pix_align);
  564. sde_kms_info_add_keyint(info, "partial_update_hmin",
  565. mode_info->roi_caps.align.min_height);
  566. sde_kms_info_add_keyint(info, "partial_update_roimerge",
  567. mode_info->roi_caps.merge_rois);
  568. }
  569. fmt = dsi_display->config.common_config.dst_format;
  570. bpp = dsi_ctrl_pixel_format_to_bpp(fmt);
  571. sde_kms_info_add_keyint(info, "bit_depth", bpp);
  572. end:
  573. return 0;
  574. }
  575. enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
  576. bool force,
  577. void *display)
  578. {
  579. enum drm_connector_status status = connector_status_unknown;
  580. struct msm_display_info info;
  581. int rc;
  582. if (!conn || !display)
  583. return status;
  584. /* get display dsi_info */
  585. memset(&info, 0x0, sizeof(info));
  586. rc = dsi_display_get_info(conn, &info, display);
  587. if (rc) {
  588. DSI_ERR("failed to get display info, rc=%d\n", rc);
  589. return connector_status_disconnected;
  590. }
  591. if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
  592. status = (info.is_connected ? connector_status_connected :
  593. connector_status_disconnected);
  594. else
  595. status = connector_status_connected;
  596. conn->display_info.width_mm = info.width_mm;
  597. conn->display_info.height_mm = info.height_mm;
  598. return status;
  599. }
  600. void dsi_connector_put_modes(struct drm_connector *connector,
  601. void *display)
  602. {
  603. struct drm_display_mode *drm_mode;
  604. struct dsi_display_mode dsi_mode;
  605. struct dsi_display *dsi_display;
  606. if (!connector || !display)
  607. return;
  608. list_for_each_entry(drm_mode, &connector->modes, head) {
  609. convert_to_dsi_mode(drm_mode, &dsi_mode);
  610. dsi_display_put_mode(display, &dsi_mode);
  611. }
  612. /* free the display structure modes also */
  613. dsi_display = display;
  614. kfree(dsi_display->modes);
  615. dsi_display->modes = NULL;
  616. }
  617. static int dsi_drm_update_edid_name(struct edid *edid, const char *name)
  618. {
  619. u8 *dtd = (u8 *)&edid->detailed_timings[3];
  620. u8 standard_header[] = {0x00, 0x00, 0x00, 0xFE, 0x00};
  621. u32 dtd_size = 18;
  622. u32 header_size = sizeof(standard_header);
  623. if (!name)
  624. return -EINVAL;
  625. /* Fill standard header */
  626. memcpy(dtd, standard_header, header_size);
  627. dtd_size -= header_size;
  628. dtd_size = min_t(u32, dtd_size, strlen(name));
  629. memcpy(dtd + header_size, name, dtd_size);
  630. return 0;
  631. }
  632. static void dsi_drm_update_dtd(struct edid *edid,
  633. struct dsi_display_mode *modes, u32 modes_count)
  634. {
  635. u32 i;
  636. u32 count = min_t(u32, modes_count, 3);
  637. for (i = 0; i < count; i++) {
  638. struct detailed_timing *dtd = &edid->detailed_timings[i];
  639. struct dsi_display_mode *mode = &modes[i];
  640. struct dsi_mode_info *timing = &mode->timing;
  641. struct detailed_pixel_timing *pd = &dtd->data.pixel_data;
  642. u32 h_blank = timing->h_front_porch + timing->h_sync_width +
  643. timing->h_back_porch;
  644. u32 v_blank = timing->v_front_porch + timing->v_sync_width +
  645. timing->v_back_porch;
  646. u32 h_img = 0, v_img = 0;
  647. dtd->pixel_clock = mode->pixel_clk_khz / 10;
  648. pd->hactive_lo = timing->h_active & 0xFF;
  649. pd->hblank_lo = h_blank & 0xFF;
  650. pd->hactive_hblank_hi = ((h_blank >> 8) & 0xF) |
  651. ((timing->h_active >> 8) & 0xF) << 4;
  652. pd->vactive_lo = timing->v_active & 0xFF;
  653. pd->vblank_lo = v_blank & 0xFF;
  654. pd->vactive_vblank_hi = ((v_blank >> 8) & 0xF) |
  655. ((timing->v_active >> 8) & 0xF) << 4;
  656. pd->hsync_offset_lo = timing->h_front_porch & 0xFF;
  657. pd->hsync_pulse_width_lo = timing->h_sync_width & 0xFF;
  658. pd->vsync_offset_pulse_width_lo =
  659. ((timing->v_front_porch & 0xF) << 4) |
  660. (timing->v_sync_width & 0xF);
  661. pd->hsync_vsync_offset_pulse_width_hi =
  662. (((timing->h_front_porch >> 8) & 0x3) << 6) |
  663. (((timing->h_sync_width >> 8) & 0x3) << 4) |
  664. (((timing->v_front_porch >> 4) & 0x3) << 2) |
  665. (((timing->v_sync_width >> 4) & 0x3) << 0);
  666. pd->width_mm_lo = h_img & 0xFF;
  667. pd->height_mm_lo = v_img & 0xFF;
  668. pd->width_height_mm_hi = (((h_img >> 8) & 0xF) << 4) |
  669. ((v_img >> 8) & 0xF);
  670. pd->hborder = 0;
  671. pd->vborder = 0;
  672. pd->misc = 0;
  673. }
  674. }
  675. static void dsi_drm_update_checksum(struct edid *edid)
  676. {
  677. u8 *data = (u8 *)edid;
  678. u32 i, sum = 0;
  679. for (i = 0; i < EDID_LENGTH - 1; i++)
  680. sum += data[i];
  681. edid->checksum = 0x100 - (sum & 0xFF);
  682. }
  683. int dsi_connector_get_modes(struct drm_connector *connector, void *data,
  684. const struct msm_resource_caps_info *avail_res)
  685. {
  686. int rc, i;
  687. u32 count = 0, edid_size;
  688. struct dsi_display_mode *modes = NULL;
  689. struct drm_display_mode drm_mode;
  690. struct dsi_display *display = data;
  691. struct edid edid;
  692. u8 width_mm = connector->display_info.width_mm;
  693. u8 height_mm = connector->display_info.height_mm;
  694. const u8 edid_buf[EDID_LENGTH] = {
  695. 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x44, 0x6D,
  696. 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1B, 0x10, 0x01, 0x03,
  697. 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47,
  698. 0x98, 0x27, 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  699. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  700. 0x01, 0x01, 0x01, 0x01,
  701. };
  702. edid_size = min_t(u32, sizeof(edid), EDID_LENGTH);
  703. memcpy(&edid, edid_buf, edid_size);
  704. rc = dsi_display_get_mode_count(display, &count);
  705. if (rc) {
  706. DSI_ERR("failed to get num of modes, rc=%d\n", rc);
  707. goto end;
  708. }
  709. rc = dsi_display_get_modes(display, &modes);
  710. if (rc) {
  711. DSI_ERR("failed to get modes, rc=%d\n", rc);
  712. count = 0;
  713. goto end;
  714. }
  715. for (i = 0; i < count; i++) {
  716. struct drm_display_mode *m;
  717. memset(&drm_mode, 0x0, sizeof(drm_mode));
  718. dsi_convert_to_drm_mode(&modes[i], &drm_mode);
  719. m = drm_mode_duplicate(connector->dev, &drm_mode);
  720. if (!m) {
  721. DSI_ERR("failed to add mode %ux%u\n",
  722. drm_mode.hdisplay,
  723. drm_mode.vdisplay);
  724. count = -ENOMEM;
  725. goto end;
  726. }
  727. m->width_mm = connector->display_info.width_mm;
  728. m->height_mm = connector->display_info.height_mm;
  729. /* set the first mode in list as preferred */
  730. if (i == 0)
  731. m->type |= DRM_MODE_TYPE_PREFERRED;
  732. drm_mode_probed_add(connector, m);
  733. }
  734. rc = dsi_drm_update_edid_name(&edid, display->panel->name);
  735. if (rc) {
  736. count = 0;
  737. goto end;
  738. }
  739. edid.width_cm = (connector->display_info.width_mm) / 10;
  740. edid.height_cm = (connector->display_info.height_mm) / 10;
  741. dsi_drm_update_dtd(&edid, modes, count);
  742. dsi_drm_update_checksum(&edid);
  743. rc = drm_connector_update_edid_property(connector, &edid);
  744. if (rc)
  745. count = 0;
  746. /*
  747. * DRM EDID structure maintains panel physical dimensions in
  748. * centimeters, we will be losing the precision anything below cm.
  749. * Changing DRM framework will effect other clients at this
  750. * moment, overriding the values back to millimeter.
  751. */
  752. connector->display_info.width_mm = width_mm;
  753. connector->display_info.height_mm = height_mm;
  754. end:
  755. DSI_DEBUG("MODE COUNT =%d\n\n", count);
  756. return count;
  757. }
  758. enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
  759. struct drm_display_mode *mode,
  760. void *display, const struct msm_resource_caps_info *avail_res)
  761. {
  762. struct dsi_display_mode dsi_mode;
  763. int rc;
  764. if (!connector || !mode) {
  765. DSI_ERR("Invalid params\n");
  766. return MODE_ERROR;
  767. }
  768. convert_to_dsi_mode(mode, &dsi_mode);
  769. rc = dsi_display_validate_mode(display, &dsi_mode,
  770. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  771. if (rc) {
  772. DSI_ERR("mode not supported, rc=%d\n", rc);
  773. return MODE_BAD;
  774. }
  775. return MODE_OK;
  776. }
  777. int dsi_conn_pre_kickoff(struct drm_connector *connector,
  778. void *display,
  779. struct msm_display_kickoff_params *params)
  780. {
  781. if (!connector || !display || !params) {
  782. DSI_ERR("Invalid params\n");
  783. return -EINVAL;
  784. }
  785. return dsi_display_pre_kickoff(connector, display, params);
  786. }
  787. int dsi_conn_prepare_commit(void *display,
  788. struct msm_display_conn_params *params)
  789. {
  790. if (!display || !params) {
  791. pr_err("Invalid params\n");
  792. return -EINVAL;
  793. }
  794. return dsi_display_pre_commit(display, params);
  795. }
  796. void dsi_conn_enable_event(struct drm_connector *connector,
  797. uint32_t event_idx, bool enable, void *display)
  798. {
  799. struct dsi_event_cb_info event_info;
  800. memset(&event_info, 0, sizeof(event_info));
  801. event_info.event_cb = sde_connector_trigger_event;
  802. event_info.event_usr_ptr = connector;
  803. dsi_display_enable_event(connector, display,
  804. event_idx, &event_info, enable);
  805. }
  806. int dsi_conn_post_kickoff(struct drm_connector *connector,
  807. struct msm_display_conn_params *params)
  808. {
  809. struct drm_encoder *encoder;
  810. struct dsi_bridge *c_bridge;
  811. struct dsi_display_mode adj_mode;
  812. struct dsi_display *display;
  813. struct dsi_display_ctrl *m_ctrl, *ctrl;
  814. int i, rc = 0;
  815. bool enable;
  816. if (!connector || !connector->state) {
  817. DSI_ERR("invalid connector or connector state\n");
  818. return -EINVAL;
  819. }
  820. encoder = connector->state->best_encoder;
  821. if (!encoder) {
  822. DSI_DEBUG("best encoder is not available\n");
  823. return 0;
  824. }
  825. c_bridge = to_dsi_bridge(encoder->bridge);
  826. adj_mode = c_bridge->dsi_mode;
  827. display = c_bridge->display;
  828. if (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) {
  829. m_ctrl = &display->ctrl[display->clk_master_idx];
  830. rc = dsi_ctrl_timing_db_update(m_ctrl->ctrl, false);
  831. if (rc) {
  832. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  833. display->name, rc);
  834. return -EINVAL;
  835. }
  836. /* Update the rest of the controllers */
  837. display_for_each_ctrl(i, display) {
  838. ctrl = &display->ctrl[i];
  839. if (!ctrl->ctrl || (ctrl == m_ctrl))
  840. continue;
  841. rc = dsi_ctrl_timing_db_update(ctrl->ctrl, false);
  842. if (rc) {
  843. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  844. display->name, rc);
  845. return -EINVAL;
  846. }
  847. }
  848. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR;
  849. }
  850. /* ensure dynamic clk switch flag is reset */
  851. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK;
  852. if (params->qsync_update) {
  853. enable = (params->qsync_mode > 0) ? true : false;
  854. display_for_each_ctrl(i, display)
  855. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  856. }
  857. return 0;
  858. }
  859. struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
  860. struct drm_device *dev,
  861. struct drm_encoder *encoder)
  862. {
  863. int rc = 0;
  864. struct dsi_bridge *bridge;
  865. bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
  866. if (!bridge) {
  867. rc = -ENOMEM;
  868. goto error;
  869. }
  870. bridge->display = display;
  871. bridge->base.funcs = &dsi_bridge_ops;
  872. bridge->base.encoder = encoder;
  873. rc = drm_bridge_attach(encoder, &bridge->base, NULL);
  874. if (rc) {
  875. DSI_ERR("failed to attach bridge, rc=%d\n", rc);
  876. goto error_free_bridge;
  877. }
  878. encoder->bridge = &bridge->base;
  879. return bridge;
  880. error_free_bridge:
  881. kfree(bridge);
  882. error:
  883. return ERR_PTR(rc);
  884. }
  885. void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
  886. {
  887. if (bridge && bridge->base.encoder)
  888. bridge->base.encoder->bridge = NULL;
  889. kfree(bridge);
  890. }