qcs405.c 241 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/clk.h>
  5. #include <linux/delay.h>
  6. #include <linux/gpio.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/i2c.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <sound/core.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/info.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <dsp/q6afe-v2.h>
  25. #include <dsp/q6core.h>
  26. #include <dsp/msm_mdf.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include <asoc/msm-cdc-pinctrl.h>
  30. #include "codecs/wcd9335.h"
  31. #include "codecs/wsa881x.h"
  32. #include "codecs/csra66x0/csra66x0.h"
  33. #include <dt-bindings/sound/audio-codec-port-types.h>
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include "codecs/bolero/wsa-macro.h"
  36. #define DRV_NAME "qcs405-asoc-snd"
  37. #define __CHIPSET__ "QCS405 "
  38. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  39. #define DEV_NAME_STR_LEN 32
  40. #define SAMPLING_RATE_8KHZ 8000
  41. #define SAMPLING_RATE_11P025KHZ 11025
  42. #define SAMPLING_RATE_16KHZ 16000
  43. #define SAMPLING_RATE_22P05KHZ 22050
  44. #define SAMPLING_RATE_32KHZ 32000
  45. #define SAMPLING_RATE_44P1KHZ 44100
  46. #define SAMPLING_RATE_48KHZ 48000
  47. #define SAMPLING_RATE_88P2KHZ 88200
  48. #define SAMPLING_RATE_96KHZ 96000
  49. #define SAMPLING_RATE_176P4KHZ 176400
  50. #define SAMPLING_RATE_192KHZ 192000
  51. #define SAMPLING_RATE_352P8KHZ 352800
  52. #define SAMPLING_RATE_384KHZ 384000
  53. #define SPDIF_TX_CORE_CLK_163_P84_MHZ 163840000
  54. #define TLMM_EAST_SPARE 0x07BA0000
  55. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  56. #define WSA8810_NAME_1 "wsa881x.20170211"
  57. #define WSA8810_NAME_2 "wsa881x.20170212"
  58. #define WCN_CDC_SLIM_RX_CH_MAX 2
  59. #define WCN_CDC_SLIM_TX_CH_MAX 4
  60. #define TDM_CHANNEL_MAX 8
  61. #define BT_SLIM_TX SLIM_TX_9
  62. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  63. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  64. enum {
  65. SLIM_RX_0 = 0,
  66. SLIM_RX_1,
  67. SLIM_RX_2,
  68. SLIM_RX_3,
  69. SLIM_RX_4,
  70. SLIM_RX_5,
  71. SLIM_RX_6,
  72. SLIM_RX_7,
  73. SLIM_RX_MAX,
  74. };
  75. enum {
  76. SLIM_TX_0 = 0,
  77. SLIM_TX_1,
  78. SLIM_TX_2,
  79. SLIM_TX_3,
  80. SLIM_TX_4,
  81. SLIM_TX_5,
  82. SLIM_TX_6,
  83. SLIM_TX_7,
  84. SLIM_TX_8,
  85. SLIM_TX_9,
  86. SLIM_TX_MAX,
  87. };
  88. enum {
  89. PRIM_MI2S = 0,
  90. SEC_MI2S,
  91. TERT_MI2S,
  92. QUAT_MI2S,
  93. QUIN_MI2S,
  94. SEN_MI2S,
  95. MI2S_MAX,
  96. };
  97. enum {
  98. PRIM_AUX_PCM = 0,
  99. SEC_AUX_PCM,
  100. TERT_AUX_PCM,
  101. QUAT_AUX_PCM,
  102. QUIN_AUX_PCM,
  103. SEN_AUX_PCM,
  104. AUX_PCM_MAX,
  105. };
  106. enum {
  107. WSA_CDC_DMA_RX_0 = 0,
  108. WSA_CDC_DMA_RX_1,
  109. CDC_DMA_RX_MAX,
  110. };
  111. enum {
  112. WSA_CDC_DMA_TX_0 = 0,
  113. WSA_CDC_DMA_TX_1,
  114. WSA_CDC_DMA_TX_2,
  115. VA_CDC_DMA_TX_0,
  116. VA_CDC_DMA_TX_1,
  117. CDC_DMA_TX_MAX,
  118. };
  119. enum {
  120. PRIM_SPDIF_RX = 0,
  121. SEC_SPDIF_RX,
  122. SPDIF_RX_MAX,
  123. };
  124. enum {
  125. PRIM_SPDIF_TX = 0,
  126. SEC_SPDIF_TX,
  127. SPDIF_TX_MAX,
  128. };
  129. struct mi2s_conf {
  130. struct mutex lock;
  131. u32 ref_cnt;
  132. u32 msm_is_mi2s_master;
  133. };
  134. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  135. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  136. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  137. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  138. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  139. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT,
  140. Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT
  141. };
  142. struct dev_config {
  143. u32 sample_rate;
  144. u32 bit_format;
  145. u32 channels;
  146. };
  147. struct msm_wsa881x_dev_info {
  148. struct device_node *of_node;
  149. u32 index;
  150. };
  151. struct msm_csra66x0_dev_info {
  152. struct device_node *of_node;
  153. u32 index;
  154. };
  155. struct msm_asoc_mach_data {
  156. struct snd_info_entry *codec_root;
  157. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  158. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  159. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  160. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  161. struct device_node *lineout_booster_gpio_p; /* used by pinctrl API */
  162. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  163. int dmic_01_gpio_cnt;
  164. int dmic_23_gpio_cnt;
  165. int dmic_45_gpio_cnt;
  166. int dmic_67_gpio_cnt;
  167. struct regulator *tdm_micb_supply;
  168. u32 tdm_micb_voltage;
  169. u32 tdm_micb_current;
  170. bool codec_is_csra;
  171. };
  172. struct msm_asoc_wcd93xx_codec {
  173. void* (*get_afe_config_fn)(struct snd_soc_component *component,
  174. enum afe_config_type config_type);
  175. };
  176. static const char *const pin_states[] = {"sleep", "i2s-active",
  177. "tdm-active"};
  178. enum {
  179. TDM_0 = 0,
  180. TDM_1,
  181. TDM_2,
  182. TDM_3,
  183. TDM_4,
  184. TDM_5,
  185. TDM_6,
  186. TDM_7,
  187. TDM_PORT_MAX,
  188. };
  189. enum {
  190. TDM_PRI = 0,
  191. TDM_SEC,
  192. TDM_TERT,
  193. TDM_QUAT,
  194. TDM_QUIN,
  195. TDM_INTERFACE_MAX,
  196. };
  197. struct tdm_port {
  198. u32 mode;
  199. u32 channel;
  200. };
  201. /* TDM default config */
  202. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  203. { /* PRI TDM */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  212. },
  213. { /* SEC TDM */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  222. },
  223. { /* TERT TDM */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  232. },
  233. { /* QUAT TDM */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  242. },
  243. { /* QUIN TDM */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  252. }
  253. };
  254. /* TDM default config */
  255. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  256. { /* PRI TDM */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  265. },
  266. { /* SEC TDM */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  275. },
  276. { /* TERT TDM */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  285. },
  286. { /* QUAT TDM */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  295. },
  296. { /* QUIN TDM */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  305. }
  306. };
  307. /* Default configuration of slimbus channels */
  308. static struct dev_config slim_rx_cfg[] = {
  309. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. };
  318. static struct dev_config slim_tx_cfg[] = {
  319. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  327. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  328. [SLIM_TX_9] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  329. };
  330. /* Default configuration of Codec DMA Interface Tx */
  331. static struct dev_config cdc_dma_rx_cfg[] = {
  332. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  334. };
  335. /* Default configuration of Codec DMA Interface Rx */
  336. static struct dev_config cdc_dma_tx_cfg[] = {
  337. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  339. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  340. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  341. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  342. };
  343. static struct dev_config usb_rx_cfg = {
  344. .sample_rate = SAMPLING_RATE_48KHZ,
  345. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  346. .channels = 2,
  347. };
  348. static struct dev_config usb_tx_cfg = {
  349. .sample_rate = SAMPLING_RATE_48KHZ,
  350. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  351. .channels = 1,
  352. };
  353. static struct dev_config proxy_rx_cfg = {
  354. .sample_rate = SAMPLING_RATE_48KHZ,
  355. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  356. .channels = 2,
  357. };
  358. /* Default configuration of MI2S channels */
  359. static struct dev_config mi2s_rx_cfg[] = {
  360. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  361. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  362. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  363. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  364. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  365. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  366. };
  367. /* Default configuration of SPDIF channels */
  368. static struct dev_config spdif_rx_cfg[] = {
  369. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  371. };
  372. static struct dev_config spdif_tx_cfg[] = {
  373. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  374. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  375. };
  376. static struct dev_config mi2s_tx_cfg[] = {
  377. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  379. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  380. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  381. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  382. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  383. };
  384. static struct dev_config aux_pcm_rx_cfg[] = {
  385. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  389. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  390. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  391. };
  392. static struct dev_config aux_pcm_tx_cfg[] = {
  393. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  399. };
  400. static int msm_vi_feed_tx_ch = 2;
  401. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  402. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  403. "Five", "Six", "Seven",
  404. "Eight"};
  405. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  406. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  407. "S32_LE"};
  408. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  409. "KHZ_32", "KHZ_44P1", "KHZ_48",
  410. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  411. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  412. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  413. "KHZ_44P1", "KHZ_48",
  414. "KHZ_88P2", "KHZ_96"};
  415. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  416. "Five", "Six", "Seven",
  417. "Eight"};
  418. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  419. "Six", "Seven", "Eight"};
  420. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  421. "KHZ_16", "KHZ_22P05",
  422. "KHZ_32", "KHZ_44P1", "KHZ_48",
  423. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  424. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  425. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  426. "Five", "Six", "Seven", "Eight"};
  427. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  428. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  429. "KHZ_48", "KHZ_176P4",
  430. "KHZ_352P8"};
  431. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  432. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  433. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  434. "KHZ_48", "KHZ_96", "KHZ_192", "KHZ_384"};
  435. static const char *const mi2s_ch_text[] = {
  436. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  437. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  438. "Fourteen", "Fifteen", "Sixteen"
  439. };
  440. static const char *const qos_text[] = {"Disable", "Enable"};
  441. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  442. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  443. "Five", "Six", "Seven",
  444. "Eight"};
  445. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  446. "KHZ_16", "KHZ_22P05",
  447. "KHZ_32", "KHZ_44P1", "KHZ_48",
  448. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  449. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  450. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  451. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  452. "KHZ_192"};
  453. static const char *spdif_ch_text[] = {"One", "Two"};
  454. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  455. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_sink, bt_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  540. cdc_dma_sample_rate_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  542. cdc_dma_sample_rate_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  544. cdc_dma_sample_rate_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  546. cdc_dma_sample_rate_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  548. cdc_dma_sample_rate_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  550. cdc_dma_sample_rate_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  552. cdc_dma_sample_rate_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  559. static struct platform_device *spdev;
  560. static bool is_initial_boot;
  561. static bool codec_reg_done;
  562. static struct snd_soc_aux_dev *msm_aux_dev;
  563. static struct snd_soc_codec_conf *msm_codec_conf;
  564. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  565. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  566. int enable, bool dapm);
  567. static int msm_wsa881x_init(struct snd_soc_component *component);
  568. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  569. struct snd_ctl_elem_value *ucontrol);
  570. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  571. {"MIC BIAS1", NULL, "MCLK TX"},
  572. {"MIC BIAS2", NULL, "MCLK TX"},
  573. {"MIC BIAS3", NULL, "MCLK TX"},
  574. {"MIC BIAS4", NULL, "MCLK TX"},
  575. };
  576. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  577. {
  578. AFE_API_VERSION_I2S_CONFIG,
  579. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  580. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  581. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  582. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  583. 0,
  584. },
  585. {
  586. AFE_API_VERSION_I2S_CONFIG,
  587. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  588. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  589. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  590. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  591. 0,
  592. },
  593. {
  594. AFE_API_VERSION_I2S_CONFIG,
  595. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  596. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  597. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  598. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  599. 0,
  600. },
  601. {
  602. AFE_API_VERSION_I2S_CONFIG,
  603. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  604. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  605. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  606. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  607. 0,
  608. },
  609. {
  610. AFE_API_VERSION_I2S_CONFIG,
  611. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  612. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  613. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  614. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  615. 0,
  616. },
  617. {
  618. AFE_API_VERSION_I2S_CONFIG,
  619. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  620. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  621. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  622. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  623. 0,
  624. }
  625. };
  626. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  627. static int slim_get_sample_rate_val(int sample_rate)
  628. {
  629. int sample_rate_val = 0;
  630. switch (sample_rate) {
  631. case SAMPLING_RATE_8KHZ:
  632. sample_rate_val = 0;
  633. break;
  634. case SAMPLING_RATE_16KHZ:
  635. sample_rate_val = 1;
  636. break;
  637. case SAMPLING_RATE_32KHZ:
  638. sample_rate_val = 2;
  639. break;
  640. case SAMPLING_RATE_44P1KHZ:
  641. sample_rate_val = 3;
  642. break;
  643. case SAMPLING_RATE_48KHZ:
  644. sample_rate_val = 4;
  645. break;
  646. case SAMPLING_RATE_88P2KHZ:
  647. sample_rate_val = 5;
  648. break;
  649. case SAMPLING_RATE_96KHZ:
  650. sample_rate_val = 6;
  651. break;
  652. case SAMPLING_RATE_176P4KHZ:
  653. sample_rate_val = 7;
  654. break;
  655. case SAMPLING_RATE_192KHZ:
  656. sample_rate_val = 8;
  657. break;
  658. case SAMPLING_RATE_352P8KHZ:
  659. sample_rate_val = 9;
  660. break;
  661. case SAMPLING_RATE_384KHZ:
  662. sample_rate_val = 10;
  663. break;
  664. default:
  665. sample_rate_val = 4;
  666. break;
  667. }
  668. return sample_rate_val;
  669. }
  670. static int slim_get_sample_rate(int value)
  671. {
  672. int sample_rate = 0;
  673. switch (value) {
  674. case 0:
  675. sample_rate = SAMPLING_RATE_8KHZ;
  676. break;
  677. case 1:
  678. sample_rate = SAMPLING_RATE_16KHZ;
  679. break;
  680. case 2:
  681. sample_rate = SAMPLING_RATE_32KHZ;
  682. break;
  683. case 3:
  684. sample_rate = SAMPLING_RATE_44P1KHZ;
  685. break;
  686. case 4:
  687. sample_rate = SAMPLING_RATE_48KHZ;
  688. break;
  689. case 5:
  690. sample_rate = SAMPLING_RATE_88P2KHZ;
  691. break;
  692. case 6:
  693. sample_rate = SAMPLING_RATE_96KHZ;
  694. break;
  695. case 7:
  696. sample_rate = SAMPLING_RATE_176P4KHZ;
  697. break;
  698. case 8:
  699. sample_rate = SAMPLING_RATE_192KHZ;
  700. break;
  701. case 9:
  702. sample_rate = SAMPLING_RATE_352P8KHZ;
  703. break;
  704. case 10:
  705. sample_rate = SAMPLING_RATE_384KHZ;
  706. break;
  707. default:
  708. sample_rate = SAMPLING_RATE_48KHZ;
  709. break;
  710. }
  711. return sample_rate;
  712. }
  713. static int slim_get_bit_format_val(int bit_format)
  714. {
  715. int val = 0;
  716. switch (bit_format) {
  717. case SNDRV_PCM_FORMAT_S32_LE:
  718. val = 3;
  719. break;
  720. case SNDRV_PCM_FORMAT_S24_3LE:
  721. val = 2;
  722. break;
  723. case SNDRV_PCM_FORMAT_S24_LE:
  724. val = 1;
  725. break;
  726. case SNDRV_PCM_FORMAT_S16_LE:
  727. default:
  728. val = 0;
  729. break;
  730. }
  731. return val;
  732. }
  733. static int slim_get_bit_format(int val)
  734. {
  735. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  736. switch (val) {
  737. case 0:
  738. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  739. break;
  740. case 1:
  741. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  742. break;
  743. case 2:
  744. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  745. break;
  746. case 3:
  747. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  748. break;
  749. default:
  750. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  751. break;
  752. }
  753. return bit_fmt;
  754. }
  755. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  756. {
  757. int port_id = 0;
  758. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  759. port_id = SLIM_RX_0;
  760. } else if (strnstr(kcontrol->id.name,
  761. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  762. port_id = SLIM_RX_2;
  763. } else if (strnstr(kcontrol->id.name,
  764. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  765. port_id = SLIM_RX_5;
  766. } else if (strnstr(kcontrol->id.name,
  767. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  768. port_id = SLIM_RX_6;
  769. } else if (strnstr(kcontrol->id.name,
  770. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  771. port_id = SLIM_TX_0;
  772. } else if (strnstr(kcontrol->id.name,
  773. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  774. port_id = SLIM_TX_1;
  775. } else {
  776. pr_err("%s: unsupported channel: %s",
  777. __func__, kcontrol->id.name);
  778. return -EINVAL;
  779. }
  780. return port_id;
  781. }
  782. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  783. struct snd_ctl_elem_value *ucontrol)
  784. {
  785. int ch_num = slim_get_port_idx(kcontrol);
  786. if (ch_num < 0)
  787. return ch_num;
  788. ucontrol->value.enumerated.item[0] =
  789. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  790. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  791. ch_num, slim_rx_cfg[ch_num].sample_rate,
  792. ucontrol->value.enumerated.item[0]);
  793. return 0;
  794. }
  795. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  796. struct snd_ctl_elem_value *ucontrol)
  797. {
  798. int ch_num = slim_get_port_idx(kcontrol);
  799. if (ch_num < 0)
  800. return ch_num;
  801. slim_rx_cfg[ch_num].sample_rate =
  802. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  803. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  804. ch_num, slim_rx_cfg[ch_num].sample_rate,
  805. ucontrol->value.enumerated.item[0]);
  806. return 0;
  807. }
  808. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  809. struct snd_ctl_elem_value *ucontrol)
  810. {
  811. int ch_num = slim_get_port_idx(kcontrol);
  812. if (ch_num < 0)
  813. return ch_num;
  814. ucontrol->value.enumerated.item[0] =
  815. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  816. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  817. ch_num, slim_tx_cfg[ch_num].sample_rate,
  818. ucontrol->value.enumerated.item[0]);
  819. return 0;
  820. }
  821. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  822. struct snd_ctl_elem_value *ucontrol)
  823. {
  824. int sample_rate = 0;
  825. int ch_num = slim_get_port_idx(kcontrol);
  826. if (ch_num < 0)
  827. return ch_num;
  828. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  829. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  830. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  831. __func__, sample_rate);
  832. return -EINVAL;
  833. }
  834. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  835. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  836. ch_num, slim_tx_cfg[ch_num].sample_rate,
  837. ucontrol->value.enumerated.item[0]);
  838. return 0;
  839. }
  840. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  841. struct snd_ctl_elem_value *ucontrol)
  842. {
  843. int ch_num = slim_get_port_idx(kcontrol);
  844. if (ch_num < 0)
  845. return ch_num;
  846. ucontrol->value.enumerated.item[0] =
  847. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  848. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  849. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  850. ucontrol->value.enumerated.item[0]);
  851. return 0;
  852. }
  853. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  854. struct snd_ctl_elem_value *ucontrol)
  855. {
  856. int ch_num = slim_get_port_idx(kcontrol);
  857. if (ch_num < 0)
  858. return ch_num;
  859. slim_rx_cfg[ch_num].bit_format =
  860. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  861. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  862. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  863. ucontrol->value.enumerated.item[0]);
  864. return 0;
  865. }
  866. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  867. struct snd_ctl_elem_value *ucontrol)
  868. {
  869. int ch_num = slim_get_port_idx(kcontrol);
  870. if (ch_num < 0)
  871. return ch_num;
  872. ucontrol->value.enumerated.item[0] =
  873. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  874. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  875. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  876. ucontrol->value.enumerated.item[0]);
  877. return 0;
  878. }
  879. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  880. struct snd_ctl_elem_value *ucontrol)
  881. {
  882. int ch_num = slim_get_port_idx(kcontrol);
  883. if (ch_num < 0)
  884. return ch_num;
  885. slim_tx_cfg[ch_num].bit_format =
  886. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  887. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  888. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  889. ucontrol->value.enumerated.item[0]);
  890. return 0;
  891. }
  892. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  893. struct snd_ctl_elem_value *ucontrol)
  894. {
  895. int ch_num = slim_get_port_idx(kcontrol);
  896. if (ch_num < 0)
  897. return ch_num;
  898. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  899. ch_num, slim_rx_cfg[ch_num].channels);
  900. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  901. return 0;
  902. }
  903. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  904. struct snd_ctl_elem_value *ucontrol)
  905. {
  906. int ch_num = slim_get_port_idx(kcontrol);
  907. if (ch_num < 0)
  908. return ch_num;
  909. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  910. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  911. ch_num, slim_rx_cfg[ch_num].channels);
  912. return 1;
  913. }
  914. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  915. struct snd_ctl_elem_value *ucontrol)
  916. {
  917. int ch_num = slim_get_port_idx(kcontrol);
  918. if (ch_num < 0)
  919. return ch_num;
  920. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  921. ch_num, slim_tx_cfg[ch_num].channels);
  922. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  923. return 0;
  924. }
  925. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  926. struct snd_ctl_elem_value *ucontrol)
  927. {
  928. int ch_num = slim_get_port_idx(kcontrol);
  929. if (ch_num < 0)
  930. return ch_num;
  931. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  932. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  933. ch_num, slim_tx_cfg[ch_num].channels);
  934. return 1;
  935. }
  936. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  937. struct snd_ctl_elem_value *ucontrol)
  938. {
  939. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  940. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  941. ucontrol->value.integer.value[0]);
  942. return 0;
  943. }
  944. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  945. struct snd_ctl_elem_value *ucontrol)
  946. {
  947. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  948. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  949. return 1;
  950. }
  951. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  952. struct snd_ctl_elem_value *ucontrol)
  953. {
  954. /*
  955. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  956. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  957. * value.
  958. */
  959. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  960. case SAMPLING_RATE_96KHZ:
  961. ucontrol->value.integer.value[0] = 5;
  962. break;
  963. case SAMPLING_RATE_88P2KHZ:
  964. ucontrol->value.integer.value[0] = 4;
  965. break;
  966. case SAMPLING_RATE_48KHZ:
  967. ucontrol->value.integer.value[0] = 3;
  968. break;
  969. case SAMPLING_RATE_44P1KHZ:
  970. ucontrol->value.integer.value[0] = 2;
  971. break;
  972. case SAMPLING_RATE_16KHZ:
  973. ucontrol->value.integer.value[0] = 1;
  974. break;
  975. case SAMPLING_RATE_8KHZ:
  976. default:
  977. ucontrol->value.integer.value[0] = 0;
  978. break;
  979. }
  980. pr_debug("%s: sample rate = %d", __func__,
  981. slim_rx_cfg[SLIM_RX_7].sample_rate);
  982. return 0;
  983. }
  984. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  985. struct snd_ctl_elem_value *ucontrol)
  986. {
  987. switch (ucontrol->value.integer.value[0]) {
  988. case 1:
  989. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  990. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  991. break;
  992. case 2:
  993. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  994. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  995. break;
  996. case 3:
  997. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  998. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  999. break;
  1000. case 4:
  1001. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1002. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1003. break;
  1004. case 5:
  1005. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1006. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1007. break;
  1008. case 0:
  1009. default:
  1010. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1011. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1012. break;
  1013. }
  1014. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1015. __func__,
  1016. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1017. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1018. ucontrol->value.enumerated.item[0]);
  1019. return 0;
  1020. }
  1021. static int msm_bt_sample_rate_sink_get(struct snd_kcontrol *kcontrol,
  1022. struct snd_ctl_elem_value *ucontrol)
  1023. {
  1024. switch (slim_tx_cfg[BT_SLIM_TX].sample_rate) {
  1025. case SAMPLING_RATE_96KHZ:
  1026. ucontrol->value.integer.value[0] = 5;
  1027. break;
  1028. case SAMPLING_RATE_88P2KHZ:
  1029. ucontrol->value.integer.value[0] = 4;
  1030. break;
  1031. case SAMPLING_RATE_48KHZ:
  1032. ucontrol->value.integer.value[0] = 3;
  1033. break;
  1034. case SAMPLING_RATE_44P1KHZ:
  1035. ucontrol->value.integer.value[0] = 2;
  1036. break;
  1037. case SAMPLING_RATE_16KHZ:
  1038. ucontrol->value.integer.value[0] = 1;
  1039. break;
  1040. case SAMPLING_RATE_8KHZ:
  1041. default:
  1042. ucontrol->value.integer.value[0] = 0;
  1043. break;
  1044. }
  1045. pr_debug("%s: sample rate = %d", __func__,
  1046. slim_tx_cfg[BT_SLIM_TX].sample_rate);
  1047. return 0;
  1048. }
  1049. static int msm_bt_sample_rate_sink_put(struct snd_kcontrol *kcontrol,
  1050. struct snd_ctl_elem_value *ucontrol)
  1051. {
  1052. switch (ucontrol->value.integer.value[0]) {
  1053. case 1:
  1054. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_16KHZ;
  1055. break;
  1056. case 2:
  1057. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_44P1KHZ;
  1058. break;
  1059. case 3:
  1060. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_48KHZ;
  1061. break;
  1062. case 4:
  1063. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_88P2KHZ;
  1064. break;
  1065. case 5:
  1066. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_96KHZ;
  1067. break;
  1068. case 0:
  1069. default:
  1070. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_8KHZ;
  1071. break;
  1072. }
  1073. pr_debug("%s: sample rate = %d, value = %d\n",
  1074. __func__,
  1075. slim_tx_cfg[BT_SLIM_TX].sample_rate,
  1076. ucontrol->value.enumerated.item[0]);
  1077. return 0;
  1078. }
  1079. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1080. {
  1081. int idx = 0;
  1082. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1083. sizeof("WSA_CDC_DMA_RX_0")))
  1084. idx = WSA_CDC_DMA_RX_0;
  1085. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1086. sizeof("WSA_CDC_DMA_RX_0")))
  1087. idx = WSA_CDC_DMA_RX_1;
  1088. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1089. sizeof("WSA_CDC_DMA_TX_0")))
  1090. idx = WSA_CDC_DMA_TX_0;
  1091. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1092. sizeof("WSA_CDC_DMA_TX_1")))
  1093. idx = WSA_CDC_DMA_TX_1;
  1094. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1095. sizeof("WSA_CDC_DMA_TX_2")))
  1096. idx = WSA_CDC_DMA_TX_2;
  1097. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1098. sizeof("VA_CDC_DMA_TX_0")))
  1099. idx = VA_CDC_DMA_TX_0;
  1100. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1101. sizeof("VA_CDC_DMA_TX_1")))
  1102. idx = VA_CDC_DMA_TX_1;
  1103. else {
  1104. pr_err("%s: unsupported port: %s\n",
  1105. __func__, kcontrol->id.name);
  1106. return -EINVAL;
  1107. }
  1108. return idx;
  1109. }
  1110. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1111. struct snd_ctl_elem_value *ucontrol)
  1112. {
  1113. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1114. if (ch_num < 0)
  1115. return ch_num;
  1116. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1117. cdc_dma_rx_cfg[ch_num].channels - 1);
  1118. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1119. return 0;
  1120. }
  1121. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1122. struct snd_ctl_elem_value *ucontrol)
  1123. {
  1124. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1125. if (ch_num < 0)
  1126. return ch_num;
  1127. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1128. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1129. cdc_dma_rx_cfg[ch_num].channels);
  1130. return 1;
  1131. }
  1132. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1133. struct snd_ctl_elem_value *ucontrol)
  1134. {
  1135. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1136. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1137. case SNDRV_PCM_FORMAT_S32_LE:
  1138. ucontrol->value.integer.value[0] = 3;
  1139. break;
  1140. case SNDRV_PCM_FORMAT_S24_3LE:
  1141. ucontrol->value.integer.value[0] = 2;
  1142. break;
  1143. case SNDRV_PCM_FORMAT_S24_LE:
  1144. ucontrol->value.integer.value[0] = 1;
  1145. break;
  1146. case SNDRV_PCM_FORMAT_S16_LE:
  1147. default:
  1148. ucontrol->value.integer.value[0] = 0;
  1149. break;
  1150. }
  1151. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1152. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1153. ucontrol->value.integer.value[0]);
  1154. return 0;
  1155. }
  1156. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1157. struct snd_ctl_elem_value *ucontrol)
  1158. {
  1159. int rc = 0;
  1160. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1161. switch (ucontrol->value.integer.value[0]) {
  1162. case 3:
  1163. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1164. break;
  1165. case 2:
  1166. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1167. break;
  1168. case 1:
  1169. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1170. break;
  1171. case 0:
  1172. default:
  1173. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1174. break;
  1175. }
  1176. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1177. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1178. ucontrol->value.integer.value[0]);
  1179. return rc;
  1180. }
  1181. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1182. {
  1183. int sample_rate_val = 0;
  1184. switch (sample_rate) {
  1185. case SAMPLING_RATE_8KHZ:
  1186. sample_rate_val = 0;
  1187. break;
  1188. case SAMPLING_RATE_11P025KHZ:
  1189. sample_rate_val = 1;
  1190. break;
  1191. case SAMPLING_RATE_16KHZ:
  1192. sample_rate_val = 2;
  1193. break;
  1194. case SAMPLING_RATE_22P05KHZ:
  1195. sample_rate_val = 3;
  1196. break;
  1197. case SAMPLING_RATE_32KHZ:
  1198. sample_rate_val = 4;
  1199. break;
  1200. case SAMPLING_RATE_44P1KHZ:
  1201. sample_rate_val = 5;
  1202. break;
  1203. case SAMPLING_RATE_48KHZ:
  1204. sample_rate_val = 6;
  1205. break;
  1206. case SAMPLING_RATE_88P2KHZ:
  1207. sample_rate_val = 7;
  1208. break;
  1209. case SAMPLING_RATE_96KHZ:
  1210. sample_rate_val = 8;
  1211. break;
  1212. case SAMPLING_RATE_176P4KHZ:
  1213. sample_rate_val = 9;
  1214. break;
  1215. case SAMPLING_RATE_192KHZ:
  1216. sample_rate_val = 10;
  1217. break;
  1218. case SAMPLING_RATE_352P8KHZ:
  1219. sample_rate_val = 11;
  1220. break;
  1221. case SAMPLING_RATE_384KHZ:
  1222. sample_rate_val = 12;
  1223. break;
  1224. default:
  1225. sample_rate_val = 6;
  1226. break;
  1227. }
  1228. return sample_rate_val;
  1229. }
  1230. static int cdc_dma_get_sample_rate(int value)
  1231. {
  1232. int sample_rate = 0;
  1233. switch (value) {
  1234. case 0:
  1235. sample_rate = SAMPLING_RATE_8KHZ;
  1236. break;
  1237. case 1:
  1238. sample_rate = SAMPLING_RATE_11P025KHZ;
  1239. break;
  1240. case 2:
  1241. sample_rate = SAMPLING_RATE_16KHZ;
  1242. break;
  1243. case 3:
  1244. sample_rate = SAMPLING_RATE_22P05KHZ;
  1245. break;
  1246. case 4:
  1247. sample_rate = SAMPLING_RATE_32KHZ;
  1248. break;
  1249. case 5:
  1250. sample_rate = SAMPLING_RATE_44P1KHZ;
  1251. break;
  1252. case 6:
  1253. sample_rate = SAMPLING_RATE_48KHZ;
  1254. break;
  1255. case 7:
  1256. sample_rate = SAMPLING_RATE_88P2KHZ;
  1257. break;
  1258. case 8:
  1259. sample_rate = SAMPLING_RATE_96KHZ;
  1260. break;
  1261. case 9:
  1262. sample_rate = SAMPLING_RATE_176P4KHZ;
  1263. break;
  1264. case 10:
  1265. sample_rate = SAMPLING_RATE_192KHZ;
  1266. break;
  1267. case 11:
  1268. sample_rate = SAMPLING_RATE_352P8KHZ;
  1269. break;
  1270. case 12:
  1271. sample_rate = SAMPLING_RATE_384KHZ;
  1272. break;
  1273. default:
  1274. sample_rate = SAMPLING_RATE_48KHZ;
  1275. break;
  1276. }
  1277. return sample_rate;
  1278. }
  1279. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1280. struct snd_ctl_elem_value *ucontrol)
  1281. {
  1282. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1283. if (ch_num < 0)
  1284. return ch_num;
  1285. ucontrol->value.enumerated.item[0] =
  1286. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1287. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1288. cdc_dma_rx_cfg[ch_num].sample_rate);
  1289. return 0;
  1290. }
  1291. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1292. struct snd_ctl_elem_value *ucontrol)
  1293. {
  1294. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1295. if (ch_num < 0)
  1296. return ch_num;
  1297. cdc_dma_rx_cfg[ch_num].sample_rate =
  1298. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1299. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1300. __func__, ucontrol->value.enumerated.item[0],
  1301. cdc_dma_rx_cfg[ch_num].sample_rate);
  1302. return 0;
  1303. }
  1304. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1305. struct snd_ctl_elem_value *ucontrol)
  1306. {
  1307. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1308. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1309. cdc_dma_tx_cfg[ch_num].channels);
  1310. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1311. return 0;
  1312. }
  1313. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1314. struct snd_ctl_elem_value *ucontrol)
  1315. {
  1316. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1317. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1318. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1319. cdc_dma_tx_cfg[ch_num].channels);
  1320. return 1;
  1321. }
  1322. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1323. struct snd_ctl_elem_value *ucontrol)
  1324. {
  1325. int sample_rate_val;
  1326. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1327. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1328. case SAMPLING_RATE_384KHZ:
  1329. sample_rate_val = 12;
  1330. break;
  1331. case SAMPLING_RATE_352P8KHZ:
  1332. sample_rate_val = 11;
  1333. break;
  1334. case SAMPLING_RATE_192KHZ:
  1335. sample_rate_val = 10;
  1336. break;
  1337. case SAMPLING_RATE_176P4KHZ:
  1338. sample_rate_val = 9;
  1339. break;
  1340. case SAMPLING_RATE_96KHZ:
  1341. sample_rate_val = 8;
  1342. break;
  1343. case SAMPLING_RATE_88P2KHZ:
  1344. sample_rate_val = 7;
  1345. break;
  1346. case SAMPLING_RATE_48KHZ:
  1347. sample_rate_val = 6;
  1348. break;
  1349. case SAMPLING_RATE_44P1KHZ:
  1350. sample_rate_val = 5;
  1351. break;
  1352. case SAMPLING_RATE_32KHZ:
  1353. sample_rate_val = 4;
  1354. break;
  1355. case SAMPLING_RATE_22P05KHZ:
  1356. sample_rate_val = 3;
  1357. break;
  1358. case SAMPLING_RATE_16KHZ:
  1359. sample_rate_val = 2;
  1360. break;
  1361. case SAMPLING_RATE_11P025KHZ:
  1362. sample_rate_val = 1;
  1363. break;
  1364. case SAMPLING_RATE_8KHZ:
  1365. sample_rate_val = 0;
  1366. break;
  1367. default:
  1368. sample_rate_val = 6;
  1369. break;
  1370. }
  1371. ucontrol->value.integer.value[0] = sample_rate_val;
  1372. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1373. cdc_dma_tx_cfg[ch_num].sample_rate);
  1374. return 0;
  1375. }
  1376. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1377. struct snd_ctl_elem_value *ucontrol)
  1378. {
  1379. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1380. switch (ucontrol->value.integer.value[0]) {
  1381. case 12:
  1382. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1383. break;
  1384. case 11:
  1385. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1386. break;
  1387. case 10:
  1388. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1389. break;
  1390. case 9:
  1391. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1392. break;
  1393. case 8:
  1394. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1395. break;
  1396. case 7:
  1397. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1398. break;
  1399. case 6:
  1400. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1401. break;
  1402. case 5:
  1403. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1404. break;
  1405. case 4:
  1406. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1407. break;
  1408. case 3:
  1409. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1410. break;
  1411. case 2:
  1412. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1413. break;
  1414. case 1:
  1415. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1416. break;
  1417. case 0:
  1418. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1419. break;
  1420. default:
  1421. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1422. break;
  1423. }
  1424. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1425. __func__, ucontrol->value.integer.value[0],
  1426. cdc_dma_tx_cfg[ch_num].sample_rate);
  1427. return 0;
  1428. }
  1429. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1430. struct snd_ctl_elem_value *ucontrol)
  1431. {
  1432. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1433. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1434. case SNDRV_PCM_FORMAT_S32_LE:
  1435. ucontrol->value.integer.value[0] = 3;
  1436. break;
  1437. case SNDRV_PCM_FORMAT_S24_3LE:
  1438. ucontrol->value.integer.value[0] = 2;
  1439. break;
  1440. case SNDRV_PCM_FORMAT_S24_LE:
  1441. ucontrol->value.integer.value[0] = 1;
  1442. break;
  1443. case SNDRV_PCM_FORMAT_S16_LE:
  1444. default:
  1445. ucontrol->value.integer.value[0] = 0;
  1446. break;
  1447. }
  1448. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1449. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1450. ucontrol->value.integer.value[0]);
  1451. return 0;
  1452. }
  1453. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1454. struct snd_ctl_elem_value *ucontrol)
  1455. {
  1456. int rc = 0;
  1457. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1458. switch (ucontrol->value.integer.value[0]) {
  1459. case 3:
  1460. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1461. break;
  1462. case 2:
  1463. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1464. break;
  1465. case 1:
  1466. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1467. break;
  1468. case 0:
  1469. default:
  1470. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1471. break;
  1472. }
  1473. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1474. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1475. ucontrol->value.integer.value[0]);
  1476. return rc;
  1477. }
  1478. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1479. struct snd_ctl_elem_value *ucontrol)
  1480. {
  1481. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1482. usb_rx_cfg.channels);
  1483. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1484. return 0;
  1485. }
  1486. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1487. struct snd_ctl_elem_value *ucontrol)
  1488. {
  1489. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1490. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1491. return 1;
  1492. }
  1493. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1494. struct snd_ctl_elem_value *ucontrol)
  1495. {
  1496. int sample_rate_val;
  1497. switch (usb_rx_cfg.sample_rate) {
  1498. case SAMPLING_RATE_384KHZ:
  1499. sample_rate_val = 12;
  1500. break;
  1501. case SAMPLING_RATE_352P8KHZ:
  1502. sample_rate_val = 11;
  1503. break;
  1504. case SAMPLING_RATE_192KHZ:
  1505. sample_rate_val = 10;
  1506. break;
  1507. case SAMPLING_RATE_176P4KHZ:
  1508. sample_rate_val = 9;
  1509. break;
  1510. case SAMPLING_RATE_96KHZ:
  1511. sample_rate_val = 8;
  1512. break;
  1513. case SAMPLING_RATE_88P2KHZ:
  1514. sample_rate_val = 7;
  1515. break;
  1516. case SAMPLING_RATE_48KHZ:
  1517. sample_rate_val = 6;
  1518. break;
  1519. case SAMPLING_RATE_44P1KHZ:
  1520. sample_rate_val = 5;
  1521. break;
  1522. case SAMPLING_RATE_32KHZ:
  1523. sample_rate_val = 4;
  1524. break;
  1525. case SAMPLING_RATE_22P05KHZ:
  1526. sample_rate_val = 3;
  1527. break;
  1528. case SAMPLING_RATE_16KHZ:
  1529. sample_rate_val = 2;
  1530. break;
  1531. case SAMPLING_RATE_11P025KHZ:
  1532. sample_rate_val = 1;
  1533. break;
  1534. case SAMPLING_RATE_8KHZ:
  1535. default:
  1536. sample_rate_val = 0;
  1537. break;
  1538. }
  1539. ucontrol->value.integer.value[0] = sample_rate_val;
  1540. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1541. usb_rx_cfg.sample_rate);
  1542. return 0;
  1543. }
  1544. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1545. struct snd_ctl_elem_value *ucontrol)
  1546. {
  1547. switch (ucontrol->value.integer.value[0]) {
  1548. case 12:
  1549. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1550. break;
  1551. case 11:
  1552. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1553. break;
  1554. case 10:
  1555. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1556. break;
  1557. case 9:
  1558. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1559. break;
  1560. case 8:
  1561. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1562. break;
  1563. case 7:
  1564. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1565. break;
  1566. case 6:
  1567. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1568. break;
  1569. case 5:
  1570. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1571. break;
  1572. case 4:
  1573. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1574. break;
  1575. case 3:
  1576. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1577. break;
  1578. case 2:
  1579. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1580. break;
  1581. case 1:
  1582. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1583. break;
  1584. case 0:
  1585. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1586. break;
  1587. default:
  1588. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1589. break;
  1590. }
  1591. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1592. __func__, ucontrol->value.integer.value[0],
  1593. usb_rx_cfg.sample_rate);
  1594. return 0;
  1595. }
  1596. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1597. struct snd_ctl_elem_value *ucontrol)
  1598. {
  1599. switch (usb_rx_cfg.bit_format) {
  1600. case SNDRV_PCM_FORMAT_S32_LE:
  1601. ucontrol->value.integer.value[0] = 3;
  1602. break;
  1603. case SNDRV_PCM_FORMAT_S24_3LE:
  1604. ucontrol->value.integer.value[0] = 2;
  1605. break;
  1606. case SNDRV_PCM_FORMAT_S24_LE:
  1607. ucontrol->value.integer.value[0] = 1;
  1608. break;
  1609. case SNDRV_PCM_FORMAT_S16_LE:
  1610. default:
  1611. ucontrol->value.integer.value[0] = 0;
  1612. break;
  1613. }
  1614. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1615. __func__, usb_rx_cfg.bit_format,
  1616. ucontrol->value.integer.value[0]);
  1617. return 0;
  1618. }
  1619. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1620. struct snd_ctl_elem_value *ucontrol)
  1621. {
  1622. int rc = 0;
  1623. switch (ucontrol->value.integer.value[0]) {
  1624. case 3:
  1625. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1626. break;
  1627. case 2:
  1628. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1629. break;
  1630. case 1:
  1631. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1632. break;
  1633. case 0:
  1634. default:
  1635. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1636. break;
  1637. }
  1638. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1639. __func__, usb_rx_cfg.bit_format,
  1640. ucontrol->value.integer.value[0]);
  1641. return rc;
  1642. }
  1643. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1644. struct snd_ctl_elem_value *ucontrol)
  1645. {
  1646. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1647. usb_tx_cfg.channels);
  1648. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1649. return 0;
  1650. }
  1651. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1652. struct snd_ctl_elem_value *ucontrol)
  1653. {
  1654. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1655. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1656. return 1;
  1657. }
  1658. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1659. struct snd_ctl_elem_value *ucontrol)
  1660. {
  1661. int sample_rate_val;
  1662. switch (usb_tx_cfg.sample_rate) {
  1663. case SAMPLING_RATE_384KHZ:
  1664. sample_rate_val = 12;
  1665. break;
  1666. case SAMPLING_RATE_352P8KHZ:
  1667. sample_rate_val = 11;
  1668. break;
  1669. case SAMPLING_RATE_192KHZ:
  1670. sample_rate_val = 10;
  1671. break;
  1672. case SAMPLING_RATE_176P4KHZ:
  1673. sample_rate_val = 9;
  1674. break;
  1675. case SAMPLING_RATE_96KHZ:
  1676. sample_rate_val = 8;
  1677. break;
  1678. case SAMPLING_RATE_88P2KHZ:
  1679. sample_rate_val = 7;
  1680. break;
  1681. case SAMPLING_RATE_48KHZ:
  1682. sample_rate_val = 6;
  1683. break;
  1684. case SAMPLING_RATE_44P1KHZ:
  1685. sample_rate_val = 5;
  1686. break;
  1687. case SAMPLING_RATE_32KHZ:
  1688. sample_rate_val = 4;
  1689. break;
  1690. case SAMPLING_RATE_22P05KHZ:
  1691. sample_rate_val = 3;
  1692. break;
  1693. case SAMPLING_RATE_16KHZ:
  1694. sample_rate_val = 2;
  1695. break;
  1696. case SAMPLING_RATE_11P025KHZ:
  1697. sample_rate_val = 1;
  1698. break;
  1699. case SAMPLING_RATE_8KHZ:
  1700. sample_rate_val = 0;
  1701. break;
  1702. default:
  1703. sample_rate_val = 6;
  1704. break;
  1705. }
  1706. ucontrol->value.integer.value[0] = sample_rate_val;
  1707. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1708. usb_tx_cfg.sample_rate);
  1709. return 0;
  1710. }
  1711. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1712. struct snd_ctl_elem_value *ucontrol)
  1713. {
  1714. switch (ucontrol->value.integer.value[0]) {
  1715. case 12:
  1716. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1717. break;
  1718. case 11:
  1719. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1720. break;
  1721. case 10:
  1722. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1723. break;
  1724. case 9:
  1725. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1726. break;
  1727. case 8:
  1728. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1729. break;
  1730. case 7:
  1731. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1732. break;
  1733. case 6:
  1734. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1735. break;
  1736. case 5:
  1737. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1738. break;
  1739. case 4:
  1740. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1741. break;
  1742. case 3:
  1743. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1744. break;
  1745. case 2:
  1746. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1747. break;
  1748. case 1:
  1749. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1750. break;
  1751. case 0:
  1752. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1753. break;
  1754. default:
  1755. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1756. break;
  1757. }
  1758. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1759. __func__, ucontrol->value.integer.value[0],
  1760. usb_tx_cfg.sample_rate);
  1761. return 0;
  1762. }
  1763. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1764. struct snd_ctl_elem_value *ucontrol)
  1765. {
  1766. switch (usb_tx_cfg.bit_format) {
  1767. case SNDRV_PCM_FORMAT_S32_LE:
  1768. ucontrol->value.integer.value[0] = 3;
  1769. break;
  1770. case SNDRV_PCM_FORMAT_S24_3LE:
  1771. ucontrol->value.integer.value[0] = 2;
  1772. break;
  1773. case SNDRV_PCM_FORMAT_S24_LE:
  1774. ucontrol->value.integer.value[0] = 1;
  1775. break;
  1776. case SNDRV_PCM_FORMAT_S16_LE:
  1777. default:
  1778. ucontrol->value.integer.value[0] = 0;
  1779. break;
  1780. }
  1781. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1782. __func__, usb_tx_cfg.bit_format,
  1783. ucontrol->value.integer.value[0]);
  1784. return 0;
  1785. }
  1786. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1787. struct snd_ctl_elem_value *ucontrol)
  1788. {
  1789. int rc = 0;
  1790. switch (ucontrol->value.integer.value[0]) {
  1791. case 3:
  1792. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1793. break;
  1794. case 2:
  1795. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1796. break;
  1797. case 1:
  1798. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1799. break;
  1800. case 0:
  1801. default:
  1802. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1803. break;
  1804. }
  1805. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1806. __func__, usb_tx_cfg.bit_format,
  1807. ucontrol->value.integer.value[0]);
  1808. return rc;
  1809. }
  1810. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1811. struct snd_ctl_elem_value *ucontrol)
  1812. {
  1813. pr_debug("%s: proxy_rx channels = %d\n",
  1814. __func__, proxy_rx_cfg.channels);
  1815. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1816. return 0;
  1817. }
  1818. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1819. struct snd_ctl_elem_value *ucontrol)
  1820. {
  1821. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1822. pr_debug("%s: proxy_rx channels = %d\n",
  1823. __func__, proxy_rx_cfg.channels);
  1824. return 1;
  1825. }
  1826. static int tdm_get_sample_rate(int value)
  1827. {
  1828. int sample_rate = 0;
  1829. switch (value) {
  1830. case 0:
  1831. sample_rate = SAMPLING_RATE_8KHZ;
  1832. break;
  1833. case 1:
  1834. sample_rate = SAMPLING_RATE_16KHZ;
  1835. break;
  1836. case 2:
  1837. sample_rate = SAMPLING_RATE_32KHZ;
  1838. break;
  1839. case 3:
  1840. sample_rate = SAMPLING_RATE_48KHZ;
  1841. break;
  1842. case 4:
  1843. sample_rate = SAMPLING_RATE_176P4KHZ;
  1844. break;
  1845. case 5:
  1846. sample_rate = SAMPLING_RATE_352P8KHZ;
  1847. break;
  1848. default:
  1849. sample_rate = SAMPLING_RATE_48KHZ;
  1850. break;
  1851. }
  1852. return sample_rate;
  1853. }
  1854. static int aux_pcm_get_sample_rate(int value)
  1855. {
  1856. int sample_rate;
  1857. switch (value) {
  1858. case 1:
  1859. sample_rate = SAMPLING_RATE_16KHZ;
  1860. break;
  1861. case 0:
  1862. default:
  1863. sample_rate = SAMPLING_RATE_8KHZ;
  1864. break;
  1865. }
  1866. return sample_rate;
  1867. }
  1868. static int tdm_get_sample_rate_val(int sample_rate)
  1869. {
  1870. int sample_rate_val = 0;
  1871. switch (sample_rate) {
  1872. case SAMPLING_RATE_8KHZ:
  1873. sample_rate_val = 0;
  1874. break;
  1875. case SAMPLING_RATE_16KHZ:
  1876. sample_rate_val = 1;
  1877. break;
  1878. case SAMPLING_RATE_32KHZ:
  1879. sample_rate_val = 2;
  1880. break;
  1881. case SAMPLING_RATE_48KHZ:
  1882. sample_rate_val = 3;
  1883. break;
  1884. case SAMPLING_RATE_176P4KHZ:
  1885. sample_rate_val = 4;
  1886. break;
  1887. case SAMPLING_RATE_352P8KHZ:
  1888. sample_rate_val = 5;
  1889. break;
  1890. default:
  1891. sample_rate_val = 3;
  1892. break;
  1893. }
  1894. return sample_rate_val;
  1895. }
  1896. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1897. {
  1898. int sample_rate_val;
  1899. switch (sample_rate) {
  1900. case SAMPLING_RATE_16KHZ:
  1901. sample_rate_val = 1;
  1902. break;
  1903. case SAMPLING_RATE_8KHZ:
  1904. default:
  1905. sample_rate_val = 0;
  1906. break;
  1907. }
  1908. return sample_rate_val;
  1909. }
  1910. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1911. struct tdm_port *port)
  1912. {
  1913. if (port) {
  1914. if (strnstr(kcontrol->id.name, "PRI",
  1915. sizeof(kcontrol->id.name))) {
  1916. port->mode = TDM_PRI;
  1917. } else if (strnstr(kcontrol->id.name, "SEC",
  1918. sizeof(kcontrol->id.name))) {
  1919. port->mode = TDM_SEC;
  1920. } else if (strnstr(kcontrol->id.name, "TERT",
  1921. sizeof(kcontrol->id.name))) {
  1922. port->mode = TDM_TERT;
  1923. } else if (strnstr(kcontrol->id.name, "QUAT",
  1924. sizeof(kcontrol->id.name))) {
  1925. port->mode = TDM_QUAT;
  1926. } else if (strnstr(kcontrol->id.name, "QUIN",
  1927. sizeof(kcontrol->id.name))) {
  1928. port->mode = TDM_QUIN;
  1929. } else {
  1930. pr_err("%s: unsupported mode in: %s",
  1931. __func__, kcontrol->id.name);
  1932. return -EINVAL;
  1933. }
  1934. if (strnstr(kcontrol->id.name, "RX_0",
  1935. sizeof(kcontrol->id.name)) ||
  1936. strnstr(kcontrol->id.name, "TX_0",
  1937. sizeof(kcontrol->id.name))) {
  1938. port->channel = TDM_0;
  1939. } else if (strnstr(kcontrol->id.name, "RX_1",
  1940. sizeof(kcontrol->id.name)) ||
  1941. strnstr(kcontrol->id.name, "TX_1",
  1942. sizeof(kcontrol->id.name))) {
  1943. port->channel = TDM_1;
  1944. } else if (strnstr(kcontrol->id.name, "RX_2",
  1945. sizeof(kcontrol->id.name)) ||
  1946. strnstr(kcontrol->id.name, "TX_2",
  1947. sizeof(kcontrol->id.name))) {
  1948. port->channel = TDM_2;
  1949. } else if (strnstr(kcontrol->id.name, "RX_3",
  1950. sizeof(kcontrol->id.name)) ||
  1951. strnstr(kcontrol->id.name, "TX_3",
  1952. sizeof(kcontrol->id.name))) {
  1953. port->channel = TDM_3;
  1954. } else if (strnstr(kcontrol->id.name, "RX_4",
  1955. sizeof(kcontrol->id.name)) ||
  1956. strnstr(kcontrol->id.name, "TX_4",
  1957. sizeof(kcontrol->id.name))) {
  1958. port->channel = TDM_4;
  1959. } else if (strnstr(kcontrol->id.name, "RX_5",
  1960. sizeof(kcontrol->id.name)) ||
  1961. strnstr(kcontrol->id.name, "TX_5",
  1962. sizeof(kcontrol->id.name))) {
  1963. port->channel = TDM_5;
  1964. } else if (strnstr(kcontrol->id.name, "RX_6",
  1965. sizeof(kcontrol->id.name)) ||
  1966. strnstr(kcontrol->id.name, "TX_6",
  1967. sizeof(kcontrol->id.name))) {
  1968. port->channel = TDM_6;
  1969. } else if (strnstr(kcontrol->id.name, "RX_7",
  1970. sizeof(kcontrol->id.name)) ||
  1971. strnstr(kcontrol->id.name, "TX_7",
  1972. sizeof(kcontrol->id.name))) {
  1973. port->channel = TDM_7;
  1974. } else {
  1975. pr_err("%s: unsupported channel in: %s",
  1976. __func__, kcontrol->id.name);
  1977. return -EINVAL;
  1978. }
  1979. } else
  1980. return -EINVAL;
  1981. return 0;
  1982. }
  1983. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1984. struct snd_ctl_elem_value *ucontrol)
  1985. {
  1986. struct tdm_port port;
  1987. int ret = tdm_get_port_idx(kcontrol, &port);
  1988. if (ret) {
  1989. pr_err("%s: unsupported control: %s",
  1990. __func__, kcontrol->id.name);
  1991. } else {
  1992. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1993. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1994. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1995. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1996. ucontrol->value.enumerated.item[0]);
  1997. }
  1998. return ret;
  1999. }
  2000. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2001. struct snd_ctl_elem_value *ucontrol)
  2002. {
  2003. struct tdm_port port;
  2004. int ret = tdm_get_port_idx(kcontrol, &port);
  2005. if (ret) {
  2006. pr_err("%s: unsupported control: %s",
  2007. __func__, kcontrol->id.name);
  2008. } else {
  2009. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  2010. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2011. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2012. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2013. ucontrol->value.enumerated.item[0]);
  2014. }
  2015. return ret;
  2016. }
  2017. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2018. struct snd_ctl_elem_value *ucontrol)
  2019. {
  2020. struct tdm_port port;
  2021. int ret = tdm_get_port_idx(kcontrol, &port);
  2022. if (ret) {
  2023. pr_err("%s: unsupported control: %s",
  2024. __func__, kcontrol->id.name);
  2025. } else {
  2026. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2027. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  2028. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2029. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2030. ucontrol->value.enumerated.item[0]);
  2031. }
  2032. return ret;
  2033. }
  2034. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2035. struct snd_ctl_elem_value *ucontrol)
  2036. {
  2037. struct tdm_port port;
  2038. int ret = tdm_get_port_idx(kcontrol, &port);
  2039. if (ret) {
  2040. pr_err("%s: unsupported control: %s",
  2041. __func__, kcontrol->id.name);
  2042. } else {
  2043. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  2044. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2045. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2046. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2047. ucontrol->value.enumerated.item[0]);
  2048. }
  2049. return ret;
  2050. }
  2051. static int tdm_get_format(int value)
  2052. {
  2053. int format = 0;
  2054. switch (value) {
  2055. case 0:
  2056. format = SNDRV_PCM_FORMAT_S16_LE;
  2057. break;
  2058. case 1:
  2059. format = SNDRV_PCM_FORMAT_S24_LE;
  2060. break;
  2061. case 2:
  2062. format = SNDRV_PCM_FORMAT_S32_LE;
  2063. break;
  2064. default:
  2065. format = SNDRV_PCM_FORMAT_S16_LE;
  2066. break;
  2067. }
  2068. return format;
  2069. }
  2070. static int tdm_get_format_val(int format)
  2071. {
  2072. int value = 0;
  2073. switch (format) {
  2074. case SNDRV_PCM_FORMAT_S16_LE:
  2075. value = 0;
  2076. break;
  2077. case SNDRV_PCM_FORMAT_S24_LE:
  2078. value = 1;
  2079. break;
  2080. case SNDRV_PCM_FORMAT_S32_LE:
  2081. value = 2;
  2082. break;
  2083. default:
  2084. value = 0;
  2085. break;
  2086. }
  2087. return value;
  2088. }
  2089. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2090. struct snd_ctl_elem_value *ucontrol)
  2091. {
  2092. struct tdm_port port;
  2093. int ret = tdm_get_port_idx(kcontrol, &port);
  2094. if (ret) {
  2095. pr_err("%s: unsupported control: %s",
  2096. __func__, kcontrol->id.name);
  2097. } else {
  2098. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2099. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2100. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2101. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2102. ucontrol->value.enumerated.item[0]);
  2103. }
  2104. return ret;
  2105. }
  2106. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2107. struct snd_ctl_elem_value *ucontrol)
  2108. {
  2109. struct tdm_port port;
  2110. int ret = tdm_get_port_idx(kcontrol, &port);
  2111. if (ret) {
  2112. pr_err("%s: unsupported control: %s",
  2113. __func__, kcontrol->id.name);
  2114. } else {
  2115. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2116. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2117. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2118. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2119. ucontrol->value.enumerated.item[0]);
  2120. }
  2121. return ret;
  2122. }
  2123. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2124. struct snd_ctl_elem_value *ucontrol)
  2125. {
  2126. struct tdm_port port;
  2127. int ret = tdm_get_port_idx(kcontrol, &port);
  2128. if (ret) {
  2129. pr_err("%s: unsupported control: %s",
  2130. __func__, kcontrol->id.name);
  2131. } else {
  2132. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2133. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2134. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2135. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2136. ucontrol->value.enumerated.item[0]);
  2137. }
  2138. return ret;
  2139. }
  2140. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2141. struct snd_ctl_elem_value *ucontrol)
  2142. {
  2143. struct tdm_port port;
  2144. int ret = tdm_get_port_idx(kcontrol, &port);
  2145. if (ret) {
  2146. pr_err("%s: unsupported control: %s",
  2147. __func__, kcontrol->id.name);
  2148. } else {
  2149. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2150. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2151. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2152. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2153. ucontrol->value.enumerated.item[0]);
  2154. }
  2155. return ret;
  2156. }
  2157. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2158. struct snd_ctl_elem_value *ucontrol)
  2159. {
  2160. struct tdm_port port;
  2161. int ret = tdm_get_port_idx(kcontrol, &port);
  2162. if (ret) {
  2163. pr_err("%s: unsupported control: %s",
  2164. __func__, kcontrol->id.name);
  2165. } else {
  2166. ucontrol->value.enumerated.item[0] =
  2167. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2168. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2169. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2170. ucontrol->value.enumerated.item[0]);
  2171. }
  2172. return ret;
  2173. }
  2174. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2175. struct snd_ctl_elem_value *ucontrol)
  2176. {
  2177. struct tdm_port port;
  2178. int ret = tdm_get_port_idx(kcontrol, &port);
  2179. if (ret) {
  2180. pr_err("%s: unsupported control: %s",
  2181. __func__, kcontrol->id.name);
  2182. } else {
  2183. tdm_rx_cfg[port.mode][port.channel].channels =
  2184. ucontrol->value.enumerated.item[0] + 1;
  2185. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2186. tdm_rx_cfg[port.mode][port.channel].channels,
  2187. ucontrol->value.enumerated.item[0] + 1);
  2188. }
  2189. return ret;
  2190. }
  2191. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2192. struct snd_ctl_elem_value *ucontrol)
  2193. {
  2194. struct tdm_port port;
  2195. int ret = tdm_get_port_idx(kcontrol, &port);
  2196. if (ret) {
  2197. pr_err("%s: unsupported control: %s",
  2198. __func__, kcontrol->id.name);
  2199. } else {
  2200. ucontrol->value.enumerated.item[0] =
  2201. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2202. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2203. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2204. ucontrol->value.enumerated.item[0]);
  2205. }
  2206. return ret;
  2207. }
  2208. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2209. struct snd_ctl_elem_value *ucontrol)
  2210. {
  2211. struct tdm_port port;
  2212. int ret = tdm_get_port_idx(kcontrol, &port);
  2213. if (ret) {
  2214. pr_err("%s: unsupported control: %s",
  2215. __func__, kcontrol->id.name);
  2216. } else {
  2217. tdm_tx_cfg[port.mode][port.channel].channels =
  2218. ucontrol->value.enumerated.item[0] + 1;
  2219. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2220. tdm_tx_cfg[port.mode][port.channel].channels,
  2221. ucontrol->value.enumerated.item[0] + 1);
  2222. }
  2223. return ret;
  2224. }
  2225. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2226. {
  2227. int idx;
  2228. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2229. sizeof("PRIM_AUX_PCM")))
  2230. idx = PRIM_AUX_PCM;
  2231. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2232. sizeof("SEC_AUX_PCM")))
  2233. idx = SEC_AUX_PCM;
  2234. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2235. sizeof("TERT_AUX_PCM")))
  2236. idx = TERT_AUX_PCM;
  2237. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2238. sizeof("QUAT_AUX_PCM")))
  2239. idx = QUAT_AUX_PCM;
  2240. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2241. sizeof("QUIN_AUX_PCM")))
  2242. idx = QUIN_AUX_PCM;
  2243. else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  2244. sizeof("SENN_AUX_PCM")))
  2245. idx = SEN_AUX_PCM;
  2246. else {
  2247. pr_err("%s: unsupported port: %s",
  2248. __func__, kcontrol->id.name);
  2249. idx = -EINVAL;
  2250. }
  2251. return idx;
  2252. }
  2253. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2254. struct snd_ctl_elem_value *ucontrol)
  2255. {
  2256. int idx = aux_pcm_get_port_idx(kcontrol);
  2257. if (idx < 0)
  2258. return idx;
  2259. aux_pcm_rx_cfg[idx].sample_rate =
  2260. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2261. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2262. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2263. ucontrol->value.enumerated.item[0]);
  2264. return 0;
  2265. }
  2266. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2267. struct snd_ctl_elem_value *ucontrol)
  2268. {
  2269. int idx = aux_pcm_get_port_idx(kcontrol);
  2270. if (idx < 0)
  2271. return idx;
  2272. ucontrol->value.enumerated.item[0] =
  2273. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2274. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2275. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2276. ucontrol->value.enumerated.item[0]);
  2277. return 0;
  2278. }
  2279. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2280. struct snd_ctl_elem_value *ucontrol)
  2281. {
  2282. int idx = aux_pcm_get_port_idx(kcontrol);
  2283. if (idx < 0)
  2284. return idx;
  2285. aux_pcm_tx_cfg[idx].sample_rate =
  2286. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2287. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2288. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2289. ucontrol->value.enumerated.item[0]);
  2290. return 0;
  2291. }
  2292. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2293. struct snd_ctl_elem_value *ucontrol)
  2294. {
  2295. int idx = aux_pcm_get_port_idx(kcontrol);
  2296. if (idx < 0)
  2297. return idx;
  2298. ucontrol->value.enumerated.item[0] =
  2299. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2300. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2301. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2302. ucontrol->value.enumerated.item[0]);
  2303. return 0;
  2304. }
  2305. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2306. {
  2307. int idx;
  2308. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2309. sizeof("PRIM_MI2S_RX")))
  2310. idx = PRIM_MI2S;
  2311. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2312. sizeof("SEC_MI2S_RX")))
  2313. idx = SEC_MI2S;
  2314. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2315. sizeof("TERT_MI2S_RX")))
  2316. idx = TERT_MI2S;
  2317. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2318. sizeof("QUAT_MI2S_RX")))
  2319. idx = QUAT_MI2S;
  2320. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2321. sizeof("QUIN_MI2S_RX")))
  2322. idx = QUIN_MI2S;
  2323. else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2324. sizeof("SEN_MI2S_RX")))
  2325. idx = SEN_MI2S;
  2326. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2327. sizeof("PRIM_MI2S_TX")))
  2328. idx = PRIM_MI2S;
  2329. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2330. sizeof("SEC_MI2S_TX")))
  2331. idx = SEC_MI2S;
  2332. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2333. sizeof("TERT_MI2S_TX")))
  2334. idx = TERT_MI2S;
  2335. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2336. sizeof("QUAT_MI2S_TX")))
  2337. idx = QUAT_MI2S;
  2338. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2339. sizeof("QUIN_MI2S_TX")))
  2340. idx = QUIN_MI2S;
  2341. else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2342. sizeof("SEN_MI2S_TX")))
  2343. idx = SEN_MI2S;
  2344. else {
  2345. pr_err("%s: unsupported channel: %s",
  2346. __func__, kcontrol->id.name);
  2347. idx = -EINVAL;
  2348. }
  2349. return idx;
  2350. }
  2351. static int mi2s_get_sample_rate_val(int sample_rate)
  2352. {
  2353. int sample_rate_val;
  2354. switch (sample_rate) {
  2355. case SAMPLING_RATE_8KHZ:
  2356. sample_rate_val = 0;
  2357. break;
  2358. case SAMPLING_RATE_11P025KHZ:
  2359. sample_rate_val = 1;
  2360. break;
  2361. case SAMPLING_RATE_16KHZ:
  2362. sample_rate_val = 2;
  2363. break;
  2364. case SAMPLING_RATE_22P05KHZ:
  2365. sample_rate_val = 3;
  2366. break;
  2367. case SAMPLING_RATE_32KHZ:
  2368. sample_rate_val = 4;
  2369. break;
  2370. case SAMPLING_RATE_44P1KHZ:
  2371. sample_rate_val = 5;
  2372. break;
  2373. case SAMPLING_RATE_48KHZ:
  2374. sample_rate_val = 6;
  2375. break;
  2376. case SAMPLING_RATE_96KHZ:
  2377. sample_rate_val = 7;
  2378. break;
  2379. case SAMPLING_RATE_192KHZ:
  2380. sample_rate_val = 8;
  2381. break;
  2382. case SAMPLING_RATE_384KHZ:
  2383. sample_rate_val = 9;
  2384. break;
  2385. default:
  2386. sample_rate_val = 6;
  2387. break;
  2388. }
  2389. return sample_rate_val;
  2390. }
  2391. static int mi2s_get_sample_rate(int value)
  2392. {
  2393. int sample_rate;
  2394. switch (value) {
  2395. case 0:
  2396. sample_rate = SAMPLING_RATE_8KHZ;
  2397. break;
  2398. case 1:
  2399. sample_rate = SAMPLING_RATE_11P025KHZ;
  2400. break;
  2401. case 2:
  2402. sample_rate = SAMPLING_RATE_16KHZ;
  2403. break;
  2404. case 3:
  2405. sample_rate = SAMPLING_RATE_22P05KHZ;
  2406. break;
  2407. case 4:
  2408. sample_rate = SAMPLING_RATE_32KHZ;
  2409. break;
  2410. case 5:
  2411. sample_rate = SAMPLING_RATE_44P1KHZ;
  2412. break;
  2413. case 6:
  2414. sample_rate = SAMPLING_RATE_48KHZ;
  2415. break;
  2416. case 7:
  2417. sample_rate = SAMPLING_RATE_96KHZ;
  2418. break;
  2419. case 8:
  2420. sample_rate = SAMPLING_RATE_192KHZ;
  2421. break;
  2422. case 9:
  2423. sample_rate = SAMPLING_RATE_384KHZ;
  2424. break;
  2425. default:
  2426. sample_rate = SAMPLING_RATE_48KHZ;
  2427. break;
  2428. }
  2429. return sample_rate;
  2430. }
  2431. static int mi2s_auxpcm_get_format(int value)
  2432. {
  2433. int format;
  2434. switch (value) {
  2435. case 0:
  2436. format = SNDRV_PCM_FORMAT_S16_LE;
  2437. break;
  2438. case 1:
  2439. format = SNDRV_PCM_FORMAT_S24_LE;
  2440. break;
  2441. case 2:
  2442. format = SNDRV_PCM_FORMAT_S24_3LE;
  2443. break;
  2444. case 3:
  2445. format = SNDRV_PCM_FORMAT_S32_LE;
  2446. break;
  2447. default:
  2448. format = SNDRV_PCM_FORMAT_S16_LE;
  2449. break;
  2450. }
  2451. return format;
  2452. }
  2453. static int mi2s_auxpcm_get_format_value(int format)
  2454. {
  2455. int value;
  2456. switch (format) {
  2457. case SNDRV_PCM_FORMAT_S16_LE:
  2458. value = 0;
  2459. break;
  2460. case SNDRV_PCM_FORMAT_S24_LE:
  2461. value = 1;
  2462. break;
  2463. case SNDRV_PCM_FORMAT_S24_3LE:
  2464. value = 2;
  2465. break;
  2466. case SNDRV_PCM_FORMAT_S32_LE:
  2467. value = 3;
  2468. break;
  2469. default:
  2470. value = 0;
  2471. break;
  2472. }
  2473. return value;
  2474. }
  2475. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2476. struct snd_ctl_elem_value *ucontrol)
  2477. {
  2478. int idx = mi2s_get_port_idx(kcontrol);
  2479. if (idx < 0)
  2480. return idx;
  2481. mi2s_rx_cfg[idx].sample_rate =
  2482. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2483. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2484. idx, mi2s_rx_cfg[idx].sample_rate,
  2485. ucontrol->value.enumerated.item[0]);
  2486. return 0;
  2487. }
  2488. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2489. struct snd_ctl_elem_value *ucontrol)
  2490. {
  2491. int idx = mi2s_get_port_idx(kcontrol);
  2492. if (idx < 0)
  2493. return idx;
  2494. ucontrol->value.enumerated.item[0] =
  2495. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2496. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2497. idx, mi2s_rx_cfg[idx].sample_rate,
  2498. ucontrol->value.enumerated.item[0]);
  2499. return 0;
  2500. }
  2501. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2502. struct snd_ctl_elem_value *ucontrol)
  2503. {
  2504. int idx = mi2s_get_port_idx(kcontrol);
  2505. if (idx < 0)
  2506. return idx;
  2507. mi2s_tx_cfg[idx].sample_rate =
  2508. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2509. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2510. idx, mi2s_tx_cfg[idx].sample_rate,
  2511. ucontrol->value.enumerated.item[0]);
  2512. return 0;
  2513. }
  2514. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2515. struct snd_ctl_elem_value *ucontrol)
  2516. {
  2517. int idx = mi2s_get_port_idx(kcontrol);
  2518. if (idx < 0)
  2519. return idx;
  2520. ucontrol->value.enumerated.item[0] =
  2521. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2522. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2523. idx, mi2s_tx_cfg[idx].sample_rate,
  2524. ucontrol->value.enumerated.item[0]);
  2525. return 0;
  2526. }
  2527. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2528. struct snd_ctl_elem_value *ucontrol)
  2529. {
  2530. int idx = mi2s_get_port_idx(kcontrol);
  2531. if (idx < 0)
  2532. return idx;
  2533. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2534. idx, mi2s_rx_cfg[idx].channels);
  2535. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2536. return 0;
  2537. }
  2538. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2539. struct snd_ctl_elem_value *ucontrol)
  2540. {
  2541. int idx = mi2s_get_port_idx(kcontrol);
  2542. if (idx < 0)
  2543. return idx;
  2544. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2545. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2546. idx, mi2s_rx_cfg[idx].channels);
  2547. return 1;
  2548. }
  2549. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2550. struct snd_ctl_elem_value *ucontrol)
  2551. {
  2552. int idx = mi2s_get_port_idx(kcontrol);
  2553. if (idx < 0)
  2554. return idx;
  2555. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2556. idx, mi2s_tx_cfg[idx].channels);
  2557. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2558. return 0;
  2559. }
  2560. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2561. struct snd_ctl_elem_value *ucontrol)
  2562. {
  2563. int idx = mi2s_get_port_idx(kcontrol);
  2564. if (idx < 0)
  2565. return idx;
  2566. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2567. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2568. idx, mi2s_tx_cfg[idx].channels);
  2569. return 1;
  2570. }
  2571. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2572. struct snd_ctl_elem_value *ucontrol)
  2573. {
  2574. int idx = mi2s_get_port_idx(kcontrol);
  2575. if (idx < 0)
  2576. return idx;
  2577. ucontrol->value.enumerated.item[0] =
  2578. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2579. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2580. idx, mi2s_rx_cfg[idx].bit_format,
  2581. ucontrol->value.enumerated.item[0]);
  2582. return 0;
  2583. }
  2584. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2585. struct snd_ctl_elem_value *ucontrol)
  2586. {
  2587. struct msm_asoc_mach_data *pdata = NULL;
  2588. struct snd_soc_component *component = NULL;
  2589. struct snd_soc_card *card = NULL;
  2590. int idx = mi2s_get_port_idx(kcontrol);
  2591. component = snd_soc_kcontrol_component(kcontrol);
  2592. card = kcontrol->private_data;
  2593. pdata = snd_soc_card_get_drvdata(card);
  2594. if (idx < 0)
  2595. return idx;
  2596. /* check for PRIM_MI2S and CSRAx config to allow 24bit BE config only */
  2597. if ((PRIM_MI2S == idx) && (true==pdata->codec_is_csra))
  2598. {
  2599. mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2600. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  2601. __func__, idx, mi2s_rx_cfg[idx].bit_format,
  2602. ucontrol->value.enumerated.item[0]);
  2603. } else {
  2604. mi2s_rx_cfg[idx].bit_format =
  2605. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2606. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2607. idx, mi2s_rx_cfg[idx].bit_format,
  2608. ucontrol->value.enumerated.item[0]);
  2609. }
  2610. return 0;
  2611. }
  2612. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2613. struct snd_ctl_elem_value *ucontrol)
  2614. {
  2615. int idx = mi2s_get_port_idx(kcontrol);
  2616. if (idx < 0)
  2617. return idx;
  2618. ucontrol->value.enumerated.item[0] =
  2619. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2620. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2621. idx, mi2s_tx_cfg[idx].bit_format,
  2622. ucontrol->value.enumerated.item[0]);
  2623. return 0;
  2624. }
  2625. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2626. struct snd_ctl_elem_value *ucontrol)
  2627. {
  2628. int idx = mi2s_get_port_idx(kcontrol);
  2629. if (idx < 0)
  2630. return idx;
  2631. mi2s_tx_cfg[idx].bit_format =
  2632. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2633. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2634. idx, mi2s_tx_cfg[idx].bit_format,
  2635. ucontrol->value.enumerated.item[0]);
  2636. return 0;
  2637. }
  2638. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2639. struct snd_ctl_elem_value *ucontrol)
  2640. {
  2641. int idx = aux_pcm_get_port_idx(kcontrol);
  2642. if (idx < 0)
  2643. return idx;
  2644. ucontrol->value.enumerated.item[0] =
  2645. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2646. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2647. idx, aux_pcm_rx_cfg[idx].bit_format,
  2648. ucontrol->value.enumerated.item[0]);
  2649. return 0;
  2650. }
  2651. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2652. struct snd_ctl_elem_value *ucontrol)
  2653. {
  2654. int idx = aux_pcm_get_port_idx(kcontrol);
  2655. if (idx < 0)
  2656. return idx;
  2657. aux_pcm_rx_cfg[idx].bit_format =
  2658. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2659. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2660. idx, aux_pcm_rx_cfg[idx].bit_format,
  2661. ucontrol->value.enumerated.item[0]);
  2662. return 0;
  2663. }
  2664. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2665. struct snd_ctl_elem_value *ucontrol)
  2666. {
  2667. int idx = aux_pcm_get_port_idx(kcontrol);
  2668. if (idx < 0)
  2669. return idx;
  2670. ucontrol->value.enumerated.item[0] =
  2671. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2672. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2673. idx, aux_pcm_tx_cfg[idx].bit_format,
  2674. ucontrol->value.enumerated.item[0]);
  2675. return 0;
  2676. }
  2677. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2678. struct snd_ctl_elem_value *ucontrol)
  2679. {
  2680. int idx = aux_pcm_get_port_idx(kcontrol);
  2681. if (idx < 0)
  2682. return idx;
  2683. aux_pcm_tx_cfg[idx].bit_format =
  2684. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2685. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2686. idx, aux_pcm_tx_cfg[idx].bit_format,
  2687. ucontrol->value.enumerated.item[0]);
  2688. return 0;
  2689. }
  2690. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2691. {
  2692. int idx;
  2693. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2694. sizeof("PRIM_SPDIF_RX")))
  2695. idx = PRIM_SPDIF_RX;
  2696. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2697. sizeof("SEC_SPDIF_RX")))
  2698. idx = SEC_SPDIF_RX;
  2699. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2700. sizeof("PRIM_SPDIF_TX")))
  2701. idx = PRIM_SPDIF_TX;
  2702. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2703. sizeof("SEC_SPDIF_TX")))
  2704. idx = SEC_SPDIF_TX;
  2705. else {
  2706. pr_err("%s: unsupported channel: %s",
  2707. __func__, kcontrol->id.name);
  2708. idx = -EINVAL;
  2709. }
  2710. return idx;
  2711. }
  2712. static int spdif_get_sample_rate_val(int sample_rate)
  2713. {
  2714. int sample_rate_val;
  2715. switch (sample_rate) {
  2716. case SAMPLING_RATE_32KHZ:
  2717. sample_rate_val = 0;
  2718. break;
  2719. case SAMPLING_RATE_44P1KHZ:
  2720. sample_rate_val = 1;
  2721. break;
  2722. case SAMPLING_RATE_48KHZ:
  2723. sample_rate_val = 2;
  2724. break;
  2725. case SAMPLING_RATE_88P2KHZ:
  2726. sample_rate_val = 3;
  2727. break;
  2728. case SAMPLING_RATE_96KHZ:
  2729. sample_rate_val = 4;
  2730. break;
  2731. case SAMPLING_RATE_176P4KHZ:
  2732. sample_rate_val = 5;
  2733. break;
  2734. case SAMPLING_RATE_192KHZ:
  2735. sample_rate_val = 6;
  2736. break;
  2737. default:
  2738. sample_rate_val = 2;
  2739. break;
  2740. }
  2741. return sample_rate_val;
  2742. }
  2743. static int spdif_get_sample_rate(int value)
  2744. {
  2745. int sample_rate;
  2746. switch (value) {
  2747. case 0:
  2748. sample_rate = SAMPLING_RATE_32KHZ;
  2749. break;
  2750. case 1:
  2751. sample_rate = SAMPLING_RATE_44P1KHZ;
  2752. break;
  2753. case 2:
  2754. sample_rate = SAMPLING_RATE_48KHZ;
  2755. break;
  2756. case 3:
  2757. sample_rate = SAMPLING_RATE_88P2KHZ;
  2758. break;
  2759. case 4:
  2760. sample_rate = SAMPLING_RATE_96KHZ;
  2761. break;
  2762. case 5:
  2763. sample_rate = SAMPLING_RATE_176P4KHZ;
  2764. break;
  2765. case 6:
  2766. sample_rate = SAMPLING_RATE_192KHZ;
  2767. break;
  2768. default:
  2769. sample_rate = SAMPLING_RATE_48KHZ;
  2770. break;
  2771. }
  2772. return sample_rate;
  2773. }
  2774. static int spdif_get_format(int value)
  2775. {
  2776. int format;
  2777. switch (value) {
  2778. case 0:
  2779. format = SNDRV_PCM_FORMAT_S16_LE;
  2780. break;
  2781. case 1:
  2782. format = SNDRV_PCM_FORMAT_S24_LE;
  2783. break;
  2784. default:
  2785. format = SNDRV_PCM_FORMAT_S16_LE;
  2786. break;
  2787. }
  2788. return format;
  2789. }
  2790. static int spdif_get_format_value(int format)
  2791. {
  2792. int value;
  2793. switch (format) {
  2794. case SNDRV_PCM_FORMAT_S16_LE:
  2795. value = 0;
  2796. break;
  2797. case SNDRV_PCM_FORMAT_S24_LE:
  2798. value = 1;
  2799. break;
  2800. default:
  2801. value = 0;
  2802. break;
  2803. }
  2804. return value;
  2805. }
  2806. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2807. struct snd_ctl_elem_value *ucontrol)
  2808. {
  2809. int idx = spdif_get_port_idx(kcontrol);
  2810. if (idx < 0)
  2811. return idx;
  2812. spdif_rx_cfg[idx].sample_rate =
  2813. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2814. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2815. idx, spdif_rx_cfg[idx].sample_rate,
  2816. ucontrol->value.enumerated.item[0]);
  2817. return 0;
  2818. }
  2819. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2820. struct snd_ctl_elem_value *ucontrol)
  2821. {
  2822. int idx = spdif_get_port_idx(kcontrol);
  2823. if (idx < 0)
  2824. return idx;
  2825. ucontrol->value.enumerated.item[0] =
  2826. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2827. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2828. idx, spdif_rx_cfg[idx].sample_rate,
  2829. ucontrol->value.enumerated.item[0]);
  2830. return 0;
  2831. }
  2832. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2833. struct snd_ctl_elem_value *ucontrol)
  2834. {
  2835. int idx = spdif_get_port_idx(kcontrol);
  2836. if (idx < 0)
  2837. return idx;
  2838. spdif_tx_cfg[idx].sample_rate =
  2839. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2840. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2841. idx, spdif_tx_cfg[idx].sample_rate,
  2842. ucontrol->value.enumerated.item[0]);
  2843. return 0;
  2844. }
  2845. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2846. struct snd_ctl_elem_value *ucontrol)
  2847. {
  2848. int idx = spdif_get_port_idx(kcontrol);
  2849. if (idx < 0)
  2850. return idx;
  2851. ucontrol->value.enumerated.item[0] =
  2852. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2853. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2854. idx, spdif_tx_cfg[idx].sample_rate,
  2855. ucontrol->value.enumerated.item[0]);
  2856. return 0;
  2857. }
  2858. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2859. struct snd_ctl_elem_value *ucontrol)
  2860. {
  2861. int idx = spdif_get_port_idx(kcontrol);
  2862. if (idx < 0)
  2863. return idx;
  2864. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2865. idx, spdif_rx_cfg[idx].channels);
  2866. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2867. return 0;
  2868. }
  2869. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2870. struct snd_ctl_elem_value *ucontrol)
  2871. {
  2872. int idx = spdif_get_port_idx(kcontrol);
  2873. if (idx < 0)
  2874. return idx;
  2875. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2876. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2877. idx, spdif_rx_cfg[idx].channels);
  2878. return 1;
  2879. }
  2880. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2881. struct snd_ctl_elem_value *ucontrol)
  2882. {
  2883. int idx = spdif_get_port_idx(kcontrol);
  2884. if (idx < 0)
  2885. return idx;
  2886. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2887. idx, spdif_tx_cfg[idx].channels);
  2888. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2889. return 0;
  2890. }
  2891. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2892. struct snd_ctl_elem_value *ucontrol)
  2893. {
  2894. int idx = spdif_get_port_idx(kcontrol);
  2895. if (idx < 0)
  2896. return idx;
  2897. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2898. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2899. idx, spdif_tx_cfg[idx].channels);
  2900. return 1;
  2901. }
  2902. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2903. struct snd_ctl_elem_value *ucontrol)
  2904. {
  2905. int idx = spdif_get_port_idx(kcontrol);
  2906. if (idx < 0)
  2907. return idx;
  2908. ucontrol->value.enumerated.item[0] =
  2909. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2910. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2911. idx, spdif_rx_cfg[idx].bit_format,
  2912. ucontrol->value.enumerated.item[0]);
  2913. return 0;
  2914. }
  2915. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2916. struct snd_ctl_elem_value *ucontrol)
  2917. {
  2918. int idx = spdif_get_port_idx(kcontrol);
  2919. if (idx < 0)
  2920. return idx;
  2921. spdif_rx_cfg[idx].bit_format =
  2922. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2923. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2924. idx, spdif_rx_cfg[idx].bit_format,
  2925. ucontrol->value.enumerated.item[0]);
  2926. return 0;
  2927. }
  2928. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2929. struct snd_ctl_elem_value *ucontrol)
  2930. {
  2931. int idx = spdif_get_port_idx(kcontrol);
  2932. if (idx < 0)
  2933. return idx;
  2934. ucontrol->value.enumerated.item[0] =
  2935. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2936. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2937. idx, spdif_tx_cfg[idx].bit_format,
  2938. ucontrol->value.enumerated.item[0]);
  2939. return 0;
  2940. }
  2941. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2942. struct snd_ctl_elem_value *ucontrol)
  2943. {
  2944. int idx = spdif_get_port_idx(kcontrol);
  2945. if (idx < 0)
  2946. return idx;
  2947. spdif_tx_cfg[idx].bit_format =
  2948. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2949. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2950. idx, spdif_tx_cfg[idx].bit_format,
  2951. ucontrol->value.enumerated.item[0]);
  2952. return 0;
  2953. }
  2954. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2955. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2956. slim_rx_ch_get, slim_rx_ch_put),
  2957. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2958. slim_rx_ch_get, slim_rx_ch_put),
  2959. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2960. slim_tx_ch_get, slim_tx_ch_put),
  2961. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2962. slim_tx_ch_get, slim_tx_ch_put),
  2963. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2964. slim_rx_ch_get, slim_rx_ch_put),
  2965. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2966. slim_rx_ch_get, slim_rx_ch_put),
  2967. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2968. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2969. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2970. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2971. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2972. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2973. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2974. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2975. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2976. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2977. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2978. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2979. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2980. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2981. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2982. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2983. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2984. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2985. };
  2986. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2987. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2988. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2989. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2990. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2991. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2992. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2993. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2994. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2995. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2996. va_cdc_dma_tx_0_sample_rate,
  2997. cdc_dma_tx_sample_rate_get,
  2998. cdc_dma_tx_sample_rate_put),
  2999. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3000. va_cdc_dma_tx_1_sample_rate,
  3001. cdc_dma_tx_sample_rate_get,
  3002. cdc_dma_tx_sample_rate_put),
  3003. };
  3004. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  3005. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3006. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3007. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3008. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3009. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3010. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3011. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3012. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3013. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3014. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3015. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3016. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3017. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3018. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3019. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3020. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3021. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3022. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3023. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3024. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3025. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3026. wsa_cdc_dma_rx_0_sample_rate,
  3027. cdc_dma_rx_sample_rate_get,
  3028. cdc_dma_rx_sample_rate_put),
  3029. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3030. wsa_cdc_dma_rx_1_sample_rate,
  3031. cdc_dma_rx_sample_rate_get,
  3032. cdc_dma_rx_sample_rate_put),
  3033. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3034. wsa_cdc_dma_tx_0_sample_rate,
  3035. cdc_dma_tx_sample_rate_get,
  3036. cdc_dma_tx_sample_rate_put),
  3037. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3038. wsa_cdc_dma_tx_1_sample_rate,
  3039. cdc_dma_tx_sample_rate_get,
  3040. cdc_dma_tx_sample_rate_put),
  3041. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3042. wsa_cdc_dma_tx_2_sample_rate,
  3043. cdc_dma_tx_sample_rate_get,
  3044. cdc_dma_tx_sample_rate_put),
  3045. };
  3046. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3047. SOC_ENUM_EXT("BT_TX SampleRate", bt_sample_rate_sink,
  3048. msm_bt_sample_rate_sink_get,
  3049. msm_bt_sample_rate_sink_put),
  3050. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3051. msm_bt_sample_rate_get,
  3052. msm_bt_sample_rate_put),
  3053. SOC_ENUM_EXT("BT_RX SampleRate", bt_sample_rate,
  3054. msm_bt_sample_rate_get,
  3055. msm_bt_sample_rate_put),
  3056. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3057. proxy_rx_ch_get, proxy_rx_ch_put),
  3058. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3059. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3060. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3061. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3062. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3063. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3064. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3065. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3066. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3067. usb_audio_rx_sample_rate_get,
  3068. usb_audio_rx_sample_rate_put),
  3069. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3070. usb_audio_tx_sample_rate_get,
  3071. usb_audio_tx_sample_rate_put),
  3072. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3073. tdm_rx_sample_rate_get,
  3074. tdm_rx_sample_rate_put),
  3075. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3076. tdm_tx_sample_rate_get,
  3077. tdm_tx_sample_rate_put),
  3078. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3079. tdm_rx_format_get,
  3080. tdm_rx_format_put),
  3081. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3082. tdm_tx_format_get,
  3083. tdm_tx_format_put),
  3084. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3085. tdm_rx_ch_get,
  3086. tdm_rx_ch_put),
  3087. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3088. tdm_tx_ch_get,
  3089. tdm_tx_ch_put),
  3090. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3091. tdm_rx_sample_rate_get,
  3092. tdm_rx_sample_rate_put),
  3093. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3094. tdm_tx_sample_rate_get,
  3095. tdm_tx_sample_rate_put),
  3096. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3097. tdm_rx_format_get,
  3098. tdm_rx_format_put),
  3099. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3100. tdm_tx_format_get,
  3101. tdm_tx_format_put),
  3102. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3103. tdm_rx_ch_get,
  3104. tdm_rx_ch_put),
  3105. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3106. tdm_tx_ch_get,
  3107. tdm_tx_ch_put),
  3108. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3109. tdm_rx_sample_rate_get,
  3110. tdm_rx_sample_rate_put),
  3111. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3112. tdm_tx_sample_rate_get,
  3113. tdm_tx_sample_rate_put),
  3114. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3115. tdm_rx_format_get,
  3116. tdm_rx_format_put),
  3117. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3118. tdm_tx_format_get,
  3119. tdm_tx_format_put),
  3120. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3121. tdm_rx_ch_get,
  3122. tdm_rx_ch_put),
  3123. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3124. tdm_tx_ch_get,
  3125. tdm_tx_ch_put),
  3126. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3127. tdm_rx_sample_rate_get,
  3128. tdm_rx_sample_rate_put),
  3129. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3130. tdm_tx_sample_rate_get,
  3131. tdm_tx_sample_rate_put),
  3132. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3133. tdm_rx_format_get,
  3134. tdm_rx_format_put),
  3135. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3136. tdm_tx_format_get,
  3137. tdm_tx_format_put),
  3138. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3139. tdm_rx_ch_get,
  3140. tdm_rx_ch_put),
  3141. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3142. tdm_tx_ch_get,
  3143. tdm_tx_ch_put),
  3144. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3145. tdm_rx_sample_rate_get,
  3146. tdm_rx_sample_rate_put),
  3147. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3148. tdm_tx_sample_rate_get,
  3149. tdm_tx_sample_rate_put),
  3150. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3151. tdm_rx_format_get,
  3152. tdm_rx_format_put),
  3153. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3154. tdm_tx_format_get,
  3155. tdm_tx_format_put),
  3156. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3157. tdm_rx_ch_get,
  3158. tdm_rx_ch_put),
  3159. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3160. tdm_tx_ch_get,
  3161. tdm_tx_ch_put),
  3162. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3163. aux_pcm_rx_sample_rate_get,
  3164. aux_pcm_rx_sample_rate_put),
  3165. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3166. aux_pcm_rx_sample_rate_get,
  3167. aux_pcm_rx_sample_rate_put),
  3168. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3169. aux_pcm_rx_sample_rate_get,
  3170. aux_pcm_rx_sample_rate_put),
  3171. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3172. aux_pcm_rx_sample_rate_get,
  3173. aux_pcm_rx_sample_rate_put),
  3174. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3175. aux_pcm_rx_sample_rate_get,
  3176. aux_pcm_rx_sample_rate_put),
  3177. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3178. aux_pcm_tx_sample_rate_get,
  3179. aux_pcm_tx_sample_rate_put),
  3180. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3181. aux_pcm_tx_sample_rate_get,
  3182. aux_pcm_tx_sample_rate_put),
  3183. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3184. aux_pcm_tx_sample_rate_get,
  3185. aux_pcm_tx_sample_rate_put),
  3186. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3187. aux_pcm_tx_sample_rate_get,
  3188. aux_pcm_tx_sample_rate_put),
  3189. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3190. aux_pcm_tx_sample_rate_get,
  3191. aux_pcm_tx_sample_rate_put),
  3192. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3193. aux_pcm_tx_sample_rate_get,
  3194. aux_pcm_tx_sample_rate_put),
  3195. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3196. mi2s_rx_sample_rate_get,
  3197. mi2s_rx_sample_rate_put),
  3198. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3199. mi2s_rx_sample_rate_get,
  3200. mi2s_rx_sample_rate_put),
  3201. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3202. mi2s_rx_sample_rate_get,
  3203. mi2s_rx_sample_rate_put),
  3204. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3205. mi2s_rx_sample_rate_get,
  3206. mi2s_rx_sample_rate_put),
  3207. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3208. mi2s_rx_sample_rate_get,
  3209. mi2s_rx_sample_rate_put),
  3210. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3211. mi2s_rx_sample_rate_get,
  3212. mi2s_rx_sample_rate_put),
  3213. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3214. mi2s_tx_sample_rate_get,
  3215. mi2s_tx_sample_rate_put),
  3216. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3217. mi2s_tx_sample_rate_get,
  3218. mi2s_tx_sample_rate_put),
  3219. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3220. mi2s_tx_sample_rate_get,
  3221. mi2s_tx_sample_rate_put),
  3222. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3223. mi2s_tx_sample_rate_get,
  3224. mi2s_tx_sample_rate_put),
  3225. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3226. mi2s_tx_sample_rate_get,
  3227. mi2s_tx_sample_rate_put),
  3228. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3229. mi2s_tx_sample_rate_get,
  3230. mi2s_tx_sample_rate_put),
  3231. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3232. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3233. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3234. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3235. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3236. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3237. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3238. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3239. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3240. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3241. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3242. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3243. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3244. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3245. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3246. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3247. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3248. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3249. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3250. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3251. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3252. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3253. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3254. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3255. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3256. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3257. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3258. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3259. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3260. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3261. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3262. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3263. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3264. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3265. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3266. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3267. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3268. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3269. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3270. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3271. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3272. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3273. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3274. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3275. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3276. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3277. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3278. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3279. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3280. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3281. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3282. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3283. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3284. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3285. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3286. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3287. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3288. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3289. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3290. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3291. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3292. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3293. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3294. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3295. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3296. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3297. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3298. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3299. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3300. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3301. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3302. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3303. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3304. msm_snd_vad_cfg_put),
  3305. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3306. msm_spdif_rx_sample_rate_get,
  3307. msm_spdif_rx_sample_rate_put),
  3308. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3309. msm_spdif_tx_sample_rate_get,
  3310. msm_spdif_tx_sample_rate_put),
  3311. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3312. msm_spdif_rx_sample_rate_get,
  3313. msm_spdif_rx_sample_rate_put),
  3314. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3315. msm_spdif_tx_sample_rate_get,
  3316. msm_spdif_tx_sample_rate_put),
  3317. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3318. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3319. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3320. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3321. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3322. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3323. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3324. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3325. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3326. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3327. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3328. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3329. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3330. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3331. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3332. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3333. };
  3334. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  3335. int enable, bool dapm)
  3336. {
  3337. int ret = 0;
  3338. if (!strcmp(component.name, "tasha_codec")) {
  3339. ret = tasha_cdc_mclk_enable(component, enable, dapm);
  3340. } else {
  3341. dev_err(component->dev, "%s: unknown codec to enable ext clk\n",
  3342. __func__);
  3343. ret = -EINVAL;
  3344. }
  3345. return ret;
  3346. }
  3347. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_component *component,
  3348. int enable, bool dapm)
  3349. {
  3350. int ret = 0;
  3351. if (!strcmp(component.name, "tasha_codec")) {
  3352. ret = tasha_cdc_mclk_tx_enable(component, enable, dapm);
  3353. } else {
  3354. dev_err(component->dev, "%s: unknown codec to enable TX ext clk\n",
  3355. __func__);
  3356. ret = -EINVAL;
  3357. }
  3358. return ret;
  3359. }
  3360. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3361. struct snd_kcontrol *kcontrol, int event)
  3362. {
  3363. struct snd_soc_component *component =
  3364. snd_soc_dapm_to_component(w->dapm);
  3365. pr_debug("%s: event = %d\n", __func__, event);
  3366. switch (event) {
  3367. case SND_SOC_DAPM_PRE_PMU:
  3368. return msm_snd_enable_codec_ext_tx_clk(component, 1, true);
  3369. case SND_SOC_DAPM_POST_PMD:
  3370. return msm_snd_enable_codec_ext_tx_clk(component, 0, true);
  3371. }
  3372. return 0;
  3373. }
  3374. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3375. struct snd_kcontrol *kcontrol, int event)
  3376. {
  3377. struct snd_soc_component *component =
  3378. snd_soc_dapm_to_component(w->dapm);
  3379. pr_debug("%s: event = %d\n", __func__, event);
  3380. switch (event) {
  3381. case SND_SOC_DAPM_PRE_PMU:
  3382. return msm_snd_enable_codec_ext_clk(component, 1, true);
  3383. case SND_SOC_DAPM_POST_PMD:
  3384. return msm_snd_enable_codec_ext_clk(component, 0, true);
  3385. }
  3386. return 0;
  3387. }
  3388. static int msm_lineout_booster_ctrl_event(struct snd_soc_dapm_widget *w,
  3389. struct snd_kcontrol *k, int event)
  3390. {
  3391. struct snd_soc_component *component =
  3392. snd_soc_dapm_to_component(w->dapm);
  3393. struct snd_soc_card *card = component->card;
  3394. struct msm_asoc_mach_data *pdata =
  3395. snd_soc_card_get_drvdata(card);
  3396. pr_debug("%s: event = %d\n", __func__, event);
  3397. switch (event) {
  3398. case SND_SOC_DAPM_POST_PMU:
  3399. msm_cdc_pinctrl_select_active_state(
  3400. pdata->lineout_booster_gpio_p);
  3401. break;
  3402. case SND_SOC_DAPM_PRE_PMD:
  3403. msm_cdc_pinctrl_select_sleep_state(
  3404. pdata->lineout_booster_gpio_p);
  3405. break;
  3406. }
  3407. return 0;
  3408. }
  3409. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3410. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3411. msm_mclk_event,
  3412. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3413. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3414. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3415. SND_SOC_DAPM_SPK("lineout booster", msm_lineout_booster_ctrl_event),
  3416. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3417. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3418. };
  3419. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3420. struct snd_kcontrol *kcontrol, int event)
  3421. {
  3422. struct msm_asoc_mach_data *pdata = NULL;
  3423. struct snd_soc_component *component =
  3424. snd_soc_dapm_to_component(w->dapm);
  3425. int ret = 0;
  3426. uint32_t dmic_idx;
  3427. int *dmic_gpio_cnt;
  3428. struct device_node *dmic_gpio;
  3429. char *wname;
  3430. wname = strpbrk(w->name, "01234567");
  3431. if (!wname) {
  3432. dev_err(component->dev, "%s: widget not found\n", __func__);
  3433. return -EINVAL;
  3434. }
  3435. ret = kstrtouint(wname, 10, &dmic_idx);
  3436. if (ret < 0) {
  3437. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  3438. __func__);
  3439. return -EINVAL;
  3440. }
  3441. pdata = snd_soc_card_get_drvdata(component->card);
  3442. switch (dmic_idx) {
  3443. case 0:
  3444. case 1:
  3445. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3446. dmic_gpio = pdata->dmic_01_gpio_p;
  3447. break;
  3448. case 2:
  3449. case 3:
  3450. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3451. dmic_gpio = pdata->dmic_23_gpio_p;
  3452. break;
  3453. case 4:
  3454. case 5:
  3455. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3456. dmic_gpio = pdata->dmic_45_gpio_p;
  3457. break;
  3458. case 6:
  3459. case 7:
  3460. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3461. dmic_gpio = pdata->dmic_67_gpio_p;
  3462. break;
  3463. default:
  3464. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  3465. __func__);
  3466. return -EINVAL;
  3467. }
  3468. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3469. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3470. switch (event) {
  3471. case SND_SOC_DAPM_PRE_PMU:
  3472. (*dmic_gpio_cnt)++;
  3473. if (*dmic_gpio_cnt == 1) {
  3474. ret = msm_cdc_pinctrl_select_active_state(
  3475. dmic_gpio);
  3476. if (ret < 0) {
  3477. dev_err(component->dev, "%s: gpio set cannot be activated %sd\n",
  3478. __func__, "dmic_gpio");
  3479. return ret;
  3480. }
  3481. }
  3482. break;
  3483. case SND_SOC_DAPM_POST_PMD:
  3484. (*dmic_gpio_cnt)--;
  3485. if (*dmic_gpio_cnt == 0) {
  3486. ret = msm_cdc_pinctrl_select_sleep_state(
  3487. dmic_gpio);
  3488. if (ret < 0) {
  3489. dev_err(component->dev, "%s: gpio set cannot be de-activated %sd\n",
  3490. __func__, "dmic_gpio");
  3491. return ret;
  3492. }
  3493. }
  3494. break;
  3495. default:
  3496. dev_err(component->dev, "%s: invalid DAPM event %d\n",
  3497. __func__, event);
  3498. return -EINVAL;
  3499. }
  3500. return 0;
  3501. }
  3502. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3503. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3504. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3505. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3506. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3507. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3508. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3509. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3510. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3511. };
  3512. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3513. };
  3514. static inline int param_is_mask(int p)
  3515. {
  3516. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3517. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3518. }
  3519. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3520. int n)
  3521. {
  3522. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3523. }
  3524. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3525. unsigned int bit)
  3526. {
  3527. if (bit >= SNDRV_MASK_MAX)
  3528. return;
  3529. if (param_is_mask(n)) {
  3530. struct snd_mask *m = param_to_mask(p, n);
  3531. m->bits[0] = 0;
  3532. m->bits[1] = 0;
  3533. m->bits[bit >> 5] |= (1 << (bit & 31));
  3534. }
  3535. }
  3536. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3537. {
  3538. int ch_id = 0;
  3539. switch (be_id) {
  3540. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3541. ch_id = SLIM_RX_0;
  3542. break;
  3543. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3544. ch_id = SLIM_RX_1;
  3545. break;
  3546. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3547. ch_id = SLIM_RX_2;
  3548. break;
  3549. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3550. ch_id = SLIM_RX_3;
  3551. break;
  3552. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3553. ch_id = SLIM_RX_4;
  3554. break;
  3555. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3556. ch_id = SLIM_RX_6;
  3557. break;
  3558. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3559. ch_id = SLIM_TX_0;
  3560. break;
  3561. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3562. ch_id = SLIM_TX_3;
  3563. break;
  3564. default:
  3565. ch_id = SLIM_RX_0;
  3566. break;
  3567. }
  3568. return ch_id;
  3569. }
  3570. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3571. {
  3572. *port_id = 0xFFFF;
  3573. switch (be_id) {
  3574. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3575. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3576. break;
  3577. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3578. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3579. break;
  3580. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3581. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3582. break;
  3583. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3584. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3585. break;
  3586. default:
  3587. return -EINVAL;
  3588. }
  3589. return 0;
  3590. }
  3591. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3592. {
  3593. int idx = 0;
  3594. switch (be_id) {
  3595. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3596. idx = WSA_CDC_DMA_RX_0;
  3597. break;
  3598. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3599. idx = WSA_CDC_DMA_TX_0;
  3600. break;
  3601. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3602. idx = WSA_CDC_DMA_RX_1;
  3603. break;
  3604. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3605. idx = WSA_CDC_DMA_TX_1;
  3606. break;
  3607. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3608. idx = WSA_CDC_DMA_TX_2;
  3609. break;
  3610. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3611. idx = VA_CDC_DMA_TX_0;
  3612. break;
  3613. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3614. idx = VA_CDC_DMA_TX_1;
  3615. break;
  3616. default:
  3617. idx = VA_CDC_DMA_TX_0;
  3618. break;
  3619. }
  3620. return idx;
  3621. }
  3622. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3623. struct snd_pcm_hw_params *params)
  3624. {
  3625. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3626. struct snd_interval *rate = hw_param_interval(params,
  3627. SNDRV_PCM_HW_PARAM_RATE);
  3628. struct snd_interval *channels = hw_param_interval(params,
  3629. SNDRV_PCM_HW_PARAM_CHANNELS);
  3630. int rc = 0;
  3631. int idx;
  3632. void *config = NULL;
  3633. struct snd_soc_component *component = NULL;
  3634. pr_debug("%s: format = %d, rate = %d\n",
  3635. __func__, params_format(params), params_rate(params));
  3636. switch (dai_link->id) {
  3637. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3638. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3639. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3640. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3641. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3642. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3643. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3644. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3645. slim_rx_cfg[idx].bit_format);
  3646. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3647. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3648. break;
  3649. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3650. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3651. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3652. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3653. slim_tx_cfg[idx].bit_format);
  3654. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3655. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3656. break;
  3657. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3658. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3659. slim_tx_cfg[1].bit_format);
  3660. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3661. channels->min = channels->max = slim_tx_cfg[1].channels;
  3662. break;
  3663. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3664. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3665. SNDRV_PCM_FORMAT_S32_LE);
  3666. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3667. channels->min = channels->max = msm_vi_feed_tx_ch;
  3668. break;
  3669. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3670. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3671. slim_rx_cfg[5].bit_format);
  3672. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3673. channels->min = channels->max = slim_rx_cfg[5].channels;
  3674. break;
  3675. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3676. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  3677. if (!component) {
  3678. pr_err("%s: component is NULL\n", __func__);
  3679. return -EINVAL;
  3680. }
  3681. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3682. channels->min = channels->max = 1;
  3683. config = msm_codec_fn.get_afe_config_fn(component,
  3684. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3685. if (config) {
  3686. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3687. config, SLIMBUS_5_TX);
  3688. if (rc)
  3689. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3690. __func__, rc);
  3691. }
  3692. break;
  3693. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3694. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3695. slim_rx_cfg[SLIM_RX_7].bit_format);
  3696. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3697. channels->min = channels->max =
  3698. slim_rx_cfg[SLIM_RX_7].channels;
  3699. break;
  3700. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3701. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3702. channels->min = channels->max =
  3703. slim_tx_cfg[SLIM_TX_7].channels;
  3704. break;
  3705. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3706. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3707. channels->min = channels->max =
  3708. slim_tx_cfg[SLIM_TX_8].channels;
  3709. break;
  3710. case MSM_BACKEND_DAI_SLIMBUS_9_TX:
  3711. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3712. slim_tx_cfg[SLIM_TX_9].bit_format);
  3713. rate->min = rate->max = slim_tx_cfg[SLIM_TX_9].sample_rate;
  3714. channels->min = channels->max =
  3715. slim_tx_cfg[SLIM_TX_9].channels;
  3716. break;
  3717. case MSM_BACKEND_DAI_USB_RX:
  3718. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3719. usb_rx_cfg.bit_format);
  3720. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3721. channels->min = channels->max = usb_rx_cfg.channels;
  3722. break;
  3723. case MSM_BACKEND_DAI_USB_TX:
  3724. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3725. usb_tx_cfg.bit_format);
  3726. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3727. channels->min = channels->max = usb_tx_cfg.channels;
  3728. break;
  3729. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3730. channels->min = channels->max = proxy_rx_cfg.channels;
  3731. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3732. break;
  3733. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3734. channels->min = channels->max =
  3735. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3736. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3737. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3738. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3739. break;
  3740. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3741. channels->min = channels->max =
  3742. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3743. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3744. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3745. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3746. break;
  3747. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3748. channels->min = channels->max =
  3749. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3750. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3751. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3752. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3753. break;
  3754. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3755. channels->min = channels->max =
  3756. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3757. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3758. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3759. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3760. break;
  3761. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3762. channels->min = channels->max =
  3763. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3764. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3765. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3766. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3767. break;
  3768. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3769. channels->min = channels->max =
  3770. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3771. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3772. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3773. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3774. break;
  3775. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3776. channels->min = channels->max =
  3777. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3778. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3779. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3780. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3781. break;
  3782. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3783. channels->min = channels->max =
  3784. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3785. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3786. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3787. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3788. break;
  3789. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3790. channels->min = channels->max =
  3791. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3792. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3793. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3794. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3795. break;
  3796. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3797. channels->min = channels->max =
  3798. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3799. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3800. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3801. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3802. break;
  3803. case MSM_BACKEND_DAI_AUXPCM_RX:
  3804. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3805. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3806. rate->min = rate->max =
  3807. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3808. channels->min = channels->max =
  3809. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3810. break;
  3811. case MSM_BACKEND_DAI_AUXPCM_TX:
  3812. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3813. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3814. rate->min = rate->max =
  3815. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3816. channels->min = channels->max =
  3817. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3818. break;
  3819. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3820. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3821. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3822. rate->min = rate->max =
  3823. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3824. channels->min = channels->max =
  3825. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3826. break;
  3827. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3828. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3829. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3830. rate->min = rate->max =
  3831. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3832. channels->min = channels->max =
  3833. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3834. break;
  3835. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3836. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3837. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3838. rate->min = rate->max =
  3839. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3840. channels->min = channels->max =
  3841. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3842. break;
  3843. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3844. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3845. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3846. rate->min = rate->max =
  3847. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3848. channels->min = channels->max =
  3849. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3850. break;
  3851. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3852. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3853. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3854. rate->min = rate->max =
  3855. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3856. channels->min = channels->max =
  3857. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3858. break;
  3859. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3860. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3861. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3862. rate->min = rate->max =
  3863. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3864. channels->min = channels->max =
  3865. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3866. break;
  3867. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3868. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3869. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3870. rate->min = rate->max =
  3871. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3872. channels->min = channels->max =
  3873. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3874. break;
  3875. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3876. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3877. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3878. rate->min = rate->max =
  3879. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3880. channels->min = channels->max =
  3881. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3882. break;
  3883. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3884. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3885. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3886. rate->min = rate->max =
  3887. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3888. channels->min = channels->max =
  3889. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3890. break;
  3891. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3892. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3893. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3894. rate->min = rate->max =
  3895. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3896. channels->min = channels->max =
  3897. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3898. break;
  3899. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3900. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3901. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3902. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3903. channels->min = channels->max =
  3904. mi2s_rx_cfg[PRIM_MI2S].channels;
  3905. break;
  3906. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3907. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3908. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3909. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3910. channels->min = channels->max =
  3911. mi2s_tx_cfg[PRIM_MI2S].channels;
  3912. break;
  3913. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3914. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3915. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3916. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3917. channels->min = channels->max =
  3918. mi2s_rx_cfg[SEC_MI2S].channels;
  3919. break;
  3920. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3921. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3922. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3923. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3924. channels->min = channels->max =
  3925. mi2s_tx_cfg[SEC_MI2S].channels;
  3926. break;
  3927. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3928. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3929. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3930. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3931. channels->min = channels->max =
  3932. mi2s_rx_cfg[TERT_MI2S].channels;
  3933. break;
  3934. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3935. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3936. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3937. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3938. channels->min = channels->max =
  3939. mi2s_tx_cfg[TERT_MI2S].channels;
  3940. break;
  3941. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3942. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3943. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3944. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3945. channels->min = channels->max =
  3946. mi2s_rx_cfg[QUAT_MI2S].channels;
  3947. break;
  3948. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3949. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3950. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3951. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3952. channels->min = channels->max =
  3953. mi2s_tx_cfg[QUAT_MI2S].channels;
  3954. break;
  3955. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3956. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3957. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3958. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3959. channels->min = channels->max =
  3960. mi2s_rx_cfg[QUIN_MI2S].channels;
  3961. break;
  3962. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3963. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3964. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3965. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3966. channels->min = channels->max =
  3967. mi2s_tx_cfg[QUIN_MI2S].channels;
  3968. break;
  3969. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3970. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3971. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3972. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3973. channels->min = channels->max =
  3974. mi2s_rx_cfg[SEN_MI2S].channels;
  3975. break;
  3976. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3977. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3978. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3979. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3980. channels->min = channels->max =
  3981. mi2s_tx_cfg[SEN_MI2S].channels;
  3982. break;
  3983. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3984. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3985. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3986. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3987. cdc_dma_rx_cfg[idx].bit_format);
  3988. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3989. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3990. break;
  3991. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3992. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3993. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3994. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3995. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3996. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3997. cdc_dma_tx_cfg[idx].bit_format);
  3998. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3999. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  4000. break;
  4001. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4002. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4003. SNDRV_PCM_FORMAT_S32_LE);
  4004. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  4005. channels->min = channels->max = msm_vi_feed_tx_ch;
  4006. break;
  4007. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  4008. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4009. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  4010. rate->min = rate->max =
  4011. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  4012. channels->min = channels->max =
  4013. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  4014. break;
  4015. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  4016. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4017. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  4018. rate->min = rate->max =
  4019. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  4020. channels->min = channels->max =
  4021. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  4022. break;
  4023. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  4024. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4025. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  4026. rate->min = rate->max =
  4027. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  4028. channels->min = channels->max =
  4029. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  4030. break;
  4031. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  4032. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4033. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  4034. rate->min = rate->max =
  4035. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  4036. channels->min = channels->max =
  4037. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  4038. break;
  4039. default:
  4040. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4041. break;
  4042. }
  4043. return rc;
  4044. }
  4045. static int msm_afe_set_config(struct snd_soc_component *component)
  4046. {
  4047. int ret = 0;
  4048. void *config_data = NULL;
  4049. if (!msm_codec_fn.get_afe_config_fn) {
  4050. dev_err(component->dev, "%s: codec get afe config not init'ed\n",
  4051. __func__);
  4052. return -EINVAL;
  4053. }
  4054. config_data = msm_codec_fn.get_afe_config_fn(component,
  4055. AFE_CDC_REGISTERS_CONFIG);
  4056. if (config_data) {
  4057. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  4058. if (ret) {
  4059. dev_err(component->dev,
  4060. "%s: Failed to set codec registers config %d\n",
  4061. __func__, ret);
  4062. return ret;
  4063. }
  4064. }
  4065. config_data = msm_codec_fn.get_afe_config_fn(component,
  4066. AFE_CDC_REGISTER_PAGE_CONFIG);
  4067. if (config_data) {
  4068. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  4069. 0);
  4070. if (ret)
  4071. dev_err(component->dev,
  4072. "%s: Failed to set cdc register page config\n",
  4073. __func__);
  4074. }
  4075. config_data = msm_codec_fn.get_afe_config_fn(component,
  4076. AFE_SLIMBUS_SLAVE_CONFIG);
  4077. if (config_data) {
  4078. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  4079. if (ret) {
  4080. dev_err(component->dev,
  4081. "%s: Failed to set slimbus slave config %d\n",
  4082. __func__, ret);
  4083. return ret;
  4084. }
  4085. }
  4086. return 0;
  4087. }
  4088. static void msm_afe_clear_config(void)
  4089. {
  4090. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  4091. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  4092. }
  4093. static int msm_adsp_power_up_config(struct snd_soc_component *component,
  4094. struct snd_card *card)
  4095. {
  4096. int ret = 0;
  4097. unsigned long timeout;
  4098. int adsp_ready = 0;
  4099. bool snd_card_online = 0;
  4100. timeout = jiffies +
  4101. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  4102. do {
  4103. if (!snd_card_online) {
  4104. snd_card_online = snd_card_is_online_state(card);
  4105. pr_debug("%s: Sound card is %s\n", __func__,
  4106. snd_card_online ? "Online" : "Offline");
  4107. }
  4108. if (!adsp_ready) {
  4109. adsp_ready = q6core_is_adsp_ready();
  4110. pr_debug("%s: ADSP Audio is %s\n", __func__,
  4111. adsp_ready ? "ready" : "not ready");
  4112. }
  4113. if (snd_card_online && adsp_ready)
  4114. break;
  4115. /*
  4116. * Sound card/ADSP will be coming up after subsystem restart and
  4117. * it might not be fully up when the control reaches
  4118. * here. So, wait for 50msec before checking ADSP state
  4119. */
  4120. msleep(50);
  4121. } while (time_after(timeout, jiffies));
  4122. if (!snd_card_online || !adsp_ready) {
  4123. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  4124. __func__,
  4125. snd_card_online ? "Online" : "Offline",
  4126. adsp_ready ? "ready" : "not ready");
  4127. ret = -ETIMEDOUT;
  4128. goto err;
  4129. }
  4130. ret = msm_afe_set_config(component);
  4131. if (ret)
  4132. pr_err("%s: Failed to set AFE config. err %d\n",
  4133. __func__, ret);
  4134. return 0;
  4135. err:
  4136. return ret;
  4137. }
  4138. static int qcs405_notifier_service_cb(struct notifier_block *this,
  4139. unsigned long opcode, void *ptr)
  4140. {
  4141. int ret;
  4142. struct snd_soc_card *card = NULL;
  4143. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  4144. struct snd_soc_pcm_runtime *rtd;
  4145. struct snd_soc_dai *codec_dai;
  4146. struct snd_soc_component *component;
  4147. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  4148. switch (opcode) {
  4149. case AUDIO_NOTIFIER_SERVICE_DOWN:
  4150. /*
  4151. * Use flag to ignore initial boot notifications
  4152. * On initial boot msm_adsp_power_up_config is
  4153. * called on init. There is no need to clear
  4154. * and set the config again on initial boot.
  4155. */
  4156. if (is_initial_boot)
  4157. break;
  4158. msm_afe_clear_config();
  4159. break;
  4160. case AUDIO_NOTIFIER_SERVICE_UP:
  4161. if (is_initial_boot) {
  4162. is_initial_boot = false;
  4163. break;
  4164. }
  4165. if (!spdev)
  4166. return -EINVAL;
  4167. card = platform_get_drvdata(spdev);
  4168. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  4169. if (!rtd) {
  4170. dev_err(card->dev,
  4171. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  4172. __func__, be_dl_name);
  4173. ret = -EINVAL;
  4174. goto err;
  4175. }
  4176. codec_dai = rtd->codec_dai;
  4177. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec"))
  4178. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4179. ret = msm_adsp_power_up_config(component, card->snd_card);
  4180. if (ret < 0) {
  4181. dev_err(card->dev,
  4182. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  4183. __func__, ret);
  4184. goto err;
  4185. }
  4186. break;
  4187. default:
  4188. break;
  4189. }
  4190. err:
  4191. return NOTIFY_OK;
  4192. }
  4193. static struct notifier_block service_nb = {
  4194. .notifier_call = qcs405_notifier_service_cb,
  4195. .priority = -INT_MAX,
  4196. };
  4197. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4198. {
  4199. int ret = 0;
  4200. void *config_data;
  4201. struct snd_soc_component *component;
  4202. struct snd_soc_dapm_context *dapm;
  4203. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4204. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4205. struct snd_card *card;
  4206. struct msm_asoc_mach_data *pdata =
  4207. snd_soc_card_get_drvdata(rtd->card);
  4208. /*
  4209. * Codec SLIMBUS configuration
  4210. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4211. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4212. * TX14, TX15, TX16
  4213. */
  4214. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4215. 151, 152, 153, 154, 155, 156};
  4216. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4217. 134, 135, 136, 137, 138, 139,
  4218. 140, 141, 142, 143};
  4219. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4220. rtd->pmdown_time = 0;
  4221. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) {
  4222. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4223. dapm = snd_soc_component_get_dapm(component);
  4224. }
  4225. ret = snd_soc_add_component_controls(component, msm_snd_sb_controls,
  4226. ARRAY_SIZE(msm_snd_sb_controls));
  4227. if (ret < 0) {
  4228. pr_err("%s: add_codec_controls failed, err %d\n",
  4229. __func__, ret);
  4230. return ret;
  4231. }
  4232. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4233. ARRAY_SIZE(msm_dapm_widgets));
  4234. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4235. ARRAY_SIZE(wcd_audio_paths));
  4236. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4237. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4238. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4239. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4240. snd_soc_dapm_sync(dapm);
  4241. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4242. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4243. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4244. ret = msm_adsp_power_up_config(component, rtd->card->snd_card);
  4245. if (ret) {
  4246. dev_err(component->dev, "%s: Failed to set AFE config %d\n",
  4247. __func__, ret);
  4248. goto err;
  4249. }
  4250. config_data = msm_codec_fn.get_afe_config_fn(component,
  4251. AFE_AANC_VERSION);
  4252. if (config_data) {
  4253. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4254. if (ret) {
  4255. dev_err(component->dev, "%s: Failed to set aanc version %d\n",
  4256. __func__, ret);
  4257. goto err;
  4258. }
  4259. }
  4260. card = rtd->card->snd_card;
  4261. if (!pdata->codec_root)
  4262. pdata->codec_root = snd_info_create_subdir(card->module,
  4263. "codecs", card->proc_root);
  4264. if (!pdata->codec_root) {
  4265. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4266. __func__);
  4267. ret = 0;
  4268. goto err;
  4269. }
  4270. tasha_codec_info_create_codec_entry(pdata->codec_root, component);
  4271. codec_reg_done = true;
  4272. return 0;
  4273. err:
  4274. return ret;
  4275. }
  4276. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4277. {
  4278. int ret = 0;
  4279. struct snd_soc_component *component;
  4280. struct snd_soc_dapm_context *dapm;
  4281. struct snd_card *card;
  4282. struct msm_asoc_mach_data *pdata =
  4283. snd_soc_card_get_drvdata(rtd->card);
  4284. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4285. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4286. if (!component) {
  4287. pr_err("%s: component is NULL\n", __func__);
  4288. return -EINVAL;
  4289. }
  4290. dapm = snd_soc_component_get_dapm(component);
  4291. ret = snd_soc_add_component_controls(component, msm_snd_va_controls,
  4292. ARRAY_SIZE(msm_snd_va_controls));
  4293. if (ret < 0) {
  4294. dev_err(component->dev, "%s: add_component_controls for va failed, err %d\n",
  4295. __func__, ret);
  4296. return ret;
  4297. }
  4298. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4299. ARRAY_SIZE(msm_va_dapm_widgets));
  4300. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4301. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4302. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4303. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4304. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4305. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4306. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4307. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4308. snd_soc_dapm_sync(dapm);
  4309. card = rtd->card->snd_card;
  4310. if (!pdata->codec_root)
  4311. pdata->codec_root = snd_info_create_subdir(card->module,
  4312. "codecs", card->proc_root);
  4313. if (!pdata->codec_root) {
  4314. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4315. __func__);
  4316. ret = 0;
  4317. goto done;
  4318. }
  4319. bolero_info_create_codec_entry(pdata->codec_root, component);
  4320. done:
  4321. return ret;
  4322. }
  4323. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4324. {
  4325. int ret = 0;
  4326. struct snd_soc_component *component = NULL;
  4327. struct snd_soc_dapm_context *dapm = NULL;
  4328. struct snd_soc_component *aux_comp = NULL;
  4329. struct snd_card *card = NULL;
  4330. struct msm_asoc_mach_data *pdata =
  4331. snd_soc_card_get_drvdata(rtd->card);
  4332. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4333. if (!component) {
  4334. pr_err("%s: component is NULL\n", __func__);
  4335. return -EINVAL;
  4336. }
  4337. dapm = snd_soc_component_get_dapm(component);
  4338. ret = snd_soc_add_component_controls(component, msm_snd_wsa_controls,
  4339. ARRAY_SIZE(msm_snd_wsa_controls));
  4340. if (ret < 0) {
  4341. dev_err(component->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4342. __func__, ret);
  4343. return ret;
  4344. }
  4345. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4346. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4347. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4348. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4349. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4350. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4351. snd_soc_dapm_sync(dapm);
  4352. /*
  4353. * Send speaker configuration only for WSA8810.
  4354. * Default configuration is for WSA8815.
  4355. */
  4356. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4357. __func__, rtd->card->num_aux_devs);
  4358. if (rtd->card->num_aux_devs &&
  4359. !list_empty(&rtd->card->component_dev_list)) {
  4360. aux_comp = list_first_entry(
  4361. &rtd->card->component_dev_list,
  4362. struct snd_soc_component,
  4363. card_aux_list);
  4364. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4365. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4366. wsa_macro_set_spkr_mode(component,
  4367. WSA_MACRO_SPKR_MODE_1);
  4368. wsa_macro_set_spkr_gain_offset(component,
  4369. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4370. }
  4371. }
  4372. card = rtd->card->snd_card;
  4373. if (!pdata->codec_root)
  4374. pdata->codec_root = snd_info_create_subdir(card->module,
  4375. "codecs", card->proc_root);
  4376. if (!pdata->codec_root) {
  4377. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  4378. __func__);
  4379. ret = 0;
  4380. goto done;
  4381. }
  4382. bolero_info_create_codec_entry(pdata->codec_root, component);
  4383. done:
  4384. return ret;
  4385. }
  4386. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4387. {
  4388. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4389. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161, 162};
  4390. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4391. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4392. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4393. }
  4394. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4395. struct snd_pcm_hw_params *params)
  4396. {
  4397. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4398. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4399. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4400. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4401. int ret = 0;
  4402. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4403. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4404. u32 user_set_tx_ch = 0;
  4405. u32 rx_ch_count;
  4406. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4407. ret = snd_soc_dai_get_channel_map(codec_dai,
  4408. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4409. if (ret < 0) {
  4410. pr_err("%s: failed to get codec chan map, err:%d\n",
  4411. __func__, ret);
  4412. goto err;
  4413. }
  4414. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4415. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4416. slim_rx_cfg[5].channels);
  4417. rx_ch_count = slim_rx_cfg[5].channels;
  4418. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4419. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4420. slim_rx_cfg[2].channels);
  4421. rx_ch_count = slim_rx_cfg[2].channels;
  4422. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4423. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4424. slim_rx_cfg[6].channels);
  4425. rx_ch_count = slim_rx_cfg[6].channels;
  4426. } else {
  4427. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4428. slim_rx_cfg[0].channels);
  4429. rx_ch_count = slim_rx_cfg[0].channels;
  4430. }
  4431. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4432. rx_ch_count, rx_ch);
  4433. if (ret < 0) {
  4434. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4435. __func__, ret);
  4436. goto err;
  4437. }
  4438. } else {
  4439. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4440. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4441. ret = snd_soc_dai_get_channel_map(codec_dai,
  4442. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4443. if (ret < 0) {
  4444. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4445. __func__, ret);
  4446. goto err;
  4447. }
  4448. /* For <codec>_tx1 case */
  4449. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4450. user_set_tx_ch = slim_tx_cfg[0].channels;
  4451. /* For <codec>_tx3 case */
  4452. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4453. user_set_tx_ch = slim_tx_cfg[1].channels;
  4454. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4455. user_set_tx_ch = msm_vi_feed_tx_ch;
  4456. else
  4457. user_set_tx_ch = tx_ch_cnt;
  4458. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4459. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4460. tx_ch_cnt, dai_link->id);
  4461. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4462. user_set_tx_ch, tx_ch, 0, 0);
  4463. if (ret < 0)
  4464. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4465. __func__, ret);
  4466. }
  4467. err:
  4468. return ret;
  4469. }
  4470. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4471. struct snd_pcm_hw_params *params)
  4472. {
  4473. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4474. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4475. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4476. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4477. int ret = 0;
  4478. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4479. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4480. u32 user_set_tx_ch = 0;
  4481. u32 user_set_rx_ch = 0;
  4482. u32 ch_id;
  4483. ret = snd_soc_dai_get_channel_map(codec_dai,
  4484. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4485. &rx_ch_cdc_dma);
  4486. if (ret < 0) {
  4487. pr_err("%s: failed to get codec chan map, err:%d\n",
  4488. __func__, ret);
  4489. goto err;
  4490. }
  4491. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4492. switch (dai_link->id) {
  4493. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4494. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4495. {
  4496. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4497. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4498. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4499. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4500. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4501. user_set_rx_ch, &rx_ch_cdc_dma);
  4502. if (ret < 0) {
  4503. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4504. __func__, ret);
  4505. goto err;
  4506. }
  4507. }
  4508. break;
  4509. }
  4510. } else {
  4511. switch (dai_link->id) {
  4512. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4513. {
  4514. user_set_tx_ch = msm_vi_feed_tx_ch;
  4515. }
  4516. break;
  4517. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4518. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4519. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4520. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4521. {
  4522. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4523. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4524. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4525. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4526. }
  4527. break;
  4528. }
  4529. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4530. &tx_ch_cdc_dma, 0, 0);
  4531. if (ret < 0) {
  4532. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4533. __func__, ret);
  4534. goto err;
  4535. }
  4536. }
  4537. err:
  4538. return ret;
  4539. }
  4540. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4541. struct snd_pcm_hw_params *params)
  4542. {
  4543. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4544. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4545. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4546. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4547. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4548. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4549. int ret;
  4550. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4551. codec_dai->name, codec_dai->id);
  4552. ret = snd_soc_dai_get_channel_map(codec_dai,
  4553. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4554. if (ret) {
  4555. dev_err(rtd->dev,
  4556. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4557. __func__, ret);
  4558. goto err;
  4559. }
  4560. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4561. __func__, tx_ch_cnt, dai_link->id);
  4562. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4563. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4564. if (ret)
  4565. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4566. __func__, ret);
  4567. err:
  4568. return ret;
  4569. }
  4570. static int msm_get_port_id(int be_id)
  4571. {
  4572. int afe_port_id;
  4573. switch (be_id) {
  4574. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4575. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4576. break;
  4577. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4578. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4579. break;
  4580. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4581. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4582. break;
  4583. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4584. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4585. break;
  4586. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4587. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4588. break;
  4589. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4590. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4591. break;
  4592. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4593. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4594. break;
  4595. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4596. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4597. break;
  4598. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4599. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4600. break;
  4601. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4602. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4603. break;
  4604. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4605. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  4606. break;
  4607. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4608. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  4609. break;
  4610. default:
  4611. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4612. afe_port_id = -EINVAL;
  4613. }
  4614. return afe_port_id;
  4615. }
  4616. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4617. {
  4618. u32 bit_per_sample;
  4619. switch (bit_format) {
  4620. case SNDRV_PCM_FORMAT_S32_LE:
  4621. case SNDRV_PCM_FORMAT_S24_3LE:
  4622. case SNDRV_PCM_FORMAT_S24_LE:
  4623. bit_per_sample = 32;
  4624. break;
  4625. case SNDRV_PCM_FORMAT_S16_LE:
  4626. default:
  4627. bit_per_sample = 16;
  4628. break;
  4629. }
  4630. return bit_per_sample;
  4631. }
  4632. static void update_mi2s_clk_val(int dai_id, int stream)
  4633. {
  4634. u32 bit_per_sample;
  4635. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4636. bit_per_sample =
  4637. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4638. mi2s_clk[dai_id].clk_freq_in_hz =
  4639. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4640. } else {
  4641. bit_per_sample =
  4642. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4643. mi2s_clk[dai_id].clk_freq_in_hz =
  4644. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4645. }
  4646. }
  4647. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4648. {
  4649. int ret = 0;
  4650. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4651. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4652. int port_id = 0;
  4653. int index = cpu_dai->id;
  4654. port_id = msm_get_port_id(rtd->dai_link->id);
  4655. if (port_id < 0) {
  4656. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4657. ret = port_id;
  4658. goto err;
  4659. }
  4660. if (enable) {
  4661. update_mi2s_clk_val(index, substream->stream);
  4662. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4663. mi2s_clk[index].clk_freq_in_hz);
  4664. }
  4665. mi2s_clk[index].enable = enable;
  4666. ret = afe_set_lpass_clock_v2(port_id,
  4667. &mi2s_clk[index]);
  4668. if (ret < 0) {
  4669. dev_err(rtd->card->dev,
  4670. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4671. __func__, port_id, ret);
  4672. goto err;
  4673. }
  4674. err:
  4675. return ret;
  4676. }
  4677. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4678. struct snd_pcm_hw_params *params)
  4679. {
  4680. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4681. struct snd_interval *rate = hw_param_interval(params,
  4682. SNDRV_PCM_HW_PARAM_RATE);
  4683. struct snd_interval *channels = hw_param_interval(params,
  4684. SNDRV_PCM_HW_PARAM_CHANNELS);
  4685. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4686. channels->min = channels->max =
  4687. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4688. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4689. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4690. rate->min = rate->max =
  4691. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4692. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4693. channels->min = channels->max =
  4694. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4695. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4696. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4697. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4698. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4699. channels->min = channels->max =
  4700. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4701. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4702. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4703. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4704. } else {
  4705. pr_err("%s: dai id 0x%x not supported\n",
  4706. __func__, cpu_dai->id);
  4707. return -EINVAL;
  4708. }
  4709. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4710. __func__, cpu_dai->id, channels->max, rate->max,
  4711. params_format(params));
  4712. return 0;
  4713. }
  4714. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4715. struct snd_pcm_hw_params *params)
  4716. {
  4717. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4718. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4719. int ret = 0;
  4720. int slot_width = 32;
  4721. int channels, slots = 8;
  4722. unsigned int slot_mask, rate, clk_freq;
  4723. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4724. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4725. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4726. switch (cpu_dai->id) {
  4727. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4728. channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4729. break;
  4730. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4731. channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4732. break;
  4733. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4734. channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4735. break;
  4736. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4737. channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4738. break;
  4739. case AFE_PORT_ID_QUINARY_TDM_RX:
  4740. channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4741. break;
  4742. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4743. channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4744. break;
  4745. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4746. channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4747. break;
  4748. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4749. channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4750. break;
  4751. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4752. channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4753. break;
  4754. case AFE_PORT_ID_QUINARY_TDM_TX:
  4755. channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4756. break;
  4757. default:
  4758. pr_err("%s: dai id 0x%x not supported\n",
  4759. __func__, cpu_dai->id);
  4760. return -EINVAL;
  4761. }
  4762. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4763. /*2 slot config - bits 0 and 1 set for the first two slots */
  4764. slot_mask = 0x0000FFFF >> (16-channels);
  4765. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4766. __func__, slot_width, slots);
  4767. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4768. slots, slot_width);
  4769. if (ret < 0) {
  4770. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4771. __func__, ret);
  4772. goto end;
  4773. }
  4774. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4775. 0, NULL, channels, slot_offset);
  4776. if (ret < 0) {
  4777. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4778. __func__, ret);
  4779. goto end;
  4780. }
  4781. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4782. /*2 slot config - bits 0 and 1 set for the first two slots */
  4783. slot_mask = 0x0000FFFF >> (16-channels);
  4784. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4785. __func__, slot_width, slots);
  4786. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4787. slots, slot_width);
  4788. if (ret < 0) {
  4789. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4790. __func__, ret);
  4791. goto end;
  4792. }
  4793. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4794. channels, slot_offset, 0, NULL);
  4795. if (ret < 0) {
  4796. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4797. __func__, ret);
  4798. goto end;
  4799. }
  4800. } else {
  4801. ret = -EINVAL;
  4802. pr_err("%s: invalid use case, err:%d\n",
  4803. __func__, ret);
  4804. goto end;
  4805. }
  4806. rate = params_rate(params);
  4807. clk_freq = rate * slot_width * slots;
  4808. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4809. if (ret < 0)
  4810. pr_err("%s: failed to set tdm clk, err:%d\n",
  4811. __func__, ret);
  4812. end:
  4813. return ret;
  4814. }
  4815. static int msm_get_tdm_mode(u32 port_id)
  4816. {
  4817. u32 tdm_mode;
  4818. switch (port_id) {
  4819. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4820. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4821. tdm_mode = TDM_PRI;
  4822. break;
  4823. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4824. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4825. tdm_mode = TDM_SEC;
  4826. break;
  4827. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4828. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4829. tdm_mode = TDM_TERT;
  4830. break;
  4831. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4832. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4833. tdm_mode = TDM_QUAT;
  4834. break;
  4835. case AFE_PORT_ID_QUINARY_TDM_RX:
  4836. case AFE_PORT_ID_QUINARY_TDM_TX:
  4837. tdm_mode = TDM_QUIN;
  4838. break;
  4839. default:
  4840. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  4841. tdm_mode = -EINVAL;
  4842. }
  4843. return tdm_mode;
  4844. }
  4845. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4846. {
  4847. int ret = 0;
  4848. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4849. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4850. struct snd_soc_card *card = rtd->card;
  4851. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4852. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4853. if (tdm_mode >= TDM_INTERFACE_MAX) {
  4854. ret = -EINVAL;
  4855. pr_err("%s: Invalid TDM interface %d\n",
  4856. __func__, ret);
  4857. return ret;
  4858. }
  4859. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4860. ret = msm_cdc_pinctrl_select_active_state(
  4861. pdata->mi2s_gpio_p[tdm_mode]);
  4862. if (ret)
  4863. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  4864. __func__, ret);
  4865. }
  4866. /* Enable Mic bias for TDM Mics */
  4867. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4868. if (pdata->tdm_micb_supply) {
  4869. ret = regulator_set_voltage(pdata->tdm_micb_supply,
  4870. pdata->tdm_micb_voltage,
  4871. pdata->tdm_micb_voltage);
  4872. if (ret) {
  4873. pr_err("%s: Setting voltage failed, err = %d\n",
  4874. __func__, ret);
  4875. return ret;
  4876. }
  4877. ret = regulator_set_load(pdata->tdm_micb_supply,
  4878. pdata->tdm_micb_current);
  4879. if (ret) {
  4880. pr_err("%s: Setting current failed, err = %d\n",
  4881. __func__, ret);
  4882. return ret;
  4883. }
  4884. ret = regulator_enable(pdata->tdm_micb_supply);
  4885. if (ret) {
  4886. pr_err("%s: regulator enable failed, err = %d\n",
  4887. __func__, ret);
  4888. return ret;
  4889. }
  4890. }
  4891. }
  4892. return ret;
  4893. }
  4894. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4895. {
  4896. int ret = 0;
  4897. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4898. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4899. struct snd_soc_card *card = rtd->card;
  4900. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4901. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4902. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4903. if (pdata->tdm_micb_supply) {
  4904. ret = regulator_disable(pdata->tdm_micb_supply);
  4905. if (ret)
  4906. pr_err("%s: regulator disable failed, err = %d\n",
  4907. __func__, ret);
  4908. regulator_set_voltage(pdata->tdm_micb_supply, 0,
  4909. pdata->tdm_micb_voltage);
  4910. regulator_set_load(pdata->tdm_micb_supply, 0);
  4911. }
  4912. }
  4913. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4914. ret = msm_cdc_pinctrl_select_sleep_state(
  4915. pdata->mi2s_gpio_p[tdm_mode]);
  4916. if (ret)
  4917. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  4918. __func__, ret);
  4919. }
  4920. }
  4921. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4922. .hw_params = qcs405_tdm_snd_hw_params,
  4923. .startup = qcs405_tdm_snd_startup,
  4924. .shutdown = qcs405_tdm_snd_shutdown
  4925. };
  4926. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4927. {
  4928. cpumask_t mask;
  4929. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4930. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4931. cpumask_clear(&mask);
  4932. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4933. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4934. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4935. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4936. pm_qos_add_request(&substream->latency_pm_qos_req,
  4937. PM_QOS_CPU_DMA_LATENCY,
  4938. MSM_LL_QOS_VALUE);
  4939. return 0;
  4940. }
  4941. static struct snd_soc_ops msm_fe_qos_ops = {
  4942. .prepare = msm_fe_qos_prepare,
  4943. };
  4944. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4945. {
  4946. int ret = 0;
  4947. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4948. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4949. int index = cpu_dai->id;
  4950. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4951. struct snd_soc_card *card = rtd->card;
  4952. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4953. dev_dbg(rtd->card->dev,
  4954. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4955. __func__, substream->name, substream->stream,
  4956. cpu_dai->name, cpu_dai->id);
  4957. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4958. ret = -EINVAL;
  4959. dev_err(rtd->card->dev,
  4960. "%s: CPU DAI id (%d) out of range\n",
  4961. __func__, cpu_dai->id);
  4962. goto err;
  4963. }
  4964. /*
  4965. * Mutex protection in case the same MI2S
  4966. * interface using for both TX and RX so
  4967. * that the same clock won't be enable twice.
  4968. */
  4969. mutex_lock(&mi2s_intf_conf[index].lock);
  4970. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4971. /* Check if msm needs to provide the clock to the interface */
  4972. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4973. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4974. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4975. }
  4976. ret = msm_mi2s_set_sclk(substream, true);
  4977. if (ret < 0) {
  4978. dev_err(rtd->card->dev,
  4979. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4980. __func__, ret);
  4981. goto clean_up;
  4982. }
  4983. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4984. if (ret < 0) {
  4985. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4986. __func__, index, ret);
  4987. goto clk_off;
  4988. }
  4989. if (pdata->mi2s_gpio_p[index])
  4990. msm_cdc_pinctrl_select_active_state(
  4991. pdata->mi2s_gpio_p[index]);
  4992. }
  4993. clk_off:
  4994. if (ret < 0)
  4995. msm_mi2s_set_sclk(substream, false);
  4996. clean_up:
  4997. if (ret < 0)
  4998. mi2s_intf_conf[index].ref_cnt--;
  4999. mutex_unlock(&mi2s_intf_conf[index].lock);
  5000. err:
  5001. return ret;
  5002. }
  5003. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  5004. {
  5005. int ret;
  5006. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5007. int index = rtd->cpu_dai->id;
  5008. struct snd_soc_card *card = rtd->card;
  5009. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5010. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5011. substream->name, substream->stream);
  5012. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5013. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  5014. return;
  5015. }
  5016. mutex_lock(&mi2s_intf_conf[index].lock);
  5017. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  5018. if (pdata->mi2s_gpio_p[index])
  5019. msm_cdc_pinctrl_select_sleep_state(
  5020. pdata->mi2s_gpio_p[index]);
  5021. ret = msm_mi2s_set_sclk(substream, false);
  5022. if (ret < 0)
  5023. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  5024. __func__, index, ret);
  5025. }
  5026. mutex_unlock(&mi2s_intf_conf[index].lock);
  5027. }
  5028. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  5029. {
  5030. int ret = 0;
  5031. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5032. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5033. int port_id = cpu_dai->id;
  5034. struct afe_clk_set clk_cfg;
  5035. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  5036. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  5037. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  5038. clk_cfg.enable = enable;
  5039. /* Set core clock (based on sample rate for RX, fixed for TX) */
  5040. switch (port_id) {
  5041. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5042. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  5043. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  5044. clk_cfg.clk_freq_in_hz =
  5045. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5046. break;
  5047. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5048. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  5049. clk_cfg.clk_freq_in_hz =
  5050. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5051. break;
  5052. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  5053. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  5054. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5055. break;
  5056. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  5057. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  5058. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5059. break;
  5060. }
  5061. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5062. if (ret < 0) {
  5063. dev_err(rtd->card->dev,
  5064. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5065. __func__, port_id, ret);
  5066. goto err;
  5067. }
  5068. /* Set NPL clock for RX in addition */
  5069. switch (port_id) {
  5070. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5071. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  5072. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5073. if (ret < 0) {
  5074. dev_err(rtd->card->dev,
  5075. "%s: afe NPL failed port 0x%x, err:%d\n",
  5076. __func__, port_id, ret);
  5077. goto err;
  5078. }
  5079. break;
  5080. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5081. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  5082. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5083. if (ret < 0) {
  5084. dev_err(rtd->card->dev,
  5085. "%s: afe NPL failed for port 0x%x, err:%d\n",
  5086. __func__, port_id, ret);
  5087. goto err;
  5088. }
  5089. break;
  5090. }
  5091. if (enable) {
  5092. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5093. clk_cfg.clk_freq_in_hz);
  5094. }
  5095. err:
  5096. return ret;
  5097. }
  5098. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  5099. {
  5100. int ret = 0;
  5101. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5102. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5103. int port_id = cpu_dai->id;
  5104. dev_dbg(rtd->card->dev,
  5105. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5106. __func__, substream->name, substream->stream,
  5107. cpu_dai->name, cpu_dai->id);
  5108. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5109. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5110. ret = -EINVAL;
  5111. dev_err(rtd->card->dev,
  5112. "%s: CPU DAI id (%d) out of range\n",
  5113. __func__, cpu_dai->id);
  5114. goto err;
  5115. }
  5116. ret = msm_spdif_set_clk(substream, true);
  5117. if (ret < 0) {
  5118. dev_err(rtd->card->dev,
  5119. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  5120. __func__, port_id, ret);
  5121. }
  5122. err:
  5123. return ret;
  5124. }
  5125. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  5126. {
  5127. int ret;
  5128. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5129. int port_id = rtd->cpu_dai->id;
  5130. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5131. substream->name, substream->stream);
  5132. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5133. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5134. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  5135. return;
  5136. }
  5137. ret = msm_spdif_set_clk(substream, false);
  5138. if (ret < 0)
  5139. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  5140. __func__, port_id, ret);
  5141. }
  5142. static struct snd_soc_ops msm_mi2s_be_ops = {
  5143. .startup = msm_mi2s_snd_startup,
  5144. .shutdown = msm_mi2s_snd_shutdown,
  5145. };
  5146. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5147. .hw_params = msm_snd_cdc_dma_hw_params,
  5148. };
  5149. static struct snd_soc_ops msm_be_ops = {
  5150. .hw_params = msm_snd_hw_params,
  5151. };
  5152. static struct snd_soc_ops msm_wcn_ops = {
  5153. .hw_params = msm_wcn_hw_params,
  5154. };
  5155. static struct snd_soc_ops msm_spdif_be_ops = {
  5156. .startup = msm_spdif_snd_startup,
  5157. .shutdown = msm_spdif_snd_shutdown,
  5158. };
  5159. /* Digital audio interface glue - connects codec <---> CPU */
  5160. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5161. /* FrontEnd DAI Links */
  5162. {
  5163. .name = MSM_DAILINK_NAME(Media1),
  5164. .stream_name = "MultiMedia1",
  5165. .cpu_dai_name = "MultiMedia1",
  5166. .platform_name = "msm-pcm-dsp.0",
  5167. .dynamic = 1,
  5168. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5169. .dpcm_playback = 1,
  5170. .dpcm_capture = 1,
  5171. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5172. SND_SOC_DPCM_TRIGGER_POST},
  5173. .codec_dai_name = "snd-soc-dummy-dai",
  5174. .codec_name = "snd-soc-dummy",
  5175. .ignore_suspend = 1,
  5176. /* this dainlink has playback support */
  5177. .ignore_pmdown_time = 1,
  5178. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5179. },
  5180. {
  5181. .name = MSM_DAILINK_NAME(Media2),
  5182. .stream_name = "MultiMedia2",
  5183. .cpu_dai_name = "MultiMedia2",
  5184. .platform_name = "msm-pcm-dsp.0",
  5185. .dynamic = 1,
  5186. .dpcm_playback = 1,
  5187. .dpcm_capture = 1,
  5188. .codec_dai_name = "snd-soc-dummy-dai",
  5189. .codec_name = "snd-soc-dummy",
  5190. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5191. SND_SOC_DPCM_TRIGGER_POST},
  5192. .ignore_suspend = 1,
  5193. /* this dainlink has playback support */
  5194. .ignore_pmdown_time = 1,
  5195. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5196. },
  5197. {
  5198. .name = "VoiceMMode1",
  5199. .stream_name = "VoiceMMode1",
  5200. .cpu_dai_name = "VoiceMMode1",
  5201. .platform_name = "msm-pcm-voice",
  5202. .dynamic = 1,
  5203. .dpcm_playback = 1,
  5204. .dpcm_capture = 1,
  5205. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5206. SND_SOC_DPCM_TRIGGER_POST},
  5207. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5208. .ignore_suspend = 1,
  5209. .ignore_pmdown_time = 1,
  5210. .codec_dai_name = "snd-soc-dummy-dai",
  5211. .codec_name = "snd-soc-dummy",
  5212. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5213. },
  5214. {
  5215. .name = "MSM VoIP",
  5216. .stream_name = "VoIP",
  5217. .cpu_dai_name = "VoIP",
  5218. .platform_name = "msm-voip-dsp",
  5219. .dynamic = 1,
  5220. .dpcm_playback = 1,
  5221. .dpcm_capture = 1,
  5222. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5223. SND_SOC_DPCM_TRIGGER_POST},
  5224. .codec_dai_name = "snd-soc-dummy-dai",
  5225. .codec_name = "snd-soc-dummy",
  5226. .ignore_suspend = 1,
  5227. /* this dainlink has playback support */
  5228. .ignore_pmdown_time = 1,
  5229. .id = MSM_FRONTEND_DAI_VOIP,
  5230. },
  5231. {
  5232. .name = MSM_DAILINK_NAME(ULL),
  5233. .stream_name = "MultiMedia3",
  5234. .cpu_dai_name = "MultiMedia3",
  5235. .platform_name = "msm-pcm-dsp.2",
  5236. .dynamic = 1,
  5237. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5238. .dpcm_playback = 1,
  5239. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5240. SND_SOC_DPCM_TRIGGER_POST},
  5241. .codec_dai_name = "snd-soc-dummy-dai",
  5242. .codec_name = "snd-soc-dummy",
  5243. .ignore_suspend = 1,
  5244. /* this dainlink has playback support */
  5245. .ignore_pmdown_time = 1,
  5246. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5247. },
  5248. /* Hostless PCM purpose */
  5249. {
  5250. .name = "SLIMBUS_0 Hostless",
  5251. .stream_name = "SLIMBUS_0 Hostless",
  5252. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5253. .platform_name = "msm-pcm-hostless",
  5254. .dynamic = 1,
  5255. .dpcm_playback = 1,
  5256. .dpcm_capture = 1,
  5257. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5258. SND_SOC_DPCM_TRIGGER_POST},
  5259. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5260. .ignore_suspend = 1,
  5261. /* this dailink has playback support */
  5262. .ignore_pmdown_time = 1,
  5263. .codec_dai_name = "snd-soc-dummy-dai",
  5264. .codec_name = "snd-soc-dummy",
  5265. },
  5266. {
  5267. .name = "MSM AFE-PCM RX",
  5268. .stream_name = "AFE-PROXY RX",
  5269. .cpu_dai_name = "msm-dai-q6-dev.241",
  5270. .codec_name = "msm-stub-codec.1",
  5271. .codec_dai_name = "msm-stub-rx",
  5272. .platform_name = "msm-pcm-afe",
  5273. .dpcm_playback = 1,
  5274. .ignore_suspend = 1,
  5275. /* this dainlink has playback support */
  5276. .ignore_pmdown_time = 1,
  5277. },
  5278. {
  5279. .name = "MSM AFE-PCM TX",
  5280. .stream_name = "AFE-PROXY TX",
  5281. .cpu_dai_name = "msm-dai-q6-dev.240",
  5282. .codec_name = "msm-stub-codec.1",
  5283. .codec_dai_name = "msm-stub-tx",
  5284. .platform_name = "msm-pcm-afe",
  5285. .dpcm_capture = 1,
  5286. .ignore_suspend = 1,
  5287. },
  5288. {
  5289. .name = MSM_DAILINK_NAME(Compress1),
  5290. .stream_name = "Compress1",
  5291. .cpu_dai_name = "MultiMedia4",
  5292. .platform_name = "msm-compress-dsp",
  5293. .dynamic = 1,
  5294. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5295. .dpcm_playback = 1,
  5296. .dpcm_capture = 1,
  5297. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5298. SND_SOC_DPCM_TRIGGER_POST},
  5299. .codec_dai_name = "snd-soc-dummy-dai",
  5300. .codec_name = "snd-soc-dummy",
  5301. .ignore_suspend = 1,
  5302. .ignore_pmdown_time = 1,
  5303. /* this dainlink has playback support */
  5304. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5305. },
  5306. {
  5307. .name = "AUXPCM Hostless",
  5308. .stream_name = "AUXPCM Hostless",
  5309. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5310. .platform_name = "msm-pcm-hostless",
  5311. .dynamic = 1,
  5312. .dpcm_playback = 1,
  5313. .dpcm_capture = 1,
  5314. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5315. SND_SOC_DPCM_TRIGGER_POST},
  5316. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5317. .ignore_suspend = 1,
  5318. /* this dainlink has playback support */
  5319. .ignore_pmdown_time = 1,
  5320. .codec_dai_name = "snd-soc-dummy-dai",
  5321. .codec_name = "snd-soc-dummy",
  5322. },
  5323. {
  5324. .name = "SLIMBUS_1 Hostless",
  5325. .stream_name = "SLIMBUS_1 Hostless",
  5326. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5327. .platform_name = "msm-pcm-hostless",
  5328. .dynamic = 1,
  5329. .dpcm_playback = 1,
  5330. .dpcm_capture = 1,
  5331. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5332. SND_SOC_DPCM_TRIGGER_POST},
  5333. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5334. .ignore_suspend = 1,
  5335. /* this dailink has playback support */
  5336. .ignore_pmdown_time = 1,
  5337. .codec_dai_name = "snd-soc-dummy-dai",
  5338. .codec_name = "snd-soc-dummy",
  5339. },
  5340. {
  5341. .name = "SLIMBUS_3 Hostless",
  5342. .stream_name = "SLIMBUS_3 Hostless",
  5343. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5344. .platform_name = "msm-pcm-hostless",
  5345. .dynamic = 1,
  5346. .dpcm_playback = 1,
  5347. .dpcm_capture = 1,
  5348. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5349. SND_SOC_DPCM_TRIGGER_POST},
  5350. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5351. .ignore_suspend = 1,
  5352. /* this dailink has playback support */
  5353. .ignore_pmdown_time = 1,
  5354. .codec_dai_name = "snd-soc-dummy-dai",
  5355. .codec_name = "snd-soc-dummy",
  5356. },
  5357. {
  5358. .name = "SLIMBUS_4 Hostless",
  5359. .stream_name = "SLIMBUS_4 Hostless",
  5360. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5361. .platform_name = "msm-pcm-hostless",
  5362. .dynamic = 1,
  5363. .dpcm_playback = 1,
  5364. .dpcm_capture = 1,
  5365. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5366. SND_SOC_DPCM_TRIGGER_POST},
  5367. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5368. .ignore_suspend = 1,
  5369. /* this dailink has playback support */
  5370. .ignore_pmdown_time = 1,
  5371. .codec_dai_name = "snd-soc-dummy-dai",
  5372. .codec_name = "snd-soc-dummy",
  5373. },
  5374. {
  5375. .name = MSM_DAILINK_NAME(LowLatency),
  5376. .stream_name = "MultiMedia5",
  5377. .cpu_dai_name = "MultiMedia5",
  5378. .platform_name = "msm-pcm-dsp.1",
  5379. .dynamic = 1,
  5380. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5381. .dpcm_playback = 1,
  5382. .dpcm_capture = 1,
  5383. .codec_dai_name = "snd-soc-dummy-dai",
  5384. .codec_name = "snd-soc-dummy",
  5385. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5386. SND_SOC_DPCM_TRIGGER_POST},
  5387. .ignore_suspend = 1,
  5388. /* this dainlink has playback support */
  5389. .ignore_pmdown_time = 1,
  5390. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5391. .ops = &msm_fe_qos_ops,
  5392. },
  5393. {
  5394. .name = "Listen 1 Audio Service",
  5395. .stream_name = "Listen 1 Audio Service",
  5396. .cpu_dai_name = "LSM1",
  5397. .platform_name = "msm-lsm-client",
  5398. .dynamic = 1,
  5399. .dpcm_capture = 1,
  5400. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5401. SND_SOC_DPCM_TRIGGER_POST },
  5402. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5403. .ignore_suspend = 1,
  5404. .codec_dai_name = "snd-soc-dummy-dai",
  5405. .codec_name = "snd-soc-dummy",
  5406. .id = MSM_FRONTEND_DAI_LSM1,
  5407. },
  5408. /* Multiple Tunnel instances */
  5409. {
  5410. .name = MSM_DAILINK_NAME(Compress2),
  5411. .stream_name = "Compress2",
  5412. .cpu_dai_name = "MultiMedia7",
  5413. .platform_name = "msm-compress-dsp",
  5414. .dynamic = 1,
  5415. .dpcm_playback = 1,
  5416. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5417. SND_SOC_DPCM_TRIGGER_POST},
  5418. .codec_dai_name = "snd-soc-dummy-dai",
  5419. .codec_name = "snd-soc-dummy",
  5420. .ignore_suspend = 1,
  5421. .ignore_pmdown_time = 1,
  5422. /* this dainlink has playback support */
  5423. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5424. },
  5425. {
  5426. .name = MSM_DAILINK_NAME(MultiMedia10),
  5427. .stream_name = "MultiMedia10",
  5428. .cpu_dai_name = "MultiMedia10",
  5429. .platform_name = "msm-pcm-dsp.1",
  5430. .dynamic = 1,
  5431. .dpcm_playback = 1,
  5432. .dpcm_capture = 1,
  5433. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5434. SND_SOC_DPCM_TRIGGER_POST},
  5435. .codec_dai_name = "snd-soc-dummy-dai",
  5436. .codec_name = "snd-soc-dummy",
  5437. .ignore_suspend = 1,
  5438. .ignore_pmdown_time = 1,
  5439. /* this dainlink has playback support */
  5440. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5441. },
  5442. {
  5443. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5444. .stream_name = "MM_NOIRQ",
  5445. .cpu_dai_name = "MultiMedia8",
  5446. .platform_name = "msm-pcm-dsp-noirq",
  5447. .dynamic = 1,
  5448. .dpcm_playback = 1,
  5449. .dpcm_capture = 1,
  5450. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5451. SND_SOC_DPCM_TRIGGER_POST},
  5452. .codec_dai_name = "snd-soc-dummy-dai",
  5453. .codec_name = "snd-soc-dummy",
  5454. .ignore_suspend = 1,
  5455. .ignore_pmdown_time = 1,
  5456. /* this dainlink has playback support */
  5457. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5458. .ops = &msm_fe_qos_ops,
  5459. },
  5460. /* HDMI Hostless */
  5461. {
  5462. .name = "HDMI_RX_HOSTLESS",
  5463. .stream_name = "HDMI_RX_HOSTLESS",
  5464. .cpu_dai_name = "HDMI_HOSTLESS",
  5465. .platform_name = "msm-pcm-hostless",
  5466. .dynamic = 1,
  5467. .dpcm_playback = 1,
  5468. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5469. SND_SOC_DPCM_TRIGGER_POST},
  5470. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5471. .ignore_suspend = 1,
  5472. .ignore_pmdown_time = 1,
  5473. .codec_dai_name = "snd-soc-dummy-dai",
  5474. .codec_name = "snd-soc-dummy",
  5475. },
  5476. {
  5477. .name = "VoiceMMode2",
  5478. .stream_name = "VoiceMMode2",
  5479. .cpu_dai_name = "VoiceMMode2",
  5480. .platform_name = "msm-pcm-voice",
  5481. .dynamic = 1,
  5482. .dpcm_playback = 1,
  5483. .dpcm_capture = 1,
  5484. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5485. SND_SOC_DPCM_TRIGGER_POST},
  5486. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5487. .ignore_suspend = 1,
  5488. .ignore_pmdown_time = 1,
  5489. .codec_dai_name = "snd-soc-dummy-dai",
  5490. .codec_name = "snd-soc-dummy",
  5491. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5492. },
  5493. /* LSM FE */
  5494. {
  5495. .name = "Listen 2 Audio Service",
  5496. .stream_name = "Listen 2 Audio Service",
  5497. .cpu_dai_name = "LSM2",
  5498. .platform_name = "msm-lsm-client",
  5499. .dynamic = 1,
  5500. .dpcm_capture = 1,
  5501. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5502. SND_SOC_DPCM_TRIGGER_POST },
  5503. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5504. .ignore_suspend = 1,
  5505. .codec_dai_name = "snd-soc-dummy-dai",
  5506. .codec_name = "snd-soc-dummy",
  5507. .id = MSM_FRONTEND_DAI_LSM2,
  5508. },
  5509. {
  5510. .name = "Listen 3 Audio Service",
  5511. .stream_name = "Listen 3 Audio Service",
  5512. .cpu_dai_name = "LSM3",
  5513. .platform_name = "msm-lsm-client",
  5514. .dynamic = 1,
  5515. .dpcm_capture = 1,
  5516. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5517. SND_SOC_DPCM_TRIGGER_POST },
  5518. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5519. .ignore_suspend = 1,
  5520. .codec_dai_name = "snd-soc-dummy-dai",
  5521. .codec_name = "snd-soc-dummy",
  5522. .id = MSM_FRONTEND_DAI_LSM3,
  5523. },
  5524. {
  5525. .name = "Listen 4 Audio Service",
  5526. .stream_name = "Listen 4 Audio Service",
  5527. .cpu_dai_name = "LSM4",
  5528. .platform_name = "msm-lsm-client",
  5529. .dynamic = 1,
  5530. .dpcm_capture = 1,
  5531. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5532. SND_SOC_DPCM_TRIGGER_POST },
  5533. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5534. .ignore_suspend = 1,
  5535. .codec_dai_name = "snd-soc-dummy-dai",
  5536. .codec_name = "snd-soc-dummy",
  5537. .id = MSM_FRONTEND_DAI_LSM4,
  5538. },
  5539. {
  5540. .name = "Listen 5 Audio Service",
  5541. .stream_name = "Listen 5 Audio Service",
  5542. .cpu_dai_name = "LSM5",
  5543. .platform_name = "msm-lsm-client",
  5544. .dynamic = 1,
  5545. .dpcm_capture = 1,
  5546. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5547. SND_SOC_DPCM_TRIGGER_POST },
  5548. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5549. .ignore_suspend = 1,
  5550. .codec_dai_name = "snd-soc-dummy-dai",
  5551. .codec_name = "snd-soc-dummy",
  5552. .id = MSM_FRONTEND_DAI_LSM5,
  5553. },
  5554. {
  5555. .name = "Listen 6 Audio Service",
  5556. .stream_name = "Listen 6 Audio Service",
  5557. .cpu_dai_name = "LSM6",
  5558. .platform_name = "msm-lsm-client",
  5559. .dynamic = 1,
  5560. .dpcm_capture = 1,
  5561. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5562. SND_SOC_DPCM_TRIGGER_POST },
  5563. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5564. .ignore_suspend = 1,
  5565. .codec_dai_name = "snd-soc-dummy-dai",
  5566. .codec_name = "snd-soc-dummy",
  5567. .id = MSM_FRONTEND_DAI_LSM6,
  5568. },
  5569. {
  5570. .name = "Listen 7 Audio Service",
  5571. .stream_name = "Listen 7 Audio Service",
  5572. .cpu_dai_name = "LSM7",
  5573. .platform_name = "msm-lsm-client",
  5574. .dynamic = 1,
  5575. .dpcm_capture = 1,
  5576. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5577. SND_SOC_DPCM_TRIGGER_POST },
  5578. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5579. .ignore_suspend = 1,
  5580. .codec_dai_name = "snd-soc-dummy-dai",
  5581. .codec_name = "snd-soc-dummy",
  5582. .id = MSM_FRONTEND_DAI_LSM7,
  5583. },
  5584. {
  5585. .name = "Listen 8 Audio Service",
  5586. .stream_name = "Listen 8 Audio Service",
  5587. .cpu_dai_name = "LSM8",
  5588. .platform_name = "msm-lsm-client",
  5589. .dynamic = 1,
  5590. .dpcm_capture = 1,
  5591. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5592. SND_SOC_DPCM_TRIGGER_POST },
  5593. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5594. .ignore_suspend = 1,
  5595. .codec_dai_name = "snd-soc-dummy-dai",
  5596. .codec_name = "snd-soc-dummy",
  5597. .id = MSM_FRONTEND_DAI_LSM8,
  5598. },
  5599. {
  5600. .name = MSM_DAILINK_NAME(Media9),
  5601. .stream_name = "MultiMedia9",
  5602. .cpu_dai_name = "MultiMedia9",
  5603. .platform_name = "msm-pcm-dsp.0",
  5604. .dynamic = 1,
  5605. .dpcm_playback = 1,
  5606. .dpcm_capture = 1,
  5607. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5608. SND_SOC_DPCM_TRIGGER_POST},
  5609. .codec_dai_name = "snd-soc-dummy-dai",
  5610. .codec_name = "snd-soc-dummy",
  5611. .ignore_suspend = 1,
  5612. /* this dainlink has playback support */
  5613. .ignore_pmdown_time = 1,
  5614. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5615. },
  5616. {
  5617. .name = MSM_DAILINK_NAME(Compress4),
  5618. .stream_name = "Compress4",
  5619. .cpu_dai_name = "MultiMedia11",
  5620. .platform_name = "msm-compress-dsp",
  5621. .dynamic = 1,
  5622. .dpcm_playback = 1,
  5623. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5624. SND_SOC_DPCM_TRIGGER_POST},
  5625. .codec_dai_name = "snd-soc-dummy-dai",
  5626. .codec_name = "snd-soc-dummy",
  5627. .ignore_suspend = 1,
  5628. .ignore_pmdown_time = 1,
  5629. /* this dainlink has playback support */
  5630. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5631. },
  5632. {
  5633. .name = MSM_DAILINK_NAME(Compress5),
  5634. .stream_name = "Compress5",
  5635. .cpu_dai_name = "MultiMedia12",
  5636. .platform_name = "msm-compress-dsp",
  5637. .dynamic = 1,
  5638. .dpcm_playback = 1,
  5639. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5640. SND_SOC_DPCM_TRIGGER_POST},
  5641. .codec_dai_name = "snd-soc-dummy-dai",
  5642. .codec_name = "snd-soc-dummy",
  5643. .ignore_suspend = 1,
  5644. .ignore_pmdown_time = 1,
  5645. /* this dainlink has playback support */
  5646. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5647. },
  5648. {
  5649. .name = MSM_DAILINK_NAME(Compress6),
  5650. .stream_name = "Compress6",
  5651. .cpu_dai_name = "MultiMedia13",
  5652. .platform_name = "msm-compress-dsp",
  5653. .dynamic = 1,
  5654. .dpcm_playback = 1,
  5655. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5656. SND_SOC_DPCM_TRIGGER_POST},
  5657. .codec_dai_name = "snd-soc-dummy-dai",
  5658. .codec_name = "snd-soc-dummy",
  5659. .ignore_suspend = 1,
  5660. .ignore_pmdown_time = 1,
  5661. /* this dainlink has playback support */
  5662. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5663. },
  5664. {
  5665. .name = MSM_DAILINK_NAME(Compress7),
  5666. .stream_name = "Compress7",
  5667. .cpu_dai_name = "MultiMedia14",
  5668. .platform_name = "msm-compress-dsp",
  5669. .dynamic = 1,
  5670. .dpcm_playback = 1,
  5671. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5672. SND_SOC_DPCM_TRIGGER_POST},
  5673. .codec_dai_name = "snd-soc-dummy-dai",
  5674. .codec_name = "snd-soc-dummy",
  5675. .ignore_suspend = 1,
  5676. .ignore_pmdown_time = 1,
  5677. /* this dainlink has playback support */
  5678. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5679. },
  5680. {
  5681. .name = MSM_DAILINK_NAME(Compress8),
  5682. .stream_name = "Compress8",
  5683. .cpu_dai_name = "MultiMedia15",
  5684. .platform_name = "msm-compress-dsp",
  5685. .dynamic = 1,
  5686. .dpcm_playback = 1,
  5687. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5688. SND_SOC_DPCM_TRIGGER_POST},
  5689. .codec_dai_name = "snd-soc-dummy-dai",
  5690. .codec_name = "snd-soc-dummy",
  5691. .ignore_suspend = 1,
  5692. .ignore_pmdown_time = 1,
  5693. /* this dainlink has playback support */
  5694. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5695. },
  5696. {
  5697. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5698. .stream_name = "MM_NOIRQ_2",
  5699. .cpu_dai_name = "MultiMedia16",
  5700. .platform_name = "msm-pcm-dsp-noirq",
  5701. .dynamic = 1,
  5702. .dpcm_playback = 1,
  5703. .dpcm_capture = 1,
  5704. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5705. SND_SOC_DPCM_TRIGGER_POST},
  5706. .codec_dai_name = "snd-soc-dummy-dai",
  5707. .codec_name = "snd-soc-dummy",
  5708. .ignore_suspend = 1,
  5709. .ignore_pmdown_time = 1,
  5710. /* this dainlink has playback support */
  5711. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5712. },
  5713. {
  5714. .name = "SLIMBUS_8 Hostless",
  5715. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5716. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5717. .platform_name = "msm-pcm-hostless",
  5718. .dynamic = 1,
  5719. .dpcm_capture = 1,
  5720. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5721. SND_SOC_DPCM_TRIGGER_POST},
  5722. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5723. .ignore_suspend = 1,
  5724. .codec_dai_name = "snd-soc-dummy-dai",
  5725. .codec_name = "snd-soc-dummy",
  5726. },
  5727. /* Hostless PCM purpose */
  5728. {
  5729. .name = "CDC_DMA Hostless",
  5730. .stream_name = "CDC_DMA Hostless",
  5731. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5732. .platform_name = "msm-pcm-hostless",
  5733. .dynamic = 1,
  5734. .dpcm_playback = 1,
  5735. .dpcm_capture = 1,
  5736. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5737. SND_SOC_DPCM_TRIGGER_POST},
  5738. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5739. .ignore_suspend = 1,
  5740. /* this dailink has playback support */
  5741. .ignore_pmdown_time = 1,
  5742. .codec_dai_name = "snd-soc-dummy-dai",
  5743. .codec_name = "snd-soc-dummy",
  5744. },
  5745. };
  5746. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5747. {
  5748. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5749. .stream_name = "WSA CDC DMA0 Capture",
  5750. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5751. .platform_name = "msm-pcm-hostless",
  5752. .codec_name = "bolero_codec",
  5753. .codec_dai_name = "wsa_macro_vifeedback",
  5754. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5755. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5756. .ignore_suspend = 1,
  5757. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5758. .ops = &msm_cdc_dma_be_ops,
  5759. },
  5760. };
  5761. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5762. {
  5763. .name = MSM_DAILINK_NAME(ASM Loopback),
  5764. .stream_name = "MultiMedia6",
  5765. .cpu_dai_name = "MultiMedia6",
  5766. .platform_name = "msm-pcm-loopback",
  5767. .dynamic = 1,
  5768. .dpcm_playback = 1,
  5769. .dpcm_capture = 1,
  5770. .codec_dai_name = "snd-soc-dummy-dai",
  5771. .codec_name = "snd-soc-dummy",
  5772. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5773. SND_SOC_DPCM_TRIGGER_POST},
  5774. .ignore_suspend = 1,
  5775. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5776. .ignore_pmdown_time = 1,
  5777. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5778. },
  5779. {
  5780. .name = "USB Audio Hostless",
  5781. .stream_name = "USB Audio Hostless",
  5782. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5783. .platform_name = "msm-pcm-hostless",
  5784. .dynamic = 1,
  5785. .dpcm_playback = 1,
  5786. .dpcm_capture = 1,
  5787. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5788. SND_SOC_DPCM_TRIGGER_POST},
  5789. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5790. .ignore_suspend = 1,
  5791. .ignore_pmdown_time = 1,
  5792. .codec_dai_name = "snd-soc-dummy-dai",
  5793. .codec_name = "snd-soc-dummy",
  5794. },
  5795. {
  5796. .name = "SLIMBUS_7 Hostless",
  5797. .stream_name = "SLIMBUS_7 Hostless",
  5798. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5799. .platform_name = "msm-pcm-hostless",
  5800. .dynamic = 1,
  5801. .dpcm_capture = 1,
  5802. .dpcm_playback = 1,
  5803. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5804. SND_SOC_DPCM_TRIGGER_POST},
  5805. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5806. .ignore_suspend = 1,
  5807. .ignore_pmdown_time = 1,
  5808. .codec_dai_name = "snd-soc-dummy-dai",
  5809. .codec_name = "snd-soc-dummy",
  5810. },
  5811. {
  5812. .name = MSM_DAILINK_NAME(Compr Capture),
  5813. .stream_name = "Compr Capture",
  5814. .cpu_dai_name = "MultiMedia18",
  5815. .platform_name = "msm-compress-dsp",
  5816. .dynamic = 1,
  5817. .dpcm_capture = 1,
  5818. .codec_dai_name = "snd-soc-dummy-dai",
  5819. .codec_name = "snd-soc-dummy",
  5820. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5821. SND_SOC_DPCM_TRIGGER_POST},
  5822. .ignore_pmdown_time = 1,
  5823. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  5824. },
  5825. {
  5826. .name = MSM_DAILINK_NAME(Transcode Loopback Playback),
  5827. .stream_name = "Transcode Loopback Playback",
  5828. .cpu_dai_name = "MultiMedia26",
  5829. .platform_name = "msm-transcode-loopback",
  5830. .dynamic = 1,
  5831. .dpcm_playback = 1,
  5832. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5833. SND_SOC_DPCM_TRIGGER_POST},
  5834. .codec_dai_name = "snd-soc-dummy-dai",
  5835. .codec_name = "snd-soc-dummy",
  5836. .ignore_suspend = 1,
  5837. .ignore_pmdown_time = 1,
  5838. /* this dailink has playback support */
  5839. .id = MSM_FRONTEND_DAI_MULTIMEDIA26,
  5840. },
  5841. {
  5842. .name = MSM_DAILINK_NAME(Transcode Loopback Capture),
  5843. .stream_name = "Transcode Loopback Capture",
  5844. .cpu_dai_name = "MultiMedia27",
  5845. .platform_name = "msm-transcode-loopback",
  5846. .dynamic = 1,
  5847. .dpcm_capture = 1,
  5848. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5849. SND_SOC_DPCM_TRIGGER_POST},
  5850. .codec_dai_name = "snd-soc-dummy-dai",
  5851. .codec_name = "snd-soc-dummy",
  5852. .ignore_suspend = 1,
  5853. .ignore_pmdown_time = 1,
  5854. .id = MSM_FRONTEND_DAI_MULTIMEDIA27,
  5855. },
  5856. };
  5857. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5858. /* Backend AFE DAI Links */
  5859. {
  5860. .name = LPASS_BE_AFE_PCM_RX,
  5861. .stream_name = "AFE Playback",
  5862. .cpu_dai_name = "msm-dai-q6-dev.224",
  5863. .platform_name = "msm-pcm-routing",
  5864. .codec_name = "msm-stub-codec.1",
  5865. .codec_dai_name = "msm-stub-rx",
  5866. .no_pcm = 1,
  5867. .dpcm_playback = 1,
  5868. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5869. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5870. /* this dainlink has playback support */
  5871. .ignore_pmdown_time = 1,
  5872. .ignore_suspend = 1,
  5873. },
  5874. {
  5875. .name = LPASS_BE_AFE_PCM_TX,
  5876. .stream_name = "AFE Capture",
  5877. .cpu_dai_name = "msm-dai-q6-dev.225",
  5878. .platform_name = "msm-pcm-routing",
  5879. .codec_name = "msm-stub-codec.1",
  5880. .codec_dai_name = "msm-stub-tx",
  5881. .no_pcm = 1,
  5882. .dpcm_capture = 1,
  5883. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5884. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5885. .ignore_suspend = 1,
  5886. },
  5887. /* Incall Record Uplink BACK END DAI Link */
  5888. {
  5889. .name = LPASS_BE_INCALL_RECORD_TX,
  5890. .stream_name = "Voice Uplink Capture",
  5891. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5892. .platform_name = "msm-pcm-routing",
  5893. .codec_name = "msm-stub-codec.1",
  5894. .codec_dai_name = "msm-stub-tx",
  5895. .no_pcm = 1,
  5896. .dpcm_capture = 1,
  5897. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5898. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5899. .ignore_suspend = 1,
  5900. },
  5901. /* Incall Record Downlink BACK END DAI Link */
  5902. {
  5903. .name = LPASS_BE_INCALL_RECORD_RX,
  5904. .stream_name = "Voice Downlink Capture",
  5905. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5906. .platform_name = "msm-pcm-routing",
  5907. .codec_name = "msm-stub-codec.1",
  5908. .codec_dai_name = "msm-stub-tx",
  5909. .no_pcm = 1,
  5910. .dpcm_capture = 1,
  5911. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5912. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5913. .ignore_suspend = 1,
  5914. },
  5915. /* Incall Music BACK END DAI Link */
  5916. {
  5917. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5918. .stream_name = "Voice Farend Playback",
  5919. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5920. .platform_name = "msm-pcm-routing",
  5921. .codec_name = "msm-stub-codec.1",
  5922. .codec_dai_name = "msm-stub-rx",
  5923. .no_pcm = 1,
  5924. .dpcm_playback = 1,
  5925. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5926. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5927. .ignore_suspend = 1,
  5928. .ignore_pmdown_time = 1,
  5929. },
  5930. /* Incall Music 2 BACK END DAI Link */
  5931. {
  5932. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5933. .stream_name = "Voice2 Farend Playback",
  5934. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5935. .platform_name = "msm-pcm-routing",
  5936. .codec_name = "msm-stub-codec.1",
  5937. .codec_dai_name = "msm-stub-rx",
  5938. .no_pcm = 1,
  5939. .dpcm_playback = 1,
  5940. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5941. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5942. .ignore_suspend = 1,
  5943. .ignore_pmdown_time = 1,
  5944. },
  5945. {
  5946. .name = LPASS_BE_USB_AUDIO_RX,
  5947. .stream_name = "USB Audio Playback",
  5948. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5949. .platform_name = "msm-pcm-routing",
  5950. .codec_name = "msm-stub-codec.1",
  5951. .codec_dai_name = "msm-stub-rx",
  5952. .no_pcm = 1,
  5953. .dpcm_playback = 1,
  5954. .id = MSM_BACKEND_DAI_USB_RX,
  5955. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5956. .ignore_pmdown_time = 1,
  5957. .ignore_suspend = 1,
  5958. },
  5959. {
  5960. .name = LPASS_BE_USB_AUDIO_TX,
  5961. .stream_name = "USB Audio Capture",
  5962. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5963. .platform_name = "msm-pcm-routing",
  5964. .codec_name = "msm-stub-codec.1",
  5965. .codec_dai_name = "msm-stub-tx",
  5966. .no_pcm = 1,
  5967. .dpcm_capture = 1,
  5968. .id = MSM_BACKEND_DAI_USB_TX,
  5969. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5970. .ignore_suspend = 1,
  5971. },
  5972. {
  5973. .name = LPASS_BE_PRI_TDM_RX_0,
  5974. .stream_name = "Primary TDM0 Playback",
  5975. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5976. .platform_name = "msm-pcm-routing",
  5977. .codec_name = "msm-stub-codec.1",
  5978. .codec_dai_name = "msm-stub-rx",
  5979. .no_pcm = 1,
  5980. .dpcm_playback = 1,
  5981. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5982. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5983. .ops = &qcs405_tdm_be_ops,
  5984. .ignore_suspend = 1,
  5985. .ignore_pmdown_time = 1,
  5986. },
  5987. {
  5988. .name = LPASS_BE_PRI_TDM_TX_0,
  5989. .stream_name = "Primary TDM0 Capture",
  5990. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5991. .platform_name = "msm-pcm-routing",
  5992. .codec_name = "msm-stub-codec.1",
  5993. .codec_dai_name = "msm-stub-tx",
  5994. .no_pcm = 1,
  5995. .dpcm_capture = 1,
  5996. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5997. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5998. .ops = &qcs405_tdm_be_ops,
  5999. .ignore_suspend = 1,
  6000. },
  6001. {
  6002. .name = LPASS_BE_SEC_TDM_RX_0,
  6003. .stream_name = "Secondary TDM0 Playback",
  6004. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  6005. .platform_name = "msm-pcm-routing",
  6006. .codec_name = "msm-stub-codec.1",
  6007. .codec_dai_name = "msm-stub-rx",
  6008. .no_pcm = 1,
  6009. .dpcm_playback = 1,
  6010. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  6011. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6012. .ops = &qcs405_tdm_be_ops,
  6013. .ignore_suspend = 1,
  6014. .ignore_pmdown_time = 1,
  6015. },
  6016. {
  6017. .name = LPASS_BE_SEC_TDM_TX_0,
  6018. .stream_name = "Secondary TDM0 Capture",
  6019. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  6020. .platform_name = "msm-pcm-routing",
  6021. .codec_name = "msm-stub-codec.1",
  6022. .codec_dai_name = "msm-stub-tx",
  6023. .no_pcm = 1,
  6024. .dpcm_capture = 1,
  6025. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  6026. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6027. .ops = &qcs405_tdm_be_ops,
  6028. .ignore_suspend = 1,
  6029. },
  6030. {
  6031. .name = LPASS_BE_TERT_TDM_RX_0,
  6032. .stream_name = "Tertiary TDM0 Playback",
  6033. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  6034. .platform_name = "msm-pcm-routing",
  6035. .codec_name = "msm-stub-codec.1",
  6036. .codec_dai_name = "msm-stub-rx",
  6037. .no_pcm = 1,
  6038. .dpcm_playback = 1,
  6039. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  6040. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6041. .ops = &qcs405_tdm_be_ops,
  6042. .ignore_suspend = 1,
  6043. .ignore_pmdown_time = 1,
  6044. },
  6045. {
  6046. .name = LPASS_BE_TERT_TDM_TX_0,
  6047. .stream_name = "Tertiary TDM0 Capture",
  6048. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  6049. .platform_name = "msm-pcm-routing",
  6050. .codec_name = "msm-stub-codec.1",
  6051. .codec_dai_name = "msm-stub-tx",
  6052. .no_pcm = 1,
  6053. .dpcm_capture = 1,
  6054. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  6055. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6056. .ops = &qcs405_tdm_be_ops,
  6057. .ignore_suspend = 1,
  6058. },
  6059. {
  6060. .name = LPASS_BE_QUAT_TDM_RX_0,
  6061. .stream_name = "Quaternary TDM0 Playback",
  6062. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  6063. .platform_name = "msm-pcm-routing",
  6064. .codec_name = "msm-stub-codec.1",
  6065. .codec_dai_name = "msm-stub-rx",
  6066. .no_pcm = 1,
  6067. .dpcm_playback = 1,
  6068. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  6069. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6070. .ops = &qcs405_tdm_be_ops,
  6071. .ignore_suspend = 1,
  6072. .ignore_pmdown_time = 1,
  6073. },
  6074. {
  6075. .name = LPASS_BE_QUAT_TDM_TX_0,
  6076. .stream_name = "Quaternary TDM0 Capture",
  6077. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  6078. .platform_name = "msm-pcm-routing",
  6079. .codec_name = "msm-stub-codec.1",
  6080. .codec_dai_name = "msm-stub-tx",
  6081. .no_pcm = 1,
  6082. .dpcm_capture = 1,
  6083. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  6084. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6085. .ops = &qcs405_tdm_be_ops,
  6086. .ignore_suspend = 1,
  6087. },
  6088. {
  6089. .name = LPASS_BE_QUIN_TDM_RX_0,
  6090. .stream_name = "Quinary TDM0 Playback",
  6091. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  6092. .platform_name = "msm-pcm-routing",
  6093. .codec_name = "msm-stub-codec.1",
  6094. .codec_dai_name = "msm-stub-rx",
  6095. .no_pcm = 1,
  6096. .dpcm_playback = 1,
  6097. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  6098. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6099. .ops = &qcs405_tdm_be_ops,
  6100. .ignore_suspend = 1,
  6101. .ignore_pmdown_time = 1,
  6102. },
  6103. {
  6104. .name = LPASS_BE_QUIN_TDM_TX_0,
  6105. .stream_name = "Quinary TDM0 Capture",
  6106. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  6107. .platform_name = "msm-pcm-routing",
  6108. .codec_name = "msm-stub-codec.1",
  6109. .codec_dai_name = "msm-stub-tx",
  6110. .no_pcm = 1,
  6111. .dpcm_capture = 1,
  6112. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  6113. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6114. .ops = &qcs405_tdm_be_ops,
  6115. .ignore_suspend = 1,
  6116. },
  6117. };
  6118. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  6119. {
  6120. .name = LPASS_BE_SLIMBUS_0_RX,
  6121. .stream_name = "Slimbus Playback",
  6122. .cpu_dai_name = "msm-dai-q6-dev.16384",
  6123. .platform_name = "msm-pcm-routing",
  6124. .codec_name = "tasha_codec",
  6125. .codec_dai_name = "tasha_mix_rx1",
  6126. .no_pcm = 1,
  6127. .dpcm_playback = 1,
  6128. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  6129. .init = &msm_audrx_init,
  6130. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6131. /* this dainlink has playback support */
  6132. .ignore_pmdown_time = 1,
  6133. .ignore_suspend = 1,
  6134. .ops = &msm_be_ops,
  6135. },
  6136. {
  6137. .name = LPASS_BE_SLIMBUS_0_TX,
  6138. .stream_name = "Slimbus Capture",
  6139. .cpu_dai_name = "msm-dai-q6-dev.16385",
  6140. .platform_name = "msm-pcm-routing",
  6141. .codec_name = "tasha_codec",
  6142. .codec_dai_name = "tasha_tx1",
  6143. .no_pcm = 1,
  6144. .dpcm_capture = 1,
  6145. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  6146. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6147. .ignore_suspend = 1,
  6148. .ops = &msm_be_ops,
  6149. },
  6150. {
  6151. .name = LPASS_BE_SLIMBUS_1_RX,
  6152. .stream_name = "Slimbus1 Playback",
  6153. .cpu_dai_name = "msm-dai-q6-dev.16386",
  6154. .platform_name = "msm-pcm-routing",
  6155. .codec_name = "tasha_codec",
  6156. .codec_dai_name = "tasha_mix_rx1",
  6157. .no_pcm = 1,
  6158. .dpcm_playback = 1,
  6159. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  6160. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6161. .ops = &msm_be_ops,
  6162. /* dai link has playback support */
  6163. .ignore_pmdown_time = 1,
  6164. .ignore_suspend = 1,
  6165. },
  6166. {
  6167. .name = LPASS_BE_SLIMBUS_1_TX,
  6168. .stream_name = "Slimbus1 Capture",
  6169. .cpu_dai_name = "msm-dai-q6-dev.16387",
  6170. .platform_name = "msm-pcm-routing",
  6171. .codec_name = "tasha_codec",
  6172. .codec_dai_name = "tasha_tx3",
  6173. .no_pcm = 1,
  6174. .dpcm_capture = 1,
  6175. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  6176. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6177. .ops = &msm_be_ops,
  6178. .ignore_suspend = 1,
  6179. },
  6180. {
  6181. .name = LPASS_BE_SLIMBUS_2_RX,
  6182. .stream_name = "Slimbus2 Playback",
  6183. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6184. .platform_name = "msm-pcm-routing",
  6185. .codec_name = "tasha_codec",
  6186. .codec_dai_name = "tasha_rx2",
  6187. .no_pcm = 1,
  6188. .dpcm_playback = 1,
  6189. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6190. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6191. .ops = &msm_be_ops,
  6192. .ignore_pmdown_time = 1,
  6193. .ignore_suspend = 1,
  6194. },
  6195. {
  6196. .name = LPASS_BE_SLIMBUS_3_RX,
  6197. .stream_name = "Slimbus3 Playback",
  6198. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6199. .platform_name = "msm-pcm-routing",
  6200. .codec_name = "tasha_codec",
  6201. .codec_dai_name = "tasha_mix_rx1",
  6202. .no_pcm = 1,
  6203. .dpcm_playback = 1,
  6204. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6205. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6206. .ops = &msm_be_ops,
  6207. /* dai link has playback support */
  6208. .ignore_pmdown_time = 1,
  6209. .ignore_suspend = 1,
  6210. },
  6211. {
  6212. .name = LPASS_BE_SLIMBUS_3_TX,
  6213. .stream_name = "Slimbus3 Capture",
  6214. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6215. .platform_name = "msm-pcm-routing",
  6216. .codec_name = "tasha_codec",
  6217. .codec_dai_name = "tasha_tx1",
  6218. .no_pcm = 1,
  6219. .dpcm_capture = 1,
  6220. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6221. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6222. .ops = &msm_be_ops,
  6223. .ignore_suspend = 1,
  6224. },
  6225. {
  6226. .name = LPASS_BE_SLIMBUS_4_RX,
  6227. .stream_name = "Slimbus4 Playback",
  6228. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6229. .platform_name = "msm-pcm-routing",
  6230. .codec_name = "tasha_codec",
  6231. .codec_dai_name = "tasha_mix_rx1",
  6232. .no_pcm = 1,
  6233. .dpcm_playback = 1,
  6234. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6235. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6236. .ops = &msm_be_ops,
  6237. /* dai link has playback support */
  6238. .ignore_pmdown_time = 1,
  6239. .ignore_suspend = 1,
  6240. },
  6241. {
  6242. .name = LPASS_BE_SLIMBUS_5_RX,
  6243. .stream_name = "Slimbus5 Playback",
  6244. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6245. .platform_name = "msm-pcm-routing",
  6246. .codec_name = "tasha_codec",
  6247. .codec_dai_name = "tasha_rx3",
  6248. .no_pcm = 1,
  6249. .dpcm_playback = 1,
  6250. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6251. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6252. .ops = &msm_be_ops,
  6253. /* dai link has playback support */
  6254. .ignore_pmdown_time = 1,
  6255. .ignore_suspend = 1,
  6256. },
  6257. {
  6258. .name = LPASS_BE_SLIMBUS_6_RX,
  6259. .stream_name = "Slimbus6 Playback",
  6260. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6261. .platform_name = "msm-pcm-routing",
  6262. .codec_name = "tasha_codec",
  6263. .codec_dai_name = "tasha_rx4",
  6264. .no_pcm = 1,
  6265. .dpcm_playback = 1,
  6266. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6267. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6268. .ops = &msm_be_ops,
  6269. /* dai link has playback support */
  6270. .ignore_pmdown_time = 1,
  6271. .ignore_suspend = 1,
  6272. },
  6273. /* Slimbus VI Recording */
  6274. {
  6275. .name = LPASS_BE_SLIMBUS_TX_VI,
  6276. .stream_name = "Slimbus4 Capture",
  6277. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6278. .platform_name = "msm-pcm-routing",
  6279. .codec_name = "tasha_codec",
  6280. .codec_dai_name = "tasha_vifeedback",
  6281. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6282. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6283. .ops = &msm_be_ops,
  6284. .ignore_suspend = 1,
  6285. .no_pcm = 1,
  6286. .dpcm_capture = 1,
  6287. .ignore_pmdown_time = 1,
  6288. },
  6289. };
  6290. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6291. {
  6292. .name = LPASS_BE_SLIMBUS_7_RX,
  6293. .stream_name = "Slimbus7 Playback",
  6294. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6295. .platform_name = "msm-pcm-routing",
  6296. .codec_name = "btfmslim_slave",
  6297. /* BT codec driver determines capabilities based on
  6298. * dai name, bt codecdai name should always contains
  6299. * supported usecase information
  6300. */
  6301. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6302. .no_pcm = 1,
  6303. .dpcm_playback = 1,
  6304. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6305. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6306. .ops = &msm_wcn_ops,
  6307. /* dai link has playback support */
  6308. .ignore_pmdown_time = 1,
  6309. .ignore_suspend = 1,
  6310. },
  6311. {
  6312. .name = LPASS_BE_SLIMBUS_7_TX,
  6313. .stream_name = "Slimbus7 Capture",
  6314. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6315. .platform_name = "msm-pcm-routing",
  6316. .codec_name = "btfmslim_slave",
  6317. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6318. .no_pcm = 1,
  6319. .dpcm_capture = 1,
  6320. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6321. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6322. .ops = &msm_wcn_ops,
  6323. .ignore_suspend = 1,
  6324. },
  6325. {
  6326. .name = LPASS_BE_SLIMBUS_8_TX,
  6327. .stream_name = "Slimbus8 Capture",
  6328. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6329. .platform_name = "msm-pcm-routing",
  6330. .codec_name = "btfmslim_slave",
  6331. .codec_dai_name = "btfm_fm_slim_tx",
  6332. .no_pcm = 1,
  6333. .dpcm_capture = 1,
  6334. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6335. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6336. .init = &msm_wcn_init,
  6337. .ops = &msm_wcn_ops,
  6338. .ignore_suspend = 1,
  6339. },
  6340. {
  6341. .name = LPASS_BE_SLIMBUS_9_TX,
  6342. .stream_name = "Slimbus9 Capture",
  6343. .cpu_dai_name = "msm-dai-q6-dev.16403",
  6344. .platform_name = "msm-pcm-routing",
  6345. .codec_name = "btfmslim_slave",
  6346. .codec_dai_name = "btfm_bt_split_a2dp_slim_tx",
  6347. .no_pcm = 1,
  6348. .dpcm_capture = 1,
  6349. .id = MSM_BACKEND_DAI_SLIMBUS_9_TX,
  6350. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6351. .ops = &msm_wcn_ops,
  6352. .ignore_suspend = 1,
  6353. },
  6354. };
  6355. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6356. {
  6357. .name = LPASS_BE_PRI_MI2S_RX,
  6358. .stream_name = "Primary MI2S Playback",
  6359. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6360. .platform_name = "msm-pcm-routing",
  6361. .codec_name = "msm-stub-codec.1",
  6362. .codec_dai_name = "msm-stub-rx",
  6363. .no_pcm = 1,
  6364. .dpcm_playback = 1,
  6365. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6366. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6367. .ops = &msm_mi2s_be_ops,
  6368. .ignore_suspend = 1,
  6369. .ignore_pmdown_time = 1,
  6370. },
  6371. {
  6372. .name = LPASS_BE_PRI_MI2S_TX,
  6373. .stream_name = "Primary MI2S Capture",
  6374. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6375. .platform_name = "msm-pcm-routing",
  6376. .codec_name = "msm-stub-codec.1",
  6377. .codec_dai_name = "msm-stub-tx",
  6378. .no_pcm = 1,
  6379. .dpcm_capture = 1,
  6380. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6381. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6382. .ops = &msm_mi2s_be_ops,
  6383. .ignore_suspend = 1,
  6384. },
  6385. {
  6386. .name = LPASS_BE_SEC_MI2S_RX,
  6387. .stream_name = "Secondary MI2S Playback",
  6388. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6389. .platform_name = "msm-pcm-routing",
  6390. .codec_name = "msm-stub-codec.1",
  6391. .codec_dai_name = "msm-stub-rx",
  6392. .no_pcm = 1,
  6393. .dpcm_playback = 1,
  6394. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6395. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6396. .ops = &msm_mi2s_be_ops,
  6397. .ignore_suspend = 1,
  6398. .ignore_pmdown_time = 1,
  6399. },
  6400. {
  6401. .name = LPASS_BE_SEC_MI2S_TX,
  6402. .stream_name = "Secondary MI2S Capture",
  6403. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6404. .platform_name = "msm-pcm-routing",
  6405. .codec_name = "msm-stub-codec.1",
  6406. .codec_dai_name = "msm-stub-tx",
  6407. .no_pcm = 1,
  6408. .dpcm_capture = 1,
  6409. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6410. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6411. .ops = &msm_mi2s_be_ops,
  6412. .ignore_suspend = 1,
  6413. },
  6414. {
  6415. .name = LPASS_BE_TERT_MI2S_RX,
  6416. .stream_name = "Tertiary MI2S Playback",
  6417. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6418. .platform_name = "msm-pcm-routing",
  6419. .codec_name = "msm-stub-codec.1",
  6420. .codec_dai_name = "msm-stub-rx",
  6421. .no_pcm = 1,
  6422. .dpcm_playback = 1,
  6423. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6424. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6425. .ops = &msm_mi2s_be_ops,
  6426. .ignore_suspend = 1,
  6427. .ignore_pmdown_time = 1,
  6428. },
  6429. {
  6430. .name = LPASS_BE_TERT_MI2S_TX,
  6431. .stream_name = "Tertiary MI2S Capture",
  6432. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6433. .platform_name = "msm-pcm-routing",
  6434. .codec_name = "msm-stub-codec.1",
  6435. .codec_dai_name = "msm-stub-tx",
  6436. .no_pcm = 1,
  6437. .dpcm_capture = 1,
  6438. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6439. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6440. .ops = &msm_mi2s_be_ops,
  6441. .ignore_suspend = 1,
  6442. },
  6443. {
  6444. .name = LPASS_BE_QUAT_MI2S_RX,
  6445. .stream_name = "Quaternary MI2S Playback",
  6446. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6447. .platform_name = "msm-pcm-routing",
  6448. .codec_name = "msm-stub-codec.1",
  6449. .codec_dai_name = "msm-stub-rx",
  6450. .no_pcm = 1,
  6451. .dpcm_playback = 1,
  6452. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6453. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6454. .ops = &msm_mi2s_be_ops,
  6455. .ignore_suspend = 1,
  6456. .ignore_pmdown_time = 1,
  6457. },
  6458. {
  6459. .name = LPASS_BE_QUAT_MI2S_TX,
  6460. .stream_name = "Quaternary MI2S Capture",
  6461. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6462. .platform_name = "msm-pcm-routing",
  6463. .codec_name = "msm-stub-codec.1",
  6464. .codec_dai_name = "msm-stub-tx",
  6465. .no_pcm = 1,
  6466. .dpcm_capture = 1,
  6467. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6468. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6469. .ops = &msm_mi2s_be_ops,
  6470. .ignore_suspend = 1,
  6471. },
  6472. {
  6473. .name = LPASS_BE_QUIN_MI2S_RX,
  6474. .stream_name = "Quinary MI2S Playback",
  6475. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6476. .platform_name = "msm-pcm-routing",
  6477. .codec_name = "msm-stub-codec.1",
  6478. .codec_dai_name = "msm-stub-rx",
  6479. .no_pcm = 1,
  6480. .dpcm_playback = 1,
  6481. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6482. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6483. .ops = &msm_mi2s_be_ops,
  6484. .ignore_suspend = 1,
  6485. .ignore_pmdown_time = 1,
  6486. },
  6487. {
  6488. .name = LPASS_BE_QUIN_MI2S_TX,
  6489. .stream_name = "Quinary MI2S Capture",
  6490. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6491. .platform_name = "msm-pcm-routing",
  6492. .codec_name = "msm-stub-codec.1",
  6493. .codec_dai_name = "msm-stub-tx",
  6494. .no_pcm = 1,
  6495. .dpcm_capture = 1,
  6496. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6497. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6498. .ops = &msm_mi2s_be_ops,
  6499. .ignore_suspend = 1,
  6500. },
  6501. };
  6502. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6503. /* Primary AUX PCM Backend DAI Links */
  6504. {
  6505. .name = LPASS_BE_AUXPCM_RX,
  6506. .stream_name = "AUX PCM Playback",
  6507. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6508. .platform_name = "msm-pcm-routing",
  6509. .codec_name = "msm-stub-codec.1",
  6510. .codec_dai_name = "msm-stub-rx",
  6511. .no_pcm = 1,
  6512. .dpcm_playback = 1,
  6513. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6514. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6515. .ignore_pmdown_time = 1,
  6516. .ignore_suspend = 1,
  6517. },
  6518. {
  6519. .name = LPASS_BE_AUXPCM_TX,
  6520. .stream_name = "AUX PCM Capture",
  6521. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6522. .platform_name = "msm-pcm-routing",
  6523. .codec_name = "msm-stub-codec.1",
  6524. .codec_dai_name = "msm-stub-tx",
  6525. .no_pcm = 1,
  6526. .dpcm_capture = 1,
  6527. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6528. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6529. .ignore_suspend = 1,
  6530. },
  6531. /* Secondary AUX PCM Backend DAI Links */
  6532. {
  6533. .name = LPASS_BE_SEC_AUXPCM_RX,
  6534. .stream_name = "Sec AUX PCM Playback",
  6535. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6536. .platform_name = "msm-pcm-routing",
  6537. .codec_name = "msm-stub-codec.1",
  6538. .codec_dai_name = "msm-stub-rx",
  6539. .no_pcm = 1,
  6540. .dpcm_playback = 1,
  6541. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6542. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6543. .ignore_pmdown_time = 1,
  6544. .ignore_suspend = 1,
  6545. },
  6546. {
  6547. .name = LPASS_BE_SEC_AUXPCM_TX,
  6548. .stream_name = "Sec AUX PCM Capture",
  6549. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6550. .platform_name = "msm-pcm-routing",
  6551. .codec_name = "msm-stub-codec.1",
  6552. .codec_dai_name = "msm-stub-tx",
  6553. .no_pcm = 1,
  6554. .dpcm_capture = 1,
  6555. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6556. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6557. .ignore_suspend = 1,
  6558. },
  6559. /* Tertiary AUX PCM Backend DAI Links */
  6560. {
  6561. .name = LPASS_BE_TERT_AUXPCM_RX,
  6562. .stream_name = "Tert AUX PCM Playback",
  6563. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6564. .platform_name = "msm-pcm-routing",
  6565. .codec_name = "msm-stub-codec.1",
  6566. .codec_dai_name = "msm-stub-rx",
  6567. .no_pcm = 1,
  6568. .dpcm_playback = 1,
  6569. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6570. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6571. .ignore_suspend = 1,
  6572. },
  6573. {
  6574. .name = LPASS_BE_TERT_AUXPCM_TX,
  6575. .stream_name = "Tert AUX PCM Capture",
  6576. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6577. .platform_name = "msm-pcm-routing",
  6578. .codec_name = "msm-stub-codec.1",
  6579. .codec_dai_name = "msm-stub-tx",
  6580. .no_pcm = 1,
  6581. .dpcm_capture = 1,
  6582. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6583. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6584. .ignore_suspend = 1,
  6585. },
  6586. /* Quaternary AUX PCM Backend DAI Links */
  6587. {
  6588. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6589. .stream_name = "Quat AUX PCM Playback",
  6590. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6591. .platform_name = "msm-pcm-routing",
  6592. .codec_name = "msm-stub-codec.1",
  6593. .codec_dai_name = "msm-stub-rx",
  6594. .no_pcm = 1,
  6595. .dpcm_playback = 1,
  6596. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6597. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6598. .ignore_pmdown_time = 1,
  6599. .ignore_suspend = 1,
  6600. },
  6601. {
  6602. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6603. .stream_name = "Quat AUX PCM Capture",
  6604. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6605. .platform_name = "msm-pcm-routing",
  6606. .codec_name = "msm-stub-codec.1",
  6607. .codec_dai_name = "msm-stub-tx",
  6608. .no_pcm = 1,
  6609. .dpcm_capture = 1,
  6610. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6611. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6612. .ignore_suspend = 1,
  6613. },
  6614. /* Quinary AUX PCM Backend DAI Links */
  6615. {
  6616. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6617. .stream_name = "Quin AUX PCM Playback",
  6618. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6619. .platform_name = "msm-pcm-routing",
  6620. .codec_name = "msm-stub-codec.1",
  6621. .codec_dai_name = "msm-stub-rx",
  6622. .no_pcm = 1,
  6623. .dpcm_playback = 1,
  6624. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6625. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6626. .ignore_pmdown_time = 1,
  6627. .ignore_suspend = 1,
  6628. },
  6629. {
  6630. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6631. .stream_name = "Quin AUX PCM Capture",
  6632. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6633. .platform_name = "msm-pcm-routing",
  6634. .codec_name = "msm-stub-codec.1",
  6635. .codec_dai_name = "msm-stub-tx",
  6636. .no_pcm = 1,
  6637. .dpcm_capture = 1,
  6638. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6639. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6640. .ignore_suspend = 1,
  6641. },
  6642. };
  6643. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6644. /* WSA CDC DMA Backend DAI Links */
  6645. {
  6646. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6647. .stream_name = "WSA CDC DMA0 Playback",
  6648. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6649. .platform_name = "msm-pcm-routing",
  6650. .codec_name = "bolero_codec",
  6651. .codec_dai_name = "wsa_macro_rx1",
  6652. .no_pcm = 1,
  6653. .dpcm_playback = 1,
  6654. .init = &msm_wsa_cdc_dma_init,
  6655. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6656. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6657. .ignore_pmdown_time = 1,
  6658. .ignore_suspend = 1,
  6659. .ops = &msm_cdc_dma_be_ops,
  6660. },
  6661. {
  6662. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6663. .stream_name = "WSA CDC DMA1 Playback",
  6664. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6665. .platform_name = "msm-pcm-routing",
  6666. .codec_name = "bolero_codec",
  6667. .codec_dai_name = "wsa_macro_rx_mix",
  6668. .no_pcm = 1,
  6669. .dpcm_playback = 1,
  6670. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6671. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6672. .ignore_pmdown_time = 1,
  6673. .ignore_suspend = 1,
  6674. .ops = &msm_cdc_dma_be_ops,
  6675. },
  6676. {
  6677. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6678. .stream_name = "WSA CDC DMA1 Capture",
  6679. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6680. .platform_name = "msm-pcm-routing",
  6681. .codec_name = "bolero_codec",
  6682. .codec_dai_name = "wsa_macro_echo",
  6683. .no_pcm = 1,
  6684. .dpcm_capture = 1,
  6685. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6686. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6687. .ignore_suspend = 1,
  6688. .ops = &msm_cdc_dma_be_ops,
  6689. },
  6690. };
  6691. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6692. {
  6693. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6694. .stream_name = "VA CDC DMA0 Capture",
  6695. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6696. .platform_name = "msm-pcm-routing",
  6697. .codec_name = "bolero_codec",
  6698. .codec_dai_name = "va_macro_tx1",
  6699. .no_pcm = 1,
  6700. .dpcm_capture = 1,
  6701. .init = &msm_va_cdc_dma_init,
  6702. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6703. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6704. .ignore_suspend = 1,
  6705. .ops = &msm_cdc_dma_be_ops,
  6706. },
  6707. {
  6708. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6709. .stream_name = "VA CDC DMA1 Capture",
  6710. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6711. .platform_name = "msm-pcm-routing",
  6712. .codec_name = "bolero_codec",
  6713. .codec_dai_name = "va_macro_tx2",
  6714. .no_pcm = 1,
  6715. .dpcm_capture = 1,
  6716. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6717. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6718. .ignore_suspend = 1,
  6719. .ops = &msm_cdc_dma_be_ops,
  6720. },
  6721. };
  6722. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  6723. {
  6724. .name = LPASS_BE_PRI_SPDIF_RX,
  6725. .stream_name = "Primary SPDIF Playback",
  6726. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  6727. .platform_name = "msm-pcm-routing",
  6728. .codec_name = "msm-stub-codec.1",
  6729. .codec_dai_name = "msm-stub-rx",
  6730. .no_pcm = 1,
  6731. .dpcm_playback = 1,
  6732. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  6733. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6734. .ops = &msm_spdif_be_ops,
  6735. .ignore_suspend = 1,
  6736. .ignore_pmdown_time = 1,
  6737. },
  6738. {
  6739. .name = LPASS_BE_PRI_SPDIF_TX,
  6740. .stream_name = "Primary SPDIF Capture",
  6741. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  6742. .platform_name = "msm-pcm-routing",
  6743. .codec_name = "msm-stub-codec.1",
  6744. .codec_dai_name = "msm-stub-tx",
  6745. .no_pcm = 1,
  6746. .dpcm_capture = 1,
  6747. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  6748. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6749. .ops = &msm_spdif_be_ops,
  6750. .ignore_suspend = 1,
  6751. },
  6752. {
  6753. .name = LPASS_BE_SEC_SPDIF_RX,
  6754. .stream_name = "Secondary SPDIF Playback",
  6755. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  6756. .platform_name = "msm-pcm-routing",
  6757. .codec_name = "msm-stub-codec.1",
  6758. .codec_dai_name = "msm-stub-rx",
  6759. .no_pcm = 1,
  6760. .dpcm_playback = 1,
  6761. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  6762. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6763. .ops = &msm_spdif_be_ops,
  6764. .ignore_suspend = 1,
  6765. .ignore_pmdown_time = 1,
  6766. },
  6767. {
  6768. .name = LPASS_BE_SEC_SPDIF_TX,
  6769. .stream_name = "Secondary SPDIF Capture",
  6770. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  6771. .platform_name = "msm-pcm-routing",
  6772. .codec_name = "msm-stub-codec.1",
  6773. .codec_dai_name = "msm-stub-tx",
  6774. .no_pcm = 1,
  6775. .dpcm_capture = 1,
  6776. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  6777. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6778. .ops = &msm_spdif_be_ops,
  6779. .ignore_suspend = 1,
  6780. },
  6781. };
  6782. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  6783. {
  6784. .name = LPASS_BE_AFE_LOOPBACK_TX,
  6785. .stream_name = "AFE Loopback Capture",
  6786. .cpu_dai_name = "msm-dai-q6-dev.24577",
  6787. .platform_name = "msm-pcm-routing",
  6788. .codec_name = "msm-stub-codec.1",
  6789. .codec_dai_name = "msm-stub-tx",
  6790. .no_pcm = 1,
  6791. .dpcm_capture = 1,
  6792. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  6793. .ignore_pmdown_time = 1,
  6794. .ignore_suspend = 1,
  6795. },
  6796. };
  6797. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6798. ARRAY_SIZE(msm_common_dai_links) +
  6799. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6800. ARRAY_SIZE(msm_common_be_dai_links) +
  6801. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6802. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6803. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6804. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6805. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6806. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6807. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6808. ARRAY_SIZE(msm_spdif_be_dai_links) +
  6809. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link)];
  6810. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6811. {
  6812. int ret = 0;
  6813. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6814. &service_nb);
  6815. if (ret < 0)
  6816. pr_err("%s: Audio notifier register failed ret = %d\n",
  6817. __func__, ret);
  6818. return ret;
  6819. }
  6820. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6821. struct snd_ctl_elem_value *ucontrol)
  6822. {
  6823. int ret = 0;
  6824. int port_id;
  6825. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6826. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6827. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6828. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6829. (vad_enable < 0) || (vad_enable > 1) ||
  6830. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6831. pr_err("%s: Invalid arguments\n", __func__);
  6832. ret = -EINVAL;
  6833. goto done;
  6834. }
  6835. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6836. vad_enable, preroll_config, vad_intf);
  6837. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6838. if (ret) {
  6839. pr_err("%s: Invalid vad interface\n", __func__);
  6840. goto done;
  6841. }
  6842. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6843. done:
  6844. return ret;
  6845. }
  6846. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6847. {
  6848. int ret = 0;
  6849. uint32_t tasha_codec = 0;
  6850. ret = afe_cal_init_hwdep(card);
  6851. if (ret) {
  6852. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6853. ret = 0;
  6854. }
  6855. /* tasha late probe when it is present */
  6856. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6857. &tasha_codec);
  6858. if (ret) {
  6859. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6860. ret = 0;
  6861. } else {
  6862. if (tasha_codec) {
  6863. ret = msm_snd_card_tasha_late_probe(card);
  6864. if (ret)
  6865. dev_err(card->dev, "%s: tasha late probe err\n",
  6866. __func__);
  6867. }
  6868. }
  6869. return ret;
  6870. }
  6871. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6872. .name = "qcs405-snd-card",
  6873. .controls = msm_snd_controls,
  6874. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6875. .late_probe = msm_snd_card_codec_late_probe,
  6876. };
  6877. static int msm_populate_dai_link_component_of_node(
  6878. struct snd_soc_card *card)
  6879. {
  6880. int i, index, ret = 0;
  6881. struct device *cdev = card->dev;
  6882. struct snd_soc_dai_link *dai_link = card->dai_link;
  6883. struct device_node *np;
  6884. if (!cdev) {
  6885. pr_err("%s: Sound card device memory NULL\n", __func__);
  6886. return -ENODEV;
  6887. }
  6888. for (i = 0; i < card->num_links; i++) {
  6889. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6890. continue;
  6891. /* populate platform_of_node for snd card dai links */
  6892. if (dai_link[i].platform_name &&
  6893. !dai_link[i].platform_of_node) {
  6894. index = of_property_match_string(cdev->of_node,
  6895. "asoc-platform-names",
  6896. dai_link[i].platform_name);
  6897. if (index < 0) {
  6898. pr_err("%s: No match found for platform name: %s\n",
  6899. __func__, dai_link[i].platform_name);
  6900. ret = index;
  6901. goto err;
  6902. }
  6903. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6904. index);
  6905. if (!np) {
  6906. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6907. __func__, dai_link[i].platform_name,
  6908. index);
  6909. ret = -ENODEV;
  6910. goto err;
  6911. }
  6912. dai_link[i].platform_of_node = np;
  6913. dai_link[i].platform_name = NULL;
  6914. }
  6915. /* populate cpu_of_node for snd card dai links */
  6916. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6917. index = of_property_match_string(cdev->of_node,
  6918. "asoc-cpu-names",
  6919. dai_link[i].cpu_dai_name);
  6920. if (index >= 0) {
  6921. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6922. index);
  6923. if (!np) {
  6924. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6925. __func__,
  6926. dai_link[i].cpu_dai_name);
  6927. ret = -ENODEV;
  6928. goto err;
  6929. }
  6930. dai_link[i].cpu_of_node = np;
  6931. dai_link[i].cpu_dai_name = NULL;
  6932. }
  6933. }
  6934. /* populate codec_of_node for snd card dai links */
  6935. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6936. index = of_property_match_string(cdev->of_node,
  6937. "asoc-codec-names",
  6938. dai_link[i].codec_name);
  6939. if (index < 0)
  6940. continue;
  6941. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6942. index);
  6943. if (!np) {
  6944. pr_err("%s: retrieving phandle for codec %s failed\n",
  6945. __func__, dai_link[i].codec_name);
  6946. ret = -ENODEV;
  6947. goto err;
  6948. }
  6949. dai_link[i].codec_of_node = np;
  6950. dai_link[i].codec_name = NULL;
  6951. }
  6952. }
  6953. err:
  6954. return ret;
  6955. }
  6956. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6957. /* FrontEnd DAI Links */
  6958. {
  6959. .name = "MSMSTUB Media1",
  6960. .stream_name = "MultiMedia1",
  6961. .cpu_dai_name = "MultiMedia1",
  6962. .platform_name = "msm-pcm-dsp.0",
  6963. .dynamic = 1,
  6964. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6965. .dpcm_playback = 1,
  6966. .dpcm_capture = 1,
  6967. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6968. SND_SOC_DPCM_TRIGGER_POST},
  6969. .codec_dai_name = "snd-soc-dummy-dai",
  6970. .codec_name = "snd-soc-dummy",
  6971. .ignore_suspend = 1,
  6972. /* this dainlink has playback support */
  6973. .ignore_pmdown_time = 1,
  6974. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6975. },
  6976. };
  6977. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6978. /* Backend DAI Links */
  6979. {
  6980. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6981. .stream_name = "VA CDC DMA0 Capture",
  6982. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6983. .platform_name = "msm-pcm-routing",
  6984. .codec_name = "bolero_codec",
  6985. .codec_dai_name = "va_macro_tx1",
  6986. .no_pcm = 1,
  6987. .dpcm_capture = 1,
  6988. .init = &msm_va_cdc_dma_init,
  6989. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6990. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6991. .ignore_suspend = 1,
  6992. .ops = &msm_cdc_dma_be_ops,
  6993. },
  6994. {
  6995. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6996. .stream_name = "VA CDC DMA1 Capture",
  6997. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6998. .platform_name = "msm-pcm-routing",
  6999. .codec_name = "bolero_codec",
  7000. .codec_dai_name = "va_macro_tx2",
  7001. .no_pcm = 1,
  7002. .dpcm_capture = 1,
  7003. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  7004. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7005. .ignore_suspend = 1,
  7006. .ops = &msm_cdc_dma_be_ops,
  7007. },
  7008. };
  7009. static struct snd_soc_dai_link msm_stub_dai_links[
  7010. ARRAY_SIZE(msm_stub_fe_dai_links) +
  7011. ARRAY_SIZE(msm_stub_be_dai_links)];
  7012. struct snd_soc_card snd_soc_card_stub_msm = {
  7013. .name = "qcs405-stub-snd-card",
  7014. };
  7015. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  7016. { .compatible = "qcom,qcs405-asoc-snd",
  7017. .data = "codec"},
  7018. { .compatible = "qcom,qcs405-asoc-snd-stub",
  7019. .data = "stub_codec"},
  7020. {},
  7021. };
  7022. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  7023. {
  7024. struct snd_soc_card *card = NULL;
  7025. struct snd_soc_dai_link *dailink;
  7026. int total_links = 0;
  7027. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  7028. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  7029. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  7030. uint32_t afe_loopback_intf = 0;
  7031. const struct of_device_id *match;
  7032. char __iomem *spdif_cfg, *spdif_pin_ctl;
  7033. int rc = 0;
  7034. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  7035. if (!match) {
  7036. dev_err(dev, "%s: No DT match found for sound card\n",
  7037. __func__);
  7038. return NULL;
  7039. }
  7040. if (!strcmp(match->data, "codec")) {
  7041. card = &snd_soc_card_qcs405_msm;
  7042. memcpy(msm_qcs405_dai_links + total_links,
  7043. msm_common_dai_links,
  7044. sizeof(msm_common_dai_links));
  7045. total_links += ARRAY_SIZE(msm_common_dai_links);
  7046. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  7047. &wsa_bolero_codec);
  7048. if (rc) {
  7049. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  7050. __func__);
  7051. } else {
  7052. if (wsa_bolero_codec) {
  7053. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  7054. __func__);
  7055. memcpy(msm_qcs405_dai_links + total_links,
  7056. msm_bolero_fe_dai_links,
  7057. sizeof(msm_bolero_fe_dai_links));
  7058. total_links +=
  7059. ARRAY_SIZE(msm_bolero_fe_dai_links);
  7060. }
  7061. }
  7062. memcpy(msm_qcs405_dai_links + total_links,
  7063. msm_common_misc_fe_dai_links,
  7064. sizeof(msm_common_misc_fe_dai_links));
  7065. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  7066. memcpy(msm_qcs405_dai_links + total_links,
  7067. msm_common_be_dai_links,
  7068. sizeof(msm_common_be_dai_links));
  7069. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  7070. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  7071. &tasha_codec);
  7072. if (rc) {
  7073. dev_dbg(dev, "%s: No DT match tasha codec\n",
  7074. __func__);
  7075. } else {
  7076. if (tasha_codec) {
  7077. memcpy(msm_qcs405_dai_links + total_links,
  7078. msm_tasha_be_dai_links,
  7079. sizeof(msm_tasha_be_dai_links));
  7080. total_links +=
  7081. ARRAY_SIZE(msm_tasha_be_dai_links);
  7082. }
  7083. }
  7084. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  7085. &va_bolero_codec);
  7086. if (rc) {
  7087. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  7088. __func__);
  7089. } else {
  7090. if (va_bolero_codec) {
  7091. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  7092. __func__);
  7093. memcpy(msm_qcs405_dai_links + total_links,
  7094. msm_va_cdc_dma_be_dai_links,
  7095. sizeof(msm_va_cdc_dma_be_dai_links));
  7096. total_links +=
  7097. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  7098. }
  7099. }
  7100. if (wsa_bolero_codec) {
  7101. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  7102. __func__);
  7103. memcpy(msm_qcs405_dai_links + total_links,
  7104. msm_wsa_cdc_dma_be_dai_links,
  7105. sizeof(msm_wsa_cdc_dma_be_dai_links));
  7106. total_links +=
  7107. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  7108. }
  7109. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  7110. &mi2s_audio_intf);
  7111. if (rc) {
  7112. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  7113. __func__);
  7114. } else {
  7115. if (mi2s_audio_intf) {
  7116. memcpy(msm_qcs405_dai_links + total_links,
  7117. msm_mi2s_be_dai_links,
  7118. sizeof(msm_mi2s_be_dai_links));
  7119. total_links +=
  7120. ARRAY_SIZE(msm_mi2s_be_dai_links);
  7121. }
  7122. }
  7123. rc = of_property_read_u32(dev->of_node,
  7124. "qcom,auxpcm-audio-intf",
  7125. &auxpcm_audio_intf);
  7126. if (rc) {
  7127. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  7128. __func__);
  7129. } else {
  7130. if (auxpcm_audio_intf) {
  7131. memcpy(msm_qcs405_dai_links + total_links,
  7132. msm_auxpcm_be_dai_links,
  7133. sizeof(msm_auxpcm_be_dai_links));
  7134. total_links +=
  7135. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  7136. }
  7137. }
  7138. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  7139. &spdif_audio_intf);
  7140. if (rc) {
  7141. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  7142. __func__);
  7143. } else {
  7144. if (spdif_audio_intf) {
  7145. memcpy(msm_qcs405_dai_links + total_links,
  7146. msm_spdif_be_dai_links,
  7147. sizeof(msm_spdif_be_dai_links));
  7148. total_links +=
  7149. ARRAY_SIZE(msm_spdif_be_dai_links);
  7150. /* enable spdif coax pins */
  7151. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  7152. spdif_pin_ctl =
  7153. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  7154. iowrite32(0xc0, spdif_cfg);
  7155. iowrite32(0x2220, spdif_pin_ctl);
  7156. }
  7157. }
  7158. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  7159. &wcn_audio_intf);
  7160. if (rc) {
  7161. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  7162. __func__);
  7163. } else {
  7164. if (wcn_audio_intf) {
  7165. memcpy(msm_qcs405_dai_links + total_links,
  7166. msm_wcn_be_dai_links,
  7167. sizeof(msm_wcn_be_dai_links));
  7168. total_links +=
  7169. ARRAY_SIZE(msm_wcn_be_dai_links);
  7170. }
  7171. }
  7172. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  7173. &afe_loopback_intf);
  7174. if (rc) {
  7175. dev_dbg(dev, "%s: No DT match AFE loopback audio interface\n",
  7176. __func__);
  7177. } else {
  7178. if (afe_loopback_intf) {
  7179. memcpy(msm_qcs405_dai_links + total_links,
  7180. msm_afe_rxtx_lb_be_dai_link,
  7181. sizeof(msm_afe_rxtx_lb_be_dai_link));
  7182. total_links +=
  7183. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  7184. }
  7185. }
  7186. dailink = msm_qcs405_dai_links;
  7187. } else if (!strcmp(match->data, "stub_codec")) {
  7188. card = &snd_soc_card_stub_msm;
  7189. memcpy(msm_stub_dai_links + total_links,
  7190. msm_stub_fe_dai_links,
  7191. sizeof(msm_stub_fe_dai_links));
  7192. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  7193. memcpy(msm_stub_dai_links + total_links,
  7194. msm_stub_be_dai_links,
  7195. sizeof(msm_stub_be_dai_links));
  7196. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  7197. dailink = msm_stub_dai_links;
  7198. }
  7199. if (card) {
  7200. card->dai_link = dailink;
  7201. card->num_links = total_links;
  7202. }
  7203. return card;
  7204. }
  7205. static int msm_wsa881x_init(struct snd_soc_component *component)
  7206. {
  7207. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7208. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7209. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  7210. SPKR_L_BOOST, SPKR_L_VI};
  7211. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  7212. SPKR_R_BOOST, SPKR_R_VI};
  7213. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  7214. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  7215. struct msm_asoc_mach_data *pdata;
  7216. struct snd_soc_dapm_context *dapm;
  7217. int ret = 0;
  7218. if (!component) {
  7219. pr_err("%s component is NULL\n", __func__);
  7220. return -EINVAL;
  7221. }
  7222. dapm = snd_soc_component_get_dapm(component);
  7223. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  7224. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  7225. __func__, component->name);
  7226. wsa881x_set_channel_map(component, &spkleft_ports[0],
  7227. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7228. &ch_rate[0], &spkleft_port_types[0]);
  7229. if (dapm->component) {
  7230. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  7231. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  7232. }
  7233. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  7234. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  7235. __func__, component->name);
  7236. wsa881x_set_channel_map(component, &spkright_ports[0],
  7237. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7238. &ch_rate[0], &spkright_port_types[0]);
  7239. if (dapm->component) {
  7240. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7241. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7242. }
  7243. } else {
  7244. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  7245. component->name);
  7246. ret = -EINVAL;
  7247. goto err;
  7248. }
  7249. pdata = snd_soc_card_get_drvdata(component->card);
  7250. if (pdata && pdata->codec_root)
  7251. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7252. component);
  7253. err:
  7254. return ret;
  7255. }
  7256. static int msm_init_wsa_dev(struct platform_device *pdev,
  7257. struct snd_soc_card *card)
  7258. {
  7259. struct device_node *wsa_of_node;
  7260. u32 wsa_max_devs;
  7261. u32 wsa_dev_cnt;
  7262. int i;
  7263. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7264. const char *wsa_auxdev_name_prefix[1];
  7265. char *dev_name_str = NULL;
  7266. int found = 0;
  7267. int ret = 0;
  7268. /* Get maximum WSA device count for this platform */
  7269. ret = of_property_read_u32(pdev->dev.of_node,
  7270. "qcom,wsa-max-devs", &wsa_max_devs);
  7271. if (ret) {
  7272. dev_info(&pdev->dev,
  7273. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7274. __func__, pdev->dev.of_node->full_name, ret);
  7275. card->num_aux_devs = 0;
  7276. return 0;
  7277. }
  7278. if (wsa_max_devs == 0) {
  7279. dev_warn(&pdev->dev,
  7280. "%s: Max WSA devices is 0 for this target?\n",
  7281. __func__);
  7282. card->num_aux_devs = 0;
  7283. return 0;
  7284. }
  7285. /* Get count of WSA device phandles for this platform */
  7286. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7287. "qcom,wsa-devs", NULL);
  7288. if (wsa_dev_cnt == -ENOENT) {
  7289. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7290. __func__);
  7291. goto err;
  7292. } else if (wsa_dev_cnt <= 0) {
  7293. dev_err(&pdev->dev,
  7294. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7295. __func__, wsa_dev_cnt);
  7296. ret = -EINVAL;
  7297. goto err;
  7298. }
  7299. /*
  7300. * Expect total phandles count to be NOT less than maximum possible
  7301. * WSA count. However, if it is less, then assign same value to
  7302. * max count as well.
  7303. */
  7304. if (wsa_dev_cnt < wsa_max_devs) {
  7305. dev_dbg(&pdev->dev,
  7306. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7307. __func__, wsa_max_devs, wsa_dev_cnt);
  7308. wsa_max_devs = wsa_dev_cnt;
  7309. }
  7310. /* Make sure prefix string passed for each WSA device */
  7311. ret = of_property_count_strings(pdev->dev.of_node,
  7312. "qcom,wsa-aux-dev-prefix");
  7313. if (ret != wsa_dev_cnt) {
  7314. dev_err(&pdev->dev,
  7315. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7316. __func__, wsa_dev_cnt, ret);
  7317. ret = -EINVAL;
  7318. goto err;
  7319. }
  7320. /*
  7321. * Alloc mem to store phandle and index info of WSA device, if already
  7322. * registered with ALSA core
  7323. */
  7324. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7325. sizeof(struct msm_wsa881x_dev_info),
  7326. GFP_KERNEL);
  7327. if (!wsa881x_dev_info) {
  7328. ret = -ENOMEM;
  7329. goto err;
  7330. }
  7331. /*
  7332. * search and check whether all WSA devices are already
  7333. * registered with ALSA core or not. If found a node, store
  7334. * the node and the index in a local array of struct for later
  7335. * use.
  7336. */
  7337. for (i = 0; i < wsa_dev_cnt; i++) {
  7338. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7339. "qcom,wsa-devs", i);
  7340. if (unlikely(!wsa_of_node)) {
  7341. /* we should not be here */
  7342. dev_err(&pdev->dev,
  7343. "%s: wsa dev node is not present\n",
  7344. __func__);
  7345. ret = -EINVAL;
  7346. goto err_free_dev_info;
  7347. }
  7348. if (soc_find_component(wsa_of_node, NULL)) {
  7349. /* WSA device registered with ALSA core */
  7350. wsa881x_dev_info[found].of_node = wsa_of_node;
  7351. wsa881x_dev_info[found].index = i;
  7352. found++;
  7353. if (found == wsa_max_devs)
  7354. break;
  7355. }
  7356. }
  7357. if (found < wsa_max_devs) {
  7358. dev_err(&pdev->dev,
  7359. "%s: failed to find %d components. Found only %d\n",
  7360. __func__, wsa_max_devs, found);
  7361. return -EPROBE_DEFER;
  7362. }
  7363. dev_info(&pdev->dev,
  7364. "%s: found %d wsa881x devices registered with ALSA core\n",
  7365. __func__, found);
  7366. card->num_aux_devs = wsa_max_devs;
  7367. card->num_configs = wsa_max_devs;
  7368. /* Alloc array of AUX devs struct */
  7369. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7370. sizeof(struct snd_soc_aux_dev),
  7371. GFP_KERNEL);
  7372. if (!msm_aux_dev) {
  7373. ret = -ENOMEM;
  7374. goto err_free_dev_info;
  7375. }
  7376. /* Alloc array of codec conf struct */
  7377. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7378. sizeof(struct snd_soc_codec_conf),
  7379. GFP_KERNEL);
  7380. if (!msm_codec_conf) {
  7381. ret = -ENOMEM;
  7382. goto err_free_aux_dev;
  7383. }
  7384. for (i = 0; i < card->num_aux_devs; i++) {
  7385. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7386. GFP_KERNEL);
  7387. if (!dev_name_str) {
  7388. ret = -ENOMEM;
  7389. goto err_free_cdc_conf;
  7390. }
  7391. ret = of_property_read_string_index(pdev->dev.of_node,
  7392. "qcom,wsa-aux-dev-prefix",
  7393. wsa881x_dev_info[i].index,
  7394. wsa_auxdev_name_prefix);
  7395. if (ret) {
  7396. dev_err(&pdev->dev,
  7397. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7398. __func__, ret);
  7399. ret = -EINVAL;
  7400. goto err_free_dev_name_str;
  7401. }
  7402. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7403. msm_aux_dev[i].name = dev_name_str;
  7404. msm_aux_dev[i].codec_name = NULL;
  7405. msm_aux_dev[i].codec_of_node =
  7406. wsa881x_dev_info[i].of_node;
  7407. msm_aux_dev[i].init = msm_wsa881x_init;
  7408. msm_codec_conf[i].dev_name = NULL;
  7409. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7410. msm_codec_conf[i].of_node =
  7411. wsa881x_dev_info[i].of_node;
  7412. }
  7413. card->codec_conf = msm_codec_conf;
  7414. card->aux_dev = msm_aux_dev;
  7415. return 0;
  7416. err_free_dev_name_str:
  7417. devm_kfree(&pdev->dev, dev_name_str);
  7418. err_free_cdc_conf:
  7419. devm_kfree(&pdev->dev, msm_codec_conf);
  7420. err_free_aux_dev:
  7421. devm_kfree(&pdev->dev, msm_aux_dev);
  7422. err_free_dev_info:
  7423. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7424. err:
  7425. return ret;
  7426. }
  7427. static int msm_csra66x0_init(struct snd_soc_component *component)
  7428. {
  7429. if (!component) {
  7430. pr_err("%s component is NULL\n", __func__);
  7431. return -EINVAL;
  7432. }
  7433. return 0;
  7434. }
  7435. static int msm_init_csra_dev(struct platform_device *pdev,
  7436. struct snd_soc_card *card)
  7437. {
  7438. struct device_node *csra_of_node;
  7439. u32 csra_max_devs;
  7440. u32 csra_dev_cnt;
  7441. char *dev_name_str = NULL;
  7442. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7443. const char *csra_auxdev_name_prefix[1];
  7444. int i;
  7445. int found = 0;
  7446. int ret = 0;
  7447. /* Get maximum CSRA device count for this platform */
  7448. ret = of_property_read_u32(pdev->dev.of_node,
  7449. "qcom,csra-max-devs", &csra_max_devs);
  7450. if (ret) {
  7451. dev_info(&pdev->dev,
  7452. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7453. __func__, pdev->dev.of_node->full_name, ret);
  7454. card->num_aux_devs = 0;
  7455. return 0;
  7456. }
  7457. if (csra_max_devs == 0) {
  7458. dev_warn(&pdev->dev,
  7459. "%s: Max CSRA devices is 0 for this target?\n",
  7460. __func__);
  7461. return 0;
  7462. }
  7463. /* Get count of CSRA device phandles for this platform */
  7464. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7465. "qcom,csra-devs", NULL);
  7466. if (csra_dev_cnt == -ENOENT) {
  7467. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7468. __func__);
  7469. goto err;
  7470. } else if (csra_dev_cnt <= 0) {
  7471. dev_err(&pdev->dev,
  7472. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7473. __func__, csra_dev_cnt);
  7474. ret = -EINVAL;
  7475. goto err;
  7476. }
  7477. /*
  7478. * Expect total phandles count to be NOT less than maximum possible
  7479. * CSRA count. However, if it is less, then assign same value to
  7480. * max count as well.
  7481. */
  7482. if (csra_dev_cnt < csra_max_devs) {
  7483. dev_dbg(&pdev->dev,
  7484. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7485. __func__, csra_max_devs, csra_dev_cnt);
  7486. csra_max_devs = csra_dev_cnt;
  7487. }
  7488. /* Make sure prefix string passed for each CSRA device */
  7489. ret = of_property_count_strings(pdev->dev.of_node,
  7490. "qcom,csra-aux-dev-prefix");
  7491. if (ret != csra_dev_cnt) {
  7492. dev_err(&pdev->dev,
  7493. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7494. __func__, csra_dev_cnt, ret);
  7495. ret = -EINVAL;
  7496. goto err;
  7497. }
  7498. /*
  7499. * Alloc mem to store phandle and index info of CSRA device, if already
  7500. * registered with ALSA core
  7501. */
  7502. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7503. sizeof(struct msm_csra66x0_dev_info),
  7504. GFP_KERNEL);
  7505. if (!csra66x0_dev_info) {
  7506. ret = -ENOMEM;
  7507. goto err;
  7508. }
  7509. /*
  7510. * search and check whether all CSRA devices are already
  7511. * registered with ALSA core or not. If found a node, store
  7512. * the node and the index in a local array of struct for later
  7513. * use.
  7514. */
  7515. for (i = 0; i < csra_dev_cnt; i++) {
  7516. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7517. "qcom,csra-devs", i);
  7518. if (unlikely(!csra_of_node)) {
  7519. /* we should not be here */
  7520. dev_err(&pdev->dev,
  7521. "%s: csra dev node is not present\n",
  7522. __func__);
  7523. ret = -EINVAL;
  7524. goto err_free_dev_info;
  7525. }
  7526. if (soc_find_component(csra_of_node, NULL)) {
  7527. /* CSRA device registered with ALSA core */
  7528. csra66x0_dev_info[found].of_node = csra_of_node;
  7529. csra66x0_dev_info[found].index = i;
  7530. found++;
  7531. if (found == csra_max_devs)
  7532. break;
  7533. }
  7534. }
  7535. if (found < csra_max_devs) {
  7536. dev_dbg(&pdev->dev,
  7537. "%s: failed to find %d components. Found only %d\n",
  7538. __func__, csra_max_devs, found);
  7539. return -EPROBE_DEFER;
  7540. }
  7541. dev_info(&pdev->dev,
  7542. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7543. __func__, found);
  7544. card->num_aux_devs = csra_max_devs;
  7545. card->num_configs = csra_max_devs;
  7546. /* Alloc array of AUX devs struct */
  7547. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7548. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7549. if (!msm_aux_dev) {
  7550. ret = -ENOMEM;
  7551. goto err_free_dev_info;
  7552. }
  7553. /* Alloc array of codec conf struct */
  7554. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7555. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7556. if (!msm_codec_conf) {
  7557. ret = -ENOMEM;
  7558. goto err_free_aux_dev;
  7559. }
  7560. for (i = 0; i < card->num_aux_devs; i++) {
  7561. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7562. GFP_KERNEL);
  7563. if (!dev_name_str) {
  7564. ret = -ENOMEM;
  7565. goto err_free_cdc_conf;
  7566. }
  7567. ret = of_property_read_string_index(pdev->dev.of_node,
  7568. "qcom,csra-aux-dev-prefix",
  7569. csra66x0_dev_info[i].index,
  7570. csra_auxdev_name_prefix);
  7571. if (ret) {
  7572. dev_err(&pdev->dev,
  7573. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7574. __func__, ret);
  7575. ret = -EINVAL;
  7576. goto err_free_dev_name_str;
  7577. }
  7578. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7579. msm_aux_dev[i].name = dev_name_str;
  7580. msm_aux_dev[i].codec_name = NULL;
  7581. msm_aux_dev[i].codec_of_node =
  7582. csra66x0_dev_info[i].of_node;
  7583. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7584. msm_codec_conf[i].dev_name = NULL;
  7585. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7586. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7587. }
  7588. card->codec_conf = msm_codec_conf;
  7589. card->aux_dev = msm_aux_dev;
  7590. return 0;
  7591. err_free_dev_name_str:
  7592. devm_kfree(&pdev->dev, dev_name_str);
  7593. err_free_cdc_conf:
  7594. devm_kfree(&pdev->dev, msm_codec_conf);
  7595. err_free_aux_dev:
  7596. devm_kfree(&pdev->dev, msm_aux_dev);
  7597. err_free_dev_info:
  7598. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7599. err:
  7600. return ret;
  7601. }
  7602. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7603. {
  7604. int count;
  7605. u32 mi2s_master_slave[MI2S_MAX];
  7606. int ret;
  7607. for (count = 0; count < MI2S_MAX; count++) {
  7608. mutex_init(&mi2s_intf_conf[count].lock);
  7609. mi2s_intf_conf[count].ref_cnt = 0;
  7610. }
  7611. ret = of_property_read_u32_array(pdev->dev.of_node,
  7612. "qcom,msm-mi2s-master",
  7613. mi2s_master_slave, MI2S_MAX);
  7614. if (ret) {
  7615. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7616. __func__);
  7617. } else {
  7618. for (count = 0; count < MI2S_MAX; count++) {
  7619. mi2s_intf_conf[count].msm_is_mi2s_master =
  7620. mi2s_master_slave[count];
  7621. }
  7622. }
  7623. }
  7624. static void msm_i2s_auxpcm_deinit(void)
  7625. {
  7626. int count;
  7627. for (count = 0; count < MI2S_MAX; count++) {
  7628. mutex_destroy(&mi2s_intf_conf[count].lock);
  7629. mi2s_intf_conf[count].ref_cnt = 0;
  7630. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7631. }
  7632. }
  7633. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7634. uint32_t busnum, uint32_t addr)
  7635. {
  7636. struct i2c_adapter *adap;
  7637. u8 rbuf;
  7638. struct i2c_msg msg;
  7639. int status = 0;
  7640. adap = i2c_get_adapter(busnum);
  7641. if (!adap) {
  7642. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7643. __func__, busnum);
  7644. return -EBUSY;
  7645. }
  7646. /* to test presence, read one byte from device */
  7647. msg.addr = addr;
  7648. msg.flags = I2C_M_RD;
  7649. msg.len = 1;
  7650. msg.buf = &rbuf;
  7651. status = i2c_transfer(adap, &msg, 1);
  7652. i2c_put_adapter(adap);
  7653. if (status != 1) {
  7654. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  7655. __func__, addr);
  7656. return -ENODEV;
  7657. }
  7658. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  7659. __func__, addr);
  7660. return 0;
  7661. }
  7662. static int msm_detect_ep92_dev(struct platform_device *pdev,
  7663. struct snd_soc_card *card)
  7664. {
  7665. int i;
  7666. uint32_t ep92_busnum = 0;
  7667. uint32_t ep92_reg = 0;
  7668. const char *ep92_name = NULL;
  7669. struct snd_soc_dai_link *dai;
  7670. int rc = 0;
  7671. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  7672. &ep92_busnum);
  7673. if (rc) {
  7674. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  7675. return 0;
  7676. }
  7677. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  7678. &ep92_reg);
  7679. if (rc) {
  7680. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  7681. return 0;
  7682. }
  7683. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  7684. &ep92_name);
  7685. if (rc) {
  7686. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  7687. return 0;
  7688. }
  7689. /* check I2C bus for connected ep92 chip */
  7690. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7691. /* check a second time after a short delay */
  7692. msleep(20);
  7693. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7694. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  7695. __func__);
  7696. /* continue with snd_card registration without ep92 */
  7697. return 0;
  7698. }
  7699. }
  7700. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  7701. /* update codec info in MI2S dai link */
  7702. dai = &msm_mi2s_be_dai_links[0];
  7703. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  7704. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  7705. dev_dbg(&pdev->dev,
  7706. "%s: Set Sec MI2S dai to ep92 codec\n",
  7707. __func__);
  7708. dai->codec_name = ep92_name;
  7709. dai->codec_dai_name = "ep92-hdmi";
  7710. break;
  7711. }
  7712. dai++;
  7713. }
  7714. /* update codec info in SPDIF dai link */
  7715. dai = &msm_spdif_be_dai_links[0];
  7716. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  7717. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  7718. dev_dbg(&pdev->dev,
  7719. "%s: Set Sec SPDIF dai to ep92 codec\n",
  7720. __func__);
  7721. dai->codec_name = ep92_name;
  7722. dai->codec_dai_name = "ep92-arc";
  7723. break;
  7724. }
  7725. dai++;
  7726. }
  7727. return 0;
  7728. }
  7729. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7730. {
  7731. struct snd_soc_card *card;
  7732. struct msm_asoc_mach_data *pdata;
  7733. int ret;
  7734. u32 val;
  7735. const char *micb_supply_str = "tdm-vdd-micb-supply";
  7736. const char *micb_supply_str1 = "tdm-vdd-micb";
  7737. const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
  7738. const char *micb_current_str = "qcom,tdm-vdd-micb-current";
  7739. if (!pdev->dev.of_node) {
  7740. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  7741. return -EINVAL;
  7742. }
  7743. pdata = devm_kzalloc(&pdev->dev,
  7744. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7745. if (!pdata)
  7746. return -ENOMEM;
  7747. /* test for ep92 HDMI bridge and update dai links accordingly */
  7748. ret = msm_detect_ep92_dev(pdev, card);
  7749. if (ret)
  7750. goto err;
  7751. card = populate_snd_card_dailinks(&pdev->dev);
  7752. if (!card) {
  7753. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7754. ret = -EINVAL;
  7755. goto err;
  7756. }
  7757. card->dev = &pdev->dev;
  7758. platform_set_drvdata(pdev, card);
  7759. snd_soc_card_set_drvdata(card, pdata);
  7760. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7761. if (ret) {
  7762. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  7763. ret);
  7764. goto err;
  7765. }
  7766. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7767. if (ret) {
  7768. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  7769. ret);
  7770. goto err;
  7771. }
  7772. ret = msm_populate_dai_link_component_of_node(card);
  7773. if (ret) {
  7774. ret = -EPROBE_DEFER;
  7775. goto err;
  7776. }
  7777. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  7778. if (ret) {
  7779. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  7780. val = 0;
  7781. }
  7782. if (val) {
  7783. pdata->codec_is_csra = true;
  7784. mi2s_rx_cfg[PRIM_MI2S].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  7785. ret = msm_init_csra_dev(pdev, card);
  7786. if (ret)
  7787. goto err;
  7788. } else {
  7789. pdata->codec_is_csra = false;
  7790. ret = msm_init_wsa_dev(pdev, card);
  7791. if (ret)
  7792. goto err;
  7793. }
  7794. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7795. "qcom,cdc-dmic01-gpios", 0);
  7796. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7797. "qcom,cdc-dmic23-gpios", 0);
  7798. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7799. "qcom,cdc-dmic45-gpios", 0);
  7800. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7801. "qcom,cdc-dmic67-gpios", 0);
  7802. pdata->lineout_booster_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7803. "qcom,lineout-booster-gpio", 0);
  7804. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7805. "qcom,pri-mi2s-gpios", 0);
  7806. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7807. "qcom,sec-mi2s-gpios", 0);
  7808. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7809. "qcom,tert-mi2s-gpios", 0);
  7810. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7811. "qcom,quat-mi2s-gpios", 0);
  7812. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7813. "qcom,quin-mi2s-gpios", 0);
  7814. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  7815. pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev,
  7816. micb_supply_str1);
  7817. if (IS_ERR(pdata->tdm_micb_supply)) {
  7818. ret = PTR_ERR(pdata->tdm_micb_supply);
  7819. dev_err(&pdev->dev,
  7820. "%s:Failed to get micbias supply for TDM Mic %d\n",
  7821. __func__, ret);
  7822. }
  7823. ret = of_property_read_u32(pdev->dev.of_node,
  7824. micb_voltage_str,
  7825. &pdata->tdm_micb_voltage);
  7826. if (ret) {
  7827. dev_err(&pdev->dev,
  7828. "%s:Looking up %s property in node %s failed\n",
  7829. __func__, micb_voltage_str,
  7830. pdev->dev.of_node->full_name);
  7831. }
  7832. ret = of_property_read_u32(pdev->dev.of_node,
  7833. micb_current_str,
  7834. &pdata->tdm_micb_current);
  7835. if (ret) {
  7836. dev_err(&pdev->dev,
  7837. "%s:Looking up %s property in node %s failed\n",
  7838. __func__, micb_current_str,
  7839. pdev->dev.of_node->full_name);
  7840. }
  7841. }
  7842. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7843. if (ret == -EPROBE_DEFER) {
  7844. if (codec_reg_done)
  7845. ret = -EINVAL;
  7846. goto err;
  7847. } else if (ret) {
  7848. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  7849. ret);
  7850. goto err;
  7851. }
  7852. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7853. spdev = pdev;
  7854. ret = msm_mdf_mem_init();
  7855. if (ret)
  7856. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  7857. ret);
  7858. msm_i2s_auxpcm_init(pdev);
  7859. is_initial_boot = true;
  7860. return 0;
  7861. err:
  7862. return ret;
  7863. }
  7864. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7865. {
  7866. audio_notifier_deregister("qcs405");
  7867. msm_i2s_auxpcm_deinit();
  7868. msm_mdf_mem_deinit();
  7869. return 0;
  7870. }
  7871. static struct platform_driver qcs405_asoc_machine_driver = {
  7872. .driver = {
  7873. .name = DRV_NAME,
  7874. .owner = THIS_MODULE,
  7875. .pm = &snd_soc_pm_ops,
  7876. .of_match_table = qcs405_asoc_machine_of_match,
  7877. },
  7878. .probe = msm_asoc_machine_probe,
  7879. .remove = msm_asoc_machine_remove,
  7880. };
  7881. module_platform_driver(qcs405_asoc_machine_driver);
  7882. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  7883. MODULE_LICENSE("GPL v2");
  7884. MODULE_ALIAS("platform:" DRV_NAME);
  7885. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);