sde_plane.c 149 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115511651175118511951205121512251235124512551265127512851295130513151325133513451355136513751385139514051415142514351445145514651475148514951505151515251535154515551565157515851595160516151625163516451655166516751685169517051715172517351745175517651775178517951805181518251835184518551865187518851895190519151925193519451955196519751985199520052015202520352045205520652075208520952105211521252135214
  1. /*
  2. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <linux/debugfs.h>
  21. #include <linux/dma-buf.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/msm_drm_pp.h>
  24. #include <linux/version.h>
  25. #include <drm/drm_blend.h>
  26. #include "msm_prop.h"
  27. #include "msm_drv.h"
  28. #include "sde_kms.h"
  29. #include "sde_fence.h"
  30. #include "sde_formats.h"
  31. #include "sde_hw_sspp.h"
  32. #include "sde_hw_catalog_format.h"
  33. #include "sde_trace.h"
  34. #include "sde_crtc.h"
  35. #include "sde_vbif.h"
  36. #include "sde_plane.h"
  37. #include "sde_color_processing.h"
  38. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  39. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  40. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  41. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  42. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  43. #define PHASE_STEP_SHIFT 21
  44. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  45. #define PHASE_RESIDUAL 15
  46. #define SHARP_STRENGTH_DEFAULT 32
  47. #define SHARP_EDGE_THR_DEFAULT 112
  48. #define SHARP_SMOOTH_THR_DEFAULT 8
  49. #define SHARP_NOISE_THR_DEFAULT 2
  50. #define SDE_NAME_SIZE 12
  51. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  52. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  53. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  54. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  55. /**
  56. * enum sde_plane_qos - Different qos configurations for each pipe
  57. *
  58. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  59. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  60. * this configuration is mutually exclusive from VBLANK_CTRL.
  61. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  62. */
  63. enum sde_plane_qos {
  64. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  65. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  66. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  67. };
  68. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  69. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  70. {
  71. struct msm_drm_private *priv;
  72. if (!plane || !plane->dev)
  73. return NULL;
  74. priv = plane->dev->dev_private;
  75. if (!priv)
  76. return NULL;
  77. return to_sde_kms(priv->kms);
  78. }
  79. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  80. {
  81. struct drm_plane_state *pstate = NULL;
  82. struct drm_crtc *drm_crtc = NULL;
  83. struct sde_crtc *sde_crtc = NULL;
  84. struct sde_crtc_mixer *mixer = NULL;
  85. struct sde_hw_ctl *ctl = NULL;
  86. if (!plane) {
  87. DRM_ERROR("Invalid plane %pK\n", plane);
  88. return NULL;
  89. }
  90. pstate = plane->state;
  91. if (!pstate) {
  92. DRM_ERROR("Invalid plane state %pK\n", pstate);
  93. return NULL;
  94. }
  95. drm_crtc = pstate->crtc;
  96. if (!drm_crtc) {
  97. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  98. return NULL;
  99. }
  100. sde_crtc = to_sde_crtc(drm_crtc);
  101. if (!sde_crtc) {
  102. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  103. return NULL;
  104. }
  105. /* it will always return the first mixer and single CTL */
  106. mixer = sde_crtc->mixers;
  107. if (!mixer) {
  108. DRM_ERROR("invalid mixer %pK\n", mixer);
  109. return NULL;
  110. }
  111. ctl = mixer->hw_ctl;
  112. if (!mixer) {
  113. DRM_ERROR("invalid ctl %pK\n", ctl);
  114. return NULL;
  115. }
  116. return ctl;
  117. }
  118. static void _sde_plane_setup_panel_stacking(struct sde_plane *psde,
  119. struct sde_plane_state *pstate)
  120. {
  121. struct sde_hw_pipe_line_insertion_cfg *cfg;
  122. struct sde_crtc_state *cstate;
  123. u32 h_start = 0, h_total = 0, y_start = 0;
  124. struct drm_plane_state *dpstate = NULL;
  125. struct drm_crtc *drm_crtc = NULL;
  126. if (!psde || !psde->base.state || !psde->base.state->crtc) {
  127. SDE_ERROR("Invalid plane psde %p or drm plane state or drm crtc\n", psde);
  128. return;
  129. }
  130. dpstate = psde->base.state;
  131. drm_crtc = dpstate->crtc;
  132. cstate = to_sde_crtc_state(drm_crtc->state);
  133. pstate->lineinsertion_feature = cstate->line_insertion.panel_line_insertion_enable;
  134. if ((!test_bit(SDE_SSPP_LINE_INSERTION, (unsigned long *)&psde->features)) ||
  135. !cstate->line_insertion.panel_line_insertion_enable)
  136. return;
  137. cfg = &pstate->line_insertion_cfg;
  138. memset(cfg, 0, sizeof(*cfg));
  139. if (!cstate->line_insertion.padding_height)
  140. return;
  141. sde_crtc_calc_vpadding_param(psde->base.state->crtc->state,
  142. pstate->base.crtc_y, pstate->base.crtc_h,
  143. &y_start, &h_start, &h_total);
  144. cfg->enable = true;
  145. cfg->dummy_lines = cstate->line_insertion.padding_dummy;
  146. cfg->active_lines = cstate->line_insertion.padding_active;
  147. cfg->first_active_lines = h_start;
  148. cfg->dst_h = h_total;
  149. psde->pipe_cfg.dst_rect.y += y_start - pstate->base.crtc_y;
  150. }
  151. static bool sde_plane_enabled(const struct drm_plane_state *state)
  152. {
  153. return state && state->fb && state->crtc;
  154. }
  155. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  156. {
  157. struct sde_plane *psde;
  158. if (!plane)
  159. return false;
  160. psde = to_sde_plane(plane);
  161. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  162. }
  163. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  164. enum sde_sspp_multirect_index rect_mode, bool enable)
  165. {
  166. struct sde_plane *psde;
  167. if (!plane)
  168. return;
  169. psde = to_sde_plane(plane);
  170. if (psde->pipe_hw->ops.set_src_split_order)
  171. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  172. rect_mode, enable);
  173. }
  174. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  175. {
  176. struct sde_plane *psde;
  177. struct sde_kms *sde_kms;
  178. struct msm_drm_private *priv;
  179. if (!plane || !plane->dev) {
  180. SDE_ERROR("invalid plane\n");
  181. return;
  182. }
  183. priv = plane->dev->dev_private;
  184. if (!priv || !priv->kms) {
  185. SDE_ERROR("invalid KMS reference\n");
  186. return;
  187. }
  188. sde_kms = to_sde_kms(priv->kms);
  189. psde = to_sde_plane(plane);
  190. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm, sde_kms->catalog);
  191. }
  192. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  193. struct drm_crtc *crtc,
  194. struct drm_framebuffer *fb)
  195. {
  196. struct sde_plane *psde;
  197. const struct sde_format *fmt = NULL;
  198. u32 frame_rate, qos_count, fps_index = 0, lut_index, creq_lut_index, ds_lut_index;
  199. struct sde_perf_cfg *perf;
  200. struct sde_plane_state *pstate;
  201. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  202. bool inline_rot = false, landscape = false;
  203. struct drm_display_mode *mode;
  204. u32 fl_require0 = 0;
  205. if (!plane || !fb) {
  206. SDE_ERROR("invalid arguments\n");
  207. return;
  208. }
  209. psde = to_sde_plane(plane);
  210. pstate = to_sde_plane_state(plane->state);
  211. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  212. SDE_ERROR("invalid arguments\n");
  213. return;
  214. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  215. return;
  216. }
  217. mode = &crtc->state->adjusted_mode;
  218. landscape = mode->hdisplay > mode->vdisplay ? true : false;
  219. frame_rate = drm_mode_vrefresh(&crtc->mode);
  220. perf = &psde->catalog->perf;
  221. qos_count = perf->qos_refresh_count;
  222. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  223. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  224. (fps_index == qos_count - 1))
  225. break;
  226. fps_index++;
  227. }
  228. if (psde->is_rt_pipe) {
  229. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  230. inline_rot = (pstate->rotation & DRM_MODE_ROTATE_90);
  231. if (inline_rot && SDE_IS_IN_ROT_RESTRICTED_FMT(psde->catalog, fmt))
  232. lut_index = SDE_QOS_LUT_USAGE_INLINE_RESTRICTED_FMTS;
  233. else if (inline_rot)
  234. lut_index = SDE_QOS_LUT_USAGE_INLINE;
  235. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  236. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  237. else
  238. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  239. } else {
  240. lut_index = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB ||
  241. psde->wb_usage_type == WB_USAGE_ROT) ?
  242. SDE_QOS_LUT_USAGE_OFFLINE_WB : SDE_QOS_LUT_USAGE_NRT;
  243. }
  244. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  245. if (psde->scaler3_cfg.enable)
  246. creq_lut_index += SDE_CREQ_LUT_TYPE_QSEED;
  247. creq_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_CREQ_LUT_TYPE_MAX);
  248. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[creq_lut_index];
  249. ds_lut_index = lut_index * SDE_DANGER_SAFE_LUT_TYPE_MAX;
  250. if (landscape) {
  251. if (psde->catalog->qos_target_time_ns && sde_crtc->line_time_in_ns)
  252. fl_require0 = psde->catalog->qos_target_time_ns /
  253. (sde_crtc->line_time_in_ns * 2);
  254. if (!fl_require0 || fl_require0 < 4.5)
  255. ds_lut_index += SDE_DANGER_SAFE_LUT_TYPE_LANDSCAPE;
  256. }
  257. ds_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_DANGER_SAFE_LUT_TYPE_MAX);
  258. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[ds_lut_index];
  259. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[ds_lut_index];
  260. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0,
  261. (fmt) ? fmt->fetch_mode : 0, psde->pipe_qos_cfg.danger_lut,
  262. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut);
  263. SDE_DEBUG("plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d lut[0x%x,0x%x 0x%llx] rt:%d type:%d\n",
  264. plane->base.id, psde->pipe - SSPP_VIG0,
  265. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  266. fmt ? fmt->fetch_mode : -1, psde->pipe_qos_cfg.danger_lut,
  267. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut,
  268. psde->is_rt_pipe, psde->wb_usage_type);
  269. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  270. }
  271. /**
  272. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  273. * @plane: Pointer to drm plane
  274. * @enable: true to enable QoS control
  275. * @flags: QoS control mode (enum sde_plane_qos)
  276. */
  277. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  278. bool enable, u32 flags)
  279. {
  280. struct sde_plane *psde;
  281. if (!plane) {
  282. SDE_ERROR("invalid arguments\n");
  283. return;
  284. }
  285. psde = to_sde_plane(plane);
  286. if (!psde->pipe_hw || !psde->pipe_sblk) {
  287. SDE_ERROR("invalid arguments\n");
  288. return;
  289. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  290. return;
  291. }
  292. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  293. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  294. psde->pipe_qos_cfg.danger_vblank =
  295. psde->pipe_sblk->danger_vblank;
  296. psde->pipe_qos_cfg.vblank_en = enable;
  297. }
  298. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  299. /* this feature overrules previous VBLANK_CTRL */
  300. psde->pipe_qos_cfg.vblank_en = false;
  301. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  302. psde->pipe_qos_cfg.danger_vblank = 0;
  303. }
  304. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  305. psde->pipe_qos_cfg.danger_safe_en = enable;
  306. if (!psde->is_rt_pipe) {
  307. psde->pipe_qos_cfg.vblank_en = false;
  308. psde->pipe_qos_cfg.danger_safe_en = false;
  309. }
  310. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  311. plane->base.id,
  312. psde->pipe - SSPP_VIG0,
  313. psde->pipe_qos_cfg.danger_safe_en,
  314. psde->pipe_qos_cfg.vblank_en,
  315. psde->pipe_qos_cfg.creq_vblank,
  316. psde->pipe_qos_cfg.danger_vblank,
  317. psde->is_rt_pipe);
  318. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  319. &psde->pipe_qos_cfg);
  320. }
  321. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  322. {
  323. struct sde_plane *psde;
  324. if (!plane)
  325. return;
  326. psde = to_sde_plane(plane);
  327. psde->revalidate = enable;
  328. }
  329. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  330. {
  331. struct sde_plane *psde;
  332. int rc;
  333. if (!plane) {
  334. SDE_ERROR("invalid arguments\n");
  335. return -EINVAL;
  336. }
  337. psde = to_sde_plane(plane);
  338. if (!psde->is_rt_pipe)
  339. goto end;
  340. rc = pm_runtime_resume_and_get(plane->dev->dev);
  341. if (rc < 0) {
  342. SDE_ERROR("failed to enable power resource %d\n", rc);
  343. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  344. return rc;
  345. }
  346. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  347. pm_runtime_put_sync(plane->dev->dev);
  348. end:
  349. return 0;
  350. }
  351. /**
  352. * _sde_plane_set_ot_limit - set OT limit for the given plane
  353. * @plane: Pointer to drm plane
  354. * @crtc: Pointer to drm crtc
  355. */
  356. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  357. struct drm_crtc *crtc)
  358. {
  359. struct sde_plane *psde;
  360. struct sde_vbif_set_ot_params ot_params;
  361. struct msm_drm_private *priv;
  362. struct sde_kms *sde_kms;
  363. if (!plane || !plane->dev || !crtc) {
  364. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  365. !plane, !crtc);
  366. return;
  367. }
  368. priv = plane->dev->dev_private;
  369. if (!priv || !priv->kms) {
  370. SDE_ERROR("invalid KMS reference\n");
  371. return;
  372. }
  373. sde_kms = to_sde_kms(priv->kms);
  374. psde = to_sde_plane(plane);
  375. if (!psde->pipe_hw) {
  376. SDE_ERROR("invalid pipe reference\n");
  377. return;
  378. }
  379. memset(&ot_params, 0, sizeof(ot_params));
  380. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  381. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  382. ot_params.width = psde->pipe_cfg.src_rect.w;
  383. ot_params.height = psde->pipe_cfg.src_rect.h;
  384. ot_params.is_wfd = ((psde->is_rt_pipe)
  385. || (psde->wb_usage_type == WB_USAGE_OFFLINE_WB)) ? false : true;
  386. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  387. ot_params.vbif_idx = VBIF_RT;
  388. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  389. ot_params.rd = true;
  390. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  391. }
  392. /**
  393. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  394. * @plane: Pointer to drm plane
  395. */
  396. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  397. {
  398. struct sde_plane *psde;
  399. struct sde_vbif_set_qos_params qos_params;
  400. struct msm_drm_private *priv;
  401. struct sde_kms *sde_kms;
  402. if (!plane || !plane->dev) {
  403. SDE_ERROR("invalid arguments\n");
  404. return;
  405. }
  406. priv = plane->dev->dev_private;
  407. if (!priv || !priv->kms) {
  408. SDE_ERROR("invalid KMS reference\n");
  409. return;
  410. }
  411. sde_kms = to_sde_kms(priv->kms);
  412. psde = to_sde_plane(plane);
  413. if (!psde->pipe_hw) {
  414. SDE_ERROR("invalid pipe reference\n");
  415. return;
  416. }
  417. if (psde->is_virtual)
  418. return;
  419. memset(&qos_params, 0, sizeof(qos_params));
  420. qos_params.vbif_idx = VBIF_RT;
  421. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  422. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  423. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  424. if (psde->is_rt_pipe)
  425. qos_params.client_type = VBIF_RT_CLIENT;
  426. else
  427. qos_params.client_type = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  428. VBIF_OFFLINE_WB_CLIENT : VBIF_NRT_CLIENT;
  429. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  430. plane->base.id, qos_params.num,
  431. qos_params.vbif_idx,
  432. qos_params.xin_id, qos_params.client_type,
  433. qos_params.clk_ctrl);
  434. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  435. }
  436. /**
  437. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  438. * @plane: Pointer to drm plane
  439. * @pstate: Pointer to sde plane state
  440. */
  441. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  442. struct sde_plane_state *pstate)
  443. {
  444. struct sde_plane *psde;
  445. struct sde_hw_pipe_ts_cfg cfg;
  446. struct msm_drm_private *priv;
  447. struct sde_kms *sde_kms;
  448. if (!plane || !plane->dev) {
  449. SDE_ERROR("invalid arguments");
  450. return;
  451. }
  452. priv = plane->dev->dev_private;
  453. if (!priv || !priv->kms) {
  454. SDE_ERROR("invalid KMS reference\n");
  455. return;
  456. }
  457. sde_kms = to_sde_kms(priv->kms);
  458. psde = to_sde_plane(plane);
  459. if (!psde->pipe_hw) {
  460. SDE_ERROR("invalid pipe reference\n");
  461. return;
  462. }
  463. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  464. return;
  465. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  466. memset(&cfg, 0, sizeof(cfg));
  467. cfg.size = sde_plane_get_property(pstate,
  468. PLANE_PROP_PREFILL_SIZE);
  469. cfg.time = sde_plane_get_property(pstate,
  470. PLANE_PROP_PREFILL_TIME);
  471. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  472. plane->base.id, cfg.size, cfg.time);
  473. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  474. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  475. pstate->multirect_index);
  476. }
  477. /* helper to update a state's input fence pointer from the property */
  478. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  479. struct sde_plane_state *pstate, uint64_t fd)
  480. {
  481. if (!psde || !pstate) {
  482. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  483. !psde, !pstate);
  484. return;
  485. }
  486. /* clear previous reference */
  487. if (pstate->input_fence)
  488. sde_sync_put(pstate->input_fence);
  489. /* get fence pointer for later */
  490. if (fd == 0)
  491. pstate->input_fence = NULL;
  492. else
  493. pstate->input_fence = sde_sync_get(fd);
  494. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  495. }
  496. void sde_plane_dump_input_fence(struct drm_plane *plane)
  497. {
  498. struct sde_plane *psde;
  499. struct sde_plane_state *pstate;
  500. void *input_fence;
  501. if (!plane) {
  502. SDE_ERROR("invalid plane\n");
  503. } else if (!plane->state) {
  504. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  505. } else {
  506. psde = to_sde_plane(plane);
  507. pstate = to_sde_plane_state(plane->state);
  508. input_fence = pstate->input_fence;
  509. if (input_fence)
  510. sde_fence_dump(input_fence);
  511. }
  512. }
  513. bool sde_plane_is_sw_fence_signaled(struct drm_plane *plane)
  514. {
  515. struct sde_plane *psde;
  516. struct sde_plane_state *pstate;
  517. struct dma_fence *fence;
  518. if (!plane) {
  519. SDE_ERROR("invalid plane\n");
  520. } else if (!plane->state) {
  521. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  522. } else {
  523. psde = to_sde_plane(plane);
  524. pstate = to_sde_plane_state(plane->state);
  525. if (pstate->input_fence) {
  526. fence = (struct dma_fence *)pstate->input_fence;
  527. return dma_fence_is_signaled(fence);
  528. }
  529. }
  530. return false;
  531. }
  532. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms, int *error_status)
  533. {
  534. struct sde_plane *psde;
  535. struct sde_plane_state *pstate;
  536. uint32_t prefix;
  537. void *input_fence;
  538. int ret = -EINVAL;
  539. signed long rc;
  540. if (!plane) {
  541. SDE_ERROR("invalid plane\n");
  542. } else if (!plane->state) {
  543. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  544. } else {
  545. psde = to_sde_plane(plane);
  546. pstate = to_sde_plane_state(plane->state);
  547. input_fence = pstate->input_fence;
  548. if (input_fence) {
  549. prefix = sde_sync_get_name_prefix(input_fence);
  550. rc = sde_sync_wait(input_fence, wait_ms, error_status);
  551. switch (rc) {
  552. case 0:
  553. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
  554. wait_ms, prefix, sde_plane_get_property(pstate,
  555. PLANE_PROP_INPUT_FENCE));
  556. sde_kms_timeline_status(plane->dev);
  557. ret = -ETIMEDOUT;
  558. break;
  559. case -ERESTARTSYS:
  560. SDE_ERROR_PLANE(psde,
  561. "%ums wait interrupted on %08X\n",
  562. wait_ms, prefix);
  563. psde->is_error = true;
  564. ret = -ERESTARTSYS;
  565. break;
  566. case -EINVAL:
  567. SDE_ERROR_PLANE(psde,
  568. "invalid fence param for %08X\n",
  569. prefix);
  570. psde->is_error = true;
  571. ret = -EINVAL;
  572. break;
  573. case -EBADF:
  574. SDE_INFO("plane%d spec fd signaled on bind failure fd %lld\n",
  575. plane->base.id,
  576. sde_plane_get_property(pstate, PLANE_PROP_INPUT_FENCE));
  577. ret = 0;
  578. break;
  579. default:
  580. SDE_DEBUG_PLANE(psde, "signaled\n");
  581. ret = 0;
  582. break;
  583. }
  584. if (ret)
  585. SDE_EVT32(DRMID(plane), -ret, prefix, SDE_EVTLOG_ERROR);
  586. else
  587. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  588. } else {
  589. ret = 0;
  590. }
  591. }
  592. return ret;
  593. }
  594. /**
  595. * _sde_plane_get_aspace: gets the address space based on the
  596. * fb_translation mode property
  597. */
  598. static int _sde_plane_get_aspace(
  599. struct sde_plane *psde,
  600. struct sde_plane_state *pstate,
  601. struct msm_gem_address_space **aspace)
  602. {
  603. struct sde_kms *kms;
  604. int mode;
  605. if (!psde || !pstate || !aspace) {
  606. SDE_ERROR("invalid parameters\n");
  607. return -EINVAL;
  608. }
  609. kms = _sde_plane_get_kms(&psde->base);
  610. if (!kms) {
  611. SDE_ERROR("invalid kms\n");
  612. return -EINVAL;
  613. }
  614. mode = sde_plane_get_property(pstate,
  615. PLANE_PROP_FB_TRANSLATION_MODE);
  616. switch (mode) {
  617. case SDE_DRM_FB_NON_SEC:
  618. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  619. if (!aspace)
  620. return -EINVAL;
  621. break;
  622. case SDE_DRM_FB_SEC:
  623. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  624. if (!aspace)
  625. return -EINVAL;
  626. break;
  627. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  628. case SDE_DRM_FB_SEC_DIR_TRANS:
  629. *aspace = NULL;
  630. break;
  631. default:
  632. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  633. return -EFAULT;
  634. }
  635. return 0;
  636. }
  637. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  638. struct sde_plane_state *pstate,
  639. struct sde_hw_pipe_cfg *pipe_cfg,
  640. struct drm_framebuffer *fb)
  641. {
  642. struct sde_plane *psde;
  643. struct msm_gem_address_space *aspace = NULL;
  644. int ret, mode;
  645. bool secure = false;
  646. if (!plane || !pstate || !pipe_cfg || !fb) {
  647. SDE_ERROR(
  648. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  649. !plane, !pstate, !pipe_cfg, !fb);
  650. return;
  651. }
  652. psde = to_sde_plane(plane);
  653. if (!psde->pipe_hw) {
  654. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  655. return;
  656. }
  657. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  658. if (ret) {
  659. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  660. return;
  661. }
  662. /*
  663. * framebuffer prepare is deferred for prepare_fb calls that
  664. * happen during the transition from secure to non-secure.
  665. * Handle the prepare at this point for such cases. This can be
  666. * expected for one or two frames during the transition.
  667. */
  668. if (aspace && pstate->defer_prepare_fb) {
  669. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  670. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  671. if (ret) {
  672. SDE_ERROR_PLANE(psde,
  673. "failed to prepare framebuffer %d\n", ret);
  674. return;
  675. }
  676. pstate->defer_prepare_fb = false;
  677. }
  678. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  679. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  680. secure = true;
  681. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  682. if (ret == -EAGAIN)
  683. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  684. else if (ret) {
  685. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  686. /*
  687. * Force solid fill color on error. This is to prevent
  688. * smmu faults during secure session transition.
  689. */
  690. psde->is_error = true;
  691. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  692. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  693. pipe_cfg->layout.width,
  694. pipe_cfg->layout.height,
  695. pipe_cfg->layout.plane_addr[0],
  696. pipe_cfg->layout.plane_size[0],
  697. pipe_cfg->layout.plane_addr[1],
  698. pipe_cfg->layout.plane_size[1],
  699. pipe_cfg->layout.plane_addr[2],
  700. pipe_cfg->layout.plane_size[2],
  701. pipe_cfg->layout.plane_addr[3],
  702. pipe_cfg->layout.plane_size[3],
  703. pstate->multirect_index,
  704. secure);
  705. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  706. pstate->multirect_index);
  707. }
  708. }
  709. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  710. struct sde_plane_state *pstate)
  711. {
  712. struct sde_hw_scaler3_cfg *cfg;
  713. int ret = 0;
  714. if (!psde || !pstate) {
  715. SDE_ERROR("invalid args\n");
  716. return -EINVAL;
  717. }
  718. cfg = &psde->scaler3_cfg;
  719. cfg->dir_lut = msm_property_get_blob(
  720. &psde->property_info,
  721. &pstate->property_state, &cfg->dir_len,
  722. PLANE_PROP_SCALER_LUT_ED);
  723. cfg->cir_lut = msm_property_get_blob(
  724. &psde->property_info,
  725. &pstate->property_state, &cfg->cir_len,
  726. PLANE_PROP_SCALER_LUT_CIR);
  727. cfg->sep_lut = msm_property_get_blob(
  728. &psde->property_info,
  729. &pstate->property_state, &cfg->sep_len,
  730. PLANE_PROP_SCALER_LUT_SEP);
  731. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  732. ret = -ENODATA;
  733. return ret;
  734. }
  735. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  736. struct sde_plane_state *pstate)
  737. {
  738. struct sde_hw_scaler3_cfg *cfg;
  739. cfg = &psde->scaler3_cfg;
  740. cfg->sep_lut = msm_property_get_blob(
  741. &psde->property_info,
  742. &pstate->property_state, &cfg->sep_len,
  743. PLANE_PROP_SCALER_LUT_SEP);
  744. return cfg->sep_lut ? 0 : -ENODATA;
  745. }
  746. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  747. struct sde_plane_state *pstate, const struct sde_format *fmt,
  748. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  749. {
  750. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  751. struct sde_hw_scaler3_cfg *scale_cfg;
  752. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  753. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  754. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  755. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  756. chroma_subsmpl_h, chroma_subsmpl_v);
  757. return;
  758. }
  759. scale_cfg = &psde->scaler3_cfg;
  760. src_w = psde->pipe_cfg.src_rect.w;
  761. src_h = psde->pipe_cfg.src_rect.h;
  762. dst_w = psde->pipe_cfg.dst_rect.w;
  763. dst_h = psde->pipe_cfg.dst_rect.h;
  764. memset(scale_cfg, 0, sizeof(*scale_cfg));
  765. memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  766. /*
  767. * For inline rotation cases, scaler config is post-rotation,
  768. * so swap the dimensions here. However, pixel extension will
  769. * need pre-rotation settings, this will be corrected below
  770. * when calculating pixel extension settings.
  771. */
  772. if (inline_rotation)
  773. swap(src_w, src_h);
  774. decimated = DECIMATED_DIMENSION(src_w,
  775. psde->pipe_cfg.horz_decimation);
  776. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  777. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  778. decimated = DECIMATED_DIMENSION(src_h,
  779. psde->pipe_cfg.vert_decimation);
  780. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  781. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  782. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  783. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  784. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  785. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  786. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  787. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  788. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  789. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  790. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  791. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  792. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  793. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  794. for (i = 0; i < SDE_MAX_PLANES; i++) {
  795. /*
  796. * For inline rotation cases with pre-downscaling enabled
  797. * set x pre-downscale value if required. Only x direction
  798. * is currently supported. Use src_h as values have been swapped
  799. * and x direction corresponds to height value.
  800. */
  801. src_h_pre_down = src_h;
  802. if (pre_down_supported && inline_rotation) {
  803. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  804. src_h_pre_down = src_h / 2;
  805. }
  806. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  807. psde->pipe_cfg.horz_decimation);
  808. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  809. psde->pipe_cfg.vert_decimation);
  810. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  811. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  812. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  813. }
  814. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  815. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  816. /* For pixel extension we need the pre-rotated orientation */
  817. if (inline_rotation) {
  818. psde->pixel_ext.num_ext_pxls_top[i] =
  819. scale_cfg->src_width[i];
  820. psde->pixel_ext.num_ext_pxls_left[i] =
  821. scale_cfg->src_height[i];
  822. } else {
  823. psde->pixel_ext.num_ext_pxls_top[i] =
  824. scale_cfg->src_height[i];
  825. psde->pixel_ext.num_ext_pxls_left[i] =
  826. scale_cfg->src_width[i];
  827. }
  828. }
  829. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  830. && (src_w == dst_w) && !inline_rotation) ||
  831. pstate->multirect_mode)
  832. return;
  833. SDE_DEBUG_PLANE(psde,
  834. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  835. src_w, src_h, dst_w, dst_h,
  836. chroma_subsmpl_v, chroma_subsmpl_h,
  837. fmt->base.pixel_format);
  838. scale_cfg->dst_width = dst_w;
  839. scale_cfg->dst_height = dst_h;
  840. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  841. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  842. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  843. scale_cfg->lut_flag = 0;
  844. scale_cfg->blend_cfg = 1;
  845. scale_cfg->enable = 1;
  846. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  847. }
  848. /**
  849. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  850. * @psde: Pointer to SDE plane object
  851. * @src: Source size
  852. * @dst: Destination size
  853. * @phase_steps: Pointer to output array for phase steps
  854. * @filter: Pointer to output array for filter type
  855. * @fmt: Pointer to format definition
  856. * @chroma_subsampling: Subsampling amount for chroma channel
  857. *
  858. * Returns: 0 on success
  859. */
  860. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  861. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  862. enum sde_hw_filter *filter, const struct sde_format *fmt,
  863. uint32_t chroma_subsampling)
  864. {
  865. if (!psde || !phase_steps || !filter || !fmt) {
  866. SDE_ERROR(
  867. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  868. !psde, !phase_steps, !filter, !fmt);
  869. return -EINVAL;
  870. }
  871. /* calculate phase steps, leave init phase as zero */
  872. phase_steps[SDE_SSPP_COMP_0] =
  873. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  874. phase_steps[SDE_SSPP_COMP_1_2] =
  875. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  876. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  877. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  878. /* calculate scaler config, if necessary */
  879. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  880. filter[SDE_SSPP_COMP_3] =
  881. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  882. SDE_SCALE_FILTER_PCMN;
  883. if (SDE_FORMAT_IS_YUV(fmt)) {
  884. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  885. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  886. } else {
  887. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  888. filter[SDE_SSPP_COMP_1_2] =
  889. SDE_SCALE_FILTER_NEAREST;
  890. }
  891. } else {
  892. /* disable scaler */
  893. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  894. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  895. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  896. }
  897. return 0;
  898. }
  899. /**
  900. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  901. * @psde: Pointer to SDE plane object
  902. * @src: Source size
  903. * @dst: Destination size
  904. * @decimated_src: Source size after decimation, if any
  905. * @phase_steps: Pointer to output array for phase steps
  906. * @out_src: Output array for pixel extension values
  907. * @out_edge1: Output array for pixel extension first edge
  908. * @out_edge2: Output array for pixel extension second edge
  909. * @filter: Pointer to array for filter type
  910. * @fmt: Pointer to format definition
  911. * @chroma_subsampling: Subsampling amount for chroma channel
  912. * @post_compare: Whether to chroma subsampled source size for comparisions
  913. */
  914. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  915. uint32_t src, uint32_t dst, uint32_t decimated_src,
  916. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  917. int *out_edge2, enum sde_hw_filter *filter,
  918. const struct sde_format *fmt, uint32_t chroma_subsampling,
  919. bool post_compare)
  920. {
  921. int64_t edge1, edge2, caf;
  922. uint32_t src_work;
  923. int i, tmp;
  924. if (psde && phase_steps && out_src && out_edge1 &&
  925. out_edge2 && filter && fmt) {
  926. /* handle CAF for YUV formats */
  927. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  928. caf = PHASE_STEP_UNIT_SCALE;
  929. else
  930. caf = 0;
  931. for (i = 0; i < SDE_MAX_PLANES; i++) {
  932. src_work = decimated_src;
  933. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  934. src_work /= chroma_subsampling;
  935. if (post_compare)
  936. src = src_work;
  937. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  938. /* unity */
  939. edge1 = 0;
  940. edge2 = 0;
  941. } else if (dst >= src) {
  942. /* upscale */
  943. edge1 = (1 << PHASE_RESIDUAL);
  944. edge1 -= caf;
  945. edge2 = (1 << PHASE_RESIDUAL);
  946. edge2 += (dst - 1) * *(phase_steps + i);
  947. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  948. edge2 += caf;
  949. edge2 = -(edge2);
  950. } else {
  951. /* downscale */
  952. edge1 = 0;
  953. edge2 = (dst - 1) * *(phase_steps + i);
  954. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  955. edge2 += *(phase_steps + i);
  956. edge2 = -(edge2);
  957. }
  958. /* only enable CAF for luma plane */
  959. caf = 0;
  960. /* populate output arrays */
  961. *(out_src + i) = src_work;
  962. /* edge updates taken from __pxl_extn_helper */
  963. if (edge1 >= 0) {
  964. tmp = (uint32_t)edge1;
  965. tmp >>= PHASE_STEP_SHIFT;
  966. *(out_edge1 + i) = -tmp;
  967. } else {
  968. tmp = (uint32_t)(-edge1);
  969. *(out_edge1 + i) =
  970. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  971. PHASE_STEP_SHIFT;
  972. }
  973. if (edge2 >= 0) {
  974. tmp = (uint32_t)edge2;
  975. tmp >>= PHASE_STEP_SHIFT;
  976. *(out_edge2 + i) = -tmp;
  977. } else {
  978. tmp = (uint32_t)(-edge2);
  979. *(out_edge2 + i) =
  980. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  981. PHASE_STEP_SHIFT;
  982. }
  983. }
  984. }
  985. }
  986. static inline void _sde_plane_setup_csc(struct sde_plane *psde, struct sde_plane_state *pstate)
  987. {
  988. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  989. {
  990. /* S15.16 format */
  991. 0x00012A00, 0x00000000, 0x00019880,
  992. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  993. 0x00012A00, 0x00020480, 0x00000000,
  994. },
  995. /* signed bias */
  996. { 0xfff0, 0xff80, 0xff80,},
  997. { 0x0, 0x0, 0x0,},
  998. /* unsigned clamp */
  999. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  1000. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  1001. };
  1002. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  1003. {
  1004. /* S15.16 format */
  1005. 0x00012A00, 0x00000000, 0x00019880,
  1006. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  1007. 0x00012A00, 0x00020480, 0x00000000,
  1008. },
  1009. /* signed bias */
  1010. { 0xffc0, 0xfe00, 0xfe00,},
  1011. { 0x0, 0x0, 0x0,},
  1012. /* unsigned clamp */
  1013. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  1014. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  1015. };
  1016. if (!psde || !pstate) {
  1017. SDE_ERROR("invalid plane\n");
  1018. return;
  1019. }
  1020. /* revert to kernel default if override not available */
  1021. if (pstate->csc_usr_ptr)
  1022. pstate->csc_ptr = pstate->csc_usr_ptr;
  1023. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  1024. pstate->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  1025. else
  1026. pstate->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  1027. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  1028. pstate->csc_ptr->csc_mv[0],
  1029. pstate->csc_ptr->csc_mv[1],
  1030. pstate->csc_ptr->csc_mv[2]);
  1031. }
  1032. static void sde_color_process_plane_setup(struct drm_plane *plane)
  1033. {
  1034. struct sde_plane *psde;
  1035. struct sde_plane_state *pstate;
  1036. uint32_t hue, saturation, value, contrast;
  1037. struct drm_msm_memcol *memcol = NULL;
  1038. struct drm_msm_3d_gamut *vig_gamut = NULL;
  1039. struct drm_msm_igc_lut *igc = NULL;
  1040. struct drm_msm_pgc_lut *gc = NULL;
  1041. size_t memcol_sz = 0, size = 0;
  1042. struct sde_hw_cp_cfg hw_cfg = {};
  1043. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1044. bool fp16_igc, fp16_unmult, ucsc_unmult, ucsc_alpha_dither;
  1045. int ucsc_gc, ucsc_igc;
  1046. struct drm_msm_fp16_gc *fp16_gc = NULL;
  1047. struct drm_msm_fp16_csc *fp16_csc = NULL;
  1048. struct drm_msm_ucsc_csc *ucsc_csc = NULL;
  1049. psde = to_sde_plane(plane);
  1050. pstate = to_sde_plane_state(plane->state);
  1051. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1052. if (psde->pipe_hw->ops.setup_pa_hue)
  1053. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1054. saturation = (uint32_t) sde_plane_get_property(pstate,
  1055. PLANE_PROP_SATURATION_ADJUST);
  1056. if (psde->pipe_hw->ops.setup_pa_sat)
  1057. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1058. value = (uint32_t) sde_plane_get_property(pstate,
  1059. PLANE_PROP_VALUE_ADJUST);
  1060. if (psde->pipe_hw->ops.setup_pa_val)
  1061. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1062. contrast = (uint32_t) sde_plane_get_property(pstate,
  1063. PLANE_PROP_CONTRAST_ADJUST);
  1064. if (psde->pipe_hw->ops.setup_pa_cont)
  1065. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1066. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1067. /* Skin memory color setup */
  1068. memcol = msm_property_get_blob(&psde->property_info,
  1069. &pstate->property_state,
  1070. &memcol_sz,
  1071. PLANE_PROP_SKIN_COLOR);
  1072. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1073. MEMCOLOR_SKIN, memcol);
  1074. /* Sky memory color setup */
  1075. memcol = msm_property_get_blob(&psde->property_info,
  1076. &pstate->property_state,
  1077. &memcol_sz,
  1078. PLANE_PROP_SKY_COLOR);
  1079. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1080. MEMCOLOR_SKY, memcol);
  1081. /* Foliage memory color setup */
  1082. memcol = msm_property_get_blob(&psde->property_info,
  1083. &pstate->property_state,
  1084. &memcol_sz,
  1085. PLANE_PROP_FOLIAGE_COLOR);
  1086. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1087. MEMCOLOR_FOLIAGE, memcol);
  1088. }
  1089. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1090. psde->pipe_hw->ops.setup_vig_gamut) {
  1091. vig_gamut = msm_property_get_blob(&psde->property_info,
  1092. &pstate->property_state,
  1093. &size,
  1094. PLANE_PROP_VIG_GAMUT);
  1095. hw_cfg.last_feature = 0;
  1096. hw_cfg.ctl = ctl;
  1097. hw_cfg.len = size;
  1098. hw_cfg.payload = vig_gamut;
  1099. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1100. }
  1101. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1102. psde->pipe_hw->ops.setup_vig_igc) {
  1103. igc = msm_property_get_blob(&psde->property_info,
  1104. &pstate->property_state,
  1105. &size,
  1106. PLANE_PROP_VIG_IGC);
  1107. hw_cfg.last_feature = 0;
  1108. hw_cfg.ctl = ctl;
  1109. hw_cfg.len = size;
  1110. hw_cfg.payload = igc;
  1111. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1112. }
  1113. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1114. psde->pipe_hw->ops.setup_dma_igc) {
  1115. igc = msm_property_get_blob(&psde->property_info,
  1116. &pstate->property_state,
  1117. &size,
  1118. PLANE_PROP_DMA_IGC);
  1119. hw_cfg.last_feature = 0;
  1120. hw_cfg.ctl = ctl;
  1121. hw_cfg.len = size;
  1122. hw_cfg.payload = igc;
  1123. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1124. pstate->multirect_index);
  1125. }
  1126. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1127. psde->pipe_hw->ops.setup_dma_gc) {
  1128. gc = msm_property_get_blob(&psde->property_info,
  1129. &pstate->property_state,
  1130. &size,
  1131. PLANE_PROP_DMA_GC);
  1132. hw_cfg.last_feature = 0;
  1133. hw_cfg.ctl = ctl;
  1134. hw_cfg.len = size;
  1135. hw_cfg.payload = gc;
  1136. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1137. pstate->multirect_index);
  1138. }
  1139. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1140. psde->pipe_hw->ops.setup_fp16_igc) {
  1141. fp16_igc = !!sde_plane_get_property(pstate,
  1142. PLANE_PROP_FP16_IGC);
  1143. hw_cfg.last_feature = 0;
  1144. hw_cfg.ctl = ctl;
  1145. hw_cfg.len = sizeof(bool);
  1146. hw_cfg.payload = &fp16_igc;
  1147. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1148. pstate->multirect_index, &hw_cfg);
  1149. }
  1150. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1151. psde->pipe_hw->ops.setup_fp16_gc) {
  1152. fp16_gc = msm_property_get_blob(&psde->property_info,
  1153. &pstate->property_state,
  1154. &size,
  1155. PLANE_PROP_FP16_GC);
  1156. hw_cfg.last_feature = 0;
  1157. hw_cfg.ctl = ctl;
  1158. hw_cfg.len = size;
  1159. hw_cfg.payload = fp16_gc;
  1160. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1161. pstate->multirect_index, &hw_cfg);
  1162. }
  1163. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1164. psde->pipe_hw->ops.setup_fp16_csc) {
  1165. fp16_csc = msm_property_get_blob(&psde->property_info,
  1166. &pstate->property_state,
  1167. &size,
  1168. PLANE_PROP_FP16_CSC);
  1169. hw_cfg.last_feature = 0;
  1170. hw_cfg.ctl = ctl;
  1171. hw_cfg.len = size;
  1172. hw_cfg.payload = fp16_csc;
  1173. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1174. pstate->multirect_index, &hw_cfg);
  1175. }
  1176. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1177. psde->pipe_hw->ops.setup_fp16_unmult) {
  1178. fp16_unmult = !!sde_plane_get_property(pstate,
  1179. PLANE_PROP_FP16_UNMULT);
  1180. hw_cfg.last_feature = 0;
  1181. hw_cfg.ctl = ctl;
  1182. hw_cfg.len = sizeof(bool);
  1183. hw_cfg.payload = &fp16_unmult;
  1184. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1185. pstate->multirect_index, &hw_cfg);
  1186. }
  1187. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_IGC &&
  1188. psde->pipe_hw->ops.setup_ucsc_igc) {
  1189. ucsc_igc = sde_plane_get_property(pstate,
  1190. PLANE_PROP_UCSC_IGC);
  1191. hw_cfg.last_feature = 0;
  1192. hw_cfg.ctl = ctl;
  1193. hw_cfg.len = sizeof(int);
  1194. hw_cfg.payload = &ucsc_igc;
  1195. psde->pipe_hw->ops.setup_ucsc_igc(psde->pipe_hw,
  1196. pstate->multirect_index, &hw_cfg);
  1197. }
  1198. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_GC &&
  1199. psde->pipe_hw->ops.setup_ucsc_gc) {
  1200. ucsc_gc = sde_plane_get_property(pstate,
  1201. PLANE_PROP_UCSC_GC);
  1202. hw_cfg.last_feature = 0;
  1203. hw_cfg.ctl = ctl;
  1204. hw_cfg.len = sizeof(int);
  1205. hw_cfg.payload = &ucsc_gc;
  1206. psde->pipe_hw->ops.setup_ucsc_gc(psde->pipe_hw,
  1207. pstate->multirect_index, &hw_cfg);
  1208. }
  1209. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_CSC &&
  1210. psde->pipe_hw->ops.setup_ucsc_csc) {
  1211. ucsc_csc = msm_property_get_blob(&psde->property_info,
  1212. &pstate->property_state,
  1213. &size,
  1214. PLANE_PROP_UCSC_CSC);
  1215. hw_cfg.last_feature = 0;
  1216. hw_cfg.ctl = ctl;
  1217. hw_cfg.len = size;
  1218. hw_cfg.payload = ucsc_csc;
  1219. psde->pipe_hw->ops.setup_ucsc_csc(psde->pipe_hw,
  1220. pstate->multirect_index, &hw_cfg);
  1221. }
  1222. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_UNMULT &&
  1223. psde->pipe_hw->ops.setup_ucsc_unmult) {
  1224. ucsc_unmult = !!sde_plane_get_property(pstate,
  1225. PLANE_PROP_UCSC_UNMULT);
  1226. hw_cfg.last_feature = 0;
  1227. hw_cfg.ctl = ctl;
  1228. hw_cfg.len = sizeof(bool);
  1229. hw_cfg.payload = &ucsc_unmult;
  1230. psde->pipe_hw->ops.setup_ucsc_unmult(psde->pipe_hw,
  1231. pstate->multirect_index, &hw_cfg);
  1232. }
  1233. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_ALPHA_DITHER &&
  1234. psde->pipe_hw->ops.setup_ucsc_alpha_dither) {
  1235. ucsc_alpha_dither = !!sde_plane_get_property(pstate,
  1236. PLANE_PROP_UCSC_ALPHA_DITHER);
  1237. hw_cfg.last_feature = 0;
  1238. hw_cfg.ctl = ctl;
  1239. hw_cfg.len = sizeof(bool);
  1240. hw_cfg.payload = &ucsc_alpha_dither;
  1241. psde->pipe_hw->ops.setup_ucsc_alpha_dither(psde->pipe_hw,
  1242. pstate->multirect_index, &hw_cfg);
  1243. }
  1244. }
  1245. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1246. struct sde_plane_state *pstate,
  1247. const struct sde_format *fmt, bool color_fill)
  1248. {
  1249. struct sde_hw_pixel_ext *pe;
  1250. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1251. const struct drm_format_info *info = NULL;
  1252. if (!psde || !fmt || !pstate) {
  1253. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1254. !psde, !fmt, !pstate);
  1255. return;
  1256. }
  1257. memcpy(&psde->scaler3_cfg, &pstate->scaler3_cfg,
  1258. sizeof(psde->scaler3_cfg));
  1259. memcpy(&psde->pixel_ext, &pstate->pixel_ext,
  1260. sizeof(psde->pixel_ext));
  1261. info = drm_format_info(fmt->base.pixel_format);
  1262. pe = &psde->pixel_ext;
  1263. psde->pipe_cfg.horz_decimation =
  1264. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1265. psde->pipe_cfg.vert_decimation =
  1266. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1267. /* don't chroma subsample if decimating */
  1268. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1269. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1270. /* update scaler */
  1271. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1272. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1273. int rc = -EINVAL;
  1274. if (!color_fill && !psde->debugfs_default_scale)
  1275. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1276. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1277. _sde_plane_setup_scaler3_lut(psde, pstate);
  1278. if (rc || pstate->scaler_check_state !=
  1279. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1280. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1281. pstate->scaler_check_state,
  1282. psde->debugfs_default_scale, rc,
  1283. psde->pipe_cfg.src_rect.w,
  1284. psde->pipe_cfg.src_rect.h,
  1285. psde->pipe_cfg.dst_rect.w,
  1286. psde->pipe_cfg.dst_rect.h,
  1287. pstate->multirect_mode);
  1288. /* calculate default config for QSEED3 */
  1289. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1290. chroma_subsmpl_h, chroma_subsmpl_v);
  1291. }
  1292. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1293. color_fill || psde->debugfs_default_scale) {
  1294. uint32_t deci_dim, i;
  1295. /* calculate default configuration for QSEED2 */
  1296. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1297. SDE_DEBUG_PLANE(psde, "default config\n");
  1298. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1299. psde->pipe_cfg.horz_decimation);
  1300. _sde_plane_setup_scaler2(psde,
  1301. deci_dim,
  1302. psde->pipe_cfg.dst_rect.w,
  1303. pe->phase_step_x,
  1304. pe->horz_filter, fmt, chroma_subsmpl_h);
  1305. if (SDE_FORMAT_IS_YUV(fmt))
  1306. deci_dim &= ~0x1;
  1307. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1308. psde->pipe_cfg.dst_rect.w, deci_dim,
  1309. pe->phase_step_x,
  1310. pe->roi_w,
  1311. pe->num_ext_pxls_left,
  1312. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1313. chroma_subsmpl_h, 0);
  1314. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1315. psde->pipe_cfg.vert_decimation);
  1316. _sde_plane_setup_scaler2(psde,
  1317. deci_dim,
  1318. psde->pipe_cfg.dst_rect.h,
  1319. pe->phase_step_y,
  1320. pe->vert_filter, fmt, chroma_subsmpl_v);
  1321. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1322. psde->pipe_cfg.dst_rect.h, deci_dim,
  1323. pe->phase_step_y,
  1324. pe->roi_h,
  1325. pe->num_ext_pxls_top,
  1326. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1327. chroma_subsmpl_v, 1);
  1328. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1329. if (pe->num_ext_pxls_left[i] >= 0)
  1330. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1331. else
  1332. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1333. if (pe->num_ext_pxls_right[i] >= 0)
  1334. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1335. else
  1336. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1337. if (pe->num_ext_pxls_top[i] >= 0)
  1338. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1339. else
  1340. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1341. if (pe->num_ext_pxls_btm[i] >= 0)
  1342. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1343. else
  1344. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1345. }
  1346. }
  1347. if (psde->pipe_hw->ops.setup_pre_downscale)
  1348. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1349. &pstate->pre_down);
  1350. }
  1351. /**
  1352. * _sde_plane_color_fill - enables color fill on plane
  1353. * @psde: Pointer to SDE plane object
  1354. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1355. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1356. * Returns: 0 on success
  1357. */
  1358. static int _sde_plane_color_fill(struct sde_plane *psde,
  1359. uint32_t color, uint32_t alpha)
  1360. {
  1361. const struct sde_format *fmt;
  1362. const struct drm_plane *plane;
  1363. struct sde_plane_state *pstate;
  1364. bool blend_enable = true;
  1365. if (!psde || !psde->base.state) {
  1366. SDE_ERROR("invalid plane\n");
  1367. return -EINVAL;
  1368. }
  1369. if (!psde->pipe_hw) {
  1370. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1371. return -EINVAL;
  1372. }
  1373. plane = &psde->base;
  1374. pstate = to_sde_plane_state(plane->state);
  1375. SDE_DEBUG_PLANE(psde, "\n");
  1376. /*
  1377. * select fill format to match user property expectation,
  1378. * h/w only supports RGB variants
  1379. */
  1380. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1381. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1382. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1383. /* update sspp */
  1384. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1385. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1386. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1387. pstate->multirect_index);
  1388. /* override scaler/decimation if solid fill */
  1389. psde->pipe_cfg.src_rect.x = 0;
  1390. psde->pipe_cfg.src_rect.y = 0;
  1391. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1392. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1393. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1394. if (psde->pipe_hw->ops.setup_format)
  1395. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1396. fmt, blend_enable,
  1397. SDE_SSPP_SOLID_FILL,
  1398. pstate->multirect_index);
  1399. if (psde->pipe_hw->ops.setup_rects)
  1400. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1401. &psde->pipe_cfg,
  1402. pstate->multirect_index);
  1403. if (psde->pipe_hw->ops.setup_pe)
  1404. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1405. &psde->pixel_ext);
  1406. if (psde->pipe_hw->ops.setup_scaler &&
  1407. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1408. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1409. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1410. &psde->pipe_cfg, &psde->pixel_ext,
  1411. &psde->scaler3_cfg);
  1412. }
  1413. }
  1414. return 0;
  1415. }
  1416. /**
  1417. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1418. * @plane: Pointer to drm plane
  1419. * @state: Pointer to drm plane state to be validated
  1420. * return: 0 if success; error code otherwise
  1421. */
  1422. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1423. struct drm_plane_state *state)
  1424. {
  1425. struct sde_plane *psde;
  1426. struct sde_plane_state *pstate, *old_pstate;
  1427. int ret = 0;
  1428. u32 rotation;
  1429. if (!plane || !state) {
  1430. SDE_ERROR("invalid plane/state\n");
  1431. return -EINVAL;
  1432. }
  1433. psde = to_sde_plane(plane);
  1434. pstate = to_sde_plane_state(state);
  1435. old_pstate = to_sde_plane_state(plane->state);
  1436. /* check inline rotation and simplify the transform */
  1437. rotation = drm_rotation_simplify(
  1438. state->rotation,
  1439. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1440. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1441. if ((rotation & DRM_MODE_ROTATE_180) ||
  1442. (rotation & DRM_MODE_ROTATE_270)) {
  1443. SDE_ERROR_PLANE(psde,
  1444. "invalid rotation transform must be simplified 0x%x\n",
  1445. rotation);
  1446. ret = -EINVAL;
  1447. goto exit;
  1448. }
  1449. if (rotation & DRM_MODE_ROTATE_90) {
  1450. struct msm_drm_private *priv = plane->dev->dev_private;
  1451. struct sde_kms *sde_kms;
  1452. const struct msm_format *msm_fmt;
  1453. const struct sde_format *fmt;
  1454. struct sde_rect src;
  1455. bool q16_data = true;
  1456. POPULATE_RECT(&src, state->src_x, state->src_y,
  1457. state->src_w, state->src_h, q16_data);
  1458. /*
  1459. * DRM framework expects rotation flag in counter-clockwise
  1460. * direction and the HW expects in clockwise direction.
  1461. * Flip the flags to match with HW.
  1462. */
  1463. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1464. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1465. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1466. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1467. !psde->pipe_sblk->in_rot_maxheight ||
  1468. !psde->pipe_sblk->in_rot_format_list ||
  1469. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1470. SDE_ERROR_PLANE(psde,
  1471. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1472. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1473. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1474. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1475. !psde->pipe_sblk->in_rot_format_list,
  1476. !psde->pipe_sblk->in_rot_maxheight,
  1477. psde->features);
  1478. ret = -EINVAL;
  1479. goto exit;
  1480. }
  1481. /* check for valid height */
  1482. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1483. SDE_ERROR_PLANE(psde,
  1484. "invalid height for inline rot:%d max:%d\n",
  1485. src.h, psde->pipe_sblk->in_rot_maxheight);
  1486. ret = -EINVAL;
  1487. goto exit;
  1488. }
  1489. if (!sde_plane_enabled(state))
  1490. goto exit;
  1491. /* check for valid formats supported by inline rot */
  1492. sde_kms = to_sde_kms(priv->kms);
  1493. msm_fmt = msm_framebuffer_format(state->fb);
  1494. fmt = to_sde_format(msm_fmt);
  1495. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1496. psde->pipe_sblk->in_rot_format_list);
  1497. if (ret) {
  1498. SDE_ERROR_PLANE(psde,
  1499. "fmt:%d mode:%d unpack:%d not found within the list!\n",
  1500. (fmt) ? fmt->base.pixel_format : 0,
  1501. (fmt) ? fmt->fetch_mode : 0,
  1502. (fmt) ? fmt->unpack_tight : 0);
  1503. }
  1504. }
  1505. exit:
  1506. pstate->rotation = rotation;
  1507. return ret;
  1508. }
  1509. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1510. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1511. {
  1512. struct sde_plane *psde;
  1513. struct msm_drm_private *priv;
  1514. struct sde_vbif_set_xin_halt_params halt_params;
  1515. if (!plane || !plane->dev) {
  1516. SDE_ERROR("invalid arguments\n");
  1517. return false;
  1518. }
  1519. psde = to_sde_plane(plane);
  1520. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1521. SDE_ERROR("invalid pipe reference\n");
  1522. return false;
  1523. }
  1524. priv = plane->dev->dev_private;
  1525. if (!priv || !priv->kms) {
  1526. SDE_ERROR("invalid KMS reference\n");
  1527. return false;
  1528. }
  1529. memset(&halt_params, 0, sizeof(halt_params));
  1530. halt_params.vbif_idx = VBIF_RT;
  1531. halt_params.xin_id = xin_id;
  1532. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1533. halt_params.forced_on = halt_forced_clk;
  1534. halt_params.enable = enable;
  1535. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1536. }
  1537. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1538. {
  1539. struct sde_plane *psde;
  1540. if (!plane) {
  1541. SDE_ERROR("invalid plane\n");
  1542. return;
  1543. }
  1544. psde = to_sde_plane(plane);
  1545. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1546. SDE_ERROR("invalid pipe reference\n");
  1547. return;
  1548. }
  1549. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1550. psde->xin_halt_forced_clk =
  1551. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1552. psde->xin_halt_forced_clk, enable);
  1553. }
  1554. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1555. struct drm_crtc *crtc)
  1556. {
  1557. struct sde_plane *psde;
  1558. if (!plane || !crtc) {
  1559. SDE_ERROR("invalid plane/crtc\n");
  1560. return;
  1561. }
  1562. psde = to_sde_plane(plane);
  1563. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1564. return;
  1565. /* do all VBIF programming for the sec-ui allowed SSPP */
  1566. _sde_plane_set_qos_remap(plane);
  1567. _sde_plane_set_ot_limit(plane, crtc);
  1568. }
  1569. /**
  1570. * sde_plane_rot_install_properties - install plane rotator properties
  1571. * @plane: Pointer to drm plane
  1572. * @catalog: Pointer to mdss configuration
  1573. * return: none
  1574. */
  1575. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1576. struct sde_mdss_cfg *catalog)
  1577. {
  1578. struct sde_plane *psde = to_sde_plane(plane);
  1579. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1580. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1581. int ret = 0;
  1582. if (!plane || !psde) {
  1583. SDE_ERROR("invalid plane\n");
  1584. return;
  1585. } else if (!catalog) {
  1586. SDE_ERROR("invalid catalog\n");
  1587. return;
  1588. }
  1589. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1590. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1591. ret = drm_plane_create_rotation_property(plane,
  1592. DRM_MODE_ROTATE_0, supported_rotations);
  1593. if (ret) {
  1594. DRM_ERROR("create rotation property failed: %d\n", ret);
  1595. return;
  1596. }
  1597. }
  1598. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1599. {
  1600. struct sde_plane_state *pstate;
  1601. if (!drm_state)
  1602. return;
  1603. pstate = to_sde_plane_state(drm_state);
  1604. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1605. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1606. }
  1607. /**
  1608. * multi_rect validate API allows to validate only R0 and R1 RECT
  1609. * passing for each plane. Client of this API must not pass multiple
  1610. * plane which are not sharing same XIN client. Such calls will fail
  1611. * even though kernel client is passing valid multirect configuration.
  1612. */
  1613. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1614. {
  1615. struct sde_plane_state *pstate[R_MAX];
  1616. const struct drm_plane_state *drm_state[R_MAX];
  1617. struct sde_rect src[R_MAX], dst[R_MAX];
  1618. struct sde_plane *sde_plane[R_MAX];
  1619. const struct sde_format *fmt[R_MAX];
  1620. int xin_id[R_MAX];
  1621. bool q16_data = true;
  1622. int i, j, buffer_lines, width_threshold[R_MAX];
  1623. unsigned int max_tile_height = 1;
  1624. bool parallel_fetch_qualified = true;
  1625. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1626. const struct msm_format *msm_fmt;
  1627. bool const_alpha_enable = true;
  1628. for (i = 0; i < R_MAX; i++) {
  1629. drm_state[i] = i ? plane->r1 : plane->r0;
  1630. if (!drm_state[i]) {
  1631. SDE_ERROR("drm plane state is NULL\n");
  1632. return -EINVAL;
  1633. }
  1634. pstate[i] = to_sde_plane_state(drm_state[i]);
  1635. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1636. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1637. for (j = 0; j < i; j++) {
  1638. if (xin_id[i] != xin_id[j]) {
  1639. SDE_ERROR_PLANE(sde_plane[i],
  1640. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1641. j, xin_id[j], i, xin_id[i]);
  1642. return -EINVAL;
  1643. }
  1644. }
  1645. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1646. if (!msm_fmt) {
  1647. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1648. return -EINVAL;
  1649. }
  1650. fmt[i] = to_sde_format(msm_fmt);
  1651. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1652. (fmt[i]->tile_height > max_tile_height))
  1653. max_tile_height = fmt[i]->tile_height;
  1654. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1655. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1656. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1657. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1658. drm_state[i]->crtc_h, !q16_data);
  1659. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1660. SDE_ERROR_PLANE(sde_plane[i],
  1661. "scaling is not supported in multirect mode\n");
  1662. return -EINVAL;
  1663. }
  1664. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1665. SDE_ERROR_PLANE(sde_plane[i],
  1666. "inline rotation is not supported in mulirect mode\n");
  1667. return -EINVAL;
  1668. }
  1669. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1670. SDE_ERROR_PLANE(sde_plane[i],
  1671. "Unsupported format for multirect mode\n");
  1672. return -EINVAL;
  1673. }
  1674. /**
  1675. * SSPP PD_MEM is split half - one for each RECT.
  1676. * Tiled formats need 5 lines of buffering while fetching
  1677. * whereas linear formats need only 2 lines.
  1678. * So we cannot support more than half of the supported SSPP
  1679. * width for tiled formats.
  1680. */
  1681. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1682. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1683. width_threshold[i] /= 2;
  1684. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1685. parallel_fetch_qualified = false;
  1686. if (sde_plane[i]->is_virtual)
  1687. mode = sde_plane_get_property(pstate[i],
  1688. PLANE_PROP_MULTIRECT_MODE);
  1689. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1690. const_alpha_enable = false;
  1691. }
  1692. buffer_lines = 2 * max_tile_height;
  1693. /**
  1694. * fallback to driver mode selection logic if client is using
  1695. * multirect plane without setting property.
  1696. *
  1697. * validate multirect mode configuration based on rectangle
  1698. */
  1699. switch (mode) {
  1700. case SDE_SSPP_MULTIRECT_NONE:
  1701. if (parallel_fetch_qualified)
  1702. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1703. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1704. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1705. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1706. else
  1707. SDE_ERROR(
  1708. "planes(%d - %d) multirect mode selection fail\n",
  1709. drm_state[R0]->plane->base.id,
  1710. drm_state[R1]->plane->base.id);
  1711. break;
  1712. case SDE_SSPP_MULTIRECT_PARALLEL:
  1713. if (!parallel_fetch_qualified) {
  1714. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1715. drm_state[R0]->plane->base.id,
  1716. width_threshold[R0], src[R0].w);
  1717. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1718. drm_state[R1]->plane->base.id,
  1719. width_threshold[R1], src[R1].w);
  1720. SDE_ERROR("parallel fetch not qualified\n");
  1721. mode = SDE_SSPP_MULTIRECT_NONE;
  1722. }
  1723. break;
  1724. case SDE_SSPP_MULTIRECT_TIME_MX:
  1725. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1726. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1727. SDE_ERROR(
  1728. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1729. buffer_lines, drm_state[R0]->plane->base.id,
  1730. dst[R0].y, dst[R0].h);
  1731. SDE_ERROR(
  1732. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1733. buffer_lines, drm_state[R1]->plane->base.id,
  1734. dst[R1].y, dst[R1].h);
  1735. SDE_ERROR("time multiplexed fetch not qualified\n");
  1736. mode = SDE_SSPP_MULTIRECT_NONE;
  1737. }
  1738. break;
  1739. default:
  1740. SDE_ERROR("bad mode:%d selection\n", mode);
  1741. mode = SDE_SSPP_MULTIRECT_NONE;
  1742. break;
  1743. }
  1744. for (i = 0; i < R_MAX; i++) {
  1745. pstate[i]->multirect_mode = mode;
  1746. pstate[i]->const_alpha_en = const_alpha_enable;
  1747. }
  1748. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1749. return -EINVAL;
  1750. if (sde_plane[R0]->is_virtual) {
  1751. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1752. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1753. } else {
  1754. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1755. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1756. }
  1757. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1758. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1759. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1760. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1761. return 0;
  1762. }
  1763. /**
  1764. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1765. * @plane: Pointer to drm plane structure
  1766. * @ctl: Pointer to hardware control driver
  1767. * @set: set if true else clear
  1768. */
  1769. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1770. bool set)
  1771. {
  1772. if (!plane || !ctl) {
  1773. SDE_ERROR("invalid parameters\n");
  1774. return;
  1775. }
  1776. if (!ctl->ops.update_bitmask_sspp) {
  1777. SDE_ERROR("invalid ops\n");
  1778. return;
  1779. }
  1780. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1781. }
  1782. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1783. struct drm_plane_state *new_state)
  1784. {
  1785. struct drm_framebuffer *fb = new_state->fb;
  1786. struct sde_plane *psde = to_sde_plane(plane);
  1787. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1788. struct sde_hw_fmt_layout layout;
  1789. struct msm_gem_address_space *aspace;
  1790. int ret, mode;
  1791. if (!fb)
  1792. return 0;
  1793. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1794. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1795. if (ret) {
  1796. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1797. return ret;
  1798. }
  1799. /* cache aspace */
  1800. pstate->aspace = aspace;
  1801. /*
  1802. * when transitioning from secure to non-secure,
  1803. * plane->prepare_fb happens before the commit. In such case,
  1804. * defer the prepare_fb and handled it late, during the commit
  1805. * after attaching the domains as part of the transition
  1806. */
  1807. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1808. true : false;
  1809. if (pstate->defer_prepare_fb) {
  1810. SDE_EVT32(DRMID(plane), psde->pipe);
  1811. SDE_DEBUG_PLANE(psde,
  1812. "domain not attached, prepare_fb handled later\n");
  1813. return 0;
  1814. }
  1815. if (pstate->aspace && fb) {
  1816. ret = msm_framebuffer_prepare(fb,
  1817. pstate->aspace);
  1818. if (ret) {
  1819. SDE_ERROR("failed to prepare framebuffer fb:%d plane:%d pipe:%d ret:%d\n",
  1820. fb->base.id, plane->base.id, psde->pipe, ret);
  1821. SDE_EVT32(fb->base.id, plane->base.id, psde->pipe, ret, SDE_EVTLOG_ERROR);
  1822. return ret;
  1823. }
  1824. }
  1825. /*
  1826. * Avoid mapping during the validate phase for S2-only buffer & CSF-2.5.
  1827. * _sde_plane_set_scanout can handle the mapping after the scm_call during commit.
  1828. */
  1829. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  1830. if (mode != SDE_DRM_FB_SEC_DIR_TRANS) {
  1831. /* validate framebuffer layout before commit */
  1832. ret = sde_format_populate_layout(pstate->aspace, fb, &layout);
  1833. if (ret) {
  1834. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1835. return ret;
  1836. }
  1837. } else {
  1838. SDE_DEBUG("deferring dma-buf mapping to commit phase\n");
  1839. SDE_EVT32(DRMID(plane), fb->base.id, mode);
  1840. }
  1841. return 0;
  1842. }
  1843. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1844. struct drm_plane_state *old_state)
  1845. {
  1846. struct sde_plane *psde = to_sde_plane(plane);
  1847. struct sde_plane_state *old_pstate;
  1848. if (!old_state || !old_state->fb || !plane)
  1849. return;
  1850. old_pstate = to_sde_plane_state(old_state);
  1851. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1852. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1853. }
  1854. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1855. struct drm_plane_state *state,
  1856. struct drm_plane_state *old_state)
  1857. {
  1858. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1859. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1860. struct drm_framebuffer *fb, *old_fb;
  1861. /* no need to check it again */
  1862. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1863. return;
  1864. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1865. || psde->is_error) {
  1866. SDE_DEBUG_PLANE(psde,
  1867. "enabling/disabling full modeset required\n");
  1868. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1869. } else if (to_sde_plane_state(old_state)->pending) {
  1870. SDE_DEBUG_PLANE(psde, "still pending\n");
  1871. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1872. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1873. pstate->multirect_mode != old_pstate->multirect_mode) {
  1874. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1875. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1876. } else if (state->src_w != old_state->src_w ||
  1877. state->src_h != old_state->src_h ||
  1878. state->src_x != old_state->src_x ||
  1879. state->src_y != old_state->src_y) {
  1880. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1881. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1882. } else if (state->crtc_w != old_state->crtc_w ||
  1883. state->crtc_h != old_state->crtc_h ||
  1884. state->crtc_x != old_state->crtc_x ||
  1885. state->crtc_y != old_state->crtc_y) {
  1886. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1887. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1888. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1889. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1890. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1891. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1892. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1893. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1894. } else if (pstate->rotation != old_pstate->rotation) {
  1895. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1896. pstate->rotation, old_pstate->rotation);
  1897. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1898. }
  1899. fb = state->fb;
  1900. old_fb = old_state->fb;
  1901. if (!fb || !old_fb) {
  1902. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1903. } else if ((fb->format->format != old_fb->format->format) ||
  1904. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1905. SDE_DEBUG_PLANE(psde, "format change\n");
  1906. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1907. } else {
  1908. uint64_t new_mod = fb->modifier;
  1909. uint64_t old_mod = old_fb->modifier;
  1910. uint32_t *new_pitches = fb->pitches;
  1911. uint32_t *old_pitches = old_fb->pitches;
  1912. uint32_t *new_offset = fb->offsets;
  1913. uint32_t *old_offset = old_fb->offsets;
  1914. int i;
  1915. if (new_mod != old_mod) {
  1916. SDE_DEBUG_PLANE(psde,
  1917. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1918. new_mod, old_mod);
  1919. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1920. SDE_PLANE_DIRTY_RECTS;
  1921. }
  1922. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1923. if (new_pitches[i] != old_pitches[i]) {
  1924. SDE_DEBUG_PLANE(psde,
  1925. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1926. i, old_pitches[i], new_pitches[i]);
  1927. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1928. break;
  1929. }
  1930. }
  1931. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1932. if (new_offset[i] != old_offset[i]) {
  1933. SDE_DEBUG_PLANE(psde,
  1934. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1935. i, old_offset[i], new_offset[i]);
  1936. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1937. SDE_PLANE_DIRTY_RECTS;
  1938. break;
  1939. }
  1940. }
  1941. }
  1942. }
  1943. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1944. unsigned long base_addr, u32 size)
  1945. {
  1946. int ret = -EINVAL;
  1947. u32 addr;
  1948. struct sde_plane *psde = to_sde_plane(plane);
  1949. if (!psde || !base_addr || !size) {
  1950. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1951. return ret;
  1952. }
  1953. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1954. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1955. is_sde_plane_virtual(plane));
  1956. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1957. ret = 0;
  1958. }
  1959. return ret;
  1960. }
  1961. static inline bool _sde_plane_is_pre_downscale_enabled(
  1962. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1963. {
  1964. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1965. }
  1966. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1967. struct sde_plane_state *pstate,
  1968. const struct sde_format *fmt,
  1969. uint32_t img_w, uint32_t img_h,
  1970. uint32_t src_w, uint32_t src_h,
  1971. uint32_t deci_w, uint32_t deci_h)
  1972. {
  1973. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1974. bool pre_down_en;
  1975. int i;
  1976. if (!psde || !pstate || !fmt) {
  1977. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1978. return -EINVAL;
  1979. }
  1980. if (psde->debugfs_default_scale ||
  1981. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1982. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1983. return 0;
  1984. pd_cfg = &pstate->pre_down;
  1985. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1986. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1987. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1988. uint32_t hor_req_pixels, hor_fetch_pixels;
  1989. uint32_t vert_req_pixels, vert_fetch_pixels;
  1990. uint32_t src_w_tmp, src_h_tmp;
  1991. uint32_t scaler_w, scaler_h;
  1992. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1993. bool rot;
  1994. /* re-use color plane 1's config for plane 2 */
  1995. if (i == 2)
  1996. continue;
  1997. if (pre_down_en) {
  1998. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1999. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  2000. if (i == 0 && pd_cfg->pre_downscale_y_0)
  2001. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  2002. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  2003. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  2004. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  2005. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  2006. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  2007. i, pre_down_ratio_x, pre_down_ratio_y);
  2008. }
  2009. src_w_tmp = src_w;
  2010. src_h_tmp = src_h;
  2011. /*
  2012. * For chroma plane, width is half for the following sub sampled
  2013. * formats. Except in case of decimation, where hardware avoids
  2014. * 1 line of decimation instead of downsampling.
  2015. */
  2016. if (i == 1) {
  2017. if (!deci_w &&
  2018. (fmt->chroma_sample == SDE_CHROMA_420 ||
  2019. fmt->chroma_sample == SDE_CHROMA_H2V1))
  2020. src_w_tmp >>= 1;
  2021. if (!deci_h &&
  2022. (fmt->chroma_sample == SDE_CHROMA_420 ||
  2023. fmt->chroma_sample == SDE_CHROMA_H1V2))
  2024. src_h_tmp >>= 1;
  2025. }
  2026. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  2027. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  2028. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  2029. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  2030. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  2031. deci_w);
  2032. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  2033. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  2034. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  2035. deci_h);
  2036. if ((hor_req_pixels != hor_fetch_pixels) ||
  2037. (hor_fetch_pixels > img_w) ||
  2038. (vert_req_pixels != vert_fetch_pixels) ||
  2039. (vert_fetch_pixels > img_h)) {
  2040. SDE_ERROR_PLANE(psde,
  2041. "req %d/%d, fetch %d/%d, src %dx%d\n",
  2042. hor_req_pixels, vert_req_pixels,
  2043. hor_fetch_pixels, vert_fetch_pixels,
  2044. img_w, img_h);
  2045. return -EINVAL;
  2046. }
  2047. /*
  2048. * swap the scaler src width & height for inline-rotation 90
  2049. * comparison with Pixel-Extension, as PE is based on
  2050. * pre-rotation and QSEED is based on post-rotation
  2051. */
  2052. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  2053. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  2054. : pstate->scaler3_cfg.src_width[i];
  2055. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  2056. : pstate->scaler3_cfg.src_height[i];
  2057. /*
  2058. * Alpha plane can only be scaled using bilinear or pixel
  2059. * repeat/drop, src_width and src_height are only specified
  2060. * for Y and UV plane
  2061. */
  2062. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  2063. vert_req_pixels / pre_down_ratio_y !=
  2064. scaler_h)) {
  2065. SDE_ERROR_PLANE(psde,
  2066. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  2067. i, pstate->pixel_ext.roi_w[i],
  2068. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  2069. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  2070. return -EINVAL;
  2071. }
  2072. /*
  2073. * SSPP fetch , unpack output and QSEED3 input lines need
  2074. * to match for Y plane
  2075. */
  2076. if (i == 0 &&
  2077. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2078. BIT(SDE_DRM_DEINTERLACE)) &&
  2079. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  2080. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  2081. SDE_ERROR_PLANE(psde,
  2082. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  2083. i, pstate->pixel_ext.roi_w[i],
  2084. pstate->pixel_ext.roi_h[i],
  2085. pstate->scaler3_cfg.src_width[i],
  2086. pstate->scaler3_cfg.src_height[i],
  2087. src_w, src_h);
  2088. return -EINVAL;
  2089. }
  2090. }
  2091. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  2092. return 0;
  2093. }
  2094. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  2095. {
  2096. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  2097. }
  2098. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  2099. struct sde_plane_state *pstate, struct sde_rect *dst,
  2100. u32 src_w, u32 src_h)
  2101. {
  2102. int ret = 0;
  2103. u32 min_ratio_numer, min_ratio_denom;
  2104. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  2105. bool pd_x;
  2106. bool pd_y;
  2107. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  2108. return ret;
  2109. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  2110. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  2111. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  2112. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2113. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  2114. SDE_ERROR_PLANE(psde,
  2115. "hw does not support pre-downscale X: 0x%x\n",
  2116. psde->features);
  2117. ret = -EINVAL;
  2118. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  2119. SDE_ERROR_PLANE(psde,
  2120. "hw does not support pre-downscale Y: 0x%x\n",
  2121. psde->features);
  2122. ret = -EINVAL;
  2123. } else if (!min_ratio_numer || !min_ratio_denom) {
  2124. SDE_ERROR_PLANE(psde,
  2125. "min downscale ratio not set! %u / %u\n",
  2126. min_ratio_numer, min_ratio_denom);
  2127. ret = -EINVAL;
  2128. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2129. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2130. min_ratio_denom))) {
  2131. SDE_ERROR_PLANE(psde,
  2132. "failed min downscale-x check %u->%u, %u/%u\n",
  2133. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2134. ret = -EINVAL;
  2135. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2136. min_ratio_denom))) {
  2137. SDE_ERROR_PLANE(psde,
  2138. "failed min downscale-y check %u->%u, %u/%u\n",
  2139. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2140. ret = -EINVAL;
  2141. }
  2142. return ret;
  2143. }
  2144. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2145. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2146. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2147. u32 *max_numer_h, u32 *max_denom_h)
  2148. {
  2149. bool rotated, has_predown, default_scale;
  2150. const struct sde_sspp_sub_blks *sblk;
  2151. struct sde_hw_inline_pre_downscale_cfg *pd = NULL;
  2152. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2153. sblk = psde->pipe_sblk;
  2154. *max_numer_w = sblk->maxdwnscale;
  2155. *max_denom_w = 1;
  2156. *max_numer_h = sblk->maxdwnscale;
  2157. *max_denom_h = 1;
  2158. has_predown = _sde_plane_has_pre_downscale(psde);
  2159. if (has_predown)
  2160. pd = &pstate->pre_down;
  2161. default_scale = psde->debugfs_default_scale ||
  2162. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2163. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2164. /**
  2165. * Inline rotation has different max vertical downscaling limits since
  2166. * the source-width becomes the scaler's pre-downscaled source-height.
  2167. **/
  2168. if (rotated) {
  2169. if (pd != NULL && rt_client && has_predown) {
  2170. if (default_scale)
  2171. pd->pre_downscale_x_0 = (src_h >
  2172. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2173. *max_numer_h = pd->pre_downscale_x_0 ?
  2174. sblk->in_rot_maxdwnscale_rt_num :
  2175. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2176. *max_denom_h = pd->pre_downscale_x_0 ?
  2177. sblk->in_rot_maxdwnscale_rt_denom :
  2178. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2179. } else if (rt_client) {
  2180. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2181. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2182. } else {
  2183. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2184. }
  2185. }
  2186. }
  2187. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2188. struct sde_plane *psde, const struct sde_format *fmt,
  2189. struct sde_plane_state *pstate, struct sde_rect *src,
  2190. struct sde_rect *dst, u32 width, u32 height)
  2191. {
  2192. int ret = 0;
  2193. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2194. uint32_t scaler_src_w, scaler_src_h;
  2195. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2196. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2197. uint32_t max_upscale, max_linewidth;
  2198. bool inline_rotation, rt_client;
  2199. struct drm_crtc *crtc;
  2200. struct drm_crtc_state *new_cstate;
  2201. const struct sde_sspp_sub_blks *sblk;
  2202. if (!state || !state->state || !state->crtc) {
  2203. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2204. return -EINVAL;
  2205. }
  2206. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2207. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2208. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2209. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2210. /* with inline rotator, the source of the scaler is post-rotated */
  2211. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2212. if (inline_rotation) {
  2213. scaler_src_w = src_deci_h;
  2214. scaler_src_h = src_deci_w;
  2215. } else {
  2216. scaler_src_w = src_deci_w;
  2217. scaler_src_h = src_deci_h;
  2218. }
  2219. sblk = psde->pipe_sblk;
  2220. max_upscale = sblk->maxupscale;
  2221. if (inline_rotation)
  2222. max_linewidth = sblk->in_rot_maxheight;
  2223. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2224. max_linewidth = sblk->scaling_linewidth;
  2225. else
  2226. max_linewidth = sblk->maxlinewidth;
  2227. crtc = state->crtc;
  2228. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2229. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2230. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2231. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2232. &max_downscale_num_h, &max_downscale_denom_h);
  2233. /* decimation validation */
  2234. if ((deci_w || deci_h)
  2235. && ((deci_w > sblk->maxhdeciexp)
  2236. || (deci_h > sblk->maxvdeciexp))) {
  2237. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2238. ret = -EINVAL;
  2239. } else if ((deci_w || deci_h)
  2240. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2241. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2242. ret = -EINVAL;
  2243. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2244. ((src->w != dst->w) || (src->h != dst->h))) {
  2245. SDE_ERROR_PLANE(psde,
  2246. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2247. src->w, src->h, dst->w, dst->h);
  2248. ret = -EINVAL;
  2249. /* check scaler source width */
  2250. } else if (scaler_src_w > max_linewidth) {
  2251. SDE_ERROR_PLANE(psde,
  2252. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2253. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2254. ret = -E2BIG;
  2255. /* check max scaler capability */
  2256. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2257. ((scaler_src_h * max_upscale) < dst->h) ||
  2258. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2259. < scaler_src_w) ||
  2260. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2261. < scaler_src_h)) {
  2262. SDE_ERROR_PLANE(psde,
  2263. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2264. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2265. inline_rotation, max_downscale_num_w,
  2266. max_downscale_denom_w, max_downscale_num_h,
  2267. max_downscale_denom_h);
  2268. ret = -E2BIG;
  2269. /* check inline pre-downscale support */
  2270. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2271. pstate, dst, src_deci_w, src_deci_h)) {
  2272. ret = -EINVAL;
  2273. /* QSEED validation */
  2274. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2275. width, height, src->w, src->h,
  2276. deci_w, deci_h)) {
  2277. ret = -EINVAL;
  2278. }
  2279. return ret;
  2280. }
  2281. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2282. struct sde_plane_state *pstate, struct sde_rect *src,
  2283. const struct sde_format *fmt, int ret)
  2284. {
  2285. /* check excl rect configs */
  2286. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2287. struct sde_rect intersect;
  2288. /*
  2289. * Check exclusion rect against src rect.
  2290. * it must intersect with source rect.
  2291. */
  2292. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2293. if (intersect.w != pstate->excl_rect.w ||
  2294. intersect.h != pstate->excl_rect.h ||
  2295. SDE_FORMAT_IS_YUV(fmt)) {
  2296. SDE_ERROR_PLANE(psde,
  2297. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2298. pstate->excl_rect.x, pstate->excl_rect.y,
  2299. pstate->excl_rect.w, pstate->excl_rect.h,
  2300. src->x, src->y, src->w, src->h,
  2301. (char *)&fmt->base.pixel_format);
  2302. ret = -EINVAL;
  2303. }
  2304. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2305. pstate->excl_rect.x, pstate->excl_rect.y,
  2306. pstate->excl_rect.w, pstate->excl_rect.h);
  2307. }
  2308. return ret;
  2309. }
  2310. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2311. struct drm_plane_state *state)
  2312. {
  2313. struct sde_kms *sde_kms;
  2314. struct sde_splash_display *splash_display;
  2315. int i;
  2316. sde_kms = _sde_plane_get_kms(&psde->base);
  2317. if (!sde_kms || !state->crtc)
  2318. return 0;
  2319. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2320. splash_display = &sde_kms->splash_data.splash_display[i];
  2321. if (splash_display && splash_display->cont_splash_enabled &&
  2322. splash_display->encoder &&
  2323. state->crtc != splash_display->encoder->crtc) {
  2324. struct sde_sspp_index_info *pipe_info = &splash_display->pipe_info;
  2325. if (test_bit(psde->pipe, pipe_info->pipes) ||
  2326. test_bit(psde->pipe, pipe_info->virt_pipes)) {
  2327. SDE_ERROR_PLANE(psde, "pipe:%d used in cont-splash on crtc:%d\n",
  2328. psde->pipe,
  2329. splash_display->encoder->crtc->base.id);
  2330. return -EINVAL;
  2331. }
  2332. }
  2333. }
  2334. return 0;
  2335. }
  2336. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2337. const struct sde_format *fmt,
  2338. struct sde_rect src, struct sde_rect dst,
  2339. u32 width, u32 height)
  2340. {
  2341. int ret = 0;
  2342. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2343. struct sde_kms *sde_kms = _sde_plane_get_kms(&psde->base);
  2344. if (!sde_kms) {
  2345. SDE_ERROR("invalid sde_kms\n");
  2346. return -EINVAL;
  2347. }
  2348. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  2349. psde->pipe_sblk->format_list);
  2350. if (ret) {
  2351. SDE_ERROR_PLANE(psde, "fmt:%d mode:%d unpack:%d not found within the list!\n",
  2352. (fmt) ? fmt->base.pixel_format : 0,
  2353. (fmt) ? fmt->fetch_mode : 0,
  2354. (fmt) ? fmt->unpack_tight : 0);
  2355. return ret;
  2356. }
  2357. if (SDE_FORMAT_IS_YUV(fmt) &&
  2358. (!(psde->features & SDE_SSPP_SCALER) ||
  2359. !(psde->features & (BIT(SDE_SSPP_CSC)
  2360. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2361. SDE_ERROR_PLANE(psde,
  2362. "plane doesn't have scaler/csc for yuv\n");
  2363. ret = -EINVAL;
  2364. /* check src bounds */
  2365. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2366. src.w < min_src_size || src.h < min_src_size ||
  2367. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2368. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2369. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2370. src.x, src.y, src.w, src.h);
  2371. ret = -E2BIG;
  2372. /* valid yuv image */
  2373. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2374. (src.w & 0x1) || (src.h & 0x1))) {
  2375. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2376. src.x, src.y, src.w, src.h);
  2377. ret = -EINVAL;
  2378. /* min dst support */
  2379. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2380. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2381. dst.x, dst.y, dst.w, dst.h);
  2382. ret = -EINVAL;
  2383. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2384. !psde->catalog->ubwc_rev) {
  2385. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2386. ret = -EINVAL;
  2387. }
  2388. return ret;
  2389. }
  2390. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2391. struct drm_plane_state *state)
  2392. {
  2393. int ret = 0;
  2394. struct sde_plane *psde;
  2395. struct sde_plane_state *pstate;
  2396. const struct msm_format *msm_fmt;
  2397. const struct sde_format *fmt;
  2398. struct sde_rect src, dst;
  2399. bool q16_data = true;
  2400. struct drm_framebuffer *fb;
  2401. u32 width;
  2402. u32 height;
  2403. psde = to_sde_plane(plane);
  2404. pstate = to_sde_plane_state(state);
  2405. if (!psde->pipe_sblk) {
  2406. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2407. return -EINVAL;
  2408. }
  2409. /* src values are in Q16 fixed point, convert to integer */
  2410. POPULATE_RECT(&src, state->src_x, state->src_y,
  2411. state->src_w, state->src_h, q16_data);
  2412. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2413. state->crtc_h, !q16_data);
  2414. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2415. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2416. if (!sde_plane_enabled(state))
  2417. goto modeset_update;
  2418. fb = state->fb;
  2419. width = fb ? state->fb->width : 0x0;
  2420. height = fb ? state->fb->height : 0x0;
  2421. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2422. plane->base.id,
  2423. pstate->rotation,
  2424. width, height,
  2425. fb ? (char *) &state->fb->format->format : 0x0,
  2426. fb ? state->fb->modifier : 0x0);
  2427. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2428. state->src_w >> 16, state->src_h >> 16,
  2429. state->src_x >> 16, state->src_y >> 16,
  2430. state->crtc_w, state->crtc_h,
  2431. state->crtc_x, state->crtc_y);
  2432. msm_fmt = msm_framebuffer_format(fb);
  2433. fmt = to_sde_format(msm_fmt);
  2434. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2435. height);
  2436. if (ret)
  2437. return ret;
  2438. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2439. &src, &dst, width, height);
  2440. if (ret)
  2441. return ret;
  2442. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2443. &src, fmt, ret);
  2444. if (ret)
  2445. return ret;
  2446. ret = _sde_plane_validate_shared_crtc(psde, state);
  2447. if (ret)
  2448. return ret;
  2449. pstate->const_alpha_en = fmt->alpha_enable &&
  2450. (SDE_DRM_BLEND_OP_OPAQUE !=
  2451. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2452. (pstate->stage != SDE_STAGE_0);
  2453. modeset_update:
  2454. if (!ret)
  2455. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2456. state, plane->state);
  2457. return ret;
  2458. }
  2459. static int _sde_plane_atomic_check(struct drm_plane *plane,
  2460. struct drm_plane_state *state)
  2461. {
  2462. int ret = 0;
  2463. struct sde_plane *psde;
  2464. struct sde_plane_state *pstate;
  2465. psde = to_sde_plane(plane);
  2466. pstate = to_sde_plane_state(state);
  2467. SDE_DEBUG_PLANE(psde, "\n");
  2468. ret = sde_plane_rot_atomic_check(plane, state);
  2469. if (ret)
  2470. goto exit;
  2471. ret = sde_plane_sspp_atomic_check(plane, state);
  2472. exit:
  2473. return ret;
  2474. }
  2475. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2476. static int sde_plane_atomic_check(struct drm_plane *plane,
  2477. struct drm_atomic_state *atomic_state)
  2478. {
  2479. struct drm_plane_state *state = NULL;
  2480. if (!plane || !atomic_state) {
  2481. SDE_ERROR("invalid arg(s), plane %d atomic_state %d\n",
  2482. !plane, !atomic_state);
  2483. return -EINVAL;
  2484. }
  2485. state = drm_atomic_get_new_plane_state(atomic_state, plane);
  2486. return _sde_plane_atomic_check(plane, state);
  2487. }
  2488. #else
  2489. static int sde_plane_atomic_check(struct drm_plane *plane,
  2490. struct drm_plane_state *state)
  2491. {
  2492. if (!plane || !state) {
  2493. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2494. !plane, !state);
  2495. return -EINVAL;
  2496. }
  2497. return _sde_plane_atomic_check(plane, state);
  2498. }
  2499. #endif
  2500. void sde_plane_flush(struct drm_plane *plane)
  2501. {
  2502. struct sde_plane *psde;
  2503. struct sde_plane_state *pstate;
  2504. if (!plane || !plane->state) {
  2505. SDE_ERROR("invalid plane\n");
  2506. return;
  2507. }
  2508. psde = to_sde_plane(plane);
  2509. pstate = to_sde_plane_state(plane->state);
  2510. /*
  2511. * These updates have to be done immediately before the plane flush
  2512. * timing, and may not be moved to the atomic_update/mode_set functions.
  2513. */
  2514. if (psde->is_error)
  2515. /* force white frame with 100% alpha pipe output on error */
  2516. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2517. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2518. /* force 100% alpha */
  2519. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2520. else if (psde->pipe_hw && pstate->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2521. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, pstate->csc_ptr);
  2522. /* flag h/w flush complete */
  2523. if (plane->state)
  2524. pstate->pending = false;
  2525. }
  2526. /**
  2527. * sde_plane_set_error: enable/disable error condition
  2528. * @plane: pointer to drm_plane structure
  2529. */
  2530. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2531. {
  2532. struct sde_plane *psde;
  2533. if (!plane)
  2534. return;
  2535. psde = to_sde_plane(plane);
  2536. psde->is_error = error;
  2537. }
  2538. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2539. struct sde_plane_state *pstate)
  2540. {
  2541. struct drm_plane_state *state = psde->base.state;
  2542. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2543. struct sde_hw_pipe_sc_cfg *cfg = &pstate->sc_cfg;
  2544. bool prev_rd_en = cfg->rd_en;
  2545. u32 cache_flag, cache_rd_type, cache_wr_type;
  2546. enum sde_sys_cache_state cache_state;
  2547. if (!state->fb) {
  2548. SDE_ERROR("invalid fb on plane %d\n", DRMID(&psde->base));
  2549. return;
  2550. }
  2551. cache_state = pstate->static_cache_state;
  2552. msm_framebuffer_get_cache_hint(state->fb, &cache_flag, &cache_rd_type, &cache_wr_type);
  2553. cfg->rd_en = false;
  2554. cfg->rd_scid = 0x0;
  2555. cfg->flags = SYS_CACHE_EN_FLAG | SYS_CACHE_SCID;
  2556. /*
  2557. * if condition handles static display legacy path, where internal state machine is
  2558. * transitioning the "cache_state" variable to program the LLCC cache through
  2559. * SSPP hardware using SDE_SYS_CACHE_DISP SCID.
  2560. * else condition handles static display and IWE path, were the frame is programmed to
  2561. * LLCC cache through WB/CWB path and read back by SSPP hardware. The FB cache hints are
  2562. * used to pass information on which SCID to use during read path and LLCC cache to
  2563. * keep active.
  2564. */
  2565. if (test_bit(SDE_SYS_CACHE_DISP, psde->catalog->sde_sys_cache_type_map)
  2566. && ((cache_state == CACHE_STATE_FRAME_WRITE)
  2567. || (cache_state == CACHE_STATE_FRAME_READ))) {
  2568. cfg->type = pstate->static_cache_type;
  2569. cfg->rd_en = true;
  2570. cfg->rd_scid = sc_cfg[cfg->type].llcc_scid;
  2571. if (test_bit(SDE_FEATURE_SYS_CACHE_NSE, psde->catalog->features)) {
  2572. cfg->rd_noallocate = false;
  2573. pstate->static_cache_state = CACHE_STATE_NORMAL;
  2574. } else {
  2575. cfg->rd_noallocate = (cache_state == CACHE_STATE_FRAME_READ);
  2576. }
  2577. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2578. } else if (test_bit(cache_rd_type, psde->catalog->sde_sys_cache_type_map) && cache_flag) {
  2579. cfg->rd_en = true;
  2580. cfg->type = cache_rd_type;
  2581. cfg->rd_scid = sc_cfg[cache_rd_type].llcc_scid;
  2582. cfg->rd_noallocate = false;
  2583. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2584. cache_flag = MSM_FB_CACHE_READ_EN;
  2585. msm_framebuffer_set_cache_hint(state->fb, cache_flag, cache_rd_type, cache_wr_type);
  2586. }
  2587. if (!cfg->rd_en && !prev_rd_en)
  2588. return;
  2589. SDE_EVT32(DRMID(&psde->base), cfg->type, cfg->rd_scid, cfg->rd_en, cfg->rd_noallocate,
  2590. cfg->flags, cache_state, cache_flag, cache_rd_type, cache_wr_type,
  2591. state->fb->base.id);
  2592. psde->pipe_hw->ops.setup_sys_cache(psde->pipe_hw, cfg);
  2593. }
  2594. void sde_plane_static_img_control(struct drm_plane *plane,
  2595. enum sde_sys_cache_state state, enum sde_sys_cache_type type)
  2596. {
  2597. struct sde_plane *psde;
  2598. struct sde_plane_state *pstate;
  2599. if (!plane || !plane->state) {
  2600. SDE_ERROR("invalid plane\n");
  2601. return;
  2602. }
  2603. psde = to_sde_plane(plane);
  2604. pstate = to_sde_plane_state(plane->state);
  2605. pstate->static_cache_state = state;
  2606. pstate->static_cache_type = type;
  2607. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2608. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2609. }
  2610. static void _sde_plane_map_prop_to_dirty_bits(void)
  2611. {
  2612. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2613. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2614. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2615. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2616. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2617. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2618. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2619. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2620. plane_prop_array[PLANE_PROP_ZPOS] =
  2621. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2622. plane_prop_array[PLANE_PROP_UBWC_STATS_ROI] =
  2623. SDE_PLANE_DIRTY_RECTS;
  2624. plane_prop_array[PLANE_PROP_CSC_V1] =
  2625. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2626. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2627. SDE_PLANE_DIRTY_FORMAT;
  2628. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2629. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2630. SDE_PLANE_DIRTY_ALL;
  2631. /* no special action required */
  2632. plane_prop_array[PLANE_PROP_INFO] =
  2633. plane_prop_array[PLANE_PROP_ALPHA] =
  2634. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2635. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2636. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2637. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2638. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2639. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2640. SDE_PLANE_DIRTY_PERF;
  2641. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2642. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2643. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2644. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2645. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2646. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2647. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2648. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2649. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2650. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2651. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2652. SDE_PLANE_DIRTY_ALL;
  2653. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2654. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2655. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2656. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2657. plane_prop_array[PLANE_PROP_UCSC_UNMULT] = SDE_PLANE_DIRTY_UCSC_UNMULT;
  2658. plane_prop_array[PLANE_PROP_UCSC_IGC] = SDE_PLANE_DIRTY_UCSC_IGC;
  2659. plane_prop_array[PLANE_PROP_UCSC_CSC] = SDE_PLANE_DIRTY_UCSC_CSC;
  2660. plane_prop_array[PLANE_PROP_UCSC_GC] = SDE_PLANE_DIRTY_UCSC_GC;
  2661. plane_prop_array[PLANE_PROP_UCSC_ALPHA_DITHER] = SDE_PLANE_DIRTY_UCSC_ALPHA_DITHER;
  2662. }
  2663. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2664. struct sde_rect *src, struct sde_rect *dst)
  2665. {
  2666. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2667. u32 downscale = (src->h * 1000)/dst->h;
  2668. return (downscale > max_downscale) ? false : true;
  2669. }
  2670. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2671. struct sde_plane *psde, struct sde_plane_state *pstate,
  2672. struct sde_rect *src, struct sde_rect *dst)
  2673. {
  2674. struct sde_hw_pipe_uidle_cfg cfg;
  2675. u32 line_time = sde_crtc_get_line_time(crtc);
  2676. u32 fal1_target_idle_time_ns =
  2677. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2678. u32 fal10_target_idle_time_ns =
  2679. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2680. u32 fal10_threshold =
  2681. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2682. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2683. fal1_target_idle_time_ns) {
  2684. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2685. cfg.fal10_threshold = fal10_threshold;
  2686. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2687. cfg.fal1_threshold = min(1 +
  2688. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2689. psde->catalog->uidle_cfg.fal1_max_threshold);
  2690. cfg.fal_allowed_threshold = fal10_threshold +
  2691. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2692. cfg.fill_level_scale = 0;
  2693. /*
  2694. * if uidle fill scale is supported, determing the scale value
  2695. * and adjust fal10 thresholds to their scaled values.
  2696. * fal1 thresholds and fal_allowed are not scaled.
  2697. */
  2698. if (psde->pipe_hw->ops.setup_uidle_fill_scale) {
  2699. u32 fl_require0 = psde->catalog->qos_target_time_ns / line_time * 2;
  2700. u32 fl_require = max(fal10_threshold * 1000, fl_require0);
  2701. u32 fl_scale = fl_require / fal10_threshold;
  2702. u32 fal10_threshold_noscale;
  2703. cfg.fill_level_scale = (fl_scale <= 1) ? 0 : (32 / fl_scale);
  2704. if (cfg.fill_level_scale) {
  2705. fal10_threshold_noscale = fal10_threshold *
  2706. 32/cfg.fill_level_scale;
  2707. cfg.fal_allowed_threshold = fal10_threshold_noscale +
  2708. (fal10_target_idle_time_ns * 1000 / line_time * 2) / 1000;
  2709. }
  2710. }
  2711. } else {
  2712. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2713. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2714. fal1_target_idle_time_ns);
  2715. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2716. }
  2717. SDE_DEBUG_PLANE(psde,
  2718. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d fill_scale=%d\n",
  2719. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2720. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2721. cfg.fill_level_scale);
  2722. SDE_DEBUG_PLANE(psde,
  2723. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2724. line_time, fal1_target_idle_time_ns,
  2725. fal10_target_idle_time_ns,
  2726. psde->catalog->uidle_cfg.max_dwnscale);
  2727. SDE_EVT32_VERBOSE(cfg.enable,
  2728. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2729. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2730. cfg.fill_level_scale, psde->catalog->uidle_cfg.max_dwnscale);
  2731. if (psde->pipe_hw->ops.setup_uidle_fill_scale)
  2732. psde->pipe_hw->ops.setup_uidle_fill_scale(psde->pipe_hw, &cfg);
  2733. psde->pipe_hw->ops.setup_uidle(
  2734. psde->pipe_hw, &cfg,
  2735. pstate->multirect_index);
  2736. }
  2737. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2738. struct sde_plane_state *pstate)
  2739. {
  2740. bool enable = false;
  2741. int mode = sde_plane_get_property(pstate,
  2742. PLANE_PROP_FB_TRANSLATION_MODE);
  2743. if ((mode == SDE_DRM_FB_SEC) ||
  2744. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2745. enable = true;
  2746. /* update secure session flag */
  2747. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2748. pstate->multirect_index,
  2749. enable);
  2750. }
  2751. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2752. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2753. {
  2754. const struct sde_format *fmt;
  2755. const struct msm_format *msm_fmt;
  2756. struct sde_plane *psde;
  2757. struct drm_plane_state *state;
  2758. struct sde_plane_state *pstate;
  2759. struct sde_rect src, dst;
  2760. const struct sde_rect *crtc_roi;
  2761. bool q16_data = true;
  2762. int idx;
  2763. psde = to_sde_plane(plane);
  2764. state = plane->state;
  2765. pstate = to_sde_plane_state(state);
  2766. msm_fmt = msm_framebuffer_format(fb);
  2767. if (!msm_fmt) {
  2768. SDE_ERROR("crtc%d plane%d: null format\n",
  2769. DRMID(crtc), DRMID(plane));
  2770. return;
  2771. }
  2772. fmt = to_sde_format(msm_fmt);
  2773. POPULATE_RECT(&src, state->src_x, state->src_y,
  2774. state->src_w, state->src_h, q16_data);
  2775. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2776. state->crtc_w, state->crtc_h, !q16_data);
  2777. SDE_DEBUG_PLANE(psde,
  2778. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2779. fb->base.id, src.x, src.y, src.w, src.h,
  2780. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2781. (char *)&fmt->base.pixel_format,
  2782. SDE_FORMAT_IS_UBWC(fmt));
  2783. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2784. BIT(SDE_DRM_DEINTERLACE)) {
  2785. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2786. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2787. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2788. src.h /= 2;
  2789. src.y = DIV_ROUND_UP(src.y, 2);
  2790. src.y &= ~0x1;
  2791. }
  2792. /*
  2793. * adjust layer mixer position of the sspp in the presence
  2794. * of a partial update to the active lm origin
  2795. */
  2796. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2797. dst.x -= crtc_roi->x;
  2798. dst.y -= crtc_roi->y;
  2799. /* check for UIDLE */
  2800. if (psde->pipe_hw->ops.setup_uidle)
  2801. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2802. psde->pipe_cfg.src_rect = src;
  2803. psde->pipe_cfg.dst_rect = dst;
  2804. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2805. _sde_plane_setup_panel_stacking(psde, pstate);
  2806. /* check for color fill */
  2807. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2808. PLANE_PROP_COLOR_FILL);
  2809. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2810. /* skip remaining processing on color fill */
  2811. pstate->dirty = 0x0;
  2812. } else if (psde->pipe_hw->ops.setup_rects) {
  2813. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2814. &psde->pipe_cfg,
  2815. pstate->multirect_index);
  2816. }
  2817. if (psde->pipe_hw->ops.setup_pe &&
  2818. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2819. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2820. &psde->pixel_ext);
  2821. /**
  2822. * when programmed in multirect mode, scalar block will be
  2823. * bypassed. Still we need to update alpha and bitwidth
  2824. * ONLY for RECT0
  2825. */
  2826. if (psde->pipe_hw->ops.setup_scaler &&
  2827. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2828. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2829. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2830. &psde->pipe_cfg, &psde->pixel_ext,
  2831. &psde->scaler3_cfg);
  2832. }
  2833. /* update excl rect */
  2834. if (psde->pipe_hw->ops.setup_excl_rect)
  2835. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2836. &pstate->excl_rect,
  2837. pstate->multirect_index);
  2838. /* enable multirect config of corresponding rect */
  2839. if (psde->pipe_hw->ops.update_multirect)
  2840. psde->pipe_hw->ops.update_multirect(
  2841. psde->pipe_hw,
  2842. true,
  2843. pstate->multirect_index,
  2844. pstate->multirect_mode);
  2845. /* update line insertion */
  2846. if (pstate->lineinsertion_feature && psde->pipe_hw->ops.setup_line_insertion)
  2847. psde->pipe_hw->ops.setup_line_insertion(psde->pipe_hw,
  2848. pstate->multirect_index,
  2849. &pstate->line_insertion_cfg);
  2850. }
  2851. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2852. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2853. {
  2854. uint32_t src_flags = 0;
  2855. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2856. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2857. src_flags |= SDE_SSPP_FLIP_LR;
  2858. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2859. src_flags |= SDE_SSPP_FLIP_UD;
  2860. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2861. src_flags |= SDE_SSPP_ROT_90;
  2862. /* update format */
  2863. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2864. pstate->const_alpha_en, src_flags,
  2865. pstate->multirect_index);
  2866. if (psde->pipe_hw->ops.setup_cdp) {
  2867. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2868. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2869. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2870. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2871. cdp_cfg->ubwc_meta_enable =
  2872. SDE_FORMAT_IS_UBWC(fmt);
  2873. cdp_cfg->tile_amortize_enable =
  2874. SDE_FORMAT_IS_UBWC(fmt) ||
  2875. SDE_FORMAT_IS_TILE(fmt);
  2876. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2877. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2878. pstate->multirect_index);
  2879. }
  2880. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2881. /* update csc */
  2882. if (SDE_FORMAT_IS_YUV(fmt))
  2883. _sde_plane_setup_csc(psde, pstate);
  2884. else
  2885. pstate->csc_ptr = 0;
  2886. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2887. uint32_t pma_mode = 0;
  2888. if (fmt->alpha_enable)
  2889. pma_mode = (uint32_t) sde_plane_get_property(
  2890. pstate, PLANE_PROP_INVERSE_PMA);
  2891. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2892. pstate->multirect_index, pma_mode);
  2893. }
  2894. if (psde->pipe_hw->ops.setup_dgm_csc)
  2895. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2896. pstate->multirect_index, pstate->csc_usr_ptr);
  2897. if (psde->pipe_hw->ops.set_ubwc_stats_roi) {
  2898. if (SDE_FORMAT_IS_UBWC(fmt) && !SDE_FORMAT_IS_YUV(fmt))
  2899. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2900. pstate->multirect_index, &pstate->ubwc_stats_roi);
  2901. else
  2902. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2903. pstate->multirect_index, NULL);
  2904. }
  2905. }
  2906. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2907. {
  2908. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2909. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2910. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2911. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2912. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2913. &psde->sharp_cfg);
  2914. }
  2915. static void _sde_plane_update_properties(struct drm_plane *plane,
  2916. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2917. {
  2918. uint32_t nplanes;
  2919. const struct msm_format *msm_fmt;
  2920. const struct sde_format *fmt;
  2921. struct sde_plane *psde;
  2922. struct drm_plane_state *state;
  2923. struct sde_plane_state *pstate;
  2924. psde = to_sde_plane(plane);
  2925. state = plane->state;
  2926. pstate = to_sde_plane_state(state);
  2927. if (!pstate) {
  2928. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2929. return;
  2930. }
  2931. msm_fmt = msm_framebuffer_format(fb);
  2932. if (!msm_fmt) {
  2933. SDE_ERROR("crtc%d plane%d: null format\n",
  2934. DRMID(crtc), DRMID(plane));
  2935. return;
  2936. }
  2937. fmt = to_sde_format(msm_fmt);
  2938. nplanes = fmt->num_planes;
  2939. /* update secure session flag */
  2940. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2941. _sde_plane_update_secure_session(psde, pstate);
  2942. /* update roi config */
  2943. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2944. _sde_plane_update_roi_config(plane, crtc, fb);
  2945. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2946. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2947. psde->pipe_hw->ops.setup_format)
  2948. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2949. sde_color_process_plane_setup(plane);
  2950. /* update sharpening */
  2951. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2952. psde->pipe_hw->ops.setup_sharpening)
  2953. _sde_plane_update_sharpening(psde);
  2954. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2955. SDE_PLANE_DIRTY_FORMAT))
  2956. _sde_plane_set_qos_lut(plane, crtc, fb);
  2957. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2958. _sde_plane_set_ot_limit(plane, crtc);
  2959. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2960. _sde_plane_set_ts_prefill(plane, pstate);
  2961. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2962. _sde_plane_set_qos_remap(plane);
  2963. /* clear dirty */
  2964. pstate->dirty = 0x0;
  2965. }
  2966. static void _sde_plane_check_lut_dirty(struct sde_plane *psde,
  2967. struct sde_plane_state *pstate)
  2968. {
  2969. /**
  2970. * Valid configuration if scaler is not enabled or
  2971. * lut flag is set
  2972. */
  2973. if (pstate->scaler3_cfg.lut_flag || !pstate->scaler3_cfg.enable)
  2974. return;
  2975. pstate->scaler3_cfg.lut_flag = psde->cached_lut_flag;
  2976. SDE_EVT32(DRMID(&psde->base), pstate->scaler3_cfg.lut_flag, SDE_EVTLOG_ERROR);
  2977. }
  2978. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2979. struct drm_plane_state *old_state)
  2980. {
  2981. struct sde_plane *psde;
  2982. struct drm_plane_state *state;
  2983. struct sde_plane_state *pstate;
  2984. struct sde_plane_state *old_pstate;
  2985. struct drm_crtc *crtc;
  2986. struct drm_framebuffer *fb;
  2987. int idx;
  2988. int dirty_prop_flag;
  2989. bool is_rt;
  2990. if (!plane) {
  2991. SDE_ERROR("invalid plane\n");
  2992. return -EINVAL;
  2993. } else if (!plane->state) {
  2994. SDE_ERROR("invalid plane state\n");
  2995. return -EINVAL;
  2996. } else if (!old_state) {
  2997. SDE_ERROR("invalid old state\n");
  2998. return -EINVAL;
  2999. }
  3000. psde = to_sde_plane(plane);
  3001. state = plane->state;
  3002. pstate = to_sde_plane_state(state);
  3003. old_pstate = to_sde_plane_state(old_state);
  3004. crtc = state->crtc;
  3005. fb = state->fb;
  3006. if (!crtc || !fb) {
  3007. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  3008. !crtc, !fb);
  3009. return -EINVAL;
  3010. }
  3011. SDE_DEBUG(
  3012. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  3013. plane->base.id,
  3014. state->fb->width, state->fb->height,
  3015. (char *) &state->fb->format->format,
  3016. state->fb->modifier,
  3017. state->src_w >> 16, state->src_h >> 16,
  3018. state->src_x >> 16, state->src_y >> 16,
  3019. pstate->rotation,
  3020. state->crtc_w, state->crtc_h,
  3021. state->crtc_x, state->crtc_y);
  3022. /* Caching the valid lut flag in sde plane */
  3023. if (pstate->scaler3_cfg.enable && pstate->scaler3_cfg.lut_flag)
  3024. psde->cached_lut_flag = pstate->scaler3_cfg.lut_flag;
  3025. /* force reprogramming of all the parameters, if the flag is set */
  3026. if (psde->revalidate) {
  3027. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  3028. plane->base.id);
  3029. _sde_plane_check_lut_dirty(psde, pstate);
  3030. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  3031. psde->revalidate = false;
  3032. }
  3033. /* determine what needs to be refreshed */
  3034. mutex_lock(&psde->property_info.property_lock);
  3035. while ((idx = msm_property_pop_dirty(&psde->property_info,
  3036. &pstate->property_state)) >= 0) {
  3037. dirty_prop_flag = plane_prop_array[idx];
  3038. pstate->dirty |= dirty_prop_flag;
  3039. }
  3040. mutex_unlock(&psde->property_info.property_lock);
  3041. /**
  3042. * since plane_atomic_check is invoked before crtc_atomic_check
  3043. * in the commit sequence, all the parameters for updating the
  3044. * plane dirty flag will not be available during
  3045. * plane_atomic_check as some features params are updated
  3046. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  3047. * before sspp update.
  3048. */
  3049. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  3050. old_state);
  3051. /* re-program the output rects always if partial update roi changed */
  3052. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  3053. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  3054. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  3055. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  3056. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  3057. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  3058. if (is_rt != psde->is_rt_pipe || crtc->state->mode_changed) {
  3059. psde->is_rt_pipe = is_rt;
  3060. psde->wb_usage_type = psde->is_rt_pipe ? 0 : sde_crtc_get_wb_usage_type(crtc);
  3061. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  3062. }
  3063. /* early out if nothing dirty */
  3064. if (!pstate->dirty)
  3065. return 0;
  3066. pstate->pending = true;
  3067. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3068. _sde_plane_update_properties(plane, crtc, fb);
  3069. return 0;
  3070. }
  3071. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  3072. struct drm_plane_state *old_state)
  3073. {
  3074. struct sde_plane *psde;
  3075. struct drm_plane_state *state;
  3076. struct sde_plane_state *pstate;
  3077. u32 multirect_index = SDE_SSPP_RECT_0;
  3078. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  3079. u32 blend_type;
  3080. if (!plane) {
  3081. SDE_ERROR("invalid plane\n");
  3082. return;
  3083. } else if (!plane->state) {
  3084. SDE_ERROR("invalid plane state\n");
  3085. return;
  3086. } else if (!old_state) {
  3087. SDE_ERROR("invalid old state\n");
  3088. return;
  3089. }
  3090. psde = to_sde_plane(plane);
  3091. state = plane->state;
  3092. pstate = to_sde_plane_state(state);
  3093. blend_type = sde_plane_get_property(pstate,
  3094. PLANE_PROP_BLEND_OP);
  3095. /* some of the color features are dependent on plane with skip blend.
  3096. * if skip blend plane is being disabled, we need to disable color properties.
  3097. */
  3098. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  3099. skip_blend_plane.valid_plane = false;
  3100. skip_blend_plane.plane = SSPP_NONE;
  3101. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  3102. sde_crtc_disable_cp_features(old_state->crtc);
  3103. }
  3104. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  3105. pstate->multirect_mode);
  3106. pstate->pending = true;
  3107. pstate->static_cache_state = CACHE_STATE_DISABLED;
  3108. if (is_sde_plane_virtual(plane))
  3109. multirect_index = SDE_SSPP_RECT_1;
  3110. /* disable multirect config of corresponding rect */
  3111. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  3112. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  3113. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  3114. }
  3115. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3116. static void _sde_plane_atomic_update(struct drm_plane *plane,
  3117. struct drm_plane_state *old_state)
  3118. #else
  3119. static void sde_plane_atomic_update(struct drm_plane *plane,
  3120. struct drm_plane_state *old_state)
  3121. #endif
  3122. {
  3123. struct sde_plane *psde;
  3124. struct drm_plane_state *state;
  3125. if (!plane) {
  3126. SDE_ERROR("invalid plane\n");
  3127. return;
  3128. } else if (!plane->state) {
  3129. SDE_ERROR("invalid plane state\n");
  3130. return;
  3131. }
  3132. psde = to_sde_plane(plane);
  3133. psde->is_error = false;
  3134. state = plane->state;
  3135. SDE_DEBUG_PLANE(psde, "\n");
  3136. if (!sde_plane_enabled(state)) {
  3137. _sde_plane_atomic_disable(plane, old_state);
  3138. } else {
  3139. int ret;
  3140. ret = sde_plane_sspp_atomic_update(plane, old_state);
  3141. /* atomic_check should have ensured that this doesn't fail */
  3142. WARN_ON(ret < 0);
  3143. }
  3144. }
  3145. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3146. static void sde_plane_atomic_update(struct drm_plane *plane,
  3147. struct drm_atomic_state *atomic_state)
  3148. {
  3149. struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(atomic_state, plane);
  3150. _sde_plane_atomic_update(plane, old_state);
  3151. }
  3152. #endif
  3153. void sde_plane_restore(struct drm_plane *plane)
  3154. {
  3155. struct sde_plane *psde;
  3156. if (!plane || !plane->state) {
  3157. SDE_ERROR("invalid plane\n");
  3158. return;
  3159. }
  3160. psde = to_sde_plane(plane);
  3161. /*
  3162. * Revalidate is only true here if idle PC occurred and
  3163. * there is no plane state update in current commit cycle.
  3164. */
  3165. if (!psde->revalidate)
  3166. return;
  3167. SDE_DEBUG_PLANE(psde, "\n");
  3168. /* last plane state is same as current state */
  3169. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3170. _sde_plane_atomic_update(plane, plane->state);
  3171. #else
  3172. sde_plane_atomic_update(plane, plane->state);
  3173. #endif
  3174. }
  3175. bool sde_plane_is_cache_required(struct drm_plane *plane,
  3176. enum sde_sys_cache_type type)
  3177. {
  3178. struct sde_plane_state *pstate;
  3179. u32 cache_flag, cache_rd_type, cache_wr_type;
  3180. if (!plane || !plane->state) {
  3181. SDE_ERROR("invalid plane\n");
  3182. return false;
  3183. }
  3184. pstate = to_sde_plane_state(plane->state);
  3185. msm_framebuffer_get_cache_hint(plane->state->fb, &cache_flag, &cache_rd_type,
  3186. &cache_wr_type);
  3187. /* check if llcc is required for the plane */
  3188. if (pstate->sc_cfg.rd_en && ((pstate->sc_cfg.type == type)
  3189. || (cache_flag && (cache_rd_type == type))
  3190. || (cache_flag && (cache_wr_type == type)))) {
  3191. SDE_EVT32_VERBOSE(DRMID(plane), type, pstate->sc_cfg.rd_en, pstate->sc_cfg.type,
  3192. cache_flag, cache_rd_type, cache_wr_type,
  3193. plane->state->fb->base.id);
  3194. return true;
  3195. }
  3196. return false;
  3197. }
  3198. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  3199. {
  3200. char feature_name[256];
  3201. if (psde->pipe_sblk->maxhdeciexp) {
  3202. msm_property_install_range(&psde->property_info,
  3203. "h_decimate", 0x0, 0,
  3204. psde->pipe_sblk->maxhdeciexp, 0,
  3205. PLANE_PROP_H_DECIMATE);
  3206. }
  3207. if (psde->pipe_sblk->maxvdeciexp) {
  3208. msm_property_install_range(&psde->property_info,
  3209. "v_decimate", 0x0, 0,
  3210. psde->pipe_sblk->maxvdeciexp, 0,
  3211. PLANE_PROP_V_DECIMATE);
  3212. }
  3213. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  3214. msm_property_install_range(
  3215. &psde->property_info, "scaler_v2",
  3216. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3217. msm_property_install_blob(&psde->property_info,
  3218. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  3219. msm_property_install_blob(&psde->property_info,
  3220. "lut_cir", 0,
  3221. PLANE_PROP_SCALER_LUT_CIR);
  3222. msm_property_install_blob(&psde->property_info,
  3223. "lut_sep", 0,
  3224. PLANE_PROP_SCALER_LUT_SEP);
  3225. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  3226. msm_property_install_range(
  3227. &psde->property_info, "scaler_v2",
  3228. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3229. msm_property_install_blob(&psde->property_info,
  3230. "lut_sep", 0,
  3231. PLANE_PROP_SCALER_LUT_SEP);
  3232. } else if (psde->features & SDE_SSPP_SCALER) {
  3233. msm_property_install_range(
  3234. &psde->property_info, "scaler_v1", 0x0,
  3235. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  3236. }
  3237. if (psde->features & BIT(SDE_SSPP_CSC) ||
  3238. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  3239. msm_property_install_volatile_range(
  3240. &psde->property_info, "csc_v1", 0x0,
  3241. 0, ~0, 0, PLANE_PROP_CSC_V1);
  3242. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  3243. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3244. "SDE_SSPP_HUE_V",
  3245. psde->pipe_sblk->hsic_blk.version >> 16);
  3246. msm_property_install_range(&psde->property_info,
  3247. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3248. PLANE_PROP_HUE_ADJUST);
  3249. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3250. "SDE_SSPP_SATURATION_V",
  3251. psde->pipe_sblk->hsic_blk.version >> 16);
  3252. msm_property_install_range(&psde->property_info,
  3253. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3254. PLANE_PROP_SATURATION_ADJUST);
  3255. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3256. "SDE_SSPP_VALUE_V",
  3257. psde->pipe_sblk->hsic_blk.version >> 16);
  3258. msm_property_install_range(&psde->property_info,
  3259. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3260. PLANE_PROP_VALUE_ADJUST);
  3261. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3262. "SDE_SSPP_CONTRAST_V",
  3263. psde->pipe_sblk->hsic_blk.version >> 16);
  3264. msm_property_install_range(&psde->property_info,
  3265. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3266. PLANE_PROP_CONTRAST_ADJUST);
  3267. }
  3268. }
  3269. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3270. struct sde_kms_info *info)
  3271. {
  3272. char feature_name[256];
  3273. bool is_master = !psde->is_virtual;
  3274. static const struct drm_prop_enum_list ucsc_gc[] = {
  3275. {UCSC_GC_MODE_DISABLE, "disable"},
  3276. {UCSC_GC_MODE_SRGB, "srgb"},
  3277. {UCSC_GC_MODE_PQ, "pq"},
  3278. {UCSC_GC_MODE_GAMMA2_2, "gamma2_2"},
  3279. {UCSC_GC_MODE_HLG, "hlg"},
  3280. };
  3281. static const struct drm_prop_enum_list ucsc_igc[] = {
  3282. {UCSC_IGC_MODE_DISABLE, "disable"},
  3283. {UCSC_IGC_MODE_SRGB, "srgb"},
  3284. {UCSC_IGC_MODE_REC709, "rec709"},
  3285. {UCSC_IGC_MODE_GAMMA2_2, "gamma2_2"},
  3286. {UCSC_IGC_MODE_HLG, "hlg"},
  3287. {UCSC_IGC_MODE_PQ, "pq"},
  3288. };
  3289. if ((is_master &&
  3290. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3291. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3292. msm_property_install_range(&psde->property_info,
  3293. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3294. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3295. }
  3296. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3297. msm_property_install_volatile_range(
  3298. &psde->property_info, "csc_dma_v1", 0x0,
  3299. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3300. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3301. }
  3302. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3303. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3304. "SDE_SSPP_SKIN_COLOR_V",
  3305. psde->pipe_sblk->memcolor_blk.version >> 16);
  3306. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3307. PLANE_PROP_SKIN_COLOR);
  3308. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3309. "SDE_SSPP_SKY_COLOR_V",
  3310. psde->pipe_sblk->memcolor_blk.version >> 16);
  3311. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3312. PLANE_PROP_SKY_COLOR);
  3313. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3314. "SDE_SSPP_FOLIAGE_COLOR_V",
  3315. psde->pipe_sblk->memcolor_blk.version >> 16);
  3316. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3317. PLANE_PROP_FOLIAGE_COLOR);
  3318. }
  3319. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3320. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3321. "SDE_VIG_3D_LUT_GAMUT_V",
  3322. psde->pipe_sblk->gamut_blk.version >> 16);
  3323. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3324. PLANE_PROP_VIG_GAMUT);
  3325. }
  3326. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3327. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3328. "SDE_VIG_1D_LUT_IGC_V",
  3329. psde->pipe_sblk->igc_blk[0].version >> 16);
  3330. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3331. PLANE_PROP_VIG_IGC);
  3332. }
  3333. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3334. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3335. "SDE_DGM_1D_LUT_IGC_V",
  3336. psde->pipe_sblk->igc_blk[0].version >> 16);
  3337. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3338. PLANE_PROP_DMA_IGC);
  3339. }
  3340. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3341. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3342. "SDE_DGM_1D_LUT_GC_V",
  3343. psde->pipe_sblk->gc_blk[0].version >> 16);
  3344. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3345. PLANE_PROP_DMA_GC);
  3346. }
  3347. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3348. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3349. "SDE_SSPP_FP16_IGC_V",
  3350. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3351. msm_property_install_range(&psde->property_info, feature_name,
  3352. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3353. }
  3354. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3355. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3356. "SDE_SSPP_FP16_GC_V",
  3357. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3358. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3359. PLANE_PROP_FP16_GC);
  3360. }
  3361. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3362. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3363. "SDE_SSPP_FP16_CSC_V",
  3364. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3365. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3366. PLANE_PROP_FP16_CSC);
  3367. }
  3368. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3369. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3370. "SDE_SSPP_FP16_UNMULT_V",
  3371. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3372. msm_property_install_range(&psde->property_info, feature_name,
  3373. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3374. }
  3375. if (psde->features & BIT(SDE_SSPP_UCSC_IGC)) {
  3376. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3377. "SDE_SSPP_UCSC_IGC_V",
  3378. psde->pipe_sblk->ucsc_igc_blk[0].version >> 16);
  3379. msm_property_install_volatile_enum(&psde->property_info, feature_name,
  3380. 0x0, 0, ucsc_igc, ARRAY_SIZE(ucsc_igc), 0, PLANE_PROP_UCSC_IGC);
  3381. }
  3382. if (psde->features & BIT(SDE_SSPP_UCSC_GC)) {
  3383. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3384. "SDE_SSPP_UCSC_GC_V",
  3385. psde->pipe_sblk->ucsc_gc_blk[0].version >> 16);
  3386. msm_property_install_volatile_enum(&psde->property_info, feature_name,
  3387. 0x0, 0, ucsc_gc, ARRAY_SIZE(ucsc_gc), 0, PLANE_PROP_UCSC_GC);
  3388. }
  3389. if (psde->features & BIT(SDE_SSPP_UCSC_CSC)) {
  3390. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3391. "SDE_SSPP_UCSC_CSC_V",
  3392. psde->pipe_sblk->ucsc_csc_blk[0].version >> 16);
  3393. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3394. PLANE_PROP_UCSC_CSC);
  3395. }
  3396. if (psde->features & BIT(SDE_SSPP_UCSC_UNMULT)) {
  3397. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3398. "SDE_SSPP_UCSC_UNMULT_V",
  3399. psde->pipe_sblk->ucsc_unmult_blk[0].version >> 16);
  3400. msm_property_install_volatile_range(&psde->property_info, feature_name,
  3401. 0x0, 0, 1, 0, PLANE_PROP_UCSC_UNMULT);
  3402. }
  3403. if (psde->features & BIT(SDE_SSPP_UCSC_ALPHA_DITHER)) {
  3404. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3405. "SDE_SSPP_UCSC_ALPHA_DITHER_V",
  3406. psde->pipe_sblk->ucsc_alpha_dither_blk[0].version >> 16);
  3407. msm_property_install_volatile_range(&psde->property_info, feature_name,
  3408. 0x0, 0, 1, 0, PLANE_PROP_UCSC_ALPHA_DITHER);
  3409. }
  3410. }
  3411. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3412. u32 master_plane_id, struct sde_kms_info *info,
  3413. struct sde_mdss_cfg *catalog)
  3414. {
  3415. bool is_master = !psde->is_virtual;
  3416. const struct sde_format_extended *format_list;
  3417. u32 index;
  3418. int pipe_id;
  3419. if (is_master) {
  3420. format_list = psde->pipe_sblk->format_list;
  3421. } else {
  3422. format_list = psde->pipe_sblk->virt_format_list;
  3423. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3424. master_plane_id);
  3425. }
  3426. if (format_list) {
  3427. sde_kms_info_start(info, "pixel_formats");
  3428. while (format_list->fourcc_format) {
  3429. sde_kms_info_append_format(info,
  3430. format_list->fourcc_format,
  3431. format_list->modifier);
  3432. ++format_list;
  3433. }
  3434. sde_kms_info_stop(info);
  3435. }
  3436. if (psde->pipe_hw && catalog->qseed_hw_rev)
  3437. sde_kms_info_add_keyint(info, "scaler_step_ver", catalog->qseed_hw_rev);
  3438. sde_kms_info_add_keyint(info, "max_linewidth",
  3439. psde->pipe_sblk->maxlinewidth);
  3440. sde_kms_info_add_keyint(info, "max_upscale",
  3441. psde->pipe_sblk->maxupscale);
  3442. sde_kms_info_add_keyint(info, "max_downscale",
  3443. psde->pipe_sblk->maxdwnscale);
  3444. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3445. psde->pipe_sblk->maxhdeciexp);
  3446. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3447. psde->pipe_sblk->maxvdeciexp);
  3448. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3449. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3450. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3451. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3452. if (SDE_SSPP_VALID_VIG(psde->pipe))
  3453. pipe_id = psde->pipe - SSPP_VIG0;
  3454. else if (SDE_SSPP_VALID_DMA(psde->pipe))
  3455. pipe_id = psde->pipe - SSPP_DMA0;
  3456. else
  3457. pipe_id = -1;
  3458. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3459. index = (master_plane_id == 0) ? 0 : 1;
  3460. if (test_bit(SDE_FEATURE_DEMURA, catalog->features) &&
  3461. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3462. sde_kms_info_add_keyint(info, "demura_block",
  3463. catalog->demura_supported[psde->pipe][index]);
  3464. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3465. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3466. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3467. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3468. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3469. const struct sde_format_extended *inline_rot_fmt_list;
  3470. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3471. catalog->true_inline_rot_rev);
  3472. sde_kms_info_add_keyint(info,
  3473. "true_inline_dwnscale_rt",
  3474. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3475. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3476. sde_kms_info_add_keyint(info,
  3477. "true_inline_dwnscale_rt_numerator",
  3478. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3479. sde_kms_info_add_keyint(info,
  3480. "true_inline_dwnscale_rt_denominator",
  3481. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3482. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3483. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3484. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3485. psde->pipe_sblk->in_rot_maxheight);
  3486. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3487. if (inline_rot_fmt_list) {
  3488. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3489. while (inline_rot_fmt_list->fourcc_format) {
  3490. sde_kms_info_append_format(info,
  3491. inline_rot_fmt_list->fourcc_format,
  3492. inline_rot_fmt_list->modifier);
  3493. ++inline_rot_fmt_list;
  3494. }
  3495. sde_kms_info_stop(info);
  3496. }
  3497. }
  3498. }
  3499. /* helper to install properties which are common to planes and crtcs */
  3500. static void _sde_plane_install_properties(struct drm_plane *plane,
  3501. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3502. {
  3503. static const struct drm_prop_enum_list e_blend_op[] = {
  3504. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3505. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3506. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3507. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3508. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3509. };
  3510. static const struct drm_prop_enum_list e_src_config[] = {
  3511. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3512. };
  3513. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3514. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3515. {SDE_DRM_FB_SEC, "sec"},
  3516. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3517. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3518. };
  3519. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3520. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3521. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3522. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3523. };
  3524. struct sde_kms_info *info;
  3525. struct sde_plane *psde = to_sde_plane(plane);
  3526. bool is_master;
  3527. int zpos_max = 255;
  3528. int zpos_def = 0;
  3529. if (!plane || !psde) {
  3530. SDE_ERROR("invalid plane\n");
  3531. return;
  3532. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3533. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3534. !psde->pipe_hw, !psde->pipe_sblk);
  3535. return;
  3536. } else if (!catalog) {
  3537. SDE_ERROR("invalid catalog\n");
  3538. return;
  3539. }
  3540. psde->catalog = catalog;
  3541. is_master = !psde->is_virtual;
  3542. info = vzalloc(sizeof(struct sde_kms_info));
  3543. if (!info) {
  3544. SDE_ERROR("failed to allocate info memory\n");
  3545. return;
  3546. }
  3547. if (sde_is_custom_client()) {
  3548. if (catalog->mixer_count &&
  3549. catalog->mixer[0].sblk->maxblendstages) {
  3550. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3551. if (test_bit(SDE_FEATURE_BASE_LAYER, catalog->features) &&
  3552. (zpos_max > SDE_STAGE_MAX - 1))
  3553. zpos_max = SDE_STAGE_MAX - 1;
  3554. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3555. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3556. }
  3557. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3558. /* reserve zpos == 0 for primary planes */
  3559. zpos_def = drm_plane_index(plane) + 1;
  3560. }
  3561. msm_property_install_range(&psde->property_info, "zpos",
  3562. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3563. msm_property_install_range(&psde->property_info, "alpha",
  3564. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3565. /* linux default file descriptor range on each process */
  3566. msm_property_install_range(&psde->property_info, "input_fence",
  3567. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3568. if (is_master)
  3569. _sde_plane_install_master_only_properties(psde);
  3570. else
  3571. msm_property_install_enum(&psde->property_info,
  3572. "multirect_mode", 0x0, 0, e_multirect_mode,
  3573. ARRAY_SIZE(e_multirect_mode), 0,
  3574. PLANE_PROP_MULTIRECT_MODE);
  3575. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3576. msm_property_install_volatile_range(&psde->property_info,
  3577. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3578. sde_plane_rot_install_properties(plane, catalog);
  3579. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3580. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3581. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3582. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3583. PLANE_PROP_SRC_CONFIG);
  3584. if (psde->pipe_hw->ops.setup_solidfill)
  3585. msm_property_install_range(&psde->property_info, "color_fill",
  3586. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3587. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3588. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3589. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3590. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3591. msm_property_install_blob(&psde->property_info, "capabilities",
  3592. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3593. sde_kms_info_reset(info);
  3594. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3595. catalog);
  3596. _sde_plane_install_colorproc_properties(psde, info);
  3597. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3598. info->data, SDE_KMS_INFO_DATALEN(info),
  3599. PLANE_PROP_INFO);
  3600. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3601. 0x0, 0, e_fb_translation_mode,
  3602. ARRAY_SIZE(e_fb_translation_mode), 0,
  3603. PLANE_PROP_FB_TRANSLATION_MODE);
  3604. if (psde->pipe_hw->ops.set_ubwc_stats_roi)
  3605. msm_property_install_volatile_range(&psde->property_info, "ubwc_stats_roi",
  3606. 0, 0, ~0, 0, PLANE_PROP_UBWC_STATS_ROI);
  3607. vfree(info);
  3608. }
  3609. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3610. void __user *usr_ptr, struct sde_plane_state *pstate)
  3611. {
  3612. struct sde_drm_csc_v1 csc_v1;
  3613. int i;
  3614. if (!psde || !pstate) {
  3615. SDE_ERROR("invalid plane\n");
  3616. return;
  3617. }
  3618. pstate->csc_usr_ptr = NULL;
  3619. if (!usr_ptr) {
  3620. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3621. return;
  3622. }
  3623. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3624. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3625. return;
  3626. }
  3627. /* populate from user space */
  3628. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3629. pstate->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3630. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3631. pstate->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3632. pstate->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3633. }
  3634. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3635. pstate->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3636. pstate->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3637. }
  3638. pstate->csc_usr_ptr = &pstate->csc_cfg;
  3639. }
  3640. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3641. struct sde_plane_state *pstate, void __user *usr)
  3642. {
  3643. struct sde_drm_scaler_v1 scale_v1;
  3644. struct sde_hw_pixel_ext *pe;
  3645. int i;
  3646. if (!psde || !pstate) {
  3647. SDE_ERROR("invalid argument(s)\n");
  3648. return;
  3649. }
  3650. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3651. if (!usr) {
  3652. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3653. return;
  3654. }
  3655. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3656. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3657. return;
  3658. }
  3659. /* force property to be dirty, even if the pointer didn't change */
  3660. msm_property_set_dirty(&psde->property_info,
  3661. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3662. /* populate from user space */
  3663. pe = &pstate->pixel_ext;
  3664. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3665. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3666. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3667. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3668. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3669. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3670. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3671. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3672. }
  3673. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3674. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3675. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3676. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3677. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3678. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3679. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3680. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3681. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3682. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3683. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3684. }
  3685. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3686. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3687. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3688. }
  3689. static void _sde_plane_clear_predownscale_settings(
  3690. struct sde_plane_state *pstate)
  3691. {
  3692. pstate->pre_down.pre_downscale_x_0 = 0;
  3693. pstate->pre_down.pre_downscale_x_1 = 0;
  3694. pstate->pre_down.pre_downscale_y_0 = 0;
  3695. pstate->pre_down.pre_downscale_y_1 = 0;
  3696. }
  3697. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3698. struct sde_plane_state *pstate, void __user *usr)
  3699. {
  3700. struct sde_drm_scaler_v2 scale_v2;
  3701. struct sde_hw_pixel_ext *pe;
  3702. int i;
  3703. struct sde_hw_scaler3_cfg *cfg;
  3704. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3705. if (!psde || !pstate) {
  3706. SDE_ERROR("invalid argument(s)\n");
  3707. return;
  3708. }
  3709. cfg = &pstate->scaler3_cfg;
  3710. pd_cfg = &pstate->pre_down;
  3711. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3712. if (!usr) {
  3713. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3714. cfg->enable = 0;
  3715. _sde_plane_clear_predownscale_settings(pstate);
  3716. goto end;
  3717. }
  3718. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3719. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3720. return;
  3721. }
  3722. /* detach/ignore user data if 'disabled' */
  3723. if (!scale_v2.enable) {
  3724. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3725. cfg->enable = 0;
  3726. _sde_plane_clear_predownscale_settings(pstate);
  3727. goto end;
  3728. }
  3729. /* populate from user space */
  3730. sde_set_scaler_v2(cfg, &scale_v2);
  3731. if (_sde_plane_has_pre_downscale(psde)) {
  3732. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3733. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3734. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3735. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3736. }
  3737. pe = &pstate->pixel_ext;
  3738. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3739. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3740. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3741. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3742. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3743. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3744. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3745. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3746. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3747. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3748. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3749. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3750. }
  3751. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3752. end:
  3753. /* force property to be dirty, even if the pointer didn't change */
  3754. msm_property_set_dirty(&psde->property_info,
  3755. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3756. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3757. cfg->src_width[0], cfg->src_height[0],
  3758. cfg->dst_width, cfg->dst_height);
  3759. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3760. }
  3761. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3762. struct sde_plane_state *pstate, void __user *usr_ptr)
  3763. {
  3764. struct drm_clip_rect excl_rect_v1;
  3765. if (!psde || !pstate) {
  3766. SDE_ERROR("invalid argument(s)\n");
  3767. return;
  3768. }
  3769. if (!usr_ptr) {
  3770. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3771. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3772. return;
  3773. }
  3774. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3775. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3776. return;
  3777. }
  3778. /* populate from user space */
  3779. pstate->excl_rect.x = excl_rect_v1.x1;
  3780. pstate->excl_rect.y = excl_rect_v1.y1;
  3781. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3782. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3783. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3784. pstate->excl_rect.x, pstate->excl_rect.y,
  3785. pstate->excl_rect.w, pstate->excl_rect.h);
  3786. }
  3787. static void _sde_plane_set_ubwc_stats_roi(struct sde_plane *psde,
  3788. struct sde_plane_state *pstate, void __user *usr_ptr)
  3789. {
  3790. struct sde_drm_ubwc_stats_roi roi = {0};
  3791. if (!psde || !pstate) {
  3792. SDE_ERROR("invalid argument(s)\n");
  3793. return;
  3794. }
  3795. if (!usr_ptr) {
  3796. SDE_DEBUG_PLANE(psde, "ubwc roi disabled");
  3797. goto end;
  3798. }
  3799. if (copy_from_user(&roi, usr_ptr, sizeof(roi))) {
  3800. SDE_ERROR_PLANE(psde, "failed to copy ubwc stats roi");
  3801. return;
  3802. }
  3803. if (roi.y_coord0 > psde->pipe_cfg.src_rect.h || roi.y_coord1 > psde->pipe_cfg.src_rect.h) {
  3804. SDE_ERROR_PLANE(psde, "invalid ubwc roi y0 0x%x, y1 0x%x, src height 0x%x",
  3805. roi.y_coord0, roi.y_coord1, psde->pipe_cfg.src_rect.h);
  3806. memset(&roi, 0, sizeof(roi));
  3807. }
  3808. end:
  3809. SDE_EVT32(psde, roi.y_coord0, roi.y_coord1);
  3810. memcpy(&pstate->ubwc_stats_roi, &roi, sizeof(struct sde_drm_ubwc_stats_roi));
  3811. }
  3812. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3813. struct drm_plane_state *state, struct drm_property *property,
  3814. uint64_t val)
  3815. {
  3816. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3817. struct sde_plane_state *pstate;
  3818. int idx, ret = -EINVAL;
  3819. SDE_DEBUG_PLANE(psde, "\n");
  3820. if (!plane) {
  3821. SDE_ERROR("invalid plane\n");
  3822. } else if (!state) {
  3823. SDE_ERROR_PLANE(psde, "invalid state\n");
  3824. } else {
  3825. pstate = to_sde_plane_state(state);
  3826. ret = msm_property_atomic_set(&psde->property_info,
  3827. &pstate->property_state, property, val);
  3828. if (!ret) {
  3829. idx = msm_property_index(&psde->property_info,
  3830. property);
  3831. switch (idx) {
  3832. case PLANE_PROP_INPUT_FENCE:
  3833. _sde_plane_set_input_fence(psde, pstate, val);
  3834. break;
  3835. case PLANE_PROP_CSC_V1:
  3836. case PLANE_PROP_CSC_DMA_V1:
  3837. _sde_plane_set_csc_v1(psde, (void __user *)val, pstate);
  3838. break;
  3839. case PLANE_PROP_SCALER_V1:
  3840. _sde_plane_set_scaler_v1(psde, pstate,
  3841. (void *)(uintptr_t)val);
  3842. break;
  3843. case PLANE_PROP_SCALER_V2:
  3844. _sde_plane_set_scaler_v2(psde, pstate,
  3845. (void *)(uintptr_t)val);
  3846. break;
  3847. case PLANE_PROP_EXCL_RECT_V1:
  3848. _sde_plane_set_excl_rect_v1(psde, pstate,
  3849. (void *)(uintptr_t)val);
  3850. break;
  3851. case PLANE_PROP_UBWC_STATS_ROI:
  3852. _sde_plane_set_ubwc_stats_roi(psde, pstate,
  3853. (void __user *)(uintptr_t)val);
  3854. break;
  3855. default:
  3856. /* nothing to do */
  3857. break;
  3858. }
  3859. }
  3860. }
  3861. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3862. property->name, property->base.id, val, ret);
  3863. return ret;
  3864. }
  3865. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3866. const struct drm_plane_state *state,
  3867. struct drm_property *property, uint64_t *val)
  3868. {
  3869. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3870. struct sde_plane_state *pstate;
  3871. int ret = -EINVAL;
  3872. if (!plane) {
  3873. SDE_ERROR("invalid plane\n");
  3874. } else if (!state) {
  3875. SDE_ERROR("invalid state\n");
  3876. } else {
  3877. SDE_DEBUG_PLANE(psde, "\n");
  3878. pstate = to_sde_plane_state(state);
  3879. ret = msm_property_atomic_get(&psde->property_info,
  3880. &pstate->property_state, property, val);
  3881. }
  3882. return ret;
  3883. }
  3884. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3885. struct drm_plane_state *plane_state)
  3886. {
  3887. struct sde_plane *psde;
  3888. struct sde_plane_state *pstate;
  3889. struct drm_property *drm_prop;
  3890. enum msm_mdp_plane_property prop_idx;
  3891. if (!plane || !plane_state) {
  3892. SDE_ERROR("invalid params\n");
  3893. return -EINVAL;
  3894. }
  3895. psde = to_sde_plane(plane);
  3896. pstate = to_sde_plane_state(plane_state);
  3897. pstate->static_cache_state = CACHE_STATE_DISABLED;
  3898. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3899. uint64_t val = pstate->property_values[prop_idx].value;
  3900. uint64_t def;
  3901. int ret;
  3902. drm_prop = msm_property_index_to_drm_property(
  3903. &psde->property_info, prop_idx);
  3904. if (!drm_prop) {
  3905. /* not all props will be installed, based on caps */
  3906. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3907. prop_idx);
  3908. continue;
  3909. }
  3910. def = msm_property_get_default(&psde->property_info, prop_idx);
  3911. if (val == def)
  3912. continue;
  3913. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3914. drm_prop->name, prop_idx, val, def);
  3915. ret = sde_plane_atomic_set_property(plane, plane_state,
  3916. drm_prop, def);
  3917. if (ret) {
  3918. SDE_ERROR_PLANE(psde,
  3919. "set property failed, idx %d ret %d\n",
  3920. prop_idx, ret);
  3921. continue;
  3922. }
  3923. }
  3924. return 0;
  3925. }
  3926. static void sde_plane_destroy(struct drm_plane *plane)
  3927. {
  3928. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3929. SDE_DEBUG_PLANE(psde, "\n");
  3930. if (psde) {
  3931. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3932. if (psde->blob_info)
  3933. drm_property_blob_put(psde->blob_info);
  3934. msm_property_destroy(&psde->property_info);
  3935. mutex_destroy(&psde->lock);
  3936. /* this will destroy the states as well */
  3937. drm_plane_cleanup(plane);
  3938. if (psde->pipe_hw)
  3939. sde_hw_sspp_destroy(psde->pipe_hw);
  3940. kfree(psde);
  3941. }
  3942. }
  3943. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3944. {
  3945. struct sde_plane_state *pstate;
  3946. if (!state) {
  3947. SDE_ERROR("invalid arg state %d\n", !state);
  3948. return;
  3949. }
  3950. pstate = to_sde_plane_state(state);
  3951. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3952. SDE_DRM_FB_SEC) {
  3953. /* remove ref count for frame buffers */
  3954. if (state->fb) {
  3955. drm_framebuffer_put(state->fb);
  3956. state->fb = NULL;
  3957. }
  3958. }
  3959. }
  3960. static void sde_plane_destroy_state(struct drm_plane *plane,
  3961. struct drm_plane_state *state)
  3962. {
  3963. struct sde_plane *psde;
  3964. struct sde_plane_state *pstate;
  3965. if (!plane || !state) {
  3966. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3967. !plane, !state);
  3968. return;
  3969. }
  3970. psde = to_sde_plane(plane);
  3971. pstate = to_sde_plane_state(state);
  3972. SDE_DEBUG_PLANE(psde, "\n");
  3973. /* remove ref count for frame buffers */
  3974. if (state->fb)
  3975. drm_framebuffer_put(state->fb);
  3976. /* remove ref count for fence */
  3977. if (pstate->input_fence)
  3978. sde_sync_put(pstate->input_fence);
  3979. pstate->input_fence = 0;
  3980. /* destroy value helper */
  3981. msm_property_destroy_state(&psde->property_info, pstate,
  3982. &pstate->property_state);
  3983. }
  3984. static struct drm_plane_state *
  3985. sde_plane_duplicate_state(struct drm_plane *plane)
  3986. {
  3987. struct sde_plane *psde;
  3988. struct sde_plane_state *pstate;
  3989. struct sde_plane_state *old_state;
  3990. struct drm_property *drm_prop;
  3991. uint64_t input_fence_default;
  3992. if (!plane) {
  3993. SDE_ERROR("invalid plane\n");
  3994. return NULL;
  3995. } else if (!plane->state) {
  3996. SDE_ERROR("invalid plane state\n");
  3997. return NULL;
  3998. }
  3999. old_state = to_sde_plane_state(plane->state);
  4000. psde = to_sde_plane(plane);
  4001. if (old_state->cont_splash_populated) {
  4002. plane->state->crtc = NULL;
  4003. old_state->cont_splash_populated = false;
  4004. }
  4005. pstate = msm_property_alloc_state(&psde->property_info);
  4006. if (!pstate) {
  4007. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  4008. return NULL;
  4009. }
  4010. SDE_DEBUG_PLANE(psde, "\n");
  4011. /* duplicate value helper */
  4012. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  4013. &pstate->property_state, pstate->property_values);
  4014. /* clear out any input fence */
  4015. pstate->input_fence = 0;
  4016. input_fence_default = msm_property_get_default(
  4017. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  4018. drm_prop = msm_property_index_to_drm_property(
  4019. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  4020. if (msm_property_atomic_set(&psde->property_info,
  4021. &pstate->property_state, drm_prop,
  4022. input_fence_default))
  4023. SDE_DEBUG_PLANE(psde,
  4024. "error clearing duplicated input fence\n");
  4025. pstate->dirty = 0x0;
  4026. pstate->pending = false;
  4027. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  4028. /* reset layout offset */
  4029. if (pstate->layout_offset) {
  4030. if (pstate->layout_offset > 0)
  4031. pstate->base.crtc_x += pstate->layout_offset;
  4032. pstate->layout = SDE_LAYOUT_NONE;
  4033. pstate->layout_offset = 0;
  4034. }
  4035. return &pstate->base;
  4036. }
  4037. static void sde_plane_reset(struct drm_plane *plane)
  4038. {
  4039. struct sde_plane *psde;
  4040. struct sde_plane_state *pstate;
  4041. if (!plane) {
  4042. SDE_ERROR("invalid plane\n");
  4043. return;
  4044. }
  4045. psde = to_sde_plane(plane);
  4046. SDE_DEBUG_PLANE(psde, "\n");
  4047. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  4048. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  4049. return;
  4050. }
  4051. /* remove previous state, if present */
  4052. if (plane->state) {
  4053. sde_plane_destroy_state(plane, plane->state);
  4054. plane->state = 0;
  4055. }
  4056. pstate = msm_property_alloc_state(&psde->property_info);
  4057. if (!pstate) {
  4058. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  4059. return;
  4060. }
  4061. /* reset value helper */
  4062. msm_property_reset_state(&psde->property_info, pstate,
  4063. &pstate->property_state,
  4064. pstate->property_values);
  4065. pstate->base.plane = plane;
  4066. plane->state = &pstate->base;
  4067. }
  4068. void sde_plane_get_frame_data(struct drm_plane *plane,
  4069. struct sde_drm_plane_frame_data *data)
  4070. {
  4071. struct sde_plane *psde;
  4072. struct sde_plane_state *pstate;
  4073. struct sde_drm_ubwc_stats_data *ubwc_stats;
  4074. if (!plane) {
  4075. SDE_ERROR("invalid plane\n");
  4076. return;
  4077. }
  4078. psde = to_sde_plane(plane);
  4079. pstate = to_sde_plane_state(plane->state);
  4080. ubwc_stats = &data->ubwc_stats;
  4081. data->plane_id = DRMID(plane);
  4082. if (psde->pipe_hw->ops.get_ubwc_stats_data) {
  4083. memcpy(&ubwc_stats->roi, &pstate->ubwc_stats_roi,
  4084. sizeof(struct sde_drm_ubwc_stats_roi));
  4085. psde->pipe_hw->ops.get_ubwc_stats_data(psde->pipe_hw,
  4086. pstate->multirect_index, ubwc_stats);
  4087. }
  4088. if (psde->pipe_hw->ops.get_ubwc_error)
  4089. ubwc_stats->error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  4090. pstate->multirect_index);
  4091. if (psde->pipe_hw->ops.clear_ubwc_error && ubwc_stats->error)
  4092. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  4093. if (psde->pipe_hw->ops.get_meta_error)
  4094. ubwc_stats->meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  4095. pstate->multirect_index);
  4096. if (psde->pipe_hw->ops.clear_meta_error && ubwc_stats->meta_error)
  4097. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  4098. if (ubwc_stats->error || ubwc_stats->meta_error) {
  4099. SDE_EVT32(DRMID(plane), ubwc_stats->error, ubwc_stats->meta_error,
  4100. SDE_EVTLOG_ERROR);
  4101. SDE_DEBUG_PLANE(psde, "ubwc_error:0x%x meta_error:0x%x\n",
  4102. ubwc_stats->error, ubwc_stats->meta_error);
  4103. }
  4104. }
  4105. #if IS_ENABLED(CONFIG_DEBUG_FS)
  4106. static ssize_t _sde_plane_danger_read(struct file *file,
  4107. char __user *buff, size_t count, loff_t *ppos)
  4108. {
  4109. struct sde_kms *kms = file->private_data;
  4110. struct sde_mdss_cfg *cfg = kms->catalog;
  4111. int len = 0;
  4112. char buf[40] = {'\0'};
  4113. if (!cfg)
  4114. return -ENODEV;
  4115. if (*ppos)
  4116. return 0; /* the end */
  4117. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  4118. if (len < 0 || len >= sizeof(buf))
  4119. return 0;
  4120. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  4121. return -EFAULT;
  4122. *ppos += len; /* increase offset */
  4123. return len;
  4124. }
  4125. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  4126. {
  4127. struct drm_plane *plane;
  4128. drm_for_each_plane(plane, kms->dev) {
  4129. if (plane->fb && plane->state) {
  4130. sde_plane_danger_signal_ctrl(plane, enable);
  4131. SDE_DEBUG("plane:%d img:%dx%d ",
  4132. plane->base.id, plane->fb->width,
  4133. plane->fb->height);
  4134. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  4135. plane->state->src_x >> 16,
  4136. plane->state->src_y >> 16,
  4137. plane->state->src_w >> 16,
  4138. plane->state->src_h >> 16,
  4139. plane->state->crtc_x, plane->state->crtc_y,
  4140. plane->state->crtc_w, plane->state->crtc_h);
  4141. } else {
  4142. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  4143. }
  4144. }
  4145. }
  4146. static ssize_t _sde_plane_danger_write(struct file *file,
  4147. const char __user *user_buf, size_t count, loff_t *ppos)
  4148. {
  4149. struct sde_kms *kms = file->private_data;
  4150. struct sde_mdss_cfg *cfg = kms->catalog;
  4151. int disable_panic;
  4152. char buf[10];
  4153. if (!cfg)
  4154. return -EFAULT;
  4155. if (count >= sizeof(buf))
  4156. return -EFAULT;
  4157. if (copy_from_user(buf, user_buf, count))
  4158. return -EFAULT;
  4159. buf[count] = 0; /* end of string */
  4160. if (kstrtoint(buf, 0, &disable_panic))
  4161. return -EFAULT;
  4162. if (disable_panic) {
  4163. /* Disable panic signal for all active pipes */
  4164. SDE_DEBUG("Disabling danger:\n");
  4165. _sde_plane_set_danger_state(kms, false);
  4166. kms->has_danger_ctrl = false;
  4167. } else {
  4168. /* Enable panic signal for all active pipes */
  4169. SDE_DEBUG("Enabling danger:\n");
  4170. kms->has_danger_ctrl = true;
  4171. _sde_plane_set_danger_state(kms, true);
  4172. }
  4173. return count;
  4174. }
  4175. static const struct file_operations sde_plane_danger_enable = {
  4176. .open = simple_open,
  4177. .read = _sde_plane_danger_read,
  4178. .write = _sde_plane_danger_write,
  4179. };
  4180. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4181. {
  4182. struct sde_plane *psde;
  4183. struct sde_kms *kms;
  4184. struct msm_drm_private *priv;
  4185. const struct sde_sspp_sub_blks *sblk = 0;
  4186. const struct sde_sspp_cfg *cfg = 0;
  4187. if (!plane || !plane->dev) {
  4188. SDE_ERROR("invalid arguments\n");
  4189. return -EINVAL;
  4190. }
  4191. priv = plane->dev->dev_private;
  4192. if (!priv || !priv->kms) {
  4193. SDE_ERROR("invalid KMS reference\n");
  4194. return -EINVAL;
  4195. }
  4196. kms = to_sde_kms(priv->kms);
  4197. psde = to_sde_plane(plane);
  4198. if (psde && psde->pipe_hw)
  4199. cfg = psde->pipe_hw->cap;
  4200. if (cfg)
  4201. sblk = cfg->sblk;
  4202. if (!sblk)
  4203. return 0;
  4204. /* create overall sub-directory for the pipe */
  4205. psde->debugfs_root =
  4206. debugfs_create_dir(psde->pipe_name,
  4207. plane->dev->primary->debugfs_root);
  4208. if (!psde->debugfs_root)
  4209. return -ENOMEM;
  4210. /* don't error check these */
  4211. debugfs_create_x64("features", 0400,
  4212. psde->debugfs_root, &psde->features);
  4213. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  4214. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  4215. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  4216. debugfs_create_bool("default_scaling",
  4217. 0600,
  4218. psde->debugfs_root,
  4219. &psde->debugfs_default_scale);
  4220. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  4221. debugfs_create_u32("in_rot_max_downscale_rt_num",
  4222. 0600,
  4223. psde->debugfs_root,
  4224. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  4225. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  4226. 0600,
  4227. psde->debugfs_root,
  4228. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  4229. debugfs_create_u32("in_rot_max_downscale_nrt",
  4230. 0600,
  4231. psde->debugfs_root,
  4232. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  4233. debugfs_create_u32("in_rot_max_height",
  4234. 0600,
  4235. psde->debugfs_root,
  4236. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  4237. }
  4238. debugfs_create_u32("xin_id",
  4239. 0400,
  4240. psde->debugfs_root,
  4241. (u32 *) &cfg->xin_id);
  4242. debugfs_create_x32("creq_vblank",
  4243. 0600,
  4244. psde->debugfs_root,
  4245. (u32 *) &sblk->creq_vblank);
  4246. debugfs_create_x32("danger_vblank",
  4247. 0600,
  4248. psde->debugfs_root,
  4249. (u32 *) &sblk->danger_vblank);
  4250. debugfs_create_file("disable_danger",
  4251. 0600,
  4252. psde->debugfs_root,
  4253. kms, &sde_plane_danger_enable);
  4254. return 0;
  4255. }
  4256. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4257. {
  4258. struct sde_plane *psde;
  4259. if (!plane)
  4260. return;
  4261. psde = to_sde_plane(plane);
  4262. debugfs_remove_recursive(psde->debugfs_root);
  4263. }
  4264. #else
  4265. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4266. {
  4267. return 0;
  4268. }
  4269. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4270. {
  4271. }
  4272. #endif /* CONFIG_DEBUG_FS */
  4273. static int sde_plane_late_register(struct drm_plane *plane)
  4274. {
  4275. return _sde_plane_init_debugfs(plane);
  4276. }
  4277. static void sde_plane_early_unregister(struct drm_plane *plane)
  4278. {
  4279. _sde_plane_destroy_debugfs(plane);
  4280. }
  4281. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
  4282. static bool sde_plane_format_mod_supported(struct drm_plane *plane,
  4283. uint32_t format, uint64_t modifier)
  4284. {
  4285. return (sde_get_sde_format_ext(format, modifier) != NULL);
  4286. }
  4287. #endif
  4288. static const struct drm_plane_funcs sde_plane_funcs = {
  4289. .update_plane = drm_atomic_helper_update_plane,
  4290. .disable_plane = drm_atomic_helper_disable_plane,
  4291. .destroy = sde_plane_destroy,
  4292. .atomic_set_property = sde_plane_atomic_set_property,
  4293. .atomic_get_property = sde_plane_atomic_get_property,
  4294. .reset = sde_plane_reset,
  4295. .atomic_duplicate_state = sde_plane_duplicate_state,
  4296. .atomic_destroy_state = sde_plane_destroy_state,
  4297. .late_register = sde_plane_late_register,
  4298. .early_unregister = sde_plane_early_unregister,
  4299. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
  4300. .format_mod_supported = sde_plane_format_mod_supported,
  4301. #endif
  4302. };
  4303. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  4304. .prepare_fb = sde_plane_prepare_fb,
  4305. .cleanup_fb = sde_plane_cleanup_fb,
  4306. .atomic_check = sde_plane_atomic_check,
  4307. .atomic_update = sde_plane_atomic_update,
  4308. };
  4309. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  4310. {
  4311. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  4312. }
  4313. bool is_sde_plane_virtual(struct drm_plane *plane)
  4314. {
  4315. return plane ? to_sde_plane(plane)->is_virtual : false;
  4316. }
  4317. /* initialize plane */
  4318. struct drm_plane *sde_plane_init(struct drm_device *dev,
  4319. uint32_t pipe, bool primary_plane,
  4320. unsigned long possible_crtcs, u32 master_plane_id)
  4321. {
  4322. struct drm_plane *plane = NULL, *master_plane = NULL;
  4323. const struct sde_format_extended *format_list;
  4324. struct sde_plane *psde;
  4325. struct msm_drm_private *priv;
  4326. struct sde_kms *kms;
  4327. enum drm_plane_type type;
  4328. struct sde_vbif_clk_client clk_client;
  4329. int ret = -EINVAL;
  4330. if (!dev) {
  4331. SDE_ERROR("[%u]device is NULL\n", pipe);
  4332. goto exit;
  4333. }
  4334. priv = dev->dev_private;
  4335. if (!priv) {
  4336. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4337. goto exit;
  4338. }
  4339. if (!priv->kms) {
  4340. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4341. goto exit;
  4342. }
  4343. kms = to_sde_kms(priv->kms);
  4344. if (!kms->catalog) {
  4345. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4346. goto exit;
  4347. }
  4348. /* create and zero local structure */
  4349. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4350. if (!psde) {
  4351. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4352. ret = -ENOMEM;
  4353. goto exit;
  4354. }
  4355. /* cache local stuff for later */
  4356. plane = &psde->base;
  4357. psde->pipe = pipe;
  4358. psde->is_virtual = (master_plane_id != 0);
  4359. INIT_LIST_HEAD(&psde->mplane_list);
  4360. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4361. if (master_plane) {
  4362. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4363. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4364. }
  4365. /* initialize underlying h/w driver */
  4366. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog, psde->is_virtual,
  4367. &clk_client);
  4368. if (IS_ERR(psde->pipe_hw)) {
  4369. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4370. ret = PTR_ERR(psde->pipe_hw);
  4371. goto clean_plane;
  4372. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4373. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4374. goto clean_sspp;
  4375. }
  4376. if (test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, kms->catalog->features)) {
  4377. ret = sde_vbif_clk_register(kms, &clk_client);
  4378. if (ret) {
  4379. SDE_ERROR("failed to register vbif client %d\n",
  4380. clk_client.clk_ctrl);
  4381. goto clean_sspp;
  4382. }
  4383. }
  4384. /* cache features mask for later */
  4385. psde->features = psde->pipe_hw->cap->features_ext;
  4386. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4387. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4388. if (!psde->pipe_sblk) {
  4389. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4390. goto clean_sspp;
  4391. }
  4392. if (psde->is_virtual)
  4393. format_list = psde->pipe_sblk->virt_format_list;
  4394. else
  4395. format_list = psde->pipe_sblk->format_list;
  4396. psde->nformats = sde_populate_formats(format_list,
  4397. psde->formats,
  4398. 0,
  4399. ARRAY_SIZE(psde->formats));
  4400. if (!psde->nformats) {
  4401. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4402. goto clean_sspp;
  4403. }
  4404. if (primary_plane)
  4405. type = DRM_PLANE_TYPE_PRIMARY;
  4406. else
  4407. type = DRM_PLANE_TYPE_OVERLAY;
  4408. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4409. psde->formats, psde->nformats,
  4410. NULL, type, NULL);
  4411. if (ret)
  4412. goto clean_sspp;
  4413. /* Populate static array of plane property flags */
  4414. _sde_plane_map_prop_to_dirty_bits();
  4415. /* success! finalize initialization */
  4416. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4417. msm_property_init(&psde->property_info, &plane->base, dev,
  4418. priv->plane_property, psde->property_data,
  4419. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4420. sizeof(struct sde_plane_state));
  4421. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4422. /* save user friendly pipe name for later */
  4423. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4424. mutex_init(&psde->lock);
  4425. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4426. pipe, plane->base.id, master_plane_id);
  4427. return plane;
  4428. clean_sspp:
  4429. if (psde && psde->pipe_hw)
  4430. sde_hw_sspp_destroy(psde->pipe_hw);
  4431. clean_plane:
  4432. kfree(psde);
  4433. exit:
  4434. return ERR_PTR(ret);
  4435. }
  4436. void sde_plane_add_data_to_minidump_va(struct drm_plane *plane)
  4437. {
  4438. struct sde_plane *sde_plane;
  4439. struct sde_plane_state *pstate;
  4440. sde_plane = to_sde_plane(plane);
  4441. pstate = to_sde_plane_state(plane->state);
  4442. sde_mini_dump_add_va_region("sde_plane", sizeof(*sde_plane), sde_plane);
  4443. sde_mini_dump_add_va_region("plane_state", sizeof(*pstate), pstate);
  4444. }