hfi.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/delay.h>
  7. #include <linux/slab.h>
  8. #include <linux/random.h>
  9. #include <asm/errno.h>
  10. #include <linux/timer.h>
  11. #include <media/cam_icp.h>
  12. #include <linux/iopoll.h>
  13. #include "cam_io_util.h"
  14. #include "hfi_reg.h"
  15. #include "hfi_sys_defs.h"
  16. #include "hfi_session_defs.h"
  17. #include "hfi_intf.h"
  18. #include "cam_icp_hw_mgr_intf.h"
  19. #include "cam_debug_util.h"
  20. #include "cam_compat.h"
  21. #define HFI_VERSION_INFO_MAJOR_VAL 1
  22. #define HFI_VERSION_INFO_MINOR_VAL 1
  23. #define HFI_VERSION_INFO_STEP_VAL 0
  24. #define HFI_VERSION_INFO_STEP_VAL 0
  25. #define HFI_VERSION_INFO_MAJOR_BMSK 0xFF000000
  26. #define HFI_VERSION_INFO_MAJOR_SHFT 24
  27. #define HFI_VERSION_INFO_MINOR_BMSK 0xFFFF00
  28. #define HFI_VERSION_INFO_MINOR_SHFT 8
  29. #define HFI_VERSION_INFO_STEP_BMSK 0xFF
  30. #define HFI_VERSION_INFO_STEP_SHFT 0
  31. /* TO DO Lower timeout value */
  32. #define HFI_POLL_DELAY_US 10
  33. #define HFI_POLL_TIMEOUT_US 1500000
  34. static struct hfi_info *g_hfi;
  35. unsigned int g_icp_mmu_hdl;
  36. static DEFINE_MUTEX(hfi_cmd_q_mutex);
  37. static DEFINE_MUTEX(hfi_msg_q_mutex);
  38. static void hfi_irq_raise(struct hfi_info *hfi)
  39. {
  40. if (hfi->ops.irq_raise)
  41. hfi->ops.irq_raise(hfi->priv);
  42. }
  43. static void hfi_irq_enable(struct hfi_info *hfi)
  44. {
  45. if (hfi->ops.irq_enable)
  46. hfi->ops.irq_enable(hfi->priv);
  47. }
  48. static void __iomem *hfi_iface_addr(struct hfi_info *hfi)
  49. {
  50. void __iomem *ret = NULL;
  51. if (hfi->ops.iface_addr)
  52. ret = hfi->ops.iface_addr(hfi->priv);
  53. return IS_ERR_OR_NULL(ret) ? NULL : ret;
  54. }
  55. static void hfi_queue_dump(uint32_t *dwords, int count)
  56. {
  57. int i;
  58. int rows;
  59. int remaining;
  60. rows = count / 4;
  61. remaining = count % 4;
  62. for (i = 0; i < rows; i++, dwords += 4)
  63. CAM_DBG(CAM_HFI,
  64. "word[%04d]: 0x%08x 0x%08x 0x%08x 0x%08x",
  65. i * 4, dwords[0], dwords[1], dwords[2], dwords[3]);
  66. if (remaining == 1)
  67. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x", rows * 4, dwords[0]);
  68. else if (remaining == 2)
  69. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x 0x%08x",
  70. rows * 4, dwords[0], dwords[1]);
  71. else if (remaining == 3)
  72. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x 0x%08x 0x%08x",
  73. rows * 4, dwords[0], dwords[1], dwords[2]);
  74. }
  75. void cam_hfi_queue_dump(void)
  76. {
  77. struct hfi_mem_info *hfi_mem = &g_hfi->map;
  78. struct hfi_qtbl *qtbl;
  79. struct hfi_q_hdr *q_hdr;
  80. uint32_t *dwords;
  81. int num_dwords;
  82. if (!hfi_mem) {
  83. CAM_ERR(CAM_HFI, "hfi mem info NULL... unable to dump queues");
  84. return;
  85. }
  86. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  87. CAM_DBG(CAM_HFI,
  88. "qtbl header: version=0x%08x tbl_size=%u numq=%u qhdr_size=%u",
  89. qtbl->q_tbl_hdr.qtbl_version,
  90. qtbl->q_tbl_hdr.qtbl_size,
  91. qtbl->q_tbl_hdr.qtbl_num_q,
  92. qtbl->q_tbl_hdr.qtbl_qhdr_size);
  93. q_hdr = &qtbl->q_hdr[Q_CMD];
  94. CAM_DBG(CAM_HFI,
  95. "cmd_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
  96. hfi_mem->cmd_q.iova,
  97. q_hdr->qhdr_q_size,
  98. q_hdr->qhdr_read_idx,
  99. q_hdr->qhdr_write_idx);
  100. dwords = (uint32_t *)hfi_mem->cmd_q.kva;
  101. num_dwords = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  102. hfi_queue_dump(dwords, num_dwords);
  103. q_hdr = &qtbl->q_hdr[Q_MSG];
  104. CAM_DBG(CAM_HFI,
  105. "msg_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
  106. hfi_mem->msg_q.iova,
  107. q_hdr->qhdr_q_size,
  108. q_hdr->qhdr_read_idx,
  109. q_hdr->qhdr_write_idx);
  110. dwords = (uint32_t *)hfi_mem->msg_q.kva;
  111. num_dwords = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  112. hfi_queue_dump(dwords, num_dwords);
  113. }
  114. int hfi_write_cmd(void *cmd_ptr)
  115. {
  116. uint32_t size_in_words, empty_space, new_write_idx, read_idx, temp;
  117. uint32_t *write_q, *write_ptr;
  118. struct hfi_qtbl *q_tbl;
  119. struct hfi_q_hdr *q;
  120. int rc = 0;
  121. if (!cmd_ptr) {
  122. CAM_ERR(CAM_HFI, "command is null");
  123. return -EINVAL;
  124. }
  125. mutex_lock(&hfi_cmd_q_mutex);
  126. if (!g_hfi) {
  127. CAM_ERR(CAM_HFI, "HFI interface not setup");
  128. rc = -ENODEV;
  129. goto err;
  130. }
  131. if (g_hfi->hfi_state != HFI_READY ||
  132. !g_hfi->cmd_q_state) {
  133. CAM_ERR(CAM_HFI, "HFI state: %u, cmd q state: %u",
  134. g_hfi->hfi_state, g_hfi->cmd_q_state);
  135. rc = -ENODEV;
  136. goto err;
  137. }
  138. q_tbl = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  139. q = &q_tbl->q_hdr[Q_CMD];
  140. write_q = (uint32_t *)g_hfi->map.cmd_q.kva;
  141. size_in_words = (*(uint32_t *)cmd_ptr) >> BYTE_WORD_SHIFT;
  142. if (!size_in_words) {
  143. CAM_DBG(CAM_HFI, "failed");
  144. rc = -EINVAL;
  145. goto err;
  146. }
  147. read_idx = q->qhdr_read_idx;
  148. empty_space = (q->qhdr_write_idx >= read_idx) ?
  149. (q->qhdr_q_size - (q->qhdr_write_idx - read_idx)) :
  150. (read_idx - q->qhdr_write_idx);
  151. if (empty_space <= size_in_words) {
  152. CAM_ERR(CAM_HFI, "failed: empty space %u, size_in_words %u",
  153. empty_space, size_in_words);
  154. rc = -EIO;
  155. goto err;
  156. }
  157. new_write_idx = q->qhdr_write_idx + size_in_words;
  158. write_ptr = (uint32_t *)(write_q + q->qhdr_write_idx);
  159. if (new_write_idx < q->qhdr_q_size) {
  160. memcpy(write_ptr, (uint8_t *)cmd_ptr,
  161. size_in_words << BYTE_WORD_SHIFT);
  162. } else {
  163. new_write_idx -= q->qhdr_q_size;
  164. temp = (size_in_words - new_write_idx) << BYTE_WORD_SHIFT;
  165. memcpy(write_ptr, (uint8_t *)cmd_ptr, temp);
  166. memcpy(write_q, (uint8_t *)cmd_ptr + temp,
  167. new_write_idx << BYTE_WORD_SHIFT);
  168. }
  169. /*
  170. * To make sure command data in a command queue before
  171. * updating write index
  172. */
  173. wmb();
  174. q->qhdr_write_idx = new_write_idx;
  175. /*
  176. * Before raising interrupt make sure command data is ready for
  177. * firmware to process
  178. */
  179. wmb();
  180. hfi_irq_raise(g_hfi);
  181. err:
  182. mutex_unlock(&hfi_cmd_q_mutex);
  183. return rc;
  184. }
  185. int hfi_read_message(uint32_t *pmsg, uint8_t q_id,
  186. uint32_t *words_read)
  187. {
  188. struct hfi_qtbl *q_tbl_ptr;
  189. struct hfi_q_hdr *q;
  190. uint32_t new_read_idx, size_in_words, word_diff, temp;
  191. uint32_t *read_q, *read_ptr, *write_ptr;
  192. uint32_t size_upper_bound = 0;
  193. int rc = 0;
  194. if (!pmsg) {
  195. CAM_ERR(CAM_HFI, "Invalid msg");
  196. return -EINVAL;
  197. }
  198. if (q_id > Q_DBG) {
  199. CAM_ERR(CAM_HFI, "Invalid q :%u", q_id);
  200. return -EINVAL;
  201. }
  202. mutex_lock(&hfi_msg_q_mutex);
  203. if (!g_hfi) {
  204. CAM_ERR(CAM_HFI, "hfi not set up yet");
  205. rc = -ENODEV;
  206. goto err;
  207. }
  208. if ((g_hfi->hfi_state != HFI_READY) ||
  209. !g_hfi->msg_q_state) {
  210. CAM_ERR(CAM_HFI, "hfi state: %u, msg q state: %u",
  211. g_hfi->hfi_state, g_hfi->msg_q_state);
  212. rc = -ENODEV;
  213. goto err;
  214. }
  215. q_tbl_ptr = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  216. q = &q_tbl_ptr->q_hdr[q_id];
  217. if (q->qhdr_read_idx == q->qhdr_write_idx) {
  218. CAM_DBG(CAM_HFI, "Q not ready, state:%u, r idx:%u, w idx:%u",
  219. g_hfi->hfi_state, q->qhdr_read_idx, q->qhdr_write_idx);
  220. rc = -EIO;
  221. goto err;
  222. }
  223. if (q_id == Q_MSG) {
  224. read_q = (uint32_t *)g_hfi->map.msg_q.kva;
  225. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS;
  226. } else {
  227. read_q = (uint32_t *)g_hfi->map.dbg_q.kva;
  228. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_IN_WORDS;
  229. }
  230. read_ptr = (uint32_t *)(read_q + q->qhdr_read_idx);
  231. write_ptr = (uint32_t *)(read_q + q->qhdr_write_idx);
  232. if (write_ptr > read_ptr)
  233. size_in_words = write_ptr - read_ptr;
  234. else {
  235. word_diff = read_ptr - write_ptr;
  236. if (q_id == Q_MSG)
  237. size_in_words = (ICP_MSG_Q_SIZE_IN_BYTES >>
  238. BYTE_WORD_SHIFT) - word_diff;
  239. else
  240. size_in_words = (ICP_DBG_Q_SIZE_IN_BYTES >>
  241. BYTE_WORD_SHIFT) - word_diff;
  242. }
  243. if ((size_in_words == 0) ||
  244. (size_in_words > size_upper_bound)) {
  245. CAM_ERR(CAM_HFI, "invalid HFI message packet size - 0x%08x",
  246. size_in_words << BYTE_WORD_SHIFT);
  247. q->qhdr_read_idx = q->qhdr_write_idx;
  248. rc = -EIO;
  249. goto err;
  250. }
  251. new_read_idx = q->qhdr_read_idx + size_in_words;
  252. if (new_read_idx < q->qhdr_q_size) {
  253. memcpy(pmsg, read_ptr, size_in_words << BYTE_WORD_SHIFT);
  254. } else {
  255. new_read_idx -= q->qhdr_q_size;
  256. temp = (size_in_words - new_read_idx) << BYTE_WORD_SHIFT;
  257. memcpy(pmsg, read_ptr, temp);
  258. memcpy((uint8_t *)pmsg + temp, read_q,
  259. new_read_idx << BYTE_WORD_SHIFT);
  260. }
  261. q->qhdr_read_idx = new_read_idx;
  262. *words_read = size_in_words;
  263. /* Memory Barrier to make sure message
  264. * queue parameters are updated after read
  265. */
  266. wmb();
  267. err:
  268. mutex_unlock(&hfi_msg_q_mutex);
  269. return rc;
  270. }
  271. int hfi_cmd_ubwc_config(uint32_t *ubwc_cfg)
  272. {
  273. uint8_t *prop;
  274. struct hfi_cmd_prop *dbg_prop;
  275. uint32_t size = 0;
  276. size = sizeof(struct hfi_cmd_prop) +
  277. sizeof(struct hfi_cmd_ubwc_cfg);
  278. CAM_DBG(CAM_HFI,
  279. "size of ubwc %u, ubwc_cfg [rd-0x%x,wr-0x%x]",
  280. size, ubwc_cfg[0], ubwc_cfg[1]);
  281. prop = kzalloc(size, GFP_KERNEL);
  282. if (!prop)
  283. return -ENOMEM;
  284. dbg_prop = (struct hfi_cmd_prop *)prop;
  285. dbg_prop->size = size;
  286. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  287. dbg_prop->num_prop = 1;
  288. dbg_prop->prop_data[0] = HFI_PROP_SYS_UBWC_CFG;
  289. dbg_prop->prop_data[1] = ubwc_cfg[0];
  290. dbg_prop->prop_data[2] = ubwc_cfg[1];
  291. hfi_write_cmd(prop);
  292. kfree(prop);
  293. return 0;
  294. }
  295. int hfi_cmd_ubwc_config_ext(uint32_t *ubwc_ipe_cfg,
  296. uint32_t *ubwc_bps_cfg)
  297. {
  298. uint8_t *prop;
  299. struct hfi_cmd_prop *dbg_prop;
  300. uint32_t size = 0;
  301. size = sizeof(struct hfi_cmd_prop) +
  302. sizeof(struct hfi_cmd_ubwc_cfg_ext);
  303. CAM_DBG(CAM_HFI,
  304. "size of ubwc %u, ubwc_ipe_cfg[rd-0x%x,wr-0x%x] ubwc_bps_cfg[rd-0x%x,wr-0x%x]",
  305. size, ubwc_ipe_cfg[0], ubwc_ipe_cfg[1],
  306. ubwc_bps_cfg[0], ubwc_bps_cfg[1]);
  307. prop = kzalloc(size, GFP_KERNEL);
  308. if (!prop)
  309. return -ENOMEM;
  310. dbg_prop = (struct hfi_cmd_prop *)prop;
  311. dbg_prop->size = size;
  312. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  313. dbg_prop->num_prop = 1;
  314. dbg_prop->prop_data[0] = HFI_PROPERTY_SYS_UBWC_CONFIG_EX;
  315. dbg_prop->prop_data[1] = ubwc_bps_cfg[0];
  316. dbg_prop->prop_data[2] = ubwc_bps_cfg[1];
  317. dbg_prop->prop_data[3] = ubwc_ipe_cfg[0];
  318. dbg_prop->prop_data[4] = ubwc_ipe_cfg[1];
  319. hfi_write_cmd(prop);
  320. kfree(prop);
  321. return 0;
  322. }
  323. int hfi_enable_ipe_bps_pc(bool enable, uint32_t core_info)
  324. {
  325. uint8_t *prop;
  326. struct hfi_cmd_prop *dbg_prop;
  327. uint32_t size = 0;
  328. size = sizeof(struct hfi_cmd_prop) +
  329. sizeof(struct hfi_ipe_bps_pc);
  330. prop = kzalloc(size, GFP_KERNEL);
  331. if (!prop)
  332. return -ENOMEM;
  333. dbg_prop = (struct hfi_cmd_prop *)prop;
  334. dbg_prop->size = size;
  335. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  336. dbg_prop->num_prop = 1;
  337. dbg_prop->prop_data[0] = HFI_PROP_SYS_IPEBPS_PC;
  338. dbg_prop->prop_data[1] = enable;
  339. dbg_prop->prop_data[2] = core_info;
  340. hfi_write_cmd(prop);
  341. kfree(prop);
  342. return 0;
  343. }
  344. int hfi_set_debug_level(u64 icp_dbg_type, uint32_t lvl)
  345. {
  346. uint8_t *prop;
  347. struct hfi_cmd_prop *dbg_prop;
  348. uint32_t size = 0, val;
  349. val = HFI_DEBUG_MSG_LOW |
  350. HFI_DEBUG_MSG_MEDIUM |
  351. HFI_DEBUG_MSG_HIGH |
  352. HFI_DEBUG_MSG_ERROR |
  353. HFI_DEBUG_MSG_FATAL |
  354. HFI_DEBUG_MSG_PERF |
  355. HFI_DEBUG_CFG_WFI |
  356. HFI_DEBUG_CFG_ARM9WD;
  357. if (lvl > val)
  358. return -EINVAL;
  359. size = sizeof(struct hfi_cmd_prop) +
  360. sizeof(struct hfi_debug);
  361. prop = kzalloc(size, GFP_KERNEL);
  362. if (!prop)
  363. return -ENOMEM;
  364. dbg_prop = (struct hfi_cmd_prop *)prop;
  365. dbg_prop->size = size;
  366. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  367. dbg_prop->num_prop = 1;
  368. dbg_prop->prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  369. dbg_prop->prop_data[1] = lvl;
  370. dbg_prop->prop_data[2] = icp_dbg_type;
  371. hfi_write_cmd(prop);
  372. kfree(prop);
  373. return 0;
  374. }
  375. int hfi_set_fw_dump_level(uint32_t lvl)
  376. {
  377. uint8_t *prop = NULL;
  378. struct hfi_cmd_prop *fw_dump_level_switch_prop = NULL;
  379. uint32_t size = 0;
  380. CAM_DBG(CAM_HFI, "fw dump ENTER");
  381. size = sizeof(struct hfi_cmd_prop) + sizeof(lvl);
  382. prop = kzalloc(size, GFP_KERNEL);
  383. if (!prop)
  384. return -ENOMEM;
  385. fw_dump_level_switch_prop = (struct hfi_cmd_prop *)prop;
  386. fw_dump_level_switch_prop->size = size;
  387. fw_dump_level_switch_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  388. fw_dump_level_switch_prop->num_prop = 1;
  389. fw_dump_level_switch_prop->prop_data[0] = HFI_PROP_SYS_FW_DUMP_CFG;
  390. fw_dump_level_switch_prop->prop_data[1] = lvl;
  391. CAM_DBG(CAM_HFI, "prop->size = %d\n"
  392. "prop->pkt_type = %d\n"
  393. "prop->num_prop = %d\n"
  394. "prop->prop_data[0] = %d\n"
  395. "prop->prop_data[1] = %d\n",
  396. fw_dump_level_switch_prop->size,
  397. fw_dump_level_switch_prop->pkt_type,
  398. fw_dump_level_switch_prop->num_prop,
  399. fw_dump_level_switch_prop->prop_data[0],
  400. fw_dump_level_switch_prop->prop_data[1]);
  401. hfi_write_cmd(prop);
  402. kfree(prop);
  403. return 0;
  404. }
  405. void hfi_send_system_cmd(uint32_t type, uint64_t data, uint32_t size)
  406. {
  407. switch (type) {
  408. case HFI_CMD_SYS_INIT: {
  409. struct hfi_cmd_sys_init init;
  410. memset(&init, 0, sizeof(init));
  411. init.size = sizeof(struct hfi_cmd_sys_init);
  412. init.pkt_type = type;
  413. hfi_write_cmd(&init);
  414. }
  415. break;
  416. case HFI_CMD_SYS_PC_PREP: {
  417. struct hfi_cmd_pc_prep prep;
  418. prep.size = sizeof(struct hfi_cmd_pc_prep);
  419. prep.pkt_type = type;
  420. hfi_write_cmd(&prep);
  421. }
  422. break;
  423. case HFI_CMD_SYS_SET_PROPERTY: {
  424. struct hfi_cmd_prop prop;
  425. if ((uint32_t)data == (uint32_t)HFI_PROP_SYS_DEBUG_CFG) {
  426. prop.size = sizeof(struct hfi_cmd_prop);
  427. prop.pkt_type = type;
  428. prop.num_prop = 1;
  429. prop.prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  430. hfi_write_cmd(&prop);
  431. }
  432. }
  433. break;
  434. case HFI_CMD_SYS_GET_PROPERTY:
  435. break;
  436. case HFI_CMD_SYS_PING: {
  437. struct hfi_cmd_ping_pkt ping;
  438. ping.size = sizeof(struct hfi_cmd_ping_pkt);
  439. ping.pkt_type = type;
  440. ping.user_data = (uint64_t)data;
  441. hfi_write_cmd(&ping);
  442. }
  443. break;
  444. case HFI_CMD_SYS_RESET: {
  445. struct hfi_cmd_sys_reset_pkt reset;
  446. reset.size = sizeof(struct hfi_cmd_sys_reset_pkt);
  447. reset.pkt_type = type;
  448. reset.user_data = (uint64_t)data;
  449. hfi_write_cmd(&reset);
  450. }
  451. break;
  452. case HFI_CMD_IPEBPS_CREATE_HANDLE: {
  453. struct hfi_cmd_create_handle handle;
  454. handle.size = sizeof(struct hfi_cmd_create_handle);
  455. handle.pkt_type = type;
  456. handle.handle_type = (uint32_t)data;
  457. handle.user_data1 = 0;
  458. hfi_write_cmd(&handle);
  459. }
  460. break;
  461. case HFI_CMD_IPEBPS_ASYNC_COMMAND_INDIRECT:
  462. break;
  463. default:
  464. CAM_ERR(CAM_HFI, "command not supported :%d", type);
  465. break;
  466. }
  467. }
  468. int hfi_get_hw_caps(void *query_buf)
  469. {
  470. int i = 0;
  471. struct cam_icp_query_cap_cmd *query_cmd = NULL;
  472. if (!query_buf) {
  473. CAM_ERR(CAM_HFI, "query buf is NULL");
  474. return -EINVAL;
  475. }
  476. query_cmd = (struct cam_icp_query_cap_cmd *)query_buf;
  477. query_cmd->fw_version.major = 0x12;
  478. query_cmd->fw_version.minor = 0x12;
  479. query_cmd->fw_version.revision = 0x12;
  480. query_cmd->api_version.major = 0x13;
  481. query_cmd->api_version.minor = 0x13;
  482. query_cmd->api_version.revision = 0x13;
  483. query_cmd->num_ipe = 2;
  484. query_cmd->num_bps = 1;
  485. for (i = 0; i < CAM_ICP_DEV_TYPE_MAX; i++) {
  486. query_cmd->dev_ver[i].dev_type = i;
  487. query_cmd->dev_ver[i].hw_ver.major = 0x34 + i;
  488. query_cmd->dev_ver[i].hw_ver.minor = 0x34 + i;
  489. query_cmd->dev_ver[i].hw_ver.incr = 0x34 + i;
  490. }
  491. return 0;
  492. }
  493. int cam_hfi_resume(struct hfi_mem_info *hfi_mem)
  494. {
  495. int rc = 0;
  496. uint32_t fw_version, status = 0;
  497. void __iomem *icp_base = hfi_iface_addr(g_hfi);
  498. if (!icp_base) {
  499. CAM_ERR(CAM_HFI, "invalid HFI interface address");
  500. return -EINVAL;
  501. }
  502. if (cam_common_read_poll_timeout(icp_base +
  503. HFI_REG_ICP_HOST_INIT_RESPONSE,
  504. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
  505. 0x1, ICP_INIT_RESP_SUCCESS, &status)) {
  506. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  507. status);
  508. return -ETIMEDOUT;
  509. }
  510. hfi_irq_enable(g_hfi);
  511. fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION);
  512. CAM_DBG(CAM_HFI, "fw version : [%x]", fw_version);
  513. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova, icp_base + HFI_REG_QTBL_PTR);
  514. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  515. icp_base + HFI_REG_SFR_PTR);
  516. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  517. icp_base + HFI_REG_SHARED_MEM_PTR);
  518. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  519. icp_base + HFI_REG_SHARED_MEM_SIZE);
  520. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  521. icp_base + HFI_REG_SECONDARY_HEAP_PTR);
  522. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  523. icp_base + HFI_REG_SECONDARY_HEAP_SIZE);
  524. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  525. icp_base + HFI_REG_QDSS_IOVA);
  526. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  527. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  528. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  529. icp_base + HFI_REG_IO_REGION_IOVA);
  530. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  531. icp_base + HFI_REG_IO_REGION_SIZE);
  532. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  533. icp_base + HFI_REG_IO2_REGION_IOVA);
  534. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  535. icp_base + HFI_REG_IO2_REGION_SIZE);
  536. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.iova,
  537. icp_base + HFI_REG_FWUNCACHED_REGION_IOVA);
  538. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.len,
  539. icp_base + HFI_REG_FWUNCACHED_REGION_SIZE);
  540. CAM_DBG(CAM_HFI, "IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  541. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  542. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  543. CAM_DBG(CAM_HFI, "FwUncached : [0x%x 0x%x] Shared [0x%x 0x%x]",
  544. hfi_mem->fw_uncached.iova, hfi_mem->fw_uncached.len,
  545. hfi_mem->shmem.iova, hfi_mem->shmem.len);
  546. CAM_DBG(CAM_HFI, "SecHeap : [0x%x 0x%x] QDSS [0x%x 0x%x]",
  547. hfi_mem->sec_heap.iova, hfi_mem->sec_heap.len,
  548. hfi_mem->qdss.iova, hfi_mem->qdss.len);
  549. CAM_DBG(CAM_HFI, "QTbl : [0x%x 0x%x] Sfr [0x%x 0x%x]",
  550. hfi_mem->qtbl.iova, hfi_mem->qtbl.len,
  551. hfi_mem->sfr_buf.iova, hfi_mem->sfr_buf.len);
  552. return rc;
  553. }
  554. int cam_hfi_init(struct hfi_mem_info *hfi_mem, const struct hfi_ops *hfi_ops,
  555. void *priv, uint8_t event_driven_mode)
  556. {
  557. int rc = 0;
  558. uint32_t status = 0;
  559. struct hfi_qtbl *qtbl;
  560. struct hfi_qtbl_hdr *qtbl_hdr;
  561. struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr, *dbg_q_hdr;
  562. struct sfr_buf *sfr_buffer;
  563. void __iomem *icp_base;
  564. if (!hfi_mem || !hfi_ops || !priv) {
  565. CAM_ERR(CAM_HFI,
  566. "invalid arg: hfi_mem=%pK hfi_ops=%pK priv=%pK",
  567. hfi_mem, hfi_ops, priv);
  568. return -EINVAL;
  569. }
  570. mutex_lock(&hfi_cmd_q_mutex);
  571. mutex_lock(&hfi_msg_q_mutex);
  572. if (!g_hfi) {
  573. g_hfi = kzalloc(sizeof(struct hfi_info), GFP_KERNEL);
  574. if (!g_hfi) {
  575. rc = -ENOMEM;
  576. goto alloc_fail;
  577. }
  578. }
  579. if (g_hfi->hfi_state != HFI_DEINIT) {
  580. CAM_ERR(CAM_HFI, "hfi_init: invalid state");
  581. rc = -EINVAL;
  582. goto regions_fail;
  583. }
  584. memcpy(&g_hfi->map, hfi_mem, sizeof(g_hfi->map));
  585. g_hfi->hfi_state = HFI_DEINIT;
  586. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  587. qtbl_hdr = &qtbl->q_tbl_hdr;
  588. qtbl_hdr->qtbl_version = 0xFFFFFFFF;
  589. qtbl_hdr->qtbl_size = sizeof(struct hfi_qtbl);
  590. qtbl_hdr->qtbl_qhdr0_offset = sizeof(struct hfi_qtbl_hdr);
  591. qtbl_hdr->qtbl_qhdr_size = sizeof(struct hfi_q_hdr);
  592. qtbl_hdr->qtbl_num_q = ICP_HFI_NUMBER_OF_QS;
  593. qtbl_hdr->qtbl_num_active_q = ICP_HFI_NUMBER_OF_QS;
  594. /* setup host-to-firmware command queue */
  595. cmd_q_hdr = &qtbl->q_hdr[Q_CMD];
  596. cmd_q_hdr->qhdr_status = QHDR_ACTIVE;
  597. cmd_q_hdr->qhdr_start_addr = hfi_mem->cmd_q.iova;
  598. cmd_q_hdr->qhdr_q_size = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  599. cmd_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  600. cmd_q_hdr->qhdr_pkt_drop_cnt = RESET;
  601. cmd_q_hdr->qhdr_read_idx = RESET;
  602. cmd_q_hdr->qhdr_write_idx = RESET;
  603. /* setup firmware-to-Host message queue */
  604. msg_q_hdr = &qtbl->q_hdr[Q_MSG];
  605. msg_q_hdr->qhdr_status = QHDR_ACTIVE;
  606. msg_q_hdr->qhdr_start_addr = hfi_mem->msg_q.iova;
  607. msg_q_hdr->qhdr_q_size = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  608. msg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  609. msg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  610. msg_q_hdr->qhdr_read_idx = RESET;
  611. msg_q_hdr->qhdr_write_idx = RESET;
  612. /* setup firmware-to-Host message queue */
  613. dbg_q_hdr = &qtbl->q_hdr[Q_DBG];
  614. dbg_q_hdr->qhdr_status = QHDR_ACTIVE;
  615. dbg_q_hdr->qhdr_start_addr = hfi_mem->dbg_q.iova;
  616. dbg_q_hdr->qhdr_q_size = ICP_DBG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  617. dbg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  618. dbg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  619. dbg_q_hdr->qhdr_read_idx = RESET;
  620. dbg_q_hdr->qhdr_write_idx = RESET;
  621. sfr_buffer = (struct sfr_buf *)hfi_mem->sfr_buf.kva;
  622. sfr_buffer->size = ICP_MSG_SFR_SIZE_IN_BYTES;
  623. switch (event_driven_mode) {
  624. case INTR_MODE:
  625. cmd_q_hdr->qhdr_type = Q_CMD;
  626. cmd_q_hdr->qhdr_rx_wm = SET;
  627. cmd_q_hdr->qhdr_tx_wm = SET;
  628. cmd_q_hdr->qhdr_rx_req = SET;
  629. cmd_q_hdr->qhdr_tx_req = RESET;
  630. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  631. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  632. msg_q_hdr->qhdr_type = Q_MSG;
  633. msg_q_hdr->qhdr_rx_wm = SET;
  634. msg_q_hdr->qhdr_tx_wm = SET;
  635. msg_q_hdr->qhdr_rx_req = SET;
  636. msg_q_hdr->qhdr_tx_req = RESET;
  637. msg_q_hdr->qhdr_rx_irq_status = RESET;
  638. msg_q_hdr->qhdr_tx_irq_status = RESET;
  639. dbg_q_hdr->qhdr_type = Q_DBG;
  640. dbg_q_hdr->qhdr_rx_wm = SET;
  641. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  642. dbg_q_hdr->qhdr_rx_req = RESET;
  643. dbg_q_hdr->qhdr_tx_req = RESET;
  644. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  645. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  646. break;
  647. case POLL_MODE:
  648. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_POLL_MODE_2 |
  649. RX_EVENT_POLL_MODE_2;
  650. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_POLL_MODE_2 |
  651. RX_EVENT_POLL_MODE_2;
  652. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_POLL_MODE_2 |
  653. RX_EVENT_POLL_MODE_2;
  654. break;
  655. case WM_MODE:
  656. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_DRIVEN_MODE_2 |
  657. RX_EVENT_DRIVEN_MODE_2;
  658. cmd_q_hdr->qhdr_rx_wm = SET;
  659. cmd_q_hdr->qhdr_tx_wm = SET;
  660. cmd_q_hdr->qhdr_rx_req = RESET;
  661. cmd_q_hdr->qhdr_tx_req = SET;
  662. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  663. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  664. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_DRIVEN_MODE_2 |
  665. RX_EVENT_DRIVEN_MODE_2;
  666. msg_q_hdr->qhdr_rx_wm = SET;
  667. msg_q_hdr->qhdr_tx_wm = SET;
  668. msg_q_hdr->qhdr_rx_req = SET;
  669. msg_q_hdr->qhdr_tx_req = RESET;
  670. msg_q_hdr->qhdr_rx_irq_status = RESET;
  671. msg_q_hdr->qhdr_tx_irq_status = RESET;
  672. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_DRIVEN_MODE_2 |
  673. RX_EVENT_DRIVEN_MODE_2;
  674. dbg_q_hdr->qhdr_rx_wm = SET;
  675. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  676. dbg_q_hdr->qhdr_rx_req = RESET;
  677. dbg_q_hdr->qhdr_tx_req = RESET;
  678. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  679. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  680. break;
  681. default:
  682. CAM_ERR(CAM_HFI, "Invalid event driven mode :%u",
  683. event_driven_mode);
  684. break;
  685. }
  686. g_hfi->ops = *hfi_ops;
  687. g_hfi->priv = priv;
  688. icp_base = hfi_iface_addr(g_hfi);
  689. if (!icp_base) {
  690. CAM_ERR(CAM_HFI, "invalid HFI interface address");
  691. rc = -EINVAL;
  692. goto regions_fail;
  693. }
  694. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova,
  695. icp_base + HFI_REG_QTBL_PTR);
  696. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  697. icp_base + HFI_REG_SFR_PTR);
  698. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  699. icp_base + HFI_REG_SHARED_MEM_PTR);
  700. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  701. icp_base + HFI_REG_SHARED_MEM_SIZE);
  702. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  703. icp_base + HFI_REG_SECONDARY_HEAP_PTR);
  704. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  705. icp_base + HFI_REG_SECONDARY_HEAP_SIZE);
  706. cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_SET,
  707. icp_base + HFI_REG_HOST_ICP_INIT_REQUEST);
  708. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  709. icp_base + HFI_REG_QDSS_IOVA);
  710. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  711. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  712. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  713. icp_base + HFI_REG_IO_REGION_IOVA);
  714. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  715. icp_base + HFI_REG_IO_REGION_SIZE);
  716. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  717. icp_base + HFI_REG_IO2_REGION_IOVA);
  718. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  719. icp_base + HFI_REG_IO2_REGION_SIZE);
  720. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.iova,
  721. icp_base + HFI_REG_FWUNCACHED_REGION_IOVA);
  722. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.len,
  723. icp_base + HFI_REG_FWUNCACHED_REGION_SIZE);
  724. CAM_DBG(CAM_HFI, "IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  725. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  726. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  727. CAM_DBG(CAM_HFI, "FwUncached : [0x%x 0x%x] Shared [0x%x 0x%x]",
  728. hfi_mem->fw_uncached.iova, hfi_mem->fw_uncached.len,
  729. hfi_mem->shmem.iova, hfi_mem->shmem.len);
  730. CAM_DBG(CAM_HFI, "SecHeap : [0x%x 0x%x] QDSS [0x%x 0x%x]",
  731. hfi_mem->sec_heap.iova, hfi_mem->sec_heap.len,
  732. hfi_mem->qdss.iova, hfi_mem->qdss.len);
  733. CAM_DBG(CAM_HFI, "QTbl : [0x%x 0x%x] Sfr [0x%x 0x%x]",
  734. hfi_mem->qtbl.iova, hfi_mem->qtbl.len,
  735. hfi_mem->sfr_buf.iova, hfi_mem->sfr_buf.len);
  736. if (cam_common_read_poll_timeout(icp_base +
  737. HFI_REG_ICP_HOST_INIT_RESPONSE,
  738. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
  739. 0x1, ICP_INIT_RESP_SUCCESS, &status)) {
  740. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  741. status);
  742. rc = -ETIMEDOUT;
  743. goto regions_fail;
  744. }
  745. CAM_DBG(CAM_HFI, "ICP fw version: 0x%x",
  746. cam_io_r(icp_base + HFI_REG_FW_VERSION));
  747. g_hfi->hfi_state = HFI_READY;
  748. g_hfi->cmd_q_state = true;
  749. g_hfi->msg_q_state = true;
  750. hfi_irq_enable(g_hfi);
  751. mutex_unlock(&hfi_cmd_q_mutex);
  752. mutex_unlock(&hfi_msg_q_mutex);
  753. return rc;
  754. regions_fail:
  755. kfree(g_hfi);
  756. g_hfi = NULL;
  757. alloc_fail:
  758. mutex_unlock(&hfi_cmd_q_mutex);
  759. mutex_unlock(&hfi_msg_q_mutex);
  760. return rc;
  761. }
  762. void cam_hfi_deinit(void)
  763. {
  764. mutex_lock(&hfi_cmd_q_mutex);
  765. mutex_lock(&hfi_msg_q_mutex);
  766. if (!g_hfi) {
  767. CAM_ERR(CAM_HFI, "hfi path not established yet");
  768. goto err;
  769. }
  770. g_hfi->cmd_q_state = false;
  771. g_hfi->msg_q_state = false;
  772. cam_free_clear((void *)g_hfi);
  773. g_hfi = NULL;
  774. err:
  775. mutex_unlock(&hfi_cmd_q_mutex);
  776. mutex_unlock(&hfi_msg_q_mutex);
  777. }