hal_api.h 61 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_API_H_
  19. #define _HAL_API_H_
  20. #include "qdf_types.h"
  21. #include "qdf_util.h"
  22. #include "qdf_atomic.h"
  23. #include "hal_internal.h"
  24. #include "hif.h"
  25. #include "hif_io32.h"
  26. #include "qdf_platform.h"
  27. /* calculate the register address offset from bar0 of shadow register x */
  28. #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490)
  29. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x000008FC
  30. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  31. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  32. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  33. #elif defined(QCA_WIFI_QCA6290) || defined(QCA_WIFI_QCN9000)
  34. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x00003024
  35. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  36. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  37. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  38. #elif defined(QCA_WIFI_QCA6750)
  39. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x00000504
  40. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  41. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  42. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  43. #else
  44. #define SHADOW_REGISTER(x) 0
  45. #endif /* QCA_WIFI_QCA6390 || QCA_WIFI_QCA6490 || QCA_WIFI_QCA6750 */
  46. #define MAX_UNWINDOWED_ADDRESS 0x80000
  47. #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \
  48. defined(QCA_WIFI_QCN9000) || defined(QCA_WIFI_QCA6750)
  49. #define WINDOW_ENABLE_BIT 0x40000000
  50. #else
  51. #define WINDOW_ENABLE_BIT 0x80000000
  52. #endif
  53. #define WINDOW_REG_ADDRESS 0x310C
  54. #define WINDOW_SHIFT 19
  55. #define WINDOW_VALUE_MASK 0x3F
  56. #define WINDOW_START MAX_UNWINDOWED_ADDRESS
  57. #define WINDOW_RANGE_MASK 0x7FFFF
  58. /*
  59. * BAR + 4K is always accessible, any access outside this
  60. * space requires force wake procedure.
  61. * OFFSET = 4K - 32 bytes = 0xFE0
  62. */
  63. #define MAPPED_REF_OFF 0xFE0
  64. #ifdef ENABLE_VERBOSE_DEBUG
  65. static inline void
  66. hal_set_verbose_debug(bool flag)
  67. {
  68. is_hal_verbose_debug_enabled = flag;
  69. }
  70. #endif
  71. #ifdef ENABLE_HAL_SOC_STATS
  72. #define HAL_STATS_INC(_handle, _field, _delta) \
  73. { \
  74. if (likely(_handle)) \
  75. _handle->stats._field += _delta; \
  76. }
  77. #else
  78. #define HAL_STATS_INC(_handle, _field, _delta)
  79. #endif
  80. #ifdef ENABLE_HAL_REG_WR_HISTORY
  81. #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \
  82. hal_reg_wr_fail_history_add(hal_soc, offset, wr_val, rd_val)
  83. void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc,
  84. uint32_t offset,
  85. uint32_t wr_val,
  86. uint32_t rd_val);
  87. static inline int hal_history_get_next_index(qdf_atomic_t *table_index,
  88. int array_size)
  89. {
  90. int record_index = qdf_atomic_inc_return(table_index);
  91. return record_index & (array_size - 1);
  92. }
  93. #else
  94. #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \
  95. hal_err("write failed at reg offset 0x%x, write 0x%x read 0x%x\n", \
  96. offset, \
  97. wr_val, \
  98. rd_val)
  99. #endif
  100. /**
  101. * hal_reg_write_result_check() - check register writing result
  102. * @hal_soc: HAL soc handle
  103. * @offset: register offset to read
  104. * @exp_val: the expected value of register
  105. * @ret_confirm: result confirm flag
  106. *
  107. * Return: none
  108. */
  109. static inline void hal_reg_write_result_check(struct hal_soc *hal_soc,
  110. uint32_t offset,
  111. uint32_t exp_val)
  112. {
  113. uint32_t value;
  114. value = qdf_ioread32(hal_soc->dev_base_addr + offset);
  115. if (exp_val != value) {
  116. HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, exp_val, value);
  117. HAL_STATS_INC(hal_soc, reg_write_fail, 1);
  118. }
  119. }
  120. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) || \
  121. !defined(QCA_WIFI_QCA6750)
  122. static inline void hal_lock_reg_access(struct hal_soc *soc,
  123. unsigned long *flags)
  124. {
  125. qdf_spin_lock_irqsave(&soc->register_access_lock);
  126. }
  127. static inline void hal_unlock_reg_access(struct hal_soc *soc,
  128. unsigned long *flags)
  129. {
  130. qdf_spin_unlock_irqrestore(&soc->register_access_lock);
  131. }
  132. #else
  133. static inline void hal_lock_reg_access(struct hal_soc *soc,
  134. unsigned long *flags)
  135. {
  136. pld_lock_reg_window(soc->qdf_dev->dev, flags);
  137. }
  138. static inline void hal_unlock_reg_access(struct hal_soc *soc,
  139. unsigned long *flags)
  140. {
  141. pld_unlock_reg_window(soc->qdf_dev->dev, flags);
  142. }
  143. #endif
  144. #ifdef PCIE_REG_WINDOW_LOCAL_NO_CACHE
  145. /**
  146. * hal_select_window_confirm() - write remap window register and
  147. check writing result
  148. *
  149. */
  150. static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
  151. uint32_t offset)
  152. {
  153. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  154. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  155. WINDOW_ENABLE_BIT | window);
  156. hal_soc->register_window = window;
  157. hal_reg_write_result_check(hal_soc, WINDOW_REG_ADDRESS,
  158. WINDOW_ENABLE_BIT | window);
  159. }
  160. #else
  161. static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
  162. uint32_t offset)
  163. {
  164. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  165. if (window != hal_soc->register_window) {
  166. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  167. WINDOW_ENABLE_BIT | window);
  168. hal_soc->register_window = window;
  169. hal_reg_write_result_check(
  170. hal_soc,
  171. WINDOW_REG_ADDRESS,
  172. WINDOW_ENABLE_BIT | window);
  173. }
  174. }
  175. #endif
  176. static inline qdf_iomem_t hal_get_window_address(struct hal_soc *hal_soc,
  177. qdf_iomem_t addr)
  178. {
  179. return hal_soc->ops->hal_get_window_address(hal_soc, addr);
  180. }
  181. static inline void hal_tx_init_cmd_credit_ring(hal_soc_handle_t hal_soc_hdl,
  182. hal_ring_handle_t hal_ring_hdl)
  183. {
  184. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  185. return hal_soc->ops->hal_tx_init_cmd_credit_ring(hal_soc_hdl,
  186. hal_ring_hdl);
  187. }
  188. /**
  189. * hal_write32_mb() - Access registers to update configuration
  190. * @hal_soc: hal soc handle
  191. * @offset: offset address from the BAR
  192. * @value: value to write
  193. *
  194. * Return: None
  195. *
  196. * Description: Register address space is split below:
  197. * SHADOW REGION UNWINDOWED REGION WINDOWED REGION
  198. * |--------------------|-------------------|------------------|
  199. * BAR NO FORCE WAKE BAR+4K FORCE WAKE BAR+512K FORCE WAKE
  200. *
  201. * 1. Any access to the shadow region, doesn't need force wake
  202. * and windowing logic to access.
  203. * 2. Any access beyond BAR + 4K:
  204. * If init_phase enabled, no force wake is needed and access
  205. * should be based on windowed or unwindowed access.
  206. * If init_phase disabled, force wake is needed and access
  207. * should be based on windowed or unwindowed access.
  208. *
  209. * note1: WINDOW_RANGE_MASK = (1 << WINDOW_SHIFT) -1
  210. * note2: 1 << WINDOW_SHIFT = MAX_UNWINDOWED_ADDRESS
  211. * note3: WINDOW_VALUE_MASK = big enough that trying to write past
  212. * that window would be a bug
  213. */
  214. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
  215. !defined(QCA_WIFI_QCA6750)
  216. static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
  217. uint32_t value)
  218. {
  219. unsigned long flags;
  220. qdf_iomem_t new_addr;
  221. if (!hal_soc->use_register_windowing ||
  222. offset < MAX_UNWINDOWED_ADDRESS) {
  223. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  224. } else if (hal_soc->static_window_map) {
  225. new_addr = hal_get_window_address(hal_soc,
  226. hal_soc->dev_base_addr + offset);
  227. qdf_iowrite32(new_addr, value);
  228. } else {
  229. hal_lock_reg_access(hal_soc, &flags);
  230. hal_select_window_confirm(hal_soc, offset);
  231. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  232. (offset & WINDOW_RANGE_MASK), value);
  233. hal_unlock_reg_access(hal_soc, &flags);
  234. }
  235. }
  236. #define hal_write32_mb_confirm(_hal_soc, _offset, _value) \
  237. hal_write32_mb(_hal_soc, _offset, _value)
  238. #else
  239. static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
  240. uint32_t value)
  241. {
  242. int ret;
  243. unsigned long flags;
  244. qdf_iomem_t new_addr;
  245. /* Region < BAR + 4K can be directly accessed */
  246. if (offset < MAPPED_REF_OFF) {
  247. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  248. return;
  249. }
  250. /* Region greater than BAR + 4K */
  251. if (!hal_soc->init_phase) {
  252. ret = hif_force_wake_request(hal_soc->hif_handle);
  253. if (ret) {
  254. hal_err("Wake up request failed");
  255. qdf_check_state_before_panic();
  256. return;
  257. }
  258. }
  259. if (!hal_soc->use_register_windowing ||
  260. offset < MAX_UNWINDOWED_ADDRESS) {
  261. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  262. } else if (hal_soc->static_window_map) {
  263. new_addr = hal_get_window_address(
  264. hal_soc,
  265. hal_soc->dev_base_addr + offset);
  266. qdf_iowrite32(new_addr, value);
  267. } else {
  268. hal_lock_reg_access(hal_soc, &flags);
  269. hal_select_window_confirm(hal_soc, offset);
  270. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  271. (offset & WINDOW_RANGE_MASK), value);
  272. hal_unlock_reg_access(hal_soc, &flags);
  273. }
  274. if (!hal_soc->init_phase) {
  275. ret = hif_force_wake_release(hal_soc->hif_handle);
  276. if (ret) {
  277. hal_err("Wake up release failed");
  278. qdf_check_state_before_panic();
  279. return;
  280. }
  281. }
  282. }
  283. /**
  284. * hal_write32_mb_confirm() - write register and check wirting result
  285. *
  286. */
  287. static inline void hal_write32_mb_confirm(struct hal_soc *hal_soc,
  288. uint32_t offset,
  289. uint32_t value)
  290. {
  291. int ret;
  292. unsigned long flags;
  293. qdf_iomem_t new_addr;
  294. /* Region < BAR + 4K can be directly accessed */
  295. if (offset < MAPPED_REF_OFF) {
  296. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  297. return;
  298. }
  299. /* Region greater than BAR + 4K */
  300. if (!hal_soc->init_phase) {
  301. ret = hif_force_wake_request(hal_soc->hif_handle);
  302. if (ret) {
  303. hal_err("Wake up request failed");
  304. qdf_check_state_before_panic();
  305. return;
  306. }
  307. }
  308. if (!hal_soc->use_register_windowing ||
  309. offset < MAX_UNWINDOWED_ADDRESS) {
  310. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  311. hal_reg_write_result_check(hal_soc, offset,
  312. value);
  313. } else if (hal_soc->static_window_map) {
  314. new_addr = hal_get_window_address(
  315. hal_soc,
  316. hal_soc->dev_base_addr + offset);
  317. qdf_iowrite32(new_addr, value);
  318. hal_reg_write_result_check(hal_soc,
  319. new_addr - hal_soc->dev_base_addr,
  320. value);
  321. } else {
  322. hal_lock_reg_access(hal_soc, &flags);
  323. hal_select_window_confirm(hal_soc, offset);
  324. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  325. (offset & WINDOW_RANGE_MASK), value);
  326. hal_reg_write_result_check(
  327. hal_soc,
  328. WINDOW_START + (offset & WINDOW_RANGE_MASK),
  329. value);
  330. hal_unlock_reg_access(hal_soc, &flags);
  331. }
  332. if (!hal_soc->init_phase) {
  333. ret = hif_force_wake_release(hal_soc->hif_handle);
  334. if (ret) {
  335. hal_err("Wake up release failed");
  336. qdf_check_state_before_panic();
  337. return;
  338. }
  339. }
  340. }
  341. #endif
  342. /**
  343. * hal_write_address_32_mb - write a value to a register
  344. *
  345. */
  346. static inline
  347. void hal_write_address_32_mb(struct hal_soc *hal_soc,
  348. qdf_iomem_t addr, uint32_t value, bool wr_confirm)
  349. {
  350. uint32_t offset;
  351. if (!hal_soc->use_register_windowing)
  352. return qdf_iowrite32(addr, value);
  353. offset = addr - hal_soc->dev_base_addr;
  354. if (qdf_unlikely(wr_confirm))
  355. hal_write32_mb_confirm(hal_soc, offset, value);
  356. else
  357. hal_write32_mb(hal_soc, offset, value);
  358. }
  359. #ifdef DP_HAL_MULTIWINDOW_DIRECT_ACCESS
  360. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  361. struct hal_srng *srng,
  362. void __iomem *addr,
  363. uint32_t value)
  364. {
  365. qdf_iowrite32(addr, value);
  366. }
  367. #elif defined(FEATURE_HAL_DELAYED_REG_WRITE)
  368. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  369. struct hal_srng *srng,
  370. void __iomem *addr,
  371. uint32_t value)
  372. {
  373. hal_delayed_reg_write(hal_soc, srng, addr, value);
  374. }
  375. #else
  376. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  377. struct hal_srng *srng,
  378. void __iomem *addr,
  379. uint32_t value)
  380. {
  381. hal_write_address_32_mb(hal_soc, addr, value, false);
  382. }
  383. #endif
  384. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
  385. !defined(QCA_WIFI_QCA6750)
  386. /**
  387. * hal_read32_mb() - Access registers to read configuration
  388. * @hal_soc: hal soc handle
  389. * @offset: offset address from the BAR
  390. * @value: value to write
  391. *
  392. * Description: Register address space is split below:
  393. * SHADOW REGION UNWINDOWED REGION WINDOWED REGION
  394. * |--------------------|-------------------|------------------|
  395. * BAR NO FORCE WAKE BAR+4K FORCE WAKE BAR+512K FORCE WAKE
  396. *
  397. * 1. Any access to the shadow region, doesn't need force wake
  398. * and windowing logic to access.
  399. * 2. Any access beyond BAR + 4K:
  400. * If init_phase enabled, no force wake is needed and access
  401. * should be based on windowed or unwindowed access.
  402. * If init_phase disabled, force wake is needed and access
  403. * should be based on windowed or unwindowed access.
  404. *
  405. * Return: < 0 for failure/>= 0 for success
  406. */
  407. static inline uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
  408. {
  409. uint32_t ret;
  410. unsigned long flags;
  411. qdf_iomem_t new_addr;
  412. if (!hal_soc->use_register_windowing ||
  413. offset < MAX_UNWINDOWED_ADDRESS) {
  414. return qdf_ioread32(hal_soc->dev_base_addr + offset);
  415. } else if (hal_soc->static_window_map) {
  416. new_addr = hal_get_window_address(hal_soc, hal_soc->dev_base_addr + offset);
  417. return qdf_ioread32(new_addr);
  418. }
  419. hal_lock_reg_access(hal_soc, &flags);
  420. hal_select_window_confirm(hal_soc, offset);
  421. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  422. (offset & WINDOW_RANGE_MASK));
  423. hal_unlock_reg_access(hal_soc, &flags);
  424. return ret;
  425. }
  426. #else
  427. static
  428. uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
  429. {
  430. uint32_t ret;
  431. unsigned long flags;
  432. qdf_iomem_t new_addr;
  433. /* Region < BAR + 4K can be directly accessed */
  434. if (offset < MAPPED_REF_OFF)
  435. return qdf_ioread32(hal_soc->dev_base_addr + offset);
  436. if ((!hal_soc->init_phase) &&
  437. hif_force_wake_request(hal_soc->hif_handle)) {
  438. hal_err("Wake up request failed");
  439. qdf_check_state_before_panic();
  440. return 0;
  441. }
  442. if (!hal_soc->use_register_windowing ||
  443. offset < MAX_UNWINDOWED_ADDRESS) {
  444. ret = qdf_ioread32(hal_soc->dev_base_addr + offset);
  445. } else if (hal_soc->static_window_map) {
  446. new_addr = hal_get_window_address(
  447. hal_soc,
  448. hal_soc->dev_base_addr + offset);
  449. ret = qdf_ioread32(new_addr);
  450. } else {
  451. hal_lock_reg_access(hal_soc, &flags);
  452. hal_select_window_confirm(hal_soc, offset);
  453. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  454. (offset & WINDOW_RANGE_MASK));
  455. hal_unlock_reg_access(hal_soc, &flags);
  456. }
  457. if ((!hal_soc->init_phase) &&
  458. hif_force_wake_release(hal_soc->hif_handle)) {
  459. hal_err("Wake up release failed");
  460. qdf_check_state_before_panic();
  461. return 0;
  462. }
  463. return ret;
  464. }
  465. #endif
  466. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  467. /**
  468. * hal_dump_reg_write_srng_stats() - dump SRNG reg write stats
  469. * @hal_soc: HAL soc handle
  470. *
  471. * Return: none
  472. */
  473. void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl);
  474. /**
  475. * hal_dump_reg_write_stats() - dump reg write stats
  476. * @hal_soc: HAL soc handle
  477. *
  478. * Return: none
  479. */
  480. void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl);
  481. /**
  482. * hal_get_reg_write_pending_work() - get the number of entries
  483. * pending in the workqueue to be processed.
  484. * @hal_soc: HAL soc handle
  485. *
  486. * Returns: the number of entries pending to be processed
  487. */
  488. int hal_get_reg_write_pending_work(void *hal_soc);
  489. #else
  490. static inline void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
  491. {
  492. }
  493. static inline void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
  494. {
  495. }
  496. static inline int hal_get_reg_write_pending_work(void *hal_soc)
  497. {
  498. return 0;
  499. }
  500. #endif
  501. /**
  502. * hal_read_address_32_mb() - Read 32-bit value from the register
  503. * @soc: soc handle
  504. * @addr: register address to read
  505. *
  506. * Return: 32-bit value
  507. */
  508. static inline
  509. uint32_t hal_read_address_32_mb(struct hal_soc *soc,
  510. qdf_iomem_t addr)
  511. {
  512. uint32_t offset;
  513. uint32_t ret;
  514. if (!soc->use_register_windowing)
  515. return qdf_ioread32(addr);
  516. offset = addr - soc->dev_base_addr;
  517. ret = hal_read32_mb(soc, offset);
  518. return ret;
  519. }
  520. /**
  521. * hal_attach - Initialize HAL layer
  522. * @hif_handle: Opaque HIF handle
  523. * @qdf_dev: QDF device
  524. *
  525. * Return: Opaque HAL SOC handle
  526. * NULL on failure (if given ring is not available)
  527. *
  528. * This function should be called as part of HIF initialization (for accessing
  529. * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle()
  530. */
  531. void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev);
  532. /**
  533. * hal_detach - Detach HAL layer
  534. * @hal_soc: HAL SOC handle
  535. *
  536. * This function should be called as part of HIF detach
  537. *
  538. */
  539. extern void hal_detach(void *hal_soc);
  540. /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */
  541. enum hal_ring_type {
  542. REO_DST = 0,
  543. REO_EXCEPTION = 1,
  544. REO_REINJECT = 2,
  545. REO_CMD = 3,
  546. REO_STATUS = 4,
  547. TCL_DATA = 5,
  548. TCL_CMD_CREDIT = 6,
  549. TCL_STATUS = 7,
  550. CE_SRC = 8,
  551. CE_DST = 9,
  552. CE_DST_STATUS = 10,
  553. WBM_IDLE_LINK = 11,
  554. SW2WBM_RELEASE = 12,
  555. WBM2SW_RELEASE = 13,
  556. RXDMA_BUF = 14,
  557. RXDMA_DST = 15,
  558. RXDMA_MONITOR_BUF = 16,
  559. RXDMA_MONITOR_STATUS = 17,
  560. RXDMA_MONITOR_DST = 18,
  561. RXDMA_MONITOR_DESC = 19,
  562. DIR_BUF_RX_DMA_SRC = 20,
  563. #ifdef WLAN_FEATURE_CIF_CFR
  564. WIFI_POS_SRC,
  565. #endif
  566. MAX_RING_TYPES
  567. };
  568. #define HAL_SRNG_LMAC_RING 0x80000000
  569. /* SRNG flags passed in hal_srng_params.flags */
  570. #define HAL_SRNG_MSI_SWAP 0x00000008
  571. #define HAL_SRNG_RING_PTR_SWAP 0x00000010
  572. #define HAL_SRNG_DATA_TLV_SWAP 0x00000020
  573. #define HAL_SRNG_LOW_THRES_INTR_ENABLE 0x00010000
  574. #define HAL_SRNG_MSI_INTR 0x00020000
  575. #define HAL_SRNG_CACHED_DESC 0x00040000
  576. #ifdef QCA_WIFI_QCA6490
  577. #define HAL_SRNG_PREFETCH_TIMER 1
  578. #else
  579. #define HAL_SRNG_PREFETCH_TIMER 0
  580. #endif
  581. #define PN_SIZE_24 0
  582. #define PN_SIZE_48 1
  583. #define PN_SIZE_128 2
  584. #ifdef FORCE_WAKE
  585. /**
  586. * hal_set_init_phase() - Indicate initialization of
  587. * datapath rings
  588. * @soc: hal_soc handle
  589. * @init_phase: flag to indicate datapath rings
  590. * initialization status
  591. *
  592. * Return: None
  593. */
  594. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase);
  595. #else
  596. static inline
  597. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase)
  598. {
  599. }
  600. #endif /* FORCE_WAKE */
  601. /**
  602. * hal_srng_get_entrysize - Returns size of ring entry in bytes. Should be
  603. * used by callers for calculating the size of memory to be allocated before
  604. * calling hal_srng_setup to setup the ring
  605. *
  606. * @hal_soc: Opaque HAL SOC handle
  607. * @ring_type: one of the types from hal_ring_type
  608. *
  609. */
  610. extern uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type);
  611. /**
  612. * hal_srng_max_entries - Returns maximum possible number of ring entries
  613. * @hal_soc: Opaque HAL SOC handle
  614. * @ring_type: one of the types from hal_ring_type
  615. *
  616. * Return: Maximum number of entries for the given ring_type
  617. */
  618. uint32_t hal_srng_max_entries(void *hal_soc, int ring_type);
  619. /**
  620. * hal_srng_dump - Dump ring status
  621. * @srng: hal srng pointer
  622. */
  623. void hal_srng_dump(struct hal_srng *srng);
  624. /**
  625. * hal_srng_get_dir - Returns the direction of the ring
  626. * @hal_soc: Opaque HAL SOC handle
  627. * @ring_type: one of the types from hal_ring_type
  628. *
  629. * Return: Ring direction
  630. */
  631. enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type);
  632. /* HAL memory information */
  633. struct hal_mem_info {
  634. /* dev base virutal addr */
  635. void *dev_base_addr;
  636. /* dev base physical addr */
  637. void *dev_base_paddr;
  638. /* dev base ce virutal addr - applicable only for qca5018 */
  639. /* In qca5018 CE register are outside wcss block */
  640. /* using a separate address space to access CE registers */
  641. void *dev_base_addr_ce;
  642. /* dev base ce physical addr */
  643. void *dev_base_paddr_ce;
  644. /* Remote virtual pointer memory for HW/FW updates */
  645. void *shadow_rdptr_mem_vaddr;
  646. /* Remote physical pointer memory for HW/FW updates */
  647. void *shadow_rdptr_mem_paddr;
  648. /* Shared memory for ring pointer updates from host to FW */
  649. void *shadow_wrptr_mem_vaddr;
  650. /* Shared physical memory for ring pointer updates from host to FW */
  651. void *shadow_wrptr_mem_paddr;
  652. };
  653. /* SRNG parameters to be passed to hal_srng_setup */
  654. struct hal_srng_params {
  655. /* Physical base address of the ring */
  656. qdf_dma_addr_t ring_base_paddr;
  657. /* Virtual base address of the ring */
  658. void *ring_base_vaddr;
  659. /* Number of entries in ring */
  660. uint32_t num_entries;
  661. /* max transfer length */
  662. uint16_t max_buffer_length;
  663. /* MSI Address */
  664. qdf_dma_addr_t msi_addr;
  665. /* MSI data */
  666. uint32_t msi_data;
  667. /* Interrupt timer threshold – in micro seconds */
  668. uint32_t intr_timer_thres_us;
  669. /* Interrupt batch counter threshold – in number of ring entries */
  670. uint32_t intr_batch_cntr_thres_entries;
  671. /* Low threshold – in number of ring entries
  672. * (valid for src rings only)
  673. */
  674. uint32_t low_threshold;
  675. /* Misc flags */
  676. uint32_t flags;
  677. /* Unique ring id */
  678. uint8_t ring_id;
  679. /* Source or Destination ring */
  680. enum hal_srng_dir ring_dir;
  681. /* Size of ring entry */
  682. uint32_t entry_size;
  683. /* hw register base address */
  684. void *hwreg_base[MAX_SRNG_REG_GROUPS];
  685. /* prefetch timer config - in micro seconds */
  686. uint32_t prefetch_timer;
  687. };
  688. /* hal_construct_shadow_config() - initialize the shadow registers for dp rings
  689. * @hal_soc: hal handle
  690. *
  691. * Return: QDF_STATUS_OK on success
  692. */
  693. extern QDF_STATUS hal_construct_shadow_config(void *hal_soc);
  694. /* hal_set_one_shadow_config() - add a config for the specified ring
  695. * @hal_soc: hal handle
  696. * @ring_type: ring type
  697. * @ring_num: ring num
  698. *
  699. * The ring type and ring num uniquely specify the ring. After this call,
  700. * the hp/tp will be added as the next entry int the shadow register
  701. * configuration table. The hal code will use the shadow register address
  702. * in place of the hp/tp address.
  703. *
  704. * This function is exposed, so that the CE module can skip configuring shadow
  705. * registers for unused ring and rings assigned to the firmware.
  706. *
  707. * Return: QDF_STATUS_OK on success
  708. */
  709. extern QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type,
  710. int ring_num);
  711. /**
  712. * hal_get_shadow_config() - retrieve the config table
  713. * @hal_soc: hal handle
  714. * @shadow_config: will point to the table after
  715. * @num_shadow_registers_configured: will contain the number of valid entries
  716. */
  717. extern void hal_get_shadow_config(void *hal_soc,
  718. struct pld_shadow_reg_v2_cfg **shadow_config,
  719. int *num_shadow_registers_configured);
  720. /**
  721. * hal_srng_setup - Initialize HW SRNG ring.
  722. *
  723. * @hal_soc: Opaque HAL SOC handle
  724. * @ring_type: one of the types from hal_ring_type
  725. * @ring_num: Ring number if there are multiple rings of
  726. * same type (staring from 0)
  727. * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
  728. * @ring_params: SRNG ring params in hal_srng_params structure.
  729. * Callers are expected to allocate contiguous ring memory of size
  730. * 'num_entries * entry_size' bytes and pass the physical and virtual base
  731. * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in hal_srng_params
  732. * structure. Ring base address should be 8 byte aligned and size of each ring
  733. * entry should be queried using the API hal_srng_get_entrysize
  734. *
  735. * Return: Opaque pointer to ring on success
  736. * NULL on failure (if given ring is not available)
  737. */
  738. extern void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
  739. int mac_id, struct hal_srng_params *ring_params);
  740. /* Remapping ids of REO rings */
  741. #define REO_REMAP_TCL 0
  742. #define REO_REMAP_SW1 1
  743. #define REO_REMAP_SW2 2
  744. #define REO_REMAP_SW3 3
  745. #define REO_REMAP_SW4 4
  746. #define REO_REMAP_RELEASE 5
  747. #define REO_REMAP_FW 6
  748. #define REO_REMAP_UNUSED 7
  749. /*
  750. * Macro to access HWIO_REO_R0_ERROR_DESTINATION_RING_CTRL_IX_0
  751. * to map destination to rings
  752. */
  753. #define HAL_REO_ERR_REMAP_IX0(_VALUE, _OFFSET) \
  754. ((_VALUE) << \
  755. (HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_ ## \
  756. DESTINATION_RING_ ## _OFFSET ## _SHFT))
  757. /*
  758. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0
  759. * to map destination to rings
  760. */
  761. #define HAL_REO_REMAP_IX0(_VALUE, _OFFSET) \
  762. ((_VALUE) << \
  763. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_ ## \
  764. _OFFSET ## _SHFT))
  765. /*
  766. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1
  767. * to map destination to rings
  768. */
  769. #define HAL_REO_REMAP_IX2(_VALUE, _OFFSET) \
  770. ((_VALUE) << \
  771. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_ ## \
  772. _OFFSET ## _SHFT))
  773. /*
  774. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3
  775. * to map destination to rings
  776. */
  777. #define HAL_REO_REMAP_IX3(_VALUE, _OFFSET) \
  778. ((_VALUE) << \
  779. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_ ## \
  780. _OFFSET ## _SHFT))
  781. /**
  782. * hal_reo_read_write_ctrl_ix - Read or write REO_DESTINATION_RING_CTRL_IX
  783. * @hal_soc_hdl: HAL SOC handle
  784. * @read: boolean value to indicate if read or write
  785. * @ix0: pointer to store IX0 reg value
  786. * @ix1: pointer to store IX1 reg value
  787. * @ix2: pointer to store IX2 reg value
  788. * @ix3: pointer to store IX3 reg value
  789. */
  790. void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read,
  791. uint32_t *ix0, uint32_t *ix1,
  792. uint32_t *ix2, uint32_t *ix3);
  793. /**
  794. * hal_srng_set_hp_paddr() - Set physical address to dest SRNG head pointer
  795. * @sring: sring pointer
  796. * @paddr: physical address
  797. */
  798. extern void hal_srng_dst_set_hp_paddr(struct hal_srng *sring, uint64_t paddr);
  799. /**
  800. * hal_srng_dst_init_hp() - Initilaize head pointer with cached head pointer
  801. * @srng: sring pointer
  802. * @vaddr: virtual address
  803. */
  804. extern void hal_srng_dst_init_hp(struct hal_srng *srng, uint32_t *vaddr);
  805. /**
  806. * hal_srng_cleanup - Deinitialize HW SRNG ring.
  807. * @hal_soc: Opaque HAL SOC handle
  808. * @hal_srng: Opaque HAL SRNG pointer
  809. */
  810. void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl);
  811. static inline bool hal_srng_initialized(hal_ring_handle_t hal_ring_hdl)
  812. {
  813. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  814. return !!srng->initialized;
  815. }
  816. /**
  817. * hal_srng_dst_peek - Check if there are any entries in the ring (peek)
  818. * @hal_soc: Opaque HAL SOC handle
  819. * @hal_ring_hdl: Destination ring pointer
  820. *
  821. * Caller takes responsibility for any locking needs.
  822. *
  823. * Return: Opaque pointer for next ring entry; NULL on failire
  824. */
  825. static inline
  826. void *hal_srng_dst_peek(hal_soc_handle_t hal_soc_hdl,
  827. hal_ring_handle_t hal_ring_hdl)
  828. {
  829. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  830. if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp)
  831. return (void *)(&srng->ring_base_vaddr[srng->u.dst_ring.tp]);
  832. return NULL;
  833. }
  834. /**
  835. * hal_srng_access_start_unlocked - Start ring access (unlocked). Should use
  836. * hal_srng_access_start if locked access is required
  837. *
  838. * @hal_soc: Opaque HAL SOC handle
  839. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  840. *
  841. * Return: 0 on success; error on failire
  842. */
  843. static inline int
  844. hal_srng_access_start_unlocked(hal_soc_handle_t hal_soc_hdl,
  845. hal_ring_handle_t hal_ring_hdl)
  846. {
  847. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  848. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  849. uint32_t *desc;
  850. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  851. srng->u.src_ring.cached_tp =
  852. *(volatile uint32_t *)(srng->u.src_ring.tp_addr);
  853. else {
  854. srng->u.dst_ring.cached_hp =
  855. *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  856. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  857. desc = hal_srng_dst_peek(hal_soc_hdl, hal_ring_hdl);
  858. if (qdf_likely(desc)) {
  859. qdf_mem_dma_cache_sync(soc->qdf_dev,
  860. qdf_mem_virt_to_phys
  861. (desc),
  862. QDF_DMA_FROM_DEVICE,
  863. (srng->entry_size *
  864. sizeof(uint32_t)));
  865. qdf_prefetch(desc);
  866. }
  867. }
  868. }
  869. return 0;
  870. }
  871. /**
  872. * hal_srng_access_start - Start (locked) ring access
  873. *
  874. * @hal_soc: Opaque HAL SOC handle
  875. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  876. *
  877. * Return: 0 on success; error on failire
  878. */
  879. static inline int hal_srng_access_start(hal_soc_handle_t hal_soc_hdl,
  880. hal_ring_handle_t hal_ring_hdl)
  881. {
  882. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  883. if (qdf_unlikely(!hal_ring_hdl)) {
  884. qdf_print("Error: Invalid hal_ring\n");
  885. return -EINVAL;
  886. }
  887. SRNG_LOCK(&(srng->lock));
  888. return hal_srng_access_start_unlocked(hal_soc_hdl, hal_ring_hdl);
  889. }
  890. /**
  891. * hal_srng_dst_get_next - Get next entry from a destination ring
  892. * @hal_soc: Opaque HAL SOC handle
  893. * @hal_ring_hdl: Destination ring pointer
  894. *
  895. * Return: Opaque pointer for next ring entry; NULL on failure
  896. */
  897. static inline
  898. void *hal_srng_dst_get_next(void *hal_soc,
  899. hal_ring_handle_t hal_ring_hdl)
  900. {
  901. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  902. uint32_t *desc;
  903. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  904. return NULL;
  905. desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  906. /* TODO: Using % is expensive, but we have to do this since
  907. * size of some SRNG rings is not power of 2 (due to descriptor
  908. * sizes). Need to create separate API for rings used
  909. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  910. * SW2RXDMA and CE rings)
  911. */
  912. srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size);
  913. if (srng->u.dst_ring.tp == srng->ring_size)
  914. srng->u.dst_ring.tp = 0;
  915. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  916. struct hal_soc *soc = (struct hal_soc *)hal_soc;
  917. uint32_t *desc_next;
  918. uint32_t tp;
  919. tp = srng->u.dst_ring.tp;
  920. desc_next = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  921. qdf_mem_dma_cache_sync(soc->qdf_dev,
  922. qdf_mem_virt_to_phys(desc_next),
  923. QDF_DMA_FROM_DEVICE,
  924. (srng->entry_size *
  925. sizeof(uint32_t)));
  926. qdf_prefetch(desc_next);
  927. }
  928. return (void *)desc;
  929. }
  930. /**
  931. * hal_srng_dst_get_next_cached - Get cached next entry
  932. * @hal_soc: Opaque HAL SOC handle
  933. * @hal_ring_hdl: Destination ring pointer
  934. *
  935. * Get next entry from a destination ring and move cached tail pointer
  936. *
  937. * Return: Opaque pointer for next ring entry; NULL on failure
  938. */
  939. static inline
  940. void *hal_srng_dst_get_next_cached(void *hal_soc,
  941. hal_ring_handle_t hal_ring_hdl)
  942. {
  943. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  944. uint32_t *desc;
  945. uint32_t *desc_next;
  946. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  947. return NULL;
  948. desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  949. /* TODO: Using % is expensive, but we have to do this since
  950. * size of some SRNG rings is not power of 2 (due to descriptor
  951. * sizes). Need to create separate API for rings used
  952. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  953. * SW2RXDMA and CE rings)
  954. */
  955. srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size);
  956. if (srng->u.dst_ring.tp == srng->ring_size)
  957. srng->u.dst_ring.tp = 0;
  958. desc_next = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  959. qdf_prefetch(desc_next);
  960. return (void *)desc;
  961. }
  962. /**
  963. * hal_srng_dst_get_next_hp - Get next entry from a destination ring and move
  964. * cached head pointer
  965. *
  966. * @hal_soc: Opaque HAL SOC handle
  967. * @hal_ring_hdl: Destination ring pointer
  968. *
  969. * Return: Opaque pointer for next ring entry; NULL on failire
  970. */
  971. static inline void *
  972. hal_srng_dst_get_next_hp(hal_soc_handle_t hal_soc_hdl,
  973. hal_ring_handle_t hal_ring_hdl)
  974. {
  975. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  976. uint32_t *desc;
  977. /* TODO: Using % is expensive, but we have to do this since
  978. * size of some SRNG rings is not power of 2 (due to descriptor
  979. * sizes). Need to create separate API for rings used
  980. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  981. * SW2RXDMA and CE rings)
  982. */
  983. uint32_t next_hp = (srng->u.dst_ring.cached_hp + srng->entry_size) %
  984. srng->ring_size;
  985. if (next_hp != srng->u.dst_ring.tp) {
  986. desc = &(srng->ring_base_vaddr[srng->u.dst_ring.cached_hp]);
  987. srng->u.dst_ring.cached_hp = next_hp;
  988. return (void *)desc;
  989. }
  990. return NULL;
  991. }
  992. /**
  993. * hal_srng_dst_peek_sync - Check if there are any entries in the ring (peek)
  994. * @hal_soc: Opaque HAL SOC handle
  995. * @hal_ring_hdl: Destination ring pointer
  996. *
  997. * Sync cached head pointer with HW.
  998. * Caller takes responsibility for any locking needs.
  999. *
  1000. * Return: Opaque pointer for next ring entry; NULL on failire
  1001. */
  1002. static inline
  1003. void *hal_srng_dst_peek_sync(hal_soc_handle_t hal_soc_hdl,
  1004. hal_ring_handle_t hal_ring_hdl)
  1005. {
  1006. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1007. srng->u.dst_ring.cached_hp =
  1008. *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1009. if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp)
  1010. return (void *)(&(srng->ring_base_vaddr[srng->u.dst_ring.tp]));
  1011. return NULL;
  1012. }
  1013. /**
  1014. * hal_srng_dst_peek_sync_locked - Peek for any entries in the ring
  1015. * @hal_soc: Opaque HAL SOC handle
  1016. * @hal_ring_hdl: Destination ring pointer
  1017. *
  1018. * Sync cached head pointer with HW.
  1019. * This function takes up SRNG_LOCK. Should not be called with SRNG lock held.
  1020. *
  1021. * Return: Opaque pointer for next ring entry; NULL on failire
  1022. */
  1023. static inline
  1024. void *hal_srng_dst_peek_sync_locked(hal_soc_handle_t hal_soc_hdl,
  1025. hal_ring_handle_t hal_ring_hdl)
  1026. {
  1027. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1028. void *ring_desc_ptr = NULL;
  1029. if (qdf_unlikely(!hal_ring_hdl)) {
  1030. qdf_print("Error: Invalid hal_ring\n");
  1031. return NULL;
  1032. }
  1033. SRNG_LOCK(&srng->lock);
  1034. ring_desc_ptr = hal_srng_dst_peek_sync(hal_soc_hdl, hal_ring_hdl);
  1035. SRNG_UNLOCK(&srng->lock);
  1036. return ring_desc_ptr;
  1037. }
  1038. /**
  1039. * hal_srng_dst_num_valid - Returns number of valid entries (to be processed
  1040. * by SW) in destination ring
  1041. *
  1042. * @hal_soc: Opaque HAL SOC handle
  1043. * @hal_ring_hdl: Destination ring pointer
  1044. * @sync_hw_ptr: Sync cached head pointer with HW
  1045. *
  1046. */
  1047. static inline
  1048. uint32_t hal_srng_dst_num_valid(void *hal_soc,
  1049. hal_ring_handle_t hal_ring_hdl,
  1050. int sync_hw_ptr)
  1051. {
  1052. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1053. uint32_t hp;
  1054. uint32_t tp = srng->u.dst_ring.tp;
  1055. if (sync_hw_ptr) {
  1056. hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1057. srng->u.dst_ring.cached_hp = hp;
  1058. } else {
  1059. hp = srng->u.dst_ring.cached_hp;
  1060. }
  1061. if (hp >= tp)
  1062. return (hp - tp) / srng->entry_size;
  1063. return (srng->ring_size - tp + hp) / srng->entry_size;
  1064. }
  1065. /**
  1066. * hal_srng_dst_inv_cached_descs - API to invalidate descriptors in batch mode
  1067. * @hal_soc: Opaque HAL SOC handle
  1068. * @hal_ring_hdl: Destination ring pointer
  1069. * @entry_count: Number of descriptors to be invalidated
  1070. *
  1071. * Invalidates a set of cached descriptors starting from tail to
  1072. * provided count worth
  1073. *
  1074. * Return - None
  1075. */
  1076. static inline void hal_srng_dst_inv_cached_descs(void *hal_soc,
  1077. hal_ring_handle_t hal_ring_hdl,
  1078. uint32_t entry_count)
  1079. {
  1080. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1081. uint32_t hp = srng->u.dst_ring.cached_hp;
  1082. uint32_t tp = srng->u.dst_ring.tp;
  1083. uint32_t sync_p = 0;
  1084. /*
  1085. * If SRNG does not have cached descriptors this
  1086. * API call should be a no op
  1087. */
  1088. if (!(srng->flags & HAL_SRNG_CACHED_DESC))
  1089. return;
  1090. if (qdf_unlikely(entry_count == 0))
  1091. return;
  1092. sync_p = (entry_count - 1) * srng->entry_size;
  1093. if (hp > tp) {
  1094. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[tp],
  1095. &srng->ring_base_vaddr[tp + sync_p]
  1096. + (srng->entry_size * sizeof(uint32_t)));
  1097. } else {
  1098. /*
  1099. * We have wrapped around
  1100. */
  1101. uint32_t wrap_cnt = ((srng->ring_size - tp) / srng->entry_size);
  1102. if (entry_count <= wrap_cnt) {
  1103. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[tp],
  1104. &srng->ring_base_vaddr[tp + sync_p] +
  1105. (srng->entry_size * sizeof(uint32_t)));
  1106. return;
  1107. }
  1108. entry_count -= wrap_cnt;
  1109. sync_p = (entry_count - 1) * srng->entry_size;
  1110. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[tp],
  1111. &srng->ring_base_vaddr[srng->ring_size - srng->entry_size] +
  1112. (srng->entry_size * sizeof(uint32_t)));
  1113. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[0],
  1114. &srng->ring_base_vaddr[sync_p]
  1115. + (srng->entry_size * sizeof(uint32_t)));
  1116. }
  1117. }
  1118. /**
  1119. * hal_srng_dst_num_valid_locked - Returns num valid entries to be processed
  1120. *
  1121. * @hal_soc: Opaque HAL SOC handle
  1122. * @hal_ring_hdl: Destination ring pointer
  1123. * @sync_hw_ptr: Sync cached head pointer with HW
  1124. *
  1125. * Returns number of valid entries to be processed by the host driver. The
  1126. * function takes up SRNG lock.
  1127. *
  1128. * Return: Number of valid destination entries
  1129. */
  1130. static inline uint32_t
  1131. hal_srng_dst_num_valid_locked(hal_soc_handle_t hal_soc,
  1132. hal_ring_handle_t hal_ring_hdl,
  1133. int sync_hw_ptr)
  1134. {
  1135. uint32_t num_valid;
  1136. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1137. SRNG_LOCK(&srng->lock);
  1138. num_valid = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, sync_hw_ptr);
  1139. SRNG_UNLOCK(&srng->lock);
  1140. return num_valid;
  1141. }
  1142. /**
  1143. * hal_srng_sync_cachedhp - sync cachehp pointer from hw hp
  1144. *
  1145. * @hal_soc: Opaque HAL SOC handle
  1146. * @hal_ring_hdl: Destination ring pointer
  1147. *
  1148. */
  1149. static inline
  1150. void hal_srng_sync_cachedhp(void *hal_soc,
  1151. hal_ring_handle_t hal_ring_hdl)
  1152. {
  1153. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1154. uint32_t hp;
  1155. hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1156. srng->u.dst_ring.cached_hp = hp;
  1157. }
  1158. /**
  1159. * hal_srng_src_reap_next - Reap next entry from a source ring and move reap
  1160. * pointer. This can be used to release any buffers associated with completed
  1161. * ring entries. Note that this should not be used for posting new descriptor
  1162. * entries. Posting of new entries should be done only using
  1163. * hal_srng_src_get_next_reaped when this function is used for reaping.
  1164. *
  1165. * @hal_soc: Opaque HAL SOC handle
  1166. * @hal_ring_hdl: Source ring pointer
  1167. *
  1168. * Return: Opaque pointer for next ring entry; NULL on failire
  1169. */
  1170. static inline void *
  1171. hal_srng_src_reap_next(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1172. {
  1173. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1174. uint32_t *desc;
  1175. /* TODO: Using % is expensive, but we have to do this since
  1176. * size of some SRNG rings is not power of 2 (due to descriptor
  1177. * sizes). Need to create separate API for rings used
  1178. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1179. * SW2RXDMA and CE rings)
  1180. */
  1181. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1182. srng->ring_size;
  1183. if (next_reap_hp != srng->u.src_ring.cached_tp) {
  1184. desc = &(srng->ring_base_vaddr[next_reap_hp]);
  1185. srng->u.src_ring.reap_hp = next_reap_hp;
  1186. return (void *)desc;
  1187. }
  1188. return NULL;
  1189. }
  1190. /**
  1191. * hal_srng_src_get_next_reaped - Get next entry from a source ring that is
  1192. * already reaped using hal_srng_src_reap_next, for posting new entries to
  1193. * the ring
  1194. *
  1195. * @hal_soc: Opaque HAL SOC handle
  1196. * @hal_ring_hdl: Source ring pointer
  1197. *
  1198. * Return: Opaque pointer for next (reaped) source ring entry; NULL on failire
  1199. */
  1200. static inline void *
  1201. hal_srng_src_get_next_reaped(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1202. {
  1203. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1204. uint32_t *desc;
  1205. if (srng->u.src_ring.hp != srng->u.src_ring.reap_hp) {
  1206. desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]);
  1207. srng->u.src_ring.hp = (srng->u.src_ring.hp + srng->entry_size) %
  1208. srng->ring_size;
  1209. return (void *)desc;
  1210. }
  1211. return NULL;
  1212. }
  1213. /**
  1214. * hal_srng_src_pending_reap_next - Reap next entry from a source ring and
  1215. * move reap pointer. This API is used in detach path to release any buffers
  1216. * associated with ring entries which are pending reap.
  1217. *
  1218. * @hal_soc: Opaque HAL SOC handle
  1219. * @hal_ring_hdl: Source ring pointer
  1220. *
  1221. * Return: Opaque pointer for next ring entry; NULL on failire
  1222. */
  1223. static inline void *
  1224. hal_srng_src_pending_reap_next(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1225. {
  1226. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1227. uint32_t *desc;
  1228. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1229. srng->ring_size;
  1230. if (next_reap_hp != srng->u.src_ring.hp) {
  1231. desc = &(srng->ring_base_vaddr[next_reap_hp]);
  1232. srng->u.src_ring.reap_hp = next_reap_hp;
  1233. return (void *)desc;
  1234. }
  1235. return NULL;
  1236. }
  1237. /**
  1238. * hal_srng_src_done_val -
  1239. *
  1240. * @hal_soc: Opaque HAL SOC handle
  1241. * @hal_ring_hdl: Source ring pointer
  1242. *
  1243. * Return: Opaque pointer for next ring entry; NULL on failire
  1244. */
  1245. static inline uint32_t
  1246. hal_srng_src_done_val(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1247. {
  1248. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1249. /* TODO: Using % is expensive, but we have to do this since
  1250. * size of some SRNG rings is not power of 2 (due to descriptor
  1251. * sizes). Need to create separate API for rings used
  1252. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1253. * SW2RXDMA and CE rings)
  1254. */
  1255. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1256. srng->ring_size;
  1257. if (next_reap_hp == srng->u.src_ring.cached_tp)
  1258. return 0;
  1259. if (srng->u.src_ring.cached_tp > next_reap_hp)
  1260. return (srng->u.src_ring.cached_tp - next_reap_hp) /
  1261. srng->entry_size;
  1262. else
  1263. return ((srng->ring_size - next_reap_hp) +
  1264. srng->u.src_ring.cached_tp) / srng->entry_size;
  1265. }
  1266. /**
  1267. * hal_get_entrysize_from_srng() - Retrieve ring entry size
  1268. * @hal_ring_hdl: Source ring pointer
  1269. *
  1270. * Return: uint8_t
  1271. */
  1272. static inline
  1273. uint8_t hal_get_entrysize_from_srng(hal_ring_handle_t hal_ring_hdl)
  1274. {
  1275. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1276. return srng->entry_size;
  1277. }
  1278. /**
  1279. * hal_get_sw_hptp - Get SW head and tail pointer location for any ring
  1280. * @hal_soc: Opaque HAL SOC handle
  1281. * @hal_ring_hdl: Source ring pointer
  1282. * @tailp: Tail Pointer
  1283. * @headp: Head Pointer
  1284. *
  1285. * Return: Update tail pointer and head pointer in arguments.
  1286. */
  1287. static inline
  1288. void hal_get_sw_hptp(void *hal_soc, hal_ring_handle_t hal_ring_hdl,
  1289. uint32_t *tailp, uint32_t *headp)
  1290. {
  1291. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1292. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1293. *headp = srng->u.src_ring.hp;
  1294. *tailp = *srng->u.src_ring.tp_addr;
  1295. } else {
  1296. *tailp = srng->u.dst_ring.tp;
  1297. *headp = *srng->u.dst_ring.hp_addr;
  1298. }
  1299. }
  1300. /**
  1301. * hal_srng_src_get_next - Get next entry from a source ring and move cached tail pointer
  1302. *
  1303. * @hal_soc: Opaque HAL SOC handle
  1304. * @hal_ring_hdl: Source ring pointer
  1305. *
  1306. * Return: Opaque pointer for next ring entry; NULL on failire
  1307. */
  1308. static inline
  1309. void *hal_srng_src_get_next(void *hal_soc,
  1310. hal_ring_handle_t hal_ring_hdl)
  1311. {
  1312. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1313. uint32_t *desc;
  1314. /* TODO: Using % is expensive, but we have to do this since
  1315. * size of some SRNG rings is not power of 2 (due to descriptor
  1316. * sizes). Need to create separate API for rings used
  1317. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1318. * SW2RXDMA and CE rings)
  1319. */
  1320. uint32_t next_hp = (srng->u.src_ring.hp + srng->entry_size) %
  1321. srng->ring_size;
  1322. if (next_hp != srng->u.src_ring.cached_tp) {
  1323. desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]);
  1324. srng->u.src_ring.hp = next_hp;
  1325. /* TODO: Since reap function is not used by all rings, we can
  1326. * remove the following update of reap_hp in this function
  1327. * if we can ensure that only hal_srng_src_get_next_reaped
  1328. * is used for the rings requiring reap functionality
  1329. */
  1330. srng->u.src_ring.reap_hp = next_hp;
  1331. return (void *)desc;
  1332. }
  1333. return NULL;
  1334. }
  1335. /**
  1336. * hal_srng_src_peek_n_get_next - Get next entry from a ring without
  1337. * moving head pointer.
  1338. * hal_srng_src_get_next should be called subsequently to move the head pointer
  1339. *
  1340. * @hal_soc: Opaque HAL SOC handle
  1341. * @hal_ring_hdl: Source ring pointer
  1342. *
  1343. * Return: Opaque pointer for next ring entry; NULL on failire
  1344. */
  1345. static inline
  1346. void *hal_srng_src_peek_n_get_next(hal_soc_handle_t hal_soc_hdl,
  1347. hal_ring_handle_t hal_ring_hdl)
  1348. {
  1349. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1350. uint32_t *desc;
  1351. /* TODO: Using % is expensive, but we have to do this since
  1352. * size of some SRNG rings is not power of 2 (due to descriptor
  1353. * sizes). Need to create separate API for rings used
  1354. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1355. * SW2RXDMA and CE rings)
  1356. */
  1357. if (((srng->u.src_ring.hp + srng->entry_size) %
  1358. srng->ring_size) != srng->u.src_ring.cached_tp) {
  1359. desc = &(srng->ring_base_vaddr[(srng->u.src_ring.hp +
  1360. srng->entry_size) %
  1361. srng->ring_size]);
  1362. return (void *)desc;
  1363. }
  1364. return NULL;
  1365. }
  1366. /**
  1367. * hal_srng_src_get_cur_hp_n_move_next () - API returns current hp
  1368. * and move hp to next in src ring
  1369. *
  1370. * Usage: This API should only be used at init time replenish.
  1371. *
  1372. * @hal_soc_hdl: HAL soc handle
  1373. * @hal_ring_hdl: Source ring pointer
  1374. *
  1375. */
  1376. static inline void *
  1377. hal_srng_src_get_cur_hp_n_move_next(hal_soc_handle_t hal_soc_hdl,
  1378. hal_ring_handle_t hal_ring_hdl)
  1379. {
  1380. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1381. uint32_t *cur_desc = NULL;
  1382. uint32_t next_hp;
  1383. cur_desc = &srng->ring_base_vaddr[(srng->u.src_ring.hp)];
  1384. next_hp = (srng->u.src_ring.hp + srng->entry_size) %
  1385. srng->ring_size;
  1386. if (next_hp != srng->u.src_ring.cached_tp)
  1387. srng->u.src_ring.hp = next_hp;
  1388. return (void *)cur_desc;
  1389. }
  1390. /**
  1391. * hal_srng_src_num_avail - Returns number of available entries in src ring
  1392. *
  1393. * @hal_soc: Opaque HAL SOC handle
  1394. * @hal_ring_hdl: Source ring pointer
  1395. * @sync_hw_ptr: Sync cached tail pointer with HW
  1396. *
  1397. */
  1398. static inline uint32_t
  1399. hal_srng_src_num_avail(void *hal_soc,
  1400. hal_ring_handle_t hal_ring_hdl, int sync_hw_ptr)
  1401. {
  1402. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1403. uint32_t tp;
  1404. uint32_t hp = srng->u.src_ring.hp;
  1405. if (sync_hw_ptr) {
  1406. tp = *(srng->u.src_ring.tp_addr);
  1407. srng->u.src_ring.cached_tp = tp;
  1408. } else {
  1409. tp = srng->u.src_ring.cached_tp;
  1410. }
  1411. if (tp > hp)
  1412. return ((tp - hp) / srng->entry_size) - 1;
  1413. else
  1414. return ((srng->ring_size - hp + tp) / srng->entry_size) - 1;
  1415. }
  1416. /**
  1417. * hal_srng_access_end_unlocked - End ring access (unlocked) - update cached
  1418. * ring head/tail pointers to HW.
  1419. * This should be used only if hal_srng_access_start_unlocked to start ring
  1420. * access
  1421. *
  1422. * @hal_soc: Opaque HAL SOC handle
  1423. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1424. *
  1425. * Return: 0 on success; error on failire
  1426. */
  1427. static inline void
  1428. hal_srng_access_end_unlocked(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1429. {
  1430. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1431. /* TODO: See if we need a write memory barrier here */
  1432. if (srng->flags & HAL_SRNG_LMAC_RING) {
  1433. /* For LMAC rings, ring pointer updates are done through FW and
  1434. * hence written to a shared memory location that is read by FW
  1435. */
  1436. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1437. *(srng->u.src_ring.hp_addr) = srng->u.src_ring.hp;
  1438. } else {
  1439. *(srng->u.dst_ring.tp_addr) = srng->u.dst_ring.tp;
  1440. }
  1441. } else {
  1442. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1443. hal_srng_write_address_32_mb(hal_soc,
  1444. srng,
  1445. srng->u.src_ring.hp_addr,
  1446. srng->u.src_ring.hp);
  1447. else
  1448. hal_srng_write_address_32_mb(hal_soc,
  1449. srng,
  1450. srng->u.dst_ring.tp_addr,
  1451. srng->u.dst_ring.tp);
  1452. }
  1453. }
  1454. /**
  1455. * hal_srng_access_end - Unlock ring access and update cached ring head/tail
  1456. * pointers to HW
  1457. * This should be used only if hal_srng_access_start to start ring access
  1458. *
  1459. * @hal_soc: Opaque HAL SOC handle
  1460. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1461. *
  1462. * Return: 0 on success; error on failire
  1463. */
  1464. static inline void
  1465. hal_srng_access_end(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1466. {
  1467. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1468. if (qdf_unlikely(!hal_ring_hdl)) {
  1469. qdf_print("Error: Invalid hal_ring\n");
  1470. return;
  1471. }
  1472. hal_srng_access_end_unlocked(hal_soc, hal_ring_hdl);
  1473. SRNG_UNLOCK(&(srng->lock));
  1474. }
  1475. /**
  1476. * hal_srng_access_end_reap - Unlock ring access
  1477. * This should be used only if hal_srng_access_start to start ring access
  1478. * and should be used only while reaping SRC ring completions
  1479. *
  1480. * @hal_soc: Opaque HAL SOC handle
  1481. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1482. *
  1483. * Return: 0 on success; error on failire
  1484. */
  1485. static inline void
  1486. hal_srng_access_end_reap(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1487. {
  1488. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1489. SRNG_UNLOCK(&(srng->lock));
  1490. }
  1491. /* TODO: Check if the following definitions is available in HW headers */
  1492. #define WBM_IDLE_SCATTER_BUF_SIZE 32704
  1493. #define NUM_MPDUS_PER_LINK_DESC 6
  1494. #define NUM_MSDUS_PER_LINK_DESC 7
  1495. #define REO_QUEUE_DESC_ALIGN 128
  1496. #define LINK_DESC_ALIGN 128
  1497. #define ADDRESS_MATCH_TAG_VAL 0x5
  1498. /* Number of mpdu link pointers is 9 in case of TX_MPDU_QUEUE_HEAD and 14 in
  1499. * of TX_MPDU_QUEUE_EXT. We are defining a common average count here
  1500. */
  1501. #define NUM_MPDU_LINKS_PER_QUEUE_DESC 12
  1502. /* TODO: Check with HW team on the scatter buffer size supported. As per WBM
  1503. * MLD, scatter_buffer_size in IDLE_LIST_CONTROL register is 9 bits and size
  1504. * should be specified in 16 word units. But the number of bits defined for
  1505. * this field in HW header files is 5.
  1506. */
  1507. #define WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE 8
  1508. /**
  1509. * hal_idle_list_scatter_buf_size - Get the size of each scatter buffer
  1510. * in an idle list
  1511. *
  1512. * @hal_soc: Opaque HAL SOC handle
  1513. *
  1514. */
  1515. static inline
  1516. uint32_t hal_idle_list_scatter_buf_size(hal_soc_handle_t hal_soc_hdl)
  1517. {
  1518. return WBM_IDLE_SCATTER_BUF_SIZE;
  1519. }
  1520. /**
  1521. * hal_get_link_desc_size - Get the size of each link descriptor
  1522. *
  1523. * @hal_soc: Opaque HAL SOC handle
  1524. *
  1525. */
  1526. static inline uint32_t hal_get_link_desc_size(hal_soc_handle_t hal_soc_hdl)
  1527. {
  1528. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1529. if (!hal_soc || !hal_soc->ops) {
  1530. qdf_print("Error: Invalid ops\n");
  1531. QDF_BUG(0);
  1532. return -EINVAL;
  1533. }
  1534. if (!hal_soc->ops->hal_get_link_desc_size) {
  1535. qdf_print("Error: Invalid function pointer\n");
  1536. QDF_BUG(0);
  1537. return -EINVAL;
  1538. }
  1539. return hal_soc->ops->hal_get_link_desc_size();
  1540. }
  1541. /**
  1542. * hal_get_link_desc_align - Get the required start address alignment for
  1543. * link descriptors
  1544. *
  1545. * @hal_soc: Opaque HAL SOC handle
  1546. *
  1547. */
  1548. static inline
  1549. uint32_t hal_get_link_desc_align(hal_soc_handle_t hal_soc_hdl)
  1550. {
  1551. return LINK_DESC_ALIGN;
  1552. }
  1553. /**
  1554. * hal_num_mpdus_per_link_desc - Get number of mpdus each link desc can hold
  1555. *
  1556. * @hal_soc: Opaque HAL SOC handle
  1557. *
  1558. */
  1559. static inline
  1560. uint32_t hal_num_mpdus_per_link_desc(hal_soc_handle_t hal_soc_hdl)
  1561. {
  1562. return NUM_MPDUS_PER_LINK_DESC;
  1563. }
  1564. /**
  1565. * hal_num_msdus_per_link_desc - Get number of msdus each link desc can hold
  1566. *
  1567. * @hal_soc: Opaque HAL SOC handle
  1568. *
  1569. */
  1570. static inline
  1571. uint32_t hal_num_msdus_per_link_desc(hal_soc_handle_t hal_soc_hdl)
  1572. {
  1573. return NUM_MSDUS_PER_LINK_DESC;
  1574. }
  1575. /**
  1576. * hal_num_mpdu_links_per_queue_desc - Get number of mpdu links each queue
  1577. * descriptor can hold
  1578. *
  1579. * @hal_soc: Opaque HAL SOC handle
  1580. *
  1581. */
  1582. static inline
  1583. uint32_t hal_num_mpdu_links_per_queue_desc(hal_soc_handle_t hal_soc_hdl)
  1584. {
  1585. return NUM_MPDU_LINKS_PER_QUEUE_DESC;
  1586. }
  1587. /**
  1588. * hal_idle_list_scatter_buf_num_entries - Get the number of link desc entries
  1589. * that the given buffer size
  1590. *
  1591. * @hal_soc: Opaque HAL SOC handle
  1592. * @scatter_buf_size: Size of scatter buffer
  1593. *
  1594. */
  1595. static inline
  1596. uint32_t hal_idle_scatter_buf_num_entries(hal_soc_handle_t hal_soc_hdl,
  1597. uint32_t scatter_buf_size)
  1598. {
  1599. return (scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) /
  1600. hal_srng_get_entrysize(hal_soc_hdl, WBM_IDLE_LINK);
  1601. }
  1602. /**
  1603. * hal_idle_list_num_scatter_bufs - Get the number of sctater buffer
  1604. * each given buffer size
  1605. *
  1606. * @hal_soc: Opaque HAL SOC handle
  1607. * @total_mem: size of memory to be scattered
  1608. * @scatter_buf_size: Size of scatter buffer
  1609. *
  1610. */
  1611. static inline
  1612. uint32_t hal_idle_list_num_scatter_bufs(hal_soc_handle_t hal_soc_hdl,
  1613. uint32_t total_mem,
  1614. uint32_t scatter_buf_size)
  1615. {
  1616. uint8_t rem = (total_mem % (scatter_buf_size -
  1617. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) ? 1 : 0;
  1618. uint32_t num_scatter_bufs = (total_mem / (scatter_buf_size -
  1619. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) + rem;
  1620. return num_scatter_bufs;
  1621. }
  1622. enum hal_pn_type {
  1623. HAL_PN_NONE,
  1624. HAL_PN_WPA,
  1625. HAL_PN_WAPI_EVEN,
  1626. HAL_PN_WAPI_UNEVEN,
  1627. };
  1628. #define HAL_RX_MAX_BA_WINDOW 256
  1629. /**
  1630. * hal_get_reo_qdesc_align - Get start address alignment for reo
  1631. * queue descriptors
  1632. *
  1633. * @hal_soc: Opaque HAL SOC handle
  1634. *
  1635. */
  1636. static inline
  1637. uint32_t hal_get_reo_qdesc_align(hal_soc_handle_t hal_soc_hdl)
  1638. {
  1639. return REO_QUEUE_DESC_ALIGN;
  1640. }
  1641. /**
  1642. * hal_reo_qdesc_setup - Setup HW REO queue descriptor
  1643. *
  1644. * @hal_soc: Opaque HAL SOC handle
  1645. * @ba_window_size: BlockAck window size
  1646. * @start_seq: Starting sequence number
  1647. * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
  1648. * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
  1649. * @pn_type: PN type (one of the types defined in 'enum hal_pn_type')
  1650. *
  1651. */
  1652. void hal_reo_qdesc_setup(hal_soc_handle_t hal_soc_hdl,
  1653. int tid, uint32_t ba_window_size,
  1654. uint32_t start_seq, void *hw_qdesc_vaddr,
  1655. qdf_dma_addr_t hw_qdesc_paddr,
  1656. int pn_type);
  1657. /**
  1658. * hal_srng_get_hp_addr - Get head pointer physical address
  1659. *
  1660. * @hal_soc: Opaque HAL SOC handle
  1661. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1662. *
  1663. */
  1664. static inline qdf_dma_addr_t
  1665. hal_srng_get_hp_addr(void *hal_soc,
  1666. hal_ring_handle_t hal_ring_hdl)
  1667. {
  1668. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1669. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1670. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1671. return hal->shadow_wrptr_mem_paddr +
  1672. ((unsigned long)(srng->u.src_ring.hp_addr) -
  1673. (unsigned long)(hal->shadow_wrptr_mem_vaddr));
  1674. } else {
  1675. return hal->shadow_rdptr_mem_paddr +
  1676. ((unsigned long)(srng->u.dst_ring.hp_addr) -
  1677. (unsigned long)(hal->shadow_rdptr_mem_vaddr));
  1678. }
  1679. }
  1680. /**
  1681. * hal_srng_get_tp_addr - Get tail pointer physical address
  1682. *
  1683. * @hal_soc: Opaque HAL SOC handle
  1684. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1685. *
  1686. */
  1687. static inline qdf_dma_addr_t
  1688. hal_srng_get_tp_addr(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1689. {
  1690. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1691. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1692. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1693. return hal->shadow_rdptr_mem_paddr +
  1694. ((unsigned long)(srng->u.src_ring.tp_addr) -
  1695. (unsigned long)(hal->shadow_rdptr_mem_vaddr));
  1696. } else {
  1697. return hal->shadow_wrptr_mem_paddr +
  1698. ((unsigned long)(srng->u.dst_ring.tp_addr) -
  1699. (unsigned long)(hal->shadow_wrptr_mem_vaddr));
  1700. }
  1701. }
  1702. /**
  1703. * hal_srng_get_num_entries - Get total entries in the HAL Srng
  1704. *
  1705. * @hal_soc: Opaque HAL SOC handle
  1706. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1707. *
  1708. * Return: total number of entries in hal ring
  1709. */
  1710. static inline
  1711. uint32_t hal_srng_get_num_entries(hal_soc_handle_t hal_soc_hdl,
  1712. hal_ring_handle_t hal_ring_hdl)
  1713. {
  1714. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1715. return srng->num_entries;
  1716. }
  1717. /**
  1718. * hal_get_srng_params - Retrieve SRNG parameters for a given ring from HAL
  1719. *
  1720. * @hal_soc: Opaque HAL SOC handle
  1721. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1722. * @ring_params: SRNG parameters will be returned through this structure
  1723. */
  1724. void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl,
  1725. hal_ring_handle_t hal_ring_hdl,
  1726. struct hal_srng_params *ring_params);
  1727. /**
  1728. * hal_mem_info - Retrieve hal memory base address
  1729. *
  1730. * @hal_soc: Opaque HAL SOC handle
  1731. * @mem: pointer to structure to be updated with hal mem info
  1732. */
  1733. void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem);
  1734. /**
  1735. * hal_get_target_type - Return target type
  1736. *
  1737. * @hal_soc: Opaque HAL SOC handle
  1738. */
  1739. uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl);
  1740. /**
  1741. * hal_get_ba_aging_timeout - Retrieve BA aging timeout
  1742. *
  1743. * @hal_soc: Opaque HAL SOC handle
  1744. * @ac: Access category
  1745. * @value: timeout duration in millisec
  1746. */
  1747. void hal_get_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
  1748. uint32_t *value);
  1749. /**
  1750. * hal_set_aging_timeout - Set BA aging timeout
  1751. *
  1752. * @hal_soc: Opaque HAL SOC handle
  1753. * @ac: Access category in millisec
  1754. * @value: timeout duration value
  1755. */
  1756. void hal_set_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
  1757. uint32_t value);
  1758. /**
  1759. * hal_srng_dst_hw_init - Private function to initialize SRNG
  1760. * destination ring HW
  1761. * @hal_soc: HAL SOC handle
  1762. * @srng: SRNG ring pointer
  1763. */
  1764. static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
  1765. struct hal_srng *srng)
  1766. {
  1767. hal->ops->hal_srng_dst_hw_init(hal, srng);
  1768. }
  1769. /**
  1770. * hal_srng_src_hw_init - Private function to initialize SRNG
  1771. * source ring HW
  1772. * @hal_soc: HAL SOC handle
  1773. * @srng: SRNG ring pointer
  1774. */
  1775. static inline void hal_srng_src_hw_init(struct hal_soc *hal,
  1776. struct hal_srng *srng)
  1777. {
  1778. hal->ops->hal_srng_src_hw_init(hal, srng);
  1779. }
  1780. /**
  1781. * hal_get_hw_hptp() - Get HW head and tail pointer value for any ring
  1782. * @hal_soc: Opaque HAL SOC handle
  1783. * @hal_ring_hdl: Source ring pointer
  1784. * @headp: Head Pointer
  1785. * @tailp: Tail Pointer
  1786. * @ring_type: Ring
  1787. *
  1788. * Return: Update tail pointer and head pointer in arguments.
  1789. */
  1790. static inline
  1791. void hal_get_hw_hptp(hal_soc_handle_t hal_soc_hdl,
  1792. hal_ring_handle_t hal_ring_hdl,
  1793. uint32_t *headp, uint32_t *tailp,
  1794. uint8_t ring_type)
  1795. {
  1796. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1797. hal_soc->ops->hal_get_hw_hptp(hal_soc, hal_ring_hdl,
  1798. headp, tailp, ring_type);
  1799. }
  1800. /**
  1801. * hal_reo_setup - Initialize HW REO block
  1802. *
  1803. * @hal_soc: Opaque HAL SOC handle
  1804. * @reo_params: parameters needed by HAL for REO config
  1805. */
  1806. static inline void hal_reo_setup(hal_soc_handle_t hal_soc_hdl,
  1807. void *reoparams)
  1808. {
  1809. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1810. hal_soc->ops->hal_reo_setup(hal_soc, reoparams);
  1811. }
  1812. /**
  1813. * hal_setup_link_idle_list - Setup scattered idle list using the
  1814. * buffer list provided
  1815. *
  1816. * @hal_soc: Opaque HAL SOC handle
  1817. * @scatter_bufs_base_paddr: Array of physical base addresses
  1818. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  1819. * @num_scatter_bufs: Number of scatter buffers in the above lists
  1820. * @scatter_buf_size: Size of each scatter buffer
  1821. * @last_buf_end_offset: Offset to the last entry
  1822. * @num_entries: Total entries of all scatter bufs
  1823. *
  1824. */
  1825. static inline
  1826. void hal_setup_link_idle_list(hal_soc_handle_t hal_soc_hdl,
  1827. qdf_dma_addr_t scatter_bufs_base_paddr[],
  1828. void *scatter_bufs_base_vaddr[],
  1829. uint32_t num_scatter_bufs,
  1830. uint32_t scatter_buf_size,
  1831. uint32_t last_buf_end_offset,
  1832. uint32_t num_entries)
  1833. {
  1834. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1835. hal_soc->ops->hal_setup_link_idle_list(hal_soc, scatter_bufs_base_paddr,
  1836. scatter_bufs_base_vaddr, num_scatter_bufs,
  1837. scatter_buf_size, last_buf_end_offset,
  1838. num_entries);
  1839. }
  1840. /**
  1841. * hal_srng_dump_ring_desc() - Dump ring descriptor info
  1842. *
  1843. * @hal_soc: Opaque HAL SOC handle
  1844. * @hal_ring_hdl: Source ring pointer
  1845. * @ring_desc: Opaque ring descriptor handle
  1846. */
  1847. static inline void hal_srng_dump_ring_desc(hal_soc_handle_t hal_soc_hdl,
  1848. hal_ring_handle_t hal_ring_hdl,
  1849. hal_ring_desc_t ring_desc)
  1850. {
  1851. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1852. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1853. ring_desc, (srng->entry_size << 2));
  1854. }
  1855. /**
  1856. * hal_srng_dump_ring() - Dump last 128 descs of the ring
  1857. *
  1858. * @hal_soc: Opaque HAL SOC handle
  1859. * @hal_ring_hdl: Source ring pointer
  1860. */
  1861. static inline void hal_srng_dump_ring(hal_soc_handle_t hal_soc_hdl,
  1862. hal_ring_handle_t hal_ring_hdl)
  1863. {
  1864. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1865. uint32_t *desc;
  1866. uint32_t tp, i;
  1867. tp = srng->u.dst_ring.tp;
  1868. for (i = 0; i < 128; i++) {
  1869. if (!tp)
  1870. tp = srng->ring_size;
  1871. desc = &srng->ring_base_vaddr[tp - srng->entry_size];
  1872. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP,
  1873. QDF_TRACE_LEVEL_DEBUG,
  1874. desc, (srng->entry_size << 2));
  1875. tp -= srng->entry_size;
  1876. }
  1877. }
  1878. /*
  1879. * hal_rxdma_desc_to_hal_ring_desc - API to convert rxdma ring desc
  1880. * to opaque dp_ring desc type
  1881. * @ring_desc - rxdma ring desc
  1882. *
  1883. * Return: hal_rxdma_desc_t type
  1884. */
  1885. static inline
  1886. hal_ring_desc_t hal_rxdma_desc_to_hal_ring_desc(hal_rxdma_desc_t ring_desc)
  1887. {
  1888. return (hal_ring_desc_t)ring_desc;
  1889. }
  1890. /**
  1891. * hal_srng_set_event() - Set hal_srng event
  1892. * @hal_ring_hdl: Source ring pointer
  1893. * @event: SRNG ring event
  1894. *
  1895. * Return: None
  1896. */
  1897. static inline void hal_srng_set_event(hal_ring_handle_t hal_ring_hdl, int event)
  1898. {
  1899. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1900. qdf_atomic_set_bit(event, &srng->srng_event);
  1901. }
  1902. /**
  1903. * hal_srng_clear_event() - Clear hal_srng event
  1904. * @hal_ring_hdl: Source ring pointer
  1905. * @event: SRNG ring event
  1906. *
  1907. * Return: None
  1908. */
  1909. static inline
  1910. void hal_srng_clear_event(hal_ring_handle_t hal_ring_hdl, int event)
  1911. {
  1912. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1913. qdf_atomic_clear_bit(event, &srng->srng_event);
  1914. }
  1915. /**
  1916. * hal_srng_get_clear_event() - Clear srng event and return old value
  1917. * @hal_ring_hdl: Source ring pointer
  1918. * @event: SRNG ring event
  1919. *
  1920. * Return: Return old event value
  1921. */
  1922. static inline
  1923. int hal_srng_get_clear_event(hal_ring_handle_t hal_ring_hdl, int event)
  1924. {
  1925. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1926. return qdf_atomic_test_and_clear_bit(event, &srng->srng_event);
  1927. }
  1928. /**
  1929. * hal_srng_set_flush_last_ts() - Record last flush time stamp
  1930. * @hal_ring_hdl: Source ring pointer
  1931. *
  1932. * Return: None
  1933. */
  1934. static inline void hal_srng_set_flush_last_ts(hal_ring_handle_t hal_ring_hdl)
  1935. {
  1936. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1937. srng->last_flush_ts = qdf_get_log_timestamp();
  1938. }
  1939. /**
  1940. * hal_srng_inc_flush_cnt() - Increment flush counter
  1941. * @hal_ring_hdl: Source ring pointer
  1942. *
  1943. * Return: None
  1944. */
  1945. static inline void hal_srng_inc_flush_cnt(hal_ring_handle_t hal_ring_hdl)
  1946. {
  1947. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1948. srng->flush_count++;
  1949. }
  1950. /**
  1951. * hal_rx_sw_mon_desc_info_get () - Get SW monitor desc info
  1952. *
  1953. * @hal: Core HAL soc handle
  1954. * @ring_desc: Mon dest ring descriptor
  1955. * @desc_info: Desc info to be populated
  1956. *
  1957. * Return void
  1958. */
  1959. static inline void
  1960. hal_rx_sw_mon_desc_info_get(struct hal_soc *hal,
  1961. hal_ring_desc_t ring_desc,
  1962. hal_rx_mon_desc_info_t desc_info)
  1963. {
  1964. return hal->ops->hal_rx_sw_mon_desc_info_get(ring_desc, desc_info);
  1965. }
  1966. /**
  1967. * hal_reo_set_err_dst_remap() - Set REO error destination ring remap
  1968. * register value.
  1969. *
  1970. * @hal_soc_hdl: Opaque HAL soc handle
  1971. *
  1972. * Return: None
  1973. */
  1974. static inline void hal_reo_set_err_dst_remap(hal_soc_handle_t hal_soc_hdl)
  1975. {
  1976. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1977. if (hal_soc->ops->hal_reo_set_err_dst_remap)
  1978. hal_soc->ops->hal_reo_set_err_dst_remap(hal_soc);
  1979. }
  1980. #endif /* _HAL_APIH_ */