pll_drv.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "%s: " fmt, __func__
  6. #include <linux/module.h>
  7. #include <linux/of_device.h>
  8. #include <linux/kernel.h>
  9. #include <linux/err.h>
  10. #include <linux/delay.h>
  11. #include <linux/iopoll.h>
  12. #include "pll_drv.h"
  13. #include "dsi_pll.h"
  14. #include "dp_pll.h"
  15. #include "hdmi_pll.h"
  16. int mdss_pll_resource_enable(struct mdss_pll_resources *pll_res, bool enable)
  17. {
  18. int rc = 0;
  19. int changed = 0;
  20. if (!pll_res) {
  21. pr_err("Invalid input parameters\n");
  22. return -EINVAL;
  23. }
  24. /*
  25. * Don't turn off resources during handoff or add more than
  26. * 1 refcount.
  27. */
  28. if (pll_res->handoff_resources &&
  29. (!enable || (enable & pll_res->resource_enable))) {
  30. pr_debug("Do not turn on/off pll resources during handoff case\n");
  31. return rc;
  32. }
  33. if (enable) {
  34. if (pll_res->resource_ref_cnt == 0)
  35. changed++;
  36. pll_res->resource_ref_cnt++;
  37. } else {
  38. if (pll_res->resource_ref_cnt) {
  39. pll_res->resource_ref_cnt--;
  40. if (pll_res->resource_ref_cnt == 0)
  41. changed++;
  42. } else {
  43. pr_err("PLL Resources already OFF\n");
  44. }
  45. }
  46. if (changed) {
  47. rc = mdss_pll_util_resource_enable(pll_res, enable);
  48. if (rc)
  49. pr_err("Resource update failed rc=%d\n", rc);
  50. else
  51. pll_res->resource_enable = enable;
  52. }
  53. return rc;
  54. }
  55. static int mdss_pll_resource_init(struct platform_device *pdev,
  56. struct mdss_pll_resources *pll_res)
  57. {
  58. int rc = 0;
  59. struct dss_module_power *mp = &pll_res->mp;
  60. rc = msm_dss_config_vreg(&pdev->dev,
  61. mp->vreg_config, mp->num_vreg, 1);
  62. if (rc) {
  63. pr_err("Vreg config failed rc=%d\n", rc);
  64. goto vreg_err;
  65. }
  66. rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
  67. if (rc) {
  68. pr_err("Clock get failed rc=%d\n", rc);
  69. goto clk_err;
  70. }
  71. return rc;
  72. clk_err:
  73. msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
  74. vreg_err:
  75. return rc;
  76. }
  77. static void mdss_pll_resource_deinit(struct platform_device *pdev,
  78. struct mdss_pll_resources *pll_res)
  79. {
  80. struct dss_module_power *mp = &pll_res->mp;
  81. msm_dss_put_clk(mp->clk_config, mp->num_clk);
  82. msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
  83. }
  84. static void mdss_pll_resource_release(struct platform_device *pdev,
  85. struct mdss_pll_resources *pll_res)
  86. {
  87. struct dss_module_power *mp = &pll_res->mp;
  88. mp->num_vreg = 0;
  89. mp->num_clk = 0;
  90. }
  91. static int mdss_pll_resource_parse(struct platform_device *pdev,
  92. struct mdss_pll_resources *pll_res)
  93. {
  94. int rc = 0;
  95. const char *compatible_stream;
  96. rc = mdss_pll_util_resource_parse(pdev, pll_res);
  97. if (rc) {
  98. pr_err("Failed to parse the resources rc=%d\n", rc);
  99. goto end;
  100. }
  101. compatible_stream = of_get_property(pdev->dev.of_node,
  102. "compatible", NULL);
  103. if (!compatible_stream) {
  104. pr_err("Failed to parse the compatible stream\n");
  105. goto err;
  106. }
  107. if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_10nm"))
  108. pll_res->pll_interface_type = MDSS_DSI_PLL_10NM;
  109. if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_10nm"))
  110. pll_res->pll_interface_type = MDSS_DP_PLL_10NM;
  111. else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_7nm"))
  112. pll_res->pll_interface_type = MDSS_DP_PLL_7NM;
  113. else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_7nm"))
  114. pll_res->pll_interface_type = MDSS_DSI_PLL_7NM;
  115. else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_7nm_v2"))
  116. pll_res->pll_interface_type = MDSS_DSI_PLL_7NM_V2;
  117. else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_7nm_v4_1"))
  118. pll_res->pll_interface_type = MDSS_DSI_PLL_7NM_V4_1;
  119. else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_28lpm"))
  120. pll_res->pll_interface_type = MDSS_DSI_PLL_28LPM;
  121. else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_14nm"))
  122. pll_res->pll_interface_type = MDSS_DSI_PLL_14NM;
  123. else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_14nm"))
  124. pll_res->pll_interface_type = MDSS_DP_PLL_14NM;
  125. else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_28lpm"))
  126. pll_res->pll_interface_type = MDSS_HDMI_PLL_28LPM;
  127. else
  128. goto err;
  129. return rc;
  130. err:
  131. mdss_pll_resource_release(pdev, pll_res);
  132. end:
  133. return rc;
  134. }
  135. static int mdss_pll_clock_register(struct platform_device *pdev,
  136. struct mdss_pll_resources *pll_res)
  137. {
  138. int rc;
  139. switch (pll_res->pll_interface_type) {
  140. case MDSS_DSI_PLL_10NM:
  141. rc = dsi_pll_clock_register_10nm(pdev, pll_res);
  142. break;
  143. case MDSS_DP_PLL_10NM:
  144. rc = dp_pll_clock_register_10nm(pdev, pll_res);
  145. break;
  146. case MDSS_DSI_PLL_7NM:
  147. case MDSS_DSI_PLL_7NM_V2:
  148. case MDSS_DSI_PLL_7NM_V4_1:
  149. rc = dsi_pll_clock_register_7nm(pdev, pll_res);
  150. break;
  151. case MDSS_DP_PLL_7NM:
  152. rc = dp_pll_clock_register_7nm(pdev, pll_res);
  153. break;
  154. case MDSS_DSI_PLL_28LPM:
  155. rc = dsi_pll_clock_register_28lpm(pdev, pll_res);
  156. break;
  157. case MDSS_DSI_PLL_14NM:
  158. rc = dsi_pll_clock_register_14nm(pdev, pll_res);
  159. break;
  160. case MDSS_DP_PLL_14NM:
  161. rc = dp_pll_clock_register_14nm(pdev, pll_res);
  162. break;
  163. case MDSS_HDMI_PLL_28LPM:
  164. rc = hdmi_pll_clock_register_28lpm(pdev, pll_res);
  165. break;
  166. case MDSS_UNKNOWN_PLL:
  167. default:
  168. rc = -EINVAL;
  169. break;
  170. }
  171. if (rc)
  172. pr_err("Pll ndx=%d clock register failed rc=%d\n",
  173. pll_res->index, rc);
  174. return rc;
  175. }
  176. static inline int mdss_pll_get_ioresurces(struct platform_device *pdev,
  177. void __iomem **regmap, char *resource_name)
  178. {
  179. int rc = 0;
  180. struct resource *rsc = platform_get_resource_byname(pdev,
  181. IORESOURCE_MEM, resource_name);
  182. if (rsc) {
  183. if (!regmap)
  184. return -ENOMEM;
  185. *regmap = devm_ioremap(&pdev->dev,
  186. rsc->start, resource_size(rsc));
  187. if (!*regmap)
  188. return -ENOMEM;
  189. }
  190. return rc;
  191. }
  192. static int mdss_pll_probe(struct platform_device *pdev)
  193. {
  194. int rc = 0;
  195. const char *label;
  196. struct mdss_pll_resources *pll_res;
  197. if (!pdev->dev.of_node) {
  198. pr_err("MDSS pll driver only supports device tree probe\n");
  199. return -ENOTSUPP;
  200. }
  201. label = of_get_property(pdev->dev.of_node, "label", NULL);
  202. if (!label)
  203. pr_info("MDSS pll label not specified\n");
  204. else
  205. pr_info("MDSS pll label = %s\n", label);
  206. pll_res = devm_kzalloc(&pdev->dev, sizeof(struct mdss_pll_resources),
  207. GFP_KERNEL);
  208. if (!pll_res)
  209. return -ENOMEM;
  210. platform_set_drvdata(pdev, pll_res);
  211. rc = of_property_read_u32(pdev->dev.of_node, "cell-index",
  212. &pll_res->index);
  213. if (rc) {
  214. pr_err("Unable to get the cell-index rc=%d\n", rc);
  215. pll_res->index = 0;
  216. }
  217. pll_res->ssc_en = of_property_read_bool(pdev->dev.of_node,
  218. "qcom,dsi-pll-ssc-en");
  219. if (pll_res->ssc_en) {
  220. pr_info("%s: label=%s PLL SSC enabled\n", __func__, label);
  221. rc = of_property_read_u32(pdev->dev.of_node,
  222. "qcom,ssc-frequency-hz", &pll_res->ssc_freq);
  223. rc = of_property_read_u32(pdev->dev.of_node,
  224. "qcom,ssc-ppm", &pll_res->ssc_ppm);
  225. pll_res->ssc_center = false;
  226. label = of_get_property(pdev->dev.of_node,
  227. "qcom,dsi-pll-ssc-mode", NULL);
  228. if (label && !strcmp(label, "center-spread"))
  229. pll_res->ssc_center = true;
  230. }
  231. if (mdss_pll_get_ioresurces(pdev, &pll_res->pll_base, "pll_base")) {
  232. pr_err("Unable to remap pll base resources\n");
  233. return -ENOMEM;
  234. }
  235. pr_debug("%s: ndx=%d base=%p\n", __func__,
  236. pll_res->index, pll_res->pll_base);
  237. rc = mdss_pll_resource_parse(pdev, pll_res);
  238. if (rc) {
  239. pr_err("Pll resource parsing from dt failed rc=%d\n", rc);
  240. return rc;
  241. }
  242. if (mdss_pll_get_ioresurces(pdev, &pll_res->phy_base, "phy_base")) {
  243. pr_err("Unable to remap pll phy base resources\n");
  244. return -ENOMEM;
  245. }
  246. if (mdss_pll_get_ioresurces(pdev, &pll_res->dyn_pll_base,
  247. "dynamic_pll_base")) {
  248. pr_err("Unable to remap dynamic pll base resources\n");
  249. return -ENOMEM;
  250. }
  251. if (mdss_pll_get_ioresurces(pdev, &pll_res->ln_tx0_base,
  252. "ln_tx0_base")) {
  253. pr_err("Unable to remap Lane TX0 base resources\n");
  254. return -ENOMEM;
  255. }
  256. if (mdss_pll_get_ioresurces(pdev, &pll_res->ln_tx1_base,
  257. "ln_tx1_base")) {
  258. pr_err("Unable to remap Lane TX1 base resources\n");
  259. return -ENOMEM;
  260. }
  261. if (mdss_pll_get_ioresurces(pdev, &pll_res->gdsc_base, "gdsc_base")) {
  262. pr_err("Unable to remap gdsc base resources\n");
  263. return -ENOMEM;
  264. }
  265. rc = mdss_pll_resource_init(pdev, pll_res);
  266. if (rc) {
  267. pr_err("Pll ndx=%d resource init failed rc=%d\n",
  268. pll_res->index, rc);
  269. return rc;
  270. }
  271. rc = mdss_pll_clock_register(pdev, pll_res);
  272. if (rc) {
  273. pr_err("Pll ndx=%d clock register failed rc=%d\n",
  274. pll_res->index, rc);
  275. goto clock_register_error;
  276. }
  277. return rc;
  278. clock_register_error:
  279. mdss_pll_resource_deinit(pdev, pll_res);
  280. return rc;
  281. }
  282. static int mdss_pll_remove(struct platform_device *pdev)
  283. {
  284. struct mdss_pll_resources *pll_res;
  285. pll_res = platform_get_drvdata(pdev);
  286. if (!pll_res) {
  287. pr_err("Invalid PLL resource data\n");
  288. return 0;
  289. }
  290. mdss_pll_resource_deinit(pdev, pll_res);
  291. mdss_pll_resource_release(pdev, pll_res);
  292. return 0;
  293. }
  294. static const struct of_device_id mdss_pll_dt_match[] = {
  295. {.compatible = "qcom,mdss_dsi_pll_10nm"},
  296. {.compatible = "qcom,mdss_dp_pll_10nm"},
  297. {.compatible = "qcom,mdss_dsi_pll_7nm"},
  298. {.compatible = "qcom,mdss_dsi_pll_7nm_v2"},
  299. {.compatible = "qcom,mdss_dsi_pll_7nm_v4_1"},
  300. {.compatible = "qcom,mdss_dp_pll_7nm"},
  301. {.compatible = "qcom,mdss_dsi_pll_28lpm"},
  302. {.compatible = "qcom,mdss_dsi_pll_14nm"},
  303. {.compatible = "qcom,mdss_dp_pll_14nm"},
  304. {},
  305. };
  306. MODULE_DEVICE_TABLE(of, mdss_clock_dt_match);
  307. static struct platform_driver mdss_pll_driver = {
  308. .probe = mdss_pll_probe,
  309. .remove = mdss_pll_remove,
  310. .driver = {
  311. .name = "mdss_pll",
  312. .of_match_table = mdss_pll_dt_match,
  313. },
  314. };
  315. static int __init mdss_pll_driver_init(void)
  316. {
  317. int rc;
  318. rc = platform_driver_register(&mdss_pll_driver);
  319. if (rc)
  320. pr_err("mdss_register_pll_driver() failed!\n");
  321. return rc;
  322. }
  323. fs_initcall(mdss_pll_driver_init);
  324. static void __exit mdss_pll_driver_deinit(void)
  325. {
  326. platform_driver_unregister(&mdss_pll_driver);
  327. }
  328. module_exit(mdss_pll_driver_deinit);
  329. MODULE_LICENSE("GPL v2");
  330. MODULE_DESCRIPTION("mdss pll driver");